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drm/radeon/kms: deal with connectors sourced to the same encoder
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06
AD		 52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id);
771fe6b9
JG		 54
55/* from radeon_legacy_encoder.c */
56extern void
57radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
58 uint32_t supported_device);
59
60/* old legacy ATI BIOS routines */
61
62/* COMBIOS table offsets */
63enum radeon_combios_table_offset {
64 /* absolute offset tables */
65 COMBIOS_ASIC_INIT_1_TABLE,
66 COMBIOS_BIOS_SUPPORT_TABLE,
67 COMBIOS_DAC_PROGRAMMING_TABLE,
68 COMBIOS_MAX_COLOR_DEPTH_TABLE,
69 COMBIOS_CRTC_INFO_TABLE,
70 COMBIOS_PLL_INFO_TABLE,
71 COMBIOS_TV_INFO_TABLE,
72 COMBIOS_DFP_INFO_TABLE,
73 COMBIOS_HW_CONFIG_INFO_TABLE,
74 COMBIOS_MULTIMEDIA_INFO_TABLE,
75 COMBIOS_TV_STD_PATCH_TABLE,
76 COMBIOS_LCD_INFO_TABLE,
77 COMBIOS_MOBILE_INFO_TABLE,
78 COMBIOS_PLL_INIT_TABLE,
79 COMBIOS_MEM_CONFIG_TABLE,
80 COMBIOS_SAVE_MASK_TABLE,
81 COMBIOS_HARDCODED_EDID_TABLE,
82 COMBIOS_ASIC_INIT_2_TABLE,
83 COMBIOS_CONNECTOR_INFO_TABLE,
84 COMBIOS_DYN_CLK_1_TABLE,
85 COMBIOS_RESERVED_MEM_TABLE,
86 COMBIOS_EXT_TMDS_INFO_TABLE,
87 COMBIOS_MEM_CLK_INFO_TABLE,
88 COMBIOS_EXT_DAC_INFO_TABLE,
89 COMBIOS_MISC_INFO_TABLE,
90 COMBIOS_CRT_INFO_TABLE,
91 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
92 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
93 COMBIOS_FAN_SPEED_INFO_TABLE,
94 COMBIOS_OVERDRIVE_INFO_TABLE,
95 COMBIOS_OEM_INFO_TABLE,
96 COMBIOS_DYN_CLK_2_TABLE,
97 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
98 COMBIOS_I2C_INFO_TABLE,
99 /* relative offset tables */
100 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
101 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
102 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
103 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
104 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
105 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
106 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
110 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
111};
112
113enum radeon_combios_ddc {
114 DDC_NONE_DETECTED,
115 DDC_MONID,
116 DDC_DVI,
117 DDC_VGA,
118 DDC_CRT2,
119 DDC_LCD,
120 DDC_GPIO,
121};
122
123enum radeon_combios_connector {
124 CONNECTOR_NONE_LEGACY,
125 CONNECTOR_PROPRIETARY_LEGACY,
126 CONNECTOR_CRT_LEGACY,
127 CONNECTOR_DVI_I_LEGACY,
128 CONNECTOR_DVI_D_LEGACY,
129 CONNECTOR_CTV_LEGACY,
130 CONNECTOR_STV_LEGACY,
131 CONNECTOR_UNSUPPORTED_LEGACY
132};
133
134const int legacy_connector_convert[] = {
135 DRM_MODE_CONNECTOR_Unknown,
136 DRM_MODE_CONNECTOR_DVID,
137 DRM_MODE_CONNECTOR_VGA,
138 DRM_MODE_CONNECTOR_DVII,
139 DRM_MODE_CONNECTOR_DVID,
140 DRM_MODE_CONNECTOR_Composite,
141 DRM_MODE_CONNECTOR_SVIDEO,
142 DRM_MODE_CONNECTOR_Unknown,
143};
144
145static uint16_t combios_get_table_offset(struct drm_device *dev,
146 enum radeon_combios_table_offset table)
147{
148 struct radeon_device *rdev = dev->dev_private;
149 int rev;
150 uint16_t offset = 0, check_offset;
151
152 switch (table) {
153 /* absolute offset tables */
154 case COMBIOS_ASIC_INIT_1_TABLE:
155 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
156 if (check_offset)
157 offset = check_offset;
158 break;
159 case COMBIOS_BIOS_SUPPORT_TABLE:
160 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
161 if (check_offset)
162 offset = check_offset;
163 break;
164 case COMBIOS_DAC_PROGRAMMING_TABLE:
165 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
166 if (check_offset)
167 offset = check_offset;
168 break;
169 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
170 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
171 if (check_offset)
172 offset = check_offset;
173 break;
174 case COMBIOS_CRTC_INFO_TABLE:
175 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
176 if (check_offset)
177 offset = check_offset;
178 break;
179 case COMBIOS_PLL_INFO_TABLE:
180 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
181 if (check_offset)
182 offset = check_offset;
183 break;
184 case COMBIOS_TV_INFO_TABLE:
185 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
186 if (check_offset)
187 offset = check_offset;
188 break;
189 case COMBIOS_DFP_INFO_TABLE:
190 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
191 if (check_offset)
192 offset = check_offset;
193 break;
194 case COMBIOS_HW_CONFIG_INFO_TABLE:
195 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
196 if (check_offset)
197 offset = check_offset;
198 break;
199 case COMBIOS_MULTIMEDIA_INFO_TABLE:
200 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
201 if (check_offset)
202 offset = check_offset;
203 break;
204 case COMBIOS_TV_STD_PATCH_TABLE:
205 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
206 if (check_offset)
207 offset = check_offset;
208 break;
209 case COMBIOS_LCD_INFO_TABLE:
210 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
211 if (check_offset)
212 offset = check_offset;
213 break;
214 case COMBIOS_MOBILE_INFO_TABLE:
215 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
216 if (check_offset)
217 offset = check_offset;
218 break;
219 case COMBIOS_PLL_INIT_TABLE:
220 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
221 if (check_offset)
222 offset = check_offset;
223 break;
224 case COMBIOS_MEM_CONFIG_TABLE:
225 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
226 if (check_offset)
227 offset = check_offset;
228 break;
229 case COMBIOS_SAVE_MASK_TABLE:
230 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
231 if (check_offset)
232 offset = check_offset;
233 break;
234 case COMBIOS_HARDCODED_EDID_TABLE:
235 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
236 if (check_offset)
237 offset = check_offset;
238 break;
239 case COMBIOS_ASIC_INIT_2_TABLE:
240 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
241 if (check_offset)
242 offset = check_offset;
243 break;
244 case COMBIOS_CONNECTOR_INFO_TABLE:
245 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
246 if (check_offset)
247 offset = check_offset;
248 break;
249 case COMBIOS_DYN_CLK_1_TABLE:
250 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
251 if (check_offset)
252 offset = check_offset;
253 break;
254 case COMBIOS_RESERVED_MEM_TABLE:
255 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
256 if (check_offset)
257 offset = check_offset;
258 break;
259 case COMBIOS_EXT_TMDS_INFO_TABLE:
260 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
261 if (check_offset)
262 offset = check_offset;
263 break;
264 case COMBIOS_MEM_CLK_INFO_TABLE:
265 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
266 if (check_offset)
267 offset = check_offset;
268 break;
269 case COMBIOS_EXT_DAC_INFO_TABLE:
270 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
271 if (check_offset)
272 offset = check_offset;
273 break;
274 case COMBIOS_MISC_INFO_TABLE:
275 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
276 if (check_offset)
277 offset = check_offset;
278 break;
279 case COMBIOS_CRT_INFO_TABLE:
280 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
281 if (check_offset)
282 offset = check_offset;
283 break;
284 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
285 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
286 if (check_offset)
287 offset = check_offset;
288 break;
289 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
290 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
291 if (check_offset)
292 offset = check_offset;
293 break;
294 case COMBIOS_FAN_SPEED_INFO_TABLE:
295 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
296 if (check_offset)
297 offset = check_offset;
298 break;
299 case COMBIOS_OVERDRIVE_INFO_TABLE:
300 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
301 if (check_offset)
302 offset = check_offset;
303 break;
304 case COMBIOS_OEM_INFO_TABLE:
305 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
306 if (check_offset)
307 offset = check_offset;
308 break;
309 case COMBIOS_DYN_CLK_2_TABLE:
310 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
311 if (check_offset)
312 offset = check_offset;
313 break;
314 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
315 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
316 if (check_offset)
317 offset = check_offset;
318 break;
319 case COMBIOS_I2C_INFO_TABLE:
320 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
321 if (check_offset)
322 offset = check_offset;
323 break;
324 /* relative offset tables */
325 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
326 check_offset =
327 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
328 if (check_offset) {
329 rev = RBIOS8(check_offset);
330 if (rev > 0) {
331 check_offset = RBIOS16(check_offset + 0x3);
332 if (check_offset)
333 offset = check_offset;
334 }
335 }
336 break;
337 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
338 check_offset =
339 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
340 if (check_offset) {
341 rev = RBIOS8(check_offset);
342 if (rev > 0) {
343 check_offset = RBIOS16(check_offset + 0x5);
344 if (check_offset)
345 offset = check_offset;
346 }
347 }
348 break;
349 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
350 check_offset =
351 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
352 if (check_offset) {
353 rev = RBIOS8(check_offset);
354 if (rev > 0) {
355 check_offset = RBIOS16(check_offset + 0x7);
356 if (check_offset)
357 offset = check_offset;
358 }
359 }
360 break;
361 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
362 check_offset =
363 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
364 if (check_offset) {
365 rev = RBIOS8(check_offset);
366 if (rev == 2) {
367 check_offset = RBIOS16(check_offset + 0x9);
368 if (check_offset)
369 offset = check_offset;
370 }
371 }
372 break;
373 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
374 check_offset =
375 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
376 if (check_offset) {
377 while (RBIOS8(check_offset++));
378 check_offset += 2;
379 if (check_offset)
380 offset = check_offset;
381 }
382 break;
383 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
384 check_offset =
385 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
386 if (check_offset) {
387 check_offset = RBIOS16(check_offset + 0x11);
388 if (check_offset)
389 offset = check_offset;
390 }
391 break;
392 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
393 check_offset =
394 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
395 if (check_offset) {
396 check_offset = RBIOS16(check_offset + 0x13);
397 if (check_offset)
398 offset = check_offset;
399 }
400 break;
401 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
402 check_offset =
403 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
404 if (check_offset) {
405 check_offset = RBIOS16(check_offset + 0x15);
406 if (check_offset)
407 offset = check_offset;
408 }
409 break;
410 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
411 check_offset =
412 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
413 if (check_offset) {
414 check_offset = RBIOS16(check_offset + 0x17);
415 if (check_offset)
416 offset = check_offset;
417 }
418 break;
419 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
420 check_offset =
421 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
422 if (check_offset) {
423 check_offset = RBIOS16(check_offset + 0x2);
424 if (check_offset)
425 offset = check_offset;
426 }
427 break;
428 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
429 check_offset =
430 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
431 if (check_offset) {
432 check_offset = RBIOS16(check_offset + 0x4);
433 if (check_offset)
434 offset = check_offset;
435 }
436 break;
437 default:
438 break;
439 }
440
441 return offset;
442
443}
444
445struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
446{
447 struct radeon_i2c_bus_rec i2c;
448
449 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
450 i2c.mask_data_mask = RADEON_GPIO_EN_0;
451 i2c.a_clk_mask = RADEON_GPIO_A_1;
452 i2c.a_data_mask = RADEON_GPIO_A_0;
9b9fe724
AD		 453 i2c.en_clk_mask = RADEON_GPIO_EN_1;
454 i2c.en_data_mask = RADEON_GPIO_EN_0;
455 i2c.y_clk_mask = RADEON_GPIO_Y_1;
456 i2c.y_data_mask = RADEON_GPIO_Y_0;
771fe6b9
JG		 457 if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
458 (ddc_line == RADEON_MDGPIO_EN_REG)) {
459 i2c.mask_clk_reg = ddc_line;
460 i2c.mask_data_reg = ddc_line;
461 i2c.a_clk_reg = ddc_line;
462 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 463 i2c.en_clk_reg = ddc_line;
464 i2c.en_data_reg = ddc_line;
465 i2c.y_clk_reg = ddc_line + 4;
466 i2c.y_data_reg = ddc_line + 4;
771fe6b9
JG		 467 } else {
468 i2c.mask_clk_reg = ddc_line;
469 i2c.mask_data_reg = ddc_line;
470 i2c.a_clk_reg = ddc_line;
471 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 472 i2c.en_clk_reg = ddc_line;
473 i2c.en_data_reg = ddc_line;
474 i2c.y_clk_reg = ddc_line;
475 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 476 }
477
478 if (ddc_line)
479 i2c.valid = true;
480 else
481 i2c.valid = false;
482
483 return i2c;
484}
485
486bool radeon_combios_get_clock_info(struct drm_device *dev)
487{
488 struct radeon_device *rdev = dev->dev_private;
489 uint16_t pll_info;
490 struct radeon_pll *p1pll = &rdev->clock.p1pll;
491 struct radeon_pll *p2pll = &rdev->clock.p2pll;
492 struct radeon_pll *spll = &rdev->clock.spll;
493 struct radeon_pll *mpll = &rdev->clock.mpll;
494 int8_t rev;
495 uint16_t sclk, mclk;
496
497 if (rdev->bios == NULL)
498 return NULL;
499
500 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
501 if (pll_info) {
502 rev = RBIOS8(pll_info);
503
504 /* pixel clocks */
505 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
506 p1pll->reference_div = RBIOS16(pll_info + 0x10);
507 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
508 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
509
510 if (rev > 9) {
511 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
512 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
513 } else {
514 p1pll->pll_in_min = 40;
515 p1pll->pll_in_max = 500;
516 }
517 *p2pll = *p1pll;
518
519 /* system clock */
520 spll->reference_freq = RBIOS16(pll_info + 0x1a);
521 spll->reference_div = RBIOS16(pll_info + 0x1c);
522 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
523 spll->pll_out_max = RBIOS32(pll_info + 0x22);
524
525 if (rev > 10) {
526 spll->pll_in_min = RBIOS32(pll_info + 0x48);
527 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
528 } else {
529 /* ??? */
530 spll->pll_in_min = 40;
531 spll->pll_in_max = 500;
532 }
533
534 /* memory clock */
535 mpll->reference_freq = RBIOS16(pll_info + 0x26);
536 mpll->reference_div = RBIOS16(pll_info + 0x28);
537 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
538 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
539
540 if (rev > 10) {
541 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
542 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
543 } else {
544 /* ??? */
545 mpll->pll_in_min = 40;
546 mpll->pll_in_max = 500;
547 }
548
549 /* default sclk/mclk */
550 sclk = RBIOS16(pll_info + 0xa);
551 mclk = RBIOS16(pll_info + 0x8);
552 if (sclk == 0)
553 sclk = 200 * 100;
554 if (mclk == 0)
555 mclk = 200 * 100;
556
557 rdev->clock.default_sclk = sclk;
558 rdev->clock.default_mclk = mclk;
559
560 return true;
561 }
562 return false;
563}
564
565struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
566 radeon_encoder
567 *encoder)
568{
569 struct drm_device *dev = encoder->base.dev;
570 struct radeon_device *rdev = dev->dev_private;
571 uint16_t dac_info;
572 uint8_t rev, bg, dac;
573 struct radeon_encoder_primary_dac *p_dac = NULL;
574
575 if (rdev->bios == NULL)
576 return NULL;
577
578 /* check CRT table */
579 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
580 if (dac_info) {
581 p_dac =
582 kzalloc(sizeof(struct radeon_encoder_primary_dac),
583 GFP_KERNEL);
584
585 if (!p_dac)
586 return NULL;
587
588 rev = RBIOS8(dac_info) & 0x3;
589 if (rev < 2) {
590 bg = RBIOS8(dac_info + 0x2) & 0xf;
591 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
592 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
593 } else {
594 bg = RBIOS8(dac_info + 0x2) & 0xf;
595 dac = RBIOS8(dac_info + 0x3) & 0xf;
596 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
597 }
598
599 }
600
601 return p_dac;
602}
603
604static enum radeon_tv_std
605radeon_combios_get_tv_info(struct radeon_encoder *encoder)
606{
607 struct drm_device *dev = encoder->base.dev;
608 struct radeon_device *rdev = dev->dev_private;
609 uint16_t tv_info;
610 enum radeon_tv_std tv_std = TV_STD_NTSC;
611
612 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
613 if (tv_info) {
614 if (RBIOS8(tv_info + 6) == 'T') {
615 switch (RBIOS8(tv_info + 7) & 0xf) {
616 case 1:
617 tv_std = TV_STD_NTSC;
618 DRM_INFO("Default TV standard: NTSC\n");
619 break;
620 case 2:
621 tv_std = TV_STD_PAL;
622 DRM_INFO("Default TV standard: PAL\n");
623 break;
624 case 3:
625 tv_std = TV_STD_PAL_M;
626 DRM_INFO("Default TV standard: PAL-M\n");
627 break;
628 case 4:
629 tv_std = TV_STD_PAL_60;
630 DRM_INFO("Default TV standard: PAL-60\n");
631 break;
632 case 5:
633 tv_std = TV_STD_NTSC_J;
634 DRM_INFO("Default TV standard: NTSC-J\n");
635 break;
636 case 6:
637 tv_std = TV_STD_SCART_PAL;
638 DRM_INFO("Default TV standard: SCART-PAL\n");
639 break;
640 default:
641 tv_std = TV_STD_NTSC;
642 DRM_INFO
643 ("Unknown TV standard; defaulting to NTSC\n");
644 break;
645 }
646
647 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
648 case 0:
649 DRM_INFO("29.498928713 MHz TV ref clk\n");
650 break;
651 case 1:
652 DRM_INFO("28.636360000 MHz TV ref clk\n");
653 break;
654 case 2:
655 DRM_INFO("14.318180000 MHz TV ref clk\n");
656 break;
657 case 3:
658 DRM_INFO("27.000000000 MHz TV ref clk\n");
659 break;
660 default:
661 break;
662 }
663 }
664 }
665 return tv_std;
666}
667
668static const uint32_t default_tvdac_adj[CHIP_LAST] = {
669 0x00000000, /* r100 */
670 0x00280000, /* rv100 */
671 0x00000000, /* rs100 */
672 0x00880000, /* rv200 */
673 0x00000000, /* rs200 */
674 0x00000000, /* r200 */
675 0x00770000, /* rv250 */
676 0x00290000, /* rs300 */
677 0x00560000, /* rv280 */
678 0x00780000, /* r300 */
679 0x00770000, /* r350 */
680 0x00780000, /* rv350 */
681 0x00780000, /* rv380 */
682 0x01080000, /* r420 */
683 0x01080000, /* r423 */
684 0x01080000, /* rv410 */
685 0x00780000, /* rs400 */
686 0x00780000, /* rs480 */
687};
688
6a719e05
DA		 689static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
690 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 691{
771fe6b9
JG		 692 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
693 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
694 tv_dac->ps2_tvdac_adj = 0x00880000;
695 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
696 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 697 return;
771fe6b9
JG		 698}
699
700struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
701 radeon_encoder
702 *encoder)
703{
704 struct drm_device *dev = encoder->base.dev;
705 struct radeon_device *rdev = dev->dev_private;
706 uint16_t dac_info;
707 uint8_t rev, bg, dac;
708 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 709 int found = 0;
710
711 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
712 if (!tv_dac)
713 return NULL;
771fe6b9
JG		 714
715 if (rdev->bios == NULL)
6a719e05 716 goto out;
771fe6b9
JG		 717
718 /* first check TV table */
719 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
720 if (dac_info) {
771fe6b9
JG		 721 rev = RBIOS8(dac_info + 0x3);
722 if (rev > 4) {
723 bg = RBIOS8(dac_info + 0xc) & 0xf;
724 dac = RBIOS8(dac_info + 0xd) & 0xf;
725 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
726
727 bg = RBIOS8(dac_info + 0xe) & 0xf;
728 dac = RBIOS8(dac_info + 0xf) & 0xf;
729 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
730
731 bg = RBIOS8(dac_info + 0x10) & 0xf;
732 dac = RBIOS8(dac_info + 0x11) & 0xf;
733 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 734 found = 1;
771fe6b9
JG		 735 } else if (rev > 1) {
736 bg = RBIOS8(dac_info + 0xc) & 0xf;
737 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
738 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
739
740 bg = RBIOS8(dac_info + 0xd) & 0xf;
741 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
742 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
743
744 bg = RBIOS8(dac_info + 0xe) & 0xf;
745 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
746 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 747 found = 1;
771fe6b9 748 }
771fe6b9 749 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
6a719e05
DA		 750 }
751 if (!found) {
771fe6b9
JG		 752 /* then check CRT table */
753 dac_info =
754 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
755 if (dac_info) {
771fe6b9
JG		 756 rev = RBIOS8(dac_info) & 0x3;
757 if (rev < 2) {
758 bg = RBIOS8(dac_info + 0x3) & 0xf;
759 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
760 tv_dac->ps2_tvdac_adj =
761 (bg << 16) | (dac << 20);
762 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
763 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 764 found = 1;
771fe6b9
JG		 765 } else {
766 bg = RBIOS8(dac_info + 0x4) & 0xf;
767 dac = RBIOS8(dac_info + 0x5) & 0xf;
768 tv_dac->ps2_tvdac_adj =
769 (bg << 16) | (dac << 20);
770 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
771 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 772 found = 1;
771fe6b9 773 }
6fe7ac3f
AD		 774 } else {
775 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 776 }
777 }
778
6a719e05
DA		 779out:
780 if (!found) /* fallback to defaults */
781 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
782
771fe6b9
JG		 783 return tv_dac;
784}
785
786static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
787 radeon_device
788 *rdev)
789{
790 struct radeon_encoder_lvds *lvds = NULL;
791 uint32_t fp_vert_stretch, fp_horz_stretch;
792 uint32_t ppll_div_sel, ppll_val;
8b5c7444 793 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 794
795 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
796
797 if (!lvds)
798 return NULL;
799
800 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
801 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
802
8b5c7444
MD		 803 /* These should be fail-safe defaults, fingers crossed */
804 lvds->panel_pwr_delay = 200;
805 lvds->panel_vcc_delay = 2000;
806
807 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
808 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
809 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
810
771fe6b9 811 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 812 lvds->native_mode.vdisplay =
771fe6b9
JG		 813 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
814 RADEON_VERT_PANEL_SHIFT) + 1;
815 else
de2103e4 816 lvds->native_mode.vdisplay =
771fe6b9
JG		 817 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
818
819 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 820 lvds->native_mode.hdisplay =
771fe6b9
JG		 821 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
822 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
823 else
de2103e4 824 lvds->native_mode.hdisplay =
771fe6b9
JG		 825 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
826
de2103e4
AD		 827 if ((lvds->native_mode.hdisplay < 640) ||
828 (lvds->native_mode.vdisplay < 480)) {
829 lvds->native_mode.hdisplay = 640;
830 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 831 }
832
833 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
834 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
835 if ((ppll_val & 0x000707ff) == 0x1bb)
836 lvds->use_bios_dividers = false;
837 else {
838 lvds->panel_ref_divider =
839 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
840 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
841 lvds->panel_fb_divider = ppll_val & 0x7ff;
842
843 if ((lvds->panel_ref_divider != 0) &&
844 (lvds->panel_fb_divider > 3))
845 lvds->use_bios_dividers = true;
846 }
847 lvds->panel_vcc_delay = 200;
848
849 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 850 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
851 lvds->native_mode.vdisplay);
771fe6b9
JG		 852
853 return lvds;
854}
855
856struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
857 *encoder)
858{
859 struct drm_device *dev = encoder->base.dev;
860 struct radeon_device *rdev = dev->dev_private;
861 uint16_t lcd_info;
862 uint32_t panel_setup;
863 char stmp[30];
864 int tmp, i;
865 struct radeon_encoder_lvds *lvds = NULL;
866
8dfaa8a7
MD		 867 if (rdev->bios == NULL) {
868 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
869 goto out;
870 }
771fe6b9
JG		 871
872 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
873
874 if (lcd_info) {
875 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
876
877 if (!lvds)
878 return NULL;
879
880 for (i = 0; i < 24; i++)
881 stmp[i] = RBIOS8(lcd_info + i + 1);
882 stmp[24] = 0;
883
884 DRM_INFO("Panel ID String: %s\n", stmp);
885
de2103e4
AD		 886 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
887 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 888
de2103e4
AD		 889 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
890 lvds->native_mode.vdisplay);
771fe6b9
JG		 891
892 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
893 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
894 lvds->panel_vcc_delay = 2000;
895
896 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
897 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
898 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
899
900 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
901 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
902 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
903 if ((lvds->panel_ref_divider != 0) &&
904 (lvds->panel_fb_divider > 3))
905 lvds->use_bios_dividers = true;
906
907 panel_setup = RBIOS32(lcd_info + 0x39);
908 lvds->lvds_gen_cntl = 0xff00;
909 if (panel_setup & 0x1)
910 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
911
912 if ((panel_setup >> 4) & 0x1)
913 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
914
915 switch ((panel_setup >> 8) & 0x7) {
916 case 0:
917 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
918 break;
919 case 1:
920 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
921 break;
922 case 2:
923 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
924 break;
925 default:
926 break;
927 }
928
929 if ((panel_setup >> 16) & 0x1)
930 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
931
932 if ((panel_setup >> 17) & 0x1)
933 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
934
935 if ((panel_setup >> 18) & 0x1)
936 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
937
938 if ((panel_setup >> 23) & 0x1)
939 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
940
941 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
942
943 for (i = 0; i < 32; i++) {
944 tmp = RBIOS16(lcd_info + 64 + i * 2);
945 if (tmp == 0)
946 break;
947
de2103e4 948 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
771fe6b9 949 (RBIOS16(tmp + 2) ==
de2103e4
AD		 950 lvds->native_mode.vdisplay)) {
951 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
952 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
953 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
954 RBIOS16(tmp + 21)) * 8;
955
956 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
957 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
958 lvds->native_mode.vsync_end =
959 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
960 (RBIOS16(tmp + 28) & 0x7ff);
961
962 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 963 lvds->native_mode.flags = 0;
de2103e4
AD		 964 /* set crtc values */
965 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
966
771fe6b9
JG		 967 }
968 }
6fe7ac3f 969 } else {
771fe6b9 970 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 971 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 972 }
8dfaa8a7
MD		 973out:
974 if (lvds)
975 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 976 return lvds;
977}
978
979static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
980 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
981 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
982 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
983 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
984 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
985 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
986 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
987 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
988 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
989 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
990 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
991 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
992 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
993 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
994 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
995 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 996 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
997 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 998};
999
445282db
DA		 1000bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1001 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1002{
445282db
DA		 1003 struct drm_device *dev = encoder->base.dev;
1004 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1005 int i;
771fe6b9
JG		 1006
1007 for (i = 0; i < 4; i++) {
1008 tmds->tmds_pll[i].value =
445282db 1009 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1010 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1011 }
1012
445282db 1013 return true;
771fe6b9
JG		 1014}
1015
445282db
DA		 1016bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1017 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1018{
1019 struct drm_device *dev = encoder->base.dev;
1020 struct radeon_device *rdev = dev->dev_private;
1021 uint16_t tmds_info;
1022 int i, n;
1023 uint8_t ver;
771fe6b9
JG		 1024
1025 if (rdev->bios == NULL)
445282db 1026 return false;
771fe6b9
JG		 1027
1028 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1029
1030 if (tmds_info) {
771fe6b9
JG		 1031 ver = RBIOS8(tmds_info);
1032 DRM_INFO("DFP table revision: %d\n", ver);
1033 if (ver == 3) {
1034 n = RBIOS8(tmds_info + 5) + 1;
1035 if (n > 4)
1036 n = 4;
1037 for (i = 0; i < n; i++) {
1038 tmds->tmds_pll[i].value =
1039 RBIOS32(tmds_info + i * 10 + 0x08);
1040 tmds->tmds_pll[i].freq =
1041 RBIOS16(tmds_info + i * 10 + 0x10);
1042 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1043 tmds->tmds_pll[i].freq,
1044 tmds->tmds_pll[i].value);
1045 }
1046 } else if (ver == 4) {
1047 int stride = 0;
1048 n = RBIOS8(tmds_info + 5) + 1;
1049 if (n > 4)
1050 n = 4;
1051 for (i = 0; i < n; i++) {
1052 tmds->tmds_pll[i].value =
1053 RBIOS32(tmds_info + stride + 0x08);
1054 tmds->tmds_pll[i].freq =
1055 RBIOS16(tmds_info + stride + 0x10);
1056 if (i == 0)
1057 stride += 10;
1058 else
1059 stride += 6;
1060 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1061 tmds->tmds_pll[i].freq,
1062 tmds->tmds_pll[i].value);
1063 }
1064 }
fcec570b 1065 } else {
771fe6b9 1066 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1067 return false;
1068 }
445282db
DA		 1069 return true;
1070}
1071
fcec570b
AD		 1072bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1073 struct radeon_encoder_ext_tmds *tmds)
445282db 1074{
fcec570b
AD		 1075 struct drm_device *dev = encoder->base.dev;
1076 struct radeon_device *rdev = dev->dev_private;
1077 struct radeon_i2c_bus_rec i2c_bus;
445282db 1078
fcec570b
AD		 1079 /* default for macs */
1080 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1081 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1082
fcec570b
AD		 1083 /* XXX some macs have duallink chips */
1084 switch (rdev->mode_info.connector_table) {
1085 case CT_POWERBOOK_EXTERNAL:
1086 case CT_MINI_EXTERNAL:
1087 default:
1088 tmds->dvo_chip = DVO_SIL164;
1089 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1090 break;
1091 }
445282db 1092
fcec570b 1093 return true;
771fe6b9
JG		 1094}
1095
fcec570b
AD		 1096bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1097 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1098{
1099 struct drm_device *dev = encoder->base.dev;
1100 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1101 uint16_t offset;
1102 uint8_t ver, id, blocks, clk, data;
1103 int i;
1104 enum radeon_combios_ddc gpio;
1105 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9
JG		 1106
1107 if (rdev->bios == NULL)
fcec570b 1108 return false;
771fe6b9 1109
fcec570b
AD		 1110 tmds->i2c_bus = NULL;
1111 if (rdev->flags & RADEON_IS_IGP) {
1112 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1113 if (offset) {
1114 ver = RBIOS8(offset);
1115 DRM_INFO("GPIO Table revision: %d\n", ver);
1116 blocks = RBIOS8(offset + 2);
1117 for (i = 0; i < blocks; i++) {
1118 id = RBIOS8(offset + 3 + (i * 5) + 0);
1119 if (id == 136) {
1120 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1121 data = RBIOS8(offset + 3 + (i * 5) + 4);
1122 i2c_bus.valid = true;
1123 i2c_bus.mask_clk_mask = (1 << clk);
1124 i2c_bus.mask_data_mask = (1 << data);
1125 i2c_bus.a_clk_mask = (1 << clk);
1126 i2c_bus.a_data_mask = (1 << data);
1127 i2c_bus.en_clk_mask = (1 << clk);
1128 i2c_bus.en_data_mask = (1 << data);
1129 i2c_bus.y_clk_mask = (1 << clk);
1130 i2c_bus.y_data_mask = (1 << data);
1131 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1132 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1133 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1134 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1135 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1136 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1137 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1138 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1139 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1140 tmds->dvo_chip = DVO_SIL164;
1141 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1142 break;
1143 }
1144 }
1145 }
1146 } else {
1147 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1148 if (offset) {
1149 ver = RBIOS8(offset);
1150 DRM_INFO("External TMDS Table revision: %d\n", ver);
1151 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1152 tmds->slave_addr >>= 1; /* 7 bit addressing */
1153 gpio = RBIOS8(offset + 4 + 3);
1154 switch (gpio) {
1155 case DDC_MONID:
1156 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1157 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1158 break;
1159 case DDC_DVI:
1160 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1161 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1162 break;
1163 case DDC_VGA:
1164 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1165 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1166 break;
1167 case DDC_CRT2:
1168 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1169 if (rdev->family >= CHIP_R300)
1170 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1171 else
1172 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1173 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1174 break;
1175 case DDC_LCD: /* MM i2c */
1176 DRM_ERROR("MM i2c requires hw i2c engine\n");
1177 break;
1178 default:
1179 DRM_ERROR("Unsupported gpio %d\n", gpio);
1180 break;
1181 }
1182 }
771fe6b9 1183 }
fcec570b
AD		 1184
1185 if (!tmds->i2c_bus) {
1186 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1187 return false;
1188 }
1189
1190 return true;
771fe6b9
JG		 1191}
1192
1193bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1194{
1195 struct radeon_device *rdev = dev->dev_private;
1196 struct radeon_i2c_bus_rec ddc_i2c;
1197
1198 rdev->mode_info.connector_table = radeon_connector_table;
1199 if (rdev->mode_info.connector_table == CT_NONE) {
1200#ifdef CONFIG_PPC_PMAC
1201 if (machine_is_compatible("PowerBook3,3")) {
1202 /* powerbook with VGA */
1203 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1204 } else if (machine_is_compatible("PowerBook3,4") ||
1205 machine_is_compatible("PowerBook3,5")) {
1206 /* powerbook with internal tmds */
1207 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1208 } else if (machine_is_compatible("PowerBook5,1") ||
1209 machine_is_compatible("PowerBook5,2") ||
1210 machine_is_compatible("PowerBook5,3") ||
1211 machine_is_compatible("PowerBook5,4") ||
1212 machine_is_compatible("PowerBook5,5")) {
1213 /* powerbook with external single link tmds (sil164) */
1214 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1215 } else if (machine_is_compatible("PowerBook5,6")) {
1216 /* powerbook with external dual or single link tmds */
1217 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1218 } else if (machine_is_compatible("PowerBook5,7") ||
1219 machine_is_compatible("PowerBook5,8") ||
1220 machine_is_compatible("PowerBook5,9")) {
1221 /* PowerBook6,2 ? */
1222 /* powerbook with external dual link tmds (sil1178?) */
1223 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1224 } else if (machine_is_compatible("PowerBook4,1") ||
1225 machine_is_compatible("PowerBook4,2") ||
1226 machine_is_compatible("PowerBook4,3") ||
1227 machine_is_compatible("PowerBook6,3") ||
1228 machine_is_compatible("PowerBook6,5") ||
1229 machine_is_compatible("PowerBook6,7")) {
1230 /* ibook */
1231 rdev->mode_info.connector_table = CT_IBOOK;
1232 } else if (machine_is_compatible("PowerMac4,4")) {
1233 /* emac */
1234 rdev->mode_info.connector_table = CT_EMAC;
1235 } else if (machine_is_compatible("PowerMac10,1")) {
1236 /* mini with internal tmds */
1237 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1238 } else if (machine_is_compatible("PowerMac10,2")) {
1239 /* mini with external tmds */
1240 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1241 } else if (machine_is_compatible("PowerMac12,1")) {
1242 /* PowerMac8,1 ? */
1243 /* imac g5 isight */
1244 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1245 } else
1246#endif /* CONFIG_PPC_PMAC */
1247 rdev->mode_info.connector_table = CT_GENERIC;
1248 }
1249
1250 switch (rdev->mode_info.connector_table) {
1251 case CT_GENERIC:
1252 DRM_INFO("Connector Table: %d (generic)\n",
1253 rdev->mode_info.connector_table);
1254 /* these are the most common settings */
1255 if (rdev->flags & RADEON_SINGLE_CRTC) {
1256 /* VGA - primary dac */
1257 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1258 radeon_add_legacy_encoder(dev,
1259 radeon_get_encoder_id(dev,
1260 ATOM_DEVICE_CRT1_SUPPORT,
1261 1),
1262 ATOM_DEVICE_CRT1_SUPPORT);
1263 radeon_add_legacy_connector(dev, 0,
1264 ATOM_DEVICE_CRT1_SUPPORT,
1265 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1266 &ddc_i2c,
1267 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1268 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1269 /* LVDS */
1270 ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1271 radeon_add_legacy_encoder(dev,
1272 radeon_get_encoder_id(dev,
1273 ATOM_DEVICE_LCD1_SUPPORT,
1274 0),
1275 ATOM_DEVICE_LCD1_SUPPORT);
1276 radeon_add_legacy_connector(dev, 0,
1277 ATOM_DEVICE_LCD1_SUPPORT,
1278 DRM_MODE_CONNECTOR_LVDS,
b75fad06
AD		 1279 &ddc_i2c,
1280 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1281
1282 /* VGA - primary dac */
1283 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1284 radeon_add_legacy_encoder(dev,
1285 radeon_get_encoder_id(dev,
1286 ATOM_DEVICE_CRT1_SUPPORT,
1287 1),
1288 ATOM_DEVICE_CRT1_SUPPORT);
1289 radeon_add_legacy_connector(dev, 1,
1290 ATOM_DEVICE_CRT1_SUPPORT,
1291 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1292 &ddc_i2c,
1293 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1294 } else {
1295 /* DVI-I - tv dac, int tmds */
1296 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1297 radeon_add_legacy_encoder(dev,
1298 radeon_get_encoder_id(dev,
1299 ATOM_DEVICE_DFP1_SUPPORT,
1300 0),
1301 ATOM_DEVICE_DFP1_SUPPORT);
1302 radeon_add_legacy_encoder(dev,
1303 radeon_get_encoder_id(dev,
1304 ATOM_DEVICE_CRT2_SUPPORT,
1305 2),
1306 ATOM_DEVICE_CRT2_SUPPORT);
1307 radeon_add_legacy_connector(dev, 0,
1308 ATOM_DEVICE_DFP1_SUPPORT |
1309 ATOM_DEVICE_CRT2_SUPPORT,
1310 DRM_MODE_CONNECTOR_DVII,
b75fad06
AD		 1311 &ddc_i2c,
1312 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1313
1314 /* VGA - primary dac */
1315 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1316 radeon_add_legacy_encoder(dev,
1317 radeon_get_encoder_id(dev,
1318 ATOM_DEVICE_CRT1_SUPPORT,
1319 1),
1320 ATOM_DEVICE_CRT1_SUPPORT);
1321 radeon_add_legacy_connector(dev, 1,
1322 ATOM_DEVICE_CRT1_SUPPORT,
1323 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1324 &ddc_i2c,
1325 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1326 }
1327
1328 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1329 /* TV - tv dac */
1330 radeon_add_legacy_encoder(dev,
1331 radeon_get_encoder_id(dev,
1332 ATOM_DEVICE_TV1_SUPPORT,
1333 2),
1334 ATOM_DEVICE_TV1_SUPPORT);
1335 radeon_add_legacy_connector(dev, 2,
1336 ATOM_DEVICE_TV1_SUPPORT,
1337 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1338 &ddc_i2c,
1339 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1340 }
1341 break;
1342 case CT_IBOOK:
1343 DRM_INFO("Connector Table: %d (ibook)\n",
1344 rdev->mode_info.connector_table);
1345 /* LVDS */
1346 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1347 radeon_add_legacy_encoder(dev,
1348 radeon_get_encoder_id(dev,
1349 ATOM_DEVICE_LCD1_SUPPORT,
1350 0),
1351 ATOM_DEVICE_LCD1_SUPPORT);
1352 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1353 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1354 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1355 /* VGA - TV DAC */
1356 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1357 radeon_add_legacy_encoder(dev,
1358 radeon_get_encoder_id(dev,
1359 ATOM_DEVICE_CRT2_SUPPORT,
1360 2),
1361 ATOM_DEVICE_CRT2_SUPPORT);
1362 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1363 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1364 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1365 /* TV - TV DAC */
1366 radeon_add_legacy_encoder(dev,
1367 radeon_get_encoder_id(dev,
1368 ATOM_DEVICE_TV1_SUPPORT,
1369 2),
1370 ATOM_DEVICE_TV1_SUPPORT);
1371 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1372 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1373 &ddc_i2c,
1374 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1375 break;
1376 case CT_POWERBOOK_EXTERNAL:
1377 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1378 rdev->mode_info.connector_table);
1379 /* LVDS */
1380 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1381 radeon_add_legacy_encoder(dev,
1382 radeon_get_encoder_id(dev,
1383 ATOM_DEVICE_LCD1_SUPPORT,
1384 0),
1385 ATOM_DEVICE_LCD1_SUPPORT);
1386 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1387 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1388 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1389 /* DVI-I - primary dac, ext tmds */
1390 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1391 radeon_add_legacy_encoder(dev,
1392 radeon_get_encoder_id(dev,
1393 ATOM_DEVICE_DFP2_SUPPORT,
1394 0),
1395 ATOM_DEVICE_DFP2_SUPPORT);
1396 radeon_add_legacy_encoder(dev,
1397 radeon_get_encoder_id(dev,
1398 ATOM_DEVICE_CRT1_SUPPORT,
1399 1),
1400 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1401 /* XXX some are SL */
771fe6b9
JG		 1402 radeon_add_legacy_connector(dev, 1,
1403 ATOM_DEVICE_DFP2_SUPPORT |
1404 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1405 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1406 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I);
771fe6b9
JG		 1407 /* TV - TV DAC */
1408 radeon_add_legacy_encoder(dev,
1409 radeon_get_encoder_id(dev,
1410 ATOM_DEVICE_TV1_SUPPORT,
1411 2),
1412 ATOM_DEVICE_TV1_SUPPORT);
1413 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1414 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1415 &ddc_i2c,
1416 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1417 break;
1418 case CT_POWERBOOK_INTERNAL:
1419 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1420 rdev->mode_info.connector_table);
1421 /* LVDS */
1422 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1423 radeon_add_legacy_encoder(dev,
1424 radeon_get_encoder_id(dev,
1425 ATOM_DEVICE_LCD1_SUPPORT,
1426 0),
1427 ATOM_DEVICE_LCD1_SUPPORT);
1428 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1429 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1430 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1431 /* DVI-I - primary dac, int tmds */
1432 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1433 radeon_add_legacy_encoder(dev,
1434 radeon_get_encoder_id(dev,
1435 ATOM_DEVICE_DFP1_SUPPORT,
1436 0),
1437 ATOM_DEVICE_DFP1_SUPPORT);
1438 radeon_add_legacy_encoder(dev,
1439 radeon_get_encoder_id(dev,
1440 ATOM_DEVICE_CRT1_SUPPORT,
1441 1),
1442 ATOM_DEVICE_CRT1_SUPPORT);
1443 radeon_add_legacy_connector(dev, 1,
1444 ATOM_DEVICE_DFP1_SUPPORT |
1445 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1446 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1447 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1448 /* TV - TV DAC */
1449 radeon_add_legacy_encoder(dev,
1450 radeon_get_encoder_id(dev,
1451 ATOM_DEVICE_TV1_SUPPORT,
1452 2),
1453 ATOM_DEVICE_TV1_SUPPORT);
1454 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1455 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1456 &ddc_i2c,
1457 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1458 break;
1459 case CT_POWERBOOK_VGA:
1460 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1461 rdev->mode_info.connector_table);
1462 /* LVDS */
1463 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1464 radeon_add_legacy_encoder(dev,
1465 radeon_get_encoder_id(dev,
1466 ATOM_DEVICE_LCD1_SUPPORT,
1467 0),
1468 ATOM_DEVICE_LCD1_SUPPORT);
1469 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1470 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1471 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1472 /* VGA - primary dac */
1473 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1474 radeon_add_legacy_encoder(dev,
1475 radeon_get_encoder_id(dev,
1476 ATOM_DEVICE_CRT1_SUPPORT,
1477 1),
1478 ATOM_DEVICE_CRT1_SUPPORT);
1479 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1480 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1481 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1482 /* TV - TV DAC */
1483 radeon_add_legacy_encoder(dev,
1484 radeon_get_encoder_id(dev,
1485 ATOM_DEVICE_TV1_SUPPORT,
1486 2),
1487 ATOM_DEVICE_TV1_SUPPORT);
1488 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1489 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1490 &ddc_i2c,
1491 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1492 break;
1493 case CT_MINI_EXTERNAL:
1494 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1495 rdev->mode_info.connector_table);
1496 /* DVI-I - tv dac, ext tmds */
1497 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1498 radeon_add_legacy_encoder(dev,
1499 radeon_get_encoder_id(dev,
1500 ATOM_DEVICE_DFP2_SUPPORT,
1501 0),
1502 ATOM_DEVICE_DFP2_SUPPORT);
1503 radeon_add_legacy_encoder(dev,
1504 radeon_get_encoder_id(dev,
1505 ATOM_DEVICE_CRT2_SUPPORT,
1506 2),
1507 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1508 /* XXX are any DL? */
771fe6b9
JG		 1509 radeon_add_legacy_connector(dev, 0,
1510 ATOM_DEVICE_DFP2_SUPPORT |
1511 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1512 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1513 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1514 /* TV - TV DAC */
1515 radeon_add_legacy_encoder(dev,
1516 radeon_get_encoder_id(dev,
1517 ATOM_DEVICE_TV1_SUPPORT,
1518 2),
1519 ATOM_DEVICE_TV1_SUPPORT);
1520 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1521 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1522 &ddc_i2c,
1523 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1524 break;
1525 case CT_MINI_INTERNAL:
1526 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1527 rdev->mode_info.connector_table);
1528 /* DVI-I - tv dac, int tmds */
1529 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1530 radeon_add_legacy_encoder(dev,
1531 radeon_get_encoder_id(dev,
1532 ATOM_DEVICE_DFP1_SUPPORT,
1533 0),
1534 ATOM_DEVICE_DFP1_SUPPORT);
1535 radeon_add_legacy_encoder(dev,
1536 radeon_get_encoder_id(dev,
1537 ATOM_DEVICE_CRT2_SUPPORT,
1538 2),
1539 ATOM_DEVICE_CRT2_SUPPORT);
1540 radeon_add_legacy_connector(dev, 0,
1541 ATOM_DEVICE_DFP1_SUPPORT |
1542 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1543 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1544 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1545 /* TV - TV DAC */
1546 radeon_add_legacy_encoder(dev,
1547 radeon_get_encoder_id(dev,
1548 ATOM_DEVICE_TV1_SUPPORT,
1549 2),
1550 ATOM_DEVICE_TV1_SUPPORT);
1551 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1552 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1553 &ddc_i2c,
1554 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1555 break;
1556 case CT_IMAC_G5_ISIGHT:
1557 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1558 rdev->mode_info.connector_table);
1559 /* DVI-D - int tmds */
1560 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1561 radeon_add_legacy_encoder(dev,
1562 radeon_get_encoder_id(dev,
1563 ATOM_DEVICE_DFP1_SUPPORT,
1564 0),
1565 ATOM_DEVICE_DFP1_SUPPORT);
1566 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06
AD		 1567 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1568 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
771fe6b9
JG		 1569 /* VGA - tv dac */
1570 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1571 radeon_add_legacy_encoder(dev,
1572 radeon_get_encoder_id(dev,
1573 ATOM_DEVICE_CRT2_SUPPORT,
1574 2),
1575 ATOM_DEVICE_CRT2_SUPPORT);
1576 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1577 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1578 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1579 /* TV - TV DAC */
1580 radeon_add_legacy_encoder(dev,
1581 radeon_get_encoder_id(dev,
1582 ATOM_DEVICE_TV1_SUPPORT,
1583 2),
1584 ATOM_DEVICE_TV1_SUPPORT);
1585 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1586 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1587 &ddc_i2c,
1588 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1589 break;
1590 case CT_EMAC:
1591 DRM_INFO("Connector Table: %d (emac)\n",
1592 rdev->mode_info.connector_table);
1593 /* VGA - primary dac */
1594 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1595 radeon_add_legacy_encoder(dev,
1596 radeon_get_encoder_id(dev,
1597 ATOM_DEVICE_CRT1_SUPPORT,
1598 1),
1599 ATOM_DEVICE_CRT1_SUPPORT);
1600 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1601 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1602 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1603 /* VGA - tv dac */
1604 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1605 radeon_add_legacy_encoder(dev,
1606 radeon_get_encoder_id(dev,
1607 ATOM_DEVICE_CRT2_SUPPORT,
1608 2),
1609 ATOM_DEVICE_CRT2_SUPPORT);
1610 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1611 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1612 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1613 /* TV - TV DAC */
1614 radeon_add_legacy_encoder(dev,
1615 radeon_get_encoder_id(dev,
1616 ATOM_DEVICE_TV1_SUPPORT,
1617 2),
1618 ATOM_DEVICE_TV1_SUPPORT);
1619 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1620 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1621 &ddc_i2c,
1622 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1623 break;
1624 default:
1625 DRM_INFO("Connector table: %d (invalid)\n",
1626 rdev->mode_info.connector_table);
1627 return false;
1628 }
1629
1630 radeon_link_encoder_connector(dev);
1631
1632 return true;
1633}
1634
1635static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1636 int bios_index,
1637 enum radeon_combios_connector
1638 *legacy_connector,
1639 struct radeon_i2c_bus_rec *ddc_i2c)
1640{
1641 struct radeon_device *rdev = dev->dev_private;
1642
1643 /* XPRESS DDC quirks */
1644 if ((rdev->family == CHIP_RS400 ||
1645 rdev->family == CHIP_RS480) &&
1646 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1647 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1648 else if ((rdev->family == CHIP_RS400 ||
1649 rdev->family == CHIP_RS480) &&
1650 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1651 ddc_i2c->valid = true;
1652 ddc_i2c->mask_clk_mask = (0x20 << 8);
1653 ddc_i2c->mask_data_mask = 0x80;
1654 ddc_i2c->a_clk_mask = (0x20 << 8);
1655 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1656 ddc_i2c->en_clk_mask = (0x20 << 8);
1657 ddc_i2c->en_data_mask = 0x80;
1658 ddc_i2c->y_clk_mask = (0x20 << 8);
1659 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1660 ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
1661 ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
1662 ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
1663 ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
9b9fe724
AD		 1664 ddc_i2c->en_clk_reg = RADEON_GPIOPAD_EN;
1665 ddc_i2c->en_data_reg = RADEON_GPIOPAD_EN;
fcec570b
AD		 1666 ddc_i2c->y_clk_reg = RADEON_GPIOPAD_Y;
1667 ddc_i2c->y_data_reg = RADEON_GPIOPAD_Y;
771fe6b9
JG		 1668 }
1669
fcec570b
AD		 1670 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1671 if ((rdev->family >= CHIP_R300) &&
1672 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1673 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1674
771fe6b9
JG		 1675 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1676 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1677 if (dev->pdev->device == 0x515e &&
1678 dev->pdev->subsystem_vendor == 0x1014) {
1679 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1680 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1681 return false;
1682 }
1683
1684 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1685 if (dev->pdev->device == 0x5159 &&
1686 dev->pdev->subsystem_vendor == 0x1002 &&
1687 dev->pdev->subsystem_device == 0x013a) {
1688 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1689 *legacy_connector = CONNECTOR_CRT_LEGACY;
1690
1691 }
1692
1693 /* X300 card with extra non-existent DVI port */
1694 if (dev->pdev->device == 0x5B60 &&
1695 dev->pdev->subsystem_vendor == 0x17af &&
1696 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1697 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1698 return false;
1699 }
1700
1701 return true;
1702}
1703
790cfb34
AD		 1704static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1705{
1706 /* Acer 5102 has non-existent TV port */
1707 if (dev->pdev->device == 0x5975 &&
1708 dev->pdev->subsystem_vendor == 0x1025 &&
1709 dev->pdev->subsystem_device == 0x009f)
1710 return false;
1711
fc7f7119
AD		 1712 /* HP dc5750 has non-existent TV port */
1713 if (dev->pdev->device == 0x5974 &&
1714 dev->pdev->subsystem_vendor == 0x103c &&
1715 dev->pdev->subsystem_device == 0x280a)
1716 return false;
1717
790cfb34
AD		 1718 return true;
1719}
1720
b75fad06
AD		 1721static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1722{
1723 struct radeon_device *rdev = dev->dev_private;
1724 uint32_t ext_tmds_info;
1725
1726 if (rdev->flags & RADEON_IS_IGP) {
1727 if (is_dvi_d)
1728 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1729 else
1730 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1731 }
1732 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1733 if (ext_tmds_info) {
1734 uint8_t rev = RBIOS8(ext_tmds_info);
1735 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1736 if (rev >= 3) {
1737 if (is_dvi_d)
1738 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1739 else
1740 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1741 } else {
1742 if (flags & 1) {
1743 if (is_dvi_d)
1744 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1745 else
1746 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1747 }
1748 }
1749 }
1750 if (is_dvi_d)
1751 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1752 else
1753 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1754}
1755
771fe6b9
JG		 1756bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1757{
1758 struct radeon_device *rdev = dev->dev_private;
1759 uint32_t conn_info, entry, devices;
b75fad06 1760 uint16_t tmp, connector_object_id;
771fe6b9
JG		 1761 enum radeon_combios_ddc ddc_type;
1762 enum radeon_combios_connector connector;
1763 int i = 0;
1764 struct radeon_i2c_bus_rec ddc_i2c;
1765
1766 if (rdev->bios == NULL)
1767 return false;
1768
1769 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1770 if (conn_info) {
1771 for (i = 0; i < 4; i++) {
1772 entry = conn_info + 2 + i * 2;
1773
1774 if (!RBIOS16(entry))
1775 break;
1776
1777 tmp = RBIOS16(entry);
1778
1779 connector = (tmp >> 12) & 0xf;
1780
1781 ddc_type = (tmp >> 8) & 0xf;
1782 switch (ddc_type) {
1783 case DDC_MONID:
1784 ddc_i2c =
1785 combios_setup_i2c_bus(RADEON_GPIO_MONID);
1786 break;
1787 case DDC_DVI:
1788 ddc_i2c =
1789 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1790 break;
1791 case DDC_VGA:
1792 ddc_i2c =
1793 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1794 break;
1795 case DDC_CRT2:
1796 ddc_i2c =
1797 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1798 break;
1799 default:
1800 break;
1801 }
1802
2d152c6b
AD		 1803 if (!radeon_apply_legacy_quirks(dev, i, &connector,
1804 &ddc_i2c))
1805 continue;
771fe6b9
JG		 1806
1807 switch (connector) {
1808 case CONNECTOR_PROPRIETARY_LEGACY:
1809 if ((tmp >> 4) & 0x1)
1810 devices = ATOM_DEVICE_DFP2_SUPPORT;
1811 else
1812 devices = ATOM_DEVICE_DFP1_SUPPORT;
1813 radeon_add_legacy_encoder(dev,
1814 radeon_get_encoder_id
1815 (dev, devices, 0),
1816 devices);
1817 radeon_add_legacy_connector(dev, i, devices,
1818 legacy_connector_convert
1819 [connector],
b75fad06
AD		 1820 &ddc_i2c,
1821 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
771fe6b9
JG		 1822 break;
1823 case CONNECTOR_CRT_LEGACY:
1824 if (tmp & 0x1) {
1825 devices = ATOM_DEVICE_CRT2_SUPPORT;
1826 radeon_add_legacy_encoder(dev,
1827 radeon_get_encoder_id
1828 (dev,
1829 ATOM_DEVICE_CRT2_SUPPORT,
1830 2),
1831 ATOM_DEVICE_CRT2_SUPPORT);
1832 } else {
1833 devices = ATOM_DEVICE_CRT1_SUPPORT;
1834 radeon_add_legacy_encoder(dev,
1835 radeon_get_encoder_id
1836 (dev,
1837 ATOM_DEVICE_CRT1_SUPPORT,
1838 1),
1839 ATOM_DEVICE_CRT1_SUPPORT);
1840 }
1841 radeon_add_legacy_connector(dev,
1842 i,
1843 devices,
1844 legacy_connector_convert
1845 [connector],
b75fad06
AD		 1846 &ddc_i2c,
1847 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1848 break;
1849 case CONNECTOR_DVI_I_LEGACY:
1850 devices = 0;
1851 if (tmp & 0x1) {
1852 devices |= ATOM_DEVICE_CRT2_SUPPORT;
1853 radeon_add_legacy_encoder(dev,
1854 radeon_get_encoder_id
1855 (dev,
1856 ATOM_DEVICE_CRT2_SUPPORT,
1857 2),
1858 ATOM_DEVICE_CRT2_SUPPORT);
1859 } else {
1860 devices |= ATOM_DEVICE_CRT1_SUPPORT;
1861 radeon_add_legacy_encoder(dev,
1862 radeon_get_encoder_id
1863 (dev,
1864 ATOM_DEVICE_CRT1_SUPPORT,
1865 1),
1866 ATOM_DEVICE_CRT1_SUPPORT);
1867 }
1868 if ((tmp >> 4) & 0x1) {
1869 devices |= ATOM_DEVICE_DFP2_SUPPORT;
1870 radeon_add_legacy_encoder(dev,
1871 radeon_get_encoder_id
1872 (dev,
1873 ATOM_DEVICE_DFP2_SUPPORT,
1874 0),
1875 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 1876 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 1877 } else {
1878 devices |= ATOM_DEVICE_DFP1_SUPPORT;
1879 radeon_add_legacy_encoder(dev,
1880 radeon_get_encoder_id
1881 (dev,
1882 ATOM_DEVICE_DFP1_SUPPORT,
1883 0),
1884 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 1885 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 1886 }
1887 radeon_add_legacy_connector(dev,
1888 i,
1889 devices,
1890 legacy_connector_convert
1891 [connector],
b75fad06
AD		 1892 &ddc_i2c,
1893 connector_object_id);
771fe6b9
JG		 1894 break;
1895 case CONNECTOR_DVI_D_LEGACY:
b75fad06 1896 if ((tmp >> 4) & 0x1) {
771fe6b9 1897 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 1898 connector_object_id = combios_check_dl_dvi(dev, 1);
1899 } else {
771fe6b9 1900 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 1901 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1902 }
771fe6b9
JG		 1903 radeon_add_legacy_encoder(dev,
1904 radeon_get_encoder_id
1905 (dev, devices, 0),
1906 devices);
1907 radeon_add_legacy_connector(dev, i, devices,
1908 legacy_connector_convert
1909 [connector],
b75fad06
AD		 1910 &ddc_i2c,
1911 connector_object_id);
771fe6b9
JG		 1912 break;
1913 case CONNECTOR_CTV_LEGACY:
1914 case CONNECTOR_STV_LEGACY:
1915 radeon_add_legacy_encoder(dev,
1916 radeon_get_encoder_id
1917 (dev,
1918 ATOM_DEVICE_TV1_SUPPORT,
1919 2),
1920 ATOM_DEVICE_TV1_SUPPORT);
1921 radeon_add_legacy_connector(dev, i,
1922 ATOM_DEVICE_TV1_SUPPORT,
1923 legacy_connector_convert
1924 [connector],
b75fad06
AD		 1925 &ddc_i2c,
1926 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1927 break;
1928 default:
1929 DRM_ERROR("Unknown connector type: %d\n",
1930 connector);
1931 continue;
1932 }
1933
1934 }
1935 } else {
1936 uint16_t tmds_info =
1937 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1938 if (tmds_info) {
1939 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1940
1941 radeon_add_legacy_encoder(dev,
1942 radeon_get_encoder_id(dev,
1943 ATOM_DEVICE_CRT1_SUPPORT,
1944 1),
1945 ATOM_DEVICE_CRT1_SUPPORT);
1946 radeon_add_legacy_encoder(dev,
1947 radeon_get_encoder_id(dev,
1948 ATOM_DEVICE_DFP1_SUPPORT,
1949 0),
1950 ATOM_DEVICE_DFP1_SUPPORT);
1951
1952 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1953 radeon_add_legacy_connector(dev,
1954 0,
1955 ATOM_DEVICE_CRT1_SUPPORT |
1956 ATOM_DEVICE_DFP1_SUPPORT,
1957 DRM_MODE_CONNECTOR_DVII,
b75fad06
AD		 1958 &ddc_i2c,
1959 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9 1960 } else {
d0c403e9
AD		 1961 uint16_t crt_info =
1962 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1963 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
1964 if (crt_info) {
1965 radeon_add_legacy_encoder(dev,
1966 radeon_get_encoder_id(dev,
1967 ATOM_DEVICE_CRT1_SUPPORT,
1968 1),
1969 ATOM_DEVICE_CRT1_SUPPORT);
1970 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1971 radeon_add_legacy_connector(dev,
1972 0,
1973 ATOM_DEVICE_CRT1_SUPPORT,
1974 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1975 &ddc_i2c,
1976 CONNECTOR_OBJECT_ID_VGA);
d0c403e9
AD		 1977 } else {
1978 DRM_DEBUG("No connector info found\n");
1979 return false;
1980 }
771fe6b9
JG		 1981 }
1982 }
1983
1984 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
1985 uint16_t lcd_info =
1986 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1987 if (lcd_info) {
1988 uint16_t lcd_ddc_info =
1989 combios_get_table_offset(dev,
1990 COMBIOS_LCD_DDC_INFO_TABLE);
1991
1992 radeon_add_legacy_encoder(dev,
1993 radeon_get_encoder_id(dev,
1994 ATOM_DEVICE_LCD1_SUPPORT,
1995 0),
1996 ATOM_DEVICE_LCD1_SUPPORT);
1997
1998 if (lcd_ddc_info) {
1999 ddc_type = RBIOS8(lcd_ddc_info + 2);
2000 switch (ddc_type) {
2001 case DDC_MONID:
2002 ddc_i2c =
2003 combios_setup_i2c_bus
2004 (RADEON_GPIO_MONID);
2005 break;
2006 case DDC_DVI:
2007 ddc_i2c =
2008 combios_setup_i2c_bus
2009 (RADEON_GPIO_DVI_DDC);
2010 break;
2011 case DDC_VGA:
2012 ddc_i2c =
2013 combios_setup_i2c_bus
2014 (RADEON_GPIO_VGA_DDC);
2015 break;
2016 case DDC_CRT2:
2017 ddc_i2c =
2018 combios_setup_i2c_bus
2019 (RADEON_GPIO_CRT2_DDC);
2020 break;
2021 case DDC_LCD:
2022 ddc_i2c =
2023 combios_setup_i2c_bus
2024 (RADEON_LCD_GPIO_MASK);
2025 ddc_i2c.mask_clk_mask =
2026 RBIOS32(lcd_ddc_info + 3);
2027 ddc_i2c.mask_data_mask =
2028 RBIOS32(lcd_ddc_info + 7);
2029 ddc_i2c.a_clk_mask =
2030 RBIOS32(lcd_ddc_info + 3);
2031 ddc_i2c.a_data_mask =
2032 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2033 ddc_i2c.en_clk_mask =
771fe6b9 2034 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2035 ddc_i2c.en_data_mask =
771fe6b9 2036 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2037 ddc_i2c.y_clk_mask =
771fe6b9 2038 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2039 ddc_i2c.y_data_mask =
771fe6b9
JG		 2040 RBIOS32(lcd_ddc_info + 7);
2041 break;
2042 case DDC_GPIO:
2043 ddc_i2c =
2044 combios_setup_i2c_bus
2045 (RADEON_MDGPIO_EN_REG);
2046 ddc_i2c.mask_clk_mask =
2047 RBIOS32(lcd_ddc_info + 3);
2048 ddc_i2c.mask_data_mask =
2049 RBIOS32(lcd_ddc_info + 7);
2050 ddc_i2c.a_clk_mask =
2051 RBIOS32(lcd_ddc_info + 3);
2052 ddc_i2c.a_data_mask =
2053 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2054 ddc_i2c.en_clk_mask =
771fe6b9 2055 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2056 ddc_i2c.en_data_mask =
771fe6b9 2057 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2058 ddc_i2c.y_clk_mask =
771fe6b9 2059 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2060 ddc_i2c.y_data_mask =
771fe6b9
JG		 2061 RBIOS32(lcd_ddc_info + 7);
2062 break;
2063 default:
2064 ddc_i2c.valid = false;
2065 break;
2066 }
2067 DRM_DEBUG("LCD DDC Info Table found!\n");
2068 } else
2069 ddc_i2c.valid = false;
2070
2071 radeon_add_legacy_connector(dev,
2072 5,
2073 ATOM_DEVICE_LCD1_SUPPORT,
2074 DRM_MODE_CONNECTOR_LVDS,
b75fad06
AD		 2075 &ddc_i2c,
2076 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 2077 }
2078 }
2079
2080 /* check TV table */
2081 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2082 uint32_t tv_info =
2083 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2084 if (tv_info) {
2085 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34
AD		 2086 if (radeon_apply_legacy_tv_quirks(dev)) {
2087 radeon_add_legacy_encoder(dev,
2088 radeon_get_encoder_id
2089 (dev,
2090 ATOM_DEVICE_TV1_SUPPORT,
2091 2),
2092 ATOM_DEVICE_TV1_SUPPORT);
2093 radeon_add_legacy_connector(dev, 6,
2094 ATOM_DEVICE_TV1_SUPPORT,
2095 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 2096 &ddc_i2c,
2097 CONNECTOR_OBJECT_ID_SVIDEO);
790cfb34 2098 }
771fe6b9
JG		 2099 }
2100 }
2101 }
2102
2103 radeon_link_encoder_connector(dev);
2104
2105 return true;
2106}
2107
fcec570b
AD		 2108void radeon_external_tmds_setup(struct drm_encoder *encoder)
2109{
2110 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2111 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2112
2113 if (!tmds)
2114 return;
2115
2116 switch (tmds->dvo_chip) {
2117 case DVO_SIL164:
2118 /* sil 164 */
2119 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2120 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2121 tmds->slave_addr,
2122 0x08, 0x30);
2123 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2124 tmds->slave_addr,
2125 0x09, 0x00);
2126 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2127 tmds->slave_addr,
2128 0x0a, 0x90);
2129 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2130 tmds->slave_addr,
2131 0x0c, 0x89);
2132 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2133 tmds->slave_addr,
2134 0x08, 0x3b);
2135 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2136 break;
2137 case DVO_SIL1178:
2138 /* sil 1178 - untested */
2139 /*
2140 * 0x0f, 0x44
2141 * 0x0f, 0x4c
2142 * 0x0e, 0x01
2143 * 0x0a, 0x80
2144 * 0x09, 0x30
2145 * 0x0c, 0xc9
2146 * 0x0d, 0x70
2147 * 0x08, 0x32
2148 * 0x08, 0x33
2149 */
2150 break;
2151 default:
2152 break;
2153 }
2154
2155}
2156
2157bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2158{
2159 struct drm_device *dev = encoder->dev;
2160 struct radeon_device *rdev = dev->dev_private;
2161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2162 uint16_t offset;
2163 uint8_t blocks, slave_addr, rev;
2164 uint32_t index, id;
2165 uint32_t reg, val, and_mask, or_mask;
2166 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2167
2168 if (rdev->bios == NULL)
2169 return false;
2170
2171 if (!tmds)
2172 return false;
2173
2174 if (rdev->flags & RADEON_IS_IGP) {
2175 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2176 rev = RBIOS8(offset);
2177 if (offset) {
2178 rev = RBIOS8(offset);
2179 if (rev > 1) {
2180 blocks = RBIOS8(offset + 3);
2181 index = offset + 4;
2182 while (blocks > 0) {
2183 id = RBIOS16(index);
2184 index += 2;
2185 switch (id >> 13) {
2186 case 0:
2187 reg = (id & 0x1fff) * 4;
2188 val = RBIOS32(index);
2189 index += 4;
2190 WREG32(reg, val);
2191 break;
2192 case 2:
2193 reg = (id & 0x1fff) * 4;
2194 and_mask = RBIOS32(index);
2195 index += 4;
2196 or_mask = RBIOS32(index);
2197 index += 4;
2198 val = RREG32(reg);
2199 val = (val & and_mask) | or_mask;
2200 WREG32(reg, val);
2201 break;
2202 case 3:
2203 val = RBIOS16(index);
2204 index += 2;
2205 udelay(val);
2206 break;
2207 case 4:
2208 val = RBIOS16(index);
2209 index += 2;
2210 udelay(val * 1000);
2211 break;
2212 case 6:
2213 slave_addr = id & 0xff;
2214 slave_addr >>= 1; /* 7 bit addressing */
2215 index++;
2216 reg = RBIOS8(index);
2217 index++;
2218 val = RBIOS8(index);
2219 index++;
2220 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2221 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2222 slave_addr,
2223 reg, val);
2224 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2225 break;
2226 default:
2227 DRM_ERROR("Unknown id %d\n", id >> 13);
2228 break;
2229 }
2230 blocks--;
2231 }
2232 return true;
2233 }
2234 }
2235 } else {
2236 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2237 if (offset) {
2238 index = offset + 10;
2239 id = RBIOS16(index);
2240 while (id != 0xffff) {
2241 index += 2;
2242 switch (id >> 13) {
2243 case 0:
2244 reg = (id & 0x1fff) * 4;
2245 val = RBIOS32(index);
2246 WREG32(reg, val);
2247 break;
2248 case 2:
2249 reg = (id & 0x1fff) * 4;
2250 and_mask = RBIOS32(index);
2251 index += 4;
2252 or_mask = RBIOS32(index);
2253 index += 4;
2254 val = RREG32(reg);
2255 val = (val & and_mask) | or_mask;
2256 WREG32(reg, val);
2257 break;
2258 case 4:
2259 val = RBIOS16(index);
2260 index += 2;
2261 udelay(val);
2262 break;
2263 case 5:
2264 reg = id & 0x1fff;
2265 and_mask = RBIOS32(index);
2266 index += 4;
2267 or_mask = RBIOS32(index);
2268 index += 4;
2269 val = RREG32_PLL(reg);
2270 val = (val & and_mask) | or_mask;
2271 WREG32_PLL(reg, val);
2272 break;
2273 case 6:
2274 reg = id & 0x1fff;
2275 val = RBIOS8(index);
2276 index += 1;
2277 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2278 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2279 tmds->slave_addr,
2280 reg, val);
2281 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2282 break;
2283 default:
2284 DRM_ERROR("Unknown id %d\n", id >> 13);
2285 break;
2286 }
2287 id = RBIOS16(index);
2288 }
2289 return true;
2290 }
2291 }
2292 return false;
2293}
2294
771fe6b9
JG		 2295static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2296{
2297 struct radeon_device *rdev = dev->dev_private;
2298
2299 if (offset) {
2300 while (RBIOS16(offset)) {
2301 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2302 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2303 uint32_t val, and_mask, or_mask;
2304 uint32_t tmp;
2305
2306 offset += 2;
2307 switch (cmd) {
2308 case 0:
2309 val = RBIOS32(offset);
2310 offset += 4;
2311 WREG32(addr, val);
2312 break;
2313 case 1:
2314 val = RBIOS32(offset);
2315 offset += 4;
2316 WREG32(addr, val);
2317 break;
2318 case 2:
2319 and_mask = RBIOS32(offset);
2320 offset += 4;
2321 or_mask = RBIOS32(offset);
2322 offset += 4;
2323 tmp = RREG32(addr);
2324 tmp &= and_mask;
2325 tmp |= or_mask;
2326 WREG32(addr, tmp);
2327 break;
2328 case 3:
2329 and_mask = RBIOS32(offset);
2330 offset += 4;
2331 or_mask = RBIOS32(offset);
2332 offset += 4;
2333 tmp = RREG32(addr);
2334 tmp &= and_mask;
2335 tmp |= or_mask;
2336 WREG32(addr, tmp);
2337 break;
2338 case 4:
2339 val = RBIOS16(offset);
2340 offset += 2;
2341 udelay(val);
2342 break;
2343 case 5:
2344 val = RBIOS16(offset);
2345 offset += 2;
2346 switch (addr) {
2347 case 8:
2348 while (val--) {
2349 if (!
2350 (RREG32_PLL
2351 (RADEON_CLK_PWRMGT_CNTL) &
2352 RADEON_MC_BUSY))
2353 break;
2354 }
2355 break;
2356 case 9:
2357 while (val--) {
2358 if ((RREG32(RADEON_MC_STATUS) &
2359 RADEON_MC_IDLE))
2360 break;
2361 }
2362 break;
2363 default:
2364 break;
2365 }
2366 break;
2367 default:
2368 break;
2369 }
2370 }
2371 }
2372}
2373
2374static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2375{
2376 struct radeon_device *rdev = dev->dev_private;
2377
2378 if (offset) {
2379 while (RBIOS8(offset)) {
2380 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2381 uint8_t addr = (RBIOS8(offset) & 0x3f);
2382 uint32_t val, shift, tmp;
2383 uint32_t and_mask, or_mask;
2384
2385 offset++;
2386 switch (cmd) {
2387 case 0:
2388 val = RBIOS32(offset);
2389 offset += 4;
2390 WREG32_PLL(addr, val);
2391 break;
2392 case 1:
2393 shift = RBIOS8(offset) * 8;
2394 offset++;
2395 and_mask = RBIOS8(offset) << shift;
2396 and_mask |= ~(0xff << shift);
2397 offset++;
2398 or_mask = RBIOS8(offset) << shift;
2399 offset++;
2400 tmp = RREG32_PLL(addr);
2401 tmp &= and_mask;
2402 tmp |= or_mask;
2403 WREG32_PLL(addr, tmp);
2404 break;
2405 case 2:
2406 case 3:
2407 tmp = 1000;
2408 switch (addr) {
2409 case 1:
2410 udelay(150);
2411 break;
2412 case 2:
2413 udelay(1000);
2414 break;
2415 case 3:
2416 while (tmp--) {
2417 if (!
2418 (RREG32_PLL
2419 (RADEON_CLK_PWRMGT_CNTL) &
2420 RADEON_MC_BUSY))
2421 break;
2422 }
2423 break;
2424 case 4:
2425 while (tmp--) {
2426 if (RREG32_PLL
2427 (RADEON_CLK_PWRMGT_CNTL) &
2428 RADEON_DLL_READY)
2429 break;
2430 }
2431 break;
2432 case 5:
2433 tmp =
2434 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2435 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2436#if 0
2437 uint32_t mclk_cntl =
2438 RREG32_PLL
2439 (RADEON_MCLK_CNTL);
2440 mclk_cntl &= 0xffff0000;
2441 /*mclk_cntl |= 0x00001111;*//* ??? */
2442 WREG32_PLL(RADEON_MCLK_CNTL,
2443 mclk_cntl);
2444 udelay(10000);
2445#endif
2446 WREG32_PLL
2447 (RADEON_CLK_PWRMGT_CNTL,
2448 tmp &
2449 ~RADEON_CG_NO1_DEBUG_0);
2450 udelay(10000);
2451 }
2452 break;
2453 default:
2454 break;
2455 }
2456 break;
2457 default:
2458 break;
2459 }
2460 }
2461 }
2462}
2463
2464static void combios_parse_ram_reset_table(struct drm_device *dev,
2465 uint16_t offset)
2466{
2467 struct radeon_device *rdev = dev->dev_private;
2468 uint32_t tmp;
2469
2470 if (offset) {
2471 uint8_t val = RBIOS8(offset);
2472 while (val != 0xff) {
2473 offset++;
2474
2475 if (val == 0x0f) {
2476 uint32_t channel_complete_mask;
2477
2478 if (ASIC_IS_R300(rdev))
2479 channel_complete_mask =
2480 R300_MEM_PWRUP_COMPLETE;
2481 else
2482 channel_complete_mask =
2483 RADEON_MEM_PWRUP_COMPLETE;
2484 tmp = 20000;
2485 while (tmp--) {
2486 if ((RREG32(RADEON_MEM_STR_CNTL) &
2487 channel_complete_mask) ==
2488 channel_complete_mask)
2489 break;
2490 }
2491 } else {
2492 uint32_t or_mask = RBIOS16(offset);
2493 offset += 2;
2494
2495 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2496 tmp &= RADEON_SDRAM_MODE_MASK;
2497 tmp |= or_mask;
2498 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2499
2500 or_mask = val << 24;
2501 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2502 tmp &= RADEON_B3MEM_RESET_MASK;
2503 tmp |= or_mask;
2504 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2505 }
2506 val = RBIOS8(offset);
2507 }
2508 }
2509}
2510
2511static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2512 int mem_addr_mapping)
2513{
2514 struct radeon_device *rdev = dev->dev_private;
2515 uint32_t mem_cntl;
2516 uint32_t mem_size;
2517 uint32_t addr = 0;
2518
2519 mem_cntl = RREG32(RADEON_MEM_CNTL);
2520 if (mem_cntl & RV100_HALF_MODE)
2521 ram /= 2;
2522 mem_size = ram;
2523 mem_cntl &= ~(0xff << 8);
2524 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2525 WREG32(RADEON_MEM_CNTL, mem_cntl);
2526 RREG32(RADEON_MEM_CNTL);
2527
2528 /* sdram reset ? */
2529
2530 /* something like this???? */
2531 while (ram--) {
2532 addr = ram * 1024 * 1024;
2533 /* write to each page */
2534 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2535 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2536 /* read back and verify */
2537 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2538 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2539 return 0;
2540 }
2541
2542 return mem_size;
2543}
2544
2545static void combios_write_ram_size(struct drm_device *dev)
2546{
2547 struct radeon_device *rdev = dev->dev_private;
2548 uint8_t rev;
2549 uint16_t offset;
2550 uint32_t mem_size = 0;
2551 uint32_t mem_cntl = 0;
2552
2553 /* should do something smarter here I guess... */
2554 if (rdev->flags & RADEON_IS_IGP)
2555 return;
2556
2557 /* first check detected mem table */
2558 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2559 if (offset) {
2560 rev = RBIOS8(offset);
2561 if (rev < 3) {
2562 mem_cntl = RBIOS32(offset + 1);
2563 mem_size = RBIOS16(offset + 5);
2564 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2565 ((dev->pdev->device != 0x515e)
2566 && (dev->pdev->device != 0x5969)))
2567 WREG32(RADEON_MEM_CNTL, mem_cntl);
2568 }
2569 }
2570
2571 if (!mem_size) {
2572 offset =
2573 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2574 if (offset) {
2575 rev = RBIOS8(offset - 1);
2576 if (rev < 1) {
2577 if (((rdev->flags & RADEON_FAMILY_MASK) <
2578 CHIP_R200)
2579 && ((dev->pdev->device != 0x515e)
2580 && (dev->pdev->device != 0x5969))) {
2581 int ram = 0;
2582 int mem_addr_mapping = 0;
2583
2584 while (RBIOS8(offset)) {
2585 ram = RBIOS8(offset);
2586 mem_addr_mapping =
2587 RBIOS8(offset + 1);
2588 if (mem_addr_mapping != 0x25)
2589 ram *= 2;
2590 mem_size =
2591 combios_detect_ram(dev, ram,
2592 mem_addr_mapping);
2593 if (mem_size)
2594 break;
2595 offset += 2;
2596 }
2597 } else
2598 mem_size = RBIOS8(offset);
2599 } else {
2600 mem_size = RBIOS8(offset);
2601 mem_size *= 2; /* convert to MB */
2602 }
2603 }
2604 }
2605
2606 mem_size *= (1024 * 1024); /* convert to bytes */
2607 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2608}
2609
2610void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2611{
2612 uint16_t dyn_clk_info =
2613 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2614
2615 if (dyn_clk_info)
2616 combios_parse_pll_table(dev, dyn_clk_info);
2617}
2618
2619void radeon_combios_asic_init(struct drm_device *dev)
2620{
2621 struct radeon_device *rdev = dev->dev_private;
2622 uint16_t table;
2623
2624 /* port hardcoded mac stuff from radeonfb */
2625 if (rdev->bios == NULL)
2626 return;
2627
2628 /* ASIC INIT 1 */
2629 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2630 if (table)
2631 combios_parse_mmio_table(dev, table);
2632
2633 /* PLL INIT */
2634 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2635 if (table)
2636 combios_parse_pll_table(dev, table);
2637
2638 /* ASIC INIT 2 */
2639 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2640 if (table)
2641 combios_parse_mmio_table(dev, table);
2642
2643 if (!(rdev->flags & RADEON_IS_IGP)) {
2644 /* ASIC INIT 4 */
2645 table =
2646 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2647 if (table)
2648 combios_parse_mmio_table(dev, table);
2649
2650 /* RAM RESET */
2651 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2652 if (table)
2653 combios_parse_ram_reset_table(dev, table);
2654
2655 /* ASIC INIT 3 */
2656 table =
2657 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2658 if (table)
2659 combios_parse_mmio_table(dev, table);
2660
2661 /* write CONFIG_MEMSIZE */
2662 combios_write_ram_size(dev);
2663 }
2664
2665 /* DYN CLK 1 */
2666 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2667 if (table)
2668 combios_parse_pll_table(dev, table);
2669
2670}
2671
2672void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2673{
2674 struct radeon_device *rdev = dev->dev_private;
2675 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2676
2677 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2678 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2679 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2680
2681 /* let the bios control the backlight */
2682 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2683
2684 /* tell the bios not to handle mode switching */
2685 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2686 RADEON_ACC_MODE_CHANGE);
2687
2688 /* tell the bios a driver is loaded */
2689 bios_7_scratch |= RADEON_DRV_LOADED;
2690
2691 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2692 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2693 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2694}
2695
2696void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2697{
2698 struct drm_device *dev = encoder->dev;
2699 struct radeon_device *rdev = dev->dev_private;
2700 uint32_t bios_6_scratch;
2701
2702 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2703
2704 if (lock)
2705 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2706 else
2707 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2708
2709 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2710}
2711
2712void
2713radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2714 struct drm_encoder *encoder,
2715 bool connected)
2716{
2717 struct drm_device *dev = connector->dev;
2718 struct radeon_device *rdev = dev->dev_private;
2719 struct radeon_connector *radeon_connector =
2720 to_radeon_connector(connector);
2721 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2722 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2723 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2724
2725 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2726 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2727 if (connected) {
2728 DRM_DEBUG("TV1 connected\n");
2729 /* fix me */
2730 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2731 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2732 bios_5_scratch |= RADEON_TV1_ON;
2733 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2734 } else {
2735 DRM_DEBUG("TV1 disconnected\n");
2736 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2737 bios_5_scratch &= ~RADEON_TV1_ON;
2738 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2739 }
2740 }
2741 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2742 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2743 if (connected) {
2744 DRM_DEBUG("LCD1 connected\n");
2745 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2746 bios_5_scratch |= RADEON_LCD1_ON;
2747 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2748 } else {
2749 DRM_DEBUG("LCD1 disconnected\n");
2750 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2751 bios_5_scratch &= ~RADEON_LCD1_ON;
2752 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2753 }
2754 }
2755 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2756 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2757 if (connected) {
2758 DRM_DEBUG("CRT1 connected\n");
2759 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2760 bios_5_scratch |= RADEON_CRT1_ON;
2761 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2762 } else {
2763 DRM_DEBUG("CRT1 disconnected\n");
2764 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2765 bios_5_scratch &= ~RADEON_CRT1_ON;
2766 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2767 }
2768 }
2769 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2770 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2771 if (connected) {
2772 DRM_DEBUG("CRT2 connected\n");
2773 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2774 bios_5_scratch |= RADEON_CRT2_ON;
2775 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2776 } else {
2777 DRM_DEBUG("CRT2 disconnected\n");
2778 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2779 bios_5_scratch &= ~RADEON_CRT2_ON;
2780 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2781 }
2782 }
2783 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2784 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2785 if (connected) {
2786 DRM_DEBUG("DFP1 connected\n");
2787 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2788 bios_5_scratch |= RADEON_DFP1_ON;
2789 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2790 } else {
2791 DRM_DEBUG("DFP1 disconnected\n");
2792 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2793 bios_5_scratch &= ~RADEON_DFP1_ON;
2794 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2795 }
2796 }
2797 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2798 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2799 if (connected) {
2800 DRM_DEBUG("DFP2 connected\n");
2801 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2802 bios_5_scratch |= RADEON_DFP2_ON;
2803 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2804 } else {
2805 DRM_DEBUG("DFP2 disconnected\n");
2806 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2807 bios_5_scratch &= ~RADEON_DFP2_ON;
2808 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2809 }
2810 }
2811 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2812 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2813}
2814
2815void
2816radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2817{
2818 struct drm_device *dev = encoder->dev;
2819 struct radeon_device *rdev = dev->dev_private;
2820 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2821 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2822
2823 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2824 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2825 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2826 }
2827 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2828 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2829 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2830 }
2831 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2832 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2833 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2834 }
2835 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2836 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2837 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2838 }
2839 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2840 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2841 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2842 }
2843 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2844 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2845 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2846 }
2847 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2848}
2849
2850void
2851radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2852{
2853 struct drm_device *dev = encoder->dev;
2854 struct radeon_device *rdev = dev->dev_private;
2855 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2856 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2857
2858 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2859 if (on)
2860 bios_6_scratch |= RADEON_TV_DPMS_ON;
2861 else
2862 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2863 }
2864 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2865 if (on)
2866 bios_6_scratch |= RADEON_CRT_DPMS_ON;
2867 else
2868 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2869 }
2870 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2871 if (on)
2872 bios_6_scratch |= RADEON_LCD_DPMS_ON;
2873 else
2874 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
2875 }
2876 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
2877 if (on)
2878 bios_6_scratch |= RADEON_DFP_DPMS_ON;
2879 else
2880 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
2881 }
2882 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2883}
Clone of davem's net-next-2.6 tree