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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
5137ee94
AD		 42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
771fe6b9
JG		 44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
5137ee94 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
03047cdf
MD		 153 if (!rdev->bios)
154 return 0;
155
771fe6b9
JG		 156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447}
448
3c537889
AD		 449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450{
451 int edid_info;
452 struct edid *edid;
7466f4cc 453 unsigned char *raw;
3c537889
AD		 454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
7466f4cc
AJ		 458 raw = rdev->bios + edid_info;
459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
3c537889
AD		 460 if (edid == NULL)
461 return false;
462
7466f4cc 463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
3c537889
AD		 464
465 if (!drm_edid_is_valid(edid)) {
466 kfree(edid);
467 return false;
468 }
469
470 rdev->mode_info.bios_hardcoded_edid = edid;
471 return true;
472}
473
474struct edid *
475radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
476{
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
479 return NULL;
480}
481
6a93cb25 482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
179e8078
AD		 483 enum radeon_combios_ddc ddc,
484 u32 clk_mask,
485 u32 data_mask)
771fe6b9
JG		 486{
487 struct radeon_i2c_bus_rec i2c;
179e8078
AD		 488 int ddc_line = 0;
489
490 /* ddc id = mask reg
491 * DDC_NONE_DETECTED = none
492 * DDC_DVI = RADEON_GPIO_DVI_DDC
493 * DDC_VGA = RADEON_GPIO_VGA_DDC
494 * DDC_LCD = RADEON_GPIOPAD_MASK
495 * DDC_GPIO = RADEON_MDGPIO_MASK
496 * r1xx/r2xx
497 * DDC_MONID = RADEON_GPIO_MONID
498 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
499 * r3xx
500 * DDC_MONID = RADEON_GPIO_MONID
501 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
502 * rs3xx/rs4xx
503 * DDC_MONID = RADEON_GPIOPAD_MASK
504 * DDC_CRT2 = RADEON_GPIO_MONID
505 */
506 switch (ddc) {
507 case DDC_NONE_DETECTED:
508 default:
509 ddc_line = 0;
510 break;
511 case DDC_DVI:
512 ddc_line = RADEON_GPIO_DVI_DDC;
513 break;
514 case DDC_VGA:
515 ddc_line = RADEON_GPIO_VGA_DDC;
516 break;
517 case DDC_LCD:
518 ddc_line = RADEON_GPIOPAD_MASK;
519 break;
520 case DDC_GPIO:
521 ddc_line = RADEON_MDGPIO_MASK;
522 break;
523 case DDC_MONID:
524 if (rdev->family == CHIP_RS300 ||
525 rdev->family == CHIP_RS400 ||
526 rdev->family == CHIP_RS480)
527 ddc_line = RADEON_GPIOPAD_MASK;
528 else
529 ddc_line = RADEON_GPIO_MONID;
530 break;
531 case DDC_CRT2:
532 if (rdev->family == CHIP_RS300 ||
533 rdev->family == CHIP_RS400 ||
534 rdev->family == CHIP_RS480)
535 ddc_line = RADEON_GPIO_MONID;
536 else if (rdev->family >= CHIP_R300) {
537 ddc_line = RADEON_GPIO_DVI_DDC;
538 ddc = DDC_DVI;
539 } else
540 ddc_line = RADEON_GPIO_CRT2_DDC;
541 break;
542 }
771fe6b9 543
6a93cb25
AD		 544 if (ddc_line == RADEON_GPIOPAD_MASK) {
545 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
546 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
547 i2c.a_clk_reg = RADEON_GPIOPAD_A;
548 i2c.a_data_reg = RADEON_GPIOPAD_A;
549 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
550 i2c.en_data_reg = RADEON_GPIOPAD_EN;
551 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
552 i2c.y_data_reg = RADEON_GPIOPAD_Y;
553 } else if (ddc_line == RADEON_MDGPIO_MASK) {
554 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
555 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
556 i2c.a_clk_reg = RADEON_MDGPIO_A;
557 i2c.a_data_reg = RADEON_MDGPIO_A;
558 i2c.en_clk_reg = RADEON_MDGPIO_EN;
559 i2c.en_data_reg = RADEON_MDGPIO_EN;
560 i2c.y_clk_reg = RADEON_MDGPIO_Y;
561 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9
JG		 562 } else {
563 i2c.mask_clk_reg = ddc_line;
564 i2c.mask_data_reg = ddc_line;
565 i2c.a_clk_reg = ddc_line;
566 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 567 i2c.en_clk_reg = ddc_line;
568 i2c.en_data_reg = ddc_line;
569 i2c.y_clk_reg = ddc_line;
570 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 571 }
572
179e8078
AD		 573 if (clk_mask && data_mask) {
574 i2c.mask_clk_mask = clk_mask;
575 i2c.mask_data_mask = data_mask;
576 i2c.a_clk_mask = clk_mask;
577 i2c.a_data_mask = data_mask;
578 i2c.en_clk_mask = clk_mask;
579 i2c.en_data_mask = data_mask;
580 i2c.y_clk_mask = clk_mask;
581 i2c.y_data_mask = data_mask;
582 } else {
583 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
584 i2c.mask_data_mask = RADEON_GPIO_EN_0;
585 i2c.a_clk_mask = RADEON_GPIO_A_1;
586 i2c.a_data_mask = RADEON_GPIO_A_0;
587 i2c.en_clk_mask = RADEON_GPIO_EN_1;
588 i2c.en_data_mask = RADEON_GPIO_EN_0;
589 i2c.y_clk_mask = RADEON_GPIO_Y_1;
590 i2c.y_data_mask = RADEON_GPIO_Y_0;
591 }
592
40bacf16
AD		 593 switch (rdev->family) {
594 case CHIP_R100:
595 case CHIP_RV100:
596 case CHIP_RS100:
597 case CHIP_RV200:
598 case CHIP_RS200:
599 case CHIP_RS300:
600 switch (ddc_line) {
601 case RADEON_GPIO_DVI_DDC:
b28ea411 602 i2c.hw_capable = true;
40bacf16
AD		 603 break;
604 default:
605 i2c.hw_capable = false;
606 break;
607 }
608 break;
609 case CHIP_R200:
610 switch (ddc_line) {
611 case RADEON_GPIO_DVI_DDC:
612 case RADEON_GPIO_MONID:
613 i2c.hw_capable = true;
614 break;
615 default:
616 i2c.hw_capable = false;
617 break;
618 }
619 break;
620 case CHIP_RV250:
621 case CHIP_RV280:
622 switch (ddc_line) {
623 case RADEON_GPIO_VGA_DDC:
624 case RADEON_GPIO_DVI_DDC:
625 case RADEON_GPIO_CRT2_DDC:
626 i2c.hw_capable = true;
627 break;
628 default:
629 i2c.hw_capable = false;
630 break;
631 }
632 break;
633 case CHIP_R300:
634 case CHIP_R350:
635 switch (ddc_line) {
636 case RADEON_GPIO_VGA_DDC:
637 case RADEON_GPIO_DVI_DDC:
638 i2c.hw_capable = true;
639 break;
640 default:
641 i2c.hw_capable = false;
642 break;
643 }
644 break;
645 case CHIP_RV350:
646 case CHIP_RV380:
647 case CHIP_RS400:
648 case CHIP_RS480:
6a93cb25
AD		 649 switch (ddc_line) {
650 case RADEON_GPIO_VGA_DDC:
651 case RADEON_GPIO_DVI_DDC:
652 i2c.hw_capable = true;
653 break;
654 case RADEON_GPIO_MONID:
655 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
656 * reliably on some pre-r4xx hardware; not sure why.
657 */
658 i2c.hw_capable = false;
659 break;
660 default:
661 i2c.hw_capable = false;
662 break;
663 }
40bacf16
AD		 664 break;
665 default:
666 i2c.hw_capable = false;
667 break;
6a93cb25
AD		 668 }
669 i2c.mm_i2c = false;
f376b94f 670
179e8078 671 i2c.i2c_id = ddc;
8e36ed00 672 i2c.hpd = RADEON_HPD_NONE;
6a93cb25 673
771fe6b9
JG		 674 if (ddc_line)
675 i2c.valid = true;
676 else
677 i2c.valid = false;
678
679 return i2c;
680}
681
f376b94f
AD		 682void radeon_combios_i2c_init(struct radeon_device *rdev)
683{
684 struct drm_device *dev = rdev->ddev;
685 struct radeon_i2c_bus_rec i2c;
686
f376b94f 687
179e8078
AD		 688 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
689 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
f376b94f 690
179e8078
AD		 691 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
692 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
f376b94f
AD		 693
694 i2c.valid = true;
695 i2c.hw_capable = true;
696 i2c.mm_i2c = true;
179e8078
AD		 697 i2c.i2c_id = 0xa0;
698 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
699
700 if (rdev->family == CHIP_RS300 ||
701 rdev->family == CHIP_RS400 ||
702 rdev->family == CHIP_RS480) {
703 u16 offset;
704 u8 id, blocks, clk, data;
705 int i;
706
707 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
708 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
709
710 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
711 if (offset) {
712 blocks = RBIOS8(offset + 2);
713 for (i = 0; i < blocks; i++) {
714 id = RBIOS8(offset + 3 + (i * 5) + 0);
715 if (id == 136) {
716 clk = RBIOS8(offset + 3 + (i * 5) + 3);
717 data = RBIOS8(offset + 3 + (i * 5) + 4);
718 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
719 clk, data);
720 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
721 break;
722 }
723 }
724 }
725
726 } else if (rdev->family >= CHIP_R300) {
727 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
728 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
729 } else {
730 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
731 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
732
733 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
734 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
735 }
f376b94f
AD		 736}
737
771fe6b9
JG		 738bool radeon_combios_get_clock_info(struct drm_device *dev)
739{
740 struct radeon_device *rdev = dev->dev_private;
741 uint16_t pll_info;
742 struct radeon_pll *p1pll = &rdev->clock.p1pll;
743 struct radeon_pll *p2pll = &rdev->clock.p2pll;
744 struct radeon_pll *spll = &rdev->clock.spll;
745 struct radeon_pll *mpll = &rdev->clock.mpll;
746 int8_t rev;
747 uint16_t sclk, mclk;
748
771fe6b9
JG		 749 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
750 if (pll_info) {
751 rev = RBIOS8(pll_info);
752
753 /* pixel clocks */
754 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
755 p1pll->reference_div = RBIOS16(pll_info + 0x10);
756 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
757 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
86cb2bbf
AD		 758 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
759 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
771fe6b9
JG		 760
761 if (rev > 9) {
762 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
763 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
764 } else {
765 p1pll->pll_in_min = 40;
766 p1pll->pll_in_max = 500;
767 }
768 *p2pll = *p1pll;
769
770 /* system clock */
771 spll->reference_freq = RBIOS16(pll_info + 0x1a);
772 spll->reference_div = RBIOS16(pll_info + 0x1c);
773 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
774 spll->pll_out_max = RBIOS32(pll_info + 0x22);
775
776 if (rev > 10) {
777 spll->pll_in_min = RBIOS32(pll_info + 0x48);
778 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
779 } else {
780 /* ??? */
781 spll->pll_in_min = 40;
782 spll->pll_in_max = 500;
783 }
784
785 /* memory clock */
786 mpll->reference_freq = RBIOS16(pll_info + 0x26);
787 mpll->reference_div = RBIOS16(pll_info + 0x28);
788 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
789 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
790
791 if (rev > 10) {
792 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
793 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
794 } else {
795 /* ??? */
796 mpll->pll_in_min = 40;
797 mpll->pll_in_max = 500;
798 }
799
800 /* default sclk/mclk */
801 sclk = RBIOS16(pll_info + 0xa);
802 mclk = RBIOS16(pll_info + 0x8);
803 if (sclk == 0)
804 sclk = 200 * 100;
805 if (mclk == 0)
806 mclk = 200 * 100;
807
808 rdev->clock.default_sclk = sclk;
809 rdev->clock.default_mclk = mclk;
810
811 return true;
812 }
813 return false;
814}
815
06b6476d
AD		 816bool radeon_combios_sideport_present(struct radeon_device *rdev)
817{
818 struct drm_device *dev = rdev->ddev;
819 u16 igp_info;
820
4c70b2ea
AD		 821 /* sideport is AMD only */
822 if (rdev->family == CHIP_RS400)
823 return false;
824
06b6476d
AD		 825 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
826
827 if (igp_info) {
828 if (RBIOS16(igp_info + 0x4))
829 return true;
830 }
831 return false;
832}
833
246263cc
AD		 834static const uint32_t default_primarydac_adj[CHIP_LAST] = {
835 0x00000808, /* r100 */
836 0x00000808, /* rv100 */
837 0x00000808, /* rs100 */
838 0x00000808, /* rv200 */
839 0x00000808, /* rs200 */
840 0x00000808, /* r200 */
841 0x00000808, /* rv250 */
842 0x00000000, /* rs300 */
843 0x00000808, /* rv280 */
844 0x00000808, /* r300 */
845 0x00000808, /* r350 */
846 0x00000808, /* rv350 */
847 0x00000808, /* rv380 */
848 0x00000808, /* r420 */
849 0x00000808, /* r423 */
850 0x00000808, /* rv410 */
851 0x00000000, /* rs400 */
852 0x00000000, /* rs480 */
853};
854
855static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
856 struct radeon_encoder_primary_dac *p_dac)
857{
858 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
859 return;
860}
861
771fe6b9
JG		 862struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
863 radeon_encoder
864 *encoder)
865{
866 struct drm_device *dev = encoder->base.dev;
867 struct radeon_device *rdev = dev->dev_private;
868 uint16_t dac_info;
869 uint8_t rev, bg, dac;
870 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 871 int found = 0;
771fe6b9 872
246263cc
AD		 873 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
874 GFP_KERNEL);
875
876 if (!p_dac)
771fe6b9
JG		 877 return NULL;
878
879 /* check CRT table */
880 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
881 if (dac_info) {
771fe6b9
JG		 882 rev = RBIOS8(dac_info) & 0x3;
883 if (rev < 2) {
884 bg = RBIOS8(dac_info + 0x2) & 0xf;
885 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
886 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
887 } else {
888 bg = RBIOS8(dac_info + 0x2) & 0xf;
889 dac = RBIOS8(dac_info + 0x3) & 0xf;
890 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
891 }
3a89b4a9
AD		 892 /* if the values are all zeros, use the table */
893 if (p_dac->ps2_pdac_adj)
894 found = 1;
771fe6b9
JG		 895 }
896
246263cc
AD		 897 if (!found) /* fallback to defaults */
898 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
899
771fe6b9
JG		 900 return p_dac;
901}
902
d79766fa
AD		 903enum radeon_tv_std
904radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 905{
d79766fa 906 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 907 uint16_t tv_info;
908 enum radeon_tv_std tv_std = TV_STD_NTSC;
909
910 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
911 if (tv_info) {
912 if (RBIOS8(tv_info + 6) == 'T') {
913 switch (RBIOS8(tv_info + 7) & 0xf) {
914 case 1:
915 tv_std = TV_STD_NTSC;
916 DRM_INFO("Default TV standard: NTSC\n");
917 break;
918 case 2:
919 tv_std = TV_STD_PAL;
920 DRM_INFO("Default TV standard: PAL\n");
921 break;
922 case 3:
923 tv_std = TV_STD_PAL_M;
924 DRM_INFO("Default TV standard: PAL-M\n");
925 break;
926 case 4:
927 tv_std = TV_STD_PAL_60;
928 DRM_INFO("Default TV standard: PAL-60\n");
929 break;
930 case 5:
931 tv_std = TV_STD_NTSC_J;
932 DRM_INFO("Default TV standard: NTSC-J\n");
933 break;
934 case 6:
935 tv_std = TV_STD_SCART_PAL;
936 DRM_INFO("Default TV standard: SCART-PAL\n");
937 break;
938 default:
939 tv_std = TV_STD_NTSC;
940 DRM_INFO
941 ("Unknown TV standard; defaulting to NTSC\n");
942 break;
943 }
944
945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
946 case 0:
947 DRM_INFO("29.498928713 MHz TV ref clk\n");
948 break;
949 case 1:
950 DRM_INFO("28.636360000 MHz TV ref clk\n");
951 break;
952 case 2:
953 DRM_INFO("14.318180000 MHz TV ref clk\n");
954 break;
955 case 3:
956 DRM_INFO("27.000000000 MHz TV ref clk\n");
957 break;
958 default:
959 break;
960 }
961 }
962 }
963 return tv_std;
964}
965
966static const uint32_t default_tvdac_adj[CHIP_LAST] = {
967 0x00000000, /* r100 */
968 0x00280000, /* rv100 */
969 0x00000000, /* rs100 */
970 0x00880000, /* rv200 */
971 0x00000000, /* rs200 */
972 0x00000000, /* r200 */
973 0x00770000, /* rv250 */
974 0x00290000, /* rs300 */
975 0x00560000, /* rv280 */
976 0x00780000, /* r300 */
977 0x00770000, /* r350 */
978 0x00780000, /* rv350 */
979 0x00780000, /* rv380 */
980 0x01080000, /* r420 */
981 0x01080000, /* r423 */
982 0x01080000, /* rv410 */
983 0x00780000, /* rs400 */
984 0x00780000, /* rs480 */
985};
986
6a719e05
DA		 987static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
988 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 989{
771fe6b9
JG		 990 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
991 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
992 tv_dac->ps2_tvdac_adj = 0x00880000;
993 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
994 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 995 return;
771fe6b9
JG		 996}
997
998struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
999 radeon_encoder
1000 *encoder)
1001{
1002 struct drm_device *dev = encoder->base.dev;
1003 struct radeon_device *rdev = dev->dev_private;
1004 uint16_t dac_info;
1005 uint8_t rev, bg, dac;
1006 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 1007 int found = 0;
1008
1009 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1010 if (!tv_dac)
1011 return NULL;
771fe6b9 1012
771fe6b9
JG		 1013 /* first check TV table */
1014 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1015 if (dac_info) {
771fe6b9
JG		 1016 rev = RBIOS8(dac_info + 0x3);
1017 if (rev > 4) {
1018 bg = RBIOS8(dac_info + 0xc) & 0xf;
1019 dac = RBIOS8(dac_info + 0xd) & 0xf;
1020 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1021
1022 bg = RBIOS8(dac_info + 0xe) & 0xf;
1023 dac = RBIOS8(dac_info + 0xf) & 0xf;
1024 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1025
1026 bg = RBIOS8(dac_info + 0x10) & 0xf;
1027 dac = RBIOS8(dac_info + 0x11) & 0xf;
1028 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1029 /* if the values are all zeros, use the table */
1030 if (tv_dac->ps2_tvdac_adj)
1031 found = 1;
771fe6b9
JG		 1032 } else if (rev > 1) {
1033 bg = RBIOS8(dac_info + 0xc) & 0xf;
1034 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1035 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1036
1037 bg = RBIOS8(dac_info + 0xd) & 0xf;
1038 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1039 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1040
1041 bg = RBIOS8(dac_info + 0xe) & 0xf;
1042 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1043 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1044 /* if the values are all zeros, use the table */
1045 if (tv_dac->ps2_tvdac_adj)
1046 found = 1;
771fe6b9 1047 }
d79766fa 1048 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 1049 }
1050 if (!found) {
771fe6b9
JG		 1051 /* then check CRT table */
1052 dac_info =
1053 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1054 if (dac_info) {
771fe6b9
JG		 1055 rev = RBIOS8(dac_info) & 0x3;
1056 if (rev < 2) {
1057 bg = RBIOS8(dac_info + 0x3) & 0xf;
1058 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1059 tv_dac->ps2_tvdac_adj =
1060 (bg << 16) | (dac << 20);
1061 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1062 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1063 /* if the values are all zeros, use the table */
1064 if (tv_dac->ps2_tvdac_adj)
1065 found = 1;
771fe6b9
JG		 1066 } else {
1067 bg = RBIOS8(dac_info + 0x4) & 0xf;
1068 dac = RBIOS8(dac_info + 0x5) & 0xf;
1069 tv_dac->ps2_tvdac_adj =
1070 (bg << 16) | (dac << 20);
1071 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1072 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1073 /* if the values are all zeros, use the table */
1074 if (tv_dac->ps2_tvdac_adj)
1075 found = 1;
771fe6b9 1076 }
6fe7ac3f
AD		 1077 } else {
1078 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 1079 }
1080 }
1081
6a719e05
DA		 1082 if (!found) /* fallback to defaults */
1083 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1084
771fe6b9
JG		 1085 return tv_dac;
1086}
1087
1088static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1089 radeon_device
1090 *rdev)
1091{
1092 struct radeon_encoder_lvds *lvds = NULL;
1093 uint32_t fp_vert_stretch, fp_horz_stretch;
1094 uint32_t ppll_div_sel, ppll_val;
8b5c7444 1095 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 1096
1097 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1098
1099 if (!lvds)
1100 return NULL;
1101
1102 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1103 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1104
8b5c7444
MD		 1105 /* These should be fail-safe defaults, fingers crossed */
1106 lvds->panel_pwr_delay = 200;
1107 lvds->panel_vcc_delay = 2000;
1108
1109 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1110 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1111 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1112
771fe6b9 1113 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 1114 lvds->native_mode.vdisplay =
771fe6b9
JG		 1115 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1116 RADEON_VERT_PANEL_SHIFT) + 1;
1117 else
de2103e4 1118 lvds->native_mode.vdisplay =
771fe6b9
JG		 1119 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1120
1121 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 1122 lvds->native_mode.hdisplay =
771fe6b9
JG		 1123 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1124 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1125 else
de2103e4 1126 lvds->native_mode.hdisplay =
771fe6b9
JG		 1127 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1128
de2103e4
AD		 1129 if ((lvds->native_mode.hdisplay < 640) ||
1130 (lvds->native_mode.vdisplay < 480)) {
1131 lvds->native_mode.hdisplay = 640;
1132 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 1133 }
1134
1135 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1136 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1137 if ((ppll_val & 0x000707ff) == 0x1bb)
1138 lvds->use_bios_dividers = false;
1139 else {
1140 lvds->panel_ref_divider =
1141 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1142 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1143 lvds->panel_fb_divider = ppll_val & 0x7ff;
1144
1145 if ((lvds->panel_ref_divider != 0) &&
1146 (lvds->panel_fb_divider > 3))
1147 lvds->use_bios_dividers = true;
1148 }
1149 lvds->panel_vcc_delay = 200;
1150
1151 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1152 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1153 lvds->native_mode.vdisplay);
771fe6b9
JG		 1154
1155 return lvds;
1156}
1157
1158struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1159 *encoder)
1160{
1161 struct drm_device *dev = encoder->base.dev;
1162 struct radeon_device *rdev = dev->dev_private;
1163 uint16_t lcd_info;
1164 uint32_t panel_setup;
1165 char stmp[30];
1166 int tmp, i;
1167 struct radeon_encoder_lvds *lvds = NULL;
1168
771fe6b9
JG		 1169 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1170
1171 if (lcd_info) {
1172 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1173
1174 if (!lvds)
1175 return NULL;
1176
1177 for (i = 0; i < 24; i++)
1178 stmp[i] = RBIOS8(lcd_info + i + 1);
1179 stmp[24] = 0;
1180
1181 DRM_INFO("Panel ID String: %s\n", stmp);
1182
de2103e4
AD		 1183 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1184 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1185
de2103e4
AD		 1186 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1187 lvds->native_mode.vdisplay);
771fe6b9
JG		 1188
1189 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1190 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1191
1192 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1193 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1194 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1195
1196 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1197 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1198 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1199 if ((lvds->panel_ref_divider != 0) &&
1200 (lvds->panel_fb_divider > 3))
1201 lvds->use_bios_dividers = true;
1202
1203 panel_setup = RBIOS32(lcd_info + 0x39);
1204 lvds->lvds_gen_cntl = 0xff00;
1205 if (panel_setup & 0x1)
1206 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1207
1208 if ((panel_setup >> 4) & 0x1)
1209 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1210
1211 switch ((panel_setup >> 8) & 0x7) {
1212 case 0:
1213 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1214 break;
1215 case 1:
1216 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1217 break;
1218 case 2:
1219 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1220 break;
1221 default:
1222 break;
1223 }
1224
1225 if ((panel_setup >> 16) & 0x1)
1226 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1227
1228 if ((panel_setup >> 17) & 0x1)
1229 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1230
1231 if ((panel_setup >> 18) & 0x1)
1232 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1233
1234 if ((panel_setup >> 23) & 0x1)
1235 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1236
1237 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1238
1239 for (i = 0; i < 32; i++) {
1240 tmp = RBIOS16(lcd_info + 64 + i * 2);
1241 if (tmp == 0)
1242 break;
1243
de2103e4 1244 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
68b61a7f
AD		 1245 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1246 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1247 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1248 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1249 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1250 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1251 (RBIOS8(tmp + 23) * 8);
1252
1253 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1254 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1255 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1256 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1257 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1258 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
de2103e4
AD		 1259
1260 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1261 lvds->native_mode.flags = 0;
de2103e4
AD		 1262 /* set crtc values */
1263 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1264
771fe6b9
JG		 1265 }
1266 }
6fe7ac3f 1267 } else {
771fe6b9 1268 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1269 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1270 }
03047cdf 1271
8dfaa8a7
MD		 1272 if (lvds)
1273 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1274 return lvds;
1275}
1276
1277static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1278 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1279 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1280 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1281 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1282 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1283 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1284 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1285 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1286 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1287 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1288 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1289 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1290 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1291 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1292 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1293 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1294 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1295 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1296};
1297
445282db
DA		 1298bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1299 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1300{
445282db
DA		 1301 struct drm_device *dev = encoder->base.dev;
1302 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1303 int i;
771fe6b9
JG		 1304
1305 for (i = 0; i < 4; i++) {
1306 tmds->tmds_pll[i].value =
445282db 1307 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1308 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1309 }
1310
445282db 1311 return true;
771fe6b9
JG		 1312}
1313
445282db
DA		 1314bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1315 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1316{
1317 struct drm_device *dev = encoder->base.dev;
1318 struct radeon_device *rdev = dev->dev_private;
1319 uint16_t tmds_info;
1320 int i, n;
1321 uint8_t ver;
771fe6b9 1322
771fe6b9
JG		 1323 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1324
1325 if (tmds_info) {
771fe6b9
JG		 1326 ver = RBIOS8(tmds_info);
1327 DRM_INFO("DFP table revision: %d\n", ver);
1328 if (ver == 3) {
1329 n = RBIOS8(tmds_info + 5) + 1;
1330 if (n > 4)
1331 n = 4;
1332 for (i = 0; i < n; i++) {
1333 tmds->tmds_pll[i].value =
1334 RBIOS32(tmds_info + i * 10 + 0x08);
1335 tmds->tmds_pll[i].freq =
1336 RBIOS16(tmds_info + i * 10 + 0x10);
d9fdaafb 1337 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1338 tmds->tmds_pll[i].freq,
1339 tmds->tmds_pll[i].value);
1340 }
1341 } else if (ver == 4) {
1342 int stride = 0;
1343 n = RBIOS8(tmds_info + 5) + 1;
1344 if (n > 4)
1345 n = 4;
1346 for (i = 0; i < n; i++) {
1347 tmds->tmds_pll[i].value =
1348 RBIOS32(tmds_info + stride + 0x08);
1349 tmds->tmds_pll[i].freq =
1350 RBIOS16(tmds_info + stride + 0x10);
1351 if (i == 0)
1352 stride += 10;
1353 else
1354 stride += 6;
d9fdaafb 1355 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1356 tmds->tmds_pll[i].freq,
1357 tmds->tmds_pll[i].value);
1358 }
1359 }
fcec570b 1360 } else {
771fe6b9 1361 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1362 return false;
1363 }
445282db
DA		 1364 return true;
1365}
1366
fcec570b
AD		 1367bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1368 struct radeon_encoder_ext_tmds *tmds)
445282db 1369{
fcec570b
AD		 1370 struct drm_device *dev = encoder->base.dev;
1371 struct radeon_device *rdev = dev->dev_private;
1372 struct radeon_i2c_bus_rec i2c_bus;
445282db 1373
fcec570b 1374 /* default for macs */
179e8078 1375 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
f376b94f 1376 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
445282db 1377
fcec570b
AD		 1378 /* XXX some macs have duallink chips */
1379 switch (rdev->mode_info.connector_table) {
1380 case CT_POWERBOOK_EXTERNAL:
1381 case CT_MINI_EXTERNAL:
1382 default:
1383 tmds->dvo_chip = DVO_SIL164;
1384 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1385 break;
1386 }
445282db 1387
fcec570b 1388 return true;
771fe6b9
JG		 1389}
1390
fcec570b
AD		 1391bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1392 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1393{
1394 struct drm_device *dev = encoder->base.dev;
1395 struct radeon_device *rdev = dev->dev_private;
fcec570b 1396 uint16_t offset;
179e8078 1397 uint8_t ver;
fcec570b
AD		 1398 enum radeon_combios_ddc gpio;
1399 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1400
fcec570b
AD		 1401 tmds->i2c_bus = NULL;
1402 if (rdev->flags & RADEON_IS_IGP) {
179e8078
AD		 1403 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1404 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1405 tmds->dvo_chip = DVO_SIL164;
1406 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
fcec570b
AD		 1407 } else {
1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1409 if (offset) {
1410 ver = RBIOS8(offset);
1411 DRM_INFO("External TMDS Table revision: %d\n", ver);
1412 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1413 tmds->slave_addr >>= 1; /* 7 bit addressing */
1414 gpio = RBIOS8(offset + 4 + 3);
179e8078
AD		 1415 if (gpio == DDC_LCD) {
1416 /* MM i2c */
40bacf16
AD		 1417 i2c_bus.valid = true;
1418 i2c_bus.hw_capable = true;
1419 i2c_bus.mm_i2c = true;
179e8078
AD		 1420 i2c_bus.i2c_id = 0xa0;
1421 } else
1422 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1423 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
fcec570b 1424 }
771fe6b9 1425 }
fcec570b
AD		 1426
1427 if (!tmds->i2c_bus) {
1428 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1429 return false;
1430 }
1431
1432 return true;
771fe6b9
JG		 1433}
1434
1435bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1436{
1437 struct radeon_device *rdev = dev->dev_private;
1438 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1439 struct radeon_hpd hpd;
771fe6b9
JG		 1440
1441 rdev->mode_info.connector_table = radeon_connector_table;
1442 if (rdev->mode_info.connector_table == CT_NONE) {
1443#ifdef CONFIG_PPC_PMAC
71a157e8 1444 if (of_machine_is_compatible("PowerBook3,3")) {
771fe6b9
JG		 1445 /* powerbook with VGA */
1446 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
71a157e8
GL		 1447 } else if (of_machine_is_compatible("PowerBook3,4") ||
1448 of_machine_is_compatible("PowerBook3,5")) {
771fe6b9
JG		 1449 /* powerbook with internal tmds */
1450 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
71a157e8
GL		 1451 } else if (of_machine_is_compatible("PowerBook5,1") ||
1452 of_machine_is_compatible("PowerBook5,2") ||
1453 of_machine_is_compatible("PowerBook5,3") ||
1454 of_machine_is_compatible("PowerBook5,4") ||
1455 of_machine_is_compatible("PowerBook5,5")) {
771fe6b9
JG		 1456 /* powerbook with external single link tmds (sil164) */
1457 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8 1458 } else if (of_machine_is_compatible("PowerBook5,6")) {
771fe6b9
JG		 1459 /* powerbook with external dual or single link tmds */
1460 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1461 } else if (of_machine_is_compatible("PowerBook5,7") ||
1462 of_machine_is_compatible("PowerBook5,8") ||
1463 of_machine_is_compatible("PowerBook5,9")) {
771fe6b9
JG		 1464 /* PowerBook6,2 ? */
1465 /* powerbook with external dual link tmds (sil1178?) */
1466 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1467 } else if (of_machine_is_compatible("PowerBook4,1") ||
1468 of_machine_is_compatible("PowerBook4,2") ||
1469 of_machine_is_compatible("PowerBook4,3") ||
1470 of_machine_is_compatible("PowerBook6,3") ||
1471 of_machine_is_compatible("PowerBook6,5") ||
1472 of_machine_is_compatible("PowerBook6,7")) {
771fe6b9
JG		 1473 /* ibook */
1474 rdev->mode_info.connector_table = CT_IBOOK;
71a157e8 1475 } else if (of_machine_is_compatible("PowerMac4,4")) {
771fe6b9
JG		 1476 /* emac */
1477 rdev->mode_info.connector_table = CT_EMAC;
71a157e8 1478 } else if (of_machine_is_compatible("PowerMac10,1")) {
771fe6b9
JG		 1479 /* mini with internal tmds */
1480 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
71a157e8 1481 } else if (of_machine_is_compatible("PowerMac10,2")) {
771fe6b9
JG		 1482 /* mini with external tmds */
1483 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
71a157e8 1484 } else if (of_machine_is_compatible("PowerMac12,1")) {
771fe6b9
JG		 1485 /* PowerMac8,1 ? */
1486 /* imac g5 isight */
1487 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1488 } else
1489#endif /* CONFIG_PPC_PMAC */
76a7142a
DA		 1490#ifdef CONFIG_PPC64
1491 if (ASIC_IS_RN50(rdev))
1492 rdev->mode_info.connector_table = CT_RN50_POWER;
1493 else
1494#endif
771fe6b9
JG		 1495 rdev->mode_info.connector_table = CT_GENERIC;
1496 }
1497
1498 switch (rdev->mode_info.connector_table) {
1499 case CT_GENERIC:
1500 DRM_INFO("Connector Table: %d (generic)\n",
1501 rdev->mode_info.connector_table);
1502 /* these are the most common settings */
1503 if (rdev->flags & RADEON_SINGLE_CRTC) {
1504 /* VGA - primary dac */
179e8078 1505 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1506 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1507 radeon_add_legacy_encoder(dev,
5137ee94 1508 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1509 ATOM_DEVICE_CRT1_SUPPORT,
1510 1),
1511 ATOM_DEVICE_CRT1_SUPPORT);
1512 radeon_add_legacy_connector(dev, 0,
1513 ATOM_DEVICE_CRT1_SUPPORT,
1514 DRM_MODE_CONNECTOR_VGA,
b75fad06 1515 &ddc_i2c,
eed45b30
AD		 1516 CONNECTOR_OBJECT_ID_VGA,
1517 &hpd);
771fe6b9
JG		 1518 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1519 /* LVDS */
179e8078 1520 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
eed45b30 1521 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1522 radeon_add_legacy_encoder(dev,
5137ee94 1523 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1524 ATOM_DEVICE_LCD1_SUPPORT,
1525 0),
1526 ATOM_DEVICE_LCD1_SUPPORT);
1527 radeon_add_legacy_connector(dev, 0,
1528 ATOM_DEVICE_LCD1_SUPPORT,
1529 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1530 &ddc_i2c,
eed45b30
AD		 1531 CONNECTOR_OBJECT_ID_LVDS,
1532 &hpd);
771fe6b9
JG		 1533
1534 /* VGA - primary dac */
179e8078 1535 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1536 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1537 radeon_add_legacy_encoder(dev,
5137ee94 1538 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1539 ATOM_DEVICE_CRT1_SUPPORT,
1540 1),
1541 ATOM_DEVICE_CRT1_SUPPORT);
1542 radeon_add_legacy_connector(dev, 1,
1543 ATOM_DEVICE_CRT1_SUPPORT,
1544 DRM_MODE_CONNECTOR_VGA,
b75fad06 1545 &ddc_i2c,
eed45b30
AD		 1546 CONNECTOR_OBJECT_ID_VGA,
1547 &hpd);
771fe6b9
JG		 1548 } else {
1549 /* DVI-I - tv dac, int tmds */
179e8078 1550 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1551 hpd.hpd = RADEON_HPD_1;
771fe6b9 1552 radeon_add_legacy_encoder(dev,
5137ee94 1553 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1554 ATOM_DEVICE_DFP1_SUPPORT,
1555 0),
1556 ATOM_DEVICE_DFP1_SUPPORT);
1557 radeon_add_legacy_encoder(dev,
5137ee94 1558 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1559 ATOM_DEVICE_CRT2_SUPPORT,
1560 2),
1561 ATOM_DEVICE_CRT2_SUPPORT);
1562 radeon_add_legacy_connector(dev, 0,
1563 ATOM_DEVICE_DFP1_SUPPORT |
1564 ATOM_DEVICE_CRT2_SUPPORT,
1565 DRM_MODE_CONNECTOR_DVII,
b75fad06 1566 &ddc_i2c,
eed45b30
AD		 1567 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1568 &hpd);
771fe6b9
JG		 1569
1570 /* VGA - primary dac */
179e8078 1571 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1572 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1573 radeon_add_legacy_encoder(dev,
5137ee94 1574 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1575 ATOM_DEVICE_CRT1_SUPPORT,
1576 1),
1577 ATOM_DEVICE_CRT1_SUPPORT);
1578 radeon_add_legacy_connector(dev, 1,
1579 ATOM_DEVICE_CRT1_SUPPORT,
1580 DRM_MODE_CONNECTOR_VGA,
b75fad06 1581 &ddc_i2c,
eed45b30
AD		 1582 CONNECTOR_OBJECT_ID_VGA,
1583 &hpd);
771fe6b9
JG		 1584 }
1585
1586 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1587 /* TV - tv dac */
eed45b30
AD		 1588 ddc_i2c.valid = false;
1589 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1590 radeon_add_legacy_encoder(dev,
5137ee94 1591 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1592 ATOM_DEVICE_TV1_SUPPORT,
1593 2),
1594 ATOM_DEVICE_TV1_SUPPORT);
1595 radeon_add_legacy_connector(dev, 2,
1596 ATOM_DEVICE_TV1_SUPPORT,
1597 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1598 &ddc_i2c,
eed45b30
AD		 1599 CONNECTOR_OBJECT_ID_SVIDEO,
1600 &hpd);
771fe6b9
JG		 1601 }
1602 break;
1603 case CT_IBOOK:
1604 DRM_INFO("Connector Table: %d (ibook)\n",
1605 rdev->mode_info.connector_table);
1606 /* LVDS */
179e8078 1607 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1608 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1609 radeon_add_legacy_encoder(dev,
5137ee94 1610 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1611 ATOM_DEVICE_LCD1_SUPPORT,
1612 0),
1613 ATOM_DEVICE_LCD1_SUPPORT);
1614 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1615 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1616 CONNECTOR_OBJECT_ID_LVDS,
1617 &hpd);
771fe6b9 1618 /* VGA - TV DAC */
179e8078 1619 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1620 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1621 radeon_add_legacy_encoder(dev,
5137ee94 1622 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1623 ATOM_DEVICE_CRT2_SUPPORT,
1624 2),
1625 ATOM_DEVICE_CRT2_SUPPORT);
1626 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1627 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1628 CONNECTOR_OBJECT_ID_VGA,
1629 &hpd);
771fe6b9 1630 /* TV - TV DAC */
eed45b30
AD		 1631 ddc_i2c.valid = false;
1632 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1633 radeon_add_legacy_encoder(dev,
5137ee94 1634 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1635 ATOM_DEVICE_TV1_SUPPORT,
1636 2),
1637 ATOM_DEVICE_TV1_SUPPORT);
1638 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1639 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1640 &ddc_i2c,
eed45b30
AD		 1641 CONNECTOR_OBJECT_ID_SVIDEO,
1642 &hpd);
771fe6b9
JG		 1643 break;
1644 case CT_POWERBOOK_EXTERNAL:
1645 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1646 rdev->mode_info.connector_table);
1647 /* LVDS */
179e8078 1648 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1649 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1650 radeon_add_legacy_encoder(dev,
5137ee94 1651 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1652 ATOM_DEVICE_LCD1_SUPPORT,
1653 0),
1654 ATOM_DEVICE_LCD1_SUPPORT);
1655 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1656 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1657 CONNECTOR_OBJECT_ID_LVDS,
1658 &hpd);
771fe6b9 1659 /* DVI-I - primary dac, ext tmds */
179e8078 1660 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1661 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1662 radeon_add_legacy_encoder(dev,
5137ee94 1663 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1664 ATOM_DEVICE_DFP2_SUPPORT,
1665 0),
1666 ATOM_DEVICE_DFP2_SUPPORT);
1667 radeon_add_legacy_encoder(dev,
5137ee94 1668 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1669 ATOM_DEVICE_CRT1_SUPPORT,
1670 1),
1671 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1672 /* XXX some are SL */
771fe6b9
JG		 1673 radeon_add_legacy_connector(dev, 1,
1674 ATOM_DEVICE_DFP2_SUPPORT |
1675 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1676 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1677 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1678 &hpd);
771fe6b9 1679 /* TV - TV DAC */
eed45b30
AD		 1680 ddc_i2c.valid = false;
1681 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1682 radeon_add_legacy_encoder(dev,
5137ee94 1683 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1684 ATOM_DEVICE_TV1_SUPPORT,
1685 2),
1686 ATOM_DEVICE_TV1_SUPPORT);
1687 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1688 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1689 &ddc_i2c,
eed45b30
AD		 1690 CONNECTOR_OBJECT_ID_SVIDEO,
1691 &hpd);
771fe6b9
JG		 1692 break;
1693 case CT_POWERBOOK_INTERNAL:
1694 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1695 rdev->mode_info.connector_table);
1696 /* LVDS */
179e8078 1697 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1698 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1699 radeon_add_legacy_encoder(dev,
5137ee94 1700 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1701 ATOM_DEVICE_LCD1_SUPPORT,
1702 0),
1703 ATOM_DEVICE_LCD1_SUPPORT);
1704 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1705 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1706 CONNECTOR_OBJECT_ID_LVDS,
1707 &hpd);
771fe6b9 1708 /* DVI-I - primary dac, int tmds */
179e8078 1709 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1710 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1711 radeon_add_legacy_encoder(dev,
5137ee94 1712 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1713 ATOM_DEVICE_DFP1_SUPPORT,
1714 0),
1715 ATOM_DEVICE_DFP1_SUPPORT);
1716 radeon_add_legacy_encoder(dev,
5137ee94 1717 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1718 ATOM_DEVICE_CRT1_SUPPORT,
1719 1),
1720 ATOM_DEVICE_CRT1_SUPPORT);
1721 radeon_add_legacy_connector(dev, 1,
1722 ATOM_DEVICE_DFP1_SUPPORT |
1723 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1724 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1725 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1726 &hpd);
771fe6b9 1727 /* TV - TV DAC */
eed45b30
AD		 1728 ddc_i2c.valid = false;
1729 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1730 radeon_add_legacy_encoder(dev,
5137ee94 1731 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1732 ATOM_DEVICE_TV1_SUPPORT,
1733 2),
1734 ATOM_DEVICE_TV1_SUPPORT);
1735 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1736 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1737 &ddc_i2c,
eed45b30
AD		 1738 CONNECTOR_OBJECT_ID_SVIDEO,
1739 &hpd);
771fe6b9
JG		 1740 break;
1741 case CT_POWERBOOK_VGA:
1742 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1743 rdev->mode_info.connector_table);
1744 /* LVDS */
179e8078 1745 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1746 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1747 radeon_add_legacy_encoder(dev,
5137ee94 1748 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1749 ATOM_DEVICE_LCD1_SUPPORT,
1750 0),
1751 ATOM_DEVICE_LCD1_SUPPORT);
1752 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1753 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1754 CONNECTOR_OBJECT_ID_LVDS,
1755 &hpd);
771fe6b9 1756 /* VGA - primary dac */
179e8078 1757 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1758 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1759 radeon_add_legacy_encoder(dev,
5137ee94 1760 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1761 ATOM_DEVICE_CRT1_SUPPORT,
1762 1),
1763 ATOM_DEVICE_CRT1_SUPPORT);
1764 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1765 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1766 CONNECTOR_OBJECT_ID_VGA,
1767 &hpd);
771fe6b9 1768 /* TV - TV DAC */
eed45b30
AD		 1769 ddc_i2c.valid = false;
1770 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1771 radeon_add_legacy_encoder(dev,
5137ee94 1772 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1773 ATOM_DEVICE_TV1_SUPPORT,
1774 2),
1775 ATOM_DEVICE_TV1_SUPPORT);
1776 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1777 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1778 &ddc_i2c,
eed45b30
AD		 1779 CONNECTOR_OBJECT_ID_SVIDEO,
1780 &hpd);
771fe6b9
JG		 1781 break;
1782 case CT_MINI_EXTERNAL:
1783 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1784 rdev->mode_info.connector_table);
1785 /* DVI-I - tv dac, ext tmds */
179e8078 1786 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1787 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1788 radeon_add_legacy_encoder(dev,
5137ee94 1789 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1790 ATOM_DEVICE_DFP2_SUPPORT,
1791 0),
1792 ATOM_DEVICE_DFP2_SUPPORT);
1793 radeon_add_legacy_encoder(dev,
5137ee94 1794 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1795 ATOM_DEVICE_CRT2_SUPPORT,
1796 2),
1797 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1798 /* XXX are any DL? */
771fe6b9
JG		 1799 radeon_add_legacy_connector(dev, 0,
1800 ATOM_DEVICE_DFP2_SUPPORT |
1801 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1802 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1803 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1804 &hpd);
771fe6b9 1805 /* TV - TV DAC */
eed45b30
AD		 1806 ddc_i2c.valid = false;
1807 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1808 radeon_add_legacy_encoder(dev,
5137ee94 1809 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1810 ATOM_DEVICE_TV1_SUPPORT,
1811 2),
1812 ATOM_DEVICE_TV1_SUPPORT);
1813 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1814 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1815 &ddc_i2c,
eed45b30
AD		 1816 CONNECTOR_OBJECT_ID_SVIDEO,
1817 &hpd);
771fe6b9
JG		 1818 break;
1819 case CT_MINI_INTERNAL:
1820 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1821 rdev->mode_info.connector_table);
1822 /* DVI-I - tv dac, int tmds */
179e8078 1823 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1824 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1825 radeon_add_legacy_encoder(dev,
5137ee94 1826 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1827 ATOM_DEVICE_DFP1_SUPPORT,
1828 0),
1829 ATOM_DEVICE_DFP1_SUPPORT);
1830 radeon_add_legacy_encoder(dev,
5137ee94 1831 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1832 ATOM_DEVICE_CRT2_SUPPORT,
1833 2),
1834 ATOM_DEVICE_CRT2_SUPPORT);
1835 radeon_add_legacy_connector(dev, 0,
1836 ATOM_DEVICE_DFP1_SUPPORT |
1837 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1838 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1839 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1840 &hpd);
771fe6b9 1841 /* TV - TV DAC */
eed45b30
AD		 1842 ddc_i2c.valid = false;
1843 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1844 radeon_add_legacy_encoder(dev,
5137ee94 1845 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1846 ATOM_DEVICE_TV1_SUPPORT,
1847 2),
1848 ATOM_DEVICE_TV1_SUPPORT);
1849 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1850 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1851 &ddc_i2c,
eed45b30
AD		 1852 CONNECTOR_OBJECT_ID_SVIDEO,
1853 &hpd);
771fe6b9
JG		 1854 break;
1855 case CT_IMAC_G5_ISIGHT:
1856 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1857 rdev->mode_info.connector_table);
1858 /* DVI-D - int tmds */
179e8078 1859 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
eed45b30 1860 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1861 radeon_add_legacy_encoder(dev,
5137ee94 1862 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1863 ATOM_DEVICE_DFP1_SUPPORT,
1864 0),
1865 ATOM_DEVICE_DFP1_SUPPORT);
1866 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1867 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1868 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1869 &hpd);
771fe6b9 1870 /* VGA - tv dac */
179e8078 1871 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1872 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1873 radeon_add_legacy_encoder(dev,
5137ee94 1874 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1875 ATOM_DEVICE_CRT2_SUPPORT,
1876 2),
1877 ATOM_DEVICE_CRT2_SUPPORT);
1878 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1879 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1880 CONNECTOR_OBJECT_ID_VGA,
1881 &hpd);
771fe6b9 1882 /* TV - TV DAC */
eed45b30
AD		 1883 ddc_i2c.valid = false;
1884 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1885 radeon_add_legacy_encoder(dev,
5137ee94 1886 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1887 ATOM_DEVICE_TV1_SUPPORT,
1888 2),
1889 ATOM_DEVICE_TV1_SUPPORT);
1890 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1891 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1892 &ddc_i2c,
eed45b30
AD		 1893 CONNECTOR_OBJECT_ID_SVIDEO,
1894 &hpd);
771fe6b9
JG		 1895 break;
1896 case CT_EMAC:
1897 DRM_INFO("Connector Table: %d (emac)\n",
1898 rdev->mode_info.connector_table);
1899 /* VGA - primary dac */
179e8078 1900 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1901 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1902 radeon_add_legacy_encoder(dev,
5137ee94 1903 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1904 ATOM_DEVICE_CRT1_SUPPORT,
1905 1),
1906 ATOM_DEVICE_CRT1_SUPPORT);
1907 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1908 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1909 CONNECTOR_OBJECT_ID_VGA,
1910 &hpd);
771fe6b9 1911 /* VGA - tv dac */
179e8078 1912 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1913 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1914 radeon_add_legacy_encoder(dev,
5137ee94 1915 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1916 ATOM_DEVICE_CRT2_SUPPORT,
1917 2),
1918 ATOM_DEVICE_CRT2_SUPPORT);
1919 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1920 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1921 CONNECTOR_OBJECT_ID_VGA,
1922 &hpd);
771fe6b9 1923 /* TV - TV DAC */
eed45b30
AD		 1924 ddc_i2c.valid = false;
1925 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1926 radeon_add_legacy_encoder(dev,
5137ee94 1927 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1928 ATOM_DEVICE_TV1_SUPPORT,
1929 2),
1930 ATOM_DEVICE_TV1_SUPPORT);
1931 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1932 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1933 &ddc_i2c,
eed45b30
AD		 1934 CONNECTOR_OBJECT_ID_SVIDEO,
1935 &hpd);
771fe6b9 1936 break;
76a7142a
DA		 1937 case CT_RN50_POWER:
1938 DRM_INFO("Connector Table: %d (rn50-power)\n",
1939 rdev->mode_info.connector_table);
1940 /* VGA - primary dac */
179e8078 1941 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
76a7142a
DA		 1942 hpd.hpd = RADEON_HPD_NONE;
1943 radeon_add_legacy_encoder(dev,
5137ee94 1944 radeon_get_encoder_enum(dev,
76a7142a
DA		 1945 ATOM_DEVICE_CRT1_SUPPORT,
1946 1),
1947 ATOM_DEVICE_CRT1_SUPPORT);
1948 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1949 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1950 CONNECTOR_OBJECT_ID_VGA,
1951 &hpd);
179e8078 1952 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
76a7142a
DA		 1953 hpd.hpd = RADEON_HPD_NONE;
1954 radeon_add_legacy_encoder(dev,
5137ee94 1955 radeon_get_encoder_enum(dev,
76a7142a
DA		 1956 ATOM_DEVICE_CRT2_SUPPORT,
1957 2),
1958 ATOM_DEVICE_CRT2_SUPPORT);
1959 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1960 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1961 CONNECTOR_OBJECT_ID_VGA,
1962 &hpd);
1963 break;
771fe6b9
JG		 1964 default:
1965 DRM_INFO("Connector table: %d (invalid)\n",
1966 rdev->mode_info.connector_table);
1967 return false;
1968 }
1969
1970 radeon_link_encoder_connector(dev);
1971
1972 return true;
1973}
1974
1975static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1976 int bios_index,
1977 enum radeon_combios_connector
1978 *legacy_connector,
eed45b30
AD		 1979 struct radeon_i2c_bus_rec *ddc_i2c,
1980 struct radeon_hpd *hpd)
771fe6b9 1981{
fcec570b 1982
771fe6b9
JG		 1983 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1984 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1985 if (dev->pdev->device == 0x515e &&
1986 dev->pdev->subsystem_vendor == 0x1014) {
1987 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1988 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1989 return false;
1990 }
1991
771fe6b9
JG		 1992 /* X300 card with extra non-existent DVI port */
1993 if (dev->pdev->device == 0x5B60 &&
1994 dev->pdev->subsystem_vendor == 0x17af &&
1995 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1996 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1997 return false;
1998 }
1999
2000 return true;
2001}
2002
790cfb34
AD		 2003static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2004{
2005 /* Acer 5102 has non-existent TV port */
2006 if (dev->pdev->device == 0x5975 &&
2007 dev->pdev->subsystem_vendor == 0x1025 &&
2008 dev->pdev->subsystem_device == 0x009f)
2009 return false;
2010
fc7f7119
AD		 2011 /* HP dc5750 has non-existent TV port */
2012 if (dev->pdev->device == 0x5974 &&
2013 dev->pdev->subsystem_vendor == 0x103c &&
2014 dev->pdev->subsystem_device == 0x280a)
2015 return false;
2016
fd874ad0
AD		 2017 /* MSI S270 has non-existent TV port */
2018 if (dev->pdev->device == 0x5955 &&
2019 dev->pdev->subsystem_vendor == 0x1462 &&
2020 dev->pdev->subsystem_device == 0x0131)
2021 return false;
2022
790cfb34
AD		 2023 return true;
2024}
2025
b75fad06
AD		 2026static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2027{
2028 struct radeon_device *rdev = dev->dev_private;
2029 uint32_t ext_tmds_info;
2030
2031 if (rdev->flags & RADEON_IS_IGP) {
2032 if (is_dvi_d)
2033 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2034 else
2035 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2036 }
2037 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2038 if (ext_tmds_info) {
2039 uint8_t rev = RBIOS8(ext_tmds_info);
2040 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2041 if (rev >= 3) {
2042 if (is_dvi_d)
2043 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2044 else
2045 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2046 } else {
2047 if (flags & 1) {
2048 if (is_dvi_d)
2049 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2050 else
2051 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2052 }
2053 }
2054 }
2055 if (is_dvi_d)
2056 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2057 else
2058 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2059}
2060
771fe6b9
JG		 2061bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2062{
2063 struct radeon_device *rdev = dev->dev_private;
2064 uint32_t conn_info, entry, devices;
b75fad06 2065 uint16_t tmp, connector_object_id;
771fe6b9
JG		 2066 enum radeon_combios_ddc ddc_type;
2067 enum radeon_combios_connector connector;
2068 int i = 0;
2069 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 2070 struct radeon_hpd hpd;
771fe6b9 2071
771fe6b9
JG		 2072 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2073 if (conn_info) {
2074 for (i = 0; i < 4; i++) {
2075 entry = conn_info + 2 + i * 2;
2076
2077 if (!RBIOS16(entry))
2078 break;
2079
2080 tmp = RBIOS16(entry);
2081
2082 connector = (tmp >> 12) & 0xf;
2083
2084 ddc_type = (tmp >> 8) & 0xf;
179e8078 2085 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9 2086
eed45b30
AD		 2087 switch (connector) {
2088 case CONNECTOR_PROPRIETARY_LEGACY:
2089 case CONNECTOR_DVI_I_LEGACY:
2090 case CONNECTOR_DVI_D_LEGACY:
2091 if ((tmp >> 4) & 0x1)
2092 hpd.hpd = RADEON_HPD_2;
2093 else
2094 hpd.hpd = RADEON_HPD_1;
2095 break;
2096 default:
2097 hpd.hpd = RADEON_HPD_NONE;
2098 break;
2099 }
2100
2d152c6b 2101 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2102 &ddc_i2c, &hpd))
2d152c6b 2103 continue;
771fe6b9
JG		 2104
2105 switch (connector) {
2106 case CONNECTOR_PROPRIETARY_LEGACY:
2107 if ((tmp >> 4) & 0x1)
2108 devices = ATOM_DEVICE_DFP2_SUPPORT;
2109 else
2110 devices = ATOM_DEVICE_DFP1_SUPPORT;
2111 radeon_add_legacy_encoder(dev,
5137ee94 2112 radeon_get_encoder_enum
771fe6b9
JG		 2113 (dev, devices, 0),
2114 devices);
2115 radeon_add_legacy_connector(dev, i, devices,
2116 legacy_connector_convert
2117 [connector],
b75fad06 2118 &ddc_i2c,
eed45b30
AD		 2119 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2120 &hpd);
771fe6b9
JG		 2121 break;
2122 case CONNECTOR_CRT_LEGACY:
2123 if (tmp & 0x1) {
2124 devices = ATOM_DEVICE_CRT2_SUPPORT;
2125 radeon_add_legacy_encoder(dev,
5137ee94 2126 radeon_get_encoder_enum
771fe6b9
JG		 2127 (dev,
2128 ATOM_DEVICE_CRT2_SUPPORT,
2129 2),
2130 ATOM_DEVICE_CRT2_SUPPORT);
2131 } else {
2132 devices = ATOM_DEVICE_CRT1_SUPPORT;
2133 radeon_add_legacy_encoder(dev,
5137ee94 2134 radeon_get_encoder_enum
771fe6b9
JG		 2135 (dev,
2136 ATOM_DEVICE_CRT1_SUPPORT,
2137 1),
2138 ATOM_DEVICE_CRT1_SUPPORT);
2139 }
2140 radeon_add_legacy_connector(dev,
2141 i,
2142 devices,
2143 legacy_connector_convert
2144 [connector],
b75fad06 2145 &ddc_i2c,
eed45b30
AD		 2146 CONNECTOR_OBJECT_ID_VGA,
2147 &hpd);
771fe6b9
JG		 2148 break;
2149 case CONNECTOR_DVI_I_LEGACY:
2150 devices = 0;
2151 if (tmp & 0x1) {
2152 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2153 radeon_add_legacy_encoder(dev,
5137ee94 2154 radeon_get_encoder_enum
771fe6b9
JG		 2155 (dev,
2156 ATOM_DEVICE_CRT2_SUPPORT,
2157 2),
2158 ATOM_DEVICE_CRT2_SUPPORT);
2159 } else {
2160 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2161 radeon_add_legacy_encoder(dev,
5137ee94 2162 radeon_get_encoder_enum
771fe6b9
JG		 2163 (dev,
2164 ATOM_DEVICE_CRT1_SUPPORT,
2165 1),
2166 ATOM_DEVICE_CRT1_SUPPORT);
2167 }
2168 if ((tmp >> 4) & 0x1) {
2169 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2170 radeon_add_legacy_encoder(dev,
5137ee94 2171 radeon_get_encoder_enum
771fe6b9
JG		 2172 (dev,
2173 ATOM_DEVICE_DFP2_SUPPORT,
2174 0),
2175 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2176 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2177 } else {
2178 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2179 radeon_add_legacy_encoder(dev,
5137ee94 2180 radeon_get_encoder_enum
771fe6b9
JG		 2181 (dev,
2182 ATOM_DEVICE_DFP1_SUPPORT,
2183 0),
2184 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2185 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2186 }
2187 radeon_add_legacy_connector(dev,
2188 i,
2189 devices,
2190 legacy_connector_convert
2191 [connector],
b75fad06 2192 &ddc_i2c,
eed45b30
AD		 2193 connector_object_id,
2194 &hpd);
771fe6b9
JG		 2195 break;
2196 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2197 if ((tmp >> 4) & 0x1) {
771fe6b9 2198 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2199 connector_object_id = combios_check_dl_dvi(dev, 1);
2200 } else {
771fe6b9 2201 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2202 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2203 }
771fe6b9 2204 radeon_add_legacy_encoder(dev,
5137ee94 2205 radeon_get_encoder_enum
771fe6b9
JG		 2206 (dev, devices, 0),
2207 devices);
2208 radeon_add_legacy_connector(dev, i, devices,
2209 legacy_connector_convert
2210 [connector],
b75fad06 2211 &ddc_i2c,
eed45b30
AD		 2212 connector_object_id,
2213 &hpd);
771fe6b9
JG		 2214 break;
2215 case CONNECTOR_CTV_LEGACY:
2216 case CONNECTOR_STV_LEGACY:
2217 radeon_add_legacy_encoder(dev,
5137ee94 2218 radeon_get_encoder_enum
771fe6b9
JG		 2219 (dev,
2220 ATOM_DEVICE_TV1_SUPPORT,
2221 2),
2222 ATOM_DEVICE_TV1_SUPPORT);
2223 radeon_add_legacy_connector(dev, i,
2224 ATOM_DEVICE_TV1_SUPPORT,
2225 legacy_connector_convert
2226 [connector],
b75fad06 2227 &ddc_i2c,
eed45b30
AD		 2228 CONNECTOR_OBJECT_ID_SVIDEO,
2229 &hpd);
771fe6b9
JG		 2230 break;
2231 default:
2232 DRM_ERROR("Unknown connector type: %d\n",
2233 connector);
2234 continue;
2235 }
2236
2237 }
2238 } else {
2239 uint16_t tmds_info =
2240 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2241 if (tmds_info) {
d9fdaafb 2242 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
771fe6b9
JG		 2243
2244 radeon_add_legacy_encoder(dev,
5137ee94 2245 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2246 ATOM_DEVICE_CRT1_SUPPORT,
2247 1),
2248 ATOM_DEVICE_CRT1_SUPPORT);
2249 radeon_add_legacy_encoder(dev,
5137ee94 2250 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2251 ATOM_DEVICE_DFP1_SUPPORT,
2252 0),
2253 ATOM_DEVICE_DFP1_SUPPORT);
2254
179e8078 2255 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
8e36ed00 2256 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 2257 radeon_add_legacy_connector(dev,
2258 0,
2259 ATOM_DEVICE_CRT1_SUPPORT |
2260 ATOM_DEVICE_DFP1_SUPPORT,
2261 DRM_MODE_CONNECTOR_DVII,
b75fad06 2262 &ddc_i2c,
eed45b30
AD		 2263 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2264 &hpd);
771fe6b9 2265 } else {
d0c403e9
AD		 2266 uint16_t crt_info =
2267 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
d9fdaafb 2268 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
d0c403e9
AD		 2269 if (crt_info) {
2270 radeon_add_legacy_encoder(dev,
5137ee94 2271 radeon_get_encoder_enum(dev,
d0c403e9
AD		 2272 ATOM_DEVICE_CRT1_SUPPORT,
2273 1),
2274 ATOM_DEVICE_CRT1_SUPPORT);
179e8078 2275 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 2276 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2277 radeon_add_legacy_connector(dev,
2278 0,
2279 ATOM_DEVICE_CRT1_SUPPORT,
2280 DRM_MODE_CONNECTOR_VGA,
b75fad06 2281 &ddc_i2c,
eed45b30
AD		 2282 CONNECTOR_OBJECT_ID_VGA,
2283 &hpd);
d0c403e9 2284 } else {
d9fdaafb 2285 DRM_DEBUG_KMS("No connector info found\n");
d0c403e9
AD		 2286 return false;
2287 }
771fe6b9
JG		 2288 }
2289 }
2290
2291 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2292 uint16_t lcd_info =
2293 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2294 if (lcd_info) {
2295 uint16_t lcd_ddc_info =
2296 combios_get_table_offset(dev,
2297 COMBIOS_LCD_DDC_INFO_TABLE);
2298
2299 radeon_add_legacy_encoder(dev,
5137ee94 2300 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2301 ATOM_DEVICE_LCD1_SUPPORT,
2302 0),
2303 ATOM_DEVICE_LCD1_SUPPORT);
2304
2305 if (lcd_ddc_info) {
2306 ddc_type = RBIOS8(lcd_ddc_info + 2);
2307 switch (ddc_type) {
771fe6b9
JG		 2308 case DDC_LCD:
2309 ddc_i2c =
179e8078
AD		 2310 combios_setup_i2c_bus(rdev,
2311 DDC_LCD,
2312 RBIOS32(lcd_ddc_info + 3),
2313 RBIOS32(lcd_ddc_info + 7));
f376b94f 2314 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2315 break;
2316 case DDC_GPIO:
2317 ddc_i2c =
179e8078
AD		 2318 combios_setup_i2c_bus(rdev,
2319 DDC_GPIO,
2320 RBIOS32(lcd_ddc_info + 3),
2321 RBIOS32(lcd_ddc_info + 7));
f376b94f 2322 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2323 break;
2324 default:
179e8078
AD		 2325 ddc_i2c =
2326 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9
JG		 2327 break;
2328 }
d9fdaafb 2329 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
771fe6b9
JG		 2330 } else
2331 ddc_i2c.valid = false;
2332
eed45b30 2333 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2334 radeon_add_legacy_connector(dev,
2335 5,
2336 ATOM_DEVICE_LCD1_SUPPORT,
2337 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2338 &ddc_i2c,
eed45b30
AD		 2339 CONNECTOR_OBJECT_ID_LVDS,
2340 &hpd);
771fe6b9
JG		 2341 }
2342 }
2343
2344 /* check TV table */
2345 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2346 uint32_t tv_info =
2347 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2348 if (tv_info) {
2349 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2350 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2351 hpd.hpd = RADEON_HPD_NONE;
d294ed69 2352 ddc_i2c.valid = false;
790cfb34 2353 radeon_add_legacy_encoder(dev,
5137ee94 2354 radeon_get_encoder_enum
790cfb34
AD		 2355 (dev,
2356 ATOM_DEVICE_TV1_SUPPORT,
2357 2),
2358 ATOM_DEVICE_TV1_SUPPORT);
2359 radeon_add_legacy_connector(dev, 6,
2360 ATOM_DEVICE_TV1_SUPPORT,
2361 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2362 &ddc_i2c,
eed45b30
AD		 2363 CONNECTOR_OBJECT_ID_SVIDEO,
2364 &hpd);
790cfb34 2365 }
771fe6b9
JG		 2366 }
2367 }
2368 }
2369
2370 radeon_link_encoder_connector(dev);
2371
2372 return true;
2373}
2374
56278a8e
AD		 2375void radeon_combios_get_power_modes(struct radeon_device *rdev)
2376{
2377 struct drm_device *dev = rdev->ddev;
2378 u16 offset, misc, misc2 = 0;
2379 u8 rev, blocks, tmp;
2380 int state_index = 0;
2381
a48b9b4e 2382 rdev->pm.default_power_state_index = -1;
56278a8e 2383
56278a8e
AD		 2384 if (rdev->flags & RADEON_IS_MOBILITY) {
2385 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2386 if (offset) {
2387 rev = RBIOS8(offset);
2388 blocks = RBIOS8(offset + 0x2);
2389 /* power mode 0 tends to be the only valid one */
2390 rdev->pm.power_state[state_index].num_clock_modes = 1;
2391 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2392 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2393 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2394 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2395 goto default_mode;
0ec0e74f
AD		 2396 rdev->pm.power_state[state_index].type =
2397 POWER_STATE_TYPE_BATTERY;
56278a8e
AD		 2398 misc = RBIOS16(offset + 0x5 + 0x0);
2399 if (rev > 4)
2400 misc2 = RBIOS16(offset + 0x5 + 0xe);
79daedc9
AD		 2401 rdev->pm.power_state[state_index].misc = misc;
2402 rdev->pm.power_state[state_index].misc2 = misc2;
56278a8e
AD		 2403 if (misc & 0x4) {
2404 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2405 if (misc & 0x8)
2406 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2407 true;
2408 else
2409 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2410 false;
2411 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2412 if (rev < 6) {
2413 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2414 RBIOS16(offset + 0x5 + 0xb) * 4;
2415 tmp = RBIOS8(offset + 0x5 + 0xd);
2416 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2417 } else {
2418 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2419 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2420 if (entries && voltage_table_offset) {
2421 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2422 RBIOS16(voltage_table_offset) * 4;
2423 tmp = RBIOS8(voltage_table_offset + 0x2);
2424 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2425 } else
2426 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2427 }
2428 switch ((misc2 & 0x700) >> 8) {
2429 case 0:
2430 default:
2431 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2432 break;
2433 case 1:
2434 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2435 break;
2436 case 2:
2437 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2438 break;
2439 case 3:
2440 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2441 break;
2442 case 4:
2443 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2444 break;
2445 }
2446 } else
2447 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2448 if (rev > 6)
79daedc9 2449 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e 2450 RBIOS8(offset + 0x5 + 0x10);
d7311171 2451 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e
AD		 2452 state_index++;
2453 } else {
2454 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2455 }
2456 } else {
2457 /* XXX figure out some good default low power mode for desktop cards */
2458 }
2459
2460default_mode:
2461 /* add the default mode */
0ec0e74f
AD		 2462 rdev->pm.power_state[state_index].type =
2463 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2464 rdev->pm.power_state[state_index].num_clock_modes = 1;
2465 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2466 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2467 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
84d88f4c 2468 if ((state_index > 0) &&
8de016e2 2469 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
84d88f4c
AD		 2470 rdev->pm.power_state[state_index].clock_info[0].voltage =
2471 rdev->pm.power_state[0].clock_info[0].voltage;
2472 else
2473 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2474 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2475 rdev->pm.power_state[state_index].flags = 0;
2476 rdev->pm.default_power_state_index = state_index;
56278a8e 2477 rdev->pm.num_power_states = state_index + 1;
9038dfdf 2478
a48b9b4e
AD		 2479 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2480 rdev->pm.current_clock_mode_index = 0;
56278a8e
AD		 2481}
2482
fcec570b
AD		 2483void radeon_external_tmds_setup(struct drm_encoder *encoder)
2484{
2485 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2486 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2487
2488 if (!tmds)
2489 return;
2490
2491 switch (tmds->dvo_chip) {
2492 case DVO_SIL164:
2493 /* sil 164 */
5a6f98f5
AD		 2494 radeon_i2c_put_byte(tmds->i2c_bus,
2495 tmds->slave_addr,
2496 0x08, 0x30);
2497 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2498 tmds->slave_addr,
2499 0x09, 0x00);
5a6f98f5
AD		 2500 radeon_i2c_put_byte(tmds->i2c_bus,
2501 tmds->slave_addr,
2502 0x0a, 0x90);
2503 radeon_i2c_put_byte(tmds->i2c_bus,
2504 tmds->slave_addr,
2505 0x0c, 0x89);
2506 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2507 tmds->slave_addr,
2508 0x08, 0x3b);
fcec570b
AD		 2509 break;
2510 case DVO_SIL1178:
2511 /* sil 1178 - untested */
2512 /*
2513 * 0x0f, 0x44
2514 * 0x0f, 0x4c
2515 * 0x0e, 0x01
2516 * 0x0a, 0x80
2517 * 0x09, 0x30
2518 * 0x0c, 0xc9
2519 * 0x0d, 0x70
2520 * 0x08, 0x32
2521 * 0x08, 0x33
2522 */
2523 break;
2524 default:
2525 break;
2526 }
2527
2528}
2529
2530bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2531{
2532 struct drm_device *dev = encoder->dev;
2533 struct radeon_device *rdev = dev->dev_private;
2534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2535 uint16_t offset;
2536 uint8_t blocks, slave_addr, rev;
2537 uint32_t index, id;
2538 uint32_t reg, val, and_mask, or_mask;
2539 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2540
fcec570b
AD		 2541 if (!tmds)
2542 return false;
2543
2544 if (rdev->flags & RADEON_IS_IGP) {
2545 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2546 rev = RBIOS8(offset);
2547 if (offset) {
2548 rev = RBIOS8(offset);
2549 if (rev > 1) {
2550 blocks = RBIOS8(offset + 3);
2551 index = offset + 4;
2552 while (blocks > 0) {
2553 id = RBIOS16(index);
2554 index += 2;
2555 switch (id >> 13) {
2556 case 0:
2557 reg = (id & 0x1fff) * 4;
2558 val = RBIOS32(index);
2559 index += 4;
2560 WREG32(reg, val);
2561 break;
2562 case 2:
2563 reg = (id & 0x1fff) * 4;
2564 and_mask = RBIOS32(index);
2565 index += 4;
2566 or_mask = RBIOS32(index);
2567 index += 4;
2568 val = RREG32(reg);
2569 val = (val & and_mask) | or_mask;
2570 WREG32(reg, val);
2571 break;
2572 case 3:
2573 val = RBIOS16(index);
2574 index += 2;
2575 udelay(val);
2576 break;
2577 case 4:
2578 val = RBIOS16(index);
2579 index += 2;
2580 udelay(val * 1000);
2581 break;
2582 case 6:
2583 slave_addr = id & 0xff;
2584 slave_addr >>= 1; /* 7 bit addressing */
2585 index++;
2586 reg = RBIOS8(index);
2587 index++;
2588 val = RBIOS8(index);
2589 index++;
5a6f98f5
AD		 2590 radeon_i2c_put_byte(tmds->i2c_bus,
2591 slave_addr,
2592 reg, val);
fcec570b
AD		 2593 break;
2594 default:
2595 DRM_ERROR("Unknown id %d\n", id >> 13);
2596 break;
2597 }
2598 blocks--;
2599 }
2600 return true;
2601 }
2602 }
2603 } else {
2604 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2605 if (offset) {
2606 index = offset + 10;
2607 id = RBIOS16(index);
2608 while (id != 0xffff) {
2609 index += 2;
2610 switch (id >> 13) {
2611 case 0:
2612 reg = (id & 0x1fff) * 4;
2613 val = RBIOS32(index);
2614 WREG32(reg, val);
2615 break;
2616 case 2:
2617 reg = (id & 0x1fff) * 4;
2618 and_mask = RBIOS32(index);
2619 index += 4;
2620 or_mask = RBIOS32(index);
2621 index += 4;
2622 val = RREG32(reg);
2623 val = (val & and_mask) | or_mask;
2624 WREG32(reg, val);
2625 break;
2626 case 4:
2627 val = RBIOS16(index);
2628 index += 2;
2629 udelay(val);
2630 break;
2631 case 5:
2632 reg = id & 0x1fff;
2633 and_mask = RBIOS32(index);
2634 index += 4;
2635 or_mask = RBIOS32(index);
2636 index += 4;
2637 val = RREG32_PLL(reg);
2638 val = (val & and_mask) | or_mask;
2639 WREG32_PLL(reg, val);
2640 break;
2641 case 6:
2642 reg = id & 0x1fff;
2643 val = RBIOS8(index);
2644 index += 1;
5a6f98f5
AD		 2645 radeon_i2c_put_byte(tmds->i2c_bus,
2646 tmds->slave_addr,
2647 reg, val);
fcec570b
AD		 2648 break;
2649 default:
2650 DRM_ERROR("Unknown id %d\n", id >> 13);
2651 break;
2652 }
2653 id = RBIOS16(index);
2654 }
2655 return true;
2656 }
2657 }
2658 return false;
2659}
2660
771fe6b9
JG		 2661static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2662{
2663 struct radeon_device *rdev = dev->dev_private;
2664
2665 if (offset) {
2666 while (RBIOS16(offset)) {
2667 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2668 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2669 uint32_t val, and_mask, or_mask;
2670 uint32_t tmp;
2671
2672 offset += 2;
2673 switch (cmd) {
2674 case 0:
2675 val = RBIOS32(offset);
2676 offset += 4;
2677 WREG32(addr, val);
2678 break;
2679 case 1:
2680 val = RBIOS32(offset);
2681 offset += 4;
2682 WREG32(addr, val);
2683 break;
2684 case 2:
2685 and_mask = RBIOS32(offset);
2686 offset += 4;
2687 or_mask = RBIOS32(offset);
2688 offset += 4;
2689 tmp = RREG32(addr);
2690 tmp &= and_mask;
2691 tmp |= or_mask;
2692 WREG32(addr, tmp);
2693 break;
2694 case 3:
2695 and_mask = RBIOS32(offset);
2696 offset += 4;
2697 or_mask = RBIOS32(offset);
2698 offset += 4;
2699 tmp = RREG32(addr);
2700 tmp &= and_mask;
2701 tmp |= or_mask;
2702 WREG32(addr, tmp);
2703 break;
2704 case 4:
2705 val = RBIOS16(offset);
2706 offset += 2;
2707 udelay(val);
2708 break;
2709 case 5:
2710 val = RBIOS16(offset);
2711 offset += 2;
2712 switch (addr) {
2713 case 8:
2714 while (val--) {
2715 if (!
2716 (RREG32_PLL
2717 (RADEON_CLK_PWRMGT_CNTL) &
2718 RADEON_MC_BUSY))
2719 break;
2720 }
2721 break;
2722 case 9:
2723 while (val--) {
2724 if ((RREG32(RADEON_MC_STATUS) &
2725 RADEON_MC_IDLE))
2726 break;
2727 }
2728 break;
2729 default:
2730 break;
2731 }
2732 break;
2733 default:
2734 break;
2735 }
2736 }
2737 }
2738}
2739
2740static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2741{
2742 struct radeon_device *rdev = dev->dev_private;
2743
2744 if (offset) {
2745 while (RBIOS8(offset)) {
2746 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2747 uint8_t addr = (RBIOS8(offset) & 0x3f);
2748 uint32_t val, shift, tmp;
2749 uint32_t and_mask, or_mask;
2750
2751 offset++;
2752 switch (cmd) {
2753 case 0:
2754 val = RBIOS32(offset);
2755 offset += 4;
2756 WREG32_PLL(addr, val);
2757 break;
2758 case 1:
2759 shift = RBIOS8(offset) * 8;
2760 offset++;
2761 and_mask = RBIOS8(offset) << shift;
2762 and_mask |= ~(0xff << shift);
2763 offset++;
2764 or_mask = RBIOS8(offset) << shift;
2765 offset++;
2766 tmp = RREG32_PLL(addr);
2767 tmp &= and_mask;
2768 tmp |= or_mask;
2769 WREG32_PLL(addr, tmp);
2770 break;
2771 case 2:
2772 case 3:
2773 tmp = 1000;
2774 switch (addr) {
2775 case 1:
2776 udelay(150);
2777 break;
2778 case 2:
2779 udelay(1000);
2780 break;
2781 case 3:
2782 while (tmp--) {
2783 if (!
2784 (RREG32_PLL
2785 (RADEON_CLK_PWRMGT_CNTL) &
2786 RADEON_MC_BUSY))
2787 break;
2788 }
2789 break;
2790 case 4:
2791 while (tmp--) {
2792 if (RREG32_PLL
2793 (RADEON_CLK_PWRMGT_CNTL) &
2794 RADEON_DLL_READY)
2795 break;
2796 }
2797 break;
2798 case 5:
2799 tmp =
2800 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2801 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2802#if 0
2803 uint32_t mclk_cntl =
2804 RREG32_PLL
2805 (RADEON_MCLK_CNTL);
2806 mclk_cntl &= 0xffff0000;
2807 /*mclk_cntl |= 0x00001111;*//* ??? */
2808 WREG32_PLL(RADEON_MCLK_CNTL,
2809 mclk_cntl);
2810 udelay(10000);
2811#endif
2812 WREG32_PLL
2813 (RADEON_CLK_PWRMGT_CNTL,
2814 tmp &
2815 ~RADEON_CG_NO1_DEBUG_0);
2816 udelay(10000);
2817 }
2818 break;
2819 default:
2820 break;
2821 }
2822 break;
2823 default:
2824 break;
2825 }
2826 }
2827 }
2828}
2829
2830static void combios_parse_ram_reset_table(struct drm_device *dev,
2831 uint16_t offset)
2832{
2833 struct radeon_device *rdev = dev->dev_private;
2834 uint32_t tmp;
2835
2836 if (offset) {
2837 uint8_t val = RBIOS8(offset);
2838 while (val != 0xff) {
2839 offset++;
2840
2841 if (val == 0x0f) {
2842 uint32_t channel_complete_mask;
2843
2844 if (ASIC_IS_R300(rdev))
2845 channel_complete_mask =
2846 R300_MEM_PWRUP_COMPLETE;
2847 else
2848 channel_complete_mask =
2849 RADEON_MEM_PWRUP_COMPLETE;
2850 tmp = 20000;
2851 while (tmp--) {
2852 if ((RREG32(RADEON_MEM_STR_CNTL) &
2853 channel_complete_mask) ==
2854 channel_complete_mask)
2855 break;
2856 }
2857 } else {
2858 uint32_t or_mask = RBIOS16(offset);
2859 offset += 2;
2860
2861 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2862 tmp &= RADEON_SDRAM_MODE_MASK;
2863 tmp |= or_mask;
2864 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2865
2866 or_mask = val << 24;
2867 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2868 tmp &= RADEON_B3MEM_RESET_MASK;
2869 tmp |= or_mask;
2870 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2871 }
2872 val = RBIOS8(offset);
2873 }
2874 }
2875}
2876
2877static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2878 int mem_addr_mapping)
2879{
2880 struct radeon_device *rdev = dev->dev_private;
2881 uint32_t mem_cntl;
2882 uint32_t mem_size;
2883 uint32_t addr = 0;
2884
2885 mem_cntl = RREG32(RADEON_MEM_CNTL);
2886 if (mem_cntl & RV100_HALF_MODE)
2887 ram /= 2;
2888 mem_size = ram;
2889 mem_cntl &= ~(0xff << 8);
2890 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2891 WREG32(RADEON_MEM_CNTL, mem_cntl);
2892 RREG32(RADEON_MEM_CNTL);
2893
2894 /* sdram reset ? */
2895
2896 /* something like this???? */
2897 while (ram--) {
2898 addr = ram * 1024 * 1024;
2899 /* write to each page */
2900 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2901 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2902 /* read back and verify */
2903 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2904 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2905 return 0;
2906 }
2907
2908 return mem_size;
2909}
2910
2911static void combios_write_ram_size(struct drm_device *dev)
2912{
2913 struct radeon_device *rdev = dev->dev_private;
2914 uint8_t rev;
2915 uint16_t offset;
2916 uint32_t mem_size = 0;
2917 uint32_t mem_cntl = 0;
2918
2919 /* should do something smarter here I guess... */
2920 if (rdev->flags & RADEON_IS_IGP)
2921 return;
2922
2923 /* first check detected mem table */
2924 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2925 if (offset) {
2926 rev = RBIOS8(offset);
2927 if (rev < 3) {
2928 mem_cntl = RBIOS32(offset + 1);
2929 mem_size = RBIOS16(offset + 5);
4ce9198e
AD		 2930 if ((rdev->family < CHIP_R200) &&
2931 !ASIC_IS_RN50(rdev))
771fe6b9
JG		 2932 WREG32(RADEON_MEM_CNTL, mem_cntl);
2933 }
2934 }
2935
2936 if (!mem_size) {
2937 offset =
2938 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2939 if (offset) {
2940 rev = RBIOS8(offset - 1);
2941 if (rev < 1) {
4ce9198e
AD		 2942 if ((rdev->family < CHIP_R200)
2943 && !ASIC_IS_RN50(rdev)) {
771fe6b9
JG		 2944 int ram = 0;
2945 int mem_addr_mapping = 0;
2946
2947 while (RBIOS8(offset)) {
2948 ram = RBIOS8(offset);
2949 mem_addr_mapping =
2950 RBIOS8(offset + 1);
2951 if (mem_addr_mapping != 0x25)
2952 ram *= 2;
2953 mem_size =
2954 combios_detect_ram(dev, ram,
2955 mem_addr_mapping);
2956 if (mem_size)
2957 break;
2958 offset += 2;
2959 }
2960 } else
2961 mem_size = RBIOS8(offset);
2962 } else {
2963 mem_size = RBIOS8(offset);
2964 mem_size *= 2; /* convert to MB */
2965 }
2966 }
2967 }
2968
2969 mem_size *= (1024 * 1024); /* convert to bytes */
2970 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2971}
2972
2973void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2974{
2975 uint16_t dyn_clk_info =
2976 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2977
2978 if (dyn_clk_info)
2979 combios_parse_pll_table(dev, dyn_clk_info);
2980}
2981
2982void radeon_combios_asic_init(struct drm_device *dev)
2983{
2984 struct radeon_device *rdev = dev->dev_private;
2985 uint16_t table;
2986
2987 /* port hardcoded mac stuff from radeonfb */
2988 if (rdev->bios == NULL)
2989 return;
2990
2991 /* ASIC INIT 1 */
2992 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2993 if (table)
2994 combios_parse_mmio_table(dev, table);
2995
2996 /* PLL INIT */
2997 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2998 if (table)
2999 combios_parse_pll_table(dev, table);
3000
3001 /* ASIC INIT 2 */
3002 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3003 if (table)
3004 combios_parse_mmio_table(dev, table);
3005
3006 if (!(rdev->flags & RADEON_IS_IGP)) {
3007 /* ASIC INIT 4 */
3008 table =
3009 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3010 if (table)
3011 combios_parse_mmio_table(dev, table);
3012
3013 /* RAM RESET */
3014 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3015 if (table)
3016 combios_parse_ram_reset_table(dev, table);
3017
3018 /* ASIC INIT 3 */
3019 table =
3020 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3021 if (table)
3022 combios_parse_mmio_table(dev, table);
3023
3024 /* write CONFIG_MEMSIZE */
3025 combios_write_ram_size(dev);
3026 }
3027
580b4fff
DA		 3028 /* quirk for rs4xx HP nx6125 laptop to make it resume
3029 * - it hangs on resume inside the dynclk 1 table.
3030 */
3031 if (rdev->family == CHIP_RS480 &&
3032 rdev->pdev->subsystem_vendor == 0x103c &&
3033 rdev->pdev->subsystem_device == 0x308b)
3034 return;
3035
52fa2bbc
AD		 3036 /* quirk for rs4xx HP dv5000 laptop to make it resume
3037 * - it hangs on resume inside the dynclk 1 table.
3038 */
3039 if (rdev->family == CHIP_RS480 &&
3040 rdev->pdev->subsystem_vendor == 0x103c &&
3041 rdev->pdev->subsystem_device == 0x30a4)
3042 return;
3043
771fe6b9
JG		 3044 /* DYN CLK 1 */
3045 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3046 if (table)
3047 combios_parse_pll_table(dev, table);
3048
3049}
3050
3051void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3052{
3053 struct radeon_device *rdev = dev->dev_private;
3054 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3055
3056 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3057 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3058 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3059
3060 /* let the bios control the backlight */
3061 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3062
3063 /* tell the bios not to handle mode switching */
3064 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3065 RADEON_ACC_MODE_CHANGE);
3066
3067 /* tell the bios a driver is loaded */
3068 bios_7_scratch |= RADEON_DRV_LOADED;
3069
3070 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3071 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3072 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3073}
3074
3075void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3076{
3077 struct drm_device *dev = encoder->dev;
3078 struct radeon_device *rdev = dev->dev_private;
3079 uint32_t bios_6_scratch;
3080
3081 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3082
3083 if (lock)
3084 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3085 else
3086 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3087
3088 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3089}
3090
3091void
3092radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3093 struct drm_encoder *encoder,
3094 bool connected)
3095{
3096 struct drm_device *dev = connector->dev;
3097 struct radeon_device *rdev = dev->dev_private;
3098 struct radeon_connector *radeon_connector =
3099 to_radeon_connector(connector);
3100 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3101 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3102 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3103
3104 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3105 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3106 if (connected) {
d9fdaafb 3107 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 3108 /* fix me */
3109 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3110 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3111 bios_5_scratch |= RADEON_TV1_ON;
3112 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3113 } else {
d9fdaafb 3114 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 3115 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3116 bios_5_scratch &= ~RADEON_TV1_ON;
3117 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3118 }
3119 }
3120 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3121 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3122 if (connected) {
d9fdaafb 3123 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 3124 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3125 bios_5_scratch |= RADEON_LCD1_ON;
3126 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3127 } else {
d9fdaafb 3128 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 3129 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3130 bios_5_scratch &= ~RADEON_LCD1_ON;
3131 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3132 }
3133 }
3134 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3135 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3136 if (connected) {
d9fdaafb 3137 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 3138 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3139 bios_5_scratch |= RADEON_CRT1_ON;
3140 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3141 } else {
d9fdaafb 3142 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 3143 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3144 bios_5_scratch &= ~RADEON_CRT1_ON;
3145 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3146 }
3147 }
3148 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3149 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3150 if (connected) {
d9fdaafb 3151 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 3152 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3153 bios_5_scratch |= RADEON_CRT2_ON;
3154 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3155 } else {
d9fdaafb 3156 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 3157 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3158 bios_5_scratch &= ~RADEON_CRT2_ON;
3159 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3160 }
3161 }
3162 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3163 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3164 if (connected) {
d9fdaafb 3165 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 3166 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3167 bios_5_scratch |= RADEON_DFP1_ON;
3168 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3169 } else {
d9fdaafb 3170 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 3171 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3172 bios_5_scratch &= ~RADEON_DFP1_ON;
3173 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3174 }
3175 }
3176 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3177 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3178 if (connected) {
d9fdaafb 3179 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 3180 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3181 bios_5_scratch |= RADEON_DFP2_ON;
3182 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3183 } else {
d9fdaafb 3184 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 3185 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3186 bios_5_scratch &= ~RADEON_DFP2_ON;
3187 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3188 }
3189 }
3190 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3191 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3192}
3193
3194void
3195radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3196{
3197 struct drm_device *dev = encoder->dev;
3198 struct radeon_device *rdev = dev->dev_private;
3199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3200 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3201
3202 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3203 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3204 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3205 }
3206 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3207 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3208 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3209 }
3210 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3211 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3212 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3213 }
3214 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3215 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3216 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3217 }
3218 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3219 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3220 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3221 }
3222 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3223 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3224 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3225 }
3226 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3227}
3228
3229void
3230radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3231{
3232 struct drm_device *dev = encoder->dev;
3233 struct radeon_device *rdev = dev->dev_private;
3234 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3235 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3236
3237 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3238 if (on)
3239 bios_6_scratch |= RADEON_TV_DPMS_ON;
3240 else
3241 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3242 }
3243 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3244 if (on)
3245 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3246 else
3247 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3248 }
3249 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3250 if (on)
3251 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3252 else
3253 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3254 }
3255 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3256 if (on)
3257 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3258 else
3259 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3260 }
3261 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3262}
Clone of davem's net-next-2.6 tree