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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_clocks.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon_drm.h"
30#include "radeon_reg.h"
31#include "radeon.h"
32#include "atom.h"
33
34/* 10 khz */
7433874e 35uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
771fe6b9
JG		 36{
37 struct radeon_pll *spll = &rdev->clock.spll;
38 uint32_t fb_div, ref_div, post_div, sclk;
39
40 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
41 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
42 fb_div <<= 1;
43 fb_div *= spll->reference_freq;
44
45 ref_div =
46 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
4b30b870
DA		 47
48 if (ref_div == 0)
49 return 0;
50
771fe6b9
JG		 51 sclk = fb_div / ref_div;
52
53 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
54 if (post_div == 2)
55 sclk >>= 1;
56 else if (post_div == 3)
57 sclk >>= 2;
58 else if (post_div == 4)
38678d35 59 sclk >>= 3;
771fe6b9
JG		 60
61 return sclk;
62}
63
64/* 10 khz */
5ea597f3 65uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
771fe6b9
JG		 66{
67 struct radeon_pll *mpll = &rdev->clock.mpll;
68 uint32_t fb_div, ref_div, post_div, mclk;
69
70 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
71 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
72 fb_div <<= 1;
73 fb_div *= mpll->reference_freq;
74
75 ref_div =
76 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
4b30b870
DA		 77
78 if (ref_div == 0)
79 return 0;
80
771fe6b9
JG		 81 mclk = fb_div / ref_div;
82
83 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
84 if (post_div == 2)
85 mclk >>= 1;
86 else if (post_div == 3)
87 mclk >>= 2;
88 else if (post_div == 4)
38678d35 89 mclk >>= 3;
771fe6b9
JG		 90
91 return mclk;
92}
93
7b044f40
BH		 94#ifdef CONFIG_OF
95/*
96 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
97 * tree. Hopefully, ATI OF driver is kind enough to fill these
98 */
99static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
100{
101 struct radeon_device *rdev = dev->dev_private;
102 struct device_node *dp = rdev->pdev->dev.of_node;
103 const u32 *val;
104 struct radeon_pll *p1pll = &rdev->clock.p1pll;
105 struct radeon_pll *p2pll = &rdev->clock.p2pll;
106 struct radeon_pll *spll = &rdev->clock.spll;
107 struct radeon_pll *mpll = &rdev->clock.mpll;
108
109 if (dp == NULL)
110 return false;
111 val = of_get_property(dp, "ATY,RefCLK", NULL);
112 if (!val || !*val) {
113 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
114 return false;
115 }
116 p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
118 if (p1pll->reference_div < 2)
119 p1pll->reference_div = 12;
120 p2pll->reference_div = p1pll->reference_div;
121
122 /* These aren't in the device-tree */
123 if (rdev->family >= CHIP_R420) {
124 p1pll->pll_in_min = 100;
125 p1pll->pll_in_max = 1350;
126 p1pll->pll_out_min = 20000;
127 p1pll->pll_out_max = 50000;
128 p2pll->pll_in_min = 100;
129 p2pll->pll_in_max = 1350;
130 p2pll->pll_out_min = 20000;
131 p2pll->pll_out_max = 50000;
132 } else {
133 p1pll->pll_in_min = 40;
134 p1pll->pll_in_max = 500;
135 p1pll->pll_out_min = 12500;
136 p1pll->pll_out_max = 35000;
137 p2pll->pll_in_min = 40;
138 p2pll->pll_in_max = 500;
139 p2pll->pll_out_min = 12500;
140 p2pll->pll_out_max = 35000;
141 }
142
143 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
144 spll->reference_div = mpll->reference_div =
145 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
146 RADEON_M_SPLL_REF_DIV_MASK;
147
148 val = of_get_property(dp, "ATY,SCLK", NULL);
149 if (val && *val)
150 rdev->clock.default_sclk = (*val) / 10;
151 else
152 rdev->clock.default_sclk =
153 radeon_legacy_get_engine_clock(rdev);
154
155 val = of_get_property(dp, "ATY,MCLK", NULL);
156 if (val && *val)
157 rdev->clock.default_mclk = (*val) / 10;
158 else
159 rdev->clock.default_mclk =
160 radeon_legacy_get_memory_clock(rdev);
161
162 DRM_INFO("Using device-tree clock info\n");
163
164 return true;
165}
166#else
167static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
168{
169 return false;
170}
171#endif /* CONFIG_OF */
172
771fe6b9
JG		 173void radeon_get_clock_info(struct drm_device *dev)
174{
175 struct radeon_device *rdev = dev->dev_private;
176 struct radeon_pll *p1pll = &rdev->clock.p1pll;
177 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 178 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 179 struct radeon_pll *spll = &rdev->clock.spll;
180 struct radeon_pll *mpll = &rdev->clock.mpll;
181 int ret;
182
183 if (rdev->is_atom_bios)
184 ret = radeon_atom_get_clock_info(dev);
185 else
186 ret = radeon_combios_get_clock_info(dev);
7b044f40
BH		 187 if (!ret)
188 ret = radeon_read_clocks_OF(dev);
771fe6b9
JG		 189
190 if (ret) {
2a008d0c
AD		 191 if (p1pll->reference_div < 2) {
192 if (!ASIC_IS_AVIVO(rdev)) {
193 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
194 if (ASIC_IS_R300(rdev))
195 p1pll->reference_div =
196 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
197 else
198 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
199 if (p1pll->reference_div < 2)
200 p1pll->reference_div = 12;
201 } else
202 p1pll->reference_div = 12;
203 }
771fe6b9
JG		 204 if (p2pll->reference_div < 2)
205 p2pll->reference_div = 12;
3ce0a23d
JG		 206 if (rdev->family < CHIP_RS600) {
207 if (spll->reference_div < 2)
208 spll->reference_div =
209 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
210 RADEON_M_SPLL_REF_DIV_MASK;
211 }
771fe6b9
JG		 212 if (mpll->reference_div < 2)
213 mpll->reference_div = spll->reference_div;
214 } else {
215 if (ASIC_IS_AVIVO(rdev)) {
216 /* TODO FALLBACK */
217 } else {
218 DRM_INFO("Using generic clock info\n");
219
220 if (rdev->flags & RADEON_IS_IGP) {
221 p1pll->reference_freq = 1432;
222 p2pll->reference_freq = 1432;
223 spll->reference_freq = 1432;
224 mpll->reference_freq = 1432;
225 } else {
226 p1pll->reference_freq = 2700;
227 p2pll->reference_freq = 2700;
228 spll->reference_freq = 2700;
229 mpll->reference_freq = 2700;
230 }
231 p1pll->reference_div =
232 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
233 if (p1pll->reference_div < 2)
234 p1pll->reference_div = 12;
235 p2pll->reference_div = p1pll->reference_div;
236
237 if (rdev->family >= CHIP_R420) {
238 p1pll->pll_in_min = 100;
239 p1pll->pll_in_max = 1350;
240 p1pll->pll_out_min = 20000;
241 p1pll->pll_out_max = 50000;
242 p2pll->pll_in_min = 100;
243 p2pll->pll_in_max = 1350;
244 p2pll->pll_out_min = 20000;
245 p2pll->pll_out_max = 50000;
246 } else {
247 p1pll->pll_in_min = 40;
248 p1pll->pll_in_max = 500;
249 p1pll->pll_out_min = 12500;
250 p1pll->pll_out_max = 35000;
251 p2pll->pll_in_min = 40;
252 p2pll->pll_in_max = 500;
253 p2pll->pll_out_min = 12500;
254 p2pll->pll_out_max = 35000;
255 }
256
257 spll->reference_div =
258 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
259 RADEON_M_SPLL_REF_DIV_MASK;
260 mpll->reference_div = spll->reference_div;
261 rdev->clock.default_sclk =
262 radeon_legacy_get_engine_clock(rdev);
263 rdev->clock.default_mclk =
264 radeon_legacy_get_memory_clock(rdev);
265 }
266 }
267
268 /* pixel clocks */
269 if (ASIC_IS_AVIVO(rdev)) {
270 p1pll->min_post_div = 2;
271 p1pll->max_post_div = 0x7f;
272 p1pll->min_frac_feedback_div = 0;
273 p1pll->max_frac_feedback_div = 9;
274 p2pll->min_post_div = 2;
275 p2pll->max_post_div = 0x7f;
276 p2pll->min_frac_feedback_div = 0;
277 p2pll->max_frac_feedback_div = 9;
278 } else {
279 p1pll->min_post_div = 1;
280 p1pll->max_post_div = 16;
281 p1pll->min_frac_feedback_div = 0;
282 p1pll->max_frac_feedback_div = 0;
283 p2pll->min_post_div = 1;
284 p2pll->max_post_div = 12;
285 p2pll->min_frac_feedback_div = 0;
286 p2pll->max_frac_feedback_div = 0;
287 }
288
bcc1c2a1
AD		 289 /* dcpll is DCE4 only */
290 dcpll->min_post_div = 2;
291 dcpll->max_post_div = 0x7f;
292 dcpll->min_frac_feedback_div = 0;
293 dcpll->max_frac_feedback_div = 9;
294 dcpll->min_ref_div = 2;
295 dcpll->max_ref_div = 0x3ff;
296 dcpll->min_feedback_div = 4;
297 dcpll->max_feedback_div = 0xfff;
298 dcpll->best_vco = 0;
299
771fe6b9
JG		 300 p1pll->min_ref_div = 2;
301 p1pll->max_ref_div = 0x3ff;
302 p1pll->min_feedback_div = 4;
303 p1pll->max_feedback_div = 0x7ff;
304 p1pll->best_vco = 0;
305
306 p2pll->min_ref_div = 2;
307 p2pll->max_ref_div = 0x3ff;
308 p2pll->min_feedback_div = 4;
309 p2pll->max_feedback_div = 0x7ff;
310 p2pll->best_vco = 0;
311
312 /* system clock */
313 spll->min_post_div = 1;
314 spll->max_post_div = 1;
315 spll->min_ref_div = 2;
316 spll->max_ref_div = 0xff;
317 spll->min_feedback_div = 4;
318 spll->max_feedback_div = 0xff;
319 spll->best_vco = 0;
320
321 /* memory clock */
322 mpll->min_post_div = 1;
323 mpll->max_post_div = 1;
324 mpll->min_ref_div = 2;
325 mpll->max_ref_div = 0xff;
326 mpll->min_feedback_div = 4;
327 mpll->max_feedback_div = 0xff;
328 mpll->best_vco = 0;
329
8807286e
AD		 330 if (!rdev->clock.default_sclk)
331 rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
332 if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock)
333 rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
334
335 rdev->pm.current_sclk = rdev->clock.default_sclk;
336 rdev->pm.current_mclk = rdev->clock.default_mclk;
337
771fe6b9
JG		 338}
339
340/* 10 khz */
341static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
342 uint32_t req_clock,
343 int *fb_div, int *post_div)
344{
345 struct radeon_pll *spll = &rdev->clock.spll;
346 int ref_div = spll->reference_div;
347
348 if (!ref_div)
349 ref_div =
350 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
351 RADEON_M_SPLL_REF_DIV_MASK;
352
353 if (req_clock < 15000) {
354 *post_div = 8;
355 req_clock *= 8;
356 } else if (req_clock < 30000) {
357 *post_div = 4;
358 req_clock *= 4;
359 } else if (req_clock < 60000) {
360 *post_div = 2;
361 req_clock *= 2;
362 } else
363 *post_div = 1;
364
365 req_clock *= ref_div;
366 req_clock += spll->reference_freq;
367 req_clock /= (2 * spll->reference_freq);
368
369 *fb_div = req_clock & 0xff;
370
371 req_clock = (req_clock & 0xffff) << 1;
372 req_clock *= spll->reference_freq;
373 req_clock /= ref_div;
374 req_clock /= *post_div;
375
376 return req_clock;
377}
378
379/* 10 khz */
380void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
381 uint32_t eng_clock)
382{
383 uint32_t tmp;
384 int fb_div, post_div;
385
386 /* XXX: wait for idle */
387
388 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
389
390 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
391 tmp &= ~RADEON_DONT_USE_XTALIN;
392 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
393
394 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
395 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
396 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
397
398 udelay(10);
399
400 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
401 tmp |= RADEON_SPLL_SLEEP;
402 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
403
404 udelay(2);
405
406 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
407 tmp |= RADEON_SPLL_RESET;
408 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
409
410 udelay(200);
411
412 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
413 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
414 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
415 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
416
417 /* XXX: verify on different asics */
418 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
419 tmp &= ~RADEON_SPLL_PVG_MASK;
420 if ((eng_clock * post_div) >= 90000)
421 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
422 else
423 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
424 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
425
426 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
427 tmp &= ~RADEON_SPLL_SLEEP;
428 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
429
430 udelay(2);
431
432 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
433 tmp &= ~RADEON_SPLL_RESET;
434 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
435
436 udelay(200);
437
438 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
439 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
440 switch (post_div) {
441 case 1:
442 default:
443 tmp |= 1;
444 break;
445 case 2:
446 tmp |= 2;
447 break;
448 case 4:
449 tmp |= 3;
450 break;
451 case 8:
452 tmp |= 4;
453 break;
454 }
455 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
456
457 udelay(20);
458
459 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
460 tmp |= RADEON_DONT_USE_XTALIN;
461 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
462
463 udelay(10);
464}
465
466void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
467{
468 uint32_t tmp;
469
470 if (enable) {
471 if (rdev->flags & RADEON_SINGLE_CRTC) {
472 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
473 if ((RREG32(RADEON_CONFIG_CNTL) &
474 RADEON_CFG_ATI_REV_ID_MASK) >
475 RADEON_CFG_ATI_REV_A13) {
476 tmp &=
477 ~(RADEON_SCLK_FORCE_CP |
478 RADEON_SCLK_FORCE_RB);
479 }
480 tmp &=
481 ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
482 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
483 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
484 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
485 RADEON_SCLK_FORCE_TDM);
486 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
487 } else if (ASIC_IS_R300(rdev)) {
488 if ((rdev->family == CHIP_RS400) ||
489 (rdev->family == CHIP_RS480)) {
490 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
491 tmp &=
492 ~(RADEON_SCLK_FORCE_DISP2 |
493 RADEON_SCLK_FORCE_CP |
494 RADEON_SCLK_FORCE_HDP |
495 RADEON_SCLK_FORCE_DISP1 |
496 RADEON_SCLK_FORCE_TOP |
497 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
498 | RADEON_SCLK_FORCE_IDCT |
499 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
500 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
501 | R300_SCLK_FORCE_US |
502 RADEON_SCLK_FORCE_TV_SCLK |
503 R300_SCLK_FORCE_SU |
504 RADEON_SCLK_FORCE_OV0);
505 tmp |= RADEON_DYN_STOP_LAT_MASK;
506 tmp |=
507 RADEON_SCLK_FORCE_TOP |
508 RADEON_SCLK_FORCE_VIP;
509 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
510
511 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
512 tmp &= ~RADEON_SCLK_MORE_FORCEON;
513 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
514 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
515
516 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
517 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
518 RADEON_PIXCLK_DAC_ALWAYS_ONb);
519 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
520
521 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
522 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
523 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
524 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
525 R300_DVOCLK_ALWAYS_ONb |
526 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
527 RADEON_PIXCLK_GV_ALWAYS_ONb |
528 R300_PIXCLK_DVO_ALWAYS_ONb |
529 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
530 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
531 R300_PIXCLK_TRANS_ALWAYS_ONb |
532 R300_PIXCLK_TVO_ALWAYS_ONb |
533 R300_P2G2CLK_ALWAYS_ONb |
aa96e341 534 R300_P2G2CLK_DAC_ALWAYS_ONb);
771fe6b9
JG		 535 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
536 } else if (rdev->family >= CHIP_RV350) {
537 tmp = RREG32_PLL(R300_SCLK_CNTL2);
538 tmp &= ~(R300_SCLK_FORCE_TCL |
539 R300_SCLK_FORCE_GA |
540 R300_SCLK_FORCE_CBA);
541 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
542 R300_SCLK_GA_MAX_DYN_STOP_LAT |
543 R300_SCLK_CBA_MAX_DYN_STOP_LAT);
544 WREG32_PLL(R300_SCLK_CNTL2, tmp);
545
546 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
547 tmp &=
548 ~(RADEON_SCLK_FORCE_DISP2 |
549 RADEON_SCLK_FORCE_CP |
550 RADEON_SCLK_FORCE_HDP |
551 RADEON_SCLK_FORCE_DISP1 |
552 RADEON_SCLK_FORCE_TOP |
553 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
554 | RADEON_SCLK_FORCE_IDCT |
555 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
556 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
557 | R300_SCLK_FORCE_US |
558 RADEON_SCLK_FORCE_TV_SCLK |
559 R300_SCLK_FORCE_SU |
560 RADEON_SCLK_FORCE_OV0);
561 tmp |= RADEON_DYN_STOP_LAT_MASK;
562 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
563
564 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
565 tmp &= ~RADEON_SCLK_MORE_FORCEON;
566 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
567 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
568
569 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
570 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
571 RADEON_PIXCLK_DAC_ALWAYS_ONb);
572 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
573
574 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
575 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
576 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
577 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
578 R300_DVOCLK_ALWAYS_ONb |
579 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
580 RADEON_PIXCLK_GV_ALWAYS_ONb |
581 R300_PIXCLK_DVO_ALWAYS_ONb |
582 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
583 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
584 R300_PIXCLK_TRANS_ALWAYS_ONb |
585 R300_PIXCLK_TVO_ALWAYS_ONb |
586 R300_P2G2CLK_ALWAYS_ONb |
aa96e341 587 R300_P2G2CLK_DAC_ALWAYS_ONb);
771fe6b9
JG		 588 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
589
590 tmp = RREG32_PLL(RADEON_MCLK_MISC);
591 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
592 RADEON_IO_MCLK_DYN_ENABLE);
593 WREG32_PLL(RADEON_MCLK_MISC, tmp);
594
595 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
596 tmp |= (RADEON_FORCEON_MCLKA |
597 RADEON_FORCEON_MCLKB);
598
599 tmp &= ~(RADEON_FORCEON_YCLKA |
600 RADEON_FORCEON_YCLKB |
601 RADEON_FORCEON_MC);
602
603 /* Some releases of vbios have set DISABLE_MC_MCLKA
604 and DISABLE_MC_MCLKB bits in the vbios table. Setting these
605 bits will cause H/W hang when reading video memory with dynamic clocking
606 enabled. */
607 if ((tmp & R300_DISABLE_MC_MCLKA) &&
608 (tmp & R300_DISABLE_MC_MCLKB)) {
609 /* If both bits are set, then check the active channels */
610 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
611 if (rdev->mc.vram_width == 64) {
612 if (RREG32(RADEON_MEM_CNTL) &
613 R300_MEM_USE_CD_CH_ONLY)
614 tmp &=
615 ~R300_DISABLE_MC_MCLKB;
616 else
617 tmp &=
618 ~R300_DISABLE_MC_MCLKA;
619 } else {
620 tmp &= ~(R300_DISABLE_MC_MCLKA |
621 R300_DISABLE_MC_MCLKB);
622 }
623 }
624
625 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
626 } else {
627 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
628 tmp &= ~(R300_SCLK_FORCE_VAP);
629 tmp |= RADEON_SCLK_FORCE_CP;
630 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
631 udelay(15000);
632
633 tmp = RREG32_PLL(R300_SCLK_CNTL2);
634 tmp &= ~(R300_SCLK_FORCE_TCL |
635 R300_SCLK_FORCE_GA |
636 R300_SCLK_FORCE_CBA);
637 WREG32_PLL(R300_SCLK_CNTL2, tmp);
638 }
639 } else {
640 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
641
642 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
643 RADEON_DISP_DYN_STOP_LAT_MASK |
644 RADEON_DYN_STOP_MODE_MASK);
645
646 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
647 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
648 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
649 udelay(15000);
650
651 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
652 tmp |= RADEON_SCLK_DYN_START_CNTL;
653 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
654 udelay(15000);
655
656 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
657 to lockup randomly, leave them as set by BIOS.
658 */
659 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
660 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
661 tmp &= ~RADEON_SCLK_FORCEON_MASK;
662
663 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
664 if (((rdev->family == CHIP_RV250) &&
665 ((RREG32(RADEON_CONFIG_CNTL) &
666 RADEON_CFG_ATI_REV_ID_MASK) <
667 RADEON_CFG_ATI_REV_A13))
668 || ((rdev->family == CHIP_RV100)
669 &&
670 ((RREG32(RADEON_CONFIG_CNTL) &
671 RADEON_CFG_ATI_REV_ID_MASK) <=
672 RADEON_CFG_ATI_REV_A13))) {
673 tmp |= RADEON_SCLK_FORCE_CP;
674 tmp |= RADEON_SCLK_FORCE_VIP;
675 }
676
677 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
678
679 if ((rdev->family == CHIP_RV200) ||
680 (rdev->family == CHIP_RV250) ||
681 (rdev->family == CHIP_RV280)) {
682 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
683 tmp &= ~RADEON_SCLK_MORE_FORCEON;
684
685 /* RV200::A11 A12 RV250::A11 A12 */
686 if (((rdev->family == CHIP_RV200) ||
687 (rdev->family == CHIP_RV250)) &&
688 ((RREG32(RADEON_CONFIG_CNTL) &
689 RADEON_CFG_ATI_REV_ID_MASK) <
690 RADEON_CFG_ATI_REV_A13)) {
691 tmp |= RADEON_SCLK_MORE_FORCEON;
692 }
693 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
694 udelay(15000);
695 }
696
697 /* RV200::A11 A12, RV250::A11 A12 */
698 if (((rdev->family == CHIP_RV200) ||
699 (rdev->family == CHIP_RV250)) &&
700 ((RREG32(RADEON_CONFIG_CNTL) &
701 RADEON_CFG_ATI_REV_ID_MASK) <
702 RADEON_CFG_ATI_REV_A13)) {
703 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
704 tmp |= RADEON_TCL_BYPASS_DISABLE;
705 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
706 }
707 udelay(15000);
708
709 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
710 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
711 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
712 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
713 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
714 RADEON_PIXCLK_GV_ALWAYS_ONb |
715 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
716 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
717 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
718
719 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
720 udelay(15000);
721
722 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
723 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
724 RADEON_PIXCLK_DAC_ALWAYS_ONb);
725
726 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
727 udelay(15000);
728 }
729 } else {
730 /* Turn everything OFF (ForceON to everything) */
731 if (rdev->flags & RADEON_SINGLE_CRTC) {
732 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
733 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
734 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
735 | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
736 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
737 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
738 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
739 RADEON_SCLK_FORCE_RB);
740 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
741 } else if ((rdev->family == CHIP_RS400) ||
742 (rdev->family == CHIP_RS480)) {
743 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
744 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
745 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
746 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
747 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
748 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
749 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
750 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
751 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
752 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
753
754 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
755 tmp |= RADEON_SCLK_MORE_FORCEON;
756 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
757
758 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
759 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
760 RADEON_PIXCLK_DAC_ALWAYS_ONb |
761 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
762 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
763
764 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
765 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
766 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
767 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
768 R300_DVOCLK_ALWAYS_ONb |
769 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
770 RADEON_PIXCLK_GV_ALWAYS_ONb |
771 R300_PIXCLK_DVO_ALWAYS_ONb |
772 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
773 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
774 R300_PIXCLK_TRANS_ALWAYS_ONb |
775 R300_PIXCLK_TVO_ALWAYS_ONb |
776 R300_P2G2CLK_ALWAYS_ONb |
aa96e341 777 R300_P2G2CLK_DAC_ALWAYS_ONb |
771fe6b9
JG		 778 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
779 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
780 } else if (rdev->family >= CHIP_RV350) {
781 /* for RV350/M10, no delays are required. */
782 tmp = RREG32_PLL(R300_SCLK_CNTL2);
783 tmp |= (R300_SCLK_FORCE_TCL |
784 R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
785 WREG32_PLL(R300_SCLK_CNTL2, tmp);
786
787 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
788 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
789 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
790 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
791 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
792 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
793 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
794 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
795 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
796 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
797
798 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
799 tmp |= RADEON_SCLK_MORE_FORCEON;
800 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
801
802 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
803 tmp |= (RADEON_FORCEON_MCLKA |
804 RADEON_FORCEON_MCLKB |
805 RADEON_FORCEON_YCLKA |
806 RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
807 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
808
809 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
810 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
811 RADEON_PIXCLK_DAC_ALWAYS_ONb |
812 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
813 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
814
815 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
816 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
817 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
818 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
819 R300_DVOCLK_ALWAYS_ONb |
820 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
821 RADEON_PIXCLK_GV_ALWAYS_ONb |
822 R300_PIXCLK_DVO_ALWAYS_ONb |
823 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
824 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
825 R300_PIXCLK_TRANS_ALWAYS_ONb |
826 R300_PIXCLK_TVO_ALWAYS_ONb |
827 R300_P2G2CLK_ALWAYS_ONb |
aa96e341 828 R300_P2G2CLK_DAC_ALWAYS_ONb |
771fe6b9
JG		 829 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
830 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
831 } else {
832 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
833 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
834 tmp |= RADEON_SCLK_FORCE_SE;
835
836 if (rdev->flags & RADEON_SINGLE_CRTC) {
837 tmp |= (RADEON_SCLK_FORCE_RB |
838 RADEON_SCLK_FORCE_TDM |
839 RADEON_SCLK_FORCE_TAM |
840 RADEON_SCLK_FORCE_PB |
841 RADEON_SCLK_FORCE_RE |
842 RADEON_SCLK_FORCE_VIP |
843 RADEON_SCLK_FORCE_IDCT |
844 RADEON_SCLK_FORCE_TOP |
845 RADEON_SCLK_FORCE_DISP1 |
846 RADEON_SCLK_FORCE_DISP2 |
847 RADEON_SCLK_FORCE_HDP);
848 } else if ((rdev->family == CHIP_R300) ||
849 (rdev->family == CHIP_R350)) {
850 tmp |= (RADEON_SCLK_FORCE_HDP |
851 RADEON_SCLK_FORCE_DISP1 |
852 RADEON_SCLK_FORCE_DISP2 |
853 RADEON_SCLK_FORCE_TOP |
854 RADEON_SCLK_FORCE_IDCT |
855 RADEON_SCLK_FORCE_VIP);
856 }
857 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
858
859 udelay(16000);
860
861 if ((rdev->family == CHIP_R300) ||
862 (rdev->family == CHIP_R350)) {
863 tmp = RREG32_PLL(R300_SCLK_CNTL2);
864 tmp |= (R300_SCLK_FORCE_TCL |
865 R300_SCLK_FORCE_GA |
866 R300_SCLK_FORCE_CBA);
867 WREG32_PLL(R300_SCLK_CNTL2, tmp);
868 udelay(16000);
869 }
870
871 if (rdev->flags & RADEON_IS_IGP) {
872 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
873 tmp &= ~(RADEON_FORCEON_MCLKA |
874 RADEON_FORCEON_YCLKA);
875 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
876 udelay(16000);
877 }
878
879 if ((rdev->family == CHIP_RV200) ||
880 (rdev->family == CHIP_RV250) ||
881 (rdev->family == CHIP_RV280)) {
882 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
883 tmp |= RADEON_SCLK_MORE_FORCEON;
884 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
885 udelay(16000);
886 }
887
888 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
889 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
890 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
891 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
892 RADEON_PIXCLK_GV_ALWAYS_ONb |
893 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
894 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
895 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
896
897 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
898 udelay(16000);
899
900 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
901 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
902 RADEON_PIXCLK_DAC_ALWAYS_ONb);
903 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
904 }
905 }
906}
907
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