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Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
5137ee94
AD		 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
771fe6b9
JG		 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
5137ee94 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
5137ee94 49 uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
5137ee94 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
ea39302b
AD		 88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
a084e6ee
AD		 101 if (gpio->sucI2cId.ucAccess == id) {
102 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
103 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
104 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
105 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
106 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
107 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
108 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
109 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
110 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
111 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
112 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
113 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
114 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
115 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
116 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
117 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
118
119 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
120 i2c.hw_capable = true;
121 else
122 i2c.hw_capable = false;
123
124 if (gpio->sucI2cId.ucAccess == 0xa0)
125 i2c.mm_i2c = true;
126 else
127 i2c.mm_i2c = false;
128
129 i2c.i2c_id = gpio->sucI2cId.ucAccess;
130
f376b94f
AD		 131 if (i2c.mask_clk_reg)
132 i2c.valid = true;
a084e6ee
AD		 133 break;
134 }
d3f420d1
AD		 135 }
136 }
771fe6b9
JG		 137
138 return i2c;
139}
140
f376b94f
AD		 141void radeon_atombios_i2c_init(struct radeon_device *rdev)
142{
143 struct atom_context *ctx = rdev->mode_info.atom_context;
144 ATOM_GPIO_I2C_ASSIGMENT *gpio;
145 struct radeon_i2c_bus_rec i2c;
146 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
147 struct _ATOM_GPIO_I2C_INFO *i2c_info;
148 uint16_t data_offset, size;
149 int i, num_indices;
150 char stmp[32];
151
152 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
153
154 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
155 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
156
157 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
158 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
159
160 for (i = 0; i < num_indices; i++) {
161 gpio = &i2c_info->asGPIO_Info[i];
162 i2c.valid = false;
ea39302b
AD		 163
164 /* some evergreen boards have bad data for this entry */
165 if (ASIC_IS_DCE4(rdev)) {
166 if ((i == 7) &&
167 (gpio->usClkMaskRegisterIndex == 0x1936) &&
168 (gpio->sucI2cId.ucAccess == 0)) {
169 gpio->sucI2cId.ucAccess = 0x97;
170 gpio->ucDataMaskShift = 8;
171 gpio->ucDataEnShift = 8;
172 gpio->ucDataY_Shift = 8;
173 gpio->ucDataA_Shift = 8;
174 }
175 }
176
f376b94f
AD		 177 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
178 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
179 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
180 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
181 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
182 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
183 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
184 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
185 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
186 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
187 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
188 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
189 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
190 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
191 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
192 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
193
194 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
195 i2c.hw_capable = true;
196 else
197 i2c.hw_capable = false;
198
199 if (gpio->sucI2cId.ucAccess == 0xa0)
200 i2c.mm_i2c = true;
201 else
202 i2c.mm_i2c = false;
203
204 i2c.i2c_id = gpio->sucI2cId.ucAccess;
205
206 if (i2c.mask_clk_reg) {
207 i2c.valid = true;
208 sprintf(stmp, "0x%x", i2c.i2c_id);
209 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
210 }
211 }
212 }
213}
214
eed45b30
AD		 215static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
216 u8 id)
217{
218 struct atom_context *ctx = rdev->mode_info.atom_context;
219 struct radeon_gpio_rec gpio;
220 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
221 struct _ATOM_GPIO_PIN_LUT *gpio_info;
222 ATOM_GPIO_PIN_ASSIGNMENT *pin;
223 u16 data_offset, size;
224 int i, num_indices;
225
226 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
227 gpio.valid = false;
228
a084e6ee
AD		 229 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
230 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 231
a084e6ee
AD		 232 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
233 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 234
a084e6ee
AD		 235 for (i = 0; i < num_indices; i++) {
236 pin = &gpio_info->asGPIO_Pin[i];
237 if (id == pin->ucGPIO_ID) {
238 gpio.id = pin->ucGPIO_ID;
239 gpio.reg = pin->usGpioPin_AIndex * 4;
240 gpio.mask = (1 << pin->ucGpioPinBitShift);
241 gpio.valid = true;
242 break;
243 }
eed45b30
AD		 244 }
245 }
246
247 return gpio;
248}
249
250static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
251 struct radeon_gpio_rec *gpio)
252{
253 struct radeon_hpd hpd;
bcc1c2a1
AD		 254 u32 reg;
255
1d978dac
JD		 256 memset(&hpd, 0, sizeof(struct radeon_hpd));
257
bcc1c2a1
AD		 258 if (ASIC_IS_DCE4(rdev))
259 reg = EVERGREEN_DC_GPIO_HPD_A;
260 else
261 reg = AVIVO_DC_GPIO_HPD_A;
262
eed45b30 263 hpd.gpio = *gpio;
bcc1c2a1 264 if (gpio->reg == reg) {
eed45b30
AD		 265 switch(gpio->mask) {
266 case (1 << 0):
267 hpd.hpd = RADEON_HPD_1;
268 break;
269 case (1 << 8):
270 hpd.hpd = RADEON_HPD_2;
271 break;
272 case (1 << 16):
273 hpd.hpd = RADEON_HPD_3;
274 break;
275 case (1 << 24):
276 hpd.hpd = RADEON_HPD_4;
277 break;
278 case (1 << 26):
279 hpd.hpd = RADEON_HPD_5;
280 break;
281 case (1 << 28):
282 hpd.hpd = RADEON_HPD_6;
283 break;
284 default:
285 hpd.hpd = RADEON_HPD_NONE;
286 break;
287 }
288 } else
289 hpd.hpd = RADEON_HPD_NONE;
290 return hpd;
291}
292
771fe6b9
JG		 293static bool radeon_atom_apply_quirks(struct drm_device *dev,
294 uint32_t supported_device,
295 int *connector_type,
848577ee 296 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 297 uint16_t *line_mux,
298 struct radeon_hpd *hpd)
771fe6b9 299{
9ea2c4be 300 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 301
302 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
303 if ((dev->pdev->device == 0x791e) &&
304 (dev->pdev->subsystem_vendor == 0x1043) &&
305 (dev->pdev->subsystem_device == 0x826d)) {
306 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
307 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
308 *connector_type = DRM_MODE_CONNECTOR_DVID;
309 }
310
c86a9038
AD		 311 /* Asrock RS600 board lists the DVI port as HDMI */
312 if ((dev->pdev->device == 0x7941) &&
313 (dev->pdev->subsystem_vendor == 0x1849) &&
314 (dev->pdev->subsystem_device == 0x7941)) {
315 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
316 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
317 *connector_type = DRM_MODE_CONNECTOR_DVID;
318 }
319
f36fce0f
AD		 320 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
321 if ((dev->pdev->device == 0x796e) &&
322 (dev->pdev->subsystem_vendor == 0x1462) &&
323 (dev->pdev->subsystem_device == 0x7302)) {
324 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
325 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
326 return false;
327 }
328
771fe6b9
JG		 329 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
330 if ((dev->pdev->device == 0x7941) &&
331 (dev->pdev->subsystem_vendor == 0x147b) &&
332 (dev->pdev->subsystem_device == 0x2412)) {
333 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
334 return false;
335 }
336
337 /* Falcon NW laptop lists vga ddc line for LVDS */
338 if ((dev->pdev->device == 0x5653) &&
339 (dev->pdev->subsystem_vendor == 0x1462) &&
340 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 341 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 342 i2c_bus->valid = false;
848577ee
AD		 343 *line_mux = 53;
344 }
771fe6b9
JG		 345 }
346
4e3f9b78
AD		 347 /* HIS X1300 is DVI+VGA, not DVI+DVI */
348 if ((dev->pdev->device == 0x7146) &&
349 (dev->pdev->subsystem_vendor == 0x17af) &&
350 (dev->pdev->subsystem_device == 0x2058)) {
351 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
352 return false;
353 }
354
aa1a750e
DA		 355 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
356 if ((dev->pdev->device == 0x7142) &&
357 (dev->pdev->subsystem_vendor == 0x1458) &&
358 (dev->pdev->subsystem_device == 0x2134)) {
359 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
360 return false;
361 }
362
363
771fe6b9
JG		 364 /* Funky macbooks */
365 if ((dev->pdev->device == 0x71C5) &&
366 (dev->pdev->subsystem_vendor == 0x106b) &&
367 (dev->pdev->subsystem_device == 0x0080)) {
368 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
369 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
370 return false;
e1e8a5dd
AD		 371 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
372 *line_mux = 0x90;
771fe6b9
JG		 373 }
374
771fe6b9
JG		 375 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
376 if ((dev->pdev->device == 0x9598) &&
377 (dev->pdev->subsystem_vendor == 0x1043) &&
378 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 379 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 380 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 381 }
382 }
383
e153b70b
AD		 384 /* ASUS HD 3600 board lists the DVI port as HDMI */
385 if ((dev->pdev->device == 0x9598) &&
386 (dev->pdev->subsystem_vendor == 0x1043) &&
387 (dev->pdev->subsystem_device == 0x01e4)) {
388 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
389 *connector_type = DRM_MODE_CONNECTOR_DVII;
390 }
391 }
392
705af9c7
AD		 393 /* ASUS HD 3450 board lists the DVI port as HDMI */
394 if ((dev->pdev->device == 0x95C5) &&
395 (dev->pdev->subsystem_vendor == 0x1043) &&
396 (dev->pdev->subsystem_device == 0x01e2)) {
397 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 398 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 399 }
400 }
401
705af9c7
AD		 402 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
403 * HDMI + VGA reporting as HDMI
404 */
405 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
406 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
407 *connector_type = DRM_MODE_CONNECTOR_VGA;
408 *line_mux = 0;
409 }
410 }
411
9ea2c4be 412 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
3e5f8ff3
AD		 413 if ((dev->pdev->device == 0x95c4) &&
414 (dev->pdev->subsystem_vendor == 0x1025) &&
415 (dev->pdev->subsystem_device == 0x013c)) {
9ea2c4be
AD		 416 struct radeon_gpio_rec gpio;
417
3e5f8ff3 418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be
AD		 419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 gpio = radeon_lookup_gpio(rdev, 6);
421 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
3e5f8ff3 422 *connector_type = DRM_MODE_CONNECTOR_DVID;
9ea2c4be
AD		 423 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
424 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
425 gpio = radeon_lookup_gpio(rdev, 7);
426 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
427 }
3e5f8ff3
AD		 428 }
429
efa8450f
DA		 430 /* XFX Pine Group device rv730 reports no VGA DDC lines
431 * even though they are wired up to record 0x93
432 */
433 if ((dev->pdev->device == 0x9498) &&
434 (dev->pdev->subsystem_vendor == 0x1682) &&
435 (dev->pdev->subsystem_device == 0x2452)) {
436 struct radeon_device *rdev = dev->dev_private;
437 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
438 }
771fe6b9
JG		 439 return true;
440}
441
442const int supported_devices_connector_convert[] = {
443 DRM_MODE_CONNECTOR_Unknown,
444 DRM_MODE_CONNECTOR_VGA,
445 DRM_MODE_CONNECTOR_DVII,
446 DRM_MODE_CONNECTOR_DVID,
447 DRM_MODE_CONNECTOR_DVIA,
448 DRM_MODE_CONNECTOR_SVIDEO,
449 DRM_MODE_CONNECTOR_Composite,
450 DRM_MODE_CONNECTOR_LVDS,
451 DRM_MODE_CONNECTOR_Unknown,
452 DRM_MODE_CONNECTOR_Unknown,
453 DRM_MODE_CONNECTOR_HDMIA,
454 DRM_MODE_CONNECTOR_HDMIB,
455 DRM_MODE_CONNECTOR_Unknown,
456 DRM_MODE_CONNECTOR_Unknown,
457 DRM_MODE_CONNECTOR_9PinDIN,
458 DRM_MODE_CONNECTOR_DisplayPort
459};
460
b75fad06
AD		 461const uint16_t supported_devices_connector_object_id_convert[] = {
462 CONNECTOR_OBJECT_ID_NONE,
463 CONNECTOR_OBJECT_ID_VGA,
464 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
465 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
466 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
467 CONNECTOR_OBJECT_ID_COMPOSITE,
468 CONNECTOR_OBJECT_ID_SVIDEO,
469 CONNECTOR_OBJECT_ID_LVDS,
470 CONNECTOR_OBJECT_ID_9PIN_DIN,
471 CONNECTOR_OBJECT_ID_9PIN_DIN,
472 CONNECTOR_OBJECT_ID_DISPLAYPORT,
473 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
474 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
475 CONNECTOR_OBJECT_ID_SVIDEO
476};
477
771fe6b9
JG		 478const int object_connector_convert[] = {
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_DVII,
481 DRM_MODE_CONNECTOR_DVII,
482 DRM_MODE_CONNECTOR_DVID,
483 DRM_MODE_CONNECTOR_DVID,
484 DRM_MODE_CONNECTOR_VGA,
485 DRM_MODE_CONNECTOR_Composite,
486 DRM_MODE_CONNECTOR_SVIDEO,
487 DRM_MODE_CONNECTOR_Unknown,
705af9c7 488 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 489 DRM_MODE_CONNECTOR_9PinDIN,
490 DRM_MODE_CONNECTOR_Unknown,
491 DRM_MODE_CONNECTOR_HDMIA,
492 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 493 DRM_MODE_CONNECTOR_LVDS,
494 DRM_MODE_CONNECTOR_9PinDIN,
495 DRM_MODE_CONNECTOR_Unknown,
496 DRM_MODE_CONNECTOR_Unknown,
497 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 498 DRM_MODE_CONNECTOR_DisplayPort,
499 DRM_MODE_CONNECTOR_eDP,
500 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 501};
502
503bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
504{
505 struct radeon_device *rdev = dev->dev_private;
506 struct radeon_mode_info *mode_info = &rdev->mode_info;
507 struct atom_context *ctx = mode_info->atom_context;
508 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 509 u16 size, data_offset;
510 u8 frev, crev;
771fe6b9 511 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
26b5bc98 512 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 513 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
514 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 515 int i, j, k, path_size, device_support;
771fe6b9 516 int connector_type;
eed45b30 517 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9 518 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 519 struct radeon_router router;
eed45b30
AD		 520 struct radeon_gpio_rec gpio;
521 struct radeon_hpd hpd;
522
a084e6ee 523 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 524 return false;
525
526 if (crev < 2)
527 return false;
528
26b5bc98
AD		 529 router.valid = false;
530
771fe6b9
JG		 531 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
532 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
533 (ctx->bios + data_offset +
534 le16_to_cpu(obj_header->usDisplayPathTableOffset));
535 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
536 (ctx->bios + data_offset +
537 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
26b5bc98
AD		 538 router_obj = (ATOM_OBJECT_TABLE *)
539 (ctx->bios + data_offset +
540 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 541 device_support = le16_to_cpu(obj_header->usDeviceSupport);
542
543 path_size = 0;
544 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
545 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
546 ATOM_DISPLAY_OBJECT_PATH *path;
547 addr += path_size;
548 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
549 path_size += le16_to_cpu(path->usSize);
5137ee94 550
771fe6b9
JG		 551 if (device_support & le16_to_cpu(path->usDeviceTag)) {
552 uint8_t con_obj_id, con_obj_num, con_obj_type;
553
554 con_obj_id =
555 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
556 >> OBJECT_ID_SHIFT;
557 con_obj_num =
558 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
559 >> ENUM_ID_SHIFT;
560 con_obj_type =
561 (le16_to_cpu(path->usConnObjectId) &
562 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
563
4bbd4973
DA		 564 /* TODO CV support */
565 if (le16_to_cpu(path->usDeviceTag) ==
566 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 567 continue;
568
ee59f2b4
AD		 569 /* IGP chips */
570 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 571 (con_obj_id ==
572 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
573 uint16_t igp_offset = 0;
574 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
575
576 index =
577 GetIndexIntoMasterTable(DATA,
578 IntegratedSystemInfo);
579
a084e6ee
AD		 580 if (atom_parse_data_header(ctx, index, &size, &frev,
581 &crev, &igp_offset)) {
582
583 if (crev >= 2) {
584 igp_obj =
585 (ATOM_INTEGRATED_SYSTEM_INFO_V2
586 *) (ctx->bios + igp_offset);
587
588 if (igp_obj) {
589 uint32_t slot_config, ct;
590
591 if (con_obj_num == 1)
592 slot_config =
593 igp_obj->
594 ulDDISlot1Config;
595 else
596 slot_config =
597 igp_obj->
598 ulDDISlot2Config;
599
600 ct = (slot_config >> 16) & 0xff;
601 connector_type =
602 object_connector_convert
603 [ct];
604 connector_object_id = ct;
605 igp_lane_info =
606 slot_config & 0xffff;
607 } else
608 continue;
771fe6b9
JG		 609 } else
610 continue;
a084e6ee
AD		 611 } else {
612 igp_lane_info = 0;
613 connector_type =
614 object_connector_convert[con_obj_id];
615 connector_object_id = con_obj_id;
616 }
771fe6b9
JG		 617 } else {
618 igp_lane_info = 0;
619 connector_type =
620 object_connector_convert[con_obj_id];
b75fad06 621 connector_object_id = con_obj_id;
771fe6b9
JG		 622 }
623
624 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
625 continue;
626
26b5bc98
AD		 627 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
628 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 629
26b5bc98 630 grph_obj_id =
771fe6b9
JG		 631 (le16_to_cpu(path->usGraphicObjIds[j]) &
632 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 633 grph_obj_num =
771fe6b9
JG		 634 (le16_to_cpu(path->usGraphicObjIds[j]) &
635 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 636 grph_obj_type =
771fe6b9
JG		 637 (le16_to_cpu(path->usGraphicObjIds[j]) &
638 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
639
26b5bc98 640 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
5137ee94 641 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
771fe6b9
JG		 642
643 radeon_add_atom_encoder(dev,
5137ee94 644 encoder_obj,
771fe6b9
JG		 645 le16_to_cpu
646 (path->
647 usDeviceTag));
648
26b5bc98
AD		 649 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
650 router.valid = false;
651 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
652 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
653 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
654 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
655 (ctx->bios + data_offset +
656 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
657 ATOM_I2C_RECORD *i2c_record;
658 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
659 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
660 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
661 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
662 (ctx->bios + data_offset +
663 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
664 int enum_id;
665
666 router.router_id = router_obj_id;
667 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
668 enum_id++) {
669 if (le16_to_cpu(path->usConnObjectId) ==
670 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
671 break;
672 }
673
674 while (record->ucRecordType > 0 &&
675 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
676 switch (record->ucRecordType) {
677 case ATOM_I2C_RECORD_TYPE:
678 i2c_record =
679 (ATOM_I2C_RECORD *)
680 record;
681 i2c_config =
682 (ATOM_I2C_ID_CONFIG_ACCESS *)
683 &i2c_record->sucI2cId;
684 router.i2c_info =
685 radeon_lookup_i2c_gpio(rdev,
686 i2c_config->
687 ucAccess);
688 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
689 break;
690 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
691 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
692 record;
693 router.valid = true;
694 router.mux_type = ddc_path->ucMuxType;
695 router.mux_control_pin = ddc_path->ucMuxControlPin;
696 router.mux_state = ddc_path->ucMuxState[enum_id];
697 break;
698 }
699 record = (ATOM_COMMON_RECORD_HEADER *)
700 ((char *)record + record->ucRecordSize);
701 }
702 }
703 }
771fe6b9
JG		 704 }
705 }
706
eed45b30 707 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 708 ddc_bus.valid = false;
709 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 710 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 711 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 712 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
713 if (le16_to_cpu(path->usConnObjectId) ==
714 le16_to_cpu(con_obj->asObjects[j].
715 usObjectID)) {
716 ATOM_COMMON_RECORD_HEADER
717 *record =
718 (ATOM_COMMON_RECORD_HEADER
719 *)
720 (ctx->bios + data_offset +
721 le16_to_cpu(con_obj->
722 asObjects[j].
723 usRecordOffset));
724 ATOM_I2C_RECORD *i2c_record;
eed45b30 725 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 726 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 727
771fe6b9
JG		 728 while (record->ucRecordType > 0
729 && record->
730 ucRecordType <=
731 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 732 switch (record->ucRecordType) {
771fe6b9
JG		 733 case ATOM_I2C_RECORD_TYPE:
734 i2c_record =
eed45b30
AD		 735 (ATOM_I2C_RECORD *)
736 record;
d3f420d1
AD		 737 i2c_config =
738 (ATOM_I2C_ID_CONFIG_ACCESS *)
739 &i2c_record->sucI2cId;
eed45b30 740 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 741 i2c_config->
742 ucAccess);
eed45b30
AD		 743 break;
744 case ATOM_HPD_INT_RECORD_TYPE:
745 hpd_record =
746 (ATOM_HPD_INT_RECORD *)
747 record;
748 gpio = radeon_lookup_gpio(rdev,
749 hpd_record->ucHPDIntGPIOID);
750 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
751 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 752 break;
753 }
754 record =
755 (ATOM_COMMON_RECORD_HEADER
756 *) ((char *)record
757 +
758 record->
759 ucRecordSize);
760 }
761 break;
762 }
763 }
eed45b30 764 }
771fe6b9 765
bcc1c2a1 766 /* needed for aux chan transactions */
8e36ed00 767 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 768
705af9c7
AD		 769 conn_id = le16_to_cpu(path->usConnObjectId);
770
771 if (!radeon_atom_apply_quirks
772 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 773 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 774 continue;
775
771fe6b9 776 radeon_add_atom_connector(dev,
705af9c7 777 conn_id,
771fe6b9
JG		 778 le16_to_cpu(path->
779 usDeviceTag),
780 connector_type, &ddc_bus,
5137ee94 781 igp_lane_info,
eed45b30 782 connector_object_id,
26b5bc98
AD		 783 &hpd,
784 &router);
771fe6b9
JG		 785
786 }
787 }
788
789 radeon_link_encoder_connector(dev);
790
791 return true;
792}
793
b75fad06
AD		 794static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
795 int connector_type,
796 uint16_t devices)
797{
798 struct radeon_device *rdev = dev->dev_private;
799
800 if (rdev->flags & RADEON_IS_IGP) {
801 return supported_devices_connector_object_id_convert
802 [connector_type];
803 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
804 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
805 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
806 struct radeon_mode_info *mode_info = &rdev->mode_info;
807 struct atom_context *ctx = mode_info->atom_context;
808 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
809 uint16_t size, data_offset;
810 uint8_t frev, crev;
811 ATOM_XTMDS_INFO *xtmds;
812
a084e6ee
AD		 813 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
814 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 815
a084e6ee
AD		 816 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
817 if (connector_type == DRM_MODE_CONNECTOR_DVII)
818 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
819 else
820 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
821 } else {
822 if (connector_type == DRM_MODE_CONNECTOR_DVII)
823 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
824 else
825 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
826 }
827 } else
828 return supported_devices_connector_object_id_convert
829 [connector_type];
b75fad06
AD		 830 } else {
831 return supported_devices_connector_object_id_convert
832 [connector_type];
833 }
834}
835
771fe6b9
JG		 836struct bios_connector {
837 bool valid;
705af9c7 838 uint16_t line_mux;
771fe6b9
JG		 839 uint16_t devices;
840 int connector_type;
841 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 842 struct radeon_hpd hpd;
771fe6b9
JG		 843};
844
845bool radeon_get_atom_connector_info_from_supported_devices_table(struct
846 drm_device
847 *dev)
848{
849 struct radeon_device *rdev = dev->dev_private;
850 struct radeon_mode_info *mode_info = &rdev->mode_info;
851 struct atom_context *ctx = mode_info->atom_context;
852 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
853 uint16_t size, data_offset;
854 uint8_t frev, crev;
855 uint16_t device_support;
856 uint8_t dac;
857 union atom_supported_devices *supported_devices;
eed45b30 858 int i, j, max_device;
f49d273d
PB		 859 struct bios_connector *bios_connectors;
860 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 861 struct radeon_router router;
862
863 router.valid = false;
771fe6b9 864
f49d273d
PB		 865 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
866 if (!bios_connectors)
867 return false;
868
869 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
870 &data_offset)) {
871 kfree(bios_connectors);
a084e6ee 872 return false;
f49d273d 873 }
771fe6b9
JG		 874
875 supported_devices =
876 (union atom_supported_devices *)(ctx->bios + data_offset);
877
878 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
879
eed45b30
AD		 880 if (frev > 1)
881 max_device = ATOM_MAX_SUPPORTED_DEVICE;
882 else
883 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
884
885 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 886 ATOM_CONNECTOR_INFO_I2C ci =
887 supported_devices->info.asConnInfo[i];
888
889 bios_connectors[i].valid = false;
890
891 if (!(device_support & (1 << i))) {
892 continue;
893 }
894
895 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 896 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 897 continue;
898 }
899
771fe6b9
JG		 900 bios_connectors[i].connector_type =
901 supported_devices_connector_convert[ci.sucConnectorInfo.
902 sbfAccess.
903 bfConnectorType];
904
905 if (bios_connectors[i].connector_type ==
906 DRM_MODE_CONNECTOR_Unknown)
907 continue;
908
909 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
910
d3f420d1
AD		 911 bios_connectors[i].line_mux =
912 ci.sucI2cId.ucAccess;
771fe6b9
JG		 913
914 /* give tv unique connector ids */
915 if (i == ATOM_DEVICE_TV1_INDEX) {
916 bios_connectors[i].ddc_bus.valid = false;
917 bios_connectors[i].line_mux = 50;
918 } else if (i == ATOM_DEVICE_TV2_INDEX) {
919 bios_connectors[i].ddc_bus.valid = false;
920 bios_connectors[i].line_mux = 51;
921 } else if (i == ATOM_DEVICE_CV_INDEX) {
922 bios_connectors[i].ddc_bus.valid = false;
923 bios_connectors[i].line_mux = 52;
924 } else
925 bios_connectors[i].ddc_bus =
eed45b30
AD		 926 radeon_lookup_i2c_gpio(rdev,
927 bios_connectors[i].line_mux);
928
929 if ((crev > 1) && (frev > 1)) {
930 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
931 switch (isb) {
932 case 0x4:
933 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
934 break;
935 case 0xa:
936 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
937 break;
938 default:
939 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
940 break;
941 }
942 } else {
943 if (i == ATOM_DEVICE_DFP1_INDEX)
944 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
945 else if (i == ATOM_DEVICE_DFP2_INDEX)
946 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
947 else
948 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
949 }
771fe6b9
JG		 950
951 /* Always set the connector type to VGA for CRT1/CRT2. if they are
952 * shared with a DVI port, we'll pick up the DVI connector when we
953 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
954 */
955 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
956 bios_connectors[i].connector_type =
957 DRM_MODE_CONNECTOR_VGA;
958
959 if (!radeon_atom_apply_quirks
960 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 961 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
962 &bios_connectors[i].hpd))
771fe6b9
JG		 963 continue;
964
965 bios_connectors[i].valid = true;
966 bios_connectors[i].devices = (1 << i);
967
968 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
969 radeon_add_atom_encoder(dev,
5137ee94 970 radeon_get_encoder_enum(dev,
771fe6b9
JG		 971 (1 << i),
972 dac),
973 (1 << i));
974 else
975 radeon_add_legacy_encoder(dev,
5137ee94 976 radeon_get_encoder_enum(dev,
f56cd64f 977 (1 << i),
771fe6b9
JG		 978 dac),
979 (1 << i));
980 }
981
982 /* combine shared connectors */
eed45b30 983 for (i = 0; i < max_device; i++) {
771fe6b9 984 if (bios_connectors[i].valid) {
eed45b30 985 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 986 if (bios_connectors[j].valid && (i != j)) {
987 if (bios_connectors[i].line_mux ==
988 bios_connectors[j].line_mux) {
f56cd64f
AD		 989 /* make sure not to combine LVDS */
990 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
991 bios_connectors[i].line_mux = 53;
992 bios_connectors[i].ddc_bus.valid = false;
993 continue;
994 }
995 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
996 bios_connectors[j].line_mux = 53;
997 bios_connectors[j].ddc_bus.valid = false;
998 continue;
999 }
1000 /* combine analog and digital for DVI-I */
1001 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1002 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1003 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1004 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1005 bios_connectors[i].devices |=
1006 bios_connectors[j].devices;
1007 bios_connectors[i].connector_type =
1008 DRM_MODE_CONNECTOR_DVII;
1009 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 1010 bios_connectors[i].hpd =
1011 bios_connectors[j].hpd;
f56cd64f 1012 bios_connectors[j].valid = false;
771fe6b9
JG		 1013 }
1014 }
1015 }
1016 }
1017 }
1018 }
1019
1020 /* add the connectors */
eed45b30 1021 for (i = 0; i < max_device; i++) {
b75fad06
AD		 1022 if (bios_connectors[i].valid) {
1023 uint16_t connector_object_id =
1024 atombios_get_connector_object_id(dev,
1025 bios_connectors[i].connector_type,
1026 bios_connectors[i].devices);
771fe6b9
JG		 1027 radeon_add_atom_connector(dev,
1028 bios_connectors[i].line_mux,
1029 bios_connectors[i].devices,
1030 bios_connectors[i].
1031 connector_type,
1032 &bios_connectors[i].ddc_bus,
5137ee94 1033 0,
eed45b30 1034 connector_object_id,
26b5bc98
AD		 1035 &bios_connectors[i].hpd,
1036 &router);
b75fad06 1037 }
771fe6b9
JG		 1038 }
1039
1040 radeon_link_encoder_connector(dev);
1041
f49d273d 1042 kfree(bios_connectors);
771fe6b9
JG		 1043 return true;
1044}
1045
1046union firmware_info {
1047 ATOM_FIRMWARE_INFO info;
1048 ATOM_FIRMWARE_INFO_V1_2 info_12;
1049 ATOM_FIRMWARE_INFO_V1_3 info_13;
1050 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1051 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 1052};
1053
1054bool radeon_atom_get_clock_info(struct drm_device *dev)
1055{
1056 struct radeon_device *rdev = dev->dev_private;
1057 struct radeon_mode_info *mode_info = &rdev->mode_info;
1058 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1059 union firmware_info *firmware_info;
1060 uint8_t frev, crev;
1061 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1062 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1063 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1064 struct radeon_pll *spll = &rdev->clock.spll;
1065 struct radeon_pll *mpll = &rdev->clock.mpll;
1066 uint16_t data_offset;
1067
a084e6ee
AD		 1068 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1069 &frev, &crev, &data_offset)) {
1070 firmware_info =
1071 (union firmware_info *)(mode_info->atom_context->bios +
1072 data_offset);
771fe6b9
JG		 1073 /* pixel clocks */
1074 p1pll->reference_freq =
1075 le16_to_cpu(firmware_info->info.usReferenceClock);
1076 p1pll->reference_div = 0;
1077
bc293e58
MF		 1078 if (crev < 2)
1079 p1pll->pll_out_min =
1080 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1081 else
1082 p1pll->pll_out_min =
1083 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1084 p1pll->pll_out_max =
1085 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1086
86cb2bbf
AD		 1087 if (crev >= 4) {
1088 p1pll->lcd_pll_out_min =
1089 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1090 if (p1pll->lcd_pll_out_min == 0)
1091 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1092 p1pll->lcd_pll_out_max =
1093 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1094 if (p1pll->lcd_pll_out_max == 0)
1095 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1096 } else {
1097 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1098 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1099 }
1100
771fe6b9
JG		 1101 if (p1pll->pll_out_min == 0) {
1102 if (ASIC_IS_AVIVO(rdev))
1103 p1pll->pll_out_min = 64800;
1104 else
1105 p1pll->pll_out_min = 20000;
8f552a66
AD		 1106 } else if (p1pll->pll_out_min > 64800) {
1107 /* Limiting the pll output range is a good thing generally as
1108 * it limits the number of possible pll combinations for a given
1109 * frequency presumably to the ones that work best on each card.
1110 * However, certain duallink DVI monitors seem to like
1111 * pll combinations that would be limited by this at least on
1112 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1113 * family.
1114 */
b27b6375
AD		 1115 if (!radeon_new_pll)
1116 p1pll->pll_out_min = 64800;
771fe6b9
JG		 1117 }
1118
1119 p1pll->pll_in_min =
1120 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1121 p1pll->pll_in_max =
1122 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1123
1124 *p2pll = *p1pll;
1125
1126 /* system clock */
1127 spll->reference_freq =
1128 le16_to_cpu(firmware_info->info.usReferenceClock);
1129 spll->reference_div = 0;
1130
1131 spll->pll_out_min =
1132 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1133 spll->pll_out_max =
1134 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1135
1136 /* ??? */
1137 if (spll->pll_out_min == 0) {
1138 if (ASIC_IS_AVIVO(rdev))
1139 spll->pll_out_min = 64800;
1140 else
1141 spll->pll_out_min = 20000;
1142 }
1143
1144 spll->pll_in_min =
1145 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1146 spll->pll_in_max =
1147 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1148
1149 /* memory clock */
1150 mpll->reference_freq =
1151 le16_to_cpu(firmware_info->info.usReferenceClock);
1152 mpll->reference_div = 0;
1153
1154 mpll->pll_out_min =
1155 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1156 mpll->pll_out_max =
1157 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1158
1159 /* ??? */
1160 if (mpll->pll_out_min == 0) {
1161 if (ASIC_IS_AVIVO(rdev))
1162 mpll->pll_out_min = 64800;
1163 else
1164 mpll->pll_out_min = 20000;
1165 }
1166
1167 mpll->pll_in_min =
1168 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1169 mpll->pll_in_max =
1170 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1171
1172 rdev->clock.default_sclk =
1173 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1174 rdev->clock.default_mclk =
1175 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1176
bcc1c2a1
AD		 1177 if (ASIC_IS_DCE4(rdev)) {
1178 rdev->clock.default_dispclk =
1179 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1180 if (rdev->clock.default_dispclk == 0)
1181 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1182 rdev->clock.dp_extclk =
1183 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1184 }
1185 *dcpll = *p1pll;
1186
771fe6b9
JG		 1187 return true;
1188 }
bcc1c2a1 1189
771fe6b9
JG		 1190 return false;
1191}
1192
06b6476d
AD		 1193union igp_info {
1194 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1195 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1196};
1197
1198bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1199{
1200 struct radeon_mode_info *mode_info = &rdev->mode_info;
1201 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1202 union igp_info *igp_info;
1203 u8 frev, crev;
1204 u16 data_offset;
1205
4c70b2ea
AD		 1206 /* sideport is AMD only */
1207 if (rdev->family == CHIP_RS600)
1208 return false;
1209
a084e6ee
AD		 1210 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1211 &frev, &crev, &data_offset)) {
1212 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1213 data_offset);
06b6476d
AD		 1214 switch (crev) {
1215 case 1:
4c70b2ea
AD		 1216 if (igp_info->info.ulBootUpMemoryClock)
1217 return true;
06b6476d
AD		 1218 break;
1219 case 2:
4b80d954 1220 if (igp_info->info_2.ulBootUpSidePortClock)
06b6476d
AD		 1221 return true;
1222 break;
1223 default:
1224 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1225 break;
1226 }
1227 }
1228 return false;
1229}
1230
445282db
DA		 1231bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1232 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1233{
1234 struct drm_device *dev = encoder->base.dev;
1235 struct radeon_device *rdev = dev->dev_private;
1236 struct radeon_mode_info *mode_info = &rdev->mode_info;
1237 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1238 uint16_t data_offset;
1239 struct _ATOM_TMDS_INFO *tmds_info;
1240 uint8_t frev, crev;
1241 uint16_t maxfreq;
1242 int i;
771fe6b9 1243
a084e6ee
AD		 1244 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1245 &frev, &crev, &data_offset)) {
1246 tmds_info =
1247 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1248 data_offset);
771fe6b9 1249
771fe6b9
JG		 1250 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1251 for (i = 0; i < 4; i++) {
1252 tmds->tmds_pll[i].freq =
1253 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1254 tmds->tmds_pll[i].value =
1255 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1256 tmds->tmds_pll[i].value |=
1257 (tmds_info->asMiscInfo[i].
1258 ucPLL_VCO_Gain & 0x3f) << 6;
1259 tmds->tmds_pll[i].value |=
1260 (tmds_info->asMiscInfo[i].
1261 ucPLL_DutyCycle & 0xf) << 12;
1262 tmds->tmds_pll[i].value |=
1263 (tmds_info->asMiscInfo[i].
1264 ucPLL_VoltageSwing & 0xf) << 16;
1265
d9fdaafb 1266 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1267 tmds->tmds_pll[i].freq,
1268 tmds->tmds_pll[i].value);
1269
1270 if (maxfreq == tmds->tmds_pll[i].freq) {
1271 tmds->tmds_pll[i].freq = 0xffffffff;
1272 break;
1273 }
1274 }
445282db 1275 return true;
771fe6b9 1276 }
445282db 1277 return false;
771fe6b9
JG		 1278}
1279
ebbe1cb9
AD		 1280static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1281 radeon_encoder
1282 *encoder,
1283 int id)
1284{
1285 struct drm_device *dev = encoder->base.dev;
1286 struct radeon_device *rdev = dev->dev_private;
1287 struct radeon_mode_info *mode_info = &rdev->mode_info;
1288 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1289 uint16_t data_offset;
1290 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1291 uint8_t frev, crev;
1292 struct radeon_atom_ss *ss = NULL;
279b215e 1293 int i;
ebbe1cb9
AD		 1294
1295 if (id > ATOM_MAX_SS_ENTRY)
1296 return NULL;
1297
a084e6ee
AD		 1298 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1299 &frev, &crev, &data_offset)) {
1300 ss_info =
1301 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1302
ebbe1cb9
AD		 1303 ss =
1304 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1305
1306 if (!ss)
1307 return NULL;
1308
279b215e
AD		 1309 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1310 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1311 ss->percentage =
1312 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1313 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1314 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1315 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1316 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1317 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1d3d51b6 1318 break;
279b215e
AD		 1319 }
1320 }
ebbe1cb9
AD		 1321 }
1322 return ss;
1323}
1324
771fe6b9
JG		 1325union lvds_info {
1326 struct _ATOM_LVDS_INFO info;
1327 struct _ATOM_LVDS_INFO_V12 info_12;
1328};
1329
1330struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1331 radeon_encoder
1332 *encoder)
1333{
1334 struct drm_device *dev = encoder->base.dev;
1335 struct radeon_device *rdev = dev->dev_private;
1336 struct radeon_mode_info *mode_info = &rdev->mode_info;
1337 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1338 uint16_t data_offset, misc;
771fe6b9
JG		 1339 union lvds_info *lvds_info;
1340 uint8_t frev, crev;
1341 struct radeon_encoder_atom_dig *lvds = NULL;
5137ee94 1342 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9 1343
a084e6ee
AD		 1344 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1345 &frev, &crev, &data_offset)) {
1346 lvds_info =
1347 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1348 lvds =
1349 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1350
1351 if (!lvds)
1352 return NULL;
1353
de2103e4 1354 lvds->native_mode.clock =
771fe6b9 1355 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1356 lvds->native_mode.hdisplay =
771fe6b9 1357 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1358 lvds->native_mode.vdisplay =
771fe6b9 1359 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1360 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1361 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1362 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1363 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1364 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1365 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1366 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1367 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1368 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1369 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1370 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1371 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1372 lvds->panel_pwr_delay =
1373 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1374 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1375
1376 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1377 if (misc & ATOM_VSYNC_POLARITY)
1378 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1379 if (misc & ATOM_HSYNC_POLARITY)
1380 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1381 if (misc & ATOM_COMPOSITESYNC)
1382 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1383 if (misc & ATOM_INTERLACE)
1384 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1385 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1386 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1387
de2103e4
AD		 1388 /* set crtc values */
1389 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1390
ebbe1cb9
AD		 1391 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1392
7c27f87d 1393 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 1394 if (radeon_new_pll == 0)
1395 lvds->pll_algo = PLL_ALGO_LEGACY;
1396 else
1397 lvds->pll_algo = PLL_ALGO_NEW;
1398 } else {
1399 if (radeon_new_pll == 1)
1400 lvds->pll_algo = PLL_ALGO_NEW;
7c27f87d
AD		 1401 else
1402 lvds->pll_algo = PLL_ALGO_LEGACY;
383be5d1 1403 }
7c27f87d 1404
771fe6b9 1405 encoder->native_mode = lvds->native_mode;
5137ee94
AD		 1406
1407 if (encoder_enum == 2)
1408 lvds->linkb = true;
1409 else
1410 lvds->linkb = false;
1411
771fe6b9
JG		 1412 }
1413 return lvds;
1414}
1415
6fe7ac3f
AD		 1416struct radeon_encoder_primary_dac *
1417radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1418{
1419 struct drm_device *dev = encoder->base.dev;
1420 struct radeon_device *rdev = dev->dev_private;
1421 struct radeon_mode_info *mode_info = &rdev->mode_info;
1422 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1423 uint16_t data_offset;
1424 struct _COMPASSIONATE_DATA *dac_info;
1425 uint8_t frev, crev;
1426 uint8_t bg, dac;
6fe7ac3f
AD		 1427 struct radeon_encoder_primary_dac *p_dac = NULL;
1428
a084e6ee
AD		 1429 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1430 &frev, &crev, &data_offset)) {
1431 dac_info = (struct _COMPASSIONATE_DATA *)
1432 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1433
6fe7ac3f
AD		 1434 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1435
1436 if (!p_dac)
1437 return NULL;
1438
1439 bg = dac_info->ucDAC1_BG_Adjustment;
1440 dac = dac_info->ucDAC1_DAC_Adjustment;
1441 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1442
1443 }
1444 return p_dac;
1445}
1446
4ce001ab 1447bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1448 struct drm_display_mode *mode)
4ce001ab
DA		 1449{
1450 struct radeon_mode_info *mode_info = &rdev->mode_info;
1451 ATOM_ANALOG_TV_INFO *tv_info;
1452 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1453 ATOM_DTD_FORMAT *dtd_timings;
1454 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1455 u8 frev, crev;
5a9bcacc 1456 u16 data_offset, misc;
4ce001ab 1457
a084e6ee
AD		 1458 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1459 &frev, &crev, &data_offset))
1460 return false;
4ce001ab
DA		 1461
1462 switch (crev) {
1463 case 1:
1464 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1465 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1466 return false;
1467
5a9bcacc
AD		 1468 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1469 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1470 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1471 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1472 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1473
1474 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1475 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1476 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1477 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1478 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1479
1480 mode->flags = 0;
1481 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1482 if (misc & ATOM_VSYNC_POLARITY)
1483 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1484 if (misc & ATOM_HSYNC_POLARITY)
1485 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1486 if (misc & ATOM_COMPOSITESYNC)
1487 mode->flags |= DRM_MODE_FLAG_CSYNC;
1488 if (misc & ATOM_INTERLACE)
1489 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1490 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1491 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1492
1493 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1494
1495 if (index == 1) {
1496 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1497 mode->crtc_htotal -= 1;
1498 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1499 }
1500 break;
1501 case 2:
1502 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1503 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1504 return false;
1505
1506 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1507 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1508 le16_to_cpu(dtd_timings->usHBlanking_Time);
1509 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1510 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1511 le16_to_cpu(dtd_timings->usHSyncOffset);
1512 mode->crtc_hsync_end = mode->crtc_hsync_start +
1513 le16_to_cpu(dtd_timings->usHSyncWidth);
1514
1515 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1516 le16_to_cpu(dtd_timings->usVBlanking_Time);
1517 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1518 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1519 le16_to_cpu(dtd_timings->usVSyncOffset);
1520 mode->crtc_vsync_end = mode->crtc_vsync_start +
1521 le16_to_cpu(dtd_timings->usVSyncWidth);
1522
1523 mode->flags = 0;
1524 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1525 if (misc & ATOM_VSYNC_POLARITY)
1526 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1527 if (misc & ATOM_HSYNC_POLARITY)
1528 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1529 if (misc & ATOM_COMPOSITESYNC)
1530 mode->flags |= DRM_MODE_FLAG_CSYNC;
1531 if (misc & ATOM_INTERLACE)
1532 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1533 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1534 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1535
1536 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1537 break;
1538 }
1539 return true;
1540}
1541
d79766fa
AD		 1542enum radeon_tv_std
1543radeon_atombios_get_tv_info(struct radeon_device *rdev)
1544{
1545 struct radeon_mode_info *mode_info = &rdev->mode_info;
1546 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1547 uint16_t data_offset;
1548 uint8_t frev, crev;
1549 struct _ATOM_ANALOG_TV_INFO *tv_info;
1550 enum radeon_tv_std tv_std = TV_STD_NTSC;
1551
a084e6ee
AD		 1552 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1553 &frev, &crev, &data_offset)) {
d79766fa 1554
a084e6ee
AD		 1555 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1556 (mode_info->atom_context->bios + data_offset);
d79766fa 1557
a084e6ee
AD		 1558 switch (tv_info->ucTV_BootUpDefaultStandard) {
1559 case ATOM_TV_NTSC:
1560 tv_std = TV_STD_NTSC;
40f76d81 1561 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
a084e6ee
AD		 1562 break;
1563 case ATOM_TV_NTSCJ:
1564 tv_std = TV_STD_NTSC_J;
40f76d81 1565 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
a084e6ee
AD		 1566 break;
1567 case ATOM_TV_PAL:
1568 tv_std = TV_STD_PAL;
40f76d81 1569 DRM_DEBUG_KMS("Default TV standard: PAL\n");
a084e6ee
AD		 1570 break;
1571 case ATOM_TV_PALM:
1572 tv_std = TV_STD_PAL_M;
40f76d81 1573 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
a084e6ee
AD		 1574 break;
1575 case ATOM_TV_PALN:
1576 tv_std = TV_STD_PAL_N;
40f76d81 1577 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
a084e6ee
AD		 1578 break;
1579 case ATOM_TV_PALCN:
1580 tv_std = TV_STD_PAL_CN;
40f76d81 1581 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
a084e6ee
AD		 1582 break;
1583 case ATOM_TV_PAL60:
1584 tv_std = TV_STD_PAL_60;
40f76d81 1585 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
a084e6ee
AD		 1586 break;
1587 case ATOM_TV_SECAM:
1588 tv_std = TV_STD_SECAM;
40f76d81 1589 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
a084e6ee
AD		 1590 break;
1591 default:
1592 tv_std = TV_STD_NTSC;
40f76d81 1593 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
a084e6ee
AD		 1594 break;
1595 }
d79766fa
AD		 1596 }
1597 return tv_std;
1598}
1599
6fe7ac3f
AD		 1600struct radeon_encoder_tv_dac *
1601radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1602{
1603 struct drm_device *dev = encoder->base.dev;
1604 struct radeon_device *rdev = dev->dev_private;
1605 struct radeon_mode_info *mode_info = &rdev->mode_info;
1606 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1607 uint16_t data_offset;
1608 struct _COMPASSIONATE_DATA *dac_info;
1609 uint8_t frev, crev;
1610 uint8_t bg, dac;
6fe7ac3f
AD		 1611 struct radeon_encoder_tv_dac *tv_dac = NULL;
1612
a084e6ee
AD		 1613 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1614 &frev, &crev, &data_offset)) {
6fe7ac3f 1615
a084e6ee
AD		 1616 dac_info = (struct _COMPASSIONATE_DATA *)
1617 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1618
6fe7ac3f
AD		 1619 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1620
1621 if (!tv_dac)
1622 return NULL;
1623
1624 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1625 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1626 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1627
1628 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1629 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1630 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1631
1632 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1633 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1634 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1635
d79766fa 1636 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1637 }
1638 return tv_dac;
1639}
1640
29fb52ca
AD		 1641static const char *thermal_controller_names[] = {
1642 "NONE",
678e7dfa
AD		 1643 "lm63",
1644 "adm1032",
1645 "adm1030",
1646 "max6649",
1647 "lm64",
1648 "f75375",
1649 "asc7xxx",
29fb52ca
AD		 1650};
1651
1652static const char *pp_lib_thermal_controller_names[] = {
1653 "NONE",
678e7dfa
AD		 1654 "lm63",
1655 "adm1032",
1656 "adm1030",
1657 "max6649",
1658 "lm64",
1659 "f75375",
29fb52ca
AD		 1660 "RV6xx",
1661 "RV770",
678e7dfa 1662 "adt7473",
49f65982
AD		 1663 "External GPIO",
1664 "Evergreen",
678e7dfa 1665 "adt7473 with internal",
49f65982 1666
29fb52ca
AD		 1667};
1668
56278a8e
AD		 1669union power_info {
1670 struct _ATOM_POWERPLAY_INFO info;
1671 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1672 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1673 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1674};
1675
1676void radeon_atombios_get_power_modes(struct radeon_device *rdev)
771fe6b9 1677{
56278a8e
AD		 1678 struct radeon_mode_info *mode_info = &rdev->mode_info;
1679 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1680 u16 data_offset;
1681 u8 frev, crev;
1682 u32 misc, misc2 = 0, sclk, mclk;
1683 union power_info *power_info;
1684 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1685 struct _ATOM_PPLIB_STATE *power_state;
1686 int num_modes = 0, i, j;
1687 int state_index = 0, mode_index = 0;
29fb52ca 1688 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1689
a48b9b4e 1690 rdev->pm.default_power_state_index = -1;
56278a8e 1691
a084e6ee
AD		 1692 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1693 &frev, &crev, &data_offset)) {
1694 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
56278a8e 1695 if (frev < 4) {
29fb52ca
AD		 1696 /* add the i2c bus for thermal/fan chip */
1697 if (power_info->info.ucOverdriveThermalController > 0) {
1698 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1699 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1700 power_info->info.ucOverdriveControllerAddress >> 1);
1701 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
f376b94f 1702 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1703 if (rdev->pm.i2c_bus) {
1704 struct i2c_board_info info = { };
1705 const char *name = thermal_controller_names[power_info->info.
1706 ucOverdriveThermalController];
1707 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1708 strlcpy(info.type, name, sizeof(info.type));
1709 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1710 }
29fb52ca 1711 }
56278a8e
AD		 1712 num_modes = power_info->info.ucNumOfPowerModeEntries;
1713 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1714 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
02b17cc0 1715 /* last mode is usually default, array is low to high */
56278a8e
AD		 1716 for (i = 0; i < num_modes; i++) {
1717 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1718 switch (frev) {
1719 case 1:
1720 rdev->pm.power_state[state_index].num_clock_modes = 1;
1721 rdev->pm.power_state[state_index].clock_info[0].mclk =
1722 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1723 rdev->pm.power_state[state_index].clock_info[0].sclk =
1724 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1725 /* skip invalid modes */
1726 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1727 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1728 continue;
79daedc9 1729 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1730 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1731 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
84d88f4c
AD		 1732 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1733 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1734 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1735 VOLTAGE_GPIO;
1736 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1737 radeon_lookup_gpio(rdev,
1738 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1739 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1740 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1741 true;
1742 else
1743 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1744 false;
1745 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1746 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1747 VOLTAGE_VDDC;
1748 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1749 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1750 }
d7311171 1751 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9 1752 rdev->pm.power_state[state_index].misc = misc;
0ec0e74f
AD		 1753 /* order matters! */
1754 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1755 rdev->pm.power_state[state_index].type =
1756 POWER_STATE_TYPE_POWERSAVE;
1757 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1758 rdev->pm.power_state[state_index].type =
1759 POWER_STATE_TYPE_BATTERY;
1760 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1761 rdev->pm.power_state[state_index].type =
1762 POWER_STATE_TYPE_BATTERY;
1763 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1764 rdev->pm.power_state[state_index].type =
1765 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1766 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1767 rdev->pm.power_state[state_index].type =
1768 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1769 rdev->pm.power_state[state_index].flags &=
d7311171 1770 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1771 }
56278a8e 1772 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1773 rdev->pm.power_state[state_index].type =
1774 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1775 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1776 rdev->pm.power_state[state_index].default_clock_mode =
1777 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1778 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1779 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1780 } else if (state_index == 0) {
1781 rdev->pm.power_state[state_index].clock_info[0].flags |=
1782 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1783 }
1784 state_index++;
1785 break;
1786 case 2:
1787 rdev->pm.power_state[state_index].num_clock_modes = 1;
1788 rdev->pm.power_state[state_index].clock_info[0].mclk =
1789 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1790 rdev->pm.power_state[state_index].clock_info[0].sclk =
1791 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1792 /* skip invalid modes */
1793 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1794 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1795 continue;
79daedc9 1796 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1797 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1798 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1799 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1800 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1801 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1802 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1803 VOLTAGE_GPIO;
1804 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1805 radeon_lookup_gpio(rdev,
1806 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1807 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1808 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1809 true;
1810 else
1811 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1812 false;
1813 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1814 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1815 VOLTAGE_VDDC;
1816 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1817 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1818 }
d7311171 1819 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1820 rdev->pm.power_state[state_index].misc = misc;
1821 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1822 /* order matters! */
1823 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1824 rdev->pm.power_state[state_index].type =
1825 POWER_STATE_TYPE_POWERSAVE;
1826 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1827 rdev->pm.power_state[state_index].type =
1828 POWER_STATE_TYPE_BATTERY;
1829 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1830 rdev->pm.power_state[state_index].type =
1831 POWER_STATE_TYPE_BATTERY;
1832 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1833 rdev->pm.power_state[state_index].type =
1834 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1835 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1836 rdev->pm.power_state[state_index].type =
1837 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1838 rdev->pm.power_state[state_index].flags &=
d7311171 1839 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1840 }
0ec0e74f
AD		 1841 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1842 rdev->pm.power_state[state_index].type =
1843 POWER_STATE_TYPE_BALANCED;
a48b9b4e
AD		 1844 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1845 rdev->pm.power_state[state_index].flags &=
d7311171 1846 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1847 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1848 rdev->pm.power_state[state_index].type =
1849 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1850 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1851 rdev->pm.power_state[state_index].default_clock_mode =
1852 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1853 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1854 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1855 } else if (state_index == 0) {
1856 rdev->pm.power_state[state_index].clock_info[0].flags |=
1857 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1858 }
1859 state_index++;
1860 break;
1861 case 3:
1862 rdev->pm.power_state[state_index].num_clock_modes = 1;
1863 rdev->pm.power_state[state_index].clock_info[0].mclk =
1864 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1865 rdev->pm.power_state[state_index].clock_info[0].sclk =
1866 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1867 /* skip invalid modes */
1868 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1869 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1870 continue;
79daedc9 1871 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1872 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1873 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1874 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1875 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1876 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1877 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1878 VOLTAGE_GPIO;
1879 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1880 radeon_lookup_gpio(rdev,
1881 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1882 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1883 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1884 true;
1885 else
1886 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1887 false;
1888 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1889 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1890 VOLTAGE_VDDC;
1891 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1892 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1893 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1894 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1895 true;
1896 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1897 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1898 }
1899 }
d7311171 1900 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1901 rdev->pm.power_state[state_index].misc = misc;
1902 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1903 /* order matters! */
1904 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1905 rdev->pm.power_state[state_index].type =
1906 POWER_STATE_TYPE_POWERSAVE;
1907 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1908 rdev->pm.power_state[state_index].type =
1909 POWER_STATE_TYPE_BATTERY;
1910 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1911 rdev->pm.power_state[state_index].type =
1912 POWER_STATE_TYPE_BATTERY;
1913 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1914 rdev->pm.power_state[state_index].type =
1915 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1916 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1917 rdev->pm.power_state[state_index].type =
1918 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1919 rdev->pm.power_state[state_index].flags &=
d7311171 1920 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1921 }
0ec0e74f
AD		 1922 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1923 rdev->pm.power_state[state_index].type =
1924 POWER_STATE_TYPE_BALANCED;
56278a8e 1925 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1926 rdev->pm.power_state[state_index].type =
1927 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1928 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1929 rdev->pm.power_state[state_index].default_clock_mode =
1930 &rdev->pm.power_state[state_index].clock_info[0];
d7311171
AD		 1931 } else if (state_index == 0) {
1932 rdev->pm.power_state[state_index].clock_info[0].flags |=
1933 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1934 }
1935 state_index++;
1936 break;
1937 }
1938 }
02b17cc0 1939 /* last mode is usually default */
a48b9b4e 1940 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 1941 rdev->pm.power_state[state_index - 1].type =
1942 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1943 rdev->pm.default_power_state_index = state_index - 1;
02b17cc0
AD		 1944 rdev->pm.power_state[state_index - 1].default_clock_mode =
1945 &rdev->pm.power_state[state_index - 1].clock_info[0];
a48b9b4e 1946 rdev->pm.power_state[state_index].flags &=
d7311171 1947 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1948 rdev->pm.power_state[state_index].misc = 0;
1949 rdev->pm.power_state[state_index].misc2 = 0;
02b17cc0 1950 }
49f65982 1951 } else {
c5e8ce61
AD		 1952 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1953 uint8_t fw_frev, fw_crev;
1954 uint16_t fw_data_offset, vddc = 0;
1955 union firmware_info *firmware_info;
1956 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1957
1958 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1959 &fw_frev, &fw_crev, &fw_data_offset)) {
1960 firmware_info =
1961 (union firmware_info *)(mode_info->atom_context->bios +
1962 fw_data_offset);
1963 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1964 }
1965
29fb52ca 1966 /* add the i2c bus for thermal/fan chip */
678e7dfa 1967 if (controller->ucType > 0) {
21a8122a 1968 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
29fb52ca 1969 DRM_INFO("Internal thermal controller %s fan control\n",
678e7dfa 1970 (controller->ucFanParameters &
29fb52ca 1971 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
21a8122a
AD		 1972 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1973 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1974 DRM_INFO("Internal thermal controller %s fan control\n",
1975 (controller->ucFanParameters &
1976 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1977 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1978 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1979 DRM_INFO("Internal thermal controller %s fan control\n",
1980 (controller->ucFanParameters &
1981 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1982 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
678e7dfa 1983 } else if ((controller->ucType ==
49f65982 1984 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
678e7dfa 1985 (controller->ucType ==
49f65982
AD		 1986 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1987 DRM_INFO("Special thermal controller config\n");
29fb52ca
AD		 1988 } else {
1989 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
678e7dfa
AD		 1990 pp_lib_thermal_controller_names[controller->ucType],
1991 controller->ucI2cAddress >> 1,
1992 (controller->ucFanParameters &
29fb52ca 1993 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
678e7dfa 1994 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
f376b94f 1995 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1996 if (rdev->pm.i2c_bus) {
1997 struct i2c_board_info info = { };
1998 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1999 info.addr = controller->ucI2cAddress >> 1;
2000 strlcpy(info.type, name, sizeof(info.type));
2001 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2002 }
2003
29fb52ca
AD		 2004 }
2005 }
02b17cc0 2006 /* first mode is usually default, followed by low to high */
56278a8e
AD		 2007 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
2008 mode_index = 0;
2009 power_state = (struct _ATOM_PPLIB_STATE *)
2010 (mode_info->atom_context->bios +
2011 data_offset +
2012 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
2013 i * power_info->info_4.ucStateEntrySize);
2014 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2015 (mode_info->atom_context->bios +
2016 data_offset +
2017 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
2018 (power_state->ucNonClockStateIndex *
2019 power_info->info_4.ucNonClockSize));
56278a8e
AD		 2020 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
2021 if (rdev->flags & RADEON_IS_IGP) {
2022 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
2023 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
2024 (mode_info->atom_context->bios +
2025 data_offset +
2026 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2027 (power_state->ucClockStateIndices[j] *
2028 power_info->info_4.ucClockInfoSize));
2029 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
2030 sclk |= clock_info->ucLowEngineClockHigh << 16;
2031 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2032 /* skip invalid modes */
2033 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2034 continue;
aa1df0f2 2035 /* voltage works differently on IGPs */
56278a8e 2036 mode_index++;
49f65982
AD		 2037 } else if (ASIC_IS_DCE4(rdev)) {
2038 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2039 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2040 (mode_info->atom_context->bios +
2041 data_offset +
2042 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2043 (power_state->ucClockStateIndices[j] *
2044 power_info->info_4.ucClockInfoSize));
2045 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2046 sclk |= clock_info->ucEngineClockHigh << 16;
2047 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2048 mclk |= clock_info->ucMemoryClockHigh << 16;
2049 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2050 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2051 /* skip invalid modes */
2052 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2053 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2054 continue;
49f65982
AD		 2055 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2056 VOLTAGE_SW;
2057 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2058 clock_info->usVDDC;
2059 /* XXX usVDDCI */
2060 mode_index++;
56278a8e
AD		 2061 } else {
2062 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2063 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2064 (mode_info->atom_context->bios +
2065 data_offset +
2066 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2067 (power_state->ucClockStateIndices[j] *
2068 power_info->info_4.ucClockInfoSize));
2069 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2070 sclk |= clock_info->ucEngineClockHigh << 16;
2071 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2072 mclk |= clock_info->ucMemoryClockHigh << 16;
2073 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2074 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2075 /* skip invalid modes */
2076 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2077 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2078 continue;
56278a8e
AD		 2079 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2080 VOLTAGE_SW;
2081 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2082 clock_info->usVDDC;
2083 mode_index++;
2084 }
2085 }
2086 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2087 if (mode_index) {
845db70d 2088 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 2089 misc2 = le16_to_cpu(non_clock_info->usClassification);
79daedc9
AD		 2090 rdev->pm.power_state[state_index].misc = misc;
2091 rdev->pm.power_state[state_index].misc2 = misc2;
2092 rdev->pm.power_state[state_index].pcie_lanes =
845db70d
RM		 2093 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2094 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 2095 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2096 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2097 rdev->pm.power_state[state_index].type =
2098 POWER_STATE_TYPE_BATTERY;
2099 break;
2100 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2101 rdev->pm.power_state[state_index].type =
2102 POWER_STATE_TYPE_BALANCED;
2103 break;
2104 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2105 rdev->pm.power_state[state_index].type =
2106 POWER_STATE_TYPE_PERFORMANCE;
2107 break;
a44d2f37
AD		 2108 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2109 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2110 rdev->pm.power_state[state_index].type =
2111 POWER_STATE_TYPE_PERFORMANCE;
2112 break;
0ec0e74f 2113 }
a48b9b4e
AD		 2114 rdev->pm.power_state[state_index].flags = 0;
2115 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2116 rdev->pm.power_state[state_index].flags |=
d7311171 2117 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 2118 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 2119 rdev->pm.power_state[state_index].type =
2120 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2121 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 2122 rdev->pm.power_state[state_index].default_clock_mode =
2123 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
c5e8ce61
AD		 2124 /* patch the table values with the default slck/mclk from firmware info */
2125 for (j = 0; j < mode_index; j++) {
2126 rdev->pm.power_state[state_index].clock_info[j].mclk =
2127 rdev->clock.default_mclk;
2128 rdev->pm.power_state[state_index].clock_info[j].sclk =
2129 rdev->clock.default_sclk;
2130 if (vddc)
2131 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2132 vddc;
2133 }
56278a8e
AD		 2134 }
2135 state_index++;
2136 }
2137 }
d7311171
AD		 2138 /* if multiple clock modes, mark the lowest as no display */
2139 for (i = 0; i < state_index; i++) {
2140 if (rdev->pm.power_state[i].num_clock_modes > 1)
2141 rdev->pm.power_state[i].clock_info[0].flags |=
2142 RADEON_PM_MODE_NO_DISPLAY;
2143 }
02b17cc0 2144 /* first mode is usually default */
a48b9b4e 2145 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 2146 rdev->pm.power_state[0].type =
2147 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2148 rdev->pm.default_power_state_index = 0;
02b17cc0
AD		 2149 rdev->pm.power_state[0].default_clock_mode =
2150 &rdev->pm.power_state[0].clock_info[0];
2151 }
56278a8e
AD		 2152 }
2153 } else {
56278a8e 2154 /* add the default mode */
0ec0e74f
AD		 2155 rdev->pm.power_state[state_index].type =
2156 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2157 rdev->pm.power_state[state_index].num_clock_modes = 1;
2158 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2159 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2160 rdev->pm.power_state[state_index].default_clock_mode =
2161 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 2162 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2163 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2164 rdev->pm.default_power_state_index = state_index;
2165 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 2166 state_index++;
2167 }
02b17cc0 2168
56278a8e 2169 rdev->pm.num_power_states = state_index;
9038dfdf 2170
a48b9b4e
AD		 2171 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2172 rdev->pm.current_clock_mode_index = 0;
4d60173f 2173 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2174}
2175
771fe6b9 2176void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2177{
771fe6b9
JG		 2178 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2179 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2180
2181 args.ucEnable = enable;
2182
2183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2184}
2185
7433874e
RM		 2186uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2187{
2188 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2189 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2190
2191 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2192 return args.ulReturnEngineClock;
2193}
2194
2195uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2196{
2197 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2198 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2199
2200 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2201 return args.ulReturnMemoryClock;
2202}
2203
771fe6b9
JG		 2204void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2205 uint32_t eng_clock)
2206{
2207 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2208 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2209
2210 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2211
2212 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2213}
2214
2215void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2216 uint32_t mem_clock)
2217{
2218 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2219 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2220
2221 if (rdev->flags & RADEON_IS_IGP)
2222 return;
2223
2224 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2225
2226 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2227}
2228
7ac9aa5a
AD		 2229union set_voltage {
2230 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2231 struct _SET_VOLTAGE_PARAMETERS v1;
2232 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2233};
2234
2235void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2236{
2237 union set_voltage args;
2238 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2239 u8 frev, crev, volt_index = level;
2240
2241 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2242 return;
2243
2244 switch (crev) {
2245 case 1:
2246 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2247 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2248 args.v1.ucVoltageIndex = volt_index;
2249 break;
2250 case 2:
2251 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2252 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2253 args.v2.usVoltageLevel = cpu_to_le16(level);
2254 break;
2255 default:
2256 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2257 return;
2258 }
2259
2260 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2261}
2262
2263
2264
771fe6b9
JG		 2265void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2266{
2267 struct radeon_device *rdev = dev->dev_private;
2268 uint32_t bios_2_scratch, bios_6_scratch;
2269
2270 if (rdev->family >= CHIP_R600) {
4ce001ab 2271 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2272 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2273 } else {
4ce001ab 2274 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2275 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2276 }
2277
2278 /* let the bios control the backlight */
2279 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2280
2281 /* tell the bios not to handle mode switching */
2282 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2283
2284 if (rdev->family >= CHIP_R600) {
2285 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2286 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2287 } else {
2288 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2289 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2290 }
2291
2292}
2293
f657c2a7
YZ		 2294void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2295{
2296 uint32_t scratch_reg;
2297 int i;
2298
2299 if (rdev->family >= CHIP_R600)
2300 scratch_reg = R600_BIOS_0_SCRATCH;
2301 else
2302 scratch_reg = RADEON_BIOS_0_SCRATCH;
2303
2304 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2305 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2306}
2307
2308void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2309{
2310 uint32_t scratch_reg;
2311 int i;
2312
2313 if (rdev->family >= CHIP_R600)
2314 scratch_reg = R600_BIOS_0_SCRATCH;
2315 else
2316 scratch_reg = RADEON_BIOS_0_SCRATCH;
2317
2318 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2319 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2320}
2321
771fe6b9
JG		 2322void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2323{
2324 struct drm_device *dev = encoder->dev;
2325 struct radeon_device *rdev = dev->dev_private;
2326 uint32_t bios_6_scratch;
2327
2328 if (rdev->family >= CHIP_R600)
2329 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2330 else
2331 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2332
2333 if (lock)
2334 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2335 else
2336 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2337
2338 if (rdev->family >= CHIP_R600)
2339 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2340 else
2341 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2342}
2343
2344/* at some point we may want to break this out into individual functions */
2345void
2346radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2347 struct drm_encoder *encoder,
2348 bool connected)
2349{
2350 struct drm_device *dev = connector->dev;
2351 struct radeon_device *rdev = dev->dev_private;
2352 struct radeon_connector *radeon_connector =
2353 to_radeon_connector(connector);
2354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2355 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2356
2357 if (rdev->family >= CHIP_R600) {
2358 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2359 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2360 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2361 } else {
2362 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2363 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2364 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2365 }
2366
2367 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2368 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2369 if (connected) {
d9fdaafb 2370 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2371 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2372 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2373 } else {
d9fdaafb 2374 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2375 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2376 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2377 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2378 }
2379 }
2380 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2381 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2382 if (connected) {
d9fdaafb 2383 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2384 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2385 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2386 } else {
d9fdaafb 2387 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2388 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2389 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2390 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2391 }
2392 }
2393 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2394 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2395 if (connected) {
d9fdaafb 2396 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2397 bios_0_scratch |= ATOM_S0_LCD1;
2398 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2399 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2400 } else {
d9fdaafb 2401 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2402 bios_0_scratch &= ~ATOM_S0_LCD1;
2403 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2404 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2405 }
2406 }
2407 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2408 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2409 if (connected) {
d9fdaafb 2410 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2411 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2412 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2413 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2414 } else {
d9fdaafb 2415 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2416 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2417 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2418 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2419 }
2420 }
2421 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2422 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2423 if (connected) {
d9fdaafb 2424 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2425 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2426 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2427 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2428 } else {
d9fdaafb 2429 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2430 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2431 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2432 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2433 }
2434 }
2435 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2436 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2437 if (connected) {
d9fdaafb 2438 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2439 bios_0_scratch |= ATOM_S0_DFP1;
2440 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2441 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2442 } else {
d9fdaafb 2443 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2444 bios_0_scratch &= ~ATOM_S0_DFP1;
2445 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2446 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2447 }
2448 }
2449 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2450 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2451 if (connected) {
d9fdaafb 2452 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2453 bios_0_scratch |= ATOM_S0_DFP2;
2454 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2455 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2456 } else {
d9fdaafb 2457 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2458 bios_0_scratch &= ~ATOM_S0_DFP2;
2459 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2460 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2461 }
2462 }
2463 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2464 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2465 if (connected) {
d9fdaafb 2466 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2467 bios_0_scratch |= ATOM_S0_DFP3;
2468 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2469 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2470 } else {
d9fdaafb 2471 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2472 bios_0_scratch &= ~ATOM_S0_DFP3;
2473 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2474 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2475 }
2476 }
2477 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2478 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2479 if (connected) {
d9fdaafb 2480 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2481 bios_0_scratch |= ATOM_S0_DFP4;
2482 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2483 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2484 } else {
d9fdaafb 2485 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2486 bios_0_scratch &= ~ATOM_S0_DFP4;
2487 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2488 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2489 }
2490 }
2491 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2492 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2493 if (connected) {
d9fdaafb 2494 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2495 bios_0_scratch |= ATOM_S0_DFP5;
2496 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2497 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2498 } else {
d9fdaafb 2499 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2500 bios_0_scratch &= ~ATOM_S0_DFP5;
2501 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2502 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2503 }
2504 }
2505
2506 if (rdev->family >= CHIP_R600) {
2507 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2508 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2509 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2510 } else {
2511 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2512 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2513 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2514 }
2515}
2516
2517void
2518radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2519{
2520 struct drm_device *dev = encoder->dev;
2521 struct radeon_device *rdev = dev->dev_private;
2522 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2523 uint32_t bios_3_scratch;
2524
2525 if (rdev->family >= CHIP_R600)
2526 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2527 else
2528 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2529
2530 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2531 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2532 bios_3_scratch |= (crtc << 18);
2533 }
2534 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2535 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2536 bios_3_scratch |= (crtc << 24);
2537 }
2538 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2539 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2540 bios_3_scratch |= (crtc << 16);
2541 }
2542 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2543 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2544 bios_3_scratch |= (crtc << 20);
2545 }
2546 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2547 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2548 bios_3_scratch |= (crtc << 17);
2549 }
2550 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2551 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2552 bios_3_scratch |= (crtc << 19);
2553 }
2554 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2555 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2556 bios_3_scratch |= (crtc << 23);
2557 }
2558 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2559 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2560 bios_3_scratch |= (crtc << 25);
2561 }
2562
2563 if (rdev->family >= CHIP_R600)
2564 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2565 else
2566 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2567}
2568
2569void
2570radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2571{
2572 struct drm_device *dev = encoder->dev;
2573 struct radeon_device *rdev = dev->dev_private;
2574 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2575 uint32_t bios_2_scratch;
2576
2577 if (rdev->family >= CHIP_R600)
2578 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2579 else
2580 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2581
2582 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2583 if (on)
2584 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2585 else
2586 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2587 }
2588 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2589 if (on)
2590 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2591 else
2592 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2593 }
2594 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2595 if (on)
2596 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2597 else
2598 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2599 }
2600 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2601 if (on)
2602 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2603 else
2604 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2605 }
2606 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2607 if (on)
2608 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2609 else
2610 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2611 }
2612 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2613 if (on)
2614 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2615 else
2616 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2617 }
2618 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2619 if (on)
2620 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2621 else
2622 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2623 }
2624 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2625 if (on)
2626 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2627 else
2628 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2629 }
2630 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2631 if (on)
2632 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2633 else
2634 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2635 }
2636 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2637 if (on)
2638 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2639 else
2640 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2641 }
2642
2643 if (rdev->family >= CHIP_R600)
2644 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2645 else
2646 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2647}
Clone of davem's net-next-2.6 tree