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drm/radeon/kms: hpd cleanup
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 49 bool linkb, uint32_t igp_lane_info,
eed45b30
AD		 50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
771fe6b9
JG		 52
53/* from radeon_legacy_encoder.c */
54extern void
55radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
57
58union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62};
63
eed45b30
AD		 64static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
65 uint8_t id)
771fe6b9 66{
771fe6b9 67 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 72 uint16_t data_offset, size;
73 int i, num_indices;
771fe6b9
JG		 74
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 i2c.valid = false;
77
95beb690 78 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
95beb690
AD		 81 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
82 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
83
84 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 85 gpio = &i2c_info->asGPIO_Info[i];
86
87 if (gpio->sucI2cId.ucAccess == id) {
88 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
89 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
90 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
91 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
92 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
93 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
94 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
95 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
96 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
97 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
98 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
99 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
100 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
101 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
102 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
103 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
104
105 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
106 i2c.hw_capable = true;
107 else
108 i2c.hw_capable = false;
109
110 if (gpio->sucI2cId.ucAccess == 0xa0)
111 i2c.mm_i2c = true;
112 else
113 i2c.mm_i2c = false;
114
115 i2c.i2c_id = gpio->sucI2cId.ucAccess;
116
117 i2c.valid = true;
118 break;
119 }
d3f420d1
AD		 120 }
121 }
771fe6b9
JG		 122
123 return i2c;
124}
125
eed45b30
AD		 126static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
127 u8 id)
128{
129 struct atom_context *ctx = rdev->mode_info.atom_context;
130 struct radeon_gpio_rec gpio;
131 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
132 struct _ATOM_GPIO_PIN_LUT *gpio_info;
133 ATOM_GPIO_PIN_ASSIGNMENT *pin;
134 u16 data_offset, size;
135 int i, num_indices;
136
137 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
138 gpio.valid = false;
139
a084e6ee
AD		 140 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
141 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 142
a084e6ee
AD		 143 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
144 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 145
a084e6ee
AD		 146 for (i = 0; i < num_indices; i++) {
147 pin = &gpio_info->asGPIO_Pin[i];
148 if (id == pin->ucGPIO_ID) {
149 gpio.id = pin->ucGPIO_ID;
150 gpio.reg = pin->usGpioPin_AIndex * 4;
151 gpio.mask = (1 << pin->ucGpioPinBitShift);
152 gpio.valid = true;
153 break;
154 }
eed45b30
AD		 155 }
156 }
157
158 return gpio;
159}
160
161static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
162 struct radeon_gpio_rec *gpio)
163{
164 struct radeon_hpd hpd;
bcc1c2a1
AD		 165 u32 reg;
166
167 if (ASIC_IS_DCE4(rdev))
168 reg = EVERGREEN_DC_GPIO_HPD_A;
169 else
170 reg = AVIVO_DC_GPIO_HPD_A;
171
eed45b30 172 hpd.gpio = *gpio;
bcc1c2a1 173 if (gpio->reg == reg) {
eed45b30
AD		 174 switch(gpio->mask) {
175 case (1 << 0):
176 hpd.hpd = RADEON_HPD_1;
177 break;
178 case (1 << 8):
179 hpd.hpd = RADEON_HPD_2;
180 break;
181 case (1 << 16):
182 hpd.hpd = RADEON_HPD_3;
183 break;
184 case (1 << 24):
185 hpd.hpd = RADEON_HPD_4;
186 break;
187 case (1 << 26):
188 hpd.hpd = RADEON_HPD_5;
189 break;
190 case (1 << 28):
191 hpd.hpd = RADEON_HPD_6;
192 break;
193 default:
194 hpd.hpd = RADEON_HPD_NONE;
195 break;
196 }
197 } else
198 hpd.hpd = RADEON_HPD_NONE;
199 return hpd;
200}
201
771fe6b9
JG		 202static bool radeon_atom_apply_quirks(struct drm_device *dev,
203 uint32_t supported_device,
204 int *connector_type,
848577ee 205 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 206 uint16_t *line_mux,
207 struct radeon_hpd *hpd)
771fe6b9
JG		 208{
209
210 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
211 if ((dev->pdev->device == 0x791e) &&
212 (dev->pdev->subsystem_vendor == 0x1043) &&
213 (dev->pdev->subsystem_device == 0x826d)) {
214 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
215 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
216 *connector_type = DRM_MODE_CONNECTOR_DVID;
217 }
218
c86a9038
AD		 219 /* Asrock RS600 board lists the DVI port as HDMI */
220 if ((dev->pdev->device == 0x7941) &&
221 (dev->pdev->subsystem_vendor == 0x1849) &&
222 (dev->pdev->subsystem_device == 0x7941)) {
223 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
224 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
225 *connector_type = DRM_MODE_CONNECTOR_DVID;
226 }
227
771fe6b9
JG		 228 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
229 if ((dev->pdev->device == 0x7941) &&
230 (dev->pdev->subsystem_vendor == 0x147b) &&
231 (dev->pdev->subsystem_device == 0x2412)) {
232 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
233 return false;
234 }
235
236 /* Falcon NW laptop lists vga ddc line for LVDS */
237 if ((dev->pdev->device == 0x5653) &&
238 (dev->pdev->subsystem_vendor == 0x1462) &&
239 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 240 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 241 i2c_bus->valid = false;
848577ee
AD		 242 *line_mux = 53;
243 }
771fe6b9
JG		 244 }
245
4e3f9b78
AD		 246 /* HIS X1300 is DVI+VGA, not DVI+DVI */
247 if ((dev->pdev->device == 0x7146) &&
248 (dev->pdev->subsystem_vendor == 0x17af) &&
249 (dev->pdev->subsystem_device == 0x2058)) {
250 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
251 return false;
252 }
253
aa1a750e
DA		 254 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
255 if ((dev->pdev->device == 0x7142) &&
256 (dev->pdev->subsystem_vendor == 0x1458) &&
257 (dev->pdev->subsystem_device == 0x2134)) {
258 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
259 return false;
260 }
261
262
771fe6b9
JG		 263 /* Funky macbooks */
264 if ((dev->pdev->device == 0x71C5) &&
265 (dev->pdev->subsystem_vendor == 0x106b) &&
266 (dev->pdev->subsystem_device == 0x0080)) {
267 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
268 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
269 return false;
e1e8a5dd
AD		 270 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
271 *line_mux = 0x90;
771fe6b9
JG		 272 }
273
771fe6b9
JG		 274 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
275 if ((dev->pdev->device == 0x9598) &&
276 (dev->pdev->subsystem_vendor == 0x1043) &&
277 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 278 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 279 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 280 }
281 }
282
283 /* ASUS HD 3450 board lists the DVI port as HDMI */
284 if ((dev->pdev->device == 0x95C5) &&
285 (dev->pdev->subsystem_vendor == 0x1043) &&
286 (dev->pdev->subsystem_device == 0x01e2)) {
287 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 288 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 289 }
290 }
291
705af9c7
AD		 292 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
293 * HDMI + VGA reporting as HDMI
294 */
295 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
296 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
297 *connector_type = DRM_MODE_CONNECTOR_VGA;
298 *line_mux = 0;
299 }
300 }
301
3e5f8ff3
AD		 302 /* Acer laptop reports DVI-D as DVI-I */
303 if ((dev->pdev->device == 0x95c4) &&
304 (dev->pdev->subsystem_vendor == 0x1025) &&
305 (dev->pdev->subsystem_device == 0x013c)) {
306 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
307 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
308 *connector_type = DRM_MODE_CONNECTOR_DVID;
309 }
310
efa8450f
DA		 311 /* XFX Pine Group device rv730 reports no VGA DDC lines
312 * even though they are wired up to record 0x93
313 */
314 if ((dev->pdev->device == 0x9498) &&
315 (dev->pdev->subsystem_vendor == 0x1682) &&
316 (dev->pdev->subsystem_device == 0x2452)) {
317 struct radeon_device *rdev = dev->dev_private;
318 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
319 }
771fe6b9
JG		 320 return true;
321}
322
323const int supported_devices_connector_convert[] = {
324 DRM_MODE_CONNECTOR_Unknown,
325 DRM_MODE_CONNECTOR_VGA,
326 DRM_MODE_CONNECTOR_DVII,
327 DRM_MODE_CONNECTOR_DVID,
328 DRM_MODE_CONNECTOR_DVIA,
329 DRM_MODE_CONNECTOR_SVIDEO,
330 DRM_MODE_CONNECTOR_Composite,
331 DRM_MODE_CONNECTOR_LVDS,
332 DRM_MODE_CONNECTOR_Unknown,
333 DRM_MODE_CONNECTOR_Unknown,
334 DRM_MODE_CONNECTOR_HDMIA,
335 DRM_MODE_CONNECTOR_HDMIB,
336 DRM_MODE_CONNECTOR_Unknown,
337 DRM_MODE_CONNECTOR_Unknown,
338 DRM_MODE_CONNECTOR_9PinDIN,
339 DRM_MODE_CONNECTOR_DisplayPort
340};
341
b75fad06
AD		 342const uint16_t supported_devices_connector_object_id_convert[] = {
343 CONNECTOR_OBJECT_ID_NONE,
344 CONNECTOR_OBJECT_ID_VGA,
345 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
346 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
347 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
348 CONNECTOR_OBJECT_ID_COMPOSITE,
349 CONNECTOR_OBJECT_ID_SVIDEO,
350 CONNECTOR_OBJECT_ID_LVDS,
351 CONNECTOR_OBJECT_ID_9PIN_DIN,
352 CONNECTOR_OBJECT_ID_9PIN_DIN,
353 CONNECTOR_OBJECT_ID_DISPLAYPORT,
354 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
355 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
356 CONNECTOR_OBJECT_ID_SVIDEO
357};
358
771fe6b9
JG		 359const int object_connector_convert[] = {
360 DRM_MODE_CONNECTOR_Unknown,
361 DRM_MODE_CONNECTOR_DVII,
362 DRM_MODE_CONNECTOR_DVII,
363 DRM_MODE_CONNECTOR_DVID,
364 DRM_MODE_CONNECTOR_DVID,
365 DRM_MODE_CONNECTOR_VGA,
366 DRM_MODE_CONNECTOR_Composite,
367 DRM_MODE_CONNECTOR_SVIDEO,
368 DRM_MODE_CONNECTOR_Unknown,
705af9c7 369 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 370 DRM_MODE_CONNECTOR_9PinDIN,
371 DRM_MODE_CONNECTOR_Unknown,
372 DRM_MODE_CONNECTOR_HDMIA,
373 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 374 DRM_MODE_CONNECTOR_LVDS,
375 DRM_MODE_CONNECTOR_9PinDIN,
376 DRM_MODE_CONNECTOR_Unknown,
377 DRM_MODE_CONNECTOR_Unknown,
378 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 379 DRM_MODE_CONNECTOR_DisplayPort,
380 DRM_MODE_CONNECTOR_eDP,
381 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 382};
383
384bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
385{
386 struct radeon_device *rdev = dev->dev_private;
387 struct radeon_mode_info *mode_info = &rdev->mode_info;
388 struct atom_context *ctx = mode_info->atom_context;
389 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 390 u16 size, data_offset;
391 u8 frev, crev;
771fe6b9
JG		 392 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
393 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
394 ATOM_OBJECT_HEADER *obj_header;
395 int i, j, path_size, device_support;
396 int connector_type;
eed45b30 397 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 398 bool linkb;
399 struct radeon_i2c_bus_rec ddc_bus;
eed45b30
AD		 400 struct radeon_gpio_rec gpio;
401 struct radeon_hpd hpd;
402
a084e6ee 403 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 404 return false;
405
406 if (crev < 2)
407 return false;
408
409 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
410 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
411 (ctx->bios + data_offset +
412 le16_to_cpu(obj_header->usDisplayPathTableOffset));
413 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
414 (ctx->bios + data_offset +
415 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
416 device_support = le16_to_cpu(obj_header->usDeviceSupport);
417
418 path_size = 0;
419 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
420 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
421 ATOM_DISPLAY_OBJECT_PATH *path;
422 addr += path_size;
423 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
424 path_size += le16_to_cpu(path->usSize);
425 linkb = false;
771fe6b9
JG		 426 if (device_support & le16_to_cpu(path->usDeviceTag)) {
427 uint8_t con_obj_id, con_obj_num, con_obj_type;
428
429 con_obj_id =
430 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
431 >> OBJECT_ID_SHIFT;
432 con_obj_num =
433 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
434 >> ENUM_ID_SHIFT;
435 con_obj_type =
436 (le16_to_cpu(path->usConnObjectId) &
437 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
438
4bbd4973
DA		 439 /* TODO CV support */
440 if (le16_to_cpu(path->usDeviceTag) ==
441 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 442 continue;
443
ee59f2b4
AD		 444 /* IGP chips */
445 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 446 (con_obj_id ==
447 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
448 uint16_t igp_offset = 0;
449 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
450
451 index =
452 GetIndexIntoMasterTable(DATA,
453 IntegratedSystemInfo);
454
a084e6ee
AD		 455 if (atom_parse_data_header(ctx, index, &size, &frev,
456 &crev, &igp_offset)) {
457
458 if (crev >= 2) {
459 igp_obj =
460 (ATOM_INTEGRATED_SYSTEM_INFO_V2
461 *) (ctx->bios + igp_offset);
462
463 if (igp_obj) {
464 uint32_t slot_config, ct;
465
466 if (con_obj_num == 1)
467 slot_config =
468 igp_obj->
469 ulDDISlot1Config;
470 else
471 slot_config =
472 igp_obj->
473 ulDDISlot2Config;
474
475 ct = (slot_config >> 16) & 0xff;
476 connector_type =
477 object_connector_convert
478 [ct];
479 connector_object_id = ct;
480 igp_lane_info =
481 slot_config & 0xffff;
482 } else
483 continue;
771fe6b9
JG		 484 } else
485 continue;
a084e6ee
AD		 486 } else {
487 igp_lane_info = 0;
488 connector_type =
489 object_connector_convert[con_obj_id];
490 connector_object_id = con_obj_id;
491 }
771fe6b9
JG		 492 } else {
493 igp_lane_info = 0;
494 connector_type =
495 object_connector_convert[con_obj_id];
b75fad06 496 connector_object_id = con_obj_id;
771fe6b9
JG		 497 }
498
499 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
500 continue;
501
502 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
503 j++) {
504 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
505
506 enc_obj_id =
507 (le16_to_cpu(path->usGraphicObjIds[j]) &
508 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
509 enc_obj_num =
510 (le16_to_cpu(path->usGraphicObjIds[j]) &
511 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
512 enc_obj_type =
513 (le16_to_cpu(path->usGraphicObjIds[j]) &
514 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
515
516 /* FIXME: add support for router objects */
517 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
518 if (enc_obj_num == 2)
519 linkb = true;
520 else
521 linkb = false;
522
523 radeon_add_atom_encoder(dev,
524 enc_obj_id,
525 le16_to_cpu
526 (path->
527 usDeviceTag));
528
529 }
530 }
531
eed45b30 532 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 533 ddc_bus.valid = false;
534 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 535 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 536 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 537 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
538 if (le16_to_cpu(path->usConnObjectId) ==
539 le16_to_cpu(con_obj->asObjects[j].
540 usObjectID)) {
541 ATOM_COMMON_RECORD_HEADER
542 *record =
543 (ATOM_COMMON_RECORD_HEADER
544 *)
545 (ctx->bios + data_offset +
546 le16_to_cpu(con_obj->
547 asObjects[j].
548 usRecordOffset));
549 ATOM_I2C_RECORD *i2c_record;
eed45b30 550 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 551 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 552
771fe6b9
JG		 553 while (record->ucRecordType > 0
554 && record->
555 ucRecordType <=
556 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 557 switch (record->ucRecordType) {
771fe6b9
JG		 558 case ATOM_I2C_RECORD_TYPE:
559 i2c_record =
eed45b30
AD		 560 (ATOM_I2C_RECORD *)
561 record;
d3f420d1
AD		 562 i2c_config =
563 (ATOM_I2C_ID_CONFIG_ACCESS *)
564 &i2c_record->sucI2cId;
eed45b30 565 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 566 i2c_config->
567 ucAccess);
eed45b30
AD		 568 break;
569 case ATOM_HPD_INT_RECORD_TYPE:
570 hpd_record =
571 (ATOM_HPD_INT_RECORD *)
572 record;
573 gpio = radeon_lookup_gpio(rdev,
574 hpd_record->ucHPDIntGPIOID);
575 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
576 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 577 break;
578 }
579 record =
580 (ATOM_COMMON_RECORD_HEADER
581 *) ((char *)record
582 +
583 record->
584 ucRecordSize);
585 }
586 break;
587 }
588 }
eed45b30 589 }
771fe6b9 590
bcc1c2a1 591 /* needed for aux chan transactions */
8e36ed00 592 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 593
705af9c7
AD		 594 conn_id = le16_to_cpu(path->usConnObjectId);
595
596 if (!radeon_atom_apply_quirks
597 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 598 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 599 continue;
600
771fe6b9 601 radeon_add_atom_connector(dev,
705af9c7 602 conn_id,
771fe6b9
JG		 603 le16_to_cpu(path->
604 usDeviceTag),
605 connector_type, &ddc_bus,
b75fad06 606 linkb, igp_lane_info,
eed45b30
AD		 607 connector_object_id,
608 &hpd);
771fe6b9
JG		 609
610 }
611 }
612
613 radeon_link_encoder_connector(dev);
614
615 return true;
616}
617
b75fad06
AD		 618static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
619 int connector_type,
620 uint16_t devices)
621{
622 struct radeon_device *rdev = dev->dev_private;
623
624 if (rdev->flags & RADEON_IS_IGP) {
625 return supported_devices_connector_object_id_convert
626 [connector_type];
627 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
628 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
629 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
630 struct radeon_mode_info *mode_info = &rdev->mode_info;
631 struct atom_context *ctx = mode_info->atom_context;
632 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
633 uint16_t size, data_offset;
634 uint8_t frev, crev;
635 ATOM_XTMDS_INFO *xtmds;
636
a084e6ee
AD		 637 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
638 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 639
a084e6ee
AD		 640 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
641 if (connector_type == DRM_MODE_CONNECTOR_DVII)
642 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
643 else
644 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
645 } else {
646 if (connector_type == DRM_MODE_CONNECTOR_DVII)
647 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
648 else
649 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
650 }
651 } else
652 return supported_devices_connector_object_id_convert
653 [connector_type];
b75fad06
AD		 654 } else {
655 return supported_devices_connector_object_id_convert
656 [connector_type];
657 }
658}
659
771fe6b9
JG		 660struct bios_connector {
661 bool valid;
705af9c7 662 uint16_t line_mux;
771fe6b9
JG		 663 uint16_t devices;
664 int connector_type;
665 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 666 struct radeon_hpd hpd;
771fe6b9
JG		 667};
668
669bool radeon_get_atom_connector_info_from_supported_devices_table(struct
670 drm_device
671 *dev)
672{
673 struct radeon_device *rdev = dev->dev_private;
674 struct radeon_mode_info *mode_info = &rdev->mode_info;
675 struct atom_context *ctx = mode_info->atom_context;
676 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
677 uint16_t size, data_offset;
678 uint8_t frev, crev;
679 uint16_t device_support;
680 uint8_t dac;
681 union atom_supported_devices *supported_devices;
eed45b30 682 int i, j, max_device;
771fe6b9
JG		 683 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
684
a084e6ee
AD		 685 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
686 return false;
771fe6b9
JG		 687
688 supported_devices =
689 (union atom_supported_devices *)(ctx->bios + data_offset);
690
691 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
692
eed45b30
AD		 693 if (frev > 1)
694 max_device = ATOM_MAX_SUPPORTED_DEVICE;
695 else
696 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
697
698 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 699 ATOM_CONNECTOR_INFO_I2C ci =
700 supported_devices->info.asConnInfo[i];
701
702 bios_connectors[i].valid = false;
703
704 if (!(device_support & (1 << i))) {
705 continue;
706 }
707
708 if (i == ATOM_DEVICE_CV_INDEX) {
709 DRM_DEBUG("Skipping Component Video\n");
710 continue;
711 }
712
771fe6b9
JG		 713 bios_connectors[i].connector_type =
714 supported_devices_connector_convert[ci.sucConnectorInfo.
715 sbfAccess.
716 bfConnectorType];
717
718 if (bios_connectors[i].connector_type ==
719 DRM_MODE_CONNECTOR_Unknown)
720 continue;
721
722 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
723
d3f420d1
AD		 724 bios_connectors[i].line_mux =
725 ci.sucI2cId.ucAccess;
771fe6b9
JG		 726
727 /* give tv unique connector ids */
728 if (i == ATOM_DEVICE_TV1_INDEX) {
729 bios_connectors[i].ddc_bus.valid = false;
730 bios_connectors[i].line_mux = 50;
731 } else if (i == ATOM_DEVICE_TV2_INDEX) {
732 bios_connectors[i].ddc_bus.valid = false;
733 bios_connectors[i].line_mux = 51;
734 } else if (i == ATOM_DEVICE_CV_INDEX) {
735 bios_connectors[i].ddc_bus.valid = false;
736 bios_connectors[i].line_mux = 52;
737 } else
738 bios_connectors[i].ddc_bus =
eed45b30
AD		 739 radeon_lookup_i2c_gpio(rdev,
740 bios_connectors[i].line_mux);
741
742 if ((crev > 1) && (frev > 1)) {
743 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
744 switch (isb) {
745 case 0x4:
746 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
747 break;
748 case 0xa:
749 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
750 break;
751 default:
752 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
753 break;
754 }
755 } else {
756 if (i == ATOM_DEVICE_DFP1_INDEX)
757 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
758 else if (i == ATOM_DEVICE_DFP2_INDEX)
759 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
760 else
761 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
762 }
771fe6b9
JG		 763
764 /* Always set the connector type to VGA for CRT1/CRT2. if they are
765 * shared with a DVI port, we'll pick up the DVI connector when we
766 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
767 */
768 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
769 bios_connectors[i].connector_type =
770 DRM_MODE_CONNECTOR_VGA;
771
772 if (!radeon_atom_apply_quirks
773 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 774 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
775 &bios_connectors[i].hpd))
771fe6b9
JG		 776 continue;
777
778 bios_connectors[i].valid = true;
779 bios_connectors[i].devices = (1 << i);
780
781 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
782 radeon_add_atom_encoder(dev,
783 radeon_get_encoder_id(dev,
784 (1 << i),
785 dac),
786 (1 << i));
787 else
788 radeon_add_legacy_encoder(dev,
789 radeon_get_encoder_id(dev,
f56cd64f 790 (1 << i),
771fe6b9
JG		 791 dac),
792 (1 << i));
793 }
794
795 /* combine shared connectors */
eed45b30 796 for (i = 0; i < max_device; i++) {
771fe6b9 797 if (bios_connectors[i].valid) {
eed45b30 798 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 799 if (bios_connectors[j].valid && (i != j)) {
800 if (bios_connectors[i].line_mux ==
801 bios_connectors[j].line_mux) {
f56cd64f
AD		 802 /* make sure not to combine LVDS */
803 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
804 bios_connectors[i].line_mux = 53;
805 bios_connectors[i].ddc_bus.valid = false;
806 continue;
807 }
808 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
809 bios_connectors[j].line_mux = 53;
810 bios_connectors[j].ddc_bus.valid = false;
811 continue;
812 }
813 /* combine analog and digital for DVI-I */
814 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
815 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
816 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
817 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
818 bios_connectors[i].devices |=
819 bios_connectors[j].devices;
820 bios_connectors[i].connector_type =
821 DRM_MODE_CONNECTOR_DVII;
822 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 823 bios_connectors[i].hpd =
824 bios_connectors[j].hpd;
f56cd64f 825 bios_connectors[j].valid = false;
771fe6b9
JG		 826 }
827 }
828 }
829 }
830 }
831 }
832
833 /* add the connectors */
eed45b30 834 for (i = 0; i < max_device; i++) {
b75fad06
AD		 835 if (bios_connectors[i].valid) {
836 uint16_t connector_object_id =
837 atombios_get_connector_object_id(dev,
838 bios_connectors[i].connector_type,
839 bios_connectors[i].devices);
771fe6b9
JG		 840 radeon_add_atom_connector(dev,
841 bios_connectors[i].line_mux,
842 bios_connectors[i].devices,
843 bios_connectors[i].
844 connector_type,
845 &bios_connectors[i].ddc_bus,
b75fad06 846 false, 0,
eed45b30
AD		 847 connector_object_id,
848 &bios_connectors[i].hpd);
b75fad06 849 }
771fe6b9
JG		 850 }
851
852 radeon_link_encoder_connector(dev);
853
854 return true;
855}
856
857union firmware_info {
858 ATOM_FIRMWARE_INFO info;
859 ATOM_FIRMWARE_INFO_V1_2 info_12;
860 ATOM_FIRMWARE_INFO_V1_3 info_13;
861 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 862 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 863};
864
865bool radeon_atom_get_clock_info(struct drm_device *dev)
866{
867 struct radeon_device *rdev = dev->dev_private;
868 struct radeon_mode_info *mode_info = &rdev->mode_info;
869 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
870 union firmware_info *firmware_info;
871 uint8_t frev, crev;
872 struct radeon_pll *p1pll = &rdev->clock.p1pll;
873 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 874 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 875 struct radeon_pll *spll = &rdev->clock.spll;
876 struct radeon_pll *mpll = &rdev->clock.mpll;
877 uint16_t data_offset;
878
a084e6ee
AD		 879 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
880 &frev, &crev, &data_offset)) {
881 firmware_info =
882 (union firmware_info *)(mode_info->atom_context->bios +
883 data_offset);
771fe6b9
JG		 884 /* pixel clocks */
885 p1pll->reference_freq =
886 le16_to_cpu(firmware_info->info.usReferenceClock);
887 p1pll->reference_div = 0;
888
bc293e58
MF		 889 if (crev < 2)
890 p1pll->pll_out_min =
891 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
892 else
893 p1pll->pll_out_min =
894 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 895 p1pll->pll_out_max =
896 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
897
86cb2bbf
AD		 898 if (crev >= 4) {
899 p1pll->lcd_pll_out_min =
900 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
901 if (p1pll->lcd_pll_out_min == 0)
902 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
903 p1pll->lcd_pll_out_max =
904 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
905 if (p1pll->lcd_pll_out_max == 0)
906 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
907 } else {
908 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
909 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
910 }
911
771fe6b9
JG		 912 if (p1pll->pll_out_min == 0) {
913 if (ASIC_IS_AVIVO(rdev))
914 p1pll->pll_out_min = 64800;
915 else
916 p1pll->pll_out_min = 20000;
8f552a66
AD		 917 } else if (p1pll->pll_out_min > 64800) {
918 /* Limiting the pll output range is a good thing generally as
919 * it limits the number of possible pll combinations for a given
920 * frequency presumably to the ones that work best on each card.
921 * However, certain duallink DVI monitors seem to like
922 * pll combinations that would be limited by this at least on
923 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
924 * family.
925 */
b27b6375
AD		 926 if (!radeon_new_pll)
927 p1pll->pll_out_min = 64800;
771fe6b9
JG		 928 }
929
930 p1pll->pll_in_min =
931 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
932 p1pll->pll_in_max =
933 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
934
935 *p2pll = *p1pll;
936
937 /* system clock */
938 spll->reference_freq =
939 le16_to_cpu(firmware_info->info.usReferenceClock);
940 spll->reference_div = 0;
941
942 spll->pll_out_min =
943 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
944 spll->pll_out_max =
945 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
946
947 /* ??? */
948 if (spll->pll_out_min == 0) {
949 if (ASIC_IS_AVIVO(rdev))
950 spll->pll_out_min = 64800;
951 else
952 spll->pll_out_min = 20000;
953 }
954
955 spll->pll_in_min =
956 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
957 spll->pll_in_max =
958 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
959
960 /* memory clock */
961 mpll->reference_freq =
962 le16_to_cpu(firmware_info->info.usReferenceClock);
963 mpll->reference_div = 0;
964
965 mpll->pll_out_min =
966 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
967 mpll->pll_out_max =
968 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
969
970 /* ??? */
971 if (mpll->pll_out_min == 0) {
972 if (ASIC_IS_AVIVO(rdev))
973 mpll->pll_out_min = 64800;
974 else
975 mpll->pll_out_min = 20000;
976 }
977
978 mpll->pll_in_min =
979 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
980 mpll->pll_in_max =
981 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
982
983 rdev->clock.default_sclk =
984 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
985 rdev->clock.default_mclk =
986 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
987
bcc1c2a1
AD		 988 if (ASIC_IS_DCE4(rdev)) {
989 rdev->clock.default_dispclk =
990 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
991 if (rdev->clock.default_dispclk == 0)
992 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
993 rdev->clock.dp_extclk =
994 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
995 }
996 *dcpll = *p1pll;
997
771fe6b9
JG		 998 return true;
999 }
bcc1c2a1 1000
771fe6b9
JG		 1001 return false;
1002}
1003
06b6476d
AD		 1004union igp_info {
1005 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1006 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1007};
1008
1009bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1010{
1011 struct radeon_mode_info *mode_info = &rdev->mode_info;
1012 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1013 union igp_info *igp_info;
1014 u8 frev, crev;
1015 u16 data_offset;
1016
a084e6ee
AD		 1017 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1018 &frev, &crev, &data_offset)) {
1019 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1020 data_offset);
06b6476d
AD		 1021 switch (crev) {
1022 case 1:
1023 if (igp_info->info.ucMemoryType & 0xf0)
1024 return true;
1025 break;
1026 case 2:
1027 if (igp_info->info_2.ucMemoryType & 0x0f)
1028 return true;
1029 break;
1030 default:
1031 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1032 break;
1033 }
1034 }
1035 return false;
1036}
1037
445282db
DA		 1038bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1039 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1040{
1041 struct drm_device *dev = encoder->base.dev;
1042 struct radeon_device *rdev = dev->dev_private;
1043 struct radeon_mode_info *mode_info = &rdev->mode_info;
1044 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1045 uint16_t data_offset;
1046 struct _ATOM_TMDS_INFO *tmds_info;
1047 uint8_t frev, crev;
1048 uint16_t maxfreq;
1049 int i;
771fe6b9 1050
a084e6ee
AD		 1051 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1052 &frev, &crev, &data_offset)) {
1053 tmds_info =
1054 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1055 data_offset);
771fe6b9 1056
771fe6b9
JG		 1057 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1058 for (i = 0; i < 4; i++) {
1059 tmds->tmds_pll[i].freq =
1060 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1061 tmds->tmds_pll[i].value =
1062 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1063 tmds->tmds_pll[i].value |=
1064 (tmds_info->asMiscInfo[i].
1065 ucPLL_VCO_Gain & 0x3f) << 6;
1066 tmds->tmds_pll[i].value |=
1067 (tmds_info->asMiscInfo[i].
1068 ucPLL_DutyCycle & 0xf) << 12;
1069 tmds->tmds_pll[i].value |=
1070 (tmds_info->asMiscInfo[i].
1071 ucPLL_VoltageSwing & 0xf) << 16;
1072
1073 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1074 tmds->tmds_pll[i].freq,
1075 tmds->tmds_pll[i].value);
1076
1077 if (maxfreq == tmds->tmds_pll[i].freq) {
1078 tmds->tmds_pll[i].freq = 0xffffffff;
1079 break;
1080 }
1081 }
445282db 1082 return true;
771fe6b9 1083 }
445282db 1084 return false;
771fe6b9
JG		 1085}
1086
ebbe1cb9
AD		 1087static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1088 radeon_encoder
1089 *encoder,
1090 int id)
1091{
1092 struct drm_device *dev = encoder->base.dev;
1093 struct radeon_device *rdev = dev->dev_private;
1094 struct radeon_mode_info *mode_info = &rdev->mode_info;
1095 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1096 uint16_t data_offset;
1097 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1098 uint8_t frev, crev;
1099 struct radeon_atom_ss *ss = NULL;
279b215e 1100 int i;
ebbe1cb9
AD		 1101
1102 if (id > ATOM_MAX_SS_ENTRY)
1103 return NULL;
1104
a084e6ee
AD		 1105 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1106 &frev, &crev, &data_offset)) {
1107 ss_info =
1108 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1109
ebbe1cb9
AD		 1110 ss =
1111 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1112
1113 if (!ss)
1114 return NULL;
1115
279b215e
AD		 1116 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1117 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1118 ss->percentage =
1119 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1120 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1121 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1122 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1123 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1124 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1d3d51b6 1125 break;
279b215e
AD		 1126 }
1127 }
ebbe1cb9
AD		 1128 }
1129 return ss;
1130}
1131
771fe6b9
JG		 1132union lvds_info {
1133 struct _ATOM_LVDS_INFO info;
1134 struct _ATOM_LVDS_INFO_V12 info_12;
1135};
1136
1137struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1138 radeon_encoder
1139 *encoder)
1140{
1141 struct drm_device *dev = encoder->base.dev;
1142 struct radeon_device *rdev = dev->dev_private;
1143 struct radeon_mode_info *mode_info = &rdev->mode_info;
1144 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1145 uint16_t data_offset, misc;
771fe6b9
JG		 1146 union lvds_info *lvds_info;
1147 uint8_t frev, crev;
1148 struct radeon_encoder_atom_dig *lvds = NULL;
1149
a084e6ee
AD		 1150 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1151 &frev, &crev, &data_offset)) {
1152 lvds_info =
1153 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1154 lvds =
1155 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1156
1157 if (!lvds)
1158 return NULL;
1159
de2103e4 1160 lvds->native_mode.clock =
771fe6b9 1161 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1162 lvds->native_mode.hdisplay =
771fe6b9 1163 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1164 lvds->native_mode.vdisplay =
771fe6b9 1165 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1166 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1167 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1168 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1169 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1170 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1171 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1172 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1173 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1174 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1175 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1176 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1177 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1178 lvds->panel_pwr_delay =
1179 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1180 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1181
1182 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1183 if (misc & ATOM_VSYNC_POLARITY)
1184 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1185 if (misc & ATOM_HSYNC_POLARITY)
1186 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1187 if (misc & ATOM_COMPOSITESYNC)
1188 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1189 if (misc & ATOM_INTERLACE)
1190 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1191 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1192 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1193
de2103e4
AD		 1194 /* set crtc values */
1195 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1196
ebbe1cb9
AD		 1197 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1198
7c27f87d 1199 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 1200 if (radeon_new_pll == 0)
1201 lvds->pll_algo = PLL_ALGO_LEGACY;
1202 else
1203 lvds->pll_algo = PLL_ALGO_NEW;
1204 } else {
1205 if (radeon_new_pll == 1)
1206 lvds->pll_algo = PLL_ALGO_NEW;
7c27f87d
AD		 1207 else
1208 lvds->pll_algo = PLL_ALGO_LEGACY;
383be5d1 1209 }
7c27f87d 1210
771fe6b9
JG		 1211 encoder->native_mode = lvds->native_mode;
1212 }
1213 return lvds;
1214}
1215
6fe7ac3f
AD		 1216struct radeon_encoder_primary_dac *
1217radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1218{
1219 struct drm_device *dev = encoder->base.dev;
1220 struct radeon_device *rdev = dev->dev_private;
1221 struct radeon_mode_info *mode_info = &rdev->mode_info;
1222 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1223 uint16_t data_offset;
1224 struct _COMPASSIONATE_DATA *dac_info;
1225 uint8_t frev, crev;
1226 uint8_t bg, dac;
6fe7ac3f
AD		 1227 struct radeon_encoder_primary_dac *p_dac = NULL;
1228
a084e6ee
AD		 1229 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1230 &frev, &crev, &data_offset)) {
1231 dac_info = (struct _COMPASSIONATE_DATA *)
1232 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1233
6fe7ac3f
AD		 1234 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1235
1236 if (!p_dac)
1237 return NULL;
1238
1239 bg = dac_info->ucDAC1_BG_Adjustment;
1240 dac = dac_info->ucDAC1_DAC_Adjustment;
1241 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1242
1243 }
1244 return p_dac;
1245}
1246
4ce001ab 1247bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1248 struct drm_display_mode *mode)
4ce001ab
DA		 1249{
1250 struct radeon_mode_info *mode_info = &rdev->mode_info;
1251 ATOM_ANALOG_TV_INFO *tv_info;
1252 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1253 ATOM_DTD_FORMAT *dtd_timings;
1254 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1255 u8 frev, crev;
5a9bcacc 1256 u16 data_offset, misc;
4ce001ab 1257
a084e6ee
AD		 1258 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1259 &frev, &crev, &data_offset))
1260 return false;
4ce001ab
DA		 1261
1262 switch (crev) {
1263 case 1:
1264 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1265 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1266 return false;
1267
5a9bcacc
AD		 1268 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1269 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1270 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1271 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1272 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1273
1274 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1275 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1276 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1277 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1278 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1279
1280 mode->flags = 0;
1281 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1282 if (misc & ATOM_VSYNC_POLARITY)
1283 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1284 if (misc & ATOM_HSYNC_POLARITY)
1285 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1286 if (misc & ATOM_COMPOSITESYNC)
1287 mode->flags |= DRM_MODE_FLAG_CSYNC;
1288 if (misc & ATOM_INTERLACE)
1289 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1290 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1291 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1292
1293 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1294
1295 if (index == 1) {
1296 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1297 mode->crtc_htotal -= 1;
1298 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1299 }
1300 break;
1301 case 2:
1302 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1303 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1304 return false;
1305
1306 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1307 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1308 le16_to_cpu(dtd_timings->usHBlanking_Time);
1309 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1310 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1311 le16_to_cpu(dtd_timings->usHSyncOffset);
1312 mode->crtc_hsync_end = mode->crtc_hsync_start +
1313 le16_to_cpu(dtd_timings->usHSyncWidth);
1314
1315 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1316 le16_to_cpu(dtd_timings->usVBlanking_Time);
1317 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1318 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1319 le16_to_cpu(dtd_timings->usVSyncOffset);
1320 mode->crtc_vsync_end = mode->crtc_vsync_start +
1321 le16_to_cpu(dtd_timings->usVSyncWidth);
1322
1323 mode->flags = 0;
1324 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1325 if (misc & ATOM_VSYNC_POLARITY)
1326 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1327 if (misc & ATOM_HSYNC_POLARITY)
1328 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1329 if (misc & ATOM_COMPOSITESYNC)
1330 mode->flags |= DRM_MODE_FLAG_CSYNC;
1331 if (misc & ATOM_INTERLACE)
1332 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1333 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1334 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1335
1336 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1337 break;
1338 }
1339 return true;
1340}
1341
d79766fa
AD		 1342enum radeon_tv_std
1343radeon_atombios_get_tv_info(struct radeon_device *rdev)
1344{
1345 struct radeon_mode_info *mode_info = &rdev->mode_info;
1346 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1347 uint16_t data_offset;
1348 uint8_t frev, crev;
1349 struct _ATOM_ANALOG_TV_INFO *tv_info;
1350 enum radeon_tv_std tv_std = TV_STD_NTSC;
1351
a084e6ee
AD		 1352 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1353 &frev, &crev, &data_offset)) {
d79766fa 1354
a084e6ee
AD		 1355 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1356 (mode_info->atom_context->bios + data_offset);
d79766fa 1357
a084e6ee
AD		 1358 switch (tv_info->ucTV_BootUpDefaultStandard) {
1359 case ATOM_TV_NTSC:
1360 tv_std = TV_STD_NTSC;
1361 DRM_INFO("Default TV standard: NTSC\n");
1362 break;
1363 case ATOM_TV_NTSCJ:
1364 tv_std = TV_STD_NTSC_J;
1365 DRM_INFO("Default TV standard: NTSC-J\n");
1366 break;
1367 case ATOM_TV_PAL:
1368 tv_std = TV_STD_PAL;
1369 DRM_INFO("Default TV standard: PAL\n");
1370 break;
1371 case ATOM_TV_PALM:
1372 tv_std = TV_STD_PAL_M;
1373 DRM_INFO("Default TV standard: PAL-M\n");
1374 break;
1375 case ATOM_TV_PALN:
1376 tv_std = TV_STD_PAL_N;
1377 DRM_INFO("Default TV standard: PAL-N\n");
1378 break;
1379 case ATOM_TV_PALCN:
1380 tv_std = TV_STD_PAL_CN;
1381 DRM_INFO("Default TV standard: PAL-CN\n");
1382 break;
1383 case ATOM_TV_PAL60:
1384 tv_std = TV_STD_PAL_60;
1385 DRM_INFO("Default TV standard: PAL-60\n");
1386 break;
1387 case ATOM_TV_SECAM:
1388 tv_std = TV_STD_SECAM;
1389 DRM_INFO("Default TV standard: SECAM\n");
1390 break;
1391 default:
1392 tv_std = TV_STD_NTSC;
1393 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1394 break;
1395 }
d79766fa
AD		 1396 }
1397 return tv_std;
1398}
1399
6fe7ac3f
AD		 1400struct radeon_encoder_tv_dac *
1401radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1402{
1403 struct drm_device *dev = encoder->base.dev;
1404 struct radeon_device *rdev = dev->dev_private;
1405 struct radeon_mode_info *mode_info = &rdev->mode_info;
1406 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1407 uint16_t data_offset;
1408 struct _COMPASSIONATE_DATA *dac_info;
1409 uint8_t frev, crev;
1410 uint8_t bg, dac;
6fe7ac3f
AD		 1411 struct radeon_encoder_tv_dac *tv_dac = NULL;
1412
a084e6ee
AD		 1413 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1414 &frev, &crev, &data_offset)) {
6fe7ac3f 1415
a084e6ee
AD		 1416 dac_info = (struct _COMPASSIONATE_DATA *)
1417 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1418
6fe7ac3f
AD		 1419 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1420
1421 if (!tv_dac)
1422 return NULL;
1423
1424 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1425 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1426 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1427
1428 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1429 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1430 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1431
1432 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1433 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1434 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1435
d79766fa 1436 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1437 }
1438 return tv_dac;
1439}
1440
29fb52ca
AD		 1441static const char *thermal_controller_names[] = {
1442 "NONE",
678e7dfa
AD		 1443 "lm63",
1444 "adm1032",
1445 "adm1030",
1446 "max6649",
1447 "lm64",
1448 "f75375",
1449 "asc7xxx",
29fb52ca
AD		 1450};
1451
1452static const char *pp_lib_thermal_controller_names[] = {
1453 "NONE",
678e7dfa
AD		 1454 "lm63",
1455 "adm1032",
1456 "adm1030",
1457 "max6649",
1458 "lm64",
1459 "f75375",
29fb52ca
AD		 1460 "RV6xx",
1461 "RV770",
678e7dfa 1462 "adt7473",
49f65982
AD		 1463 "External GPIO",
1464 "Evergreen",
678e7dfa 1465 "adt7473 with internal",
49f65982 1466
29fb52ca
AD		 1467};
1468
56278a8e
AD		 1469union power_info {
1470 struct _ATOM_POWERPLAY_INFO info;
1471 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1472 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1473 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1474};
1475
1476void radeon_atombios_get_power_modes(struct radeon_device *rdev)
771fe6b9 1477{
56278a8e
AD		 1478 struct radeon_mode_info *mode_info = &rdev->mode_info;
1479 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1480 u16 data_offset;
1481 u8 frev, crev;
1482 u32 misc, misc2 = 0, sclk, mclk;
1483 union power_info *power_info;
1484 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1485 struct _ATOM_PPLIB_STATE *power_state;
1486 int num_modes = 0, i, j;
1487 int state_index = 0, mode_index = 0;
29fb52ca 1488 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1489
a48b9b4e 1490 rdev->pm.default_power_state_index = -1;
56278a8e 1491
a084e6ee
AD		 1492 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1493 &frev, &crev, &data_offset)) {
1494 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
56278a8e 1495 if (frev < 4) {
29fb52ca
AD		 1496 /* add the i2c bus for thermal/fan chip */
1497 if (power_info->info.ucOverdriveThermalController > 0) {
1498 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1499 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1500 power_info->info.ucOverdriveControllerAddress >> 1);
1501 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1502 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
678e7dfa
AD		 1503 if (rdev->pm.i2c_bus) {
1504 struct i2c_board_info info = { };
1505 const char *name = thermal_controller_names[power_info->info.
1506 ucOverdriveThermalController];
1507 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1508 strlcpy(info.type, name, sizeof(info.type));
1509 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1510 }
29fb52ca 1511 }
56278a8e
AD		 1512 num_modes = power_info->info.ucNumOfPowerModeEntries;
1513 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1514 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
02b17cc0 1515 /* last mode is usually default, array is low to high */
56278a8e
AD		 1516 for (i = 0; i < num_modes; i++) {
1517 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1518 switch (frev) {
1519 case 1:
1520 rdev->pm.power_state[state_index].num_clock_modes = 1;
1521 rdev->pm.power_state[state_index].clock_info[0].mclk =
1522 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1523 rdev->pm.power_state[state_index].clock_info[0].sclk =
1524 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1525 /* skip invalid modes */
1526 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1527 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1528 continue;
79daedc9 1529 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1530 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1531 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1532 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1533 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1534 VOLTAGE_GPIO;
1535 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1536 radeon_lookup_gpio(rdev,
1537 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1538 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1539 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1540 true;
1541 else
1542 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1543 false;
1544 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1545 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1546 VOLTAGE_VDDC;
1547 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1548 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1549 }
d7311171 1550 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9 1551 rdev->pm.power_state[state_index].misc = misc;
0ec0e74f
AD		 1552 /* order matters! */
1553 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1554 rdev->pm.power_state[state_index].type =
1555 POWER_STATE_TYPE_POWERSAVE;
1556 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1557 rdev->pm.power_state[state_index].type =
1558 POWER_STATE_TYPE_BATTERY;
1559 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1560 rdev->pm.power_state[state_index].type =
1561 POWER_STATE_TYPE_BATTERY;
1562 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1563 rdev->pm.power_state[state_index].type =
1564 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1565 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1566 rdev->pm.power_state[state_index].type =
1567 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1568 rdev->pm.power_state[state_index].flags &=
d7311171 1569 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1570 }
56278a8e 1571 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1572 rdev->pm.power_state[state_index].type =
1573 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1574 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1575 rdev->pm.power_state[state_index].default_clock_mode =
1576 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1577 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1578 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1579 } else if (state_index == 0) {
1580 rdev->pm.power_state[state_index].clock_info[0].flags |=
1581 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1582 }
1583 state_index++;
1584 break;
1585 case 2:
1586 rdev->pm.power_state[state_index].num_clock_modes = 1;
1587 rdev->pm.power_state[state_index].clock_info[0].mclk =
1588 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1589 rdev->pm.power_state[state_index].clock_info[0].sclk =
1590 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1591 /* skip invalid modes */
1592 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1593 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1594 continue;
79daedc9 1595 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1596 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1597 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1598 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1599 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1600 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1601 VOLTAGE_GPIO;
1602 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1603 radeon_lookup_gpio(rdev,
1604 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1605 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1606 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1607 true;
1608 else
1609 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1610 false;
1611 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1612 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1613 VOLTAGE_VDDC;
1614 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1615 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1616 }
d7311171 1617 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1618 rdev->pm.power_state[state_index].misc = misc;
1619 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1620 /* order matters! */
1621 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1622 rdev->pm.power_state[state_index].type =
1623 POWER_STATE_TYPE_POWERSAVE;
1624 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1625 rdev->pm.power_state[state_index].type =
1626 POWER_STATE_TYPE_BATTERY;
1627 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1628 rdev->pm.power_state[state_index].type =
1629 POWER_STATE_TYPE_BATTERY;
1630 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1631 rdev->pm.power_state[state_index].type =
1632 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1633 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1634 rdev->pm.power_state[state_index].type =
1635 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1636 rdev->pm.power_state[state_index].flags &=
d7311171 1637 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1638 }
0ec0e74f
AD		 1639 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1640 rdev->pm.power_state[state_index].type =
1641 POWER_STATE_TYPE_BALANCED;
a48b9b4e
AD		 1642 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1643 rdev->pm.power_state[state_index].flags &=
d7311171 1644 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1645 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1646 rdev->pm.power_state[state_index].type =
1647 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1648 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1649 rdev->pm.power_state[state_index].default_clock_mode =
1650 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1651 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1652 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1653 } else if (state_index == 0) {
1654 rdev->pm.power_state[state_index].clock_info[0].flags |=
1655 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1656 }
1657 state_index++;
1658 break;
1659 case 3:
1660 rdev->pm.power_state[state_index].num_clock_modes = 1;
1661 rdev->pm.power_state[state_index].clock_info[0].mclk =
1662 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1663 rdev->pm.power_state[state_index].clock_info[0].sclk =
1664 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1665 /* skip invalid modes */
1666 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1667 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1668 continue;
79daedc9 1669 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1670 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1671 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1672 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1673 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1674 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1675 VOLTAGE_GPIO;
1676 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1677 radeon_lookup_gpio(rdev,
1678 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1679 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1680 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1681 true;
1682 else
1683 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1684 false;
1685 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1686 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1687 VOLTAGE_VDDC;
1688 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1689 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1690 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1691 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1692 true;
1693 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1694 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1695 }
1696 }
d7311171 1697 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1698 rdev->pm.power_state[state_index].misc = misc;
1699 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1700 /* order matters! */
1701 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1702 rdev->pm.power_state[state_index].type =
1703 POWER_STATE_TYPE_POWERSAVE;
1704 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1705 rdev->pm.power_state[state_index].type =
1706 POWER_STATE_TYPE_BATTERY;
1707 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1708 rdev->pm.power_state[state_index].type =
1709 POWER_STATE_TYPE_BATTERY;
1710 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1711 rdev->pm.power_state[state_index].type =
1712 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1713 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1714 rdev->pm.power_state[state_index].type =
1715 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1716 rdev->pm.power_state[state_index].flags &=
d7311171 1717 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1718 }
0ec0e74f
AD		 1719 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1720 rdev->pm.power_state[state_index].type =
1721 POWER_STATE_TYPE_BALANCED;
56278a8e 1722 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1723 rdev->pm.power_state[state_index].type =
1724 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1725 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1726 rdev->pm.power_state[state_index].default_clock_mode =
1727 &rdev->pm.power_state[state_index].clock_info[0];
d7311171
AD		 1728 } else if (state_index == 0) {
1729 rdev->pm.power_state[state_index].clock_info[0].flags |=
1730 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1731 }
1732 state_index++;
1733 break;
1734 }
1735 }
02b17cc0 1736 /* last mode is usually default */
a48b9b4e 1737 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 1738 rdev->pm.power_state[state_index - 1].type =
1739 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1740 rdev->pm.default_power_state_index = state_index - 1;
02b17cc0
AD		 1741 rdev->pm.power_state[state_index - 1].default_clock_mode =
1742 &rdev->pm.power_state[state_index - 1].clock_info[0];
a48b9b4e 1743 rdev->pm.power_state[state_index].flags &=
d7311171 1744 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1745 rdev->pm.power_state[state_index].misc = 0;
1746 rdev->pm.power_state[state_index].misc2 = 0;
02b17cc0 1747 }
49f65982 1748 } else {
29fb52ca
AD		 1749 /* add the i2c bus for thermal/fan chip */
1750 /* no support for internal controller yet */
678e7dfa
AD		 1751 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1752 if (controller->ucType > 0) {
1753 if ((controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1754 (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) ||
1755 (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN)) {
29fb52ca 1756 DRM_INFO("Internal thermal controller %s fan control\n",
678e7dfa 1757 (controller->ucFanParameters &
29fb52ca 1758 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
678e7dfa 1759 } else if ((controller->ucType ==
49f65982 1760 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
678e7dfa 1761 (controller->ucType ==
49f65982
AD		 1762 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1763 DRM_INFO("Special thermal controller config\n");
29fb52ca
AD		 1764 } else {
1765 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
678e7dfa
AD		 1766 pp_lib_thermal_controller_names[controller->ucType],
1767 controller->ucI2cAddress >> 1,
1768 (controller->ucFanParameters &
29fb52ca 1769 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
678e7dfa 1770 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
29fb52ca 1771 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
678e7dfa
AD		 1772 if (rdev->pm.i2c_bus) {
1773 struct i2c_board_info info = { };
1774 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1775 info.addr = controller->ucI2cAddress >> 1;
1776 strlcpy(info.type, name, sizeof(info.type));
1777 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1778 }
1779
29fb52ca
AD		 1780 }
1781 }
02b17cc0 1782 /* first mode is usually default, followed by low to high */
56278a8e
AD		 1783 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1784 mode_index = 0;
1785 power_state = (struct _ATOM_PPLIB_STATE *)
1786 (mode_info->atom_context->bios +
1787 data_offset +
1788 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1789 i * power_info->info_4.ucStateEntrySize);
1790 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1791 (mode_info->atom_context->bios +
1792 data_offset +
1793 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1794 (power_state->ucNonClockStateIndex *
1795 power_info->info_4.ucNonClockSize));
56278a8e
AD		 1796 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1797 if (rdev->flags & RADEON_IS_IGP) {
1798 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1799 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1800 (mode_info->atom_context->bios +
1801 data_offset +
1802 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1803 (power_state->ucClockStateIndices[j] *
1804 power_info->info_4.ucClockInfoSize));
1805 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1806 sclk |= clock_info->ucLowEngineClockHigh << 16;
1807 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1808 /* skip invalid modes */
1809 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1810 continue;
56278a8e
AD		 1811 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1812 VOLTAGE_SW;
1813 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1814 clock_info->usVDDC;
1815 mode_index++;
49f65982
AD		 1816 } else if (ASIC_IS_DCE4(rdev)) {
1817 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1818 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1819 (mode_info->atom_context->bios +
1820 data_offset +
1821 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1822 (power_state->ucClockStateIndices[j] *
1823 power_info->info_4.ucClockInfoSize));
1824 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1825 sclk |= clock_info->ucEngineClockHigh << 16;
1826 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1827 mclk |= clock_info->ucMemoryClockHigh << 16;
1828 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1829 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1830 /* skip invalid modes */
1831 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1832 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1833 continue;
49f65982
AD		 1834 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1835 VOLTAGE_SW;
1836 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1837 clock_info->usVDDC;
1838 /* XXX usVDDCI */
1839 mode_index++;
56278a8e
AD		 1840 } else {
1841 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1842 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1843 (mode_info->atom_context->bios +
1844 data_offset +
1845 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1846 (power_state->ucClockStateIndices[j] *
1847 power_info->info_4.ucClockInfoSize));
1848 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1849 sclk |= clock_info->ucEngineClockHigh << 16;
1850 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1851 mclk |= clock_info->ucMemoryClockHigh << 16;
1852 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1853 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1854 /* skip invalid modes */
1855 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1856 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1857 continue;
56278a8e
AD		 1858 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1859 VOLTAGE_SW;
1860 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1861 clock_info->usVDDC;
1862 mode_index++;
1863 }
1864 }
1865 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1866 if (mode_index) {
845db70d 1867 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 1868 misc2 = le16_to_cpu(non_clock_info->usClassification);
79daedc9
AD		 1869 rdev->pm.power_state[state_index].misc = misc;
1870 rdev->pm.power_state[state_index].misc2 = misc2;
1871 rdev->pm.power_state[state_index].pcie_lanes =
845db70d
RM		 1872 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1873 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 1874 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1875 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1876 rdev->pm.power_state[state_index].type =
1877 POWER_STATE_TYPE_BATTERY;
1878 break;
1879 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1880 rdev->pm.power_state[state_index].type =
1881 POWER_STATE_TYPE_BALANCED;
1882 break;
1883 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1884 rdev->pm.power_state[state_index].type =
1885 POWER_STATE_TYPE_PERFORMANCE;
1886 break;
1887 }
a48b9b4e
AD		 1888 rdev->pm.power_state[state_index].flags = 0;
1889 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1890 rdev->pm.power_state[state_index].flags |=
d7311171 1891 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1892 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 1893 rdev->pm.power_state[state_index].type =
1894 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1895 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1896 rdev->pm.power_state[state_index].default_clock_mode =
1897 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
56278a8e
AD		 1898 }
1899 state_index++;
1900 }
1901 }
d7311171
AD		 1902 /* if multiple clock modes, mark the lowest as no display */
1903 for (i = 0; i < state_index; i++) {
1904 if (rdev->pm.power_state[i].num_clock_modes > 1)
1905 rdev->pm.power_state[i].clock_info[0].flags |=
1906 RADEON_PM_MODE_NO_DISPLAY;
1907 }
02b17cc0 1908 /* first mode is usually default */
a48b9b4e 1909 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 1910 rdev->pm.power_state[0].type =
1911 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1912 rdev->pm.default_power_state_index = 0;
02b17cc0
AD		 1913 rdev->pm.power_state[0].default_clock_mode =
1914 &rdev->pm.power_state[0].clock_info[0];
1915 }
56278a8e
AD		 1916 }
1917 } else {
56278a8e 1918 /* add the default mode */
0ec0e74f
AD		 1919 rdev->pm.power_state[state_index].type =
1920 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 1921 rdev->pm.power_state[state_index].num_clock_modes = 1;
1922 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1923 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1924 rdev->pm.power_state[state_index].default_clock_mode =
1925 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 1926 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 1927 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 1928 rdev->pm.default_power_state_index = state_index;
1929 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 1930 state_index++;
1931 }
02b17cc0 1932
56278a8e 1933 rdev->pm.num_power_states = state_index;
9038dfdf 1934
a48b9b4e
AD		 1935 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1936 rdev->pm.current_clock_mode_index = 0;
771fe6b9
JG		 1937}
1938
771fe6b9 1939void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 1940{
771fe6b9
JG		 1941 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1942 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 1943
1944 args.ucEnable = enable;
1945
1946 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1947}
1948
7433874e
RM		 1949uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1950{
1951 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1952 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1953
1954 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1955 return args.ulReturnEngineClock;
1956}
1957
1958uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1959{
1960 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1961 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1962
1963 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1964 return args.ulReturnMemoryClock;
1965}
1966
771fe6b9
JG		 1967void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1968 uint32_t eng_clock)
1969{
1970 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1971 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1972
1973 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1974
1975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1976}
1977
1978void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1979 uint32_t mem_clock)
1980{
1981 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1982 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1983
1984 if (rdev->flags & RADEON_IS_IGP)
1985 return;
1986
1987 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1988
1989 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1990}
1991
1992void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1993{
1994 struct radeon_device *rdev = dev->dev_private;
1995 uint32_t bios_2_scratch, bios_6_scratch;
1996
1997 if (rdev->family >= CHIP_R600) {
4ce001ab 1998 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1999 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2000 } else {
4ce001ab 2001 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2002 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2003 }
2004
2005 /* let the bios control the backlight */
2006 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2007
2008 /* tell the bios not to handle mode switching */
2009 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2010
2011 if (rdev->family >= CHIP_R600) {
2012 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2013 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2014 } else {
2015 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2016 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2017 }
2018
2019}
2020
f657c2a7
YZ		 2021void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2022{
2023 uint32_t scratch_reg;
2024 int i;
2025
2026 if (rdev->family >= CHIP_R600)
2027 scratch_reg = R600_BIOS_0_SCRATCH;
2028 else
2029 scratch_reg = RADEON_BIOS_0_SCRATCH;
2030
2031 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2032 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2033}
2034
2035void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2036{
2037 uint32_t scratch_reg;
2038 int i;
2039
2040 if (rdev->family >= CHIP_R600)
2041 scratch_reg = R600_BIOS_0_SCRATCH;
2042 else
2043 scratch_reg = RADEON_BIOS_0_SCRATCH;
2044
2045 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2046 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2047}
2048
771fe6b9
JG		 2049void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2050{
2051 struct drm_device *dev = encoder->dev;
2052 struct radeon_device *rdev = dev->dev_private;
2053 uint32_t bios_6_scratch;
2054
2055 if (rdev->family >= CHIP_R600)
2056 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2057 else
2058 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2059
2060 if (lock)
2061 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2062 else
2063 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2064
2065 if (rdev->family >= CHIP_R600)
2066 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2067 else
2068 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2069}
2070
2071/* at some point we may want to break this out into individual functions */
2072void
2073radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2074 struct drm_encoder *encoder,
2075 bool connected)
2076{
2077 struct drm_device *dev = connector->dev;
2078 struct radeon_device *rdev = dev->dev_private;
2079 struct radeon_connector *radeon_connector =
2080 to_radeon_connector(connector);
2081 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2082 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2083
2084 if (rdev->family >= CHIP_R600) {
2085 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2086 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2087 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2088 } else {
2089 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2090 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2091 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2092 }
2093
2094 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2095 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2096 if (connected) {
2097 DRM_DEBUG("TV1 connected\n");
2098 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2099 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2100 } else {
2101 DRM_DEBUG("TV1 disconnected\n");
2102 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2103 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2104 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2105 }
2106 }
2107 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2108 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2109 if (connected) {
2110 DRM_DEBUG("CV connected\n");
2111 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2112 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2113 } else {
2114 DRM_DEBUG("CV disconnected\n");
2115 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2116 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2117 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2118 }
2119 }
2120 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2121 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2122 if (connected) {
2123 DRM_DEBUG("LCD1 connected\n");
2124 bios_0_scratch |= ATOM_S0_LCD1;
2125 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2126 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2127 } else {
2128 DRM_DEBUG("LCD1 disconnected\n");
2129 bios_0_scratch &= ~ATOM_S0_LCD1;
2130 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2131 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2132 }
2133 }
2134 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2135 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2136 if (connected) {
2137 DRM_DEBUG("CRT1 connected\n");
2138 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2139 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2140 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2141 } else {
2142 DRM_DEBUG("CRT1 disconnected\n");
2143 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2144 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2145 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2146 }
2147 }
2148 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2149 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2150 if (connected) {
2151 DRM_DEBUG("CRT2 connected\n");
2152 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2153 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2154 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2155 } else {
2156 DRM_DEBUG("CRT2 disconnected\n");
2157 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2158 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2159 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2160 }
2161 }
2162 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2163 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2164 if (connected) {
2165 DRM_DEBUG("DFP1 connected\n");
2166 bios_0_scratch |= ATOM_S0_DFP1;
2167 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2168 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2169 } else {
2170 DRM_DEBUG("DFP1 disconnected\n");
2171 bios_0_scratch &= ~ATOM_S0_DFP1;
2172 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2173 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2174 }
2175 }
2176 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2177 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2178 if (connected) {
2179 DRM_DEBUG("DFP2 connected\n");
2180 bios_0_scratch |= ATOM_S0_DFP2;
2181 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2182 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2183 } else {
2184 DRM_DEBUG("DFP2 disconnected\n");
2185 bios_0_scratch &= ~ATOM_S0_DFP2;
2186 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2187 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2188 }
2189 }
2190 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2191 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2192 if (connected) {
2193 DRM_DEBUG("DFP3 connected\n");
2194 bios_0_scratch |= ATOM_S0_DFP3;
2195 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2196 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2197 } else {
2198 DRM_DEBUG("DFP3 disconnected\n");
2199 bios_0_scratch &= ~ATOM_S0_DFP3;
2200 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2201 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2202 }
2203 }
2204 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2205 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2206 if (connected) {
2207 DRM_DEBUG("DFP4 connected\n");
2208 bios_0_scratch |= ATOM_S0_DFP4;
2209 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2210 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2211 } else {
2212 DRM_DEBUG("DFP4 disconnected\n");
2213 bios_0_scratch &= ~ATOM_S0_DFP4;
2214 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2215 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2216 }
2217 }
2218 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2219 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2220 if (connected) {
2221 DRM_DEBUG("DFP5 connected\n");
2222 bios_0_scratch |= ATOM_S0_DFP5;
2223 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2224 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2225 } else {
2226 DRM_DEBUG("DFP5 disconnected\n");
2227 bios_0_scratch &= ~ATOM_S0_DFP5;
2228 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2229 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2230 }
2231 }
2232
2233 if (rdev->family >= CHIP_R600) {
2234 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2235 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2236 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2237 } else {
2238 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2239 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2240 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2241 }
2242}
2243
2244void
2245radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2246{
2247 struct drm_device *dev = encoder->dev;
2248 struct radeon_device *rdev = dev->dev_private;
2249 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2250 uint32_t bios_3_scratch;
2251
2252 if (rdev->family >= CHIP_R600)
2253 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2254 else
2255 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2256
2257 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2258 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2259 bios_3_scratch |= (crtc << 18);
2260 }
2261 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2262 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2263 bios_3_scratch |= (crtc << 24);
2264 }
2265 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2266 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2267 bios_3_scratch |= (crtc << 16);
2268 }
2269 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2270 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2271 bios_3_scratch |= (crtc << 20);
2272 }
2273 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2274 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2275 bios_3_scratch |= (crtc << 17);
2276 }
2277 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2278 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2279 bios_3_scratch |= (crtc << 19);
2280 }
2281 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2282 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2283 bios_3_scratch |= (crtc << 23);
2284 }
2285 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2286 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2287 bios_3_scratch |= (crtc << 25);
2288 }
2289
2290 if (rdev->family >= CHIP_R600)
2291 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2292 else
2293 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2294}
2295
2296void
2297radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2298{
2299 struct drm_device *dev = encoder->dev;
2300 struct radeon_device *rdev = dev->dev_private;
2301 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2302 uint32_t bios_2_scratch;
2303
2304 if (rdev->family >= CHIP_R600)
2305 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2306 else
2307 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2308
2309 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2310 if (on)
2311 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2312 else
2313 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2314 }
2315 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2316 if (on)
2317 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2318 else
2319 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2320 }
2321 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2322 if (on)
2323 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2324 else
2325 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2326 }
2327 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2328 if (on)
2329 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2330 else
2331 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2332 }
2333 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2334 if (on)
2335 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2336 else
2337 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2338 }
2339 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2340 if (on)
2341 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2342 else
2343 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2344 }
2345 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2346 if (on)
2347 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2348 else
2349 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2350 }
2351 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2352 if (on)
2353 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2354 else
2355 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2356 }
2357 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2358 if (on)
2359 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2360 else
2361 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2362 }
2363 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2364 if (on)
2365 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2366 else
2367 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2368 }
2369
2370 if (rdev->family >= CHIP_R600)
2371 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2372 else
2373 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2374}
Clone of davem's net-next-2.6 tree