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drm/radeon/kms: rework encoder handling
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
5137ee94
AD		 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
771fe6b9
JG		 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
5137ee94 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
5137ee94 49 uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
5137ee94 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
88 if (gpio->sucI2cId.ucAccess == id) {
89 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
90 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
91 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
92 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
93 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
94 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
95 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
96 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
97 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
98 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
99 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
100 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
101 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
102 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
103 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
104 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
105
106 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
107 i2c.hw_capable = true;
108 else
109 i2c.hw_capable = false;
110
111 if (gpio->sucI2cId.ucAccess == 0xa0)
112 i2c.mm_i2c = true;
113 else
114 i2c.mm_i2c = false;
115
116 i2c.i2c_id = gpio->sucI2cId.ucAccess;
117
f376b94f
AD		 118 if (i2c.mask_clk_reg)
119 i2c.valid = true;
a084e6ee
AD		 120 break;
121 }
d3f420d1
AD		 122 }
123 }
771fe6b9
JG		 124
125 return i2c;
126}
127
f376b94f
AD		 128void radeon_atombios_i2c_init(struct radeon_device *rdev)
129{
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
136 int i, num_indices;
137 char stmp[32];
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
143
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
146
147 for (i = 0; i < num_indices; i++) {
148 gpio = &i2c_info->asGPIO_Info[i];
149 i2c.valid = false;
150 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
151 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
152 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
153 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
154 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
155 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
156 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
157 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
158 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
159 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
160 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
161 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
162 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
163 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
164 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
165 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
166
167 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
168 i2c.hw_capable = true;
169 else
170 i2c.hw_capable = false;
171
172 if (gpio->sucI2cId.ucAccess == 0xa0)
173 i2c.mm_i2c = true;
174 else
175 i2c.mm_i2c = false;
176
177 i2c.i2c_id = gpio->sucI2cId.ucAccess;
178
179 if (i2c.mask_clk_reg) {
180 i2c.valid = true;
181 sprintf(stmp, "0x%x", i2c.i2c_id);
182 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
183 }
184 }
185 }
186}
187
eed45b30
AD		 188static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
189 u8 id)
190{
191 struct atom_context *ctx = rdev->mode_info.atom_context;
192 struct radeon_gpio_rec gpio;
193 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
194 struct _ATOM_GPIO_PIN_LUT *gpio_info;
195 ATOM_GPIO_PIN_ASSIGNMENT *pin;
196 u16 data_offset, size;
197 int i, num_indices;
198
199 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
200 gpio.valid = false;
201
a084e6ee
AD		 202 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
203 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 204
a084e6ee
AD		 205 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
206 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 207
a084e6ee
AD		 208 for (i = 0; i < num_indices; i++) {
209 pin = &gpio_info->asGPIO_Pin[i];
210 if (id == pin->ucGPIO_ID) {
211 gpio.id = pin->ucGPIO_ID;
212 gpio.reg = pin->usGpioPin_AIndex * 4;
213 gpio.mask = (1 << pin->ucGpioPinBitShift);
214 gpio.valid = true;
215 break;
216 }
eed45b30
AD		 217 }
218 }
219
220 return gpio;
221}
222
223static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
224 struct radeon_gpio_rec *gpio)
225{
226 struct radeon_hpd hpd;
bcc1c2a1
AD		 227 u32 reg;
228
1d978dac
JD		 229 memset(&hpd, 0, sizeof(struct radeon_hpd));
230
bcc1c2a1
AD		 231 if (ASIC_IS_DCE4(rdev))
232 reg = EVERGREEN_DC_GPIO_HPD_A;
233 else
234 reg = AVIVO_DC_GPIO_HPD_A;
235
eed45b30 236 hpd.gpio = *gpio;
bcc1c2a1 237 if (gpio->reg == reg) {
eed45b30
AD		 238 switch(gpio->mask) {
239 case (1 << 0):
240 hpd.hpd = RADEON_HPD_1;
241 break;
242 case (1 << 8):
243 hpd.hpd = RADEON_HPD_2;
244 break;
245 case (1 << 16):
246 hpd.hpd = RADEON_HPD_3;
247 break;
248 case (1 << 24):
249 hpd.hpd = RADEON_HPD_4;
250 break;
251 case (1 << 26):
252 hpd.hpd = RADEON_HPD_5;
253 break;
254 case (1 << 28):
255 hpd.hpd = RADEON_HPD_6;
256 break;
257 default:
258 hpd.hpd = RADEON_HPD_NONE;
259 break;
260 }
261 } else
262 hpd.hpd = RADEON_HPD_NONE;
263 return hpd;
264}
265
771fe6b9
JG		 266static bool radeon_atom_apply_quirks(struct drm_device *dev,
267 uint32_t supported_device,
268 int *connector_type,
848577ee 269 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 270 uint16_t *line_mux,
271 struct radeon_hpd *hpd)
771fe6b9 272{
9ea2c4be 273 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 274
275 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
276 if ((dev->pdev->device == 0x791e) &&
277 (dev->pdev->subsystem_vendor == 0x1043) &&
278 (dev->pdev->subsystem_device == 0x826d)) {
279 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
280 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
281 *connector_type = DRM_MODE_CONNECTOR_DVID;
282 }
283
c86a9038
AD		 284 /* Asrock RS600 board lists the DVI port as HDMI */
285 if ((dev->pdev->device == 0x7941) &&
286 (dev->pdev->subsystem_vendor == 0x1849) &&
287 (dev->pdev->subsystem_device == 0x7941)) {
288 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
289 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
290 *connector_type = DRM_MODE_CONNECTOR_DVID;
291 }
292
771fe6b9
JG		 293 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
294 if ((dev->pdev->device == 0x7941) &&
295 (dev->pdev->subsystem_vendor == 0x147b) &&
296 (dev->pdev->subsystem_device == 0x2412)) {
297 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
298 return false;
299 }
300
301 /* Falcon NW laptop lists vga ddc line for LVDS */
302 if ((dev->pdev->device == 0x5653) &&
303 (dev->pdev->subsystem_vendor == 0x1462) &&
304 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 305 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 306 i2c_bus->valid = false;
848577ee
AD		 307 *line_mux = 53;
308 }
771fe6b9
JG		 309 }
310
4e3f9b78
AD		 311 /* HIS X1300 is DVI+VGA, not DVI+DVI */
312 if ((dev->pdev->device == 0x7146) &&
313 (dev->pdev->subsystem_vendor == 0x17af) &&
314 (dev->pdev->subsystem_device == 0x2058)) {
315 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
316 return false;
317 }
318
aa1a750e
DA		 319 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
320 if ((dev->pdev->device == 0x7142) &&
321 (dev->pdev->subsystem_vendor == 0x1458) &&
322 (dev->pdev->subsystem_device == 0x2134)) {
323 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
324 return false;
325 }
326
327
771fe6b9
JG		 328 /* Funky macbooks */
329 if ((dev->pdev->device == 0x71C5) &&
330 (dev->pdev->subsystem_vendor == 0x106b) &&
331 (dev->pdev->subsystem_device == 0x0080)) {
332 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
333 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
334 return false;
e1e8a5dd
AD		 335 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
336 *line_mux = 0x90;
771fe6b9
JG		 337 }
338
771fe6b9
JG		 339 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
340 if ((dev->pdev->device == 0x9598) &&
341 (dev->pdev->subsystem_vendor == 0x1043) &&
342 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 343 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 344 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 345 }
346 }
347
e153b70b
AD		 348 /* ASUS HD 3600 board lists the DVI port as HDMI */
349 if ((dev->pdev->device == 0x9598) &&
350 (dev->pdev->subsystem_vendor == 0x1043) &&
351 (dev->pdev->subsystem_device == 0x01e4)) {
352 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
353 *connector_type = DRM_MODE_CONNECTOR_DVII;
354 }
355 }
356
705af9c7
AD		 357 /* ASUS HD 3450 board lists the DVI port as HDMI */
358 if ((dev->pdev->device == 0x95C5) &&
359 (dev->pdev->subsystem_vendor == 0x1043) &&
360 (dev->pdev->subsystem_device == 0x01e2)) {
361 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 362 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 363 }
364 }
365
705af9c7
AD		 366 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
367 * HDMI + VGA reporting as HDMI
368 */
369 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
370 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
371 *connector_type = DRM_MODE_CONNECTOR_VGA;
372 *line_mux = 0;
373 }
374 }
375
9ea2c4be 376 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
3e5f8ff3
AD		 377 if ((dev->pdev->device == 0x95c4) &&
378 (dev->pdev->subsystem_vendor == 0x1025) &&
379 (dev->pdev->subsystem_device == 0x013c)) {
9ea2c4be
AD		 380 struct radeon_gpio_rec gpio;
381
3e5f8ff3 382 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be
AD		 383 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
384 gpio = radeon_lookup_gpio(rdev, 6);
385 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
3e5f8ff3 386 *connector_type = DRM_MODE_CONNECTOR_DVID;
9ea2c4be
AD		 387 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
388 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
389 gpio = radeon_lookup_gpio(rdev, 7);
390 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
391 }
3e5f8ff3
AD		 392 }
393
efa8450f
DA		 394 /* XFX Pine Group device rv730 reports no VGA DDC lines
395 * even though they are wired up to record 0x93
396 */
397 if ((dev->pdev->device == 0x9498) &&
398 (dev->pdev->subsystem_vendor == 0x1682) &&
399 (dev->pdev->subsystem_device == 0x2452)) {
400 struct radeon_device *rdev = dev->dev_private;
401 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
402 }
771fe6b9
JG		 403 return true;
404}
405
406const int supported_devices_connector_convert[] = {
407 DRM_MODE_CONNECTOR_Unknown,
408 DRM_MODE_CONNECTOR_VGA,
409 DRM_MODE_CONNECTOR_DVII,
410 DRM_MODE_CONNECTOR_DVID,
411 DRM_MODE_CONNECTOR_DVIA,
412 DRM_MODE_CONNECTOR_SVIDEO,
413 DRM_MODE_CONNECTOR_Composite,
414 DRM_MODE_CONNECTOR_LVDS,
415 DRM_MODE_CONNECTOR_Unknown,
416 DRM_MODE_CONNECTOR_Unknown,
417 DRM_MODE_CONNECTOR_HDMIA,
418 DRM_MODE_CONNECTOR_HDMIB,
419 DRM_MODE_CONNECTOR_Unknown,
420 DRM_MODE_CONNECTOR_Unknown,
421 DRM_MODE_CONNECTOR_9PinDIN,
422 DRM_MODE_CONNECTOR_DisplayPort
423};
424
b75fad06
AD		 425const uint16_t supported_devices_connector_object_id_convert[] = {
426 CONNECTOR_OBJECT_ID_NONE,
427 CONNECTOR_OBJECT_ID_VGA,
428 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
429 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
430 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
431 CONNECTOR_OBJECT_ID_COMPOSITE,
432 CONNECTOR_OBJECT_ID_SVIDEO,
433 CONNECTOR_OBJECT_ID_LVDS,
434 CONNECTOR_OBJECT_ID_9PIN_DIN,
435 CONNECTOR_OBJECT_ID_9PIN_DIN,
436 CONNECTOR_OBJECT_ID_DISPLAYPORT,
437 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
438 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
439 CONNECTOR_OBJECT_ID_SVIDEO
440};
441
771fe6b9
JG		 442const int object_connector_convert[] = {
443 DRM_MODE_CONNECTOR_Unknown,
444 DRM_MODE_CONNECTOR_DVII,
445 DRM_MODE_CONNECTOR_DVII,
446 DRM_MODE_CONNECTOR_DVID,
447 DRM_MODE_CONNECTOR_DVID,
448 DRM_MODE_CONNECTOR_VGA,
449 DRM_MODE_CONNECTOR_Composite,
450 DRM_MODE_CONNECTOR_SVIDEO,
451 DRM_MODE_CONNECTOR_Unknown,
705af9c7 452 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 453 DRM_MODE_CONNECTOR_9PinDIN,
454 DRM_MODE_CONNECTOR_Unknown,
455 DRM_MODE_CONNECTOR_HDMIA,
456 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 457 DRM_MODE_CONNECTOR_LVDS,
458 DRM_MODE_CONNECTOR_9PinDIN,
459 DRM_MODE_CONNECTOR_Unknown,
460 DRM_MODE_CONNECTOR_Unknown,
461 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 462 DRM_MODE_CONNECTOR_DisplayPort,
463 DRM_MODE_CONNECTOR_eDP,
464 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 465};
466
467bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
468{
469 struct radeon_device *rdev = dev->dev_private;
470 struct radeon_mode_info *mode_info = &rdev->mode_info;
471 struct atom_context *ctx = mode_info->atom_context;
472 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 473 u16 size, data_offset;
474 u8 frev, crev;
771fe6b9 475 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
26b5bc98 476 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 477 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
478 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 479 int i, j, k, path_size, device_support;
771fe6b9 480 int connector_type;
eed45b30 481 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9 482 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 483 struct radeon_router router;
eed45b30
AD		 484 struct radeon_gpio_rec gpio;
485 struct radeon_hpd hpd;
486
a084e6ee 487 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 488 return false;
489
490 if (crev < 2)
491 return false;
492
26b5bc98
AD		 493 router.valid = false;
494
771fe6b9
JG		 495 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
496 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
497 (ctx->bios + data_offset +
498 le16_to_cpu(obj_header->usDisplayPathTableOffset));
499 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
500 (ctx->bios + data_offset +
501 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
26b5bc98
AD		 502 router_obj = (ATOM_OBJECT_TABLE *)
503 (ctx->bios + data_offset +
504 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 505 device_support = le16_to_cpu(obj_header->usDeviceSupport);
506
507 path_size = 0;
508 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
509 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
510 ATOM_DISPLAY_OBJECT_PATH *path;
511 addr += path_size;
512 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
513 path_size += le16_to_cpu(path->usSize);
5137ee94 514
771fe6b9
JG		 515 if (device_support & le16_to_cpu(path->usDeviceTag)) {
516 uint8_t con_obj_id, con_obj_num, con_obj_type;
517
518 con_obj_id =
519 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
520 >> OBJECT_ID_SHIFT;
521 con_obj_num =
522 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
523 >> ENUM_ID_SHIFT;
524 con_obj_type =
525 (le16_to_cpu(path->usConnObjectId) &
526 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
527
4bbd4973
DA		 528 /* TODO CV support */
529 if (le16_to_cpu(path->usDeviceTag) ==
530 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 531 continue;
532
ee59f2b4
AD		 533 /* IGP chips */
534 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 535 (con_obj_id ==
536 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
537 uint16_t igp_offset = 0;
538 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
539
540 index =
541 GetIndexIntoMasterTable(DATA,
542 IntegratedSystemInfo);
543
a084e6ee
AD		 544 if (atom_parse_data_header(ctx, index, &size, &frev,
545 &crev, &igp_offset)) {
546
547 if (crev >= 2) {
548 igp_obj =
549 (ATOM_INTEGRATED_SYSTEM_INFO_V2
550 *) (ctx->bios + igp_offset);
551
552 if (igp_obj) {
553 uint32_t slot_config, ct;
554
555 if (con_obj_num == 1)
556 slot_config =
557 igp_obj->
558 ulDDISlot1Config;
559 else
560 slot_config =
561 igp_obj->
562 ulDDISlot2Config;
563
564 ct = (slot_config >> 16) & 0xff;
565 connector_type =
566 object_connector_convert
567 [ct];
568 connector_object_id = ct;
569 igp_lane_info =
570 slot_config & 0xffff;
571 } else
572 continue;
771fe6b9
JG		 573 } else
574 continue;
a084e6ee
AD		 575 } else {
576 igp_lane_info = 0;
577 connector_type =
578 object_connector_convert[con_obj_id];
579 connector_object_id = con_obj_id;
580 }
771fe6b9
JG		 581 } else {
582 igp_lane_info = 0;
583 connector_type =
584 object_connector_convert[con_obj_id];
b75fad06 585 connector_object_id = con_obj_id;
771fe6b9
JG		 586 }
587
588 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
589 continue;
590
26b5bc98
AD		 591 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
592 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 593
26b5bc98 594 grph_obj_id =
771fe6b9
JG		 595 (le16_to_cpu(path->usGraphicObjIds[j]) &
596 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 597 grph_obj_num =
771fe6b9
JG		 598 (le16_to_cpu(path->usGraphicObjIds[j]) &
599 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 600 grph_obj_type =
771fe6b9
JG		 601 (le16_to_cpu(path->usGraphicObjIds[j]) &
602 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
603
26b5bc98 604 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
5137ee94 605 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
771fe6b9
JG		 606
607 radeon_add_atom_encoder(dev,
5137ee94 608 encoder_obj,
771fe6b9
JG		 609 le16_to_cpu
610 (path->
611 usDeviceTag));
612
26b5bc98
AD		 613 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
614 router.valid = false;
615 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
616 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
617 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
618 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
619 (ctx->bios + data_offset +
620 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
621 ATOM_I2C_RECORD *i2c_record;
622 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
623 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
624 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
625 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
626 (ctx->bios + data_offset +
627 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
628 int enum_id;
629
630 router.router_id = router_obj_id;
631 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
632 enum_id++) {
633 if (le16_to_cpu(path->usConnObjectId) ==
634 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
635 break;
636 }
637
638 while (record->ucRecordType > 0 &&
639 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
640 switch (record->ucRecordType) {
641 case ATOM_I2C_RECORD_TYPE:
642 i2c_record =
643 (ATOM_I2C_RECORD *)
644 record;
645 i2c_config =
646 (ATOM_I2C_ID_CONFIG_ACCESS *)
647 &i2c_record->sucI2cId;
648 router.i2c_info =
649 radeon_lookup_i2c_gpio(rdev,
650 i2c_config->
651 ucAccess);
652 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
653 break;
654 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
655 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
656 record;
657 router.valid = true;
658 router.mux_type = ddc_path->ucMuxType;
659 router.mux_control_pin = ddc_path->ucMuxControlPin;
660 router.mux_state = ddc_path->ucMuxState[enum_id];
661 break;
662 }
663 record = (ATOM_COMMON_RECORD_HEADER *)
664 ((char *)record + record->ucRecordSize);
665 }
666 }
667 }
771fe6b9
JG		 668 }
669 }
670
eed45b30 671 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 672 ddc_bus.valid = false;
673 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 674 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 675 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 676 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
677 if (le16_to_cpu(path->usConnObjectId) ==
678 le16_to_cpu(con_obj->asObjects[j].
679 usObjectID)) {
680 ATOM_COMMON_RECORD_HEADER
681 *record =
682 (ATOM_COMMON_RECORD_HEADER
683 *)
684 (ctx->bios + data_offset +
685 le16_to_cpu(con_obj->
686 asObjects[j].
687 usRecordOffset));
688 ATOM_I2C_RECORD *i2c_record;
eed45b30 689 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 690 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 691
771fe6b9
JG		 692 while (record->ucRecordType > 0
693 && record->
694 ucRecordType <=
695 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 696 switch (record->ucRecordType) {
771fe6b9
JG		 697 case ATOM_I2C_RECORD_TYPE:
698 i2c_record =
eed45b30
AD		 699 (ATOM_I2C_RECORD *)
700 record;
d3f420d1
AD		 701 i2c_config =
702 (ATOM_I2C_ID_CONFIG_ACCESS *)
703 &i2c_record->sucI2cId;
eed45b30 704 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 705 i2c_config->
706 ucAccess);
eed45b30
AD		 707 break;
708 case ATOM_HPD_INT_RECORD_TYPE:
709 hpd_record =
710 (ATOM_HPD_INT_RECORD *)
711 record;
712 gpio = radeon_lookup_gpio(rdev,
713 hpd_record->ucHPDIntGPIOID);
714 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
715 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 716 break;
717 }
718 record =
719 (ATOM_COMMON_RECORD_HEADER
720 *) ((char *)record
721 +
722 record->
723 ucRecordSize);
724 }
725 break;
726 }
727 }
eed45b30 728 }
771fe6b9 729
bcc1c2a1 730 /* needed for aux chan transactions */
8e36ed00 731 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 732
705af9c7
AD		 733 conn_id = le16_to_cpu(path->usConnObjectId);
734
735 if (!radeon_atom_apply_quirks
736 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 737 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 738 continue;
739
771fe6b9 740 radeon_add_atom_connector(dev,
705af9c7 741 conn_id,
771fe6b9
JG		 742 le16_to_cpu(path->
743 usDeviceTag),
744 connector_type, &ddc_bus,
5137ee94 745 igp_lane_info,
eed45b30 746 connector_object_id,
26b5bc98
AD		 747 &hpd,
748 &router);
771fe6b9
JG		 749
750 }
751 }
752
753 radeon_link_encoder_connector(dev);
754
755 return true;
756}
757
b75fad06
AD		 758static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
759 int connector_type,
760 uint16_t devices)
761{
762 struct radeon_device *rdev = dev->dev_private;
763
764 if (rdev->flags & RADEON_IS_IGP) {
765 return supported_devices_connector_object_id_convert
766 [connector_type];
767 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
768 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
769 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
770 struct radeon_mode_info *mode_info = &rdev->mode_info;
771 struct atom_context *ctx = mode_info->atom_context;
772 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
773 uint16_t size, data_offset;
774 uint8_t frev, crev;
775 ATOM_XTMDS_INFO *xtmds;
776
a084e6ee
AD		 777 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
778 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 779
a084e6ee
AD		 780 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
781 if (connector_type == DRM_MODE_CONNECTOR_DVII)
782 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
783 else
784 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
785 } else {
786 if (connector_type == DRM_MODE_CONNECTOR_DVII)
787 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
788 else
789 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
790 }
791 } else
792 return supported_devices_connector_object_id_convert
793 [connector_type];
b75fad06
AD		 794 } else {
795 return supported_devices_connector_object_id_convert
796 [connector_type];
797 }
798}
799
771fe6b9
JG		 800struct bios_connector {
801 bool valid;
705af9c7 802 uint16_t line_mux;
771fe6b9
JG		 803 uint16_t devices;
804 int connector_type;
805 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 806 struct radeon_hpd hpd;
771fe6b9
JG		 807};
808
809bool radeon_get_atom_connector_info_from_supported_devices_table(struct
810 drm_device
811 *dev)
812{
813 struct radeon_device *rdev = dev->dev_private;
814 struct radeon_mode_info *mode_info = &rdev->mode_info;
815 struct atom_context *ctx = mode_info->atom_context;
816 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
817 uint16_t size, data_offset;
818 uint8_t frev, crev;
819 uint16_t device_support;
820 uint8_t dac;
821 union atom_supported_devices *supported_devices;
eed45b30 822 int i, j, max_device;
f49d273d
PB		 823 struct bios_connector *bios_connectors;
824 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 825 struct radeon_router router;
826
827 router.valid = false;
771fe6b9 828
f49d273d
PB		 829 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
830 if (!bios_connectors)
831 return false;
832
833 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
834 &data_offset)) {
835 kfree(bios_connectors);
a084e6ee 836 return false;
f49d273d 837 }
771fe6b9
JG		 838
839 supported_devices =
840 (union atom_supported_devices *)(ctx->bios + data_offset);
841
842 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
843
eed45b30
AD		 844 if (frev > 1)
845 max_device = ATOM_MAX_SUPPORTED_DEVICE;
846 else
847 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
848
849 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 850 ATOM_CONNECTOR_INFO_I2C ci =
851 supported_devices->info.asConnInfo[i];
852
853 bios_connectors[i].valid = false;
854
855 if (!(device_support & (1 << i))) {
856 continue;
857 }
858
859 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 860 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 861 continue;
862 }
863
771fe6b9
JG		 864 bios_connectors[i].connector_type =
865 supported_devices_connector_convert[ci.sucConnectorInfo.
866 sbfAccess.
867 bfConnectorType];
868
869 if (bios_connectors[i].connector_type ==
870 DRM_MODE_CONNECTOR_Unknown)
871 continue;
872
873 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
874
d3f420d1
AD		 875 bios_connectors[i].line_mux =
876 ci.sucI2cId.ucAccess;
771fe6b9
JG		 877
878 /* give tv unique connector ids */
879 if (i == ATOM_DEVICE_TV1_INDEX) {
880 bios_connectors[i].ddc_bus.valid = false;
881 bios_connectors[i].line_mux = 50;
882 } else if (i == ATOM_DEVICE_TV2_INDEX) {
883 bios_connectors[i].ddc_bus.valid = false;
884 bios_connectors[i].line_mux = 51;
885 } else if (i == ATOM_DEVICE_CV_INDEX) {
886 bios_connectors[i].ddc_bus.valid = false;
887 bios_connectors[i].line_mux = 52;
888 } else
889 bios_connectors[i].ddc_bus =
eed45b30
AD		 890 radeon_lookup_i2c_gpio(rdev,
891 bios_connectors[i].line_mux);
892
893 if ((crev > 1) && (frev > 1)) {
894 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
895 switch (isb) {
896 case 0x4:
897 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
898 break;
899 case 0xa:
900 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
901 break;
902 default:
903 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
904 break;
905 }
906 } else {
907 if (i == ATOM_DEVICE_DFP1_INDEX)
908 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
909 else if (i == ATOM_DEVICE_DFP2_INDEX)
910 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
911 else
912 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
913 }
771fe6b9
JG		 914
915 /* Always set the connector type to VGA for CRT1/CRT2. if they are
916 * shared with a DVI port, we'll pick up the DVI connector when we
917 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
918 */
919 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
920 bios_connectors[i].connector_type =
921 DRM_MODE_CONNECTOR_VGA;
922
923 if (!radeon_atom_apply_quirks
924 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 925 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
926 &bios_connectors[i].hpd))
771fe6b9
JG		 927 continue;
928
929 bios_connectors[i].valid = true;
930 bios_connectors[i].devices = (1 << i);
931
932 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
933 radeon_add_atom_encoder(dev,
5137ee94 934 radeon_get_encoder_enum(dev,
771fe6b9
JG		 935 (1 << i),
936 dac),
937 (1 << i));
938 else
939 radeon_add_legacy_encoder(dev,
5137ee94 940 radeon_get_encoder_enum(dev,
f56cd64f 941 (1 << i),
771fe6b9
JG		 942 dac),
943 (1 << i));
944 }
945
946 /* combine shared connectors */
eed45b30 947 for (i = 0; i < max_device; i++) {
771fe6b9 948 if (bios_connectors[i].valid) {
eed45b30 949 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 950 if (bios_connectors[j].valid && (i != j)) {
951 if (bios_connectors[i].line_mux ==
952 bios_connectors[j].line_mux) {
f56cd64f
AD		 953 /* make sure not to combine LVDS */
954 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
955 bios_connectors[i].line_mux = 53;
956 bios_connectors[i].ddc_bus.valid = false;
957 continue;
958 }
959 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
960 bios_connectors[j].line_mux = 53;
961 bios_connectors[j].ddc_bus.valid = false;
962 continue;
963 }
964 /* combine analog and digital for DVI-I */
965 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
966 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
967 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
968 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
969 bios_connectors[i].devices |=
970 bios_connectors[j].devices;
971 bios_connectors[i].connector_type =
972 DRM_MODE_CONNECTOR_DVII;
973 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 974 bios_connectors[i].hpd =
975 bios_connectors[j].hpd;
f56cd64f 976 bios_connectors[j].valid = false;
771fe6b9
JG		 977 }
978 }
979 }
980 }
981 }
982 }
983
984 /* add the connectors */
eed45b30 985 for (i = 0; i < max_device; i++) {
b75fad06
AD		 986 if (bios_connectors[i].valid) {
987 uint16_t connector_object_id =
988 atombios_get_connector_object_id(dev,
989 bios_connectors[i].connector_type,
990 bios_connectors[i].devices);
771fe6b9
JG		 991 radeon_add_atom_connector(dev,
992 bios_connectors[i].line_mux,
993 bios_connectors[i].devices,
994 bios_connectors[i].
995 connector_type,
996 &bios_connectors[i].ddc_bus,
5137ee94 997 0,
eed45b30 998 connector_object_id,
26b5bc98
AD		 999 &bios_connectors[i].hpd,
1000 &router);
b75fad06 1001 }
771fe6b9
JG		 1002 }
1003
1004 radeon_link_encoder_connector(dev);
1005
f49d273d 1006 kfree(bios_connectors);
771fe6b9
JG		 1007 return true;
1008}
1009
1010union firmware_info {
1011 ATOM_FIRMWARE_INFO info;
1012 ATOM_FIRMWARE_INFO_V1_2 info_12;
1013 ATOM_FIRMWARE_INFO_V1_3 info_13;
1014 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1015 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 1016};
1017
1018bool radeon_atom_get_clock_info(struct drm_device *dev)
1019{
1020 struct radeon_device *rdev = dev->dev_private;
1021 struct radeon_mode_info *mode_info = &rdev->mode_info;
1022 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1023 union firmware_info *firmware_info;
1024 uint8_t frev, crev;
1025 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1026 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1027 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1028 struct radeon_pll *spll = &rdev->clock.spll;
1029 struct radeon_pll *mpll = &rdev->clock.mpll;
1030 uint16_t data_offset;
1031
a084e6ee
AD		 1032 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1033 &frev, &crev, &data_offset)) {
1034 firmware_info =
1035 (union firmware_info *)(mode_info->atom_context->bios +
1036 data_offset);
771fe6b9
JG		 1037 /* pixel clocks */
1038 p1pll->reference_freq =
1039 le16_to_cpu(firmware_info->info.usReferenceClock);
1040 p1pll->reference_div = 0;
1041
bc293e58
MF		 1042 if (crev < 2)
1043 p1pll->pll_out_min =
1044 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1045 else
1046 p1pll->pll_out_min =
1047 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1048 p1pll->pll_out_max =
1049 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1050
86cb2bbf
AD		 1051 if (crev >= 4) {
1052 p1pll->lcd_pll_out_min =
1053 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1054 if (p1pll->lcd_pll_out_min == 0)
1055 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1056 p1pll->lcd_pll_out_max =
1057 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1058 if (p1pll->lcd_pll_out_max == 0)
1059 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1060 } else {
1061 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1062 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1063 }
1064
771fe6b9
JG		 1065 if (p1pll->pll_out_min == 0) {
1066 if (ASIC_IS_AVIVO(rdev))
1067 p1pll->pll_out_min = 64800;
1068 else
1069 p1pll->pll_out_min = 20000;
8f552a66
AD		 1070 } else if (p1pll->pll_out_min > 64800) {
1071 /* Limiting the pll output range is a good thing generally as
1072 * it limits the number of possible pll combinations for a given
1073 * frequency presumably to the ones that work best on each card.
1074 * However, certain duallink DVI monitors seem to like
1075 * pll combinations that would be limited by this at least on
1076 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1077 * family.
1078 */
b27b6375
AD		 1079 if (!radeon_new_pll)
1080 p1pll->pll_out_min = 64800;
771fe6b9
JG		 1081 }
1082
1083 p1pll->pll_in_min =
1084 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1085 p1pll->pll_in_max =
1086 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1087
1088 *p2pll = *p1pll;
1089
1090 /* system clock */
1091 spll->reference_freq =
1092 le16_to_cpu(firmware_info->info.usReferenceClock);
1093 spll->reference_div = 0;
1094
1095 spll->pll_out_min =
1096 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1097 spll->pll_out_max =
1098 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1099
1100 /* ??? */
1101 if (spll->pll_out_min == 0) {
1102 if (ASIC_IS_AVIVO(rdev))
1103 spll->pll_out_min = 64800;
1104 else
1105 spll->pll_out_min = 20000;
1106 }
1107
1108 spll->pll_in_min =
1109 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1110 spll->pll_in_max =
1111 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1112
1113 /* memory clock */
1114 mpll->reference_freq =
1115 le16_to_cpu(firmware_info->info.usReferenceClock);
1116 mpll->reference_div = 0;
1117
1118 mpll->pll_out_min =
1119 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1120 mpll->pll_out_max =
1121 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1122
1123 /* ??? */
1124 if (mpll->pll_out_min == 0) {
1125 if (ASIC_IS_AVIVO(rdev))
1126 mpll->pll_out_min = 64800;
1127 else
1128 mpll->pll_out_min = 20000;
1129 }
1130
1131 mpll->pll_in_min =
1132 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1133 mpll->pll_in_max =
1134 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1135
1136 rdev->clock.default_sclk =
1137 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1138 rdev->clock.default_mclk =
1139 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1140
bcc1c2a1
AD		 1141 if (ASIC_IS_DCE4(rdev)) {
1142 rdev->clock.default_dispclk =
1143 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1144 if (rdev->clock.default_dispclk == 0)
1145 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1146 rdev->clock.dp_extclk =
1147 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1148 }
1149 *dcpll = *p1pll;
1150
771fe6b9
JG		 1151 return true;
1152 }
bcc1c2a1 1153
771fe6b9
JG		 1154 return false;
1155}
1156
06b6476d
AD		 1157union igp_info {
1158 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1159 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1160};
1161
1162bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1163{
1164 struct radeon_mode_info *mode_info = &rdev->mode_info;
1165 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1166 union igp_info *igp_info;
1167 u8 frev, crev;
1168 u16 data_offset;
1169
4c70b2ea
AD		 1170 /* sideport is AMD only */
1171 if (rdev->family == CHIP_RS600)
1172 return false;
1173
a084e6ee
AD		 1174 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1175 &frev, &crev, &data_offset)) {
1176 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1177 data_offset);
06b6476d
AD		 1178 switch (crev) {
1179 case 1:
4c70b2ea
AD		 1180 if (igp_info->info.ulBootUpMemoryClock)
1181 return true;
06b6476d
AD		 1182 break;
1183 case 2:
1184 if (igp_info->info_2.ucMemoryType & 0x0f)
1185 return true;
1186 break;
1187 default:
1188 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1189 break;
1190 }
1191 }
1192 return false;
1193}
1194
445282db
DA		 1195bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1196 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1197{
1198 struct drm_device *dev = encoder->base.dev;
1199 struct radeon_device *rdev = dev->dev_private;
1200 struct radeon_mode_info *mode_info = &rdev->mode_info;
1201 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1202 uint16_t data_offset;
1203 struct _ATOM_TMDS_INFO *tmds_info;
1204 uint8_t frev, crev;
1205 uint16_t maxfreq;
1206 int i;
771fe6b9 1207
a084e6ee
AD		 1208 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1209 &frev, &crev, &data_offset)) {
1210 tmds_info =
1211 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1212 data_offset);
771fe6b9 1213
771fe6b9
JG		 1214 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1215 for (i = 0; i < 4; i++) {
1216 tmds->tmds_pll[i].freq =
1217 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1218 tmds->tmds_pll[i].value =
1219 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1220 tmds->tmds_pll[i].value |=
1221 (tmds_info->asMiscInfo[i].
1222 ucPLL_VCO_Gain & 0x3f) << 6;
1223 tmds->tmds_pll[i].value |=
1224 (tmds_info->asMiscInfo[i].
1225 ucPLL_DutyCycle & 0xf) << 12;
1226 tmds->tmds_pll[i].value |=
1227 (tmds_info->asMiscInfo[i].
1228 ucPLL_VoltageSwing & 0xf) << 16;
1229
d9fdaafb 1230 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1231 tmds->tmds_pll[i].freq,
1232 tmds->tmds_pll[i].value);
1233
1234 if (maxfreq == tmds->tmds_pll[i].freq) {
1235 tmds->tmds_pll[i].freq = 0xffffffff;
1236 break;
1237 }
1238 }
445282db 1239 return true;
771fe6b9 1240 }
445282db 1241 return false;
771fe6b9
JG		 1242}
1243
ebbe1cb9
AD		 1244static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1245 radeon_encoder
1246 *encoder,
1247 int id)
1248{
1249 struct drm_device *dev = encoder->base.dev;
1250 struct radeon_device *rdev = dev->dev_private;
1251 struct radeon_mode_info *mode_info = &rdev->mode_info;
1252 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1253 uint16_t data_offset;
1254 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1255 uint8_t frev, crev;
1256 struct radeon_atom_ss *ss = NULL;
279b215e 1257 int i;
ebbe1cb9
AD		 1258
1259 if (id > ATOM_MAX_SS_ENTRY)
1260 return NULL;
1261
a084e6ee
AD		 1262 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1263 &frev, &crev, &data_offset)) {
1264 ss_info =
1265 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1266
ebbe1cb9
AD		 1267 ss =
1268 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1269
1270 if (!ss)
1271 return NULL;
1272
279b215e
AD		 1273 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1274 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1275 ss->percentage =
1276 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1277 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1278 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1279 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1280 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1281 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1d3d51b6 1282 break;
279b215e
AD		 1283 }
1284 }
ebbe1cb9
AD		 1285 }
1286 return ss;
1287}
1288
771fe6b9
JG		 1289union lvds_info {
1290 struct _ATOM_LVDS_INFO info;
1291 struct _ATOM_LVDS_INFO_V12 info_12;
1292};
1293
1294struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1295 radeon_encoder
1296 *encoder)
1297{
1298 struct drm_device *dev = encoder->base.dev;
1299 struct radeon_device *rdev = dev->dev_private;
1300 struct radeon_mode_info *mode_info = &rdev->mode_info;
1301 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1302 uint16_t data_offset, misc;
771fe6b9
JG		 1303 union lvds_info *lvds_info;
1304 uint8_t frev, crev;
1305 struct radeon_encoder_atom_dig *lvds = NULL;
5137ee94 1306 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9 1307
a084e6ee
AD		 1308 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1309 &frev, &crev, &data_offset)) {
1310 lvds_info =
1311 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1312 lvds =
1313 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1314
1315 if (!lvds)
1316 return NULL;
1317
de2103e4 1318 lvds->native_mode.clock =
771fe6b9 1319 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1320 lvds->native_mode.hdisplay =
771fe6b9 1321 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1322 lvds->native_mode.vdisplay =
771fe6b9 1323 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1324 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1325 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1326 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1327 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1328 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1329 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1330 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1331 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1332 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1333 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1334 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1335 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1336 lvds->panel_pwr_delay =
1337 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1338 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1339
1340 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1341 if (misc & ATOM_VSYNC_POLARITY)
1342 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1343 if (misc & ATOM_HSYNC_POLARITY)
1344 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1345 if (misc & ATOM_COMPOSITESYNC)
1346 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1347 if (misc & ATOM_INTERLACE)
1348 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1349 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1350 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1351
de2103e4
AD		 1352 /* set crtc values */
1353 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1354
ebbe1cb9
AD		 1355 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1356
7c27f87d 1357 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 1358 if (radeon_new_pll == 0)
1359 lvds->pll_algo = PLL_ALGO_LEGACY;
1360 else
1361 lvds->pll_algo = PLL_ALGO_NEW;
1362 } else {
1363 if (radeon_new_pll == 1)
1364 lvds->pll_algo = PLL_ALGO_NEW;
7c27f87d
AD		 1365 else
1366 lvds->pll_algo = PLL_ALGO_LEGACY;
383be5d1 1367 }
7c27f87d 1368
771fe6b9 1369 encoder->native_mode = lvds->native_mode;
5137ee94
AD		 1370
1371 if (encoder_enum == 2)
1372 lvds->linkb = true;
1373 else
1374 lvds->linkb = false;
1375
771fe6b9
JG		 1376 }
1377 return lvds;
1378}
1379
6fe7ac3f
AD		 1380struct radeon_encoder_primary_dac *
1381radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1382{
1383 struct drm_device *dev = encoder->base.dev;
1384 struct radeon_device *rdev = dev->dev_private;
1385 struct radeon_mode_info *mode_info = &rdev->mode_info;
1386 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1387 uint16_t data_offset;
1388 struct _COMPASSIONATE_DATA *dac_info;
1389 uint8_t frev, crev;
1390 uint8_t bg, dac;
6fe7ac3f
AD		 1391 struct radeon_encoder_primary_dac *p_dac = NULL;
1392
a084e6ee
AD		 1393 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1394 &frev, &crev, &data_offset)) {
1395 dac_info = (struct _COMPASSIONATE_DATA *)
1396 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1397
6fe7ac3f
AD		 1398 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1399
1400 if (!p_dac)
1401 return NULL;
1402
1403 bg = dac_info->ucDAC1_BG_Adjustment;
1404 dac = dac_info->ucDAC1_DAC_Adjustment;
1405 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1406
1407 }
1408 return p_dac;
1409}
1410
4ce001ab 1411bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1412 struct drm_display_mode *mode)
4ce001ab
DA		 1413{
1414 struct radeon_mode_info *mode_info = &rdev->mode_info;
1415 ATOM_ANALOG_TV_INFO *tv_info;
1416 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1417 ATOM_DTD_FORMAT *dtd_timings;
1418 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1419 u8 frev, crev;
5a9bcacc 1420 u16 data_offset, misc;
4ce001ab 1421
a084e6ee
AD		 1422 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1423 &frev, &crev, &data_offset))
1424 return false;
4ce001ab
DA		 1425
1426 switch (crev) {
1427 case 1:
1428 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1429 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1430 return false;
1431
5a9bcacc
AD		 1432 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1433 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1434 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1435 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1436 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1437
1438 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1439 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1440 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1441 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1442 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1443
1444 mode->flags = 0;
1445 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1446 if (misc & ATOM_VSYNC_POLARITY)
1447 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1448 if (misc & ATOM_HSYNC_POLARITY)
1449 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1450 if (misc & ATOM_COMPOSITESYNC)
1451 mode->flags |= DRM_MODE_FLAG_CSYNC;
1452 if (misc & ATOM_INTERLACE)
1453 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1454 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1455 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1456
1457 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1458
1459 if (index == 1) {
1460 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1461 mode->crtc_htotal -= 1;
1462 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1463 }
1464 break;
1465 case 2:
1466 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1467 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1468 return false;
1469
1470 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1471 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1472 le16_to_cpu(dtd_timings->usHBlanking_Time);
1473 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1474 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1475 le16_to_cpu(dtd_timings->usHSyncOffset);
1476 mode->crtc_hsync_end = mode->crtc_hsync_start +
1477 le16_to_cpu(dtd_timings->usHSyncWidth);
1478
1479 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1480 le16_to_cpu(dtd_timings->usVBlanking_Time);
1481 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1482 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1483 le16_to_cpu(dtd_timings->usVSyncOffset);
1484 mode->crtc_vsync_end = mode->crtc_vsync_start +
1485 le16_to_cpu(dtd_timings->usVSyncWidth);
1486
1487 mode->flags = 0;
1488 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1489 if (misc & ATOM_VSYNC_POLARITY)
1490 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1491 if (misc & ATOM_HSYNC_POLARITY)
1492 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1493 if (misc & ATOM_COMPOSITESYNC)
1494 mode->flags |= DRM_MODE_FLAG_CSYNC;
1495 if (misc & ATOM_INTERLACE)
1496 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1497 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1498 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1499
1500 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1501 break;
1502 }
1503 return true;
1504}
1505
d79766fa
AD		 1506enum radeon_tv_std
1507radeon_atombios_get_tv_info(struct radeon_device *rdev)
1508{
1509 struct radeon_mode_info *mode_info = &rdev->mode_info;
1510 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1511 uint16_t data_offset;
1512 uint8_t frev, crev;
1513 struct _ATOM_ANALOG_TV_INFO *tv_info;
1514 enum radeon_tv_std tv_std = TV_STD_NTSC;
1515
a084e6ee
AD		 1516 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1517 &frev, &crev, &data_offset)) {
d79766fa 1518
a084e6ee
AD		 1519 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1520 (mode_info->atom_context->bios + data_offset);
d79766fa 1521
a084e6ee
AD		 1522 switch (tv_info->ucTV_BootUpDefaultStandard) {
1523 case ATOM_TV_NTSC:
1524 tv_std = TV_STD_NTSC;
1525 DRM_INFO("Default TV standard: NTSC\n");
1526 break;
1527 case ATOM_TV_NTSCJ:
1528 tv_std = TV_STD_NTSC_J;
1529 DRM_INFO("Default TV standard: NTSC-J\n");
1530 break;
1531 case ATOM_TV_PAL:
1532 tv_std = TV_STD_PAL;
1533 DRM_INFO("Default TV standard: PAL\n");
1534 break;
1535 case ATOM_TV_PALM:
1536 tv_std = TV_STD_PAL_M;
1537 DRM_INFO("Default TV standard: PAL-M\n");
1538 break;
1539 case ATOM_TV_PALN:
1540 tv_std = TV_STD_PAL_N;
1541 DRM_INFO("Default TV standard: PAL-N\n");
1542 break;
1543 case ATOM_TV_PALCN:
1544 tv_std = TV_STD_PAL_CN;
1545 DRM_INFO("Default TV standard: PAL-CN\n");
1546 break;
1547 case ATOM_TV_PAL60:
1548 tv_std = TV_STD_PAL_60;
1549 DRM_INFO("Default TV standard: PAL-60\n");
1550 break;
1551 case ATOM_TV_SECAM:
1552 tv_std = TV_STD_SECAM;
1553 DRM_INFO("Default TV standard: SECAM\n");
1554 break;
1555 default:
1556 tv_std = TV_STD_NTSC;
1557 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1558 break;
1559 }
d79766fa
AD		 1560 }
1561 return tv_std;
1562}
1563
6fe7ac3f
AD		 1564struct radeon_encoder_tv_dac *
1565radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1566{
1567 struct drm_device *dev = encoder->base.dev;
1568 struct radeon_device *rdev = dev->dev_private;
1569 struct radeon_mode_info *mode_info = &rdev->mode_info;
1570 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1571 uint16_t data_offset;
1572 struct _COMPASSIONATE_DATA *dac_info;
1573 uint8_t frev, crev;
1574 uint8_t bg, dac;
6fe7ac3f
AD		 1575 struct radeon_encoder_tv_dac *tv_dac = NULL;
1576
a084e6ee
AD		 1577 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1578 &frev, &crev, &data_offset)) {
6fe7ac3f 1579
a084e6ee
AD		 1580 dac_info = (struct _COMPASSIONATE_DATA *)
1581 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1582
6fe7ac3f
AD		 1583 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1584
1585 if (!tv_dac)
1586 return NULL;
1587
1588 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1589 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1590 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1591
1592 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1593 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1594 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1595
1596 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1597 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1598 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1599
d79766fa 1600 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1601 }
1602 return tv_dac;
1603}
1604
29fb52ca
AD		 1605static const char *thermal_controller_names[] = {
1606 "NONE",
678e7dfa
AD		 1607 "lm63",
1608 "adm1032",
1609 "adm1030",
1610 "max6649",
1611 "lm64",
1612 "f75375",
1613 "asc7xxx",
29fb52ca
AD		 1614};
1615
1616static const char *pp_lib_thermal_controller_names[] = {
1617 "NONE",
678e7dfa
AD		 1618 "lm63",
1619 "adm1032",
1620 "adm1030",
1621 "max6649",
1622 "lm64",
1623 "f75375",
29fb52ca
AD		 1624 "RV6xx",
1625 "RV770",
678e7dfa 1626 "adt7473",
49f65982
AD		 1627 "External GPIO",
1628 "Evergreen",
678e7dfa 1629 "adt7473 with internal",
49f65982 1630
29fb52ca
AD		 1631};
1632
56278a8e
AD		 1633union power_info {
1634 struct _ATOM_POWERPLAY_INFO info;
1635 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1636 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1637 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1638};
1639
1640void radeon_atombios_get_power_modes(struct radeon_device *rdev)
771fe6b9 1641{
56278a8e
AD		 1642 struct radeon_mode_info *mode_info = &rdev->mode_info;
1643 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1644 u16 data_offset;
1645 u8 frev, crev;
1646 u32 misc, misc2 = 0, sclk, mclk;
1647 union power_info *power_info;
1648 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1649 struct _ATOM_PPLIB_STATE *power_state;
1650 int num_modes = 0, i, j;
1651 int state_index = 0, mode_index = 0;
29fb52ca 1652 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1653
a48b9b4e 1654 rdev->pm.default_power_state_index = -1;
56278a8e 1655
a084e6ee
AD		 1656 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1657 &frev, &crev, &data_offset)) {
1658 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
56278a8e 1659 if (frev < 4) {
29fb52ca
AD		 1660 /* add the i2c bus for thermal/fan chip */
1661 if (power_info->info.ucOverdriveThermalController > 0) {
1662 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1663 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1664 power_info->info.ucOverdriveControllerAddress >> 1);
1665 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
f376b94f 1666 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1667 if (rdev->pm.i2c_bus) {
1668 struct i2c_board_info info = { };
1669 const char *name = thermal_controller_names[power_info->info.
1670 ucOverdriveThermalController];
1671 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1672 strlcpy(info.type, name, sizeof(info.type));
1673 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1674 }
29fb52ca 1675 }
56278a8e
AD		 1676 num_modes = power_info->info.ucNumOfPowerModeEntries;
1677 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1678 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
02b17cc0 1679 /* last mode is usually default, array is low to high */
56278a8e
AD		 1680 for (i = 0; i < num_modes; i++) {
1681 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1682 switch (frev) {
1683 case 1:
1684 rdev->pm.power_state[state_index].num_clock_modes = 1;
1685 rdev->pm.power_state[state_index].clock_info[0].mclk =
1686 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1687 rdev->pm.power_state[state_index].clock_info[0].sclk =
1688 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1689 /* skip invalid modes */
1690 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1691 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1692 continue;
79daedc9 1693 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1694 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1695 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
84d88f4c
AD		 1696 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1697 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1698 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1699 VOLTAGE_GPIO;
1700 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1701 radeon_lookup_gpio(rdev,
1702 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1703 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1704 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1705 true;
1706 else
1707 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1708 false;
1709 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1710 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1711 VOLTAGE_VDDC;
1712 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1713 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1714 }
d7311171 1715 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9 1716 rdev->pm.power_state[state_index].misc = misc;
0ec0e74f
AD		 1717 /* order matters! */
1718 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1719 rdev->pm.power_state[state_index].type =
1720 POWER_STATE_TYPE_POWERSAVE;
1721 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1722 rdev->pm.power_state[state_index].type =
1723 POWER_STATE_TYPE_BATTERY;
1724 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1725 rdev->pm.power_state[state_index].type =
1726 POWER_STATE_TYPE_BATTERY;
1727 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1728 rdev->pm.power_state[state_index].type =
1729 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1730 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1731 rdev->pm.power_state[state_index].type =
1732 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1733 rdev->pm.power_state[state_index].flags &=
d7311171 1734 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1735 }
56278a8e 1736 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1737 rdev->pm.power_state[state_index].type =
1738 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1739 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1740 rdev->pm.power_state[state_index].default_clock_mode =
1741 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1742 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1743 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1744 } else if (state_index == 0) {
1745 rdev->pm.power_state[state_index].clock_info[0].flags |=
1746 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1747 }
1748 state_index++;
1749 break;
1750 case 2:
1751 rdev->pm.power_state[state_index].num_clock_modes = 1;
1752 rdev->pm.power_state[state_index].clock_info[0].mclk =
1753 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1754 rdev->pm.power_state[state_index].clock_info[0].sclk =
1755 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1756 /* skip invalid modes */
1757 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1758 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1759 continue;
79daedc9 1760 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1761 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1762 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1763 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1764 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1765 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1766 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1767 VOLTAGE_GPIO;
1768 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1769 radeon_lookup_gpio(rdev,
1770 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1771 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1772 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1773 true;
1774 else
1775 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1776 false;
1777 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1778 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1779 VOLTAGE_VDDC;
1780 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1781 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1782 }
d7311171 1783 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1784 rdev->pm.power_state[state_index].misc = misc;
1785 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1786 /* order matters! */
1787 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1788 rdev->pm.power_state[state_index].type =
1789 POWER_STATE_TYPE_POWERSAVE;
1790 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1791 rdev->pm.power_state[state_index].type =
1792 POWER_STATE_TYPE_BATTERY;
1793 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1794 rdev->pm.power_state[state_index].type =
1795 POWER_STATE_TYPE_BATTERY;
1796 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1797 rdev->pm.power_state[state_index].type =
1798 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1799 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1800 rdev->pm.power_state[state_index].type =
1801 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1802 rdev->pm.power_state[state_index].flags &=
d7311171 1803 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1804 }
0ec0e74f
AD		 1805 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1806 rdev->pm.power_state[state_index].type =
1807 POWER_STATE_TYPE_BALANCED;
a48b9b4e
AD		 1808 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1809 rdev->pm.power_state[state_index].flags &=
d7311171 1810 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1811 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1812 rdev->pm.power_state[state_index].type =
1813 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1814 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1815 rdev->pm.power_state[state_index].default_clock_mode =
1816 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1817 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1818 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1819 } else if (state_index == 0) {
1820 rdev->pm.power_state[state_index].clock_info[0].flags |=
1821 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1822 }
1823 state_index++;
1824 break;
1825 case 3:
1826 rdev->pm.power_state[state_index].num_clock_modes = 1;
1827 rdev->pm.power_state[state_index].clock_info[0].mclk =
1828 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1829 rdev->pm.power_state[state_index].clock_info[0].sclk =
1830 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1831 /* skip invalid modes */
1832 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1833 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1834 continue;
79daedc9 1835 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1836 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1837 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1838 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1839 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1840 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1841 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1842 VOLTAGE_GPIO;
1843 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1844 radeon_lookup_gpio(rdev,
1845 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1846 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1847 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1848 true;
1849 else
1850 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1851 false;
1852 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1853 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1854 VOLTAGE_VDDC;
1855 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1856 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1857 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1858 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1859 true;
1860 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1861 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1862 }
1863 }
d7311171 1864 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1865 rdev->pm.power_state[state_index].misc = misc;
1866 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1867 /* order matters! */
1868 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1869 rdev->pm.power_state[state_index].type =
1870 POWER_STATE_TYPE_POWERSAVE;
1871 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1872 rdev->pm.power_state[state_index].type =
1873 POWER_STATE_TYPE_BATTERY;
1874 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1875 rdev->pm.power_state[state_index].type =
1876 POWER_STATE_TYPE_BATTERY;
1877 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1878 rdev->pm.power_state[state_index].type =
1879 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1880 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1881 rdev->pm.power_state[state_index].type =
1882 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1883 rdev->pm.power_state[state_index].flags &=
d7311171 1884 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1885 }
0ec0e74f
AD		 1886 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1887 rdev->pm.power_state[state_index].type =
1888 POWER_STATE_TYPE_BALANCED;
56278a8e 1889 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1890 rdev->pm.power_state[state_index].type =
1891 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1892 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1893 rdev->pm.power_state[state_index].default_clock_mode =
1894 &rdev->pm.power_state[state_index].clock_info[0];
d7311171
AD		 1895 } else if (state_index == 0) {
1896 rdev->pm.power_state[state_index].clock_info[0].flags |=
1897 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1898 }
1899 state_index++;
1900 break;
1901 }
1902 }
02b17cc0 1903 /* last mode is usually default */
a48b9b4e 1904 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 1905 rdev->pm.power_state[state_index - 1].type =
1906 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1907 rdev->pm.default_power_state_index = state_index - 1;
02b17cc0
AD		 1908 rdev->pm.power_state[state_index - 1].default_clock_mode =
1909 &rdev->pm.power_state[state_index - 1].clock_info[0];
a48b9b4e 1910 rdev->pm.power_state[state_index].flags &=
d7311171 1911 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1912 rdev->pm.power_state[state_index].misc = 0;
1913 rdev->pm.power_state[state_index].misc2 = 0;
02b17cc0 1914 }
49f65982 1915 } else {
c5e8ce61
AD		 1916 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1917 uint8_t fw_frev, fw_crev;
1918 uint16_t fw_data_offset, vddc = 0;
1919 union firmware_info *firmware_info;
1920 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1921
1922 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1923 &fw_frev, &fw_crev, &fw_data_offset)) {
1924 firmware_info =
1925 (union firmware_info *)(mode_info->atom_context->bios +
1926 fw_data_offset);
1927 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1928 }
1929
29fb52ca 1930 /* add the i2c bus for thermal/fan chip */
678e7dfa 1931 if (controller->ucType > 0) {
21a8122a 1932 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
29fb52ca 1933 DRM_INFO("Internal thermal controller %s fan control\n",
678e7dfa 1934 (controller->ucFanParameters &
29fb52ca 1935 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
21a8122a
AD		 1936 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1937 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1938 DRM_INFO("Internal thermal controller %s fan control\n",
1939 (controller->ucFanParameters &
1940 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1941 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1942 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1943 DRM_INFO("Internal thermal controller %s fan control\n",
1944 (controller->ucFanParameters &
1945 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1946 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
678e7dfa 1947 } else if ((controller->ucType ==
49f65982 1948 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
678e7dfa 1949 (controller->ucType ==
49f65982
AD		 1950 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1951 DRM_INFO("Special thermal controller config\n");
29fb52ca
AD		 1952 } else {
1953 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
678e7dfa
AD		 1954 pp_lib_thermal_controller_names[controller->ucType],
1955 controller->ucI2cAddress >> 1,
1956 (controller->ucFanParameters &
29fb52ca 1957 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
678e7dfa 1958 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
f376b94f 1959 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1960 if (rdev->pm.i2c_bus) {
1961 struct i2c_board_info info = { };
1962 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1963 info.addr = controller->ucI2cAddress >> 1;
1964 strlcpy(info.type, name, sizeof(info.type));
1965 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1966 }
1967
29fb52ca
AD		 1968 }
1969 }
02b17cc0 1970 /* first mode is usually default, followed by low to high */
56278a8e
AD		 1971 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1972 mode_index = 0;
1973 power_state = (struct _ATOM_PPLIB_STATE *)
1974 (mode_info->atom_context->bios +
1975 data_offset +
1976 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1977 i * power_info->info_4.ucStateEntrySize);
1978 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1979 (mode_info->atom_context->bios +
1980 data_offset +
1981 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1982 (power_state->ucNonClockStateIndex *
1983 power_info->info_4.ucNonClockSize));
56278a8e
AD		 1984 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1985 if (rdev->flags & RADEON_IS_IGP) {
1986 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1987 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1988 (mode_info->atom_context->bios +
1989 data_offset +
1990 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1991 (power_state->ucClockStateIndices[j] *
1992 power_info->info_4.ucClockInfoSize));
1993 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1994 sclk |= clock_info->ucLowEngineClockHigh << 16;
1995 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1996 /* skip invalid modes */
1997 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1998 continue;
aa1df0f2 1999 /* voltage works differently on IGPs */
56278a8e 2000 mode_index++;
49f65982
AD		 2001 } else if (ASIC_IS_DCE4(rdev)) {
2002 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2003 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2004 (mode_info->atom_context->bios +
2005 data_offset +
2006 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2007 (power_state->ucClockStateIndices[j] *
2008 power_info->info_4.ucClockInfoSize));
2009 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2010 sclk |= clock_info->ucEngineClockHigh << 16;
2011 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2012 mclk |= clock_info->ucMemoryClockHigh << 16;
2013 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2014 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2015 /* skip invalid modes */
2016 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2017 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2018 continue;
49f65982
AD		 2019 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2020 VOLTAGE_SW;
2021 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2022 clock_info->usVDDC;
2023 /* XXX usVDDCI */
2024 mode_index++;
56278a8e
AD		 2025 } else {
2026 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2027 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2028 (mode_info->atom_context->bios +
2029 data_offset +
2030 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2031 (power_state->ucClockStateIndices[j] *
2032 power_info->info_4.ucClockInfoSize));
2033 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2034 sclk |= clock_info->ucEngineClockHigh << 16;
2035 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2036 mclk |= clock_info->ucMemoryClockHigh << 16;
2037 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2038 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2039 /* skip invalid modes */
2040 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2041 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2042 continue;
56278a8e
AD		 2043 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2044 VOLTAGE_SW;
2045 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2046 clock_info->usVDDC;
2047 mode_index++;
2048 }
2049 }
2050 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2051 if (mode_index) {
845db70d 2052 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 2053 misc2 = le16_to_cpu(non_clock_info->usClassification);
79daedc9
AD		 2054 rdev->pm.power_state[state_index].misc = misc;
2055 rdev->pm.power_state[state_index].misc2 = misc2;
2056 rdev->pm.power_state[state_index].pcie_lanes =
845db70d
RM		 2057 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2058 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 2059 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2060 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_BATTERY;
2063 break;
2064 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2065 rdev->pm.power_state[state_index].type =
2066 POWER_STATE_TYPE_BALANCED;
2067 break;
2068 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2069 rdev->pm.power_state[state_index].type =
2070 POWER_STATE_TYPE_PERFORMANCE;
2071 break;
a44d2f37
AD		 2072 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2073 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2074 rdev->pm.power_state[state_index].type =
2075 POWER_STATE_TYPE_PERFORMANCE;
2076 break;
0ec0e74f 2077 }
a48b9b4e
AD		 2078 rdev->pm.power_state[state_index].flags = 0;
2079 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2080 rdev->pm.power_state[state_index].flags |=
d7311171 2081 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 2082 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 2083 rdev->pm.power_state[state_index].type =
2084 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2085 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 2086 rdev->pm.power_state[state_index].default_clock_mode =
2087 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
c5e8ce61
AD		 2088 /* patch the table values with the default slck/mclk from firmware info */
2089 for (j = 0; j < mode_index; j++) {
2090 rdev->pm.power_state[state_index].clock_info[j].mclk =
2091 rdev->clock.default_mclk;
2092 rdev->pm.power_state[state_index].clock_info[j].sclk =
2093 rdev->clock.default_sclk;
2094 if (vddc)
2095 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2096 vddc;
2097 }
56278a8e
AD		 2098 }
2099 state_index++;
2100 }
2101 }
d7311171
AD		 2102 /* if multiple clock modes, mark the lowest as no display */
2103 for (i = 0; i < state_index; i++) {
2104 if (rdev->pm.power_state[i].num_clock_modes > 1)
2105 rdev->pm.power_state[i].clock_info[0].flags |=
2106 RADEON_PM_MODE_NO_DISPLAY;
2107 }
02b17cc0 2108 /* first mode is usually default */
a48b9b4e 2109 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 2110 rdev->pm.power_state[0].type =
2111 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2112 rdev->pm.default_power_state_index = 0;
02b17cc0
AD		 2113 rdev->pm.power_state[0].default_clock_mode =
2114 &rdev->pm.power_state[0].clock_info[0];
2115 }
56278a8e
AD		 2116 }
2117 } else {
56278a8e 2118 /* add the default mode */
0ec0e74f
AD		 2119 rdev->pm.power_state[state_index].type =
2120 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2121 rdev->pm.power_state[state_index].num_clock_modes = 1;
2122 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2123 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2124 rdev->pm.power_state[state_index].default_clock_mode =
2125 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 2126 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2127 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2128 rdev->pm.default_power_state_index = state_index;
2129 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 2130 state_index++;
2131 }
02b17cc0 2132
56278a8e 2133 rdev->pm.num_power_states = state_index;
9038dfdf 2134
a48b9b4e
AD		 2135 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2136 rdev->pm.current_clock_mode_index = 0;
4d60173f 2137 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2138}
2139
771fe6b9 2140void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2141{
771fe6b9
JG		 2142 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2143 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2144
2145 args.ucEnable = enable;
2146
2147 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2148}
2149
7433874e
RM		 2150uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2151{
2152 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2153 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2154
2155 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2156 return args.ulReturnEngineClock;
2157}
2158
2159uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2160{
2161 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2162 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2163
2164 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2165 return args.ulReturnMemoryClock;
2166}
2167
771fe6b9
JG		 2168void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2169 uint32_t eng_clock)
2170{
2171 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2172 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2173
2174 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2175
2176 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2177}
2178
2179void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2180 uint32_t mem_clock)
2181{
2182 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2183 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2184
2185 if (rdev->flags & RADEON_IS_IGP)
2186 return;
2187
2188 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2189
2190 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2191}
2192
7ac9aa5a
AD		 2193union set_voltage {
2194 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2195 struct _SET_VOLTAGE_PARAMETERS v1;
2196 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2197};
2198
2199void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2200{
2201 union set_voltage args;
2202 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2203 u8 frev, crev, volt_index = level;
2204
2205 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2206 return;
2207
2208 switch (crev) {
2209 case 1:
2210 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2211 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2212 args.v1.ucVoltageIndex = volt_index;
2213 break;
2214 case 2:
2215 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2216 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2217 args.v2.usVoltageLevel = cpu_to_le16(level);
2218 break;
2219 default:
2220 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2221 return;
2222 }
2223
2224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2225}
2226
2227
2228
771fe6b9
JG		 2229void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2230{
2231 struct radeon_device *rdev = dev->dev_private;
2232 uint32_t bios_2_scratch, bios_6_scratch;
2233
2234 if (rdev->family >= CHIP_R600) {
4ce001ab 2235 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2236 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2237 } else {
4ce001ab 2238 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2239 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2240 }
2241
2242 /* let the bios control the backlight */
2243 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2244
2245 /* tell the bios not to handle mode switching */
2246 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2247
2248 if (rdev->family >= CHIP_R600) {
2249 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2250 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2251 } else {
2252 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2253 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2254 }
2255
2256}
2257
f657c2a7
YZ		 2258void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2259{
2260 uint32_t scratch_reg;
2261 int i;
2262
2263 if (rdev->family >= CHIP_R600)
2264 scratch_reg = R600_BIOS_0_SCRATCH;
2265 else
2266 scratch_reg = RADEON_BIOS_0_SCRATCH;
2267
2268 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2269 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2270}
2271
2272void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2273{
2274 uint32_t scratch_reg;
2275 int i;
2276
2277 if (rdev->family >= CHIP_R600)
2278 scratch_reg = R600_BIOS_0_SCRATCH;
2279 else
2280 scratch_reg = RADEON_BIOS_0_SCRATCH;
2281
2282 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2283 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2284}
2285
771fe6b9
JG		 2286void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2287{
2288 struct drm_device *dev = encoder->dev;
2289 struct radeon_device *rdev = dev->dev_private;
2290 uint32_t bios_6_scratch;
2291
2292 if (rdev->family >= CHIP_R600)
2293 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2294 else
2295 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2296
2297 if (lock)
2298 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2299 else
2300 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2301
2302 if (rdev->family >= CHIP_R600)
2303 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2304 else
2305 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2306}
2307
2308/* at some point we may want to break this out into individual functions */
2309void
2310radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2311 struct drm_encoder *encoder,
2312 bool connected)
2313{
2314 struct drm_device *dev = connector->dev;
2315 struct radeon_device *rdev = dev->dev_private;
2316 struct radeon_connector *radeon_connector =
2317 to_radeon_connector(connector);
2318 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2319 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2320
2321 if (rdev->family >= CHIP_R600) {
2322 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2323 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2324 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2325 } else {
2326 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2327 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2328 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2329 }
2330
2331 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2332 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2333 if (connected) {
d9fdaafb 2334 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2335 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2336 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2337 } else {
d9fdaafb 2338 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2339 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2340 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2341 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2342 }
2343 }
2344 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2345 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2346 if (connected) {
d9fdaafb 2347 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2348 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2349 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2350 } else {
d9fdaafb 2351 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2352 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2353 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2354 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2355 }
2356 }
2357 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2358 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2359 if (connected) {
d9fdaafb 2360 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2361 bios_0_scratch |= ATOM_S0_LCD1;
2362 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2363 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2364 } else {
d9fdaafb 2365 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2366 bios_0_scratch &= ~ATOM_S0_LCD1;
2367 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2368 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2369 }
2370 }
2371 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2372 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2373 if (connected) {
d9fdaafb 2374 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2375 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2376 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2377 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2378 } else {
d9fdaafb 2379 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2380 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2381 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2382 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2383 }
2384 }
2385 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2386 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2387 if (connected) {
d9fdaafb 2388 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2389 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2390 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2391 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2392 } else {
d9fdaafb 2393 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2394 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2395 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2396 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2397 }
2398 }
2399 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2400 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2401 if (connected) {
d9fdaafb 2402 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2403 bios_0_scratch |= ATOM_S0_DFP1;
2404 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2405 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2406 } else {
d9fdaafb 2407 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2408 bios_0_scratch &= ~ATOM_S0_DFP1;
2409 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2410 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2411 }
2412 }
2413 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2414 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2415 if (connected) {
d9fdaafb 2416 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2417 bios_0_scratch |= ATOM_S0_DFP2;
2418 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2419 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2420 } else {
d9fdaafb 2421 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2422 bios_0_scratch &= ~ATOM_S0_DFP2;
2423 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2424 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2425 }
2426 }
2427 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2428 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2429 if (connected) {
d9fdaafb 2430 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2431 bios_0_scratch |= ATOM_S0_DFP3;
2432 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2433 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2434 } else {
d9fdaafb 2435 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2436 bios_0_scratch &= ~ATOM_S0_DFP3;
2437 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2438 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2439 }
2440 }
2441 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2442 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2443 if (connected) {
d9fdaafb 2444 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2445 bios_0_scratch |= ATOM_S0_DFP4;
2446 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2447 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2448 } else {
d9fdaafb 2449 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2450 bios_0_scratch &= ~ATOM_S0_DFP4;
2451 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2452 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2453 }
2454 }
2455 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2456 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2457 if (connected) {
d9fdaafb 2458 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2459 bios_0_scratch |= ATOM_S0_DFP5;
2460 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2461 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2462 } else {
d9fdaafb 2463 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2464 bios_0_scratch &= ~ATOM_S0_DFP5;
2465 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2466 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2467 }
2468 }
2469
2470 if (rdev->family >= CHIP_R600) {
2471 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2472 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2473 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2474 } else {
2475 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2476 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2477 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2478 }
2479}
2480
2481void
2482radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2483{
2484 struct drm_device *dev = encoder->dev;
2485 struct radeon_device *rdev = dev->dev_private;
2486 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2487 uint32_t bios_3_scratch;
2488
2489 if (rdev->family >= CHIP_R600)
2490 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2491 else
2492 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2493
2494 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2495 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2496 bios_3_scratch |= (crtc << 18);
2497 }
2498 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2499 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2500 bios_3_scratch |= (crtc << 24);
2501 }
2502 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2503 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2504 bios_3_scratch |= (crtc << 16);
2505 }
2506 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2507 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2508 bios_3_scratch |= (crtc << 20);
2509 }
2510 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2511 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2512 bios_3_scratch |= (crtc << 17);
2513 }
2514 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2515 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2516 bios_3_scratch |= (crtc << 19);
2517 }
2518 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2519 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2520 bios_3_scratch |= (crtc << 23);
2521 }
2522 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2523 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2524 bios_3_scratch |= (crtc << 25);
2525 }
2526
2527 if (rdev->family >= CHIP_R600)
2528 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2529 else
2530 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2531}
2532
2533void
2534radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2535{
2536 struct drm_device *dev = encoder->dev;
2537 struct radeon_device *rdev = dev->dev_private;
2538 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2539 uint32_t bios_2_scratch;
2540
2541 if (rdev->family >= CHIP_R600)
2542 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2543 else
2544 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2545
2546 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2547 if (on)
2548 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2549 else
2550 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2551 }
2552 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2553 if (on)
2554 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2555 else
2556 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2557 }
2558 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2559 if (on)
2560 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2561 else
2562 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2563 }
2564 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2565 if (on)
2566 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2567 else
2568 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2569 }
2570 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2571 if (on)
2572 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2573 else
2574 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2575 }
2576 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2577 if (on)
2578 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2579 else
2580 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2581 }
2582 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2583 if (on)
2584 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2585 else
2586 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2587 }
2588 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2589 if (on)
2590 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2591 else
2592 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2593 }
2594 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2595 if (on)
2596 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2597 else
2598 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2599 }
2600 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2601 if (on)
2602 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2603 else
2604 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2605 }
2606
2607 if (rdev->family >= CHIP_R600)
2608 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2609 else
2610 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2611}
Clone of davem's net-next-2.6 tree