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drm/radeon: Fix stack data leak
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 49 bool linkb, uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
88 if (gpio->sucI2cId.ucAccess == id) {
89 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
90 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
91 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
92 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
93 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
94 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
95 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
96 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
97 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
98 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
99 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
100 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
101 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
102 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
103 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
104 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
105
106 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
107 i2c.hw_capable = true;
108 else
109 i2c.hw_capable = false;
110
111 if (gpio->sucI2cId.ucAccess == 0xa0)
112 i2c.mm_i2c = true;
113 else
114 i2c.mm_i2c = false;
115
116 i2c.i2c_id = gpio->sucI2cId.ucAccess;
117
f376b94f
AD		 118 if (i2c.mask_clk_reg)
119 i2c.valid = true;
a084e6ee
AD		 120 break;
121 }
d3f420d1
AD		 122 }
123 }
771fe6b9
JG		 124
125 return i2c;
126}
127
f376b94f
AD		 128void radeon_atombios_i2c_init(struct radeon_device *rdev)
129{
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
136 int i, num_indices;
137 char stmp[32];
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
143
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
146
147 for (i = 0; i < num_indices; i++) {
148 gpio = &i2c_info->asGPIO_Info[i];
149 i2c.valid = false;
150 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
151 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
152 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
153 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
154 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
155 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
156 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
157 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
158 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
159 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
160 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
161 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
162 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
163 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
164 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
165 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
166
167 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
168 i2c.hw_capable = true;
169 else
170 i2c.hw_capable = false;
171
172 if (gpio->sucI2cId.ucAccess == 0xa0)
173 i2c.mm_i2c = true;
174 else
175 i2c.mm_i2c = false;
176
177 i2c.i2c_id = gpio->sucI2cId.ucAccess;
178
179 if (i2c.mask_clk_reg) {
180 i2c.valid = true;
181 sprintf(stmp, "0x%x", i2c.i2c_id);
182 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
183 }
184 }
185 }
186}
187
eed45b30
AD		 188static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
189 u8 id)
190{
191 struct atom_context *ctx = rdev->mode_info.atom_context;
192 struct radeon_gpio_rec gpio;
193 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
194 struct _ATOM_GPIO_PIN_LUT *gpio_info;
195 ATOM_GPIO_PIN_ASSIGNMENT *pin;
196 u16 data_offset, size;
197 int i, num_indices;
198
199 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
200 gpio.valid = false;
201
a084e6ee
AD		 202 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
203 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 204
a084e6ee
AD		 205 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
206 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 207
a084e6ee
AD		 208 for (i = 0; i < num_indices; i++) {
209 pin = &gpio_info->asGPIO_Pin[i];
210 if (id == pin->ucGPIO_ID) {
211 gpio.id = pin->ucGPIO_ID;
212 gpio.reg = pin->usGpioPin_AIndex * 4;
213 gpio.mask = (1 << pin->ucGpioPinBitShift);
214 gpio.valid = true;
215 break;
216 }
eed45b30
AD		 217 }
218 }
219
220 return gpio;
221}
222
223static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
224 struct radeon_gpio_rec *gpio)
225{
226 struct radeon_hpd hpd;
bcc1c2a1
AD		 227 u32 reg;
228
1d978dac
JD		 229 memset(&hpd, 0, sizeof(struct radeon_hpd));
230
bcc1c2a1
AD		 231 if (ASIC_IS_DCE4(rdev))
232 reg = EVERGREEN_DC_GPIO_HPD_A;
233 else
234 reg = AVIVO_DC_GPIO_HPD_A;
235
eed45b30 236 hpd.gpio = *gpio;
bcc1c2a1 237 if (gpio->reg == reg) {
eed45b30
AD		 238 switch(gpio->mask) {
239 case (1 << 0):
240 hpd.hpd = RADEON_HPD_1;
241 break;
242 case (1 << 8):
243 hpd.hpd = RADEON_HPD_2;
244 break;
245 case (1 << 16):
246 hpd.hpd = RADEON_HPD_3;
247 break;
248 case (1 << 24):
249 hpd.hpd = RADEON_HPD_4;
250 break;
251 case (1 << 26):
252 hpd.hpd = RADEON_HPD_5;
253 break;
254 case (1 << 28):
255 hpd.hpd = RADEON_HPD_6;
256 break;
257 default:
258 hpd.hpd = RADEON_HPD_NONE;
259 break;
260 }
261 } else
262 hpd.hpd = RADEON_HPD_NONE;
263 return hpd;
264}
265
771fe6b9
JG		 266static bool radeon_atom_apply_quirks(struct drm_device *dev,
267 uint32_t supported_device,
268 int *connector_type,
848577ee 269 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 270 uint16_t *line_mux,
271 struct radeon_hpd *hpd)
771fe6b9 272{
9ea2c4be 273 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 274
275 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
276 if ((dev->pdev->device == 0x791e) &&
277 (dev->pdev->subsystem_vendor == 0x1043) &&
278 (dev->pdev->subsystem_device == 0x826d)) {
279 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
280 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
281 *connector_type = DRM_MODE_CONNECTOR_DVID;
282 }
283
c86a9038
AD		 284 /* Asrock RS600 board lists the DVI port as HDMI */
285 if ((dev->pdev->device == 0x7941) &&
286 (dev->pdev->subsystem_vendor == 0x1849) &&
287 (dev->pdev->subsystem_device == 0x7941)) {
288 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
289 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
290 *connector_type = DRM_MODE_CONNECTOR_DVID;
291 }
292
771fe6b9
JG		 293 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
294 if ((dev->pdev->device == 0x7941) &&
295 (dev->pdev->subsystem_vendor == 0x147b) &&
296 (dev->pdev->subsystem_device == 0x2412)) {
297 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
298 return false;
299 }
300
301 /* Falcon NW laptop lists vga ddc line for LVDS */
302 if ((dev->pdev->device == 0x5653) &&
303 (dev->pdev->subsystem_vendor == 0x1462) &&
304 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 305 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 306 i2c_bus->valid = false;
848577ee
AD		 307 *line_mux = 53;
308 }
771fe6b9
JG		 309 }
310
4e3f9b78
AD		 311 /* HIS X1300 is DVI+VGA, not DVI+DVI */
312 if ((dev->pdev->device == 0x7146) &&
313 (dev->pdev->subsystem_vendor == 0x17af) &&
314 (dev->pdev->subsystem_device == 0x2058)) {
315 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
316 return false;
317 }
318
aa1a750e
DA		 319 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
320 if ((dev->pdev->device == 0x7142) &&
321 (dev->pdev->subsystem_vendor == 0x1458) &&
322 (dev->pdev->subsystem_device == 0x2134)) {
323 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
324 return false;
325 }
326
327
771fe6b9
JG		 328 /* Funky macbooks */
329 if ((dev->pdev->device == 0x71C5) &&
330 (dev->pdev->subsystem_vendor == 0x106b) &&
331 (dev->pdev->subsystem_device == 0x0080)) {
332 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
333 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
334 return false;
e1e8a5dd
AD		 335 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
336 *line_mux = 0x90;
771fe6b9
JG		 337 }
338
771fe6b9
JG		 339 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
340 if ((dev->pdev->device == 0x9598) &&
341 (dev->pdev->subsystem_vendor == 0x1043) &&
342 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 343 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 344 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 345 }
346 }
347
e153b70b
AD		 348 /* ASUS HD 3600 board lists the DVI port as HDMI */
349 if ((dev->pdev->device == 0x9598) &&
350 (dev->pdev->subsystem_vendor == 0x1043) &&
351 (dev->pdev->subsystem_device == 0x01e4)) {
352 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
353 *connector_type = DRM_MODE_CONNECTOR_DVII;
354 }
355 }
356
705af9c7
AD		 357 /* ASUS HD 3450 board lists the DVI port as HDMI */
358 if ((dev->pdev->device == 0x95C5) &&
359 (dev->pdev->subsystem_vendor == 0x1043) &&
360 (dev->pdev->subsystem_device == 0x01e2)) {
361 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 362 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 363 }
364 }
365
705af9c7
AD		 366 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
367 * HDMI + VGA reporting as HDMI
368 */
369 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
370 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
371 *connector_type = DRM_MODE_CONNECTOR_VGA;
372 *line_mux = 0;
373 }
374 }
375
9ea2c4be 376 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
3e5f8ff3
AD		 377 if ((dev->pdev->device == 0x95c4) &&
378 (dev->pdev->subsystem_vendor == 0x1025) &&
379 (dev->pdev->subsystem_device == 0x013c)) {
9ea2c4be
AD		 380 struct radeon_gpio_rec gpio;
381
3e5f8ff3 382 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be
AD		 383 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
384 gpio = radeon_lookup_gpio(rdev, 6);
385 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
3e5f8ff3 386 *connector_type = DRM_MODE_CONNECTOR_DVID;
9ea2c4be
AD		 387 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
388 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
389 gpio = radeon_lookup_gpio(rdev, 7);
390 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
391 }
3e5f8ff3
AD		 392 }
393
efa8450f
DA		 394 /* XFX Pine Group device rv730 reports no VGA DDC lines
395 * even though they are wired up to record 0x93
396 */
397 if ((dev->pdev->device == 0x9498) &&
398 (dev->pdev->subsystem_vendor == 0x1682) &&
399 (dev->pdev->subsystem_device == 0x2452)) {
400 struct radeon_device *rdev = dev->dev_private;
401 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
402 }
771fe6b9
JG		 403 return true;
404}
405
406const int supported_devices_connector_convert[] = {
407 DRM_MODE_CONNECTOR_Unknown,
408 DRM_MODE_CONNECTOR_VGA,
409 DRM_MODE_CONNECTOR_DVII,
410 DRM_MODE_CONNECTOR_DVID,
411 DRM_MODE_CONNECTOR_DVIA,
412 DRM_MODE_CONNECTOR_SVIDEO,
413 DRM_MODE_CONNECTOR_Composite,
414 DRM_MODE_CONNECTOR_LVDS,
415 DRM_MODE_CONNECTOR_Unknown,
416 DRM_MODE_CONNECTOR_Unknown,
417 DRM_MODE_CONNECTOR_HDMIA,
418 DRM_MODE_CONNECTOR_HDMIB,
419 DRM_MODE_CONNECTOR_Unknown,
420 DRM_MODE_CONNECTOR_Unknown,
421 DRM_MODE_CONNECTOR_9PinDIN,
422 DRM_MODE_CONNECTOR_DisplayPort
423};
424
b75fad06
AD		 425const uint16_t supported_devices_connector_object_id_convert[] = {
426 CONNECTOR_OBJECT_ID_NONE,
427 CONNECTOR_OBJECT_ID_VGA,
428 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
429 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
430 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
431 CONNECTOR_OBJECT_ID_COMPOSITE,
432 CONNECTOR_OBJECT_ID_SVIDEO,
433 CONNECTOR_OBJECT_ID_LVDS,
434 CONNECTOR_OBJECT_ID_9PIN_DIN,
435 CONNECTOR_OBJECT_ID_9PIN_DIN,
436 CONNECTOR_OBJECT_ID_DISPLAYPORT,
437 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
438 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
439 CONNECTOR_OBJECT_ID_SVIDEO
440};
441
771fe6b9
JG		 442const int object_connector_convert[] = {
443 DRM_MODE_CONNECTOR_Unknown,
444 DRM_MODE_CONNECTOR_DVII,
445 DRM_MODE_CONNECTOR_DVII,
446 DRM_MODE_CONNECTOR_DVID,
447 DRM_MODE_CONNECTOR_DVID,
448 DRM_MODE_CONNECTOR_VGA,
449 DRM_MODE_CONNECTOR_Composite,
450 DRM_MODE_CONNECTOR_SVIDEO,
451 DRM_MODE_CONNECTOR_Unknown,
705af9c7 452 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 453 DRM_MODE_CONNECTOR_9PinDIN,
454 DRM_MODE_CONNECTOR_Unknown,
455 DRM_MODE_CONNECTOR_HDMIA,
456 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 457 DRM_MODE_CONNECTOR_LVDS,
458 DRM_MODE_CONNECTOR_9PinDIN,
459 DRM_MODE_CONNECTOR_Unknown,
460 DRM_MODE_CONNECTOR_Unknown,
461 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 462 DRM_MODE_CONNECTOR_DisplayPort,
463 DRM_MODE_CONNECTOR_eDP,
464 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 465};
466
467bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
468{
469 struct radeon_device *rdev = dev->dev_private;
470 struct radeon_mode_info *mode_info = &rdev->mode_info;
471 struct atom_context *ctx = mode_info->atom_context;
472 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 473 u16 size, data_offset;
474 u8 frev, crev;
771fe6b9 475 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
26b5bc98 476 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 477 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
478 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 479 int i, j, k, path_size, device_support;
771fe6b9 480 int connector_type;
eed45b30 481 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 482 bool linkb;
483 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 484 struct radeon_router router;
eed45b30
AD		 485 struct radeon_gpio_rec gpio;
486 struct radeon_hpd hpd;
487
a084e6ee 488 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 489 return false;
490
491 if (crev < 2)
492 return false;
493
26b5bc98
AD		 494 router.valid = false;
495
771fe6b9
JG		 496 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
497 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
498 (ctx->bios + data_offset +
499 le16_to_cpu(obj_header->usDisplayPathTableOffset));
500 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
501 (ctx->bios + data_offset +
502 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
26b5bc98
AD		 503 router_obj = (ATOM_OBJECT_TABLE *)
504 (ctx->bios + data_offset +
505 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 506 device_support = le16_to_cpu(obj_header->usDeviceSupport);
507
508 path_size = 0;
509 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
510 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
511 ATOM_DISPLAY_OBJECT_PATH *path;
512 addr += path_size;
513 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
514 path_size += le16_to_cpu(path->usSize);
515 linkb = false;
771fe6b9
JG		 516 if (device_support & le16_to_cpu(path->usDeviceTag)) {
517 uint8_t con_obj_id, con_obj_num, con_obj_type;
518
519 con_obj_id =
520 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
521 >> OBJECT_ID_SHIFT;
522 con_obj_num =
523 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
524 >> ENUM_ID_SHIFT;
525 con_obj_type =
526 (le16_to_cpu(path->usConnObjectId) &
527 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
528
4bbd4973
DA		 529 /* TODO CV support */
530 if (le16_to_cpu(path->usDeviceTag) ==
531 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 532 continue;
533
ee59f2b4
AD		 534 /* IGP chips */
535 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 536 (con_obj_id ==
537 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
538 uint16_t igp_offset = 0;
539 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
540
541 index =
542 GetIndexIntoMasterTable(DATA,
543 IntegratedSystemInfo);
544
a084e6ee
AD		 545 if (atom_parse_data_header(ctx, index, &size, &frev,
546 &crev, &igp_offset)) {
547
548 if (crev >= 2) {
549 igp_obj =
550 (ATOM_INTEGRATED_SYSTEM_INFO_V2
551 *) (ctx->bios + igp_offset);
552
553 if (igp_obj) {
554 uint32_t slot_config, ct;
555
556 if (con_obj_num == 1)
557 slot_config =
558 igp_obj->
559 ulDDISlot1Config;
560 else
561 slot_config =
562 igp_obj->
563 ulDDISlot2Config;
564
565 ct = (slot_config >> 16) & 0xff;
566 connector_type =
567 object_connector_convert
568 [ct];
569 connector_object_id = ct;
570 igp_lane_info =
571 slot_config & 0xffff;
572 } else
573 continue;
771fe6b9
JG		 574 } else
575 continue;
a084e6ee
AD		 576 } else {
577 igp_lane_info = 0;
578 connector_type =
579 object_connector_convert[con_obj_id];
580 connector_object_id = con_obj_id;
581 }
771fe6b9
JG		 582 } else {
583 igp_lane_info = 0;
584 connector_type =
585 object_connector_convert[con_obj_id];
b75fad06 586 connector_object_id = con_obj_id;
771fe6b9
JG		 587 }
588
589 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
590 continue;
591
26b5bc98
AD		 592 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
593 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 594
26b5bc98 595 grph_obj_id =
771fe6b9
JG		 596 (le16_to_cpu(path->usGraphicObjIds[j]) &
597 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 598 grph_obj_num =
771fe6b9
JG		 599 (le16_to_cpu(path->usGraphicObjIds[j]) &
600 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 601 grph_obj_type =
771fe6b9
JG		 602 (le16_to_cpu(path->usGraphicObjIds[j]) &
603 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
604
26b5bc98
AD		 605 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
606 if (grph_obj_num == 2)
771fe6b9
JG		 607 linkb = true;
608 else
609 linkb = false;
610
611 radeon_add_atom_encoder(dev,
26b5bc98 612 grph_obj_id,
771fe6b9
JG		 613 le16_to_cpu
614 (path->
615 usDeviceTag));
616
26b5bc98
AD		 617 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
618 router.valid = false;
619 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
620 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
621 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
622 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
623 (ctx->bios + data_offset +
624 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
625 ATOM_I2C_RECORD *i2c_record;
626 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
627 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
628 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
629 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
630 (ctx->bios + data_offset +
631 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
632 int enum_id;
633
634 router.router_id = router_obj_id;
635 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
636 enum_id++) {
637 if (le16_to_cpu(path->usConnObjectId) ==
638 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
639 break;
640 }
641
642 while (record->ucRecordType > 0 &&
643 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
644 switch (record->ucRecordType) {
645 case ATOM_I2C_RECORD_TYPE:
646 i2c_record =
647 (ATOM_I2C_RECORD *)
648 record;
649 i2c_config =
650 (ATOM_I2C_ID_CONFIG_ACCESS *)
651 &i2c_record->sucI2cId;
652 router.i2c_info =
653 radeon_lookup_i2c_gpio(rdev,
654 i2c_config->
655 ucAccess);
656 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
657 break;
658 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
659 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
660 record;
661 router.valid = true;
662 router.mux_type = ddc_path->ucMuxType;
663 router.mux_control_pin = ddc_path->ucMuxControlPin;
664 router.mux_state = ddc_path->ucMuxState[enum_id];
665 break;
666 }
667 record = (ATOM_COMMON_RECORD_HEADER *)
668 ((char *)record + record->ucRecordSize);
669 }
670 }
671 }
771fe6b9
JG		 672 }
673 }
674
eed45b30 675 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 676 ddc_bus.valid = false;
677 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 678 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 679 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 680 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
681 if (le16_to_cpu(path->usConnObjectId) ==
682 le16_to_cpu(con_obj->asObjects[j].
683 usObjectID)) {
684 ATOM_COMMON_RECORD_HEADER
685 *record =
686 (ATOM_COMMON_RECORD_HEADER
687 *)
688 (ctx->bios + data_offset +
689 le16_to_cpu(con_obj->
690 asObjects[j].
691 usRecordOffset));
692 ATOM_I2C_RECORD *i2c_record;
eed45b30 693 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 694 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 695
771fe6b9
JG		 696 while (record->ucRecordType > 0
697 && record->
698 ucRecordType <=
699 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 700 switch (record->ucRecordType) {
771fe6b9
JG		 701 case ATOM_I2C_RECORD_TYPE:
702 i2c_record =
eed45b30
AD		 703 (ATOM_I2C_RECORD *)
704 record;
d3f420d1
AD		 705 i2c_config =
706 (ATOM_I2C_ID_CONFIG_ACCESS *)
707 &i2c_record->sucI2cId;
eed45b30 708 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 709 i2c_config->
710 ucAccess);
eed45b30
AD		 711 break;
712 case ATOM_HPD_INT_RECORD_TYPE:
713 hpd_record =
714 (ATOM_HPD_INT_RECORD *)
715 record;
716 gpio = radeon_lookup_gpio(rdev,
717 hpd_record->ucHPDIntGPIOID);
718 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
719 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 720 break;
721 }
722 record =
723 (ATOM_COMMON_RECORD_HEADER
724 *) ((char *)record
725 +
726 record->
727 ucRecordSize);
728 }
729 break;
730 }
731 }
eed45b30 732 }
771fe6b9 733
bcc1c2a1 734 /* needed for aux chan transactions */
8e36ed00 735 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 736
705af9c7
AD		 737 conn_id = le16_to_cpu(path->usConnObjectId);
738
739 if (!radeon_atom_apply_quirks
740 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 741 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 742 continue;
743
771fe6b9 744 radeon_add_atom_connector(dev,
705af9c7 745 conn_id,
771fe6b9
JG		 746 le16_to_cpu(path->
747 usDeviceTag),
748 connector_type, &ddc_bus,
b75fad06 749 linkb, igp_lane_info,
eed45b30 750 connector_object_id,
26b5bc98
AD		 751 &hpd,
752 &router);
771fe6b9
JG		 753
754 }
755 }
756
757 radeon_link_encoder_connector(dev);
758
759 return true;
760}
761
b75fad06
AD		 762static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
763 int connector_type,
764 uint16_t devices)
765{
766 struct radeon_device *rdev = dev->dev_private;
767
768 if (rdev->flags & RADEON_IS_IGP) {
769 return supported_devices_connector_object_id_convert
770 [connector_type];
771 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
772 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
773 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
774 struct radeon_mode_info *mode_info = &rdev->mode_info;
775 struct atom_context *ctx = mode_info->atom_context;
776 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
777 uint16_t size, data_offset;
778 uint8_t frev, crev;
779 ATOM_XTMDS_INFO *xtmds;
780
a084e6ee
AD		 781 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
782 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 783
a084e6ee
AD		 784 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
785 if (connector_type == DRM_MODE_CONNECTOR_DVII)
786 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
787 else
788 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
789 } else {
790 if (connector_type == DRM_MODE_CONNECTOR_DVII)
791 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
792 else
793 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
794 }
795 } else
796 return supported_devices_connector_object_id_convert
797 [connector_type];
b75fad06
AD		 798 } else {
799 return supported_devices_connector_object_id_convert
800 [connector_type];
801 }
802}
803
771fe6b9
JG		 804struct bios_connector {
805 bool valid;
705af9c7 806 uint16_t line_mux;
771fe6b9
JG		 807 uint16_t devices;
808 int connector_type;
809 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 810 struct radeon_hpd hpd;
771fe6b9
JG		 811};
812
813bool radeon_get_atom_connector_info_from_supported_devices_table(struct
814 drm_device
815 *dev)
816{
817 struct radeon_device *rdev = dev->dev_private;
818 struct radeon_mode_info *mode_info = &rdev->mode_info;
819 struct atom_context *ctx = mode_info->atom_context;
820 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
821 uint16_t size, data_offset;
822 uint8_t frev, crev;
823 uint16_t device_support;
824 uint8_t dac;
825 union atom_supported_devices *supported_devices;
eed45b30 826 int i, j, max_device;
f49d273d
PB		 827 struct bios_connector *bios_connectors;
828 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 829 struct radeon_router router;
830
831 router.valid = false;
771fe6b9 832
f49d273d
PB		 833 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
834 if (!bios_connectors)
835 return false;
836
837 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
838 &data_offset)) {
839 kfree(bios_connectors);
a084e6ee 840 return false;
f49d273d 841 }
771fe6b9
JG		 842
843 supported_devices =
844 (union atom_supported_devices *)(ctx->bios + data_offset);
845
846 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
847
eed45b30
AD		 848 if (frev > 1)
849 max_device = ATOM_MAX_SUPPORTED_DEVICE;
850 else
851 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
852
853 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 854 ATOM_CONNECTOR_INFO_I2C ci =
855 supported_devices->info.asConnInfo[i];
856
857 bios_connectors[i].valid = false;
858
859 if (!(device_support & (1 << i))) {
860 continue;
861 }
862
863 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 864 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 865 continue;
866 }
867
771fe6b9
JG		 868 bios_connectors[i].connector_type =
869 supported_devices_connector_convert[ci.sucConnectorInfo.
870 sbfAccess.
871 bfConnectorType];
872
873 if (bios_connectors[i].connector_type ==
874 DRM_MODE_CONNECTOR_Unknown)
875 continue;
876
877 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
878
d3f420d1
AD		 879 bios_connectors[i].line_mux =
880 ci.sucI2cId.ucAccess;
771fe6b9
JG		 881
882 /* give tv unique connector ids */
883 if (i == ATOM_DEVICE_TV1_INDEX) {
884 bios_connectors[i].ddc_bus.valid = false;
885 bios_connectors[i].line_mux = 50;
886 } else if (i == ATOM_DEVICE_TV2_INDEX) {
887 bios_connectors[i].ddc_bus.valid = false;
888 bios_connectors[i].line_mux = 51;
889 } else if (i == ATOM_DEVICE_CV_INDEX) {
890 bios_connectors[i].ddc_bus.valid = false;
891 bios_connectors[i].line_mux = 52;
892 } else
893 bios_connectors[i].ddc_bus =
eed45b30
AD		 894 radeon_lookup_i2c_gpio(rdev,
895 bios_connectors[i].line_mux);
896
897 if ((crev > 1) && (frev > 1)) {
898 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
899 switch (isb) {
900 case 0x4:
901 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
902 break;
903 case 0xa:
904 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
905 break;
906 default:
907 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
908 break;
909 }
910 } else {
911 if (i == ATOM_DEVICE_DFP1_INDEX)
912 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
913 else if (i == ATOM_DEVICE_DFP2_INDEX)
914 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
915 else
916 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
917 }
771fe6b9
JG		 918
919 /* Always set the connector type to VGA for CRT1/CRT2. if they are
920 * shared with a DVI port, we'll pick up the DVI connector when we
921 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
922 */
923 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
924 bios_connectors[i].connector_type =
925 DRM_MODE_CONNECTOR_VGA;
926
927 if (!radeon_atom_apply_quirks
928 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 929 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
930 &bios_connectors[i].hpd))
771fe6b9
JG		 931 continue;
932
933 bios_connectors[i].valid = true;
934 bios_connectors[i].devices = (1 << i);
935
936 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
937 radeon_add_atom_encoder(dev,
938 radeon_get_encoder_id(dev,
939 (1 << i),
940 dac),
941 (1 << i));
942 else
943 radeon_add_legacy_encoder(dev,
944 radeon_get_encoder_id(dev,
f56cd64f 945 (1 << i),
771fe6b9
JG		 946 dac),
947 (1 << i));
948 }
949
950 /* combine shared connectors */
eed45b30 951 for (i = 0; i < max_device; i++) {
771fe6b9 952 if (bios_connectors[i].valid) {
eed45b30 953 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 954 if (bios_connectors[j].valid && (i != j)) {
955 if (bios_connectors[i].line_mux ==
956 bios_connectors[j].line_mux) {
f56cd64f
AD		 957 /* make sure not to combine LVDS */
958 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
959 bios_connectors[i].line_mux = 53;
960 bios_connectors[i].ddc_bus.valid = false;
961 continue;
962 }
963 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
964 bios_connectors[j].line_mux = 53;
965 bios_connectors[j].ddc_bus.valid = false;
966 continue;
967 }
968 /* combine analog and digital for DVI-I */
969 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
970 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
971 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
972 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
973 bios_connectors[i].devices |=
974 bios_connectors[j].devices;
975 bios_connectors[i].connector_type =
976 DRM_MODE_CONNECTOR_DVII;
977 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 978 bios_connectors[i].hpd =
979 bios_connectors[j].hpd;
f56cd64f 980 bios_connectors[j].valid = false;
771fe6b9
JG		 981 }
982 }
983 }
984 }
985 }
986 }
987
988 /* add the connectors */
eed45b30 989 for (i = 0; i < max_device; i++) {
b75fad06
AD		 990 if (bios_connectors[i].valid) {
991 uint16_t connector_object_id =
992 atombios_get_connector_object_id(dev,
993 bios_connectors[i].connector_type,
994 bios_connectors[i].devices);
771fe6b9
JG		 995 radeon_add_atom_connector(dev,
996 bios_connectors[i].line_mux,
997 bios_connectors[i].devices,
998 bios_connectors[i].
999 connector_type,
1000 &bios_connectors[i].ddc_bus,
b75fad06 1001 false, 0,
eed45b30 1002 connector_object_id,
26b5bc98
AD		 1003 &bios_connectors[i].hpd,
1004 &router);
b75fad06 1005 }
771fe6b9
JG		 1006 }
1007
1008 radeon_link_encoder_connector(dev);
1009
f49d273d 1010 kfree(bios_connectors);
771fe6b9
JG		 1011 return true;
1012}
1013
1014union firmware_info {
1015 ATOM_FIRMWARE_INFO info;
1016 ATOM_FIRMWARE_INFO_V1_2 info_12;
1017 ATOM_FIRMWARE_INFO_V1_3 info_13;
1018 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1019 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 1020};
1021
1022bool radeon_atom_get_clock_info(struct drm_device *dev)
1023{
1024 struct radeon_device *rdev = dev->dev_private;
1025 struct radeon_mode_info *mode_info = &rdev->mode_info;
1026 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1027 union firmware_info *firmware_info;
1028 uint8_t frev, crev;
1029 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1030 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1031 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1032 struct radeon_pll *spll = &rdev->clock.spll;
1033 struct radeon_pll *mpll = &rdev->clock.mpll;
1034 uint16_t data_offset;
1035
a084e6ee
AD		 1036 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1037 &frev, &crev, &data_offset)) {
1038 firmware_info =
1039 (union firmware_info *)(mode_info->atom_context->bios +
1040 data_offset);
771fe6b9
JG		 1041 /* pixel clocks */
1042 p1pll->reference_freq =
1043 le16_to_cpu(firmware_info->info.usReferenceClock);
1044 p1pll->reference_div = 0;
1045
bc293e58
MF		 1046 if (crev < 2)
1047 p1pll->pll_out_min =
1048 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1049 else
1050 p1pll->pll_out_min =
1051 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1052 p1pll->pll_out_max =
1053 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1054
86cb2bbf
AD		 1055 if (crev >= 4) {
1056 p1pll->lcd_pll_out_min =
1057 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1058 if (p1pll->lcd_pll_out_min == 0)
1059 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1060 p1pll->lcd_pll_out_max =
1061 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1062 if (p1pll->lcd_pll_out_max == 0)
1063 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1064 } else {
1065 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1066 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1067 }
1068
771fe6b9
JG		 1069 if (p1pll->pll_out_min == 0) {
1070 if (ASIC_IS_AVIVO(rdev))
1071 p1pll->pll_out_min = 64800;
1072 else
1073 p1pll->pll_out_min = 20000;
8f552a66
AD		 1074 } else if (p1pll->pll_out_min > 64800) {
1075 /* Limiting the pll output range is a good thing generally as
1076 * it limits the number of possible pll combinations for a given
1077 * frequency presumably to the ones that work best on each card.
1078 * However, certain duallink DVI monitors seem to like
1079 * pll combinations that would be limited by this at least on
1080 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1081 * family.
1082 */
b27b6375
AD		 1083 if (!radeon_new_pll)
1084 p1pll->pll_out_min = 64800;
771fe6b9
JG		 1085 }
1086
1087 p1pll->pll_in_min =
1088 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1089 p1pll->pll_in_max =
1090 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1091
1092 *p2pll = *p1pll;
1093
1094 /* system clock */
1095 spll->reference_freq =
1096 le16_to_cpu(firmware_info->info.usReferenceClock);
1097 spll->reference_div = 0;
1098
1099 spll->pll_out_min =
1100 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1101 spll->pll_out_max =
1102 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1103
1104 /* ??? */
1105 if (spll->pll_out_min == 0) {
1106 if (ASIC_IS_AVIVO(rdev))
1107 spll->pll_out_min = 64800;
1108 else
1109 spll->pll_out_min = 20000;
1110 }
1111
1112 spll->pll_in_min =
1113 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1114 spll->pll_in_max =
1115 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1116
1117 /* memory clock */
1118 mpll->reference_freq =
1119 le16_to_cpu(firmware_info->info.usReferenceClock);
1120 mpll->reference_div = 0;
1121
1122 mpll->pll_out_min =
1123 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1124 mpll->pll_out_max =
1125 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1126
1127 /* ??? */
1128 if (mpll->pll_out_min == 0) {
1129 if (ASIC_IS_AVIVO(rdev))
1130 mpll->pll_out_min = 64800;
1131 else
1132 mpll->pll_out_min = 20000;
1133 }
1134
1135 mpll->pll_in_min =
1136 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1137 mpll->pll_in_max =
1138 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1139
1140 rdev->clock.default_sclk =
1141 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1142 rdev->clock.default_mclk =
1143 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1144
bcc1c2a1
AD		 1145 if (ASIC_IS_DCE4(rdev)) {
1146 rdev->clock.default_dispclk =
1147 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1148 if (rdev->clock.default_dispclk == 0)
1149 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1150 rdev->clock.dp_extclk =
1151 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1152 }
1153 *dcpll = *p1pll;
1154
771fe6b9
JG		 1155 return true;
1156 }
bcc1c2a1 1157
771fe6b9
JG		 1158 return false;
1159}
1160
06b6476d
AD		 1161union igp_info {
1162 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1163 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1164};
1165
1166bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1167{
1168 struct radeon_mode_info *mode_info = &rdev->mode_info;
1169 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1170 union igp_info *igp_info;
1171 u8 frev, crev;
1172 u16 data_offset;
1173
4c70b2ea
AD		 1174 /* sideport is AMD only */
1175 if (rdev->family == CHIP_RS600)
1176 return false;
1177
a084e6ee
AD		 1178 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1179 &frev, &crev, &data_offset)) {
1180 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1181 data_offset);
06b6476d
AD		 1182 switch (crev) {
1183 case 1:
4c70b2ea
AD		 1184 if (igp_info->info.ulBootUpMemoryClock)
1185 return true;
06b6476d
AD		 1186 break;
1187 case 2:
1188 if (igp_info->info_2.ucMemoryType & 0x0f)
1189 return true;
1190 break;
1191 default:
1192 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1193 break;
1194 }
1195 }
1196 return false;
1197}
1198
445282db
DA		 1199bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1200 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1201{
1202 struct drm_device *dev = encoder->base.dev;
1203 struct radeon_device *rdev = dev->dev_private;
1204 struct radeon_mode_info *mode_info = &rdev->mode_info;
1205 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1206 uint16_t data_offset;
1207 struct _ATOM_TMDS_INFO *tmds_info;
1208 uint8_t frev, crev;
1209 uint16_t maxfreq;
1210 int i;
771fe6b9 1211
a084e6ee
AD		 1212 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1213 &frev, &crev, &data_offset)) {
1214 tmds_info =
1215 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1216 data_offset);
771fe6b9 1217
771fe6b9
JG		 1218 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1219 for (i = 0; i < 4; i++) {
1220 tmds->tmds_pll[i].freq =
1221 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1222 tmds->tmds_pll[i].value =
1223 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1224 tmds->tmds_pll[i].value |=
1225 (tmds_info->asMiscInfo[i].
1226 ucPLL_VCO_Gain & 0x3f) << 6;
1227 tmds->tmds_pll[i].value |=
1228 (tmds_info->asMiscInfo[i].
1229 ucPLL_DutyCycle & 0xf) << 12;
1230 tmds->tmds_pll[i].value |=
1231 (tmds_info->asMiscInfo[i].
1232 ucPLL_VoltageSwing & 0xf) << 16;
1233
d9fdaafb 1234 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1235 tmds->tmds_pll[i].freq,
1236 tmds->tmds_pll[i].value);
1237
1238 if (maxfreq == tmds->tmds_pll[i].freq) {
1239 tmds->tmds_pll[i].freq = 0xffffffff;
1240 break;
1241 }
1242 }
445282db 1243 return true;
771fe6b9 1244 }
445282db 1245 return false;
771fe6b9
JG		 1246}
1247
ebbe1cb9
AD		 1248static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1249 radeon_encoder
1250 *encoder,
1251 int id)
1252{
1253 struct drm_device *dev = encoder->base.dev;
1254 struct radeon_device *rdev = dev->dev_private;
1255 struct radeon_mode_info *mode_info = &rdev->mode_info;
1256 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1257 uint16_t data_offset;
1258 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1259 uint8_t frev, crev;
1260 struct radeon_atom_ss *ss = NULL;
279b215e 1261 int i;
ebbe1cb9
AD		 1262
1263 if (id > ATOM_MAX_SS_ENTRY)
1264 return NULL;
1265
a084e6ee
AD		 1266 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1267 &frev, &crev, &data_offset)) {
1268 ss_info =
1269 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1270
ebbe1cb9
AD		 1271 ss =
1272 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1273
1274 if (!ss)
1275 return NULL;
1276
279b215e
AD		 1277 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1278 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1279 ss->percentage =
1280 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1281 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1282 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1283 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1284 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1285 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1d3d51b6 1286 break;
279b215e
AD		 1287 }
1288 }
ebbe1cb9
AD		 1289 }
1290 return ss;
1291}
1292
771fe6b9
JG		 1293union lvds_info {
1294 struct _ATOM_LVDS_INFO info;
1295 struct _ATOM_LVDS_INFO_V12 info_12;
1296};
1297
1298struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1299 radeon_encoder
1300 *encoder)
1301{
1302 struct drm_device *dev = encoder->base.dev;
1303 struct radeon_device *rdev = dev->dev_private;
1304 struct radeon_mode_info *mode_info = &rdev->mode_info;
1305 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1306 uint16_t data_offset, misc;
771fe6b9
JG		 1307 union lvds_info *lvds_info;
1308 uint8_t frev, crev;
1309 struct radeon_encoder_atom_dig *lvds = NULL;
1310
a084e6ee
AD		 1311 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1312 &frev, &crev, &data_offset)) {
1313 lvds_info =
1314 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1315 lvds =
1316 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1317
1318 if (!lvds)
1319 return NULL;
1320
de2103e4 1321 lvds->native_mode.clock =
771fe6b9 1322 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1323 lvds->native_mode.hdisplay =
771fe6b9 1324 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1325 lvds->native_mode.vdisplay =
771fe6b9 1326 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1327 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1328 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1329 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1330 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1331 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1332 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1333 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1334 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1335 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1336 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1337 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1338 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1339 lvds->panel_pwr_delay =
1340 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1341 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1342
1343 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1344 if (misc & ATOM_VSYNC_POLARITY)
1345 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1346 if (misc & ATOM_HSYNC_POLARITY)
1347 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1348 if (misc & ATOM_COMPOSITESYNC)
1349 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1350 if (misc & ATOM_INTERLACE)
1351 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1352 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1353 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1354
de2103e4
AD		 1355 /* set crtc values */
1356 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1357
ebbe1cb9
AD		 1358 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1359
7c27f87d 1360 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 1361 if (radeon_new_pll == 0)
1362 lvds->pll_algo = PLL_ALGO_LEGACY;
1363 else
1364 lvds->pll_algo = PLL_ALGO_NEW;
1365 } else {
1366 if (radeon_new_pll == 1)
1367 lvds->pll_algo = PLL_ALGO_NEW;
7c27f87d
AD		 1368 else
1369 lvds->pll_algo = PLL_ALGO_LEGACY;
383be5d1 1370 }
7c27f87d 1371
771fe6b9
JG		 1372 encoder->native_mode = lvds->native_mode;
1373 }
1374 return lvds;
1375}
1376
6fe7ac3f
AD		 1377struct radeon_encoder_primary_dac *
1378radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1379{
1380 struct drm_device *dev = encoder->base.dev;
1381 struct radeon_device *rdev = dev->dev_private;
1382 struct radeon_mode_info *mode_info = &rdev->mode_info;
1383 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1384 uint16_t data_offset;
1385 struct _COMPASSIONATE_DATA *dac_info;
1386 uint8_t frev, crev;
1387 uint8_t bg, dac;
6fe7ac3f
AD		 1388 struct radeon_encoder_primary_dac *p_dac = NULL;
1389
a084e6ee
AD		 1390 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1391 &frev, &crev, &data_offset)) {
1392 dac_info = (struct _COMPASSIONATE_DATA *)
1393 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1394
6fe7ac3f
AD		 1395 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1396
1397 if (!p_dac)
1398 return NULL;
1399
1400 bg = dac_info->ucDAC1_BG_Adjustment;
1401 dac = dac_info->ucDAC1_DAC_Adjustment;
1402 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1403
1404 }
1405 return p_dac;
1406}
1407
4ce001ab 1408bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1409 struct drm_display_mode *mode)
4ce001ab
DA		 1410{
1411 struct radeon_mode_info *mode_info = &rdev->mode_info;
1412 ATOM_ANALOG_TV_INFO *tv_info;
1413 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1414 ATOM_DTD_FORMAT *dtd_timings;
1415 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1416 u8 frev, crev;
5a9bcacc 1417 u16 data_offset, misc;
4ce001ab 1418
a084e6ee
AD		 1419 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1420 &frev, &crev, &data_offset))
1421 return false;
4ce001ab
DA		 1422
1423 switch (crev) {
1424 case 1:
1425 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1426 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1427 return false;
1428
5a9bcacc
AD		 1429 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1430 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1431 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1432 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1433 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1434
1435 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1436 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1437 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1438 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1439 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1440
1441 mode->flags = 0;
1442 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1443 if (misc & ATOM_VSYNC_POLARITY)
1444 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1445 if (misc & ATOM_HSYNC_POLARITY)
1446 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1447 if (misc & ATOM_COMPOSITESYNC)
1448 mode->flags |= DRM_MODE_FLAG_CSYNC;
1449 if (misc & ATOM_INTERLACE)
1450 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1451 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1452 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1453
1454 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1455
1456 if (index == 1) {
1457 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1458 mode->crtc_htotal -= 1;
1459 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1460 }
1461 break;
1462 case 2:
1463 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1464 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1465 return false;
1466
1467 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1468 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1469 le16_to_cpu(dtd_timings->usHBlanking_Time);
1470 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1471 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1472 le16_to_cpu(dtd_timings->usHSyncOffset);
1473 mode->crtc_hsync_end = mode->crtc_hsync_start +
1474 le16_to_cpu(dtd_timings->usHSyncWidth);
1475
1476 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1477 le16_to_cpu(dtd_timings->usVBlanking_Time);
1478 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1479 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1480 le16_to_cpu(dtd_timings->usVSyncOffset);
1481 mode->crtc_vsync_end = mode->crtc_vsync_start +
1482 le16_to_cpu(dtd_timings->usVSyncWidth);
1483
1484 mode->flags = 0;
1485 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1486 if (misc & ATOM_VSYNC_POLARITY)
1487 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1488 if (misc & ATOM_HSYNC_POLARITY)
1489 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1490 if (misc & ATOM_COMPOSITESYNC)
1491 mode->flags |= DRM_MODE_FLAG_CSYNC;
1492 if (misc & ATOM_INTERLACE)
1493 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1494 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1495 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1496
1497 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1498 break;
1499 }
1500 return true;
1501}
1502
d79766fa
AD		 1503enum radeon_tv_std
1504radeon_atombios_get_tv_info(struct radeon_device *rdev)
1505{
1506 struct radeon_mode_info *mode_info = &rdev->mode_info;
1507 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1508 uint16_t data_offset;
1509 uint8_t frev, crev;
1510 struct _ATOM_ANALOG_TV_INFO *tv_info;
1511 enum radeon_tv_std tv_std = TV_STD_NTSC;
1512
a084e6ee
AD		 1513 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1514 &frev, &crev, &data_offset)) {
d79766fa 1515
a084e6ee
AD		 1516 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1517 (mode_info->atom_context->bios + data_offset);
d79766fa 1518
a084e6ee
AD		 1519 switch (tv_info->ucTV_BootUpDefaultStandard) {
1520 case ATOM_TV_NTSC:
1521 tv_std = TV_STD_NTSC;
1522 DRM_INFO("Default TV standard: NTSC\n");
1523 break;
1524 case ATOM_TV_NTSCJ:
1525 tv_std = TV_STD_NTSC_J;
1526 DRM_INFO("Default TV standard: NTSC-J\n");
1527 break;
1528 case ATOM_TV_PAL:
1529 tv_std = TV_STD_PAL;
1530 DRM_INFO("Default TV standard: PAL\n");
1531 break;
1532 case ATOM_TV_PALM:
1533 tv_std = TV_STD_PAL_M;
1534 DRM_INFO("Default TV standard: PAL-M\n");
1535 break;
1536 case ATOM_TV_PALN:
1537 tv_std = TV_STD_PAL_N;
1538 DRM_INFO("Default TV standard: PAL-N\n");
1539 break;
1540 case ATOM_TV_PALCN:
1541 tv_std = TV_STD_PAL_CN;
1542 DRM_INFO("Default TV standard: PAL-CN\n");
1543 break;
1544 case ATOM_TV_PAL60:
1545 tv_std = TV_STD_PAL_60;
1546 DRM_INFO("Default TV standard: PAL-60\n");
1547 break;
1548 case ATOM_TV_SECAM:
1549 tv_std = TV_STD_SECAM;
1550 DRM_INFO("Default TV standard: SECAM\n");
1551 break;
1552 default:
1553 tv_std = TV_STD_NTSC;
1554 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1555 break;
1556 }
d79766fa
AD		 1557 }
1558 return tv_std;
1559}
1560
6fe7ac3f
AD		 1561struct radeon_encoder_tv_dac *
1562radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1563{
1564 struct drm_device *dev = encoder->base.dev;
1565 struct radeon_device *rdev = dev->dev_private;
1566 struct radeon_mode_info *mode_info = &rdev->mode_info;
1567 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1568 uint16_t data_offset;
1569 struct _COMPASSIONATE_DATA *dac_info;
1570 uint8_t frev, crev;
1571 uint8_t bg, dac;
6fe7ac3f
AD		 1572 struct radeon_encoder_tv_dac *tv_dac = NULL;
1573
a084e6ee
AD		 1574 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1575 &frev, &crev, &data_offset)) {
6fe7ac3f 1576
a084e6ee
AD		 1577 dac_info = (struct _COMPASSIONATE_DATA *)
1578 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1579
6fe7ac3f
AD		 1580 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1581
1582 if (!tv_dac)
1583 return NULL;
1584
1585 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1586 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1587 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1588
1589 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1590 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1591 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1592
1593 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1594 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1595 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1596
d79766fa 1597 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1598 }
1599 return tv_dac;
1600}
1601
29fb52ca
AD		 1602static const char *thermal_controller_names[] = {
1603 "NONE",
678e7dfa
AD		 1604 "lm63",
1605 "adm1032",
1606 "adm1030",
1607 "max6649",
1608 "lm64",
1609 "f75375",
1610 "asc7xxx",
29fb52ca
AD		 1611};
1612
1613static const char *pp_lib_thermal_controller_names[] = {
1614 "NONE",
678e7dfa
AD		 1615 "lm63",
1616 "adm1032",
1617 "adm1030",
1618 "max6649",
1619 "lm64",
1620 "f75375",
29fb52ca
AD		 1621 "RV6xx",
1622 "RV770",
678e7dfa 1623 "adt7473",
49f65982
AD		 1624 "External GPIO",
1625 "Evergreen",
678e7dfa 1626 "adt7473 with internal",
49f65982 1627
29fb52ca
AD		 1628};
1629
56278a8e
AD		 1630union power_info {
1631 struct _ATOM_POWERPLAY_INFO info;
1632 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1633 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1634 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1635};
1636
1637void radeon_atombios_get_power_modes(struct radeon_device *rdev)
771fe6b9 1638{
56278a8e
AD		 1639 struct radeon_mode_info *mode_info = &rdev->mode_info;
1640 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1641 u16 data_offset;
1642 u8 frev, crev;
1643 u32 misc, misc2 = 0, sclk, mclk;
1644 union power_info *power_info;
1645 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1646 struct _ATOM_PPLIB_STATE *power_state;
1647 int num_modes = 0, i, j;
1648 int state_index = 0, mode_index = 0;
29fb52ca 1649 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1650
a48b9b4e 1651 rdev->pm.default_power_state_index = -1;
56278a8e 1652
a084e6ee
AD		 1653 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1654 &frev, &crev, &data_offset)) {
1655 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
56278a8e 1656 if (frev < 4) {
29fb52ca
AD		 1657 /* add the i2c bus for thermal/fan chip */
1658 if (power_info->info.ucOverdriveThermalController > 0) {
1659 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1660 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1661 power_info->info.ucOverdriveControllerAddress >> 1);
1662 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
f376b94f 1663 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1664 if (rdev->pm.i2c_bus) {
1665 struct i2c_board_info info = { };
1666 const char *name = thermal_controller_names[power_info->info.
1667 ucOverdriveThermalController];
1668 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1669 strlcpy(info.type, name, sizeof(info.type));
1670 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1671 }
29fb52ca 1672 }
56278a8e
AD		 1673 num_modes = power_info->info.ucNumOfPowerModeEntries;
1674 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1675 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
02b17cc0 1676 /* last mode is usually default, array is low to high */
56278a8e
AD		 1677 for (i = 0; i < num_modes; i++) {
1678 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1679 switch (frev) {
1680 case 1:
1681 rdev->pm.power_state[state_index].num_clock_modes = 1;
1682 rdev->pm.power_state[state_index].clock_info[0].mclk =
1683 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1684 rdev->pm.power_state[state_index].clock_info[0].sclk =
1685 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1686 /* skip invalid modes */
1687 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1688 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1689 continue;
79daedc9 1690 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1691 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1692 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
84d88f4c
AD		 1693 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1694 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1695 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1696 VOLTAGE_GPIO;
1697 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1698 radeon_lookup_gpio(rdev,
1699 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1700 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1701 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1702 true;
1703 else
1704 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1705 false;
1706 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1707 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1708 VOLTAGE_VDDC;
1709 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1710 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1711 }
d7311171 1712 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9 1713 rdev->pm.power_state[state_index].misc = misc;
0ec0e74f
AD		 1714 /* order matters! */
1715 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1716 rdev->pm.power_state[state_index].type =
1717 POWER_STATE_TYPE_POWERSAVE;
1718 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1719 rdev->pm.power_state[state_index].type =
1720 POWER_STATE_TYPE_BATTERY;
1721 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1722 rdev->pm.power_state[state_index].type =
1723 POWER_STATE_TYPE_BATTERY;
1724 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1725 rdev->pm.power_state[state_index].type =
1726 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1727 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1728 rdev->pm.power_state[state_index].type =
1729 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1730 rdev->pm.power_state[state_index].flags &=
d7311171 1731 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1732 }
56278a8e 1733 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1734 rdev->pm.power_state[state_index].type =
1735 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1736 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1737 rdev->pm.power_state[state_index].default_clock_mode =
1738 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1739 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1740 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1741 } else if (state_index == 0) {
1742 rdev->pm.power_state[state_index].clock_info[0].flags |=
1743 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1744 }
1745 state_index++;
1746 break;
1747 case 2:
1748 rdev->pm.power_state[state_index].num_clock_modes = 1;
1749 rdev->pm.power_state[state_index].clock_info[0].mclk =
1750 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1751 rdev->pm.power_state[state_index].clock_info[0].sclk =
1752 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1753 /* skip invalid modes */
1754 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1755 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1756 continue;
79daedc9 1757 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1758 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1759 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1760 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1761 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1762 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1763 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1764 VOLTAGE_GPIO;
1765 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1766 radeon_lookup_gpio(rdev,
1767 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1768 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1769 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1770 true;
1771 else
1772 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1773 false;
1774 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1775 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1776 VOLTAGE_VDDC;
1777 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1778 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1779 }
d7311171 1780 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1781 rdev->pm.power_state[state_index].misc = misc;
1782 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1783 /* order matters! */
1784 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1785 rdev->pm.power_state[state_index].type =
1786 POWER_STATE_TYPE_POWERSAVE;
1787 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1788 rdev->pm.power_state[state_index].type =
1789 POWER_STATE_TYPE_BATTERY;
1790 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1791 rdev->pm.power_state[state_index].type =
1792 POWER_STATE_TYPE_BATTERY;
1793 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1794 rdev->pm.power_state[state_index].type =
1795 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1796 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1797 rdev->pm.power_state[state_index].type =
1798 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1799 rdev->pm.power_state[state_index].flags &=
d7311171 1800 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1801 }
0ec0e74f
AD		 1802 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1803 rdev->pm.power_state[state_index].type =
1804 POWER_STATE_TYPE_BALANCED;
a48b9b4e
AD		 1805 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1806 rdev->pm.power_state[state_index].flags &=
d7311171 1807 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1808 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1809 rdev->pm.power_state[state_index].type =
1810 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1811 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1812 rdev->pm.power_state[state_index].default_clock_mode =
1813 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1814 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1815 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1816 } else if (state_index == 0) {
1817 rdev->pm.power_state[state_index].clock_info[0].flags |=
1818 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1819 }
1820 state_index++;
1821 break;
1822 case 3:
1823 rdev->pm.power_state[state_index].num_clock_modes = 1;
1824 rdev->pm.power_state[state_index].clock_info[0].mclk =
1825 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1826 rdev->pm.power_state[state_index].clock_info[0].sclk =
1827 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1828 /* skip invalid modes */
1829 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1830 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1831 continue;
79daedc9 1832 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1833 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1834 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1835 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1836 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1837 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1838 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1839 VOLTAGE_GPIO;
1840 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1841 radeon_lookup_gpio(rdev,
1842 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1843 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1844 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1845 true;
1846 else
1847 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1848 false;
1849 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1850 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1851 VOLTAGE_VDDC;
1852 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1853 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1854 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1855 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1856 true;
1857 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1858 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1859 }
1860 }
d7311171 1861 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1862 rdev->pm.power_state[state_index].misc = misc;
1863 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1864 /* order matters! */
1865 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1866 rdev->pm.power_state[state_index].type =
1867 POWER_STATE_TYPE_POWERSAVE;
1868 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1869 rdev->pm.power_state[state_index].type =
1870 POWER_STATE_TYPE_BATTERY;
1871 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1872 rdev->pm.power_state[state_index].type =
1873 POWER_STATE_TYPE_BATTERY;
1874 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1875 rdev->pm.power_state[state_index].type =
1876 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1877 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1878 rdev->pm.power_state[state_index].type =
1879 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1880 rdev->pm.power_state[state_index].flags &=
d7311171 1881 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1882 }
0ec0e74f
AD		 1883 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1884 rdev->pm.power_state[state_index].type =
1885 POWER_STATE_TYPE_BALANCED;
56278a8e 1886 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1887 rdev->pm.power_state[state_index].type =
1888 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1889 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1890 rdev->pm.power_state[state_index].default_clock_mode =
1891 &rdev->pm.power_state[state_index].clock_info[0];
d7311171
AD		 1892 } else if (state_index == 0) {
1893 rdev->pm.power_state[state_index].clock_info[0].flags |=
1894 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1895 }
1896 state_index++;
1897 break;
1898 }
1899 }
02b17cc0 1900 /* last mode is usually default */
a48b9b4e 1901 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 1902 rdev->pm.power_state[state_index - 1].type =
1903 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1904 rdev->pm.default_power_state_index = state_index - 1;
02b17cc0
AD		 1905 rdev->pm.power_state[state_index - 1].default_clock_mode =
1906 &rdev->pm.power_state[state_index - 1].clock_info[0];
a48b9b4e 1907 rdev->pm.power_state[state_index].flags &=
d7311171 1908 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1909 rdev->pm.power_state[state_index].misc = 0;
1910 rdev->pm.power_state[state_index].misc2 = 0;
02b17cc0 1911 }
49f65982 1912 } else {
c5e8ce61
AD		 1913 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1914 uint8_t fw_frev, fw_crev;
1915 uint16_t fw_data_offset, vddc = 0;
1916 union firmware_info *firmware_info;
1917 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1918
1919 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1920 &fw_frev, &fw_crev, &fw_data_offset)) {
1921 firmware_info =
1922 (union firmware_info *)(mode_info->atom_context->bios +
1923 fw_data_offset);
1924 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1925 }
1926
29fb52ca 1927 /* add the i2c bus for thermal/fan chip */
678e7dfa 1928 if (controller->ucType > 0) {
21a8122a 1929 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
29fb52ca 1930 DRM_INFO("Internal thermal controller %s fan control\n",
678e7dfa 1931 (controller->ucFanParameters &
29fb52ca 1932 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
21a8122a
AD		 1933 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1934 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1935 DRM_INFO("Internal thermal controller %s fan control\n",
1936 (controller->ucFanParameters &
1937 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1938 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1939 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1940 DRM_INFO("Internal thermal controller %s fan control\n",
1941 (controller->ucFanParameters &
1942 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1943 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
678e7dfa 1944 } else if ((controller->ucType ==
49f65982 1945 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
678e7dfa 1946 (controller->ucType ==
49f65982
AD		 1947 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1948 DRM_INFO("Special thermal controller config\n");
29fb52ca
AD		 1949 } else {
1950 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
678e7dfa
AD		 1951 pp_lib_thermal_controller_names[controller->ucType],
1952 controller->ucI2cAddress >> 1,
1953 (controller->ucFanParameters &
29fb52ca 1954 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
678e7dfa 1955 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
f376b94f 1956 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1957 if (rdev->pm.i2c_bus) {
1958 struct i2c_board_info info = { };
1959 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1960 info.addr = controller->ucI2cAddress >> 1;
1961 strlcpy(info.type, name, sizeof(info.type));
1962 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1963 }
1964
29fb52ca
AD		 1965 }
1966 }
02b17cc0 1967 /* first mode is usually default, followed by low to high */
56278a8e
AD		 1968 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1969 mode_index = 0;
1970 power_state = (struct _ATOM_PPLIB_STATE *)
1971 (mode_info->atom_context->bios +
1972 data_offset +
1973 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1974 i * power_info->info_4.ucStateEntrySize);
1975 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1976 (mode_info->atom_context->bios +
1977 data_offset +
1978 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1979 (power_state->ucNonClockStateIndex *
1980 power_info->info_4.ucNonClockSize));
56278a8e
AD		 1981 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1982 if (rdev->flags & RADEON_IS_IGP) {
1983 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1984 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1985 (mode_info->atom_context->bios +
1986 data_offset +
1987 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1988 (power_state->ucClockStateIndices[j] *
1989 power_info->info_4.ucClockInfoSize));
1990 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1991 sclk |= clock_info->ucLowEngineClockHigh << 16;
1992 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1993 /* skip invalid modes */
1994 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1995 continue;
aa1df0f2 1996 /* voltage works differently on IGPs */
56278a8e 1997 mode_index++;
49f65982
AD		 1998 } else if (ASIC_IS_DCE4(rdev)) {
1999 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2000 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2001 (mode_info->atom_context->bios +
2002 data_offset +
2003 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2004 (power_state->ucClockStateIndices[j] *
2005 power_info->info_4.ucClockInfoSize));
2006 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2007 sclk |= clock_info->ucEngineClockHigh << 16;
2008 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2009 mclk |= clock_info->ucMemoryClockHigh << 16;
2010 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2011 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2012 /* skip invalid modes */
2013 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2014 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2015 continue;
49f65982
AD		 2016 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2017 VOLTAGE_SW;
2018 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2019 clock_info->usVDDC;
2020 /* XXX usVDDCI */
2021 mode_index++;
56278a8e
AD		 2022 } else {
2023 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2024 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2025 (mode_info->atom_context->bios +
2026 data_offset +
2027 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2028 (power_state->ucClockStateIndices[j] *
2029 power_info->info_4.ucClockInfoSize));
2030 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2031 sclk |= clock_info->ucEngineClockHigh << 16;
2032 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2033 mclk |= clock_info->ucMemoryClockHigh << 16;
2034 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2035 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2036 /* skip invalid modes */
2037 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2038 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2039 continue;
56278a8e
AD		 2040 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2041 VOLTAGE_SW;
2042 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2043 clock_info->usVDDC;
2044 mode_index++;
2045 }
2046 }
2047 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2048 if (mode_index) {
845db70d 2049 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 2050 misc2 = le16_to_cpu(non_clock_info->usClassification);
79daedc9
AD		 2051 rdev->pm.power_state[state_index].misc = misc;
2052 rdev->pm.power_state[state_index].misc2 = misc2;
2053 rdev->pm.power_state[state_index].pcie_lanes =
845db70d
RM		 2054 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2055 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 2056 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2057 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2058 rdev->pm.power_state[state_index].type =
2059 POWER_STATE_TYPE_BATTERY;
2060 break;
2061 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2062 rdev->pm.power_state[state_index].type =
2063 POWER_STATE_TYPE_BALANCED;
2064 break;
2065 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2066 rdev->pm.power_state[state_index].type =
2067 POWER_STATE_TYPE_PERFORMANCE;
2068 break;
a44d2f37
AD		 2069 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2070 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2071 rdev->pm.power_state[state_index].type =
2072 POWER_STATE_TYPE_PERFORMANCE;
2073 break;
0ec0e74f 2074 }
a48b9b4e
AD		 2075 rdev->pm.power_state[state_index].flags = 0;
2076 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2077 rdev->pm.power_state[state_index].flags |=
d7311171 2078 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 2079 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 2080 rdev->pm.power_state[state_index].type =
2081 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2082 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 2083 rdev->pm.power_state[state_index].default_clock_mode =
2084 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
c5e8ce61
AD		 2085 /* patch the table values with the default slck/mclk from firmware info */
2086 for (j = 0; j < mode_index; j++) {
2087 rdev->pm.power_state[state_index].clock_info[j].mclk =
2088 rdev->clock.default_mclk;
2089 rdev->pm.power_state[state_index].clock_info[j].sclk =
2090 rdev->clock.default_sclk;
2091 if (vddc)
2092 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2093 vddc;
2094 }
56278a8e
AD		 2095 }
2096 state_index++;
2097 }
2098 }
d7311171
AD		 2099 /* if multiple clock modes, mark the lowest as no display */
2100 for (i = 0; i < state_index; i++) {
2101 if (rdev->pm.power_state[i].num_clock_modes > 1)
2102 rdev->pm.power_state[i].clock_info[0].flags |=
2103 RADEON_PM_MODE_NO_DISPLAY;
2104 }
02b17cc0 2105 /* first mode is usually default */
a48b9b4e 2106 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 2107 rdev->pm.power_state[0].type =
2108 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2109 rdev->pm.default_power_state_index = 0;
02b17cc0
AD		 2110 rdev->pm.power_state[0].default_clock_mode =
2111 &rdev->pm.power_state[0].clock_info[0];
2112 }
56278a8e
AD		 2113 }
2114 } else {
56278a8e 2115 /* add the default mode */
0ec0e74f
AD		 2116 rdev->pm.power_state[state_index].type =
2117 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2118 rdev->pm.power_state[state_index].num_clock_modes = 1;
2119 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2120 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2121 rdev->pm.power_state[state_index].default_clock_mode =
2122 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 2123 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2124 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2125 rdev->pm.default_power_state_index = state_index;
2126 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 2127 state_index++;
2128 }
02b17cc0 2129
56278a8e 2130 rdev->pm.num_power_states = state_index;
9038dfdf 2131
a48b9b4e
AD		 2132 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2133 rdev->pm.current_clock_mode_index = 0;
4d60173f 2134 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2135}
2136
771fe6b9 2137void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2138{
771fe6b9
JG		 2139 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2140 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2141
2142 args.ucEnable = enable;
2143
2144 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2145}
2146
7433874e
RM		 2147uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2148{
2149 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2150 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2151
2152 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2153 return args.ulReturnEngineClock;
2154}
2155
2156uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2157{
2158 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2159 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2160
2161 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2162 return args.ulReturnMemoryClock;
2163}
2164
771fe6b9
JG		 2165void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2166 uint32_t eng_clock)
2167{
2168 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2169 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2170
2171 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2172
2173 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2174}
2175
2176void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2177 uint32_t mem_clock)
2178{
2179 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2180 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2181
2182 if (rdev->flags & RADEON_IS_IGP)
2183 return;
2184
2185 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2186
2187 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2188}
2189
7ac9aa5a
AD		 2190union set_voltage {
2191 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2192 struct _SET_VOLTAGE_PARAMETERS v1;
2193 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2194};
2195
2196void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2197{
2198 union set_voltage args;
2199 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2200 u8 frev, crev, volt_index = level;
2201
2202 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2203 return;
2204
2205 switch (crev) {
2206 case 1:
2207 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2208 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2209 args.v1.ucVoltageIndex = volt_index;
2210 break;
2211 case 2:
2212 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2213 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2214 args.v2.usVoltageLevel = cpu_to_le16(level);
2215 break;
2216 default:
2217 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2218 return;
2219 }
2220
2221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2222}
2223
2224
2225
771fe6b9
JG		 2226void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2227{
2228 struct radeon_device *rdev = dev->dev_private;
2229 uint32_t bios_2_scratch, bios_6_scratch;
2230
2231 if (rdev->family >= CHIP_R600) {
4ce001ab 2232 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2233 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2234 } else {
4ce001ab 2235 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2236 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2237 }
2238
2239 /* let the bios control the backlight */
2240 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2241
2242 /* tell the bios not to handle mode switching */
2243 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2244
2245 if (rdev->family >= CHIP_R600) {
2246 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2247 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2248 } else {
2249 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2250 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2251 }
2252
2253}
2254
f657c2a7
YZ		 2255void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2256{
2257 uint32_t scratch_reg;
2258 int i;
2259
2260 if (rdev->family >= CHIP_R600)
2261 scratch_reg = R600_BIOS_0_SCRATCH;
2262 else
2263 scratch_reg = RADEON_BIOS_0_SCRATCH;
2264
2265 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2266 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2267}
2268
2269void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2270{
2271 uint32_t scratch_reg;
2272 int i;
2273
2274 if (rdev->family >= CHIP_R600)
2275 scratch_reg = R600_BIOS_0_SCRATCH;
2276 else
2277 scratch_reg = RADEON_BIOS_0_SCRATCH;
2278
2279 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2280 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2281}
2282
771fe6b9
JG		 2283void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2284{
2285 struct drm_device *dev = encoder->dev;
2286 struct radeon_device *rdev = dev->dev_private;
2287 uint32_t bios_6_scratch;
2288
2289 if (rdev->family >= CHIP_R600)
2290 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2291 else
2292 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2293
2294 if (lock)
2295 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2296 else
2297 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2298
2299 if (rdev->family >= CHIP_R600)
2300 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2301 else
2302 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2303}
2304
2305/* at some point we may want to break this out into individual functions */
2306void
2307radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2308 struct drm_encoder *encoder,
2309 bool connected)
2310{
2311 struct drm_device *dev = connector->dev;
2312 struct radeon_device *rdev = dev->dev_private;
2313 struct radeon_connector *radeon_connector =
2314 to_radeon_connector(connector);
2315 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2316 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2317
2318 if (rdev->family >= CHIP_R600) {
2319 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2320 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2321 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2322 } else {
2323 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2324 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2325 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2326 }
2327
2328 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2329 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2330 if (connected) {
d9fdaafb 2331 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2332 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2333 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2334 } else {
d9fdaafb 2335 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2336 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2337 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2338 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2339 }
2340 }
2341 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2342 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2343 if (connected) {
d9fdaafb 2344 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2345 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2346 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2347 } else {
d9fdaafb 2348 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2349 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2350 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2351 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2352 }
2353 }
2354 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2355 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2356 if (connected) {
d9fdaafb 2357 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2358 bios_0_scratch |= ATOM_S0_LCD1;
2359 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2360 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2361 } else {
d9fdaafb 2362 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2363 bios_0_scratch &= ~ATOM_S0_LCD1;
2364 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2365 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2366 }
2367 }
2368 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2369 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2370 if (connected) {
d9fdaafb 2371 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2372 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2373 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2374 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2375 } else {
d9fdaafb 2376 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2377 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2378 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2379 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2380 }
2381 }
2382 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2383 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2384 if (connected) {
d9fdaafb 2385 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2386 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2387 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2388 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2389 } else {
d9fdaafb 2390 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2391 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2392 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2393 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2394 }
2395 }
2396 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2397 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2398 if (connected) {
d9fdaafb 2399 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2400 bios_0_scratch |= ATOM_S0_DFP1;
2401 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2402 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2403 } else {
d9fdaafb 2404 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2405 bios_0_scratch &= ~ATOM_S0_DFP1;
2406 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2407 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2408 }
2409 }
2410 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2411 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2412 if (connected) {
d9fdaafb 2413 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2414 bios_0_scratch |= ATOM_S0_DFP2;
2415 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2416 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2417 } else {
d9fdaafb 2418 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2419 bios_0_scratch &= ~ATOM_S0_DFP2;
2420 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2421 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2422 }
2423 }
2424 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2425 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2426 if (connected) {
d9fdaafb 2427 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2428 bios_0_scratch |= ATOM_S0_DFP3;
2429 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2430 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2431 } else {
d9fdaafb 2432 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2433 bios_0_scratch &= ~ATOM_S0_DFP3;
2434 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2435 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2436 }
2437 }
2438 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2439 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2440 if (connected) {
d9fdaafb 2441 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2442 bios_0_scratch |= ATOM_S0_DFP4;
2443 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2444 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2445 } else {
d9fdaafb 2446 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2447 bios_0_scratch &= ~ATOM_S0_DFP4;
2448 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2449 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2450 }
2451 }
2452 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2453 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2454 if (connected) {
d9fdaafb 2455 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2456 bios_0_scratch |= ATOM_S0_DFP5;
2457 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2458 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2459 } else {
d9fdaafb 2460 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2461 bios_0_scratch &= ~ATOM_S0_DFP5;
2462 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2463 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2464 }
2465 }
2466
2467 if (rdev->family >= CHIP_R600) {
2468 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2469 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2470 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2471 } else {
2472 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2473 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2474 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2475 }
2476}
2477
2478void
2479radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2480{
2481 struct drm_device *dev = encoder->dev;
2482 struct radeon_device *rdev = dev->dev_private;
2483 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2484 uint32_t bios_3_scratch;
2485
2486 if (rdev->family >= CHIP_R600)
2487 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2488 else
2489 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2490
2491 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2492 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2493 bios_3_scratch |= (crtc << 18);
2494 }
2495 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2496 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2497 bios_3_scratch |= (crtc << 24);
2498 }
2499 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2500 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2501 bios_3_scratch |= (crtc << 16);
2502 }
2503 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2504 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2505 bios_3_scratch |= (crtc << 20);
2506 }
2507 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2508 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2509 bios_3_scratch |= (crtc << 17);
2510 }
2511 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2512 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2513 bios_3_scratch |= (crtc << 19);
2514 }
2515 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2516 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2517 bios_3_scratch |= (crtc << 23);
2518 }
2519 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2520 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2521 bios_3_scratch |= (crtc << 25);
2522 }
2523
2524 if (rdev->family >= CHIP_R600)
2525 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2526 else
2527 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2528}
2529
2530void
2531radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2532{
2533 struct drm_device *dev = encoder->dev;
2534 struct radeon_device *rdev = dev->dev_private;
2535 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2536 uint32_t bios_2_scratch;
2537
2538 if (rdev->family >= CHIP_R600)
2539 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2540 else
2541 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2542
2543 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2544 if (on)
2545 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2546 else
2547 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2548 }
2549 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2550 if (on)
2551 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2552 else
2553 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2554 }
2555 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2556 if (on)
2557 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2558 else
2559 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2560 }
2561 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2562 if (on)
2563 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2564 else
2565 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2566 }
2567 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2568 if (on)
2569 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2570 else
2571 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2572 }
2573 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2574 if (on)
2575 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2576 else
2577 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2578 }
2579 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2580 if (on)
2581 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2582 else
2583 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2584 }
2585 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2586 if (on)
2587 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2588 else
2589 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2590 }
2591 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2592 if (on)
2593 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2594 else
2595 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2596 }
2597 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2598 if (on)
2599 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2600 else
2601 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2602 }
2603
2604 if (rdev->family >= CHIP_R600)
2605 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2606 else
2607 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2608}
Clone of davem's net-next-2.6 tree