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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
29 | ||
30 | #include "atom.h" | |
31 | #include "atom-bits.h" | |
32 | ||
33 | /* from radeon_encoder.c */ | |
34 | extern uint32_t | |
35 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, | |
36 | uint8_t dac); | |
37 | extern void radeon_link_encoder_connector(struct drm_device *dev); | |
38 | extern void | |
39 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, | |
40 | uint32_t supported_device); | |
41 | ||
42 | /* from radeon_connector.c */ | |
43 | extern void | |
44 | radeon_add_atom_connector(struct drm_device *dev, | |
45 | uint32_t connector_id, | |
46 | uint32_t supported_device, | |
47 | int connector_type, | |
48 | struct radeon_i2c_bus_rec *i2c_bus, | |
b75fad06 | 49 | bool linkb, uint32_t igp_lane_info, |
eed45b30 AD |
50 | uint16_t connector_object_id, |
51 | struct radeon_hpd *hpd); | |
771fe6b9 JG |
52 | |
53 | /* from radeon_legacy_encoder.c */ | |
54 | extern void | |
55 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, | |
56 | uint32_t supported_device); | |
57 | ||
58 | union atom_supported_devices { | |
59 | struct _ATOM_SUPPORTED_DEVICES_INFO info; | |
60 | struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; | |
61 | struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; | |
62 | }; | |
63 | ||
eed45b30 AD |
64 | static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, |
65 | uint8_t id) | |
771fe6b9 | 66 | { |
771fe6b9 | 67 | struct atom_context *ctx = rdev->mode_info.atom_context; |
6a93cb25 | 68 | ATOM_GPIO_I2C_ASSIGMENT *gpio; |
771fe6b9 JG |
69 | struct radeon_i2c_bus_rec i2c; |
70 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); | |
71 | struct _ATOM_GPIO_I2C_INFO *i2c_info; | |
95beb690 AD |
72 | uint16_t data_offset, size; |
73 | int i, num_indices; | |
771fe6b9 JG |
74 | |
75 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); | |
76 | i2c.valid = false; | |
77 | ||
95beb690 | 78 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
a084e6ee AD |
79 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
80 | ||
95beb690 AD |
81 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
82 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); | |
83 | ||
84 | for (i = 0; i < num_indices; i++) { | |
a084e6ee AD |
85 | gpio = &i2c_info->asGPIO_Info[i]; |
86 | ||
87 | if (gpio->sucI2cId.ucAccess == id) { | |
88 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; | |
89 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; | |
90 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; | |
91 | i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; | |
92 | i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; | |
93 | i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; | |
94 | i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; | |
95 | i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; | |
96 | i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); | |
97 | i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); | |
98 | i2c.en_clk_mask = (1 << gpio->ucClkEnShift); | |
99 | i2c.en_data_mask = (1 << gpio->ucDataEnShift); | |
100 | i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); | |
101 | i2c.y_data_mask = (1 << gpio->ucDataY_Shift); | |
102 | i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); | |
103 | i2c.a_data_mask = (1 << gpio->ucDataA_Shift); | |
104 | ||
105 | if (gpio->sucI2cId.sbfAccess.bfHW_Capable) | |
106 | i2c.hw_capable = true; | |
107 | else | |
108 | i2c.hw_capable = false; | |
109 | ||
110 | if (gpio->sucI2cId.ucAccess == 0xa0) | |
111 | i2c.mm_i2c = true; | |
112 | else | |
113 | i2c.mm_i2c = false; | |
114 | ||
115 | i2c.i2c_id = gpio->sucI2cId.ucAccess; | |
116 | ||
117 | i2c.valid = true; | |
118 | break; | |
119 | } | |
d3f420d1 AD |
120 | } |
121 | } | |
771fe6b9 JG |
122 | |
123 | return i2c; | |
124 | } | |
125 | ||
eed45b30 AD |
126 | static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, |
127 | u8 id) | |
128 | { | |
129 | struct atom_context *ctx = rdev->mode_info.atom_context; | |
130 | struct radeon_gpio_rec gpio; | |
131 | int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); | |
132 | struct _ATOM_GPIO_PIN_LUT *gpio_info; | |
133 | ATOM_GPIO_PIN_ASSIGNMENT *pin; | |
134 | u16 data_offset, size; | |
135 | int i, num_indices; | |
136 | ||
137 | memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); | |
138 | gpio.valid = false; | |
139 | ||
a084e6ee AD |
140 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
141 | gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); | |
eed45b30 | 142 | |
a084e6ee AD |
143 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
144 | sizeof(ATOM_GPIO_PIN_ASSIGNMENT); | |
eed45b30 | 145 | |
a084e6ee AD |
146 | for (i = 0; i < num_indices; i++) { |
147 | pin = &gpio_info->asGPIO_Pin[i]; | |
148 | if (id == pin->ucGPIO_ID) { | |
149 | gpio.id = pin->ucGPIO_ID; | |
150 | gpio.reg = pin->usGpioPin_AIndex * 4; | |
151 | gpio.mask = (1 << pin->ucGpioPinBitShift); | |
152 | gpio.valid = true; | |
153 | break; | |
154 | } | |
eed45b30 AD |
155 | } |
156 | } | |
157 | ||
158 | return gpio; | |
159 | } | |
160 | ||
161 | static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, | |
162 | struct radeon_gpio_rec *gpio) | |
163 | { | |
164 | struct radeon_hpd hpd; | |
bcc1c2a1 AD |
165 | u32 reg; |
166 | ||
167 | if (ASIC_IS_DCE4(rdev)) | |
168 | reg = EVERGREEN_DC_GPIO_HPD_A; | |
169 | else | |
170 | reg = AVIVO_DC_GPIO_HPD_A; | |
171 | ||
eed45b30 | 172 | hpd.gpio = *gpio; |
bcc1c2a1 | 173 | if (gpio->reg == reg) { |
eed45b30 AD |
174 | switch(gpio->mask) { |
175 | case (1 << 0): | |
176 | hpd.hpd = RADEON_HPD_1; | |
177 | break; | |
178 | case (1 << 8): | |
179 | hpd.hpd = RADEON_HPD_2; | |
180 | break; | |
181 | case (1 << 16): | |
182 | hpd.hpd = RADEON_HPD_3; | |
183 | break; | |
184 | case (1 << 24): | |
185 | hpd.hpd = RADEON_HPD_4; | |
186 | break; | |
187 | case (1 << 26): | |
188 | hpd.hpd = RADEON_HPD_5; | |
189 | break; | |
190 | case (1 << 28): | |
191 | hpd.hpd = RADEON_HPD_6; | |
192 | break; | |
193 | default: | |
194 | hpd.hpd = RADEON_HPD_NONE; | |
195 | break; | |
196 | } | |
197 | } else | |
198 | hpd.hpd = RADEON_HPD_NONE; | |
199 | return hpd; | |
200 | } | |
201 | ||
771fe6b9 JG |
202 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
203 | uint32_t supported_device, | |
204 | int *connector_type, | |
848577ee | 205 | struct radeon_i2c_bus_rec *i2c_bus, |
eed45b30 AD |
206 | uint16_t *line_mux, |
207 | struct radeon_hpd *hpd) | |
771fe6b9 JG |
208 | { |
209 | ||
210 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ | |
211 | if ((dev->pdev->device == 0x791e) && | |
212 | (dev->pdev->subsystem_vendor == 0x1043) && | |
213 | (dev->pdev->subsystem_device == 0x826d)) { | |
214 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && | |
215 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) | |
216 | *connector_type = DRM_MODE_CONNECTOR_DVID; | |
217 | } | |
218 | ||
c86a9038 AD |
219 | /* Asrock RS600 board lists the DVI port as HDMI */ |
220 | if ((dev->pdev->device == 0x7941) && | |
221 | (dev->pdev->subsystem_vendor == 0x1849) && | |
222 | (dev->pdev->subsystem_device == 0x7941)) { | |
223 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && | |
224 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) | |
225 | *connector_type = DRM_MODE_CONNECTOR_DVID; | |
226 | } | |
227 | ||
771fe6b9 JG |
228 | /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ |
229 | if ((dev->pdev->device == 0x7941) && | |
230 | (dev->pdev->subsystem_vendor == 0x147b) && | |
231 | (dev->pdev->subsystem_device == 0x2412)) { | |
232 | if (*connector_type == DRM_MODE_CONNECTOR_DVII) | |
233 | return false; | |
234 | } | |
235 | ||
236 | /* Falcon NW laptop lists vga ddc line for LVDS */ | |
237 | if ((dev->pdev->device == 0x5653) && | |
238 | (dev->pdev->subsystem_vendor == 0x1462) && | |
239 | (dev->pdev->subsystem_device == 0x0291)) { | |
848577ee | 240 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { |
771fe6b9 | 241 | i2c_bus->valid = false; |
848577ee AD |
242 | *line_mux = 53; |
243 | } | |
771fe6b9 JG |
244 | } |
245 | ||
4e3f9b78 AD |
246 | /* HIS X1300 is DVI+VGA, not DVI+DVI */ |
247 | if ((dev->pdev->device == 0x7146) && | |
248 | (dev->pdev->subsystem_vendor == 0x17af) && | |
249 | (dev->pdev->subsystem_device == 0x2058)) { | |
250 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) | |
251 | return false; | |
252 | } | |
253 | ||
aa1a750e DA |
254 | /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ |
255 | if ((dev->pdev->device == 0x7142) && | |
256 | (dev->pdev->subsystem_vendor == 0x1458) && | |
257 | (dev->pdev->subsystem_device == 0x2134)) { | |
258 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) | |
259 | return false; | |
260 | } | |
261 | ||
262 | ||
771fe6b9 JG |
263 | /* Funky macbooks */ |
264 | if ((dev->pdev->device == 0x71C5) && | |
265 | (dev->pdev->subsystem_vendor == 0x106b) && | |
266 | (dev->pdev->subsystem_device == 0x0080)) { | |
267 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || | |
268 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) | |
269 | return false; | |
e1e8a5dd AD |
270 | if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) |
271 | *line_mux = 0x90; | |
771fe6b9 JG |
272 | } |
273 | ||
771fe6b9 JG |
274 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
275 | if ((dev->pdev->device == 0x9598) && | |
276 | (dev->pdev->subsystem_vendor == 0x1043) && | |
277 | (dev->pdev->subsystem_device == 0x01da)) { | |
705af9c7 | 278 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
d42571ef | 279 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
705af9c7 AD |
280 | } |
281 | } | |
282 | ||
283 | /* ASUS HD 3450 board lists the DVI port as HDMI */ | |
284 | if ((dev->pdev->device == 0x95C5) && | |
285 | (dev->pdev->subsystem_vendor == 0x1043) && | |
286 | (dev->pdev->subsystem_device == 0x01e2)) { | |
287 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { | |
d42571ef | 288 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
771fe6b9 JG |
289 | } |
290 | } | |
291 | ||
705af9c7 AD |
292 | /* some BIOSes seem to report DAC on HDMI - usually this is a board with |
293 | * HDMI + VGA reporting as HDMI | |
294 | */ | |
295 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { | |
296 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { | |
297 | *connector_type = DRM_MODE_CONNECTOR_VGA; | |
298 | *line_mux = 0; | |
299 | } | |
300 | } | |
301 | ||
3e5f8ff3 AD |
302 | /* Acer laptop reports DVI-D as DVI-I */ |
303 | if ((dev->pdev->device == 0x95c4) && | |
304 | (dev->pdev->subsystem_vendor == 0x1025) && | |
305 | (dev->pdev->subsystem_device == 0x013c)) { | |
306 | if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && | |
307 | (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) | |
308 | *connector_type = DRM_MODE_CONNECTOR_DVID; | |
309 | } | |
310 | ||
efa8450f DA |
311 | /* XFX Pine Group device rv730 reports no VGA DDC lines |
312 | * even though they are wired up to record 0x93 | |
313 | */ | |
314 | if ((dev->pdev->device == 0x9498) && | |
315 | (dev->pdev->subsystem_vendor == 0x1682) && | |
316 | (dev->pdev->subsystem_device == 0x2452)) { | |
317 | struct radeon_device *rdev = dev->dev_private; | |
318 | *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); | |
319 | } | |
771fe6b9 JG |
320 | return true; |
321 | } | |
322 | ||
323 | const int supported_devices_connector_convert[] = { | |
324 | DRM_MODE_CONNECTOR_Unknown, | |
325 | DRM_MODE_CONNECTOR_VGA, | |
326 | DRM_MODE_CONNECTOR_DVII, | |
327 | DRM_MODE_CONNECTOR_DVID, | |
328 | DRM_MODE_CONNECTOR_DVIA, | |
329 | DRM_MODE_CONNECTOR_SVIDEO, | |
330 | DRM_MODE_CONNECTOR_Composite, | |
331 | DRM_MODE_CONNECTOR_LVDS, | |
332 | DRM_MODE_CONNECTOR_Unknown, | |
333 | DRM_MODE_CONNECTOR_Unknown, | |
334 | DRM_MODE_CONNECTOR_HDMIA, | |
335 | DRM_MODE_CONNECTOR_HDMIB, | |
336 | DRM_MODE_CONNECTOR_Unknown, | |
337 | DRM_MODE_CONNECTOR_Unknown, | |
338 | DRM_MODE_CONNECTOR_9PinDIN, | |
339 | DRM_MODE_CONNECTOR_DisplayPort | |
340 | }; | |
341 | ||
b75fad06 AD |
342 | const uint16_t supported_devices_connector_object_id_convert[] = { |
343 | CONNECTOR_OBJECT_ID_NONE, | |
344 | CONNECTOR_OBJECT_ID_VGA, | |
345 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ | |
346 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ | |
347 | CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ | |
348 | CONNECTOR_OBJECT_ID_COMPOSITE, | |
349 | CONNECTOR_OBJECT_ID_SVIDEO, | |
350 | CONNECTOR_OBJECT_ID_LVDS, | |
351 | CONNECTOR_OBJECT_ID_9PIN_DIN, | |
352 | CONNECTOR_OBJECT_ID_9PIN_DIN, | |
353 | CONNECTOR_OBJECT_ID_DISPLAYPORT, | |
354 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A, | |
355 | CONNECTOR_OBJECT_ID_HDMI_TYPE_B, | |
356 | CONNECTOR_OBJECT_ID_SVIDEO | |
357 | }; | |
358 | ||
771fe6b9 JG |
359 | const int object_connector_convert[] = { |
360 | DRM_MODE_CONNECTOR_Unknown, | |
361 | DRM_MODE_CONNECTOR_DVII, | |
362 | DRM_MODE_CONNECTOR_DVII, | |
363 | DRM_MODE_CONNECTOR_DVID, | |
364 | DRM_MODE_CONNECTOR_DVID, | |
365 | DRM_MODE_CONNECTOR_VGA, | |
366 | DRM_MODE_CONNECTOR_Composite, | |
367 | DRM_MODE_CONNECTOR_SVIDEO, | |
368 | DRM_MODE_CONNECTOR_Unknown, | |
705af9c7 | 369 | DRM_MODE_CONNECTOR_Unknown, |
771fe6b9 JG |
370 | DRM_MODE_CONNECTOR_9PinDIN, |
371 | DRM_MODE_CONNECTOR_Unknown, | |
372 | DRM_MODE_CONNECTOR_HDMIA, | |
373 | DRM_MODE_CONNECTOR_HDMIB, | |
771fe6b9 JG |
374 | DRM_MODE_CONNECTOR_LVDS, |
375 | DRM_MODE_CONNECTOR_9PinDIN, | |
376 | DRM_MODE_CONNECTOR_Unknown, | |
377 | DRM_MODE_CONNECTOR_Unknown, | |
378 | DRM_MODE_CONNECTOR_Unknown, | |
196c58d2 AD |
379 | DRM_MODE_CONNECTOR_DisplayPort, |
380 | DRM_MODE_CONNECTOR_eDP, | |
381 | DRM_MODE_CONNECTOR_Unknown | |
771fe6b9 JG |
382 | }; |
383 | ||
384 | bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) | |
385 | { | |
386 | struct radeon_device *rdev = dev->dev_private; | |
387 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
388 | struct atom_context *ctx = mode_info->atom_context; | |
389 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
eed45b30 AD |
390 | u16 size, data_offset; |
391 | u8 frev, crev; | |
771fe6b9 JG |
392 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
393 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; | |
394 | ATOM_OBJECT_HEADER *obj_header; | |
395 | int i, j, path_size, device_support; | |
396 | int connector_type; | |
eed45b30 | 397 | u16 igp_lane_info, conn_id, connector_object_id; |
771fe6b9 JG |
398 | bool linkb; |
399 | struct radeon_i2c_bus_rec ddc_bus; | |
eed45b30 AD |
400 | struct radeon_gpio_rec gpio; |
401 | struct radeon_hpd hpd; | |
402 | ||
a084e6ee | 403 | if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) |
771fe6b9 JG |
404 | return false; |
405 | ||
406 | if (crev < 2) | |
407 | return false; | |
408 | ||
409 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); | |
410 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) | |
411 | (ctx->bios + data_offset + | |
412 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); | |
413 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) | |
414 | (ctx->bios + data_offset + | |
415 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); | |
416 | device_support = le16_to_cpu(obj_header->usDeviceSupport); | |
417 | ||
418 | path_size = 0; | |
419 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { | |
420 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; | |
421 | ATOM_DISPLAY_OBJECT_PATH *path; | |
422 | addr += path_size; | |
423 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; | |
424 | path_size += le16_to_cpu(path->usSize); | |
425 | linkb = false; | |
771fe6b9 JG |
426 | if (device_support & le16_to_cpu(path->usDeviceTag)) { |
427 | uint8_t con_obj_id, con_obj_num, con_obj_type; | |
428 | ||
429 | con_obj_id = | |
430 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) | |
431 | >> OBJECT_ID_SHIFT; | |
432 | con_obj_num = | |
433 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) | |
434 | >> ENUM_ID_SHIFT; | |
435 | con_obj_type = | |
436 | (le16_to_cpu(path->usConnObjectId) & | |
437 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
438 | ||
4bbd4973 DA |
439 | /* TODO CV support */ |
440 | if (le16_to_cpu(path->usDeviceTag) == | |
441 | ATOM_DEVICE_CV_SUPPORT) | |
771fe6b9 JG |
442 | continue; |
443 | ||
ee59f2b4 AD |
444 | /* IGP chips */ |
445 | if ((rdev->flags & RADEON_IS_IGP) && | |
771fe6b9 JG |
446 | (con_obj_id == |
447 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { | |
448 | uint16_t igp_offset = 0; | |
449 | ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; | |
450 | ||
451 | index = | |
452 | GetIndexIntoMasterTable(DATA, | |
453 | IntegratedSystemInfo); | |
454 | ||
a084e6ee AD |
455 | if (atom_parse_data_header(ctx, index, &size, &frev, |
456 | &crev, &igp_offset)) { | |
457 | ||
458 | if (crev >= 2) { | |
459 | igp_obj = | |
460 | (ATOM_INTEGRATED_SYSTEM_INFO_V2 | |
461 | *) (ctx->bios + igp_offset); | |
462 | ||
463 | if (igp_obj) { | |
464 | uint32_t slot_config, ct; | |
465 | ||
466 | if (con_obj_num == 1) | |
467 | slot_config = | |
468 | igp_obj-> | |
469 | ulDDISlot1Config; | |
470 | else | |
471 | slot_config = | |
472 | igp_obj-> | |
473 | ulDDISlot2Config; | |
474 | ||
475 | ct = (slot_config >> 16) & 0xff; | |
476 | connector_type = | |
477 | object_connector_convert | |
478 | [ct]; | |
479 | connector_object_id = ct; | |
480 | igp_lane_info = | |
481 | slot_config & 0xffff; | |
482 | } else | |
483 | continue; | |
771fe6b9 JG |
484 | } else |
485 | continue; | |
a084e6ee AD |
486 | } else { |
487 | igp_lane_info = 0; | |
488 | connector_type = | |
489 | object_connector_convert[con_obj_id]; | |
490 | connector_object_id = con_obj_id; | |
491 | } | |
771fe6b9 JG |
492 | } else { |
493 | igp_lane_info = 0; | |
494 | connector_type = | |
495 | object_connector_convert[con_obj_id]; | |
b75fad06 | 496 | connector_object_id = con_obj_id; |
771fe6b9 JG |
497 | } |
498 | ||
499 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | |
500 | continue; | |
501 | ||
502 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); | |
503 | j++) { | |
504 | uint8_t enc_obj_id, enc_obj_num, enc_obj_type; | |
505 | ||
506 | enc_obj_id = | |
507 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
508 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
509 | enc_obj_num = | |
510 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
511 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
512 | enc_obj_type = | |
513 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
514 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
515 | ||
516 | /* FIXME: add support for router objects */ | |
517 | if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { | |
518 | if (enc_obj_num == 2) | |
519 | linkb = true; | |
520 | else | |
521 | linkb = false; | |
522 | ||
523 | radeon_add_atom_encoder(dev, | |
524 | enc_obj_id, | |
525 | le16_to_cpu | |
526 | (path-> | |
527 | usDeviceTag)); | |
528 | ||
529 | } | |
530 | } | |
531 | ||
eed45b30 | 532 | /* look up gpio for ddc, hpd */ |
2bfcc0fc AD |
533 | ddc_bus.valid = false; |
534 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 535 | if ((le16_to_cpu(path->usDeviceTag) & |
eed45b30 | 536 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { |
771fe6b9 JG |
537 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { |
538 | if (le16_to_cpu(path->usConnObjectId) == | |
539 | le16_to_cpu(con_obj->asObjects[j]. | |
540 | usObjectID)) { | |
541 | ATOM_COMMON_RECORD_HEADER | |
542 | *record = | |
543 | (ATOM_COMMON_RECORD_HEADER | |
544 | *) | |
545 | (ctx->bios + data_offset + | |
546 | le16_to_cpu(con_obj-> | |
547 | asObjects[j]. | |
548 | usRecordOffset)); | |
549 | ATOM_I2C_RECORD *i2c_record; | |
eed45b30 | 550 | ATOM_HPD_INT_RECORD *hpd_record; |
d3f420d1 | 551 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; |
6a93cb25 | 552 | |
771fe6b9 JG |
553 | while (record->ucRecordType > 0 |
554 | && record-> | |
555 | ucRecordType <= | |
556 | ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
eed45b30 | 557 | switch (record->ucRecordType) { |
771fe6b9 JG |
558 | case ATOM_I2C_RECORD_TYPE: |
559 | i2c_record = | |
eed45b30 AD |
560 | (ATOM_I2C_RECORD *) |
561 | record; | |
d3f420d1 AD |
562 | i2c_config = |
563 | (ATOM_I2C_ID_CONFIG_ACCESS *) | |
564 | &i2c_record->sucI2cId; | |
eed45b30 | 565 | ddc_bus = radeon_lookup_i2c_gpio(rdev, |
d3f420d1 AD |
566 | i2c_config-> |
567 | ucAccess); | |
eed45b30 AD |
568 | break; |
569 | case ATOM_HPD_INT_RECORD_TYPE: | |
570 | hpd_record = | |
571 | (ATOM_HPD_INT_RECORD *) | |
572 | record; | |
573 | gpio = radeon_lookup_gpio(rdev, | |
574 | hpd_record->ucHPDIntGPIOID); | |
575 | hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); | |
576 | hpd.plugged_state = hpd_record->ucPlugged_PinState; | |
771fe6b9 JG |
577 | break; |
578 | } | |
579 | record = | |
580 | (ATOM_COMMON_RECORD_HEADER | |
581 | *) ((char *)record | |
582 | + | |
583 | record-> | |
584 | ucRecordSize); | |
585 | } | |
586 | break; | |
587 | } | |
588 | } | |
eed45b30 | 589 | } |
771fe6b9 | 590 | |
bcc1c2a1 | 591 | /* needed for aux chan transactions */ |
8e36ed00 | 592 | ddc_bus.hpd = hpd.hpd; |
bcc1c2a1 | 593 | |
705af9c7 AD |
594 | conn_id = le16_to_cpu(path->usConnObjectId); |
595 | ||
596 | if (!radeon_atom_apply_quirks | |
597 | (dev, le16_to_cpu(path->usDeviceTag), &connector_type, | |
eed45b30 | 598 | &ddc_bus, &conn_id, &hpd)) |
705af9c7 AD |
599 | continue; |
600 | ||
771fe6b9 | 601 | radeon_add_atom_connector(dev, |
705af9c7 | 602 | conn_id, |
771fe6b9 JG |
603 | le16_to_cpu(path-> |
604 | usDeviceTag), | |
605 | connector_type, &ddc_bus, | |
b75fad06 | 606 | linkb, igp_lane_info, |
eed45b30 AD |
607 | connector_object_id, |
608 | &hpd); | |
771fe6b9 JG |
609 | |
610 | } | |
611 | } | |
612 | ||
613 | radeon_link_encoder_connector(dev); | |
614 | ||
615 | return true; | |
616 | } | |
617 | ||
b75fad06 AD |
618 | static uint16_t atombios_get_connector_object_id(struct drm_device *dev, |
619 | int connector_type, | |
620 | uint16_t devices) | |
621 | { | |
622 | struct radeon_device *rdev = dev->dev_private; | |
623 | ||
624 | if (rdev->flags & RADEON_IS_IGP) { | |
625 | return supported_devices_connector_object_id_convert | |
626 | [connector_type]; | |
627 | } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || | |
628 | (connector_type == DRM_MODE_CONNECTOR_DVID)) && | |
629 | (devices & ATOM_DEVICE_DFP2_SUPPORT)) { | |
630 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
631 | struct atom_context *ctx = mode_info->atom_context; | |
632 | int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); | |
633 | uint16_t size, data_offset; | |
634 | uint8_t frev, crev; | |
635 | ATOM_XTMDS_INFO *xtmds; | |
636 | ||
a084e6ee AD |
637 | if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { |
638 | xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); | |
b75fad06 | 639 | |
a084e6ee AD |
640 | if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { |
641 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
642 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; | |
643 | else | |
644 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; | |
645 | } else { | |
646 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
647 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; | |
648 | else | |
649 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; | |
650 | } | |
651 | } else | |
652 | return supported_devices_connector_object_id_convert | |
653 | [connector_type]; | |
b75fad06 AD |
654 | } else { |
655 | return supported_devices_connector_object_id_convert | |
656 | [connector_type]; | |
657 | } | |
658 | } | |
659 | ||
771fe6b9 JG |
660 | struct bios_connector { |
661 | bool valid; | |
705af9c7 | 662 | uint16_t line_mux; |
771fe6b9 JG |
663 | uint16_t devices; |
664 | int connector_type; | |
665 | struct radeon_i2c_bus_rec ddc_bus; | |
eed45b30 | 666 | struct radeon_hpd hpd; |
771fe6b9 JG |
667 | }; |
668 | ||
669 | bool radeon_get_atom_connector_info_from_supported_devices_table(struct | |
670 | drm_device | |
671 | *dev) | |
672 | { | |
673 | struct radeon_device *rdev = dev->dev_private; | |
674 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
675 | struct atom_context *ctx = mode_info->atom_context; | |
676 | int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); | |
677 | uint16_t size, data_offset; | |
678 | uint8_t frev, crev; | |
679 | uint16_t device_support; | |
680 | uint8_t dac; | |
681 | union atom_supported_devices *supported_devices; | |
eed45b30 | 682 | int i, j, max_device; |
f49d273d PB |
683 | struct bios_connector *bios_connectors; |
684 | size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; | |
771fe6b9 | 685 | |
f49d273d PB |
686 | bios_connectors = kzalloc(bc_size, GFP_KERNEL); |
687 | if (!bios_connectors) | |
688 | return false; | |
689 | ||
690 | if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, | |
691 | &data_offset)) { | |
692 | kfree(bios_connectors); | |
a084e6ee | 693 | return false; |
f49d273d | 694 | } |
771fe6b9 JG |
695 | |
696 | supported_devices = | |
697 | (union atom_supported_devices *)(ctx->bios + data_offset); | |
698 | ||
699 | device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); | |
700 | ||
eed45b30 AD |
701 | if (frev > 1) |
702 | max_device = ATOM_MAX_SUPPORTED_DEVICE; | |
703 | else | |
704 | max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; | |
705 | ||
706 | for (i = 0; i < max_device; i++) { | |
771fe6b9 JG |
707 | ATOM_CONNECTOR_INFO_I2C ci = |
708 | supported_devices->info.asConnInfo[i]; | |
709 | ||
710 | bios_connectors[i].valid = false; | |
711 | ||
712 | if (!(device_support & (1 << i))) { | |
713 | continue; | |
714 | } | |
715 | ||
716 | if (i == ATOM_DEVICE_CV_INDEX) { | |
717 | DRM_DEBUG("Skipping Component Video\n"); | |
718 | continue; | |
719 | } | |
720 | ||
771fe6b9 JG |
721 | bios_connectors[i].connector_type = |
722 | supported_devices_connector_convert[ci.sucConnectorInfo. | |
723 | sbfAccess. | |
724 | bfConnectorType]; | |
725 | ||
726 | if (bios_connectors[i].connector_type == | |
727 | DRM_MODE_CONNECTOR_Unknown) | |
728 | continue; | |
729 | ||
730 | dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; | |
731 | ||
d3f420d1 AD |
732 | bios_connectors[i].line_mux = |
733 | ci.sucI2cId.ucAccess; | |
771fe6b9 JG |
734 | |
735 | /* give tv unique connector ids */ | |
736 | if (i == ATOM_DEVICE_TV1_INDEX) { | |
737 | bios_connectors[i].ddc_bus.valid = false; | |
738 | bios_connectors[i].line_mux = 50; | |
739 | } else if (i == ATOM_DEVICE_TV2_INDEX) { | |
740 | bios_connectors[i].ddc_bus.valid = false; | |
741 | bios_connectors[i].line_mux = 51; | |
742 | } else if (i == ATOM_DEVICE_CV_INDEX) { | |
743 | bios_connectors[i].ddc_bus.valid = false; | |
744 | bios_connectors[i].line_mux = 52; | |
745 | } else | |
746 | bios_connectors[i].ddc_bus = | |
eed45b30 AD |
747 | radeon_lookup_i2c_gpio(rdev, |
748 | bios_connectors[i].line_mux); | |
749 | ||
750 | if ((crev > 1) && (frev > 1)) { | |
751 | u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; | |
752 | switch (isb) { | |
753 | case 0x4: | |
754 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; | |
755 | break; | |
756 | case 0xa: | |
757 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; | |
758 | break; | |
759 | default: | |
760 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; | |
761 | break; | |
762 | } | |
763 | } else { | |
764 | if (i == ATOM_DEVICE_DFP1_INDEX) | |
765 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; | |
766 | else if (i == ATOM_DEVICE_DFP2_INDEX) | |
767 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; | |
768 | else | |
769 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; | |
770 | } | |
771fe6b9 JG |
771 | |
772 | /* Always set the connector type to VGA for CRT1/CRT2. if they are | |
773 | * shared with a DVI port, we'll pick up the DVI connector when we | |
774 | * merge the outputs. Some bioses incorrectly list VGA ports as DVI. | |
775 | */ | |
776 | if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) | |
777 | bios_connectors[i].connector_type = | |
778 | DRM_MODE_CONNECTOR_VGA; | |
779 | ||
780 | if (!radeon_atom_apply_quirks | |
781 | (dev, (1 << i), &bios_connectors[i].connector_type, | |
eed45b30 AD |
782 | &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, |
783 | &bios_connectors[i].hpd)) | |
771fe6b9 JG |
784 | continue; |
785 | ||
786 | bios_connectors[i].valid = true; | |
787 | bios_connectors[i].devices = (1 << i); | |
788 | ||
789 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) | |
790 | radeon_add_atom_encoder(dev, | |
791 | radeon_get_encoder_id(dev, | |
792 | (1 << i), | |
793 | dac), | |
794 | (1 << i)); | |
795 | else | |
796 | radeon_add_legacy_encoder(dev, | |
797 | radeon_get_encoder_id(dev, | |
f56cd64f | 798 | (1 << i), |
771fe6b9 JG |
799 | dac), |
800 | (1 << i)); | |
801 | } | |
802 | ||
803 | /* combine shared connectors */ | |
eed45b30 | 804 | for (i = 0; i < max_device; i++) { |
771fe6b9 | 805 | if (bios_connectors[i].valid) { |
eed45b30 | 806 | for (j = 0; j < max_device; j++) { |
771fe6b9 JG |
807 | if (bios_connectors[j].valid && (i != j)) { |
808 | if (bios_connectors[i].line_mux == | |
809 | bios_connectors[j].line_mux) { | |
f56cd64f AD |
810 | /* make sure not to combine LVDS */ |
811 | if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
812 | bios_connectors[i].line_mux = 53; | |
813 | bios_connectors[i].ddc_bus.valid = false; | |
814 | continue; | |
815 | } | |
816 | if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
817 | bios_connectors[j].line_mux = 53; | |
818 | bios_connectors[j].ddc_bus.valid = false; | |
819 | continue; | |
820 | } | |
821 | /* combine analog and digital for DVI-I */ | |
822 | if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && | |
823 | (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || | |
824 | ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && | |
825 | (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { | |
826 | bios_connectors[i].devices |= | |
827 | bios_connectors[j].devices; | |
828 | bios_connectors[i].connector_type = | |
829 | DRM_MODE_CONNECTOR_DVII; | |
830 | if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) | |
eed45b30 AD |
831 | bios_connectors[i].hpd = |
832 | bios_connectors[j].hpd; | |
f56cd64f | 833 | bios_connectors[j].valid = false; |
771fe6b9 JG |
834 | } |
835 | } | |
836 | } | |
837 | } | |
838 | } | |
839 | } | |
840 | ||
841 | /* add the connectors */ | |
eed45b30 | 842 | for (i = 0; i < max_device; i++) { |
b75fad06 AD |
843 | if (bios_connectors[i].valid) { |
844 | uint16_t connector_object_id = | |
845 | atombios_get_connector_object_id(dev, | |
846 | bios_connectors[i].connector_type, | |
847 | bios_connectors[i].devices); | |
771fe6b9 JG |
848 | radeon_add_atom_connector(dev, |
849 | bios_connectors[i].line_mux, | |
850 | bios_connectors[i].devices, | |
851 | bios_connectors[i]. | |
852 | connector_type, | |
853 | &bios_connectors[i].ddc_bus, | |
b75fad06 | 854 | false, 0, |
eed45b30 AD |
855 | connector_object_id, |
856 | &bios_connectors[i].hpd); | |
b75fad06 | 857 | } |
771fe6b9 JG |
858 | } |
859 | ||
860 | radeon_link_encoder_connector(dev); | |
861 | ||
f49d273d | 862 | kfree(bios_connectors); |
771fe6b9 JG |
863 | return true; |
864 | } | |
865 | ||
866 | union firmware_info { | |
867 | ATOM_FIRMWARE_INFO info; | |
868 | ATOM_FIRMWARE_INFO_V1_2 info_12; | |
869 | ATOM_FIRMWARE_INFO_V1_3 info_13; | |
870 | ATOM_FIRMWARE_INFO_V1_4 info_14; | |
bcc1c2a1 | 871 | ATOM_FIRMWARE_INFO_V2_1 info_21; |
771fe6b9 JG |
872 | }; |
873 | ||
874 | bool radeon_atom_get_clock_info(struct drm_device *dev) | |
875 | { | |
876 | struct radeon_device *rdev = dev->dev_private; | |
877 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
878 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
879 | union firmware_info *firmware_info; | |
880 | uint8_t frev, crev; | |
881 | struct radeon_pll *p1pll = &rdev->clock.p1pll; | |
882 | struct radeon_pll *p2pll = &rdev->clock.p2pll; | |
bcc1c2a1 | 883 | struct radeon_pll *dcpll = &rdev->clock.dcpll; |
771fe6b9 JG |
884 | struct radeon_pll *spll = &rdev->clock.spll; |
885 | struct radeon_pll *mpll = &rdev->clock.mpll; | |
886 | uint16_t data_offset; | |
887 | ||
a084e6ee AD |
888 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
889 | &frev, &crev, &data_offset)) { | |
890 | firmware_info = | |
891 | (union firmware_info *)(mode_info->atom_context->bios + | |
892 | data_offset); | |
771fe6b9 JG |
893 | /* pixel clocks */ |
894 | p1pll->reference_freq = | |
895 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
896 | p1pll->reference_div = 0; | |
897 | ||
bc293e58 MF |
898 | if (crev < 2) |
899 | p1pll->pll_out_min = | |
900 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); | |
901 | else | |
902 | p1pll->pll_out_min = | |
903 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); | |
771fe6b9 JG |
904 | p1pll->pll_out_max = |
905 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); | |
906 | ||
86cb2bbf AD |
907 | if (crev >= 4) { |
908 | p1pll->lcd_pll_out_min = | |
909 | le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; | |
910 | if (p1pll->lcd_pll_out_min == 0) | |
911 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; | |
912 | p1pll->lcd_pll_out_max = | |
913 | le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; | |
914 | if (p1pll->lcd_pll_out_max == 0) | |
915 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; | |
916 | } else { | |
917 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; | |
918 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; | |
919 | } | |
920 | ||
771fe6b9 JG |
921 | if (p1pll->pll_out_min == 0) { |
922 | if (ASIC_IS_AVIVO(rdev)) | |
923 | p1pll->pll_out_min = 64800; | |
924 | else | |
925 | p1pll->pll_out_min = 20000; | |
8f552a66 AD |
926 | } else if (p1pll->pll_out_min > 64800) { |
927 | /* Limiting the pll output range is a good thing generally as | |
928 | * it limits the number of possible pll combinations for a given | |
929 | * frequency presumably to the ones that work best on each card. | |
930 | * However, certain duallink DVI monitors seem to like | |
931 | * pll combinations that would be limited by this at least on | |
932 | * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per | |
933 | * family. | |
934 | */ | |
b27b6375 AD |
935 | if (!radeon_new_pll) |
936 | p1pll->pll_out_min = 64800; | |
771fe6b9 JG |
937 | } |
938 | ||
939 | p1pll->pll_in_min = | |
940 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); | |
941 | p1pll->pll_in_max = | |
942 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); | |
943 | ||
944 | *p2pll = *p1pll; | |
945 | ||
946 | /* system clock */ | |
947 | spll->reference_freq = | |
948 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
949 | spll->reference_div = 0; | |
950 | ||
951 | spll->pll_out_min = | |
952 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); | |
953 | spll->pll_out_max = | |
954 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); | |
955 | ||
956 | /* ??? */ | |
957 | if (spll->pll_out_min == 0) { | |
958 | if (ASIC_IS_AVIVO(rdev)) | |
959 | spll->pll_out_min = 64800; | |
960 | else | |
961 | spll->pll_out_min = 20000; | |
962 | } | |
963 | ||
964 | spll->pll_in_min = | |
965 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); | |
966 | spll->pll_in_max = | |
967 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); | |
968 | ||
969 | /* memory clock */ | |
970 | mpll->reference_freq = | |
971 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
972 | mpll->reference_div = 0; | |
973 | ||
974 | mpll->pll_out_min = | |
975 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); | |
976 | mpll->pll_out_max = | |
977 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); | |
978 | ||
979 | /* ??? */ | |
980 | if (mpll->pll_out_min == 0) { | |
981 | if (ASIC_IS_AVIVO(rdev)) | |
982 | mpll->pll_out_min = 64800; | |
983 | else | |
984 | mpll->pll_out_min = 20000; | |
985 | } | |
986 | ||
987 | mpll->pll_in_min = | |
988 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); | |
989 | mpll->pll_in_max = | |
990 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); | |
991 | ||
992 | rdev->clock.default_sclk = | |
993 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); | |
994 | rdev->clock.default_mclk = | |
995 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); | |
996 | ||
bcc1c2a1 AD |
997 | if (ASIC_IS_DCE4(rdev)) { |
998 | rdev->clock.default_dispclk = | |
999 | le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); | |
1000 | if (rdev->clock.default_dispclk == 0) | |
1001 | rdev->clock.default_dispclk = 60000; /* 600 Mhz */ | |
1002 | rdev->clock.dp_extclk = | |
1003 | le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); | |
1004 | } | |
1005 | *dcpll = *p1pll; | |
1006 | ||
771fe6b9 JG |
1007 | return true; |
1008 | } | |
bcc1c2a1 | 1009 | |
771fe6b9 JG |
1010 | return false; |
1011 | } | |
1012 | ||
06b6476d AD |
1013 | union igp_info { |
1014 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
1015 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; | |
1016 | }; | |
1017 | ||
1018 | bool radeon_atombios_sideport_present(struct radeon_device *rdev) | |
1019 | { | |
1020 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1021 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
1022 | union igp_info *igp_info; | |
1023 | u8 frev, crev; | |
1024 | u16 data_offset; | |
1025 | ||
a084e6ee AD |
1026 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1027 | &frev, &crev, &data_offset)) { | |
1028 | igp_info = (union igp_info *)(mode_info->atom_context->bios + | |
06b6476d | 1029 | data_offset); |
06b6476d AD |
1030 | switch (crev) { |
1031 | case 1: | |
1032 | if (igp_info->info.ucMemoryType & 0xf0) | |
1033 | return true; | |
1034 | break; | |
1035 | case 2: | |
1036 | if (igp_info->info_2.ucMemoryType & 0x0f) | |
1037 | return true; | |
1038 | break; | |
1039 | default: | |
1040 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); | |
1041 | break; | |
1042 | } | |
1043 | } | |
1044 | return false; | |
1045 | } | |
1046 | ||
445282db DA |
1047 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
1048 | struct radeon_encoder_int_tmds *tmds) | |
771fe6b9 JG |
1049 | { |
1050 | struct drm_device *dev = encoder->base.dev; | |
1051 | struct radeon_device *rdev = dev->dev_private; | |
1052 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1053 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); | |
1054 | uint16_t data_offset; | |
1055 | struct _ATOM_TMDS_INFO *tmds_info; | |
1056 | uint8_t frev, crev; | |
1057 | uint16_t maxfreq; | |
1058 | int i; | |
771fe6b9 | 1059 | |
a084e6ee AD |
1060 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1061 | &frev, &crev, &data_offset)) { | |
1062 | tmds_info = | |
1063 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + | |
1064 | data_offset); | |
771fe6b9 | 1065 | |
771fe6b9 JG |
1066 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
1067 | for (i = 0; i < 4; i++) { | |
1068 | tmds->tmds_pll[i].freq = | |
1069 | le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); | |
1070 | tmds->tmds_pll[i].value = | |
1071 | tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; | |
1072 | tmds->tmds_pll[i].value |= | |
1073 | (tmds_info->asMiscInfo[i]. | |
1074 | ucPLL_VCO_Gain & 0x3f) << 6; | |
1075 | tmds->tmds_pll[i].value |= | |
1076 | (tmds_info->asMiscInfo[i]. | |
1077 | ucPLL_DutyCycle & 0xf) << 12; | |
1078 | tmds->tmds_pll[i].value |= | |
1079 | (tmds_info->asMiscInfo[i]. | |
1080 | ucPLL_VoltageSwing & 0xf) << 16; | |
1081 | ||
1082 | DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", | |
1083 | tmds->tmds_pll[i].freq, | |
1084 | tmds->tmds_pll[i].value); | |
1085 | ||
1086 | if (maxfreq == tmds->tmds_pll[i].freq) { | |
1087 | tmds->tmds_pll[i].freq = 0xffffffff; | |
1088 | break; | |
1089 | } | |
1090 | } | |
445282db | 1091 | return true; |
771fe6b9 | 1092 | } |
445282db | 1093 | return false; |
771fe6b9 JG |
1094 | } |
1095 | ||
ebbe1cb9 AD |
1096 | static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct |
1097 | radeon_encoder | |
1098 | *encoder, | |
1099 | int id) | |
1100 | { | |
1101 | struct drm_device *dev = encoder->base.dev; | |
1102 | struct radeon_device *rdev = dev->dev_private; | |
1103 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1104 | int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); | |
1105 | uint16_t data_offset; | |
1106 | struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; | |
1107 | uint8_t frev, crev; | |
1108 | struct radeon_atom_ss *ss = NULL; | |
279b215e | 1109 | int i; |
ebbe1cb9 AD |
1110 | |
1111 | if (id > ATOM_MAX_SS_ENTRY) | |
1112 | return NULL; | |
1113 | ||
a084e6ee AD |
1114 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1115 | &frev, &crev, &data_offset)) { | |
1116 | ss_info = | |
1117 | (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); | |
ebbe1cb9 | 1118 | |
ebbe1cb9 AD |
1119 | ss = |
1120 | kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL); | |
1121 | ||
1122 | if (!ss) | |
1123 | return NULL; | |
1124 | ||
279b215e AD |
1125 | for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) { |
1126 | if (ss_info->asSS_Info[i].ucSS_Id == id) { | |
1127 | ss->percentage = | |
1128 | le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage); | |
1129 | ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType; | |
1130 | ss->step = ss_info->asSS_Info[i].ucSS_Step; | |
1131 | ss->delay = ss_info->asSS_Info[i].ucSS_Delay; | |
1132 | ss->range = ss_info->asSS_Info[i].ucSS_Range; | |
1133 | ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div; | |
1d3d51b6 | 1134 | break; |
279b215e AD |
1135 | } |
1136 | } | |
ebbe1cb9 AD |
1137 | } |
1138 | return ss; | |
1139 | } | |
1140 | ||
771fe6b9 JG |
1141 | union lvds_info { |
1142 | struct _ATOM_LVDS_INFO info; | |
1143 | struct _ATOM_LVDS_INFO_V12 info_12; | |
1144 | }; | |
1145 | ||
1146 | struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct | |
1147 | radeon_encoder | |
1148 | *encoder) | |
1149 | { | |
1150 | struct drm_device *dev = encoder->base.dev; | |
1151 | struct radeon_device *rdev = dev->dev_private; | |
1152 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1153 | int index = GetIndexIntoMasterTable(DATA, LVDS_Info); | |
7dde8a19 | 1154 | uint16_t data_offset, misc; |
771fe6b9 JG |
1155 | union lvds_info *lvds_info; |
1156 | uint8_t frev, crev; | |
1157 | struct radeon_encoder_atom_dig *lvds = NULL; | |
1158 | ||
a084e6ee AD |
1159 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1160 | &frev, &crev, &data_offset)) { | |
1161 | lvds_info = | |
1162 | (union lvds_info *)(mode_info->atom_context->bios + data_offset); | |
771fe6b9 JG |
1163 | lvds = |
1164 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); | |
1165 | ||
1166 | if (!lvds) | |
1167 | return NULL; | |
1168 | ||
de2103e4 | 1169 | lvds->native_mode.clock = |
771fe6b9 | 1170 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
de2103e4 | 1171 | lvds->native_mode.hdisplay = |
771fe6b9 | 1172 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
de2103e4 | 1173 | lvds->native_mode.vdisplay = |
771fe6b9 | 1174 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
de2103e4 AD |
1175 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
1176 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); | |
1177 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + | |
1178 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); | |
1179 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + | |
1180 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); | |
1181 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + | |
1182 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); | |
1183 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + | |
1ff26a36 | 1184 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); |
de2103e4 AD |
1185 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
1186 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); | |
771fe6b9 JG |
1187 | lvds->panel_pwr_delay = |
1188 | le16_to_cpu(lvds_info->info.usOffDelayInMs); | |
1189 | lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; | |
7dde8a19 AD |
1190 | |
1191 | misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); | |
1192 | if (misc & ATOM_VSYNC_POLARITY) | |
1193 | lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
1194 | if (misc & ATOM_HSYNC_POLARITY) | |
1195 | lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
1196 | if (misc & ATOM_COMPOSITESYNC) | |
1197 | lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; | |
1198 | if (misc & ATOM_INTERLACE) | |
1199 | lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
1200 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1201 | lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; | |
1202 | ||
de2103e4 AD |
1203 | /* set crtc values */ |
1204 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); | |
771fe6b9 | 1205 | |
ebbe1cb9 AD |
1206 | lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id); |
1207 | ||
7c27f87d | 1208 | if (ASIC_IS_AVIVO(rdev)) { |
383be5d1 AD |
1209 | if (radeon_new_pll == 0) |
1210 | lvds->pll_algo = PLL_ALGO_LEGACY; | |
1211 | else | |
1212 | lvds->pll_algo = PLL_ALGO_NEW; | |
1213 | } else { | |
1214 | if (radeon_new_pll == 1) | |
1215 | lvds->pll_algo = PLL_ALGO_NEW; | |
7c27f87d AD |
1216 | else |
1217 | lvds->pll_algo = PLL_ALGO_LEGACY; | |
383be5d1 | 1218 | } |
7c27f87d | 1219 | |
771fe6b9 JG |
1220 | encoder->native_mode = lvds->native_mode; |
1221 | } | |
1222 | return lvds; | |
1223 | } | |
1224 | ||
6fe7ac3f AD |
1225 | struct radeon_encoder_primary_dac * |
1226 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) | |
1227 | { | |
1228 | struct drm_device *dev = encoder->base.dev; | |
1229 | struct radeon_device *rdev = dev->dev_private; | |
1230 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1231 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); | |
1232 | uint16_t data_offset; | |
1233 | struct _COMPASSIONATE_DATA *dac_info; | |
1234 | uint8_t frev, crev; | |
1235 | uint8_t bg, dac; | |
6fe7ac3f AD |
1236 | struct radeon_encoder_primary_dac *p_dac = NULL; |
1237 | ||
a084e6ee AD |
1238 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1239 | &frev, &crev, &data_offset)) { | |
1240 | dac_info = (struct _COMPASSIONATE_DATA *) | |
1241 | (mode_info->atom_context->bios + data_offset); | |
6fe7ac3f | 1242 | |
6fe7ac3f AD |
1243 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); |
1244 | ||
1245 | if (!p_dac) | |
1246 | return NULL; | |
1247 | ||
1248 | bg = dac_info->ucDAC1_BG_Adjustment; | |
1249 | dac = dac_info->ucDAC1_DAC_Adjustment; | |
1250 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); | |
1251 | ||
1252 | } | |
1253 | return p_dac; | |
1254 | } | |
1255 | ||
4ce001ab | 1256 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
5a9bcacc | 1257 | struct drm_display_mode *mode) |
4ce001ab DA |
1258 | { |
1259 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1260 | ATOM_ANALOG_TV_INFO *tv_info; | |
1261 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; | |
1262 | ATOM_DTD_FORMAT *dtd_timings; | |
1263 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); | |
1264 | u8 frev, crev; | |
5a9bcacc | 1265 | u16 data_offset, misc; |
4ce001ab | 1266 | |
a084e6ee AD |
1267 | if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, |
1268 | &frev, &crev, &data_offset)) | |
1269 | return false; | |
4ce001ab DA |
1270 | |
1271 | switch (crev) { | |
1272 | case 1: | |
1273 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); | |
0031c41b | 1274 | if (index >= MAX_SUPPORTED_TV_TIMING) |
4ce001ab DA |
1275 | return false; |
1276 | ||
5a9bcacc AD |
1277 | mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
1278 | mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); | |
1279 | mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); | |
1280 | mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + | |
1281 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); | |
1282 | ||
1283 | mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); | |
1284 | mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); | |
1285 | mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); | |
1286 | mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + | |
1287 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); | |
1288 | ||
1289 | mode->flags = 0; | |
1290 | misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); | |
1291 | if (misc & ATOM_VSYNC_POLARITY) | |
1292 | mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
1293 | if (misc & ATOM_HSYNC_POLARITY) | |
1294 | mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
1295 | if (misc & ATOM_COMPOSITESYNC) | |
1296 | mode->flags |= DRM_MODE_FLAG_CSYNC; | |
1297 | if (misc & ATOM_INTERLACE) | |
1298 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1299 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1300 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; | |
1301 | ||
1302 | mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; | |
4ce001ab DA |
1303 | |
1304 | if (index == 1) { | |
1305 | /* PAL timings appear to have wrong values for totals */ | |
5a9bcacc AD |
1306 | mode->crtc_htotal -= 1; |
1307 | mode->crtc_vtotal -= 1; | |
4ce001ab DA |
1308 | } |
1309 | break; | |
1310 | case 2: | |
1311 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); | |
0031c41b | 1312 | if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) |
4ce001ab DA |
1313 | return false; |
1314 | ||
1315 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; | |
5a9bcacc AD |
1316 | mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + |
1317 | le16_to_cpu(dtd_timings->usHBlanking_Time); | |
1318 | mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); | |
1319 | mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + | |
1320 | le16_to_cpu(dtd_timings->usHSyncOffset); | |
1321 | mode->crtc_hsync_end = mode->crtc_hsync_start + | |
1322 | le16_to_cpu(dtd_timings->usHSyncWidth); | |
1323 | ||
1324 | mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + | |
1325 | le16_to_cpu(dtd_timings->usVBlanking_Time); | |
1326 | mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); | |
1327 | mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + | |
1328 | le16_to_cpu(dtd_timings->usVSyncOffset); | |
1329 | mode->crtc_vsync_end = mode->crtc_vsync_start + | |
1330 | le16_to_cpu(dtd_timings->usVSyncWidth); | |
1331 | ||
1332 | mode->flags = 0; | |
1333 | misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); | |
1334 | if (misc & ATOM_VSYNC_POLARITY) | |
1335 | mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
1336 | if (misc & ATOM_HSYNC_POLARITY) | |
1337 | mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
1338 | if (misc & ATOM_COMPOSITESYNC) | |
1339 | mode->flags |= DRM_MODE_FLAG_CSYNC; | |
1340 | if (misc & ATOM_INTERLACE) | |
1341 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1342 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1343 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; | |
1344 | ||
1345 | mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; | |
4ce001ab DA |
1346 | break; |
1347 | } | |
1348 | return true; | |
1349 | } | |
1350 | ||
d79766fa AD |
1351 | enum radeon_tv_std |
1352 | radeon_atombios_get_tv_info(struct radeon_device *rdev) | |
1353 | { | |
1354 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1355 | int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); | |
1356 | uint16_t data_offset; | |
1357 | uint8_t frev, crev; | |
1358 | struct _ATOM_ANALOG_TV_INFO *tv_info; | |
1359 | enum radeon_tv_std tv_std = TV_STD_NTSC; | |
1360 | ||
a084e6ee AD |
1361 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1362 | &frev, &crev, &data_offset)) { | |
d79766fa | 1363 | |
a084e6ee AD |
1364 | tv_info = (struct _ATOM_ANALOG_TV_INFO *) |
1365 | (mode_info->atom_context->bios + data_offset); | |
d79766fa | 1366 | |
a084e6ee AD |
1367 | switch (tv_info->ucTV_BootUpDefaultStandard) { |
1368 | case ATOM_TV_NTSC: | |
1369 | tv_std = TV_STD_NTSC; | |
1370 | DRM_INFO("Default TV standard: NTSC\n"); | |
1371 | break; | |
1372 | case ATOM_TV_NTSCJ: | |
1373 | tv_std = TV_STD_NTSC_J; | |
1374 | DRM_INFO("Default TV standard: NTSC-J\n"); | |
1375 | break; | |
1376 | case ATOM_TV_PAL: | |
1377 | tv_std = TV_STD_PAL; | |
1378 | DRM_INFO("Default TV standard: PAL\n"); | |
1379 | break; | |
1380 | case ATOM_TV_PALM: | |
1381 | tv_std = TV_STD_PAL_M; | |
1382 | DRM_INFO("Default TV standard: PAL-M\n"); | |
1383 | break; | |
1384 | case ATOM_TV_PALN: | |
1385 | tv_std = TV_STD_PAL_N; | |
1386 | DRM_INFO("Default TV standard: PAL-N\n"); | |
1387 | break; | |
1388 | case ATOM_TV_PALCN: | |
1389 | tv_std = TV_STD_PAL_CN; | |
1390 | DRM_INFO("Default TV standard: PAL-CN\n"); | |
1391 | break; | |
1392 | case ATOM_TV_PAL60: | |
1393 | tv_std = TV_STD_PAL_60; | |
1394 | DRM_INFO("Default TV standard: PAL-60\n"); | |
1395 | break; | |
1396 | case ATOM_TV_SECAM: | |
1397 | tv_std = TV_STD_SECAM; | |
1398 | DRM_INFO("Default TV standard: SECAM\n"); | |
1399 | break; | |
1400 | default: | |
1401 | tv_std = TV_STD_NTSC; | |
1402 | DRM_INFO("Unknown TV standard; defaulting to NTSC\n"); | |
1403 | break; | |
1404 | } | |
d79766fa AD |
1405 | } |
1406 | return tv_std; | |
1407 | } | |
1408 | ||
6fe7ac3f AD |
1409 | struct radeon_encoder_tv_dac * |
1410 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) | |
1411 | { | |
1412 | struct drm_device *dev = encoder->base.dev; | |
1413 | struct radeon_device *rdev = dev->dev_private; | |
1414 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1415 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); | |
1416 | uint16_t data_offset; | |
1417 | struct _COMPASSIONATE_DATA *dac_info; | |
1418 | uint8_t frev, crev; | |
1419 | uint8_t bg, dac; | |
6fe7ac3f AD |
1420 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
1421 | ||
a084e6ee AD |
1422 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1423 | &frev, &crev, &data_offset)) { | |
6fe7ac3f | 1424 | |
a084e6ee AD |
1425 | dac_info = (struct _COMPASSIONATE_DATA *) |
1426 | (mode_info->atom_context->bios + data_offset); | |
6fe7ac3f | 1427 | |
6fe7ac3f AD |
1428 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
1429 | ||
1430 | if (!tv_dac) | |
1431 | return NULL; | |
1432 | ||
1433 | bg = dac_info->ucDAC2_CRT2_BG_Adjustment; | |
1434 | dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; | |
1435 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); | |
1436 | ||
1437 | bg = dac_info->ucDAC2_PAL_BG_Adjustment; | |
1438 | dac = dac_info->ucDAC2_PAL_DAC_Adjustment; | |
1439 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); | |
1440 | ||
1441 | bg = dac_info->ucDAC2_NTSC_BG_Adjustment; | |
1442 | dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; | |
1443 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); | |
1444 | ||
d79766fa | 1445 | tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); |
6fe7ac3f AD |
1446 | } |
1447 | return tv_dac; | |
1448 | } | |
1449 | ||
29fb52ca AD |
1450 | static const char *thermal_controller_names[] = { |
1451 | "NONE", | |
678e7dfa AD |
1452 | "lm63", |
1453 | "adm1032", | |
1454 | "adm1030", | |
1455 | "max6649", | |
1456 | "lm64", | |
1457 | "f75375", | |
1458 | "asc7xxx", | |
29fb52ca AD |
1459 | }; |
1460 | ||
1461 | static const char *pp_lib_thermal_controller_names[] = { | |
1462 | "NONE", | |
678e7dfa AD |
1463 | "lm63", |
1464 | "adm1032", | |
1465 | "adm1030", | |
1466 | "max6649", | |
1467 | "lm64", | |
1468 | "f75375", | |
29fb52ca AD |
1469 | "RV6xx", |
1470 | "RV770", | |
678e7dfa | 1471 | "adt7473", |
49f65982 AD |
1472 | "External GPIO", |
1473 | "Evergreen", | |
678e7dfa | 1474 | "adt7473 with internal", |
49f65982 | 1475 | |
29fb52ca AD |
1476 | }; |
1477 | ||
56278a8e AD |
1478 | union power_info { |
1479 | struct _ATOM_POWERPLAY_INFO info; | |
1480 | struct _ATOM_POWERPLAY_INFO_V2 info_2; | |
1481 | struct _ATOM_POWERPLAY_INFO_V3 info_3; | |
1482 | struct _ATOM_PPLIB_POWERPLAYTABLE info_4; | |
1483 | }; | |
1484 | ||
1485 | void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |
771fe6b9 | 1486 | { |
56278a8e AD |
1487 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
1488 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
1489 | u16 data_offset; | |
1490 | u8 frev, crev; | |
1491 | u32 misc, misc2 = 0, sclk, mclk; | |
1492 | union power_info *power_info; | |
1493 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
1494 | struct _ATOM_PPLIB_STATE *power_state; | |
1495 | int num_modes = 0, i, j; | |
1496 | int state_index = 0, mode_index = 0; | |
29fb52ca | 1497 | struct radeon_i2c_bus_rec i2c_bus; |
771fe6b9 | 1498 | |
a48b9b4e | 1499 | rdev->pm.default_power_state_index = -1; |
56278a8e | 1500 | |
a084e6ee AD |
1501 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1502 | &frev, &crev, &data_offset)) { | |
1503 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
56278a8e | 1504 | if (frev < 4) { |
29fb52ca AD |
1505 | /* add the i2c bus for thermal/fan chip */ |
1506 | if (power_info->info.ucOverdriveThermalController > 0) { | |
1507 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", | |
1508 | thermal_controller_names[power_info->info.ucOverdriveThermalController], | |
1509 | power_info->info.ucOverdriveControllerAddress >> 1); | |
1510 | i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); | |
1511 | rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal"); | |
678e7dfa AD |
1512 | if (rdev->pm.i2c_bus) { |
1513 | struct i2c_board_info info = { }; | |
1514 | const char *name = thermal_controller_names[power_info->info. | |
1515 | ucOverdriveThermalController]; | |
1516 | info.addr = power_info->info.ucOverdriveControllerAddress >> 1; | |
1517 | strlcpy(info.type, name, sizeof(info.type)); | |
1518 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); | |
1519 | } | |
29fb52ca | 1520 | } |
56278a8e AD |
1521 | num_modes = power_info->info.ucNumOfPowerModeEntries; |
1522 | if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) | |
1523 | num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; | |
02b17cc0 | 1524 | /* last mode is usually default, array is low to high */ |
56278a8e AD |
1525 | for (i = 0; i < num_modes; i++) { |
1526 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | |
1527 | switch (frev) { | |
1528 | case 1: | |
1529 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
1530 | rdev->pm.power_state[state_index].clock_info[0].mclk = | |
1531 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); | |
1532 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
1533 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); | |
1534 | /* skip invalid modes */ | |
1535 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
1536 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
1537 | continue; | |
79daedc9 | 1538 | rdev->pm.power_state[state_index].pcie_lanes = |
56278a8e AD |
1539 | power_info->info.asPowerPlayInfo[i].ucNumPciELanes; |
1540 | misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); | |
84d88f4c AD |
1541 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
1542 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { | |
56278a8e AD |
1543 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
1544 | VOLTAGE_GPIO; | |
1545 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
1546 | radeon_lookup_gpio(rdev, | |
1547 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); | |
1548 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
1549 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1550 | true; | |
1551 | else | |
1552 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1553 | false; | |
1554 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
1555 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1556 | VOLTAGE_VDDC; | |
1557 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
1558 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; | |
1559 | } | |
d7311171 | 1560 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
79daedc9 | 1561 | rdev->pm.power_state[state_index].misc = misc; |
0ec0e74f AD |
1562 | /* order matters! */ |
1563 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) | |
1564 | rdev->pm.power_state[state_index].type = | |
1565 | POWER_STATE_TYPE_POWERSAVE; | |
1566 | if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) | |
1567 | rdev->pm.power_state[state_index].type = | |
1568 | POWER_STATE_TYPE_BATTERY; | |
1569 | if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) | |
1570 | rdev->pm.power_state[state_index].type = | |
1571 | POWER_STATE_TYPE_BATTERY; | |
1572 | if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) | |
1573 | rdev->pm.power_state[state_index].type = | |
1574 | POWER_STATE_TYPE_BALANCED; | |
a48b9b4e | 1575 | if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { |
0ec0e74f AD |
1576 | rdev->pm.power_state[state_index].type = |
1577 | POWER_STATE_TYPE_PERFORMANCE; | |
a48b9b4e | 1578 | rdev->pm.power_state[state_index].flags &= |
d7311171 | 1579 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
a48b9b4e | 1580 | } |
56278a8e | 1581 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { |
0ec0e74f AD |
1582 | rdev->pm.power_state[state_index].type = |
1583 | POWER_STATE_TYPE_DEFAULT; | |
a48b9b4e | 1584 | rdev->pm.default_power_state_index = state_index; |
56278a8e AD |
1585 | rdev->pm.power_state[state_index].default_clock_mode = |
1586 | &rdev->pm.power_state[state_index].clock_info[0]; | |
a48b9b4e | 1587 | rdev->pm.power_state[state_index].flags &= |
d7311171 AD |
1588 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
1589 | } else if (state_index == 0) { | |
1590 | rdev->pm.power_state[state_index].clock_info[0].flags |= | |
1591 | RADEON_PM_MODE_NO_DISPLAY; | |
56278a8e AD |
1592 | } |
1593 | state_index++; | |
1594 | break; | |
1595 | case 2: | |
1596 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
1597 | rdev->pm.power_state[state_index].clock_info[0].mclk = | |
1598 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); | |
1599 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
1600 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); | |
1601 | /* skip invalid modes */ | |
1602 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
1603 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
1604 | continue; | |
79daedc9 | 1605 | rdev->pm.power_state[state_index].pcie_lanes = |
56278a8e AD |
1606 | power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; |
1607 | misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); | |
1608 | misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); | |
84d88f4c AD |
1609 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
1610 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { | |
56278a8e AD |
1611 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
1612 | VOLTAGE_GPIO; | |
1613 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
1614 | radeon_lookup_gpio(rdev, | |
1615 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); | |
1616 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
1617 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1618 | true; | |
1619 | else | |
1620 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1621 | false; | |
1622 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
1623 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1624 | VOLTAGE_VDDC; | |
1625 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
1626 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; | |
1627 | } | |
d7311171 | 1628 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
79daedc9 AD |
1629 | rdev->pm.power_state[state_index].misc = misc; |
1630 | rdev->pm.power_state[state_index].misc2 = misc2; | |
0ec0e74f AD |
1631 | /* order matters! */ |
1632 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) | |
1633 | rdev->pm.power_state[state_index].type = | |
1634 | POWER_STATE_TYPE_POWERSAVE; | |
1635 | if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) | |
1636 | rdev->pm.power_state[state_index].type = | |
1637 | POWER_STATE_TYPE_BATTERY; | |
1638 | if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) | |
1639 | rdev->pm.power_state[state_index].type = | |
1640 | POWER_STATE_TYPE_BATTERY; | |
1641 | if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) | |
1642 | rdev->pm.power_state[state_index].type = | |
1643 | POWER_STATE_TYPE_BALANCED; | |
a48b9b4e | 1644 | if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { |
0ec0e74f AD |
1645 | rdev->pm.power_state[state_index].type = |
1646 | POWER_STATE_TYPE_PERFORMANCE; | |
a48b9b4e | 1647 | rdev->pm.power_state[state_index].flags &= |
d7311171 | 1648 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
a48b9b4e | 1649 | } |
0ec0e74f AD |
1650 | if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) |
1651 | rdev->pm.power_state[state_index].type = | |
1652 | POWER_STATE_TYPE_BALANCED; | |
a48b9b4e AD |
1653 | if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT) |
1654 | rdev->pm.power_state[state_index].flags &= | |
d7311171 | 1655 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
56278a8e | 1656 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { |
0ec0e74f AD |
1657 | rdev->pm.power_state[state_index].type = |
1658 | POWER_STATE_TYPE_DEFAULT; | |
a48b9b4e | 1659 | rdev->pm.default_power_state_index = state_index; |
56278a8e AD |
1660 | rdev->pm.power_state[state_index].default_clock_mode = |
1661 | &rdev->pm.power_state[state_index].clock_info[0]; | |
a48b9b4e | 1662 | rdev->pm.power_state[state_index].flags &= |
d7311171 AD |
1663 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
1664 | } else if (state_index == 0) { | |
1665 | rdev->pm.power_state[state_index].clock_info[0].flags |= | |
1666 | RADEON_PM_MODE_NO_DISPLAY; | |
56278a8e AD |
1667 | } |
1668 | state_index++; | |
1669 | break; | |
1670 | case 3: | |
1671 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
1672 | rdev->pm.power_state[state_index].clock_info[0].mclk = | |
1673 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); | |
1674 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
1675 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); | |
1676 | /* skip invalid modes */ | |
1677 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
1678 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
1679 | continue; | |
79daedc9 | 1680 | rdev->pm.power_state[state_index].pcie_lanes = |
56278a8e AD |
1681 | power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; |
1682 | misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); | |
1683 | misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); | |
84d88f4c AD |
1684 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
1685 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { | |
56278a8e AD |
1686 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
1687 | VOLTAGE_GPIO; | |
1688 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
1689 | radeon_lookup_gpio(rdev, | |
1690 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); | |
1691 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
1692 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1693 | true; | |
1694 | else | |
1695 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1696 | false; | |
1697 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
1698 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1699 | VOLTAGE_VDDC; | |
1700 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
1701 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; | |
1702 | if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { | |
1703 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = | |
1704 | true; | |
1705 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = | |
1706 | power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; | |
1707 | } | |
1708 | } | |
d7311171 | 1709 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
79daedc9 AD |
1710 | rdev->pm.power_state[state_index].misc = misc; |
1711 | rdev->pm.power_state[state_index].misc2 = misc2; | |
0ec0e74f AD |
1712 | /* order matters! */ |
1713 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) | |
1714 | rdev->pm.power_state[state_index].type = | |
1715 | POWER_STATE_TYPE_POWERSAVE; | |
1716 | if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) | |
1717 | rdev->pm.power_state[state_index].type = | |
1718 | POWER_STATE_TYPE_BATTERY; | |
1719 | if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) | |
1720 | rdev->pm.power_state[state_index].type = | |
1721 | POWER_STATE_TYPE_BATTERY; | |
1722 | if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) | |
1723 | rdev->pm.power_state[state_index].type = | |
1724 | POWER_STATE_TYPE_BALANCED; | |
a48b9b4e | 1725 | if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { |
0ec0e74f AD |
1726 | rdev->pm.power_state[state_index].type = |
1727 | POWER_STATE_TYPE_PERFORMANCE; | |
a48b9b4e | 1728 | rdev->pm.power_state[state_index].flags &= |
d7311171 | 1729 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
a48b9b4e | 1730 | } |
0ec0e74f AD |
1731 | if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) |
1732 | rdev->pm.power_state[state_index].type = | |
1733 | POWER_STATE_TYPE_BALANCED; | |
56278a8e | 1734 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { |
0ec0e74f AD |
1735 | rdev->pm.power_state[state_index].type = |
1736 | POWER_STATE_TYPE_DEFAULT; | |
a48b9b4e | 1737 | rdev->pm.default_power_state_index = state_index; |
56278a8e AD |
1738 | rdev->pm.power_state[state_index].default_clock_mode = |
1739 | &rdev->pm.power_state[state_index].clock_info[0]; | |
d7311171 AD |
1740 | } else if (state_index == 0) { |
1741 | rdev->pm.power_state[state_index].clock_info[0].flags |= | |
1742 | RADEON_PM_MODE_NO_DISPLAY; | |
56278a8e AD |
1743 | } |
1744 | state_index++; | |
1745 | break; | |
1746 | } | |
1747 | } | |
02b17cc0 | 1748 | /* last mode is usually default */ |
a48b9b4e | 1749 | if (rdev->pm.default_power_state_index == -1) { |
02b17cc0 AD |
1750 | rdev->pm.power_state[state_index - 1].type = |
1751 | POWER_STATE_TYPE_DEFAULT; | |
a48b9b4e | 1752 | rdev->pm.default_power_state_index = state_index - 1; |
02b17cc0 AD |
1753 | rdev->pm.power_state[state_index - 1].default_clock_mode = |
1754 | &rdev->pm.power_state[state_index - 1].clock_info[0]; | |
a48b9b4e | 1755 | rdev->pm.power_state[state_index].flags &= |
d7311171 | 1756 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
79daedc9 AD |
1757 | rdev->pm.power_state[state_index].misc = 0; |
1758 | rdev->pm.power_state[state_index].misc2 = 0; | |
02b17cc0 | 1759 | } |
49f65982 | 1760 | } else { |
c5e8ce61 AD |
1761 | int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
1762 | uint8_t fw_frev, fw_crev; | |
1763 | uint16_t fw_data_offset, vddc = 0; | |
1764 | union firmware_info *firmware_info; | |
1765 | ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController; | |
1766 | ||
1767 | if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL, | |
1768 | &fw_frev, &fw_crev, &fw_data_offset)) { | |
1769 | firmware_info = | |
1770 | (union firmware_info *)(mode_info->atom_context->bios + | |
1771 | fw_data_offset); | |
1772 | vddc = firmware_info->info_14.usBootUpVDDCVoltage; | |
1773 | } | |
1774 | ||
29fb52ca AD |
1775 | /* add the i2c bus for thermal/fan chip */ |
1776 | /* no support for internal controller yet */ | |
678e7dfa AD |
1777 | if (controller->ucType > 0) { |
1778 | if ((controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) || | |
1779 | (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) || | |
1780 | (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN)) { | |
29fb52ca | 1781 | DRM_INFO("Internal thermal controller %s fan control\n", |
678e7dfa | 1782 | (controller->ucFanParameters & |
29fb52ca | 1783 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
678e7dfa | 1784 | } else if ((controller->ucType == |
49f65982 | 1785 | ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || |
678e7dfa | 1786 | (controller->ucType == |
49f65982 AD |
1787 | ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) { |
1788 | DRM_INFO("Special thermal controller config\n"); | |
29fb52ca AD |
1789 | } else { |
1790 | DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", | |
678e7dfa AD |
1791 | pp_lib_thermal_controller_names[controller->ucType], |
1792 | controller->ucI2cAddress >> 1, | |
1793 | (controller->ucFanParameters & | |
29fb52ca | 1794 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
678e7dfa | 1795 | i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); |
29fb52ca | 1796 | rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal"); |
678e7dfa AD |
1797 | if (rdev->pm.i2c_bus) { |
1798 | struct i2c_board_info info = { }; | |
1799 | const char *name = pp_lib_thermal_controller_names[controller->ucType]; | |
1800 | info.addr = controller->ucI2cAddress >> 1; | |
1801 | strlcpy(info.type, name, sizeof(info.type)); | |
1802 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); | |
1803 | } | |
1804 | ||
29fb52ca AD |
1805 | } |
1806 | } | |
02b17cc0 | 1807 | /* first mode is usually default, followed by low to high */ |
56278a8e AD |
1808 | for (i = 0; i < power_info->info_4.ucNumStates; i++) { |
1809 | mode_index = 0; | |
1810 | power_state = (struct _ATOM_PPLIB_STATE *) | |
1811 | (mode_info->atom_context->bios + | |
1812 | data_offset + | |
1813 | le16_to_cpu(power_info->info_4.usStateArrayOffset) + | |
1814 | i * power_info->info_4.ucStateEntrySize); | |
1815 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) | |
1816 | (mode_info->atom_context->bios + | |
1817 | data_offset + | |
1818 | le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) + | |
1819 | (power_state->ucNonClockStateIndex * | |
1820 | power_info->info_4.ucNonClockSize)); | |
56278a8e AD |
1821 | for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) { |
1822 | if (rdev->flags & RADEON_IS_IGP) { | |
1823 | struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info = | |
1824 | (struct _ATOM_PPLIB_RS780_CLOCK_INFO *) | |
1825 | (mode_info->atom_context->bios + | |
1826 | data_offset + | |
1827 | le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + | |
1828 | (power_state->ucClockStateIndices[j] * | |
1829 | power_info->info_4.ucClockInfoSize)); | |
1830 | sclk = le16_to_cpu(clock_info->usLowEngineClockLow); | |
1831 | sclk |= clock_info->ucLowEngineClockHigh << 16; | |
1832 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
1833 | /* skip invalid modes */ | |
1834 | if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) | |
1835 | continue; | |
aa1df0f2 | 1836 | /* voltage works differently on IGPs */ |
56278a8e | 1837 | mode_index++; |
49f65982 AD |
1838 | } else if (ASIC_IS_DCE4(rdev)) { |
1839 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info = | |
1840 | (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *) | |
1841 | (mode_info->atom_context->bios + | |
1842 | data_offset + | |
1843 | le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + | |
1844 | (power_state->ucClockStateIndices[j] * | |
1845 | power_info->info_4.ucClockInfoSize)); | |
1846 | sclk = le16_to_cpu(clock_info->usEngineClockLow); | |
1847 | sclk |= clock_info->ucEngineClockHigh << 16; | |
1848 | mclk = le16_to_cpu(clock_info->usMemoryClockLow); | |
1849 | mclk |= clock_info->ucMemoryClockHigh << 16; | |
1850 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; | |
1851 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
1852 | /* skip invalid modes */ | |
1853 | if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || | |
1854 | (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) | |
1855 | continue; | |
49f65982 AD |
1856 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
1857 | VOLTAGE_SW; | |
1858 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | |
1859 | clock_info->usVDDC; | |
1860 | /* XXX usVDDCI */ | |
1861 | mode_index++; | |
56278a8e AD |
1862 | } else { |
1863 | struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info = | |
1864 | (struct _ATOM_PPLIB_R600_CLOCK_INFO *) | |
1865 | (mode_info->atom_context->bios + | |
1866 | data_offset + | |
1867 | le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + | |
1868 | (power_state->ucClockStateIndices[j] * | |
1869 | power_info->info_4.ucClockInfoSize)); | |
1870 | sclk = le16_to_cpu(clock_info->usEngineClockLow); | |
1871 | sclk |= clock_info->ucEngineClockHigh << 16; | |
1872 | mclk = le16_to_cpu(clock_info->usMemoryClockLow); | |
1873 | mclk |= clock_info->ucMemoryClockHigh << 16; | |
1874 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; | |
1875 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
1876 | /* skip invalid modes */ | |
1877 | if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || | |
1878 | (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) | |
1879 | continue; | |
56278a8e AD |
1880 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
1881 | VOLTAGE_SW; | |
1882 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | |
1883 | clock_info->usVDDC; | |
1884 | mode_index++; | |
1885 | } | |
1886 | } | |
1887 | rdev->pm.power_state[state_index].num_clock_modes = mode_index; | |
1888 | if (mode_index) { | |
845db70d | 1889 | misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); |
56278a8e | 1890 | misc2 = le16_to_cpu(non_clock_info->usClassification); |
79daedc9 AD |
1891 | rdev->pm.power_state[state_index].misc = misc; |
1892 | rdev->pm.power_state[state_index].misc2 = misc2; | |
1893 | rdev->pm.power_state[state_index].pcie_lanes = | |
845db70d RM |
1894 | ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> |
1895 | ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; | |
0ec0e74f AD |
1896 | switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { |
1897 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: | |
1898 | rdev->pm.power_state[state_index].type = | |
1899 | POWER_STATE_TYPE_BATTERY; | |
1900 | break; | |
1901 | case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: | |
1902 | rdev->pm.power_state[state_index].type = | |
1903 | POWER_STATE_TYPE_BALANCED; | |
1904 | break; | |
1905 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: | |
1906 | rdev->pm.power_state[state_index].type = | |
1907 | POWER_STATE_TYPE_PERFORMANCE; | |
1908 | break; | |
1909 | } | |
a48b9b4e AD |
1910 | rdev->pm.power_state[state_index].flags = 0; |
1911 | if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) | |
1912 | rdev->pm.power_state[state_index].flags |= | |
d7311171 | 1913 | RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
56278a8e | 1914 | if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { |
0ec0e74f AD |
1915 | rdev->pm.power_state[state_index].type = |
1916 | POWER_STATE_TYPE_DEFAULT; | |
a48b9b4e | 1917 | rdev->pm.default_power_state_index = state_index; |
56278a8e AD |
1918 | rdev->pm.power_state[state_index].default_clock_mode = |
1919 | &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; | |
c5e8ce61 AD |
1920 | /* patch the table values with the default slck/mclk from firmware info */ |
1921 | for (j = 0; j < mode_index; j++) { | |
1922 | rdev->pm.power_state[state_index].clock_info[j].mclk = | |
1923 | rdev->clock.default_mclk; | |
1924 | rdev->pm.power_state[state_index].clock_info[j].sclk = | |
1925 | rdev->clock.default_sclk; | |
1926 | if (vddc) | |
1927 | rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = | |
1928 | vddc; | |
1929 | } | |
56278a8e AD |
1930 | } |
1931 | state_index++; | |
1932 | } | |
1933 | } | |
d7311171 AD |
1934 | /* if multiple clock modes, mark the lowest as no display */ |
1935 | for (i = 0; i < state_index; i++) { | |
1936 | if (rdev->pm.power_state[i].num_clock_modes > 1) | |
1937 | rdev->pm.power_state[i].clock_info[0].flags |= | |
1938 | RADEON_PM_MODE_NO_DISPLAY; | |
1939 | } | |
02b17cc0 | 1940 | /* first mode is usually default */ |
a48b9b4e | 1941 | if (rdev->pm.default_power_state_index == -1) { |
02b17cc0 AD |
1942 | rdev->pm.power_state[0].type = |
1943 | POWER_STATE_TYPE_DEFAULT; | |
a48b9b4e | 1944 | rdev->pm.default_power_state_index = 0; |
02b17cc0 AD |
1945 | rdev->pm.power_state[0].default_clock_mode = |
1946 | &rdev->pm.power_state[0].clock_info[0]; | |
1947 | } | |
56278a8e AD |
1948 | } |
1949 | } else { | |
56278a8e | 1950 | /* add the default mode */ |
0ec0e74f AD |
1951 | rdev->pm.power_state[state_index].type = |
1952 | POWER_STATE_TYPE_DEFAULT; | |
56278a8e AD |
1953 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
1954 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; | |
1955 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; | |
1956 | rdev->pm.power_state[state_index].default_clock_mode = | |
1957 | &rdev->pm.power_state[state_index].clock_info[0]; | |
56278a8e | 1958 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
79daedc9 | 1959 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
a48b9b4e AD |
1960 | rdev->pm.default_power_state_index = state_index; |
1961 | rdev->pm.power_state[state_index].flags = 0; | |
56278a8e AD |
1962 | state_index++; |
1963 | } | |
02b17cc0 | 1964 | |
56278a8e | 1965 | rdev->pm.num_power_states = state_index; |
9038dfdf | 1966 | |
a48b9b4e AD |
1967 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
1968 | rdev->pm.current_clock_mode_index = 0; | |
4d60173f | 1969 | rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; |
771fe6b9 JG |
1970 | } |
1971 | ||
771fe6b9 | 1972 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) |
771fe6b9 | 1973 | { |
771fe6b9 JG |
1974 | DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; |
1975 | int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); | |
771fe6b9 JG |
1976 | |
1977 | args.ucEnable = enable; | |
1978 | ||
1979 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1980 | } | |
1981 | ||
7433874e RM |
1982 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) |
1983 | { | |
1984 | GET_ENGINE_CLOCK_PS_ALLOCATION args; | |
1985 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); | |
1986 | ||
1987 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1988 | return args.ulReturnEngineClock; | |
1989 | } | |
1990 | ||
1991 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) | |
1992 | { | |
1993 | GET_MEMORY_CLOCK_PS_ALLOCATION args; | |
1994 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); | |
1995 | ||
1996 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1997 | return args.ulReturnMemoryClock; | |
1998 | } | |
1999 | ||
771fe6b9 JG |
2000 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
2001 | uint32_t eng_clock) | |
2002 | { | |
2003 | SET_ENGINE_CLOCK_PS_ALLOCATION args; | |
2004 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); | |
2005 | ||
2006 | args.ulTargetEngineClock = eng_clock; /* 10 khz */ | |
2007 | ||
2008 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2009 | } | |
2010 | ||
2011 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, | |
2012 | uint32_t mem_clock) | |
2013 | { | |
2014 | SET_MEMORY_CLOCK_PS_ALLOCATION args; | |
2015 | int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); | |
2016 | ||
2017 | if (rdev->flags & RADEON_IS_IGP) | |
2018 | return; | |
2019 | ||
2020 | args.ulTargetMemoryClock = mem_clock; /* 10 khz */ | |
2021 | ||
2022 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2023 | } | |
2024 | ||
7ac9aa5a AD |
2025 | union set_voltage { |
2026 | struct _SET_VOLTAGE_PS_ALLOCATION alloc; | |
2027 | struct _SET_VOLTAGE_PARAMETERS v1; | |
2028 | struct _SET_VOLTAGE_PARAMETERS_V2 v2; | |
2029 | }; | |
2030 | ||
2031 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level) | |
2032 | { | |
2033 | union set_voltage args; | |
2034 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
2035 | u8 frev, crev, volt_index = level; | |
2036 | ||
2037 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
2038 | return; | |
2039 | ||
2040 | switch (crev) { | |
2041 | case 1: | |
2042 | args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC; | |
2043 | args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; | |
2044 | args.v1.ucVoltageIndex = volt_index; | |
2045 | break; | |
2046 | case 2: | |
2047 | args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC; | |
2048 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; | |
2049 | args.v2.usVoltageLevel = cpu_to_le16(level); | |
2050 | break; | |
2051 | default: | |
2052 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
2053 | return; | |
2054 | } | |
2055 | ||
2056 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
2057 | } | |
2058 | ||
2059 | ||
2060 | ||
771fe6b9 JG |
2061 | void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) |
2062 | { | |
2063 | struct radeon_device *rdev = dev->dev_private; | |
2064 | uint32_t bios_2_scratch, bios_6_scratch; | |
2065 | ||
2066 | if (rdev->family >= CHIP_R600) { | |
4ce001ab | 2067 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
771fe6b9 JG |
2068 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
2069 | } else { | |
4ce001ab | 2070 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
771fe6b9 JG |
2071 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
2072 | } | |
2073 | ||
2074 | /* let the bios control the backlight */ | |
2075 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; | |
2076 | ||
2077 | /* tell the bios not to handle mode switching */ | |
2078 | bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE); | |
2079 | ||
2080 | if (rdev->family >= CHIP_R600) { | |
2081 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); | |
2082 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
2083 | } else { | |
2084 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); | |
2085 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
2086 | } | |
2087 | ||
2088 | } | |
2089 | ||
f657c2a7 YZ |
2090 | void radeon_save_bios_scratch_regs(struct radeon_device *rdev) |
2091 | { | |
2092 | uint32_t scratch_reg; | |
2093 | int i; | |
2094 | ||
2095 | if (rdev->family >= CHIP_R600) | |
2096 | scratch_reg = R600_BIOS_0_SCRATCH; | |
2097 | else | |
2098 | scratch_reg = RADEON_BIOS_0_SCRATCH; | |
2099 | ||
2100 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) | |
2101 | rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); | |
2102 | } | |
2103 | ||
2104 | void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) | |
2105 | { | |
2106 | uint32_t scratch_reg; | |
2107 | int i; | |
2108 | ||
2109 | if (rdev->family >= CHIP_R600) | |
2110 | scratch_reg = R600_BIOS_0_SCRATCH; | |
2111 | else | |
2112 | scratch_reg = RADEON_BIOS_0_SCRATCH; | |
2113 | ||
2114 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) | |
2115 | WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); | |
2116 | } | |
2117 | ||
771fe6b9 JG |
2118 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
2119 | { | |
2120 | struct drm_device *dev = encoder->dev; | |
2121 | struct radeon_device *rdev = dev->dev_private; | |
2122 | uint32_t bios_6_scratch; | |
2123 | ||
2124 | if (rdev->family >= CHIP_R600) | |
2125 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); | |
2126 | else | |
2127 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
2128 | ||
2129 | if (lock) | |
2130 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; | |
2131 | else | |
2132 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; | |
2133 | ||
2134 | if (rdev->family >= CHIP_R600) | |
2135 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
2136 | else | |
2137 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
2138 | } | |
2139 | ||
2140 | /* at some point we may want to break this out into individual functions */ | |
2141 | void | |
2142 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |
2143 | struct drm_encoder *encoder, | |
2144 | bool connected) | |
2145 | { | |
2146 | struct drm_device *dev = connector->dev; | |
2147 | struct radeon_device *rdev = dev->dev_private; | |
2148 | struct radeon_connector *radeon_connector = | |
2149 | to_radeon_connector(connector); | |
2150 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2151 | uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; | |
2152 | ||
2153 | if (rdev->family >= CHIP_R600) { | |
2154 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
2155 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); | |
2156 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); | |
2157 | } else { | |
2158 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
2159 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); | |
2160 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
2161 | } | |
2162 | ||
2163 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && | |
2164 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { | |
2165 | if (connected) { | |
2166 | DRM_DEBUG("TV1 connected\n"); | |
2167 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; | |
2168 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; | |
2169 | } else { | |
2170 | DRM_DEBUG("TV1 disconnected\n"); | |
2171 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; | |
2172 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; | |
2173 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; | |
2174 | } | |
2175 | } | |
2176 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && | |
2177 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { | |
2178 | if (connected) { | |
2179 | DRM_DEBUG("CV connected\n"); | |
2180 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; | |
2181 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; | |
2182 | } else { | |
2183 | DRM_DEBUG("CV disconnected\n"); | |
2184 | bios_0_scratch &= ~ATOM_S0_CV_MASK; | |
2185 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; | |
2186 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; | |
2187 | } | |
2188 | } | |
2189 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && | |
2190 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { | |
2191 | if (connected) { | |
2192 | DRM_DEBUG("LCD1 connected\n"); | |
2193 | bios_0_scratch |= ATOM_S0_LCD1; | |
2194 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; | |
2195 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; | |
2196 | } else { | |
2197 | DRM_DEBUG("LCD1 disconnected\n"); | |
2198 | bios_0_scratch &= ~ATOM_S0_LCD1; | |
2199 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; | |
2200 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; | |
2201 | } | |
2202 | } | |
2203 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && | |
2204 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { | |
2205 | if (connected) { | |
2206 | DRM_DEBUG("CRT1 connected\n"); | |
2207 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; | |
2208 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; | |
2209 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; | |
2210 | } else { | |
2211 | DRM_DEBUG("CRT1 disconnected\n"); | |
2212 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; | |
2213 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; | |
2214 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; | |
2215 | } | |
2216 | } | |
2217 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && | |
2218 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { | |
2219 | if (connected) { | |
2220 | DRM_DEBUG("CRT2 connected\n"); | |
2221 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; | |
2222 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; | |
2223 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; | |
2224 | } else { | |
2225 | DRM_DEBUG("CRT2 disconnected\n"); | |
2226 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; | |
2227 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; | |
2228 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; | |
2229 | } | |
2230 | } | |
2231 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && | |
2232 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { | |
2233 | if (connected) { | |
2234 | DRM_DEBUG("DFP1 connected\n"); | |
2235 | bios_0_scratch |= ATOM_S0_DFP1; | |
2236 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; | |
2237 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; | |
2238 | } else { | |
2239 | DRM_DEBUG("DFP1 disconnected\n"); | |
2240 | bios_0_scratch &= ~ATOM_S0_DFP1; | |
2241 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; | |
2242 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; | |
2243 | } | |
2244 | } | |
2245 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && | |
2246 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { | |
2247 | if (connected) { | |
2248 | DRM_DEBUG("DFP2 connected\n"); | |
2249 | bios_0_scratch |= ATOM_S0_DFP2; | |
2250 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; | |
2251 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; | |
2252 | } else { | |
2253 | DRM_DEBUG("DFP2 disconnected\n"); | |
2254 | bios_0_scratch &= ~ATOM_S0_DFP2; | |
2255 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; | |
2256 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; | |
2257 | } | |
2258 | } | |
2259 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && | |
2260 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { | |
2261 | if (connected) { | |
2262 | DRM_DEBUG("DFP3 connected\n"); | |
2263 | bios_0_scratch |= ATOM_S0_DFP3; | |
2264 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; | |
2265 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; | |
2266 | } else { | |
2267 | DRM_DEBUG("DFP3 disconnected\n"); | |
2268 | bios_0_scratch &= ~ATOM_S0_DFP3; | |
2269 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; | |
2270 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; | |
2271 | } | |
2272 | } | |
2273 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && | |
2274 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { | |
2275 | if (connected) { | |
2276 | DRM_DEBUG("DFP4 connected\n"); | |
2277 | bios_0_scratch |= ATOM_S0_DFP4; | |
2278 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; | |
2279 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; | |
2280 | } else { | |
2281 | DRM_DEBUG("DFP4 disconnected\n"); | |
2282 | bios_0_scratch &= ~ATOM_S0_DFP4; | |
2283 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; | |
2284 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; | |
2285 | } | |
2286 | } | |
2287 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && | |
2288 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { | |
2289 | if (connected) { | |
2290 | DRM_DEBUG("DFP5 connected\n"); | |
2291 | bios_0_scratch |= ATOM_S0_DFP5; | |
2292 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; | |
2293 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; | |
2294 | } else { | |
2295 | DRM_DEBUG("DFP5 disconnected\n"); | |
2296 | bios_0_scratch &= ~ATOM_S0_DFP5; | |
2297 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; | |
2298 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | if (rdev->family >= CHIP_R600) { | |
2303 | WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); | |
2304 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); | |
2305 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
2306 | } else { | |
2307 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); | |
2308 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); | |
2309 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
2310 | } | |
2311 | } | |
2312 | ||
2313 | void | |
2314 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) | |
2315 | { | |
2316 | struct drm_device *dev = encoder->dev; | |
2317 | struct radeon_device *rdev = dev->dev_private; | |
2318 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2319 | uint32_t bios_3_scratch; | |
2320 | ||
2321 | if (rdev->family >= CHIP_R600) | |
2322 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); | |
2323 | else | |
2324 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); | |
2325 | ||
2326 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2327 | bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; | |
2328 | bios_3_scratch |= (crtc << 18); | |
2329 | } | |
2330 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2331 | bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; | |
2332 | bios_3_scratch |= (crtc << 24); | |
2333 | } | |
2334 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
2335 | bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; | |
2336 | bios_3_scratch |= (crtc << 16); | |
2337 | } | |
2338 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
2339 | bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; | |
2340 | bios_3_scratch |= (crtc << 20); | |
2341 | } | |
2342 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
2343 | bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; | |
2344 | bios_3_scratch |= (crtc << 17); | |
2345 | } | |
2346 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { | |
2347 | bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; | |
2348 | bios_3_scratch |= (crtc << 19); | |
2349 | } | |
2350 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { | |
2351 | bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; | |
2352 | bios_3_scratch |= (crtc << 23); | |
2353 | } | |
2354 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { | |
2355 | bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; | |
2356 | bios_3_scratch |= (crtc << 25); | |
2357 | } | |
2358 | ||
2359 | if (rdev->family >= CHIP_R600) | |
2360 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); | |
2361 | else | |
2362 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); | |
2363 | } | |
2364 | ||
2365 | void | |
2366 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) | |
2367 | { | |
2368 | struct drm_device *dev = encoder->dev; | |
2369 | struct radeon_device *rdev = dev->dev_private; | |
2370 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2371 | uint32_t bios_2_scratch; | |
2372 | ||
2373 | if (rdev->family >= CHIP_R600) | |
2374 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); | |
2375 | else | |
2376 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); | |
2377 | ||
2378 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2379 | if (on) | |
2380 | bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; | |
2381 | else | |
2382 | bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; | |
2383 | } | |
2384 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2385 | if (on) | |
2386 | bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; | |
2387 | else | |
2388 | bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; | |
2389 | } | |
2390 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
2391 | if (on) | |
2392 | bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; | |
2393 | else | |
2394 | bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; | |
2395 | } | |
2396 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
2397 | if (on) | |
2398 | bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; | |
2399 | else | |
2400 | bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; | |
2401 | } | |
2402 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
2403 | if (on) | |
2404 | bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; | |
2405 | else | |
2406 | bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; | |
2407 | } | |
2408 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { | |
2409 | if (on) | |
2410 | bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; | |
2411 | else | |
2412 | bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; | |
2413 | } | |
2414 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { | |
2415 | if (on) | |
2416 | bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; | |
2417 | else | |
2418 | bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; | |
2419 | } | |
2420 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { | |
2421 | if (on) | |
2422 | bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; | |
2423 | else | |
2424 | bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; | |
2425 | } | |
2426 | if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { | |
2427 | if (on) | |
2428 | bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; | |
2429 | else | |
2430 | bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; | |
2431 | } | |
2432 | if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { | |
2433 | if (on) | |
2434 | bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; | |
2435 | else | |
2436 | bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; | |
2437 | } | |
2438 | ||
2439 | if (rdev->family >= CHIP_R600) | |
2440 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); | |
2441 | else | |
2442 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); | |
2443 | } |