]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/radeon/radeon.h
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: IB locking dumps out a lockdep ordering issue
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47#include <asm/atomic.h>
48#include <linux/wait.h>
49#include <linux/list.h>
50#include <linux/kref.h>
51
52#include "radeon_mode.h"
53#include "radeon_reg.h"
771fe6b9
JG		 54
55/*
56 * Modules parameters.
57 */
58extern int radeon_no_wb;
59extern int radeon_modeset;
60extern int radeon_dynclks;
61extern int radeon_r4xx_atom;
62extern int radeon_agpmode;
63extern int radeon_vram_limit;
64extern int radeon_gart_size;
65extern int radeon_benchmarking;
ecc0b326 66extern int radeon_testing;
771fe6b9 67extern int radeon_connector_table;
4ce001ab 68extern int radeon_tv;
771fe6b9
JG		 69
70/*
71 * Copy from radeon_drv.h so we don't have to include both and have conflicting
72 * symbol;
73 */
74#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
75#define RADEON_IB_POOL_SIZE 16
76#define RADEON_DEBUGFS_MAX_NUM_FILES 32
77#define RADEONFB_CONN_LIMIT 4
78
79enum radeon_family {
80 CHIP_R100,
81 CHIP_RV100,
82 CHIP_RS100,
83 CHIP_RV200,
84 CHIP_RS200,
85 CHIP_R200,
86 CHIP_RV250,
87 CHIP_RS300,
88 CHIP_RV280,
89 CHIP_R300,
90 CHIP_R350,
91 CHIP_RV350,
92 CHIP_RV380,
93 CHIP_R420,
94 CHIP_R423,
95 CHIP_RV410,
96 CHIP_RS400,
97 CHIP_RS480,
98 CHIP_RS600,
99 CHIP_RS690,
100 CHIP_RS740,
101 CHIP_RV515,
102 CHIP_R520,
103 CHIP_RV530,
104 CHIP_RV560,
105 CHIP_RV570,
106 CHIP_R580,
107 CHIP_R600,
108 CHIP_RV610,
109 CHIP_RV630,
110 CHIP_RV620,
111 CHIP_RV635,
112 CHIP_RV670,
113 CHIP_RS780,
3ce0a23d 114 CHIP_RS880,
771fe6b9
JG		 115 CHIP_RV770,
116 CHIP_RV730,
117 CHIP_RV710,
3ce0a23d 118 CHIP_RV740,
771fe6b9
JG		 119 CHIP_LAST,
120};
121
122enum radeon_chip_flags {
123 RADEON_FAMILY_MASK = 0x0000ffffUL,
124 RADEON_FLAGS_MASK = 0xffff0000UL,
125 RADEON_IS_MOBILITY = 0x00010000UL,
126 RADEON_IS_IGP = 0x00020000UL,
127 RADEON_SINGLE_CRTC = 0x00040000UL,
128 RADEON_IS_AGP = 0x00080000UL,
129 RADEON_HAS_HIERZ = 0x00100000UL,
130 RADEON_IS_PCIE = 0x00200000UL,
131 RADEON_NEW_MEMMAP = 0x00400000UL,
132 RADEON_IS_PCI = 0x00800000UL,
133 RADEON_IS_IGPGART = 0x01000000UL,
134};
135
136
137/*
138 * Errata workarounds.
139 */
140enum radeon_pll_errata {
141 CHIP_ERRATA_R300_CG = 0x00000001,
142 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
143 CHIP_ERRATA_PLL_DELAY = 0x00000004
144};
145
146
147struct radeon_device;
148
149
150/*
151 * BIOS.
152 */
153bool radeon_get_bios(struct radeon_device *rdev);
154
3ce0a23d 155
771fe6b9 156/*
3ce0a23d 157 * Dummy page
771fe6b9 158 */
3ce0a23d
JG		 159struct radeon_dummy_page {
160 struct page *page;
161 dma_addr_t addr;
162};
163int radeon_dummy_page_init(struct radeon_device *rdev);
164void radeon_dummy_page_fini(struct radeon_device *rdev);
165
771fe6b9 166
3ce0a23d
JG		 167/*
168 * Clocks
169 */
771fe6b9
JG		 170struct radeon_clock {
171 struct radeon_pll p1pll;
172 struct radeon_pll p2pll;
173 struct radeon_pll spll;
174 struct radeon_pll mpll;
175 /* 10 Khz units */
176 uint32_t default_mclk;
177 uint32_t default_sclk;
178};
179
3ce0a23d 180
771fe6b9
JG		 181/*
182 * Fences.
183 */
184struct radeon_fence_driver {
185 uint32_t scratch_reg;
186 atomic_t seq;
187 uint32_t last_seq;
188 unsigned long count_timeout;
189 wait_queue_head_t queue;
190 rwlock_t lock;
191 struct list_head created;
192 struct list_head emited;
193 struct list_head signaled;
194};
195
196struct radeon_fence {
197 struct radeon_device *rdev;
198 struct kref kref;
199 struct list_head list;
200 /* protected by radeon_fence.lock */
201 uint32_t seq;
202 unsigned long timeout;
203 bool emited;
204 bool signaled;
205};
206
207int radeon_fence_driver_init(struct radeon_device *rdev);
208void radeon_fence_driver_fini(struct radeon_device *rdev);
209int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
210int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
211void radeon_fence_process(struct radeon_device *rdev);
212bool radeon_fence_signaled(struct radeon_fence *fence);
213int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
214int radeon_fence_wait_next(struct radeon_device *rdev);
215int radeon_fence_wait_last(struct radeon_device *rdev);
216struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
217void radeon_fence_unref(struct radeon_fence **fence);
218
e024e110
DA		 219/*
220 * Tiling registers
221 */
222struct radeon_surface_reg {
223 struct radeon_object *robj;
224};
225
226#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 227
228/*
229 * Radeon buffer.
230 */
231struct radeon_object;
232
233struct radeon_object_list {
234 struct list_head list;
235 struct radeon_object *robj;
236 uint64_t gpu_offset;
237 unsigned rdomain;
238 unsigned wdomain;
e024e110 239 uint32_t tiling_flags;
771fe6b9
JG		 240};
241
242int radeon_object_init(struct radeon_device *rdev);
243void radeon_object_fini(struct radeon_device *rdev);
244int radeon_object_create(struct radeon_device *rdev,
245 struct drm_gem_object *gobj,
246 unsigned long size,
247 bool kernel,
248 uint32_t domain,
249 bool interruptible,
250 struct radeon_object **robj_ptr);
251int radeon_object_kmap(struct radeon_object *robj, void **ptr);
252void radeon_object_kunmap(struct radeon_object *robj);
253void radeon_object_unref(struct radeon_object **robj);
254int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
255 uint64_t *gpu_addr);
256void radeon_object_unpin(struct radeon_object *robj);
257int radeon_object_wait(struct radeon_object *robj);
cefb87ef 258int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
771fe6b9
JG		 259int radeon_object_evict_vram(struct radeon_device *rdev);
260int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
261void radeon_object_force_delete(struct radeon_device *rdev);
262void radeon_object_list_add_object(struct radeon_object_list *lobj,
263 struct list_head *head);
264int radeon_object_list_validate(struct list_head *head, void *fence);
265void radeon_object_list_unvalidate(struct list_head *head);
266void radeon_object_list_clean(struct list_head *head);
267int radeon_object_fbdev_mmap(struct radeon_object *robj,
268 struct vm_area_struct *vma);
269unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 270void radeon_object_clear_surface_reg(struct radeon_object *robj);
271int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
272 bool force_drop);
273void radeon_object_set_tiling_flags(struct radeon_object *robj,
274 uint32_t tiling_flags, uint32_t pitch);
275void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
276void radeon_bo_move_notify(struct ttm_buffer_object *bo,
277 struct ttm_mem_reg *mem);
278void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 279/*
280 * GEM objects.
281 */
282struct radeon_gem {
283 struct list_head objects;
284};
285
286int radeon_gem_init(struct radeon_device *rdev);
287void radeon_gem_fini(struct radeon_device *rdev);
288int radeon_gem_object_create(struct radeon_device *rdev, int size,
289 int alignment, int initial_domain,
290 bool discardable, bool kernel,
291 bool interruptible,
292 struct drm_gem_object **obj);
293int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
294 uint64_t *gpu_addr);
295void radeon_gem_object_unpin(struct drm_gem_object *obj);
296
297
298/*
299 * GART structures, functions & helpers
300 */
301struct radeon_mc;
302
303struct radeon_gart_table_ram {
304 volatile uint32_t *ptr;
305};
306
307struct radeon_gart_table_vram {
308 struct radeon_object *robj;
309 volatile uint32_t *ptr;
310};
311
312union radeon_gart_table {
313 struct radeon_gart_table_ram ram;
314 struct radeon_gart_table_vram vram;
315};
316
317struct radeon_gart {
318 dma_addr_t table_addr;
319 unsigned num_gpu_pages;
320 unsigned num_cpu_pages;
321 unsigned table_size;
322 union radeon_gart_table table;
323 struct page **pages;
324 dma_addr_t *pages_addr;
325 bool ready;
326};
327
328int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
329void radeon_gart_table_ram_free(struct radeon_device *rdev);
330int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
331void radeon_gart_table_vram_free(struct radeon_device *rdev);
332int radeon_gart_init(struct radeon_device *rdev);
333void radeon_gart_fini(struct radeon_device *rdev);
334void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
335 int pages);
336int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
337 int pages, struct page **pagelist);
338
339
340/*
341 * GPU MC structures, functions & helpers
342 */
343struct radeon_mc {
344 resource_size_t aper_size;
345 resource_size_t aper_base;
346 resource_size_t agp_base;
7a50f01a
DA		 347 /* for some chips with <= 32MB we need to lie
348 * about vram size near mc fb location */
3ce0a23d
JG		 349 u64 mc_vram_size;
350 u64 gtt_location;
351 u64 gtt_size;
352 u64 gtt_start;
353 u64 gtt_end;
354 u64 vram_location;
355 u64 vram_start;
356 u64 vram_end;
771fe6b9 357 unsigned vram_width;
3ce0a23d 358 u64 real_vram_size;
771fe6b9
JG		 359 int vram_mtrr;
360 bool vram_is_ddr;
361};
362
363int radeon_mc_setup(struct radeon_device *rdev);
364
365
366/*
367 * GPU scratch registers structures, functions & helpers
368 */
369struct radeon_scratch {
370 unsigned num_reg;
371 bool free[32];
372 uint32_t reg[32];
373};
374
375int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
376void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
377
378
379/*
380 * IRQS.
381 */
382struct radeon_irq {
383 bool installed;
384 bool sw_int;
385 /* FIXME: use a define max crtc rather than hardcode it */
386 bool crtc_vblank_int[2];
387};
388
389int radeon_irq_kms_init(struct radeon_device *rdev);
390void radeon_irq_kms_fini(struct radeon_device *rdev);
391
392
393/*
394 * CP & ring.
395 */
396struct radeon_ib {
397 struct list_head list;
398 unsigned long idx;
399 uint64_t gpu_addr;
400 struct radeon_fence *fence;
401 volatile uint32_t *ptr;
402 uint32_t length_dw;
403};
404
ecb114a1
DA		 405/*
406 * locking -
407 * mutex protects scheduled_ibs, ready, alloc_bm
408 */
771fe6b9
JG		 409struct radeon_ib_pool {
410 struct mutex mutex;
411 struct radeon_object *robj;
412 struct list_head scheduled_ibs;
413 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
414 bool ready;
415 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
416};
417
418struct radeon_cp {
419 struct radeon_object *ring_obj;
420 volatile uint32_t *ring;
421 unsigned rptr;
422 unsigned wptr;
423 unsigned wptr_old;
424 unsigned ring_size;
425 unsigned ring_free_dw;
426 int count_dw;
427 uint64_t gpu_addr;
428 uint32_t align_mask;
429 uint32_t ptr_mask;
430 struct mutex mutex;
431 bool ready;
432};
433
3ce0a23d
JG		 434struct r600_blit {
435 struct radeon_object *shader_obj;
436 u64 shader_gpu_addr;
437 u32 vs_offset, ps_offset;
438 u32 state_offset;
439 u32 state_len;
440 u32 vb_used, vb_total;
441 struct radeon_ib *vb_ib;
442};
443
771fe6b9
JG		 444int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
445void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
446int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
447int radeon_ib_pool_init(struct radeon_device *rdev);
448void radeon_ib_pool_fini(struct radeon_device *rdev);
449int radeon_ib_test(struct radeon_device *rdev);
450/* Ring access between begin & end cannot sleep */
451void radeon_ring_free_size(struct radeon_device *rdev);
452int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
453void radeon_ring_unlock_commit(struct radeon_device *rdev);
454void radeon_ring_unlock_undo(struct radeon_device *rdev);
455int radeon_ring_test(struct radeon_device *rdev);
456int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
457void radeon_ring_fini(struct radeon_device *rdev);
458
459
460/*
461 * CS.
462 */
463struct radeon_cs_reloc {
464 struct drm_gem_object *gobj;
465 struct radeon_object *robj;
466 struct radeon_object_list lobj;
467 uint32_t handle;
468 uint32_t flags;
469};
470
471struct radeon_cs_chunk {
472 uint32_t chunk_id;
473 uint32_t length_dw;
474 uint32_t *kdata;
475};
476
477struct radeon_cs_parser {
478 struct radeon_device *rdev;
479 struct drm_file *filp;
480 /* chunks */
481 unsigned nchunks;
482 struct radeon_cs_chunk *chunks;
483 uint64_t *chunks_array;
484 /* IB */
485 unsigned idx;
486 /* relocations */
487 unsigned nrelocs;
488 struct radeon_cs_reloc *relocs;
489 struct radeon_cs_reloc **relocs_ptr;
490 struct list_head validated;
491 /* indices of various chunks */
492 int chunk_ib_idx;
493 int chunk_relocs_idx;
494 struct radeon_ib *ib;
495 void *track;
3ce0a23d 496 unsigned family;
771fe6b9
JG		 497};
498
499struct radeon_cs_packet {
500 unsigned idx;
501 unsigned type;
502 unsigned reg;
503 unsigned opcode;
504 int count;
505 unsigned one_reg_wr;
506};
507
508typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
509 struct radeon_cs_packet *pkt,
510 unsigned idx, unsigned reg);
511typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
512 struct radeon_cs_packet *pkt);
513
514
515/*
516 * AGP
517 */
518int radeon_agp_init(struct radeon_device *rdev);
519void radeon_agp_fini(struct radeon_device *rdev);
520
521
522/*
523 * Writeback
524 */
525struct radeon_wb {
526 struct radeon_object *wb_obj;
527 volatile uint32_t *wb;
528 uint64_t gpu_addr;
529};
530
c93bb85b
JG		 531/**
532 * struct radeon_pm - power management datas
533 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
534 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
535 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
536 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
537 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
538 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
539 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
540 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
541 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
542 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
543 * @needed_bandwidth: current bandwidth needs
544 *
545 * It keeps track of various data needed to take powermanagement decision.
546 * Bandwith need is used to determine minimun clock of the GPU and memory.
547 * Equation between gpu/memory clock and available bandwidth is hw dependent
548 * (type of memory, bus size, efficiency, ...)
549 */
550struct radeon_pm {
551 fixed20_12 max_bandwidth;
552 fixed20_12 igp_sideport_mclk;
553 fixed20_12 igp_system_mclk;
554 fixed20_12 igp_ht_link_clk;
555 fixed20_12 igp_ht_link_width;
556 fixed20_12 k8_bandwidth;
557 fixed20_12 sideport_bandwidth;
558 fixed20_12 ht_bandwidth;
559 fixed20_12 core_bandwidth;
560 fixed20_12 sclk;
561 fixed20_12 needed_bandwidth;
562};
563
771fe6b9
JG		 564
565/*
566 * Benchmarking
567 */
568void radeon_benchmark(struct radeon_device *rdev);
569
570
ecc0b326
MD		 571/*
572 * Testing
573 */
574void radeon_test_moves(struct radeon_device *rdev);
575
576
771fe6b9
JG		 577/*
578 * Debugfs
579 */
580int radeon_debugfs_add_files(struct radeon_device *rdev,
581 struct drm_info_list *files,
582 unsigned nfiles);
583int radeon_debugfs_fence_init(struct radeon_device *rdev);
584int r100_debugfs_rbbm_init(struct radeon_device *rdev);
585int r100_debugfs_cp_init(struct radeon_device *rdev);
586
587
588/*
589 * ASIC specific functions.
590 */
591struct radeon_asic {
068a117c 592 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 593 void (*fini)(struct radeon_device *rdev);
594 int (*resume)(struct radeon_device *rdev);
595 int (*suspend)(struct radeon_device *rdev);
771fe6b9
JG		 596 void (*errata)(struct radeon_device *rdev);
597 void (*vram_info)(struct radeon_device *rdev);
598 int (*gpu_reset)(struct radeon_device *rdev);
599 int (*mc_init)(struct radeon_device *rdev);
600 void (*mc_fini)(struct radeon_device *rdev);
601 int (*wb_init)(struct radeon_device *rdev);
602 void (*wb_fini)(struct radeon_device *rdev);
4aac0473
JG		 603 int (*gart_init)(struct radeon_device *rdev);
604 void (*gart_fini)(struct radeon_device *rdev);
771fe6b9
JG		 605 int (*gart_enable)(struct radeon_device *rdev);
606 void (*gart_disable)(struct radeon_device *rdev);
607 void (*gart_tlb_flush)(struct radeon_device *rdev);
608 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
609 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
610 void (*cp_fini)(struct radeon_device *rdev);
611 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 612 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 613 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 614 int (*ring_test)(struct radeon_device *rdev);
615 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
616 int (*ib_test)(struct radeon_device *rdev);
771fe6b9
JG		 617 int (*irq_set)(struct radeon_device *rdev);
618 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 619 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 620 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
621 int (*cs_parse)(struct radeon_cs_parser *p);
622 int (*copy_blit)(struct radeon_device *rdev,
623 uint64_t src_offset,
624 uint64_t dst_offset,
625 unsigned num_pages,
626 struct radeon_fence *fence);
627 int (*copy_dma)(struct radeon_device *rdev,
628 uint64_t src_offset,
629 uint64_t dst_offset,
630 unsigned num_pages,
631 struct radeon_fence *fence);
632 int (*copy)(struct radeon_device *rdev,
633 uint64_t src_offset,
634 uint64_t dst_offset,
635 unsigned num_pages,
636 struct radeon_fence *fence);
637 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
638 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
639 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
640 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 641 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
642 uint32_t tiling_flags, uint32_t pitch,
643 uint32_t offset, uint32_t obj_size);
644 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 645 void (*bandwidth_update)(struct radeon_device *rdev);
771fe6b9
JG		 646};
647
21f9a437
JG		 648/*
649 * Asic structures
650 */
551ebd83
DA		 651struct r100_asic {
652 const unsigned *reg_safe_bm;
653 unsigned reg_safe_bm_size;
654};
655
21f9a437
JG		 656struct r300_asic {
657 const unsigned *reg_safe_bm;
658 unsigned reg_safe_bm_size;
659};
660
661struct r600_asic {
662 unsigned max_pipes;
663 unsigned max_tile_pipes;
664 unsigned max_simds;
665 unsigned max_backends;
666 unsigned max_gprs;
667 unsigned max_threads;
668 unsigned max_stack_entries;
669 unsigned max_hw_contexts;
670 unsigned max_gs_threads;
671 unsigned sx_max_export_size;
672 unsigned sx_max_export_pos_size;
673 unsigned sx_max_export_smx_size;
674 unsigned sq_num_cf_insts;
675};
676
677struct rv770_asic {
678 unsigned max_pipes;
679 unsigned max_tile_pipes;
680 unsigned max_simds;
681 unsigned max_backends;
682 unsigned max_gprs;
683 unsigned max_threads;
684 unsigned max_stack_entries;
685 unsigned max_hw_contexts;
686 unsigned max_gs_threads;
687 unsigned sx_max_export_size;
688 unsigned sx_max_export_pos_size;
689 unsigned sx_max_export_smx_size;
690 unsigned sq_num_cf_insts;
691 unsigned sx_num_of_sets;
692 unsigned sc_prim_fifo_size;
693 unsigned sc_hiz_tile_fifo_size;
694 unsigned sc_earlyz_tile_fifo_fize;
695};
696
068a117c
JG		 697union radeon_asic_config {
698 struct r300_asic r300;
551ebd83 699 struct r100_asic r100;
3ce0a23d
JG		 700 struct r600_asic r600;
701 struct rv770_asic rv770;
068a117c
JG		 702};
703
771fe6b9
JG		 704
705/*
706 * IOCTL.
707 */
708int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
709 struct drm_file *filp);
710int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *filp);
712int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
713 struct drm_file *file_priv);
714int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
715 struct drm_file *file_priv);
716int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
717 struct drm_file *file_priv);
718int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
719 struct drm_file *file_priv);
720int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
721 struct drm_file *filp);
722int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *filp);
724int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
725 struct drm_file *filp);
726int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
727 struct drm_file *filp);
728int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 729int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
730 struct drm_file *filp);
731int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
732 struct drm_file *filp);
771fe6b9
JG		 733
734
735/*
736 * Core structure, functions and helpers.
737 */
738typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
739typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
740
741struct radeon_device {
9f022ddf 742 struct device *dev;
771fe6b9
JG		 743 struct drm_device *ddev;
744 struct pci_dev *pdev;
745 /* ASIC */
068a117c 746 union radeon_asic_config config;
771fe6b9
JG		 747 enum radeon_family family;
748 unsigned long flags;
749 int usec_timeout;
750 enum radeon_pll_errata pll_errata;
751 int num_gb_pipes;
f779b3e5 752 int num_z_pipes;
771fe6b9
JG		 753 int disp_priority;
754 /* BIOS */
755 uint8_t *bios;
756 bool is_atom_bios;
757 uint16_t bios_header_start;
758 struct radeon_object *stollen_vga_memory;
759 struct fb_info *fbdev_info;
760 struct radeon_object *fbdev_robj;
761 struct radeon_framebuffer *fbdev_rfb;
762 /* Register mmio */
4c9bc75c
DA		 763 resource_size_t rmmio_base;
764 resource_size_t rmmio_size;
771fe6b9 765 void *rmmio;
771fe6b9
JG		 766 radeon_rreg_t mc_rreg;
767 radeon_wreg_t mc_wreg;
768 radeon_rreg_t pll_rreg;
769 radeon_wreg_t pll_wreg;
de1b2898 770 uint32_t pcie_reg_mask;
771fe6b9
JG		 771 radeon_rreg_t pciep_rreg;
772 radeon_wreg_t pciep_wreg;
773 struct radeon_clock clock;
774 struct radeon_mc mc;
775 struct radeon_gart gart;
776 struct radeon_mode_info mode_info;
777 struct radeon_scratch scratch;
778 struct radeon_mman mman;
779 struct radeon_fence_driver fence_drv;
780 struct radeon_cp cp;
781 struct radeon_ib_pool ib_pool;
782 struct radeon_irq irq;
783 struct radeon_asic *asic;
784 struct radeon_gem gem;
c93bb85b 785 struct radeon_pm pm;
771fe6b9
JG		 786 struct mutex cs_mutex;
787 struct radeon_wb wb;
3ce0a23d 788 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 789 bool gpu_lockup;
790 bool shutdown;
791 bool suspend;
ad49f501 792 bool need_dma32;
3ce0a23d 793 bool new_init_path;
e024e110 794 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 795 const struct firmware *me_fw; /* all family ME firmware */
796 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
797 struct r600_blit r600_blit;
771fe6b9
JG		 798};
799
800int radeon_device_init(struct radeon_device *rdev,
801 struct drm_device *ddev,
802 struct pci_dev *pdev,
803 uint32_t flags);
804void radeon_device_fini(struct radeon_device *rdev);
805int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
806
3ce0a23d
JG		 807/* r600 blit */
808int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
809void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
810void r600_kms_blit_copy(struct radeon_device *rdev,
811 u64 src_gpu_addr, u64 dst_gpu_addr,
812 int size_bytes);
813
de1b2898
DA		 814static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
815{
816 if (reg < 0x10000)
817 return readl(((void __iomem *)rdev->rmmio) + reg);
818 else {
819 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
820 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
821 }
822}
823
824static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
825{
826 if (reg < 0x10000)
827 writel(v, ((void __iomem *)rdev->rmmio) + reg);
828 else {
829 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
830 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
831 }
832}
833
771fe6b9
JG		 834
835/*
836 * Registers read & write functions.
837 */
838#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
839#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 840#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 841#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 842#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 843#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
844#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
845#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
846#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
847#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
848#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 849#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
850#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 851#define WREG32_P(reg, val, mask) \
852 do { \
853 uint32_t tmp_ = RREG32(reg); \
854 tmp_ &= (mask); \
855 tmp_ |= ((val) & ~(mask)); \
856 WREG32(reg, tmp_); \
857 } while (0)
858#define WREG32_PLL_P(reg, val, mask) \
859 do { \
860 uint32_t tmp_ = RREG32_PLL(reg); \
861 tmp_ &= (mask); \
862 tmp_ |= ((val) & ~(mask)); \
863 WREG32_PLL(reg, tmp_); \
864 } while (0)
3ce0a23d 865#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 866
de1b2898
DA		 867/*
868 * Indirect registers accessor
869 */
870static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
871{
872 uint32_t r;
873
874 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
875 r = RREG32(RADEON_PCIE_DATA);
876 return r;
877}
878
879static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
880{
881 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
882 WREG32(RADEON_PCIE_DATA, (v));
883}
884
771fe6b9
JG		 885void r100_pll_errata_after_index(struct radeon_device *rdev);
886
887
888/*
889 * ASICs helpers.
890 */
b995e433
DA		 891#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
892 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 893#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
894 (rdev->family == CHIP_RV200) || \
895 (rdev->family == CHIP_RS100) || \
896 (rdev->family == CHIP_RS200) || \
897 (rdev->family == CHIP_RV250) || \
898 (rdev->family == CHIP_RV280) || \
899 (rdev->family == CHIP_RS300))
900#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
901 (rdev->family == CHIP_RV350) || \
902 (rdev->family == CHIP_R350) || \
903 (rdev->family == CHIP_RV380) || \
904 (rdev->family == CHIP_R420) || \
905 (rdev->family == CHIP_R423) || \
906 (rdev->family == CHIP_RV410) || \
907 (rdev->family == CHIP_RS400) || \
908 (rdev->family == CHIP_RS480))
909#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
910#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
911#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
912
913
914/*
915 * BIOS helpers.
916 */
917#define RBIOS8(i) (rdev->bios[i])
918#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
919#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
920
921int radeon_combios_init(struct radeon_device *rdev);
922void radeon_combios_fini(struct radeon_device *rdev);
923int radeon_atombios_init(struct radeon_device *rdev);
924void radeon_atombios_fini(struct radeon_device *rdev);
925
926
927/*
928 * RING helpers.
929 */
771fe6b9
JG		 930static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
931{
932#if DRM_DEBUG_CODE
933 if (rdev->cp.count_dw <= 0) {
934 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
935 }
936#endif
937 rdev->cp.ring[rdev->cp.wptr++] = v;
938 rdev->cp.wptr &= rdev->cp.ptr_mask;
939 rdev->cp.count_dw--;
940 rdev->cp.ring_free_dw--;
941}
942
943
944/*
945 * ASICs macro.
946 */
068a117c 947#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 948#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
949#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
950#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9
JG		 951#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
952#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
953#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
954#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
955#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
956#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
957#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
958#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
4aac0473
JG		 959#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
960#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
771fe6b9
JG		 961#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
962#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
963#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
964#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
965#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
966#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
967#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
3ce0a23d 968#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 969#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 970#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
971#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
972#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
771fe6b9
JG		 973#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
974#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 975#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 976#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
977#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
978#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
979#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
980#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
981#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
982#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
983#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 984#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
985#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 986#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
771fe6b9 987
6cf8a3f5 988/* Common functions */
4aac0473 989extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 990extern int radeon_modeset_init(struct radeon_device *rdev);
991extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 992extern bool radeon_card_posted(struct radeon_device *rdev);
21f9a437
JG		 993extern int radeon_clocks_init(struct radeon_device *rdev);
994extern void radeon_clocks_fini(struct radeon_device *rdev);
995extern void radeon_scratch_init(struct radeon_device *rdev);
996extern void radeon_surface_init(struct radeon_device *rdev);
997extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
6cf8a3f5 998
a18d7ea1 999/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 1000struct r100_mc_save {
1001 u32 GENMO_WT;
1002 u32 CRTC_EXT_CNTL;
1003 u32 CRTC_GEN_CNTL;
1004 u32 CRTC2_GEN_CNTL;
1005 u32 CUR_OFFSET;
1006 u32 CUR2_OFFSET;
1007};
1008extern void r100_cp_disable(struct radeon_device *rdev);
1009extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1010extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 1011extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 1012extern int r100_pci_gart_init(struct radeon_device *rdev);
1013extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 1014extern int r100_pci_gart_enable(struct radeon_device *rdev);
1015extern void r100_pci_gart_disable(struct radeon_device *rdev);
1016extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 1017extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1018extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1019extern void r100_ib_fini(struct radeon_device *rdev);
1020extern int r100_ib_init(struct radeon_device *rdev);
1021extern void r100_irq_disable(struct radeon_device *rdev);
1022extern int r100_irq_set(struct radeon_device *rdev);
1023extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1024extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1025extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1026extern void r100_wb_disable(struct radeon_device *rdev);
1027extern void r100_wb_fini(struct radeon_device *rdev);
1028extern int r100_wb_init(struct radeon_device *rdev);
1029
1030/* r300,r350,rv350,rv370,rv380 */
1031extern void r300_set_reg_safe(struct radeon_device *rdev);
1032extern void r300_mc_program(struct radeon_device *rdev);
1033extern void r300_vram_info(struct radeon_device *rdev);
4aac0473
JG		 1034extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1035extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1036extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1037extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1038
905b6822 1039/* r420,r423,rv410 */
21f9a437
JG		 1040extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1041extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1042extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
905b6822 1043
21f9a437
JG		 1044/* rv515 */
1045extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1046
1047/* rs690, rs740 */
1048extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1049 struct drm_display_mode *mode1,
1050 struct drm_display_mode *mode2);
1051
1052/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1053extern bool r600_card_posted(struct radeon_device *rdev);
1054extern void r600_cp_stop(struct radeon_device *rdev);
1055extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1056extern int r600_cp_resume(struct radeon_device *rdev);
1057extern int r600_count_pipe_bits(uint32_t val);
1058extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1059extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1060extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1061extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1062extern int r600_ib_test(struct radeon_device *rdev);
1063extern int r600_ring_test(struct radeon_device *rdev);
1064extern int r600_wb_init(struct radeon_device *rdev);
1065extern void r600_wb_fini(struct radeon_device *rdev);
1066extern void r600_scratch_init(struct radeon_device *rdev);
1067extern int r600_blit_init(struct radeon_device *rdev);
1068extern void r600_blit_fini(struct radeon_device *rdev);
1069extern int r600_cp_init_microcode(struct radeon_device *rdev);
1070
771fe6b9 1071#endif
Clone of davem's net-next-2.6 tree