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CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47#include <asm/atomic.h>
48#include <linux/wait.h>
49#include <linux/list.h>
50#include <linux/kref.h>
51
52#include "radeon_mode.h"
53#include "radeon_reg.h"
068a117c 54#include "r300.h"
771fe6b9
JG		 55
56/*
57 * Modules parameters.
58 */
59extern int radeon_no_wb;
60extern int radeon_modeset;
61extern int radeon_dynclks;
62extern int radeon_r4xx_atom;
63extern int radeon_agpmode;
64extern int radeon_vram_limit;
65extern int radeon_gart_size;
66extern int radeon_benchmarking;
67extern int radeon_connector_table;
68
69/*
70 * Copy from radeon_drv.h so we don't have to include both and have conflicting
71 * symbol;
72 */
73#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
74#define RADEON_IB_POOL_SIZE 16
75#define RADEON_DEBUGFS_MAX_NUM_FILES 32
76#define RADEONFB_CONN_LIMIT 4
77
78enum radeon_family {
79 CHIP_R100,
80 CHIP_RV100,
81 CHIP_RS100,
82 CHIP_RV200,
83 CHIP_RS200,
84 CHIP_R200,
85 CHIP_RV250,
86 CHIP_RS300,
87 CHIP_RV280,
88 CHIP_R300,
89 CHIP_R350,
90 CHIP_RV350,
91 CHIP_RV380,
92 CHIP_R420,
93 CHIP_R423,
94 CHIP_RV410,
95 CHIP_RS400,
96 CHIP_RS480,
97 CHIP_RS600,
98 CHIP_RS690,
99 CHIP_RS740,
100 CHIP_RV515,
101 CHIP_R520,
102 CHIP_RV530,
103 CHIP_RV560,
104 CHIP_RV570,
105 CHIP_R580,
106 CHIP_R600,
107 CHIP_RV610,
108 CHIP_RV630,
109 CHIP_RV620,
110 CHIP_RV635,
111 CHIP_RV670,
112 CHIP_RS780,
113 CHIP_RV770,
114 CHIP_RV730,
115 CHIP_RV710,
116 CHIP_LAST,
117};
118
119enum radeon_chip_flags {
120 RADEON_FAMILY_MASK = 0x0000ffffUL,
121 RADEON_FLAGS_MASK = 0xffff0000UL,
122 RADEON_IS_MOBILITY = 0x00010000UL,
123 RADEON_IS_IGP = 0x00020000UL,
124 RADEON_SINGLE_CRTC = 0x00040000UL,
125 RADEON_IS_AGP = 0x00080000UL,
126 RADEON_HAS_HIERZ = 0x00100000UL,
127 RADEON_IS_PCIE = 0x00200000UL,
128 RADEON_NEW_MEMMAP = 0x00400000UL,
129 RADEON_IS_PCI = 0x00800000UL,
130 RADEON_IS_IGPGART = 0x01000000UL,
131};
132
133
134/*
135 * Errata workarounds.
136 */
137enum radeon_pll_errata {
138 CHIP_ERRATA_R300_CG = 0x00000001,
139 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
140 CHIP_ERRATA_PLL_DELAY = 0x00000004
141};
142
143
144struct radeon_device;
145
146
147/*
148 * BIOS.
149 */
150bool radeon_get_bios(struct radeon_device *rdev);
151
152/*
153 * Clocks
154 */
155
156struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
159 struct radeon_pll spll;
160 struct radeon_pll mpll;
161 /* 10 Khz units */
162 uint32_t default_mclk;
163 uint32_t default_sclk;
164};
165
166/*
167 * Fences.
168 */
169struct radeon_fence_driver {
170 uint32_t scratch_reg;
171 atomic_t seq;
172 uint32_t last_seq;
173 unsigned long count_timeout;
174 wait_queue_head_t queue;
175 rwlock_t lock;
176 struct list_head created;
177 struct list_head emited;
178 struct list_head signaled;
179};
180
181struct radeon_fence {
182 struct radeon_device *rdev;
183 struct kref kref;
184 struct list_head list;
185 /* protected by radeon_fence.lock */
186 uint32_t seq;
187 unsigned long timeout;
188 bool emited;
189 bool signaled;
190};
191
192int radeon_fence_driver_init(struct radeon_device *rdev);
193void radeon_fence_driver_fini(struct radeon_device *rdev);
194int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
195int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
196void radeon_fence_process(struct radeon_device *rdev);
197bool radeon_fence_signaled(struct radeon_fence *fence);
198int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
199int radeon_fence_wait_next(struct radeon_device *rdev);
200int radeon_fence_wait_last(struct radeon_device *rdev);
201struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
202void radeon_fence_unref(struct radeon_fence **fence);
203
e024e110
DA		 204/*
205 * Tiling registers
206 */
207struct radeon_surface_reg {
208 struct radeon_object *robj;
209};
210
211#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 212
213/*
214 * Radeon buffer.
215 */
216struct radeon_object;
217
218struct radeon_object_list {
219 struct list_head list;
220 struct radeon_object *robj;
221 uint64_t gpu_offset;
222 unsigned rdomain;
223 unsigned wdomain;
e024e110 224 uint32_t tiling_flags;
771fe6b9
JG		 225};
226
227int radeon_object_init(struct radeon_device *rdev);
228void radeon_object_fini(struct radeon_device *rdev);
229int radeon_object_create(struct radeon_device *rdev,
230 struct drm_gem_object *gobj,
231 unsigned long size,
232 bool kernel,
233 uint32_t domain,
234 bool interruptible,
235 struct radeon_object **robj_ptr);
236int radeon_object_kmap(struct radeon_object *robj, void **ptr);
237void radeon_object_kunmap(struct radeon_object *robj);
238void radeon_object_unref(struct radeon_object **robj);
239int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
240 uint64_t *gpu_addr);
241void radeon_object_unpin(struct radeon_object *robj);
242int radeon_object_wait(struct radeon_object *robj);
243int radeon_object_evict_vram(struct radeon_device *rdev);
244int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
245void radeon_object_force_delete(struct radeon_device *rdev);
246void radeon_object_list_add_object(struct radeon_object_list *lobj,
247 struct list_head *head);
248int radeon_object_list_validate(struct list_head *head, void *fence);
249void radeon_object_list_unvalidate(struct list_head *head);
250void radeon_object_list_clean(struct list_head *head);
251int radeon_object_fbdev_mmap(struct radeon_object *robj,
252 struct vm_area_struct *vma);
253unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 254void radeon_object_clear_surface_reg(struct radeon_object *robj);
255int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
256 bool force_drop);
257void radeon_object_set_tiling_flags(struct radeon_object *robj,
258 uint32_t tiling_flags, uint32_t pitch);
259void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
260void radeon_bo_move_notify(struct ttm_buffer_object *bo,
261 struct ttm_mem_reg *mem);
262void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 263/*
264 * GEM objects.
265 */
266struct radeon_gem {
267 struct list_head objects;
268};
269
270int radeon_gem_init(struct radeon_device *rdev);
271void radeon_gem_fini(struct radeon_device *rdev);
272int radeon_gem_object_create(struct radeon_device *rdev, int size,
273 int alignment, int initial_domain,
274 bool discardable, bool kernel,
275 bool interruptible,
276 struct drm_gem_object **obj);
277int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
278 uint64_t *gpu_addr);
279void radeon_gem_object_unpin(struct drm_gem_object *obj);
280
281
282/*
283 * GART structures, functions & helpers
284 */
285struct radeon_mc;
286
287struct radeon_gart_table_ram {
288 volatile uint32_t *ptr;
289};
290
291struct radeon_gart_table_vram {
292 struct radeon_object *robj;
293 volatile uint32_t *ptr;
294};
295
296union radeon_gart_table {
297 struct radeon_gart_table_ram ram;
298 struct radeon_gart_table_vram vram;
299};
300
301struct radeon_gart {
302 dma_addr_t table_addr;
303 unsigned num_gpu_pages;
304 unsigned num_cpu_pages;
305 unsigned table_size;
306 union radeon_gart_table table;
307 struct page **pages;
308 dma_addr_t *pages_addr;
309 bool ready;
310};
311
312int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
313void radeon_gart_table_ram_free(struct radeon_device *rdev);
314int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
315void radeon_gart_table_vram_free(struct radeon_device *rdev);
316int radeon_gart_init(struct radeon_device *rdev);
317void radeon_gart_fini(struct radeon_device *rdev);
318void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
319 int pages);
320int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
321 int pages, struct page **pagelist);
322
323
324/*
325 * GPU MC structures, functions & helpers
326 */
327struct radeon_mc {
328 resource_size_t aper_size;
329 resource_size_t aper_base;
330 resource_size_t agp_base;
331 unsigned gtt_location;
332 unsigned gtt_size;
333 unsigned vram_location;
334 unsigned vram_size;
335 unsigned vram_width;
336 int vram_mtrr;
337 bool vram_is_ddr;
338};
339
340int radeon_mc_setup(struct radeon_device *rdev);
341
342
343/*
344 * GPU scratch registers structures, functions & helpers
345 */
346struct radeon_scratch {
347 unsigned num_reg;
348 bool free[32];
349 uint32_t reg[32];
350};
351
352int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
353void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
354
355
356/*
357 * IRQS.
358 */
359struct radeon_irq {
360 bool installed;
361 bool sw_int;
362 /* FIXME: use a define max crtc rather than hardcode it */
363 bool crtc_vblank_int[2];
364};
365
366int radeon_irq_kms_init(struct radeon_device *rdev);
367void radeon_irq_kms_fini(struct radeon_device *rdev);
368
369
370/*
371 * CP & ring.
372 */
373struct radeon_ib {
374 struct list_head list;
375 unsigned long idx;
376 uint64_t gpu_addr;
377 struct radeon_fence *fence;
378 volatile uint32_t *ptr;
379 uint32_t length_dw;
380};
381
382struct radeon_ib_pool {
383 struct mutex mutex;
384 struct radeon_object *robj;
385 struct list_head scheduled_ibs;
386 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
387 bool ready;
388 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
389};
390
391struct radeon_cp {
392 struct radeon_object *ring_obj;
393 volatile uint32_t *ring;
394 unsigned rptr;
395 unsigned wptr;
396 unsigned wptr_old;
397 unsigned ring_size;
398 unsigned ring_free_dw;
399 int count_dw;
400 uint64_t gpu_addr;
401 uint32_t align_mask;
402 uint32_t ptr_mask;
403 struct mutex mutex;
404 bool ready;
405};
406
407int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
408void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
409int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
410int radeon_ib_pool_init(struct radeon_device *rdev);
411void radeon_ib_pool_fini(struct radeon_device *rdev);
412int radeon_ib_test(struct radeon_device *rdev);
413/* Ring access between begin & end cannot sleep */
414void radeon_ring_free_size(struct radeon_device *rdev);
415int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
416void radeon_ring_unlock_commit(struct radeon_device *rdev);
417void radeon_ring_unlock_undo(struct radeon_device *rdev);
418int radeon_ring_test(struct radeon_device *rdev);
419int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
420void radeon_ring_fini(struct radeon_device *rdev);
421
422
423/*
424 * CS.
425 */
426struct radeon_cs_reloc {
427 struct drm_gem_object *gobj;
428 struct radeon_object *robj;
429 struct radeon_object_list lobj;
430 uint32_t handle;
431 uint32_t flags;
432};
433
434struct radeon_cs_chunk {
435 uint32_t chunk_id;
436 uint32_t length_dw;
437 uint32_t *kdata;
438};
439
440struct radeon_cs_parser {
441 struct radeon_device *rdev;
442 struct drm_file *filp;
443 /* chunks */
444 unsigned nchunks;
445 struct radeon_cs_chunk *chunks;
446 uint64_t *chunks_array;
447 /* IB */
448 unsigned idx;
449 /* relocations */
450 unsigned nrelocs;
451 struct radeon_cs_reloc *relocs;
452 struct radeon_cs_reloc **relocs_ptr;
453 struct list_head validated;
454 /* indices of various chunks */
455 int chunk_ib_idx;
456 int chunk_relocs_idx;
457 struct radeon_ib *ib;
458 void *track;
459};
460
461struct radeon_cs_packet {
462 unsigned idx;
463 unsigned type;
464 unsigned reg;
465 unsigned opcode;
466 int count;
467 unsigned one_reg_wr;
468};
469
470typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
471 struct radeon_cs_packet *pkt,
472 unsigned idx, unsigned reg);
473typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
474 struct radeon_cs_packet *pkt);
475
476
477/*
478 * AGP
479 */
480int radeon_agp_init(struct radeon_device *rdev);
481void radeon_agp_fini(struct radeon_device *rdev);
482
483
484/*
485 * Writeback
486 */
487struct radeon_wb {
488 struct radeon_object *wb_obj;
489 volatile uint32_t *wb;
490 uint64_t gpu_addr;
491};
492
493
494/*
495 * Benchmarking
496 */
497void radeon_benchmark(struct radeon_device *rdev);
498
499
500/*
501 * Debugfs
502 */
503int radeon_debugfs_add_files(struct radeon_device *rdev,
504 struct drm_info_list *files,
505 unsigned nfiles);
506int radeon_debugfs_fence_init(struct radeon_device *rdev);
507int r100_debugfs_rbbm_init(struct radeon_device *rdev);
508int r100_debugfs_cp_init(struct radeon_device *rdev);
509
510
511/*
512 * ASIC specific functions.
513 */
514struct radeon_asic {
068a117c 515 int (*init)(struct radeon_device *rdev);
771fe6b9
JG		 516 void (*errata)(struct radeon_device *rdev);
517 void (*vram_info)(struct radeon_device *rdev);
518 int (*gpu_reset)(struct radeon_device *rdev);
519 int (*mc_init)(struct radeon_device *rdev);
520 void (*mc_fini)(struct radeon_device *rdev);
521 int (*wb_init)(struct radeon_device *rdev);
522 void (*wb_fini)(struct radeon_device *rdev);
523 int (*gart_enable)(struct radeon_device *rdev);
524 void (*gart_disable)(struct radeon_device *rdev);
525 void (*gart_tlb_flush)(struct radeon_device *rdev);
526 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
527 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
528 void (*cp_fini)(struct radeon_device *rdev);
529 void (*cp_disable)(struct radeon_device *rdev);
530 void (*ring_start)(struct radeon_device *rdev);
531 int (*irq_set)(struct radeon_device *rdev);
532 int (*irq_process)(struct radeon_device *rdev);
533 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
534 int (*cs_parse)(struct radeon_cs_parser *p);
535 int (*copy_blit)(struct radeon_device *rdev,
536 uint64_t src_offset,
537 uint64_t dst_offset,
538 unsigned num_pages,
539 struct radeon_fence *fence);
540 int (*copy_dma)(struct radeon_device *rdev,
541 uint64_t src_offset,
542 uint64_t dst_offset,
543 unsigned num_pages,
544 struct radeon_fence *fence);
545 int (*copy)(struct radeon_device *rdev,
546 uint64_t src_offset,
547 uint64_t dst_offset,
548 unsigned num_pages,
549 struct radeon_fence *fence);
550 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
551 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
552 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
553 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 554
555 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
556 uint32_t tiling_flags, uint32_t pitch,
557 uint32_t offset, uint32_t obj_size);
558 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
771fe6b9
JG		 559};
560
068a117c
JG		 561union radeon_asic_config {
562 struct r300_asic r300;
563};
564
2a0f8918
DA		 565/* r100 */
566void r100_vram_init_sizes(struct radeon_device *rdev);
771fe6b9
JG		 567
568/*
569 * IOCTL.
570 */
571int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
572 struct drm_file *filp);
573int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
574 struct drm_file *filp);
575int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
576 struct drm_file *file_priv);
577int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
578 struct drm_file *file_priv);
579int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
580 struct drm_file *file_priv);
581int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
582 struct drm_file *file_priv);
583int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
584 struct drm_file *filp);
585int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
586 struct drm_file *filp);
587int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
588 struct drm_file *filp);
589int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
590 struct drm_file *filp);
591int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 592int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
593 struct drm_file *filp);
594int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
595 struct drm_file *filp);
771fe6b9
JG		 596
597
598/*
599 * Core structure, functions and helpers.
600 */
601typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
602typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
603
604struct radeon_device {
605 struct drm_device *ddev;
606 struct pci_dev *pdev;
607 /* ASIC */
068a117c 608 union radeon_asic_config config;
771fe6b9
JG		 609 enum radeon_family family;
610 unsigned long flags;
611 int usec_timeout;
612 enum radeon_pll_errata pll_errata;
613 int num_gb_pipes;
614 int disp_priority;
615 /* BIOS */
616 uint8_t *bios;
617 bool is_atom_bios;
618 uint16_t bios_header_start;
619 struct radeon_object *stollen_vga_memory;
620 struct fb_info *fbdev_info;
621 struct radeon_object *fbdev_robj;
622 struct radeon_framebuffer *fbdev_rfb;
623 /* Register mmio */
4c9bc75c
DA		 624 resource_size_t rmmio_base;
625 resource_size_t rmmio_size;
771fe6b9
JG		 626 void *rmmio;
627 radeon_rreg_t mm_rreg;
628 radeon_wreg_t mm_wreg;
629 radeon_rreg_t mc_rreg;
630 radeon_wreg_t mc_wreg;
631 radeon_rreg_t pll_rreg;
632 radeon_wreg_t pll_wreg;
633 radeon_rreg_t pcie_rreg;
634 radeon_wreg_t pcie_wreg;
635 radeon_rreg_t pciep_rreg;
636 radeon_wreg_t pciep_wreg;
637 struct radeon_clock clock;
638 struct radeon_mc mc;
639 struct radeon_gart gart;
640 struct radeon_mode_info mode_info;
641 struct radeon_scratch scratch;
642 struct radeon_mman mman;
643 struct radeon_fence_driver fence_drv;
644 struct radeon_cp cp;
645 struct radeon_ib_pool ib_pool;
646 struct radeon_irq irq;
647 struct radeon_asic *asic;
648 struct radeon_gem gem;
649 struct mutex cs_mutex;
650 struct radeon_wb wb;
651 bool gpu_lockup;
652 bool shutdown;
653 bool suspend;
ad49f501 654 bool need_dma32;
e024e110 655 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
771fe6b9
JG		 656};
657
658int radeon_device_init(struct radeon_device *rdev,
659 struct drm_device *ddev,
660 struct pci_dev *pdev,
661 uint32_t flags);
662void radeon_device_fini(struct radeon_device *rdev);
663int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
664
665
666/*
667 * Registers read & write functions.
668 */
669#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
670#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
671#define RREG32(reg) rdev->mm_rreg(rdev, (reg))
672#define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v))
673#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
674#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
675#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
676#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
677#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
678#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
679#define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg))
680#define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v))
681#define WREG32_P(reg, val, mask) \
682 do { \
683 uint32_t tmp_ = RREG32(reg); \
684 tmp_ &= (mask); \
685 tmp_ |= ((val) & ~(mask)); \
686 WREG32(reg, tmp_); \
687 } while (0)
688#define WREG32_PLL_P(reg, val, mask) \
689 do { \
690 uint32_t tmp_ = RREG32_PLL(reg); \
691 tmp_ &= (mask); \
692 tmp_ |= ((val) & ~(mask)); \
693 WREG32_PLL(reg, tmp_); \
694 } while (0)
695
696void r100_pll_errata_after_index(struct radeon_device *rdev);
697
698
699/*
700 * ASICs helpers.
701 */
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DA		 702#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
703 (rdev->pdev->device == 0x5969))
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JG		 704#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
705 (rdev->family == CHIP_RV200) || \
706 (rdev->family == CHIP_RS100) || \
707 (rdev->family == CHIP_RS200) || \
708 (rdev->family == CHIP_RV250) || \
709 (rdev->family == CHIP_RV280) || \
710 (rdev->family == CHIP_RS300))
711#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
712 (rdev->family == CHIP_RV350) || \
713 (rdev->family == CHIP_R350) || \
714 (rdev->family == CHIP_RV380) || \
715 (rdev->family == CHIP_R420) || \
716 (rdev->family == CHIP_R423) || \
717 (rdev->family == CHIP_RV410) || \
718 (rdev->family == CHIP_RS400) || \
719 (rdev->family == CHIP_RS480))
720#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
721#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
722#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
723
724
725/*
726 * BIOS helpers.
727 */
728#define RBIOS8(i) (rdev->bios[i])
729#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
730#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
731
732int radeon_combios_init(struct radeon_device *rdev);
733void radeon_combios_fini(struct radeon_device *rdev);
734int radeon_atombios_init(struct radeon_device *rdev);
735void radeon_atombios_fini(struct radeon_device *rdev);
736
737
738/*
739 * RING helpers.
740 */
741#define CP_PACKET0 0x00000000
742#define PACKET0_BASE_INDEX_SHIFT 0
743#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
744#define PACKET0_COUNT_SHIFT 16
745#define PACKET0_COUNT_MASK (0x3fff << 16)
746#define CP_PACKET1 0x40000000
747#define CP_PACKET2 0x80000000
748#define PACKET2_PAD_SHIFT 0
749#define PACKET2_PAD_MASK (0x3fffffff << 0)
750#define CP_PACKET3 0xC0000000
751#define PACKET3_IT_OPCODE_SHIFT 8
752#define PACKET3_IT_OPCODE_MASK (0xff << 8)
753#define PACKET3_COUNT_SHIFT 16
754#define PACKET3_COUNT_MASK (0x3fff << 16)
755/* PACKET3 op code */
756#define PACKET3_NOP 0x10
757#define PACKET3_3D_DRAW_VBUF 0x28
758#define PACKET3_3D_DRAW_IMMD 0x29
759#define PACKET3_3D_DRAW_INDX 0x2A
760#define PACKET3_3D_LOAD_VBPNTR 0x2F
761#define PACKET3_INDX_BUFFER 0x33
762#define PACKET3_3D_DRAW_VBUF_2 0x34
763#define PACKET3_3D_DRAW_IMMD_2 0x35
764#define PACKET3_3D_DRAW_INDX_2 0x36
765#define PACKET3_BITBLT_MULTI 0x9B
766
767#define PACKET0(reg, n) (CP_PACKET0 | \
768 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
769 REG_SET(PACKET0_COUNT, (n)))
770#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
771#define PACKET3(op, n) (CP_PACKET3 | \
772 REG_SET(PACKET3_IT_OPCODE, (op)) | \
773 REG_SET(PACKET3_COUNT, (n)))
774
775#define PACKET_TYPE0 0
776#define PACKET_TYPE1 1
777#define PACKET_TYPE2 2
778#define PACKET_TYPE3 3
779
780#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
781#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
782#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
783#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
784#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
785
786static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
787{
788#if DRM_DEBUG_CODE
789 if (rdev->cp.count_dw <= 0) {
790 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
791 }
792#endif
793 rdev->cp.ring[rdev->cp.wptr++] = v;
794 rdev->cp.wptr &= rdev->cp.ptr_mask;
795 rdev->cp.count_dw--;
796 rdev->cp.ring_free_dw--;
797}
798
799
800/*
801 * ASICs macro.
802 */
068a117c 803#define radeon_init(rdev) (rdev)->asic->init((rdev))
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JG		 804#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
805#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
806#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
807#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
808#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
809#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
810#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
811#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
812#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
813#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
814#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
815#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
816#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
817#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
818#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
819#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
820#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
821#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
822#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
823#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
824#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
825#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
826#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
827#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
828#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
829#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
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DA		 830#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
831#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
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JG		 832
833#endif
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