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drivers/gpu/drm/radeon/radeon_combios.c: fix warning
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
771fe6b9
JG		 63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
c2142715 73#include "radeon_family.h"
771fe6b9
JG		 74#include "radeon_mode.h"
75#include "radeon_reg.h"
771fe6b9
JG		 76
77/*
78 * Modules parameters.
79 */
80extern int radeon_no_wb;
81extern int radeon_modeset;
82extern int radeon_dynclks;
83extern int radeon_r4xx_atom;
84extern int radeon_agpmode;
85extern int radeon_vram_limit;
86extern int radeon_gart_size;
87extern int radeon_benchmarking;
ecc0b326 88extern int radeon_testing;
771fe6b9 89extern int radeon_connector_table;
4ce001ab 90extern int radeon_tv;
b27b6375 91extern int radeon_new_pll;
dafc3bd5 92extern int radeon_audio;
771fe6b9
JG		 93
94/*
95 * Copy from radeon_drv.h so we don't have to include both and have conflicting
96 * symbol;
97 */
98#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
99#define RADEON_IB_POOL_SIZE 16
100#define RADEON_DEBUGFS_MAX_NUM_FILES 32
101#define RADEONFB_CONN_LIMIT 4
f657c2a7 102#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 103
771fe6b9
JG		 104/*
105 * Errata workarounds.
106 */
107enum radeon_pll_errata {
108 CHIP_ERRATA_R300_CG = 0x00000001,
109 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
110 CHIP_ERRATA_PLL_DELAY = 0x00000004
111};
112
113
114struct radeon_device;
115
116
117/*
118 * BIOS.
119 */
120bool radeon_get_bios(struct radeon_device *rdev);
121
3ce0a23d 122
771fe6b9 123/*
3ce0a23d 124 * Dummy page
771fe6b9 125 */
3ce0a23d
JG		 126struct radeon_dummy_page {
127 struct page *page;
128 dma_addr_t addr;
129};
130int radeon_dummy_page_init(struct radeon_device *rdev);
131void radeon_dummy_page_fini(struct radeon_device *rdev);
132
771fe6b9 133
3ce0a23d
JG		 134/*
135 * Clocks
136 */
771fe6b9
JG		 137struct radeon_clock {
138 struct radeon_pll p1pll;
139 struct radeon_pll p2pll;
140 struct radeon_pll spll;
141 struct radeon_pll mpll;
142 /* 10 Khz units */
143 uint32_t default_mclk;
144 uint32_t default_sclk;
145};
146
7433874e
RM		 147/*
148 * Power management
149 */
150int radeon_pm_init(struct radeon_device *rdev);
3ce0a23d 151
771fe6b9
JG		 152/*
153 * Fences.
154 */
155struct radeon_fence_driver {
156 uint32_t scratch_reg;
157 atomic_t seq;
158 uint32_t last_seq;
159 unsigned long count_timeout;
160 wait_queue_head_t queue;
161 rwlock_t lock;
162 struct list_head created;
163 struct list_head emited;
164 struct list_head signaled;
0a0c7596 165 bool initialized;
771fe6b9
JG		 166};
167
168struct radeon_fence {
169 struct radeon_device *rdev;
170 struct kref kref;
171 struct list_head list;
172 /* protected by radeon_fence.lock */
173 uint32_t seq;
174 unsigned long timeout;
175 bool emited;
176 bool signaled;
177};
178
179int radeon_fence_driver_init(struct radeon_device *rdev);
180void radeon_fence_driver_fini(struct radeon_device *rdev);
181int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
182int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
183void radeon_fence_process(struct radeon_device *rdev);
184bool radeon_fence_signaled(struct radeon_fence *fence);
185int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
186int radeon_fence_wait_next(struct radeon_device *rdev);
187int radeon_fence_wait_last(struct radeon_device *rdev);
188struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
189void radeon_fence_unref(struct radeon_fence **fence);
190
e024e110
DA		 191/*
192 * Tiling registers
193 */
194struct radeon_surface_reg {
4c788679 195 struct radeon_bo *bo;
e024e110
DA		 196};
197
198#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 199
200/*
4c788679 201 * TTM.
771fe6b9 202 */
4c788679
JG		 203struct radeon_mman {
204 struct ttm_bo_global_ref bo_global_ref;
205 struct ttm_global_reference mem_global_ref;
4c788679 206 struct ttm_bo_device bdev;
0a0c7596
JG		 207 bool mem_global_referenced;
208 bool initialized;
4c788679
JG		 209};
210
211struct radeon_bo {
212 /* Protected by gem.mutex */
213 struct list_head list;
214 /* Protected by tbo.reserved */
312ea8da
JG		 215 u32 placements[3];
216 struct ttm_placement placement;
4c788679
JG		 217 struct ttm_buffer_object tbo;
218 struct ttm_bo_kmap_obj kmap;
219 unsigned pin_count;
220 void *kptr;
221 u32 tiling_flags;
222 u32 pitch;
223 int surface_reg;
224 /* Constant after initialization */
225 struct radeon_device *rdev;
226 struct drm_gem_object *gobj;
227};
771fe6b9 228
4c788679 229struct radeon_bo_list {
771fe6b9 230 struct list_head list;
4c788679 231 struct radeon_bo *bo;
771fe6b9
JG		 232 uint64_t gpu_offset;
233 unsigned rdomain;
234 unsigned wdomain;
4c788679 235 u32 tiling_flags;
771fe6b9
JG		 236};
237
771fe6b9
JG		 238/*
239 * GEM objects.
240 */
241struct radeon_gem {
4c788679 242 struct mutex mutex;
771fe6b9
JG		 243 struct list_head objects;
244};
245
246int radeon_gem_init(struct radeon_device *rdev);
247void radeon_gem_fini(struct radeon_device *rdev);
248int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 249 int alignment, int initial_domain,
250 bool discardable, bool kernel,
251 struct drm_gem_object **obj);
771fe6b9
JG		 252int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
253 uint64_t *gpu_addr);
254void radeon_gem_object_unpin(struct drm_gem_object *obj);
255
256
257/*
258 * GART structures, functions & helpers
259 */
260struct radeon_mc;
261
262struct radeon_gart_table_ram {
263 volatile uint32_t *ptr;
264};
265
266struct radeon_gart_table_vram {
4c788679 267 struct radeon_bo *robj;
771fe6b9
JG		 268 volatile uint32_t *ptr;
269};
270
271union radeon_gart_table {
272 struct radeon_gart_table_ram ram;
273 struct radeon_gart_table_vram vram;
274};
275
a77f1718
MT		 276#define RADEON_GPU_PAGE_SIZE 4096
277
771fe6b9
JG		 278struct radeon_gart {
279 dma_addr_t table_addr;
280 unsigned num_gpu_pages;
281 unsigned num_cpu_pages;
282 unsigned table_size;
283 union radeon_gart_table table;
284 struct page **pages;
285 dma_addr_t *pages_addr;
286 bool ready;
287};
288
289int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
290void radeon_gart_table_ram_free(struct radeon_device *rdev);
291int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
292void radeon_gart_table_vram_free(struct radeon_device *rdev);
293int radeon_gart_init(struct radeon_device *rdev);
294void radeon_gart_fini(struct radeon_device *rdev);
295void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
296 int pages);
297int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
298 int pages, struct page **pagelist);
299
300
301/*
302 * GPU MC structures, functions & helpers
303 */
304struct radeon_mc {
305 resource_size_t aper_size;
306 resource_size_t aper_base;
307 resource_size_t agp_base;
7a50f01a
DA		 308 /* for some chips with <= 32MB we need to lie
309 * about vram size near mc fb location */
3ce0a23d
JG		 310 u64 mc_vram_size;
311 u64 gtt_location;
312 u64 gtt_size;
313 u64 gtt_start;
314 u64 gtt_end;
315 u64 vram_location;
316 u64 vram_start;
317 u64 vram_end;
771fe6b9 318 unsigned vram_width;
3ce0a23d 319 u64 real_vram_size;
771fe6b9
JG		 320 int vram_mtrr;
321 bool vram_is_ddr;
06b6476d 322 bool igp_sideport_enabled;
771fe6b9
JG		 323};
324
325int radeon_mc_setup(struct radeon_device *rdev);
06b6476d
AD		 326bool radeon_combios_sideport_present(struct radeon_device *rdev);
327bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 328
329/*
330 * GPU scratch registers structures, functions & helpers
331 */
332struct radeon_scratch {
333 unsigned num_reg;
334 bool free[32];
335 uint32_t reg[32];
336};
337
338int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
339void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
340
341
342/*
343 * IRQS.
344 */
345struct radeon_irq {
346 bool installed;
347 bool sw_int;
348 /* FIXME: use a define max crtc rather than hardcode it */
349 bool crtc_vblank_int[2];
b500f680
AD		 350 /* FIXME: use defines for max hpd/dacs */
351 bool hpd[6];
1614f8b1
DA		 352 spinlock_t sw_lock;
353 int sw_refcount;
771fe6b9
JG		 354};
355
356int radeon_irq_kms_init(struct radeon_device *rdev);
357void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 358void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
359void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
771fe6b9
JG		 360
361/*
362 * CP & ring.
363 */
364struct radeon_ib {
365 struct list_head list;
366 unsigned long idx;
367 uint64_t gpu_addr;
368 struct radeon_fence *fence;
513bcb46 369 uint32_t *ptr;
771fe6b9
JG		 370 uint32_t length_dw;
371};
372
ecb114a1
DA		 373/*
374 * locking -
375 * mutex protects scheduled_ibs, ready, alloc_bm
376 */
771fe6b9
JG		 377struct radeon_ib_pool {
378 struct mutex mutex;
4c788679 379 struct radeon_bo *robj;
771fe6b9
JG		 380 struct list_head scheduled_ibs;
381 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
382 bool ready;
383 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
384};
385
386struct radeon_cp {
4c788679 387 struct radeon_bo *ring_obj;
771fe6b9
JG		 388 volatile uint32_t *ring;
389 unsigned rptr;
390 unsigned wptr;
391 unsigned wptr_old;
392 unsigned ring_size;
393 unsigned ring_free_dw;
394 int count_dw;
395 uint64_t gpu_addr;
396 uint32_t align_mask;
397 uint32_t ptr_mask;
398 struct mutex mutex;
399 bool ready;
400};
401
d8f60cfc
AD		 402/*
403 * R6xx+ IH ring
404 */
405struct r600_ih {
4c788679 406 struct radeon_bo *ring_obj;
d8f60cfc
AD		 407 volatile uint32_t *ring;
408 unsigned rptr;
409 unsigned wptr;
410 unsigned wptr_old;
411 unsigned ring_size;
412 uint64_t gpu_addr;
d8f60cfc
AD		 413 uint32_t ptr_mask;
414 spinlock_t lock;
415 bool enabled;
416};
417
3ce0a23d 418struct r600_blit {
ff82f052 419 struct mutex mutex;
4c788679 420 struct radeon_bo *shader_obj;
3ce0a23d
JG		 421 u64 shader_gpu_addr;
422 u32 vs_offset, ps_offset;
423 u32 state_offset;
424 u32 state_len;
425 u32 vb_used, vb_total;
426 struct radeon_ib *vb_ib;
427};
428
771fe6b9
JG		 429int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
430void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
431int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
432int radeon_ib_pool_init(struct radeon_device *rdev);
433void radeon_ib_pool_fini(struct radeon_device *rdev);
434int radeon_ib_test(struct radeon_device *rdev);
435/* Ring access between begin & end cannot sleep */
436void radeon_ring_free_size(struct radeon_device *rdev);
437int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
438void radeon_ring_unlock_commit(struct radeon_device *rdev);
439void radeon_ring_unlock_undo(struct radeon_device *rdev);
440int radeon_ring_test(struct radeon_device *rdev);
441int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
442void radeon_ring_fini(struct radeon_device *rdev);
443
444
445/*
446 * CS.
447 */
448struct radeon_cs_reloc {
449 struct drm_gem_object *gobj;
4c788679
JG		 450 struct radeon_bo *robj;
451 struct radeon_bo_list lobj;
771fe6b9
JG		 452 uint32_t handle;
453 uint32_t flags;
454};
455
456struct radeon_cs_chunk {
457 uint32_t chunk_id;
458 uint32_t length_dw;
513bcb46
DA		 459 int kpage_idx[2];
460 uint32_t *kpage[2];
771fe6b9 461 uint32_t *kdata;
513bcb46
DA		 462 void __user *user_ptr;
463 int last_copied_page;
464 int last_page_index;
771fe6b9
JG		 465};
466
467struct radeon_cs_parser {
c8c15ff1 468 struct device *dev;
771fe6b9
JG		 469 struct radeon_device *rdev;
470 struct drm_file *filp;
471 /* chunks */
472 unsigned nchunks;
473 struct radeon_cs_chunk *chunks;
474 uint64_t *chunks_array;
475 /* IB */
476 unsigned idx;
477 /* relocations */
478 unsigned nrelocs;
479 struct radeon_cs_reloc *relocs;
480 struct radeon_cs_reloc **relocs_ptr;
481 struct list_head validated;
482 /* indices of various chunks */
483 int chunk_ib_idx;
484 int chunk_relocs_idx;
485 struct radeon_ib *ib;
486 void *track;
3ce0a23d 487 unsigned family;
513bcb46 488 int parser_error;
771fe6b9
JG		 489};
490
513bcb46
DA		 491extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
492extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
493
494
495static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
496{
497 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
498 u32 pg_idx, pg_offset;
499 u32 idx_value = 0;
500 int new_page;
501
502 pg_idx = (idx * 4) / PAGE_SIZE;
503 pg_offset = (idx * 4) % PAGE_SIZE;
504
505 if (ibc->kpage_idx[0] == pg_idx)
506 return ibc->kpage[0][pg_offset/4];
507 if (ibc->kpage_idx[1] == pg_idx)
508 return ibc->kpage[1][pg_offset/4];
509
510 new_page = radeon_cs_update_pages(p, pg_idx);
511 if (new_page < 0) {
512 p->parser_error = new_page;
513 return 0;
514 }
515
516 idx_value = ibc->kpage[new_page][pg_offset/4];
517 return idx_value;
518}
519
771fe6b9
JG		 520struct radeon_cs_packet {
521 unsigned idx;
522 unsigned type;
523 unsigned reg;
524 unsigned opcode;
525 int count;
526 unsigned one_reg_wr;
527};
528
529typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
530 struct radeon_cs_packet *pkt,
531 unsigned idx, unsigned reg);
532typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
533 struct radeon_cs_packet *pkt);
534
535
536/*
537 * AGP
538 */
539int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 540void radeon_agp_resume(struct radeon_device *rdev);
771fe6b9
JG		 541void radeon_agp_fini(struct radeon_device *rdev);
542
543
544/*
545 * Writeback
546 */
547struct radeon_wb {
4c788679 548 struct radeon_bo *wb_obj;
771fe6b9
JG		 549 volatile uint32_t *wb;
550 uint64_t gpu_addr;
551};
552
c93bb85b
JG		 553/**
554 * struct radeon_pm - power management datas
555 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
556 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
557 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
558 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
559 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
560 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
561 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
562 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
563 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
564 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
565 * @needed_bandwidth: current bandwidth needs
566 *
567 * It keeps track of various data needed to take powermanagement decision.
568 * Bandwith need is used to determine minimun clock of the GPU and memory.
569 * Equation between gpu/memory clock and available bandwidth is hw dependent
570 * (type of memory, bus size, efficiency, ...)
571 */
572struct radeon_pm {
573 fixed20_12 max_bandwidth;
574 fixed20_12 igp_sideport_mclk;
575 fixed20_12 igp_system_mclk;
576 fixed20_12 igp_ht_link_clk;
577 fixed20_12 igp_ht_link_width;
578 fixed20_12 k8_bandwidth;
579 fixed20_12 sideport_bandwidth;
580 fixed20_12 ht_bandwidth;
581 fixed20_12 core_bandwidth;
582 fixed20_12 sclk;
583 fixed20_12 needed_bandwidth;
584};
585
771fe6b9
JG		 586
587/*
588 * Benchmarking
589 */
590void radeon_benchmark(struct radeon_device *rdev);
591
592
ecc0b326
MD		 593/*
594 * Testing
595 */
596void radeon_test_moves(struct radeon_device *rdev);
597
598
771fe6b9
JG		 599/*
600 * Debugfs
601 */
602int radeon_debugfs_add_files(struct radeon_device *rdev,
603 struct drm_info_list *files,
604 unsigned nfiles);
605int radeon_debugfs_fence_init(struct radeon_device *rdev);
606int r100_debugfs_rbbm_init(struct radeon_device *rdev);
607int r100_debugfs_cp_init(struct radeon_device *rdev);
608
609
610/*
611 * ASIC specific functions.
612 */
613struct radeon_asic {
068a117c 614 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 615 void (*fini)(struct radeon_device *rdev);
616 int (*resume)(struct radeon_device *rdev);
617 int (*suspend)(struct radeon_device *rdev);
28d52043 618 void (*vga_set_state)(struct radeon_device *rdev, bool state);
771fe6b9 619 int (*gpu_reset)(struct radeon_device *rdev);
771fe6b9
JG		 620 void (*gart_tlb_flush)(struct radeon_device *rdev);
621 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
622 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
623 void (*cp_fini)(struct radeon_device *rdev);
624 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 625 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 626 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 627 int (*ring_test)(struct radeon_device *rdev);
628 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 629 int (*irq_set)(struct radeon_device *rdev);
630 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 631 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 632 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
633 int (*cs_parse)(struct radeon_cs_parser *p);
634 int (*copy_blit)(struct radeon_device *rdev,
635 uint64_t src_offset,
636 uint64_t dst_offset,
637 unsigned num_pages,
638 struct radeon_fence *fence);
639 int (*copy_dma)(struct radeon_device *rdev,
640 uint64_t src_offset,
641 uint64_t dst_offset,
642 unsigned num_pages,
643 struct radeon_fence *fence);
644 int (*copy)(struct radeon_device *rdev,
645 uint64_t src_offset,
646 uint64_t dst_offset,
647 unsigned num_pages,
648 struct radeon_fence *fence);
7433874e 649 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 650 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 651 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9
JG		 652 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
653 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
654 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 655 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
656 uint32_t tiling_flags, uint32_t pitch,
657 uint32_t offset, uint32_t obj_size);
658 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 659 void (*bandwidth_update)(struct radeon_device *rdev);
429770b3
AD		 660 void (*hpd_init)(struct radeon_device *rdev);
661 void (*hpd_fini)(struct radeon_device *rdev);
662 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
663 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
062b389c
JG		 664 /* ioctl hw specific callback. Some hw might want to perform special
665 * operation on specific ioctl. For instance on wait idle some hw
666 * might want to perform and HDP flush through MMIO as it seems that
667 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
668 * through ring.
669 */
670 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
771fe6b9
JG		 671};
672
21f9a437
JG		 673/*
674 * Asic structures
675 */
551ebd83
DA		 676struct r100_asic {
677 const unsigned *reg_safe_bm;
678 unsigned reg_safe_bm_size;
cafe6609 679 u32 hdp_cntl;
551ebd83
DA		 680};
681
21f9a437
JG		 682struct r300_asic {
683 const unsigned *reg_safe_bm;
684 unsigned reg_safe_bm_size;
62cdc0c2 685 u32 resync_scratch;
cafe6609 686 u32 hdp_cntl;
21f9a437
JG		 687};
688
689struct r600_asic {
690 unsigned max_pipes;
691 unsigned max_tile_pipes;
692 unsigned max_simds;
693 unsigned max_backends;
694 unsigned max_gprs;
695 unsigned max_threads;
696 unsigned max_stack_entries;
697 unsigned max_hw_contexts;
698 unsigned max_gs_threads;
699 unsigned sx_max_export_size;
700 unsigned sx_max_export_pos_size;
701 unsigned sx_max_export_smx_size;
702 unsigned sq_num_cf_insts;
703};
704
705struct rv770_asic {
706 unsigned max_pipes;
707 unsigned max_tile_pipes;
708 unsigned max_simds;
709 unsigned max_backends;
710 unsigned max_gprs;
711 unsigned max_threads;
712 unsigned max_stack_entries;
713 unsigned max_hw_contexts;
714 unsigned max_gs_threads;
715 unsigned sx_max_export_size;
716 unsigned sx_max_export_pos_size;
717 unsigned sx_max_export_smx_size;
718 unsigned sq_num_cf_insts;
719 unsigned sx_num_of_sets;
720 unsigned sc_prim_fifo_size;
721 unsigned sc_hiz_tile_fifo_size;
722 unsigned sc_earlyz_tile_fifo_fize;
723};
724
068a117c
JG		 725union radeon_asic_config {
726 struct r300_asic r300;
551ebd83 727 struct r100_asic r100;
3ce0a23d
JG		 728 struct r600_asic r600;
729 struct rv770_asic rv770;
068a117c
JG		 730};
731
771fe6b9
JG		 732
733/*
734 * IOCTL.
735 */
736int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
737 struct drm_file *filp);
738int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
739 struct drm_file *filp);
740int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
741 struct drm_file *file_priv);
742int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
743 struct drm_file *file_priv);
744int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
745 struct drm_file *file_priv);
746int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
747 struct drm_file *file_priv);
748int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
749 struct drm_file *filp);
750int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
751 struct drm_file *filp);
752int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
753 struct drm_file *filp);
754int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
755 struct drm_file *filp);
756int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 757int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
758 struct drm_file *filp);
759int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
760 struct drm_file *filp);
771fe6b9
JG		 761
762
763/*
764 * Core structure, functions and helpers.
765 */
766typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
767typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
768
769struct radeon_device {
9f022ddf 770 struct device *dev;
771fe6b9
JG		 771 struct drm_device *ddev;
772 struct pci_dev *pdev;
773 /* ASIC */
068a117c 774 union radeon_asic_config config;
771fe6b9
JG		 775 enum radeon_family family;
776 unsigned long flags;
777 int usec_timeout;
778 enum radeon_pll_errata pll_errata;
779 int num_gb_pipes;
f779b3e5 780 int num_z_pipes;
771fe6b9
JG		 781 int disp_priority;
782 /* BIOS */
783 uint8_t *bios;
784 bool is_atom_bios;
785 uint16_t bios_header_start;
4c788679 786 struct radeon_bo *stollen_vga_memory;
771fe6b9 787 struct fb_info *fbdev_info;
4c788679 788 struct radeon_bo *fbdev_rbo;
771fe6b9
JG		 789 struct radeon_framebuffer *fbdev_rfb;
790 /* Register mmio */
4c9bc75c
DA		 791 resource_size_t rmmio_base;
792 resource_size_t rmmio_size;
771fe6b9 793 void *rmmio;
771fe6b9
JG		 794 radeon_rreg_t mc_rreg;
795 radeon_wreg_t mc_wreg;
796 radeon_rreg_t pll_rreg;
797 radeon_wreg_t pll_wreg;
de1b2898 798 uint32_t pcie_reg_mask;
771fe6b9
JG		 799 radeon_rreg_t pciep_rreg;
800 radeon_wreg_t pciep_wreg;
801 struct radeon_clock clock;
802 struct radeon_mc mc;
803 struct radeon_gart gart;
804 struct radeon_mode_info mode_info;
805 struct radeon_scratch scratch;
806 struct radeon_mman mman;
807 struct radeon_fence_driver fence_drv;
808 struct radeon_cp cp;
809 struct radeon_ib_pool ib_pool;
810 struct radeon_irq irq;
811 struct radeon_asic *asic;
812 struct radeon_gem gem;
c93bb85b 813 struct radeon_pm pm;
f657c2a7 814 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 815 struct mutex cs_mutex;
816 struct radeon_wb wb;
3ce0a23d 817 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 818 bool gpu_lockup;
819 bool shutdown;
820 bool suspend;
ad49f501 821 bool need_dma32;
733289c2 822 bool accel_working;
e024e110 823 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 824 const struct firmware *me_fw; /* all family ME firmware */
825 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 826 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
3ce0a23d 827 struct r600_blit r600_blit;
3e5cb98d 828 int msi_enabled; /* msi enabled */
d8f60cfc 829 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2
AD		 830 struct workqueue_struct *wq;
831 struct work_struct hotplug_work;
dafc3bd5
CK		 832
833 /* audio stuff */
834 struct timer_list audio_timer;
835 int audio_channels;
836 int audio_rate;
837 int audio_bits_per_sample;
838 uint8_t audio_status_bits;
839 uint8_t audio_category_code;
771fe6b9
JG		 840};
841
842int radeon_device_init(struct radeon_device *rdev,
843 struct drm_device *ddev,
844 struct pci_dev *pdev,
845 uint32_t flags);
846void radeon_device_fini(struct radeon_device *rdev);
847int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
848
3ce0a23d
JG		 849/* r600 blit */
850int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
851void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
852void r600_kms_blit_copy(struct radeon_device *rdev,
853 u64 src_gpu_addr, u64 dst_gpu_addr,
854 int size_bytes);
855
de1b2898
DA		 856static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
857{
07bec2df 858 if (reg < rdev->rmmio_size)
de1b2898
DA		 859 return readl(((void __iomem *)rdev->rmmio) + reg);
860 else {
861 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
862 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
863 }
864}
865
866static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
867{
07bec2df 868 if (reg < rdev->rmmio_size)
de1b2898
DA		 869 writel(v, ((void __iomem *)rdev->rmmio) + reg);
870 else {
871 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
872 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
873 }
874}
875
4c788679
JG		 876/*
877 * Cast helper
878 */
879#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 880
881/*
882 * Registers read & write functions.
883 */
884#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
885#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 886#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 887#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 888#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 889#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
890#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
891#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
892#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
893#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
894#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 895#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
896#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 897#define WREG32_P(reg, val, mask) \
898 do { \
899 uint32_t tmp_ = RREG32(reg); \
900 tmp_ &= (mask); \
901 tmp_ |= ((val) & ~(mask)); \
902 WREG32(reg, tmp_); \
903 } while (0)
904#define WREG32_PLL_P(reg, val, mask) \
905 do { \
906 uint32_t tmp_ = RREG32_PLL(reg); \
907 tmp_ &= (mask); \
908 tmp_ |= ((val) & ~(mask)); \
909 WREG32_PLL(reg, tmp_); \
910 } while (0)
3ce0a23d 911#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 912
de1b2898
DA		 913/*
914 * Indirect registers accessor
915 */
916static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
917{
918 uint32_t r;
919
920 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
921 r = RREG32(RADEON_PCIE_DATA);
922 return r;
923}
924
925static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
926{
927 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
928 WREG32(RADEON_PCIE_DATA, (v));
929}
930
771fe6b9
JG		 931void r100_pll_errata_after_index(struct radeon_device *rdev);
932
933
934/*
935 * ASICs helpers.
936 */
b995e433
DA		 937#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
938 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 939#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
940 (rdev->family == CHIP_RV200) || \
941 (rdev->family == CHIP_RS100) || \
942 (rdev->family == CHIP_RS200) || \
943 (rdev->family == CHIP_RV250) || \
944 (rdev->family == CHIP_RV280) || \
945 (rdev->family == CHIP_RS300))
946#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
947 (rdev->family == CHIP_RV350) || \
948 (rdev->family == CHIP_R350) || \
949 (rdev->family == CHIP_RV380) || \
950 (rdev->family == CHIP_R420) || \
951 (rdev->family == CHIP_R423) || \
952 (rdev->family == CHIP_RV410) || \
953 (rdev->family == CHIP_RS400) || \
954 (rdev->family == CHIP_RS480))
955#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
956#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
957#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
958
959
960/*
961 * BIOS helpers.
962 */
963#define RBIOS8(i) (rdev->bios[i])
964#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
965#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
966
967int radeon_combios_init(struct radeon_device *rdev);
968void radeon_combios_fini(struct radeon_device *rdev);
969int radeon_atombios_init(struct radeon_device *rdev);
970void radeon_atombios_fini(struct radeon_device *rdev);
971
972
973/*
974 * RING helpers.
975 */
771fe6b9
JG		 976static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
977{
978#if DRM_DEBUG_CODE
979 if (rdev->cp.count_dw <= 0) {
980 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
981 }
982#endif
983 rdev->cp.ring[rdev->cp.wptr++] = v;
984 rdev->cp.wptr &= rdev->cp.ptr_mask;
985 rdev->cp.count_dw--;
986 rdev->cp.ring_free_dw--;
987}
988
989
990/*
991 * ASICs macro.
992 */
068a117c 993#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 994#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
995#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
996#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 997#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 998#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
771fe6b9 999#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
771fe6b9
JG		 1000#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1001#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 1002#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 1003#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 1004#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1005#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 1006#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1007#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 1008#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 1009#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1010#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1011#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1012#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 1013#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1014#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1015#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1016#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
771fe6b9
JG		 1017#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1018#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1019#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1020#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1021#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
429770b3
AD		 1022#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1023#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1024#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1025#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
771fe6b9 1026
6cf8a3f5 1027/* Common functions */
700a0cc0
JG		 1028/* AGP */
1029extern void radeon_agp_disable(struct radeon_device *rdev);
4aac0473 1030extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 1031extern int radeon_modeset_init(struct radeon_device *rdev);
1032extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1033extern bool radeon_card_posted(struct radeon_device *rdev);
72542d77 1034extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437
JG		 1035extern int radeon_clocks_init(struct radeon_device *rdev);
1036extern void radeon_clocks_fini(struct radeon_device *rdev);
1037extern void radeon_scratch_init(struct radeon_device *rdev);
1038extern void radeon_surface_init(struct radeon_device *rdev);
1039extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1040extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1041extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1042extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1043extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
6cf8a3f5 1044
a18d7ea1 1045/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 1046struct r100_mc_save {
1047 u32 GENMO_WT;
1048 u32 CRTC_EXT_CNTL;
1049 u32 CRTC_GEN_CNTL;
1050 u32 CRTC2_GEN_CNTL;
1051 u32 CUR_OFFSET;
1052 u32 CUR2_OFFSET;
1053};
1054extern void r100_cp_disable(struct radeon_device *rdev);
1055extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1056extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 1057extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 1058extern int r100_pci_gart_init(struct radeon_device *rdev);
1059extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 1060extern int r100_pci_gart_enable(struct radeon_device *rdev);
1061extern void r100_pci_gart_disable(struct radeon_device *rdev);
1062extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 1063extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1064extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1065extern void r100_ib_fini(struct radeon_device *rdev);
1066extern int r100_ib_init(struct radeon_device *rdev);
1067extern void r100_irq_disable(struct radeon_device *rdev);
1068extern int r100_irq_set(struct radeon_device *rdev);
1069extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1070extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1071extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1072extern void r100_wb_disable(struct radeon_device *rdev);
1073extern void r100_wb_fini(struct radeon_device *rdev);
1074extern int r100_wb_init(struct radeon_device *rdev);
d39c3b89
JG		 1075extern void r100_hdp_reset(struct radeon_device *rdev);
1076extern int r100_rb2d_reset(struct radeon_device *rdev);
1077extern int r100_cp_reset(struct radeon_device *rdev);
ca6ffc64 1078extern void r100_vga_render_disable(struct radeon_device *rdev);
207bf9e9
JG		 1079extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1080 struct radeon_cs_packet *pkt,
4c788679 1081 struct radeon_bo *robj);
207bf9e9
JG		 1082extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1083 struct radeon_cs_packet *pkt,
1084 const unsigned *auth, unsigned n,
1085 radeon_packet0_check_t check);
1086extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1087 struct radeon_cs_packet *pkt,
1088 unsigned idx);
17e15b0c 1089extern void r100_enable_bm(struct radeon_device *rdev);
92cde00c 1090extern void r100_set_common_regs(struct radeon_device *rdev);
9f022ddf 1091
d4550907
JG		 1092/* rv200,rv250,rv280 */
1093extern void r200_set_safe_registers(struct radeon_device *rdev);
9f022ddf
JG		 1094
1095/* r300,r350,rv350,rv370,rv380 */
1096extern void r300_set_reg_safe(struct radeon_device *rdev);
1097extern void r300_mc_program(struct radeon_device *rdev);
1098extern void r300_vram_info(struct radeon_device *rdev);
ca6ffc64
JG		 1099extern void r300_clock_startup(struct radeon_device *rdev);
1100extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1101extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1102extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1103extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1104extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1105
905b6822 1106/* r420,r423,rv410 */
d39c3b89 1107extern int r420_mc_init(struct radeon_device *rdev);
21f9a437
JG		 1108extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1109extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1110extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1111extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1112
21f9a437 1113/* rv515 */
d39c3b89
JG		 1114struct rv515_mc_save {
1115 u32 d1vga_control;
1116 u32 d2vga_control;
1117 u32 vga_render_control;
1118 u32 vga_hdp_control;
1119 u32 d1crtc_control;
1120 u32 d2crtc_control;
1121};
21f9a437 1122extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1123extern void rv515_vga_render_disable(struct radeon_device *rdev);
1124extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1125extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1126extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1127extern void rv515_clock_startup(struct radeon_device *rdev);
1128extern void rv515_debugfs(struct radeon_device *rdev);
1129extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1130
3bc68535
JG		 1131/* rs400 */
1132extern int rs400_gart_init(struct radeon_device *rdev);
1133extern int rs400_gart_enable(struct radeon_device *rdev);
1134extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1135extern void rs400_gart_disable(struct radeon_device *rdev);
1136extern void rs400_gart_fini(struct radeon_device *rdev);
1137
1138/* rs600 */
1139extern void rs600_set_safe_registers(struct radeon_device *rdev);
ac447df4
JG		 1140extern int rs600_irq_set(struct radeon_device *rdev);
1141extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1142
21f9a437
JG		 1143/* rs690, rs740 */
1144extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1145 struct drm_display_mode *mode1,
1146 struct drm_display_mode *mode2);
1147
1148/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1149extern bool r600_card_posted(struct radeon_device *rdev);
1150extern void r600_cp_stop(struct radeon_device *rdev);
1151extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1152extern int r600_cp_resume(struct radeon_device *rdev);
1153extern int r600_count_pipe_bits(uint32_t val);
1154extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1155extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1156extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1157extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1158extern int r600_ib_test(struct radeon_device *rdev);
1159extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1160extern void r600_wb_fini(struct radeon_device *rdev);
81cc35bf
JG		 1161extern int r600_wb_enable(struct radeon_device *rdev);
1162extern void r600_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1163extern void r600_scratch_init(struct radeon_device *rdev);
1164extern int r600_blit_init(struct radeon_device *rdev);
1165extern void r600_blit_fini(struct radeon_device *rdev);
d8f60cfc 1166extern int r600_init_microcode(struct radeon_device *rdev);
fe62e1a4 1167extern int r600_gpu_reset(struct radeon_device *rdev);
d8f60cfc
AD		 1168/* r600 irq */
1169extern int r600_irq_init(struct radeon_device *rdev);
1170extern void r600_irq_fini(struct radeon_device *rdev);
1171extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1172extern int r600_irq_set(struct radeon_device *rdev);
0c45249f
JG		 1173extern void r600_irq_suspend(struct radeon_device *rdev);
1174/* r600 audio */
dafc3bd5
CK		 1175extern int r600_audio_init(struct radeon_device *rdev);
1176extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1177extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1178extern void r600_audio_fini(struct radeon_device *rdev);
1179extern void r600_hdmi_init(struct drm_encoder *encoder);
1180extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1181extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1182extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1183extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1184 int channels,
1185 int rate,
1186 int bps,
1187 uint8_t status_bits,
1188 uint8_t category_code);
1189
4c788679
JG		 1190#include "radeon_object.h"
1191
771fe6b9 1192#endif
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