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drm/radeon: Endianness fixes for radeondrmfb.
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon.h
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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47#include <asm/atomic.h>
48#include <linux/wait.h>
49#include <linux/list.h>
50#include <linux/kref.h>
51
52#include "radeon_mode.h"
53#include "radeon_reg.h"
068a117c 54#include "r300.h"
771fe6b9
JG		 55
56/*
57 * Modules parameters.
58 */
59extern int radeon_no_wb;
60extern int radeon_modeset;
61extern int radeon_dynclks;
62extern int radeon_r4xx_atom;
63extern int radeon_agpmode;
64extern int radeon_vram_limit;
65extern int radeon_gart_size;
66extern int radeon_benchmarking;
67extern int radeon_connector_table;
68
69/*
70 * Copy from radeon_drv.h so we don't have to include both and have conflicting
71 * symbol;
72 */
73#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
74#define RADEON_IB_POOL_SIZE 16
75#define RADEON_DEBUGFS_MAX_NUM_FILES 32
76#define RADEONFB_CONN_LIMIT 4
77
78enum radeon_family {
79 CHIP_R100,
80 CHIP_RV100,
81 CHIP_RS100,
82 CHIP_RV200,
83 CHIP_RS200,
84 CHIP_R200,
85 CHIP_RV250,
86 CHIP_RS300,
87 CHIP_RV280,
88 CHIP_R300,
89 CHIP_R350,
90 CHIP_RV350,
91 CHIP_RV380,
92 CHIP_R420,
93 CHIP_R423,
94 CHIP_RV410,
95 CHIP_RS400,
96 CHIP_RS480,
97 CHIP_RS600,
98 CHIP_RS690,
99 CHIP_RS740,
100 CHIP_RV515,
101 CHIP_R520,
102 CHIP_RV530,
103 CHIP_RV560,
104 CHIP_RV570,
105 CHIP_R580,
106 CHIP_R600,
107 CHIP_RV610,
108 CHIP_RV630,
109 CHIP_RV620,
110 CHIP_RV635,
111 CHIP_RV670,
112 CHIP_RS780,
113 CHIP_RV770,
114 CHIP_RV730,
115 CHIP_RV710,
116 CHIP_LAST,
117};
118
119enum radeon_chip_flags {
120 RADEON_FAMILY_MASK = 0x0000ffffUL,
121 RADEON_FLAGS_MASK = 0xffff0000UL,
122 RADEON_IS_MOBILITY = 0x00010000UL,
123 RADEON_IS_IGP = 0x00020000UL,
124 RADEON_SINGLE_CRTC = 0x00040000UL,
125 RADEON_IS_AGP = 0x00080000UL,
126 RADEON_HAS_HIERZ = 0x00100000UL,
127 RADEON_IS_PCIE = 0x00200000UL,
128 RADEON_NEW_MEMMAP = 0x00400000UL,
129 RADEON_IS_PCI = 0x00800000UL,
130 RADEON_IS_IGPGART = 0x01000000UL,
131};
132
133
134/*
135 * Errata workarounds.
136 */
137enum radeon_pll_errata {
138 CHIP_ERRATA_R300_CG = 0x00000001,
139 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
140 CHIP_ERRATA_PLL_DELAY = 0x00000004
141};
142
143
144struct radeon_device;
145
146
147/*
148 * BIOS.
149 */
150bool radeon_get_bios(struct radeon_device *rdev);
151
152/*
153 * Clocks
154 */
155
156struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
159 struct radeon_pll spll;
160 struct radeon_pll mpll;
161 /* 10 Khz units */
162 uint32_t default_mclk;
163 uint32_t default_sclk;
164};
165
166/*
167 * Fences.
168 */
169struct radeon_fence_driver {
170 uint32_t scratch_reg;
171 atomic_t seq;
172 uint32_t last_seq;
173 unsigned long count_timeout;
174 wait_queue_head_t queue;
175 rwlock_t lock;
176 struct list_head created;
177 struct list_head emited;
178 struct list_head signaled;
179};
180
181struct radeon_fence {
182 struct radeon_device *rdev;
183 struct kref kref;
184 struct list_head list;
185 /* protected by radeon_fence.lock */
186 uint32_t seq;
187 unsigned long timeout;
188 bool emited;
189 bool signaled;
190};
191
192int radeon_fence_driver_init(struct radeon_device *rdev);
193void radeon_fence_driver_fini(struct radeon_device *rdev);
194int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
195int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
196void radeon_fence_process(struct radeon_device *rdev);
197bool radeon_fence_signaled(struct radeon_fence *fence);
198int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
199int radeon_fence_wait_next(struct radeon_device *rdev);
200int radeon_fence_wait_last(struct radeon_device *rdev);
201struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
202void radeon_fence_unref(struct radeon_fence **fence);
203
204
205/*
206 * Radeon buffer.
207 */
208struct radeon_object;
209
210struct radeon_object_list {
211 struct list_head list;
212 struct radeon_object *robj;
213 uint64_t gpu_offset;
214 unsigned rdomain;
215 unsigned wdomain;
216};
217
218int radeon_object_init(struct radeon_device *rdev);
219void radeon_object_fini(struct radeon_device *rdev);
220int radeon_object_create(struct radeon_device *rdev,
221 struct drm_gem_object *gobj,
222 unsigned long size,
223 bool kernel,
224 uint32_t domain,
225 bool interruptible,
226 struct radeon_object **robj_ptr);
227int radeon_object_kmap(struct radeon_object *robj, void **ptr);
228void radeon_object_kunmap(struct radeon_object *robj);
229void radeon_object_unref(struct radeon_object **robj);
230int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
231 uint64_t *gpu_addr);
232void radeon_object_unpin(struct radeon_object *robj);
233int radeon_object_wait(struct radeon_object *robj);
234int radeon_object_evict_vram(struct radeon_device *rdev);
235int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
236void radeon_object_force_delete(struct radeon_device *rdev);
237void radeon_object_list_add_object(struct radeon_object_list *lobj,
238 struct list_head *head);
239int radeon_object_list_validate(struct list_head *head, void *fence);
240void radeon_object_list_unvalidate(struct list_head *head);
241void radeon_object_list_clean(struct list_head *head);
242int radeon_object_fbdev_mmap(struct radeon_object *robj,
243 struct vm_area_struct *vma);
244unsigned long radeon_object_size(struct radeon_object *robj);
245
246
247/*
248 * GEM objects.
249 */
250struct radeon_gem {
251 struct list_head objects;
252};
253
254int radeon_gem_init(struct radeon_device *rdev);
255void radeon_gem_fini(struct radeon_device *rdev);
256int radeon_gem_object_create(struct radeon_device *rdev, int size,
257 int alignment, int initial_domain,
258 bool discardable, bool kernel,
259 bool interruptible,
260 struct drm_gem_object **obj);
261int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
262 uint64_t *gpu_addr);
263void radeon_gem_object_unpin(struct drm_gem_object *obj);
264
265
266/*
267 * GART structures, functions & helpers
268 */
269struct radeon_mc;
270
271struct radeon_gart_table_ram {
272 volatile uint32_t *ptr;
273};
274
275struct radeon_gart_table_vram {
276 struct radeon_object *robj;
277 volatile uint32_t *ptr;
278};
279
280union radeon_gart_table {
281 struct radeon_gart_table_ram ram;
282 struct radeon_gart_table_vram vram;
283};
284
285struct radeon_gart {
286 dma_addr_t table_addr;
287 unsigned num_gpu_pages;
288 unsigned num_cpu_pages;
289 unsigned table_size;
290 union radeon_gart_table table;
291 struct page **pages;
292 dma_addr_t *pages_addr;
293 bool ready;
294};
295
296int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
297void radeon_gart_table_ram_free(struct radeon_device *rdev);
298int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
299void radeon_gart_table_vram_free(struct radeon_device *rdev);
300int radeon_gart_init(struct radeon_device *rdev);
301void radeon_gart_fini(struct radeon_device *rdev);
302void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
303 int pages);
304int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
305 int pages, struct page **pagelist);
306
307
308/*
309 * GPU MC structures, functions & helpers
310 */
311struct radeon_mc {
312 resource_size_t aper_size;
313 resource_size_t aper_base;
314 resource_size_t agp_base;
315 unsigned gtt_location;
316 unsigned gtt_size;
317 unsigned vram_location;
318 unsigned vram_size;
319 unsigned vram_width;
320 int vram_mtrr;
321 bool vram_is_ddr;
322};
323
324int radeon_mc_setup(struct radeon_device *rdev);
325
326
327/*
328 * GPU scratch registers structures, functions & helpers
329 */
330struct radeon_scratch {
331 unsigned num_reg;
332 bool free[32];
333 uint32_t reg[32];
334};
335
336int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
337void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
338
339
340/*
341 * IRQS.
342 */
343struct radeon_irq {
344 bool installed;
345 bool sw_int;
346 /* FIXME: use a define max crtc rather than hardcode it */
347 bool crtc_vblank_int[2];
348};
349
350int radeon_irq_kms_init(struct radeon_device *rdev);
351void radeon_irq_kms_fini(struct radeon_device *rdev);
352
353
354/*
355 * CP & ring.
356 */
357struct radeon_ib {
358 struct list_head list;
359 unsigned long idx;
360 uint64_t gpu_addr;
361 struct radeon_fence *fence;
362 volatile uint32_t *ptr;
363 uint32_t length_dw;
364};
365
366struct radeon_ib_pool {
367 struct mutex mutex;
368 struct radeon_object *robj;
369 struct list_head scheduled_ibs;
370 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
371 bool ready;
372 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
373};
374
375struct radeon_cp {
376 struct radeon_object *ring_obj;
377 volatile uint32_t *ring;
378 unsigned rptr;
379 unsigned wptr;
380 unsigned wptr_old;
381 unsigned ring_size;
382 unsigned ring_free_dw;
383 int count_dw;
384 uint64_t gpu_addr;
385 uint32_t align_mask;
386 uint32_t ptr_mask;
387 struct mutex mutex;
388 bool ready;
389};
390
391int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
392void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
393int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
394int radeon_ib_pool_init(struct radeon_device *rdev);
395void radeon_ib_pool_fini(struct radeon_device *rdev);
396int radeon_ib_test(struct radeon_device *rdev);
397/* Ring access between begin & end cannot sleep */
398void radeon_ring_free_size(struct radeon_device *rdev);
399int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
400void radeon_ring_unlock_commit(struct radeon_device *rdev);
401void radeon_ring_unlock_undo(struct radeon_device *rdev);
402int radeon_ring_test(struct radeon_device *rdev);
403int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
404void radeon_ring_fini(struct radeon_device *rdev);
405
406
407/*
408 * CS.
409 */
410struct radeon_cs_reloc {
411 struct drm_gem_object *gobj;
412 struct radeon_object *robj;
413 struct radeon_object_list lobj;
414 uint32_t handle;
415 uint32_t flags;
416};
417
418struct radeon_cs_chunk {
419 uint32_t chunk_id;
420 uint32_t length_dw;
421 uint32_t *kdata;
422};
423
424struct radeon_cs_parser {
425 struct radeon_device *rdev;
426 struct drm_file *filp;
427 /* chunks */
428 unsigned nchunks;
429 struct radeon_cs_chunk *chunks;
430 uint64_t *chunks_array;
431 /* IB */
432 unsigned idx;
433 /* relocations */
434 unsigned nrelocs;
435 struct radeon_cs_reloc *relocs;
436 struct radeon_cs_reloc **relocs_ptr;
437 struct list_head validated;
438 /* indices of various chunks */
439 int chunk_ib_idx;
440 int chunk_relocs_idx;
441 struct radeon_ib *ib;
442 void *track;
443};
444
445struct radeon_cs_packet {
446 unsigned idx;
447 unsigned type;
448 unsigned reg;
449 unsigned opcode;
450 int count;
451 unsigned one_reg_wr;
452};
453
454typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
455 struct radeon_cs_packet *pkt,
456 unsigned idx, unsigned reg);
457typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
458 struct radeon_cs_packet *pkt);
459
460
461/*
462 * AGP
463 */
464int radeon_agp_init(struct radeon_device *rdev);
465void radeon_agp_fini(struct radeon_device *rdev);
466
467
468/*
469 * Writeback
470 */
471struct radeon_wb {
472 struct radeon_object *wb_obj;
473 volatile uint32_t *wb;
474 uint64_t gpu_addr;
475};
476
477
478/*
479 * Benchmarking
480 */
481void radeon_benchmark(struct radeon_device *rdev);
482
483
484/*
485 * Debugfs
486 */
487int radeon_debugfs_add_files(struct radeon_device *rdev,
488 struct drm_info_list *files,
489 unsigned nfiles);
490int radeon_debugfs_fence_init(struct radeon_device *rdev);
491int r100_debugfs_rbbm_init(struct radeon_device *rdev);
492int r100_debugfs_cp_init(struct radeon_device *rdev);
493
494
495/*
496 * ASIC specific functions.
497 */
498struct radeon_asic {
068a117c 499 int (*init)(struct radeon_device *rdev);
771fe6b9
JG		 500 void (*errata)(struct radeon_device *rdev);
501 void (*vram_info)(struct radeon_device *rdev);
502 int (*gpu_reset)(struct radeon_device *rdev);
503 int (*mc_init)(struct radeon_device *rdev);
504 void (*mc_fini)(struct radeon_device *rdev);
505 int (*wb_init)(struct radeon_device *rdev);
506 void (*wb_fini)(struct radeon_device *rdev);
507 int (*gart_enable)(struct radeon_device *rdev);
508 void (*gart_disable)(struct radeon_device *rdev);
509 void (*gart_tlb_flush)(struct radeon_device *rdev);
510 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
511 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
512 void (*cp_fini)(struct radeon_device *rdev);
513 void (*cp_disable)(struct radeon_device *rdev);
514 void (*ring_start)(struct radeon_device *rdev);
515 int (*irq_set)(struct radeon_device *rdev);
516 int (*irq_process)(struct radeon_device *rdev);
517 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
518 int (*cs_parse)(struct radeon_cs_parser *p);
519 int (*copy_blit)(struct radeon_device *rdev,
520 uint64_t src_offset,
521 uint64_t dst_offset,
522 unsigned num_pages,
523 struct radeon_fence *fence);
524 int (*copy_dma)(struct radeon_device *rdev,
525 uint64_t src_offset,
526 uint64_t dst_offset,
527 unsigned num_pages,
528 struct radeon_fence *fence);
529 int (*copy)(struct radeon_device *rdev,
530 uint64_t src_offset,
531 uint64_t dst_offset,
532 unsigned num_pages,
533 struct radeon_fence *fence);
534 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
535 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
536 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
537 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
538};
539
068a117c
JG		 540union radeon_asic_config {
541 struct r300_asic r300;
542};
543
771fe6b9
JG		 544
545/*
546 * IOCTL.
547 */
548int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
549 struct drm_file *filp);
550int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
551 struct drm_file *filp);
552int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
553 struct drm_file *file_priv);
554int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
555 struct drm_file *file_priv);
556int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
557 struct drm_file *file_priv);
558int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
559 struct drm_file *file_priv);
560int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
561 struct drm_file *filp);
562int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
563 struct drm_file *filp);
564int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
565 struct drm_file *filp);
566int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
567 struct drm_file *filp);
568int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
569
570
571/*
572 * Core structure, functions and helpers.
573 */
574typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
575typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
576
577struct radeon_device {
578 struct drm_device *ddev;
579 struct pci_dev *pdev;
580 /* ASIC */
068a117c 581 union radeon_asic_config config;
771fe6b9
JG		 582 enum radeon_family family;
583 unsigned long flags;
584 int usec_timeout;
585 enum radeon_pll_errata pll_errata;
586 int num_gb_pipes;
587 int disp_priority;
588 /* BIOS */
589 uint8_t *bios;
590 bool is_atom_bios;
591 uint16_t bios_header_start;
592 struct radeon_object *stollen_vga_memory;
593 struct fb_info *fbdev_info;
594 struct radeon_object *fbdev_robj;
595 struct radeon_framebuffer *fbdev_rfb;
596 /* Register mmio */
4c9bc75c
DA		 597 resource_size_t rmmio_base;
598 resource_size_t rmmio_size;
771fe6b9
JG		 599 void *rmmio;
600 radeon_rreg_t mm_rreg;
601 radeon_wreg_t mm_wreg;
602 radeon_rreg_t mc_rreg;
603 radeon_wreg_t mc_wreg;
604 radeon_rreg_t pll_rreg;
605 radeon_wreg_t pll_wreg;
606 radeon_rreg_t pcie_rreg;
607 radeon_wreg_t pcie_wreg;
608 radeon_rreg_t pciep_rreg;
609 radeon_wreg_t pciep_wreg;
610 struct radeon_clock clock;
611 struct radeon_mc mc;
612 struct radeon_gart gart;
613 struct radeon_mode_info mode_info;
614 struct radeon_scratch scratch;
615 struct radeon_mman mman;
616 struct radeon_fence_driver fence_drv;
617 struct radeon_cp cp;
618 struct radeon_ib_pool ib_pool;
619 struct radeon_irq irq;
620 struct radeon_asic *asic;
621 struct radeon_gem gem;
622 struct mutex cs_mutex;
623 struct radeon_wb wb;
624 bool gpu_lockup;
625 bool shutdown;
626 bool suspend;
627};
628
629int radeon_device_init(struct radeon_device *rdev,
630 struct drm_device *ddev,
631 struct pci_dev *pdev,
632 uint32_t flags);
633void radeon_device_fini(struct radeon_device *rdev);
634int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
635
636
637/*
638 * Registers read & write functions.
639 */
640#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
641#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
642#define RREG32(reg) rdev->mm_rreg(rdev, (reg))
643#define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v))
644#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
645#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
646#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
647#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
648#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
649#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
650#define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg))
651#define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v))
652#define WREG32_P(reg, val, mask) \
653 do { \
654 uint32_t tmp_ = RREG32(reg); \
655 tmp_ &= (mask); \
656 tmp_ |= ((val) & ~(mask)); \
657 WREG32(reg, tmp_); \
658 } while (0)
659#define WREG32_PLL_P(reg, val, mask) \
660 do { \
661 uint32_t tmp_ = RREG32_PLL(reg); \
662 tmp_ &= (mask); \
663 tmp_ |= ((val) & ~(mask)); \
664 WREG32_PLL(reg, tmp_); \
665 } while (0)
666
667void r100_pll_errata_after_index(struct radeon_device *rdev);
668
669
670/*
671 * ASICs helpers.
672 */
673#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
674 (rdev->family == CHIP_RV200) || \
675 (rdev->family == CHIP_RS100) || \
676 (rdev->family == CHIP_RS200) || \
677 (rdev->family == CHIP_RV250) || \
678 (rdev->family == CHIP_RV280) || \
679 (rdev->family == CHIP_RS300))
680#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
681 (rdev->family == CHIP_RV350) || \
682 (rdev->family == CHIP_R350) || \
683 (rdev->family == CHIP_RV380) || \
684 (rdev->family == CHIP_R420) || \
685 (rdev->family == CHIP_R423) || \
686 (rdev->family == CHIP_RV410) || \
687 (rdev->family == CHIP_RS400) || \
688 (rdev->family == CHIP_RS480))
689#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
690#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
691#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
692
693
694/*
695 * BIOS helpers.
696 */
697#define RBIOS8(i) (rdev->bios[i])
698#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
699#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
700
701int radeon_combios_init(struct radeon_device *rdev);
702void radeon_combios_fini(struct radeon_device *rdev);
703int radeon_atombios_init(struct radeon_device *rdev);
704void radeon_atombios_fini(struct radeon_device *rdev);
705
706
707/*
708 * RING helpers.
709 */
710#define CP_PACKET0 0x00000000
711#define PACKET0_BASE_INDEX_SHIFT 0
712#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
713#define PACKET0_COUNT_SHIFT 16
714#define PACKET0_COUNT_MASK (0x3fff << 16)
715#define CP_PACKET1 0x40000000
716#define CP_PACKET2 0x80000000
717#define PACKET2_PAD_SHIFT 0
718#define PACKET2_PAD_MASK (0x3fffffff << 0)
719#define CP_PACKET3 0xC0000000
720#define PACKET3_IT_OPCODE_SHIFT 8
721#define PACKET3_IT_OPCODE_MASK (0xff << 8)
722#define PACKET3_COUNT_SHIFT 16
723#define PACKET3_COUNT_MASK (0x3fff << 16)
724/* PACKET3 op code */
725#define PACKET3_NOP 0x10
726#define PACKET3_3D_DRAW_VBUF 0x28
727#define PACKET3_3D_DRAW_IMMD 0x29
728#define PACKET3_3D_DRAW_INDX 0x2A
729#define PACKET3_3D_LOAD_VBPNTR 0x2F
730#define PACKET3_INDX_BUFFER 0x33
731#define PACKET3_3D_DRAW_VBUF_2 0x34
732#define PACKET3_3D_DRAW_IMMD_2 0x35
733#define PACKET3_3D_DRAW_INDX_2 0x36
734#define PACKET3_BITBLT_MULTI 0x9B
735
736#define PACKET0(reg, n) (CP_PACKET0 | \
737 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
738 REG_SET(PACKET0_COUNT, (n)))
739#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
740#define PACKET3(op, n) (CP_PACKET3 | \
741 REG_SET(PACKET3_IT_OPCODE, (op)) | \
742 REG_SET(PACKET3_COUNT, (n)))
743
744#define PACKET_TYPE0 0
745#define PACKET_TYPE1 1
746#define PACKET_TYPE2 2
747#define PACKET_TYPE3 3
748
749#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
750#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
751#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
752#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
753#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
754
755static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
756{
757#if DRM_DEBUG_CODE
758 if (rdev->cp.count_dw <= 0) {
759 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
760 }
761#endif
762 rdev->cp.ring[rdev->cp.wptr++] = v;
763 rdev->cp.wptr &= rdev->cp.ptr_mask;
764 rdev->cp.count_dw--;
765 rdev->cp.ring_free_dw--;
766}
767
768
769/*
770 * ASICs macro.
771 */
068a117c 772#define radeon_init(rdev) (rdev)->asic->init((rdev))
771fe6b9
JG		 773#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
774#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
775#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
776#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
777#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
778#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
779#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
780#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
781#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
782#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
783#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
784#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
785#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
786#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
787#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
788#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
789#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
790#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
791#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
792#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
793#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
794#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
795#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
796#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
797#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
798#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
799
800#endif
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