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drm/radeon/kms: we should return 0 when we have no modes not -1.
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47#include <asm/atomic.h>
48#include <linux/wait.h>
49#include <linux/list.h>
50#include <linux/kref.h>
51
52#include "radeon_mode.h"
53#include "radeon_reg.h"
771fe6b9
JG		 54
55/*
56 * Modules parameters.
57 */
58extern int radeon_no_wb;
59extern int radeon_modeset;
60extern int radeon_dynclks;
61extern int radeon_r4xx_atom;
62extern int radeon_agpmode;
63extern int radeon_vram_limit;
64extern int radeon_gart_size;
65extern int radeon_benchmarking;
ecc0b326 66extern int radeon_testing;
771fe6b9 67extern int radeon_connector_table;
4ce001ab 68extern int radeon_tv;
771fe6b9
JG		 69
70/*
71 * Copy from radeon_drv.h so we don't have to include both and have conflicting
72 * symbol;
73 */
74#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
75#define RADEON_IB_POOL_SIZE 16
76#define RADEON_DEBUGFS_MAX_NUM_FILES 32
77#define RADEONFB_CONN_LIMIT 4
78
79enum radeon_family {
80 CHIP_R100,
81 CHIP_RV100,
82 CHIP_RS100,
83 CHIP_RV200,
84 CHIP_RS200,
85 CHIP_R200,
86 CHIP_RV250,
87 CHIP_RS300,
88 CHIP_RV280,
89 CHIP_R300,
90 CHIP_R350,
91 CHIP_RV350,
92 CHIP_RV380,
93 CHIP_R420,
94 CHIP_R423,
95 CHIP_RV410,
96 CHIP_RS400,
97 CHIP_RS480,
98 CHIP_RS600,
99 CHIP_RS690,
100 CHIP_RS740,
101 CHIP_RV515,
102 CHIP_R520,
103 CHIP_RV530,
104 CHIP_RV560,
105 CHIP_RV570,
106 CHIP_R580,
107 CHIP_R600,
108 CHIP_RV610,
109 CHIP_RV630,
110 CHIP_RV620,
111 CHIP_RV635,
112 CHIP_RV670,
113 CHIP_RS780,
3ce0a23d 114 CHIP_RS880,
771fe6b9
JG		 115 CHIP_RV770,
116 CHIP_RV730,
117 CHIP_RV710,
3ce0a23d 118 CHIP_RV740,
771fe6b9
JG		 119 CHIP_LAST,
120};
121
122enum radeon_chip_flags {
123 RADEON_FAMILY_MASK = 0x0000ffffUL,
124 RADEON_FLAGS_MASK = 0xffff0000UL,
125 RADEON_IS_MOBILITY = 0x00010000UL,
126 RADEON_IS_IGP = 0x00020000UL,
127 RADEON_SINGLE_CRTC = 0x00040000UL,
128 RADEON_IS_AGP = 0x00080000UL,
129 RADEON_HAS_HIERZ = 0x00100000UL,
130 RADEON_IS_PCIE = 0x00200000UL,
131 RADEON_NEW_MEMMAP = 0x00400000UL,
132 RADEON_IS_PCI = 0x00800000UL,
133 RADEON_IS_IGPGART = 0x01000000UL,
134};
135
136
137/*
138 * Errata workarounds.
139 */
140enum radeon_pll_errata {
141 CHIP_ERRATA_R300_CG = 0x00000001,
142 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
143 CHIP_ERRATA_PLL_DELAY = 0x00000004
144};
145
146
147struct radeon_device;
148
149
150/*
151 * BIOS.
152 */
153bool radeon_get_bios(struct radeon_device *rdev);
154
3ce0a23d 155
771fe6b9 156/*
3ce0a23d 157 * Dummy page
771fe6b9 158 */
3ce0a23d
JG		 159struct radeon_dummy_page {
160 struct page *page;
161 dma_addr_t addr;
162};
163int radeon_dummy_page_init(struct radeon_device *rdev);
164void radeon_dummy_page_fini(struct radeon_device *rdev);
165
771fe6b9 166
3ce0a23d
JG		 167/*
168 * Clocks
169 */
771fe6b9
JG		 170struct radeon_clock {
171 struct radeon_pll p1pll;
172 struct radeon_pll p2pll;
173 struct radeon_pll spll;
174 struct radeon_pll mpll;
175 /* 10 Khz units */
176 uint32_t default_mclk;
177 uint32_t default_sclk;
178};
179
3ce0a23d 180
771fe6b9
JG		 181/*
182 * Fences.
183 */
184struct radeon_fence_driver {
185 uint32_t scratch_reg;
186 atomic_t seq;
187 uint32_t last_seq;
188 unsigned long count_timeout;
189 wait_queue_head_t queue;
190 rwlock_t lock;
191 struct list_head created;
192 struct list_head emited;
193 struct list_head signaled;
194};
195
196struct radeon_fence {
197 struct radeon_device *rdev;
198 struct kref kref;
199 struct list_head list;
200 /* protected by radeon_fence.lock */
201 uint32_t seq;
202 unsigned long timeout;
203 bool emited;
204 bool signaled;
205};
206
207int radeon_fence_driver_init(struct radeon_device *rdev);
208void radeon_fence_driver_fini(struct radeon_device *rdev);
209int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
210int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
211void radeon_fence_process(struct radeon_device *rdev);
212bool radeon_fence_signaled(struct radeon_fence *fence);
213int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
214int radeon_fence_wait_next(struct radeon_device *rdev);
215int radeon_fence_wait_last(struct radeon_device *rdev);
216struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
217void radeon_fence_unref(struct radeon_fence **fence);
218
e024e110
DA		 219/*
220 * Tiling registers
221 */
222struct radeon_surface_reg {
223 struct radeon_object *robj;
224};
225
226#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 227
228/*
229 * Radeon buffer.
230 */
231struct radeon_object;
232
233struct radeon_object_list {
234 struct list_head list;
235 struct radeon_object *robj;
236 uint64_t gpu_offset;
237 unsigned rdomain;
238 unsigned wdomain;
e024e110 239 uint32_t tiling_flags;
771fe6b9
JG		 240};
241
242int radeon_object_init(struct radeon_device *rdev);
243void radeon_object_fini(struct radeon_device *rdev);
244int radeon_object_create(struct radeon_device *rdev,
245 struct drm_gem_object *gobj,
246 unsigned long size,
247 bool kernel,
248 uint32_t domain,
249 bool interruptible,
250 struct radeon_object **robj_ptr);
251int radeon_object_kmap(struct radeon_object *robj, void **ptr);
252void radeon_object_kunmap(struct radeon_object *robj);
253void radeon_object_unref(struct radeon_object **robj);
254int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
255 uint64_t *gpu_addr);
256void radeon_object_unpin(struct radeon_object *robj);
257int radeon_object_wait(struct radeon_object *robj);
cefb87ef 258int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
771fe6b9
JG		 259int radeon_object_evict_vram(struct radeon_device *rdev);
260int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
261void radeon_object_force_delete(struct radeon_device *rdev);
262void radeon_object_list_add_object(struct radeon_object_list *lobj,
263 struct list_head *head);
264int radeon_object_list_validate(struct list_head *head, void *fence);
265void radeon_object_list_unvalidate(struct list_head *head);
266void radeon_object_list_clean(struct list_head *head);
267int radeon_object_fbdev_mmap(struct radeon_object *robj,
268 struct vm_area_struct *vma);
269unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 270void radeon_object_clear_surface_reg(struct radeon_object *robj);
271int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
272 bool force_drop);
273void radeon_object_set_tiling_flags(struct radeon_object *robj,
274 uint32_t tiling_flags, uint32_t pitch);
275void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
276void radeon_bo_move_notify(struct ttm_buffer_object *bo,
277 struct ttm_mem_reg *mem);
278void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 279/*
280 * GEM objects.
281 */
282struct radeon_gem {
283 struct list_head objects;
284};
285
286int radeon_gem_init(struct radeon_device *rdev);
287void radeon_gem_fini(struct radeon_device *rdev);
288int radeon_gem_object_create(struct radeon_device *rdev, int size,
289 int alignment, int initial_domain,
290 bool discardable, bool kernel,
291 bool interruptible,
292 struct drm_gem_object **obj);
293int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
294 uint64_t *gpu_addr);
295void radeon_gem_object_unpin(struct drm_gem_object *obj);
296
297
298/*
299 * GART structures, functions & helpers
300 */
301struct radeon_mc;
302
303struct radeon_gart_table_ram {
304 volatile uint32_t *ptr;
305};
306
307struct radeon_gart_table_vram {
308 struct radeon_object *robj;
309 volatile uint32_t *ptr;
310};
311
312union radeon_gart_table {
313 struct radeon_gart_table_ram ram;
314 struct radeon_gart_table_vram vram;
315};
316
317struct radeon_gart {
318 dma_addr_t table_addr;
319 unsigned num_gpu_pages;
320 unsigned num_cpu_pages;
321 unsigned table_size;
322 union radeon_gart_table table;
323 struct page **pages;
324 dma_addr_t *pages_addr;
325 bool ready;
326};
327
328int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
329void radeon_gart_table_ram_free(struct radeon_device *rdev);
330int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
331void radeon_gart_table_vram_free(struct radeon_device *rdev);
332int radeon_gart_init(struct radeon_device *rdev);
333void radeon_gart_fini(struct radeon_device *rdev);
334void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
335 int pages);
336int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
337 int pages, struct page **pagelist);
338
339
340/*
341 * GPU MC structures, functions & helpers
342 */
343struct radeon_mc {
344 resource_size_t aper_size;
345 resource_size_t aper_base;
346 resource_size_t agp_base;
7a50f01a
DA		 347 /* for some chips with <= 32MB we need to lie
348 * about vram size near mc fb location */
3ce0a23d
JG		 349 u64 mc_vram_size;
350 u64 gtt_location;
351 u64 gtt_size;
352 u64 gtt_start;
353 u64 gtt_end;
354 u64 vram_location;
355 u64 vram_start;
356 u64 vram_end;
771fe6b9 357 unsigned vram_width;
3ce0a23d 358 u64 real_vram_size;
771fe6b9
JG		 359 int vram_mtrr;
360 bool vram_is_ddr;
361};
362
363int radeon_mc_setup(struct radeon_device *rdev);
364
365
366/*
367 * GPU scratch registers structures, functions & helpers
368 */
369struct radeon_scratch {
370 unsigned num_reg;
371 bool free[32];
372 uint32_t reg[32];
373};
374
375int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
376void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
377
378
379/*
380 * IRQS.
381 */
382struct radeon_irq {
383 bool installed;
384 bool sw_int;
385 /* FIXME: use a define max crtc rather than hardcode it */
386 bool crtc_vblank_int[2];
387};
388
389int radeon_irq_kms_init(struct radeon_device *rdev);
390void radeon_irq_kms_fini(struct radeon_device *rdev);
391
392
393/*
394 * CP & ring.
395 */
396struct radeon_ib {
397 struct list_head list;
398 unsigned long idx;
399 uint64_t gpu_addr;
400 struct radeon_fence *fence;
401 volatile uint32_t *ptr;
402 uint32_t length_dw;
403};
404
405struct radeon_ib_pool {
406 struct mutex mutex;
407 struct radeon_object *robj;
408 struct list_head scheduled_ibs;
409 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
410 bool ready;
411 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
412};
413
414struct radeon_cp {
415 struct radeon_object *ring_obj;
416 volatile uint32_t *ring;
417 unsigned rptr;
418 unsigned wptr;
419 unsigned wptr_old;
420 unsigned ring_size;
421 unsigned ring_free_dw;
422 int count_dw;
423 uint64_t gpu_addr;
424 uint32_t align_mask;
425 uint32_t ptr_mask;
426 struct mutex mutex;
427 bool ready;
428};
429
3ce0a23d
JG		 430struct r600_blit {
431 struct radeon_object *shader_obj;
432 u64 shader_gpu_addr;
433 u32 vs_offset, ps_offset;
434 u32 state_offset;
435 u32 state_len;
436 u32 vb_used, vb_total;
437 struct radeon_ib *vb_ib;
438};
439
771fe6b9
JG		 440int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
441void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
442int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
443int radeon_ib_pool_init(struct radeon_device *rdev);
444void radeon_ib_pool_fini(struct radeon_device *rdev);
445int radeon_ib_test(struct radeon_device *rdev);
446/* Ring access between begin & end cannot sleep */
447void radeon_ring_free_size(struct radeon_device *rdev);
448int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
449void radeon_ring_unlock_commit(struct radeon_device *rdev);
450void radeon_ring_unlock_undo(struct radeon_device *rdev);
451int radeon_ring_test(struct radeon_device *rdev);
452int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
453void radeon_ring_fini(struct radeon_device *rdev);
454
455
456/*
457 * CS.
458 */
459struct radeon_cs_reloc {
460 struct drm_gem_object *gobj;
461 struct radeon_object *robj;
462 struct radeon_object_list lobj;
463 uint32_t handle;
464 uint32_t flags;
465};
466
467struct radeon_cs_chunk {
468 uint32_t chunk_id;
469 uint32_t length_dw;
470 uint32_t *kdata;
471};
472
473struct radeon_cs_parser {
474 struct radeon_device *rdev;
475 struct drm_file *filp;
476 /* chunks */
477 unsigned nchunks;
478 struct radeon_cs_chunk *chunks;
479 uint64_t *chunks_array;
480 /* IB */
481 unsigned idx;
482 /* relocations */
483 unsigned nrelocs;
484 struct radeon_cs_reloc *relocs;
485 struct radeon_cs_reloc **relocs_ptr;
486 struct list_head validated;
487 /* indices of various chunks */
488 int chunk_ib_idx;
489 int chunk_relocs_idx;
490 struct radeon_ib *ib;
491 void *track;
3ce0a23d 492 unsigned family;
771fe6b9
JG		 493};
494
495struct radeon_cs_packet {
496 unsigned idx;
497 unsigned type;
498 unsigned reg;
499 unsigned opcode;
500 int count;
501 unsigned one_reg_wr;
502};
503
504typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
505 struct radeon_cs_packet *pkt,
506 unsigned idx, unsigned reg);
507typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
508 struct radeon_cs_packet *pkt);
509
510
511/*
512 * AGP
513 */
514int radeon_agp_init(struct radeon_device *rdev);
515void radeon_agp_fini(struct radeon_device *rdev);
516
517
518/*
519 * Writeback
520 */
521struct radeon_wb {
522 struct radeon_object *wb_obj;
523 volatile uint32_t *wb;
524 uint64_t gpu_addr;
525};
526
c93bb85b
JG		 527/**
528 * struct radeon_pm - power management datas
529 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
530 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
531 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
532 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
533 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
534 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
535 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
536 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
537 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
538 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
539 * @needed_bandwidth: current bandwidth needs
540 *
541 * It keeps track of various data needed to take powermanagement decision.
542 * Bandwith need is used to determine minimun clock of the GPU and memory.
543 * Equation between gpu/memory clock and available bandwidth is hw dependent
544 * (type of memory, bus size, efficiency, ...)
545 */
546struct radeon_pm {
547 fixed20_12 max_bandwidth;
548 fixed20_12 igp_sideport_mclk;
549 fixed20_12 igp_system_mclk;
550 fixed20_12 igp_ht_link_clk;
551 fixed20_12 igp_ht_link_width;
552 fixed20_12 k8_bandwidth;
553 fixed20_12 sideport_bandwidth;
554 fixed20_12 ht_bandwidth;
555 fixed20_12 core_bandwidth;
556 fixed20_12 sclk;
557 fixed20_12 needed_bandwidth;
558};
559
771fe6b9
JG		 560
561/*
562 * Benchmarking
563 */
564void radeon_benchmark(struct radeon_device *rdev);
565
566
ecc0b326
MD		 567/*
568 * Testing
569 */
570void radeon_test_moves(struct radeon_device *rdev);
571
572
771fe6b9
JG		 573/*
574 * Debugfs
575 */
576int radeon_debugfs_add_files(struct radeon_device *rdev,
577 struct drm_info_list *files,
578 unsigned nfiles);
579int radeon_debugfs_fence_init(struct radeon_device *rdev);
580int r100_debugfs_rbbm_init(struct radeon_device *rdev);
581int r100_debugfs_cp_init(struct radeon_device *rdev);
582
583
584/*
585 * ASIC specific functions.
586 */
587struct radeon_asic {
068a117c 588 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 589 void (*fini)(struct radeon_device *rdev);
590 int (*resume)(struct radeon_device *rdev);
591 int (*suspend)(struct radeon_device *rdev);
771fe6b9
JG		 592 void (*errata)(struct radeon_device *rdev);
593 void (*vram_info)(struct radeon_device *rdev);
594 int (*gpu_reset)(struct radeon_device *rdev);
595 int (*mc_init)(struct radeon_device *rdev);
596 void (*mc_fini)(struct radeon_device *rdev);
597 int (*wb_init)(struct radeon_device *rdev);
598 void (*wb_fini)(struct radeon_device *rdev);
4aac0473
JG		 599 int (*gart_init)(struct radeon_device *rdev);
600 void (*gart_fini)(struct radeon_device *rdev);
771fe6b9
JG		 601 int (*gart_enable)(struct radeon_device *rdev);
602 void (*gart_disable)(struct radeon_device *rdev);
603 void (*gart_tlb_flush)(struct radeon_device *rdev);
604 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
605 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
606 void (*cp_fini)(struct radeon_device *rdev);
607 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 608 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 609 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 610 int (*ring_test)(struct radeon_device *rdev);
611 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
612 int (*ib_test)(struct radeon_device *rdev);
771fe6b9
JG		 613 int (*irq_set)(struct radeon_device *rdev);
614 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 615 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 616 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
617 int (*cs_parse)(struct radeon_cs_parser *p);
618 int (*copy_blit)(struct radeon_device *rdev,
619 uint64_t src_offset,
620 uint64_t dst_offset,
621 unsigned num_pages,
622 struct radeon_fence *fence);
623 int (*copy_dma)(struct radeon_device *rdev,
624 uint64_t src_offset,
625 uint64_t dst_offset,
626 unsigned num_pages,
627 struct radeon_fence *fence);
628 int (*copy)(struct radeon_device *rdev,
629 uint64_t src_offset,
630 uint64_t dst_offset,
631 unsigned num_pages,
632 struct radeon_fence *fence);
633 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
634 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
635 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
636 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 637 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
638 uint32_t tiling_flags, uint32_t pitch,
639 uint32_t offset, uint32_t obj_size);
640 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 641 void (*bandwidth_update)(struct radeon_device *rdev);
771fe6b9
JG		 642};
643
21f9a437
JG		 644/*
645 * Asic structures
646 */
551ebd83
DA		 647struct r100_asic {
648 const unsigned *reg_safe_bm;
649 unsigned reg_safe_bm_size;
650};
651
21f9a437
JG		 652struct r300_asic {
653 const unsigned *reg_safe_bm;
654 unsigned reg_safe_bm_size;
655};
656
657struct r600_asic {
658 unsigned max_pipes;
659 unsigned max_tile_pipes;
660 unsigned max_simds;
661 unsigned max_backends;
662 unsigned max_gprs;
663 unsigned max_threads;
664 unsigned max_stack_entries;
665 unsigned max_hw_contexts;
666 unsigned max_gs_threads;
667 unsigned sx_max_export_size;
668 unsigned sx_max_export_pos_size;
669 unsigned sx_max_export_smx_size;
670 unsigned sq_num_cf_insts;
671};
672
673struct rv770_asic {
674 unsigned max_pipes;
675 unsigned max_tile_pipes;
676 unsigned max_simds;
677 unsigned max_backends;
678 unsigned max_gprs;
679 unsigned max_threads;
680 unsigned max_stack_entries;
681 unsigned max_hw_contexts;
682 unsigned max_gs_threads;
683 unsigned sx_max_export_size;
684 unsigned sx_max_export_pos_size;
685 unsigned sx_max_export_smx_size;
686 unsigned sq_num_cf_insts;
687 unsigned sx_num_of_sets;
688 unsigned sc_prim_fifo_size;
689 unsigned sc_hiz_tile_fifo_size;
690 unsigned sc_earlyz_tile_fifo_fize;
691};
692
068a117c
JG		 693union radeon_asic_config {
694 struct r300_asic r300;
551ebd83 695 struct r100_asic r100;
3ce0a23d
JG		 696 struct r600_asic r600;
697 struct rv770_asic rv770;
068a117c
JG		 698};
699
771fe6b9
JG		 700
701/*
702 * IOCTL.
703 */
704int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
705 struct drm_file *filp);
706int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
707 struct drm_file *filp);
708int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
709 struct drm_file *file_priv);
710int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *file_priv);
712int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
713 struct drm_file *file_priv);
714int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
715 struct drm_file *file_priv);
716int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
717 struct drm_file *filp);
718int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
719 struct drm_file *filp);
720int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
721 struct drm_file *filp);
722int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *filp);
724int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 725int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
726 struct drm_file *filp);
727int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
728 struct drm_file *filp);
771fe6b9
JG		 729
730
731/*
732 * Core structure, functions and helpers.
733 */
734typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
735typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
736
737struct radeon_device {
9f022ddf 738 struct device *dev;
771fe6b9
JG		 739 struct drm_device *ddev;
740 struct pci_dev *pdev;
741 /* ASIC */
068a117c 742 union radeon_asic_config config;
771fe6b9
JG		 743 enum radeon_family family;
744 unsigned long flags;
745 int usec_timeout;
746 enum radeon_pll_errata pll_errata;
747 int num_gb_pipes;
f779b3e5 748 int num_z_pipes;
771fe6b9
JG		 749 int disp_priority;
750 /* BIOS */
751 uint8_t *bios;
752 bool is_atom_bios;
753 uint16_t bios_header_start;
754 struct radeon_object *stollen_vga_memory;
755 struct fb_info *fbdev_info;
756 struct radeon_object *fbdev_robj;
757 struct radeon_framebuffer *fbdev_rfb;
758 /* Register mmio */
4c9bc75c
DA		 759 resource_size_t rmmio_base;
760 resource_size_t rmmio_size;
771fe6b9 761 void *rmmio;
771fe6b9
JG		 762 radeon_rreg_t mc_rreg;
763 radeon_wreg_t mc_wreg;
764 radeon_rreg_t pll_rreg;
765 radeon_wreg_t pll_wreg;
de1b2898 766 uint32_t pcie_reg_mask;
771fe6b9
JG		 767 radeon_rreg_t pciep_rreg;
768 radeon_wreg_t pciep_wreg;
769 struct radeon_clock clock;
770 struct radeon_mc mc;
771 struct radeon_gart gart;
772 struct radeon_mode_info mode_info;
773 struct radeon_scratch scratch;
774 struct radeon_mman mman;
775 struct radeon_fence_driver fence_drv;
776 struct radeon_cp cp;
777 struct radeon_ib_pool ib_pool;
778 struct radeon_irq irq;
779 struct radeon_asic *asic;
780 struct radeon_gem gem;
c93bb85b 781 struct radeon_pm pm;
771fe6b9
JG		 782 struct mutex cs_mutex;
783 struct radeon_wb wb;
3ce0a23d 784 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 785 bool gpu_lockup;
786 bool shutdown;
787 bool suspend;
ad49f501 788 bool need_dma32;
3ce0a23d 789 bool new_init_path;
e024e110 790 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 791 const struct firmware *me_fw; /* all family ME firmware */
792 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
793 struct r600_blit r600_blit;
771fe6b9
JG		 794};
795
796int radeon_device_init(struct radeon_device *rdev,
797 struct drm_device *ddev,
798 struct pci_dev *pdev,
799 uint32_t flags);
800void radeon_device_fini(struct radeon_device *rdev);
801int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
802
3ce0a23d
JG		 803/* r600 blit */
804int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
805void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
806void r600_kms_blit_copy(struct radeon_device *rdev,
807 u64 src_gpu_addr, u64 dst_gpu_addr,
808 int size_bytes);
809
de1b2898
DA		 810static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
811{
812 if (reg < 0x10000)
813 return readl(((void __iomem *)rdev->rmmio) + reg);
814 else {
815 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
816 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
817 }
818}
819
820static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
821{
822 if (reg < 0x10000)
823 writel(v, ((void __iomem *)rdev->rmmio) + reg);
824 else {
825 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
826 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
827 }
828}
829
771fe6b9
JG		 830
831/*
832 * Registers read & write functions.
833 */
834#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
835#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 836#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 837#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 838#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 839#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
840#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
841#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
842#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
843#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
844#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 845#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
846#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 847#define WREG32_P(reg, val, mask) \
848 do { \
849 uint32_t tmp_ = RREG32(reg); \
850 tmp_ &= (mask); \
851 tmp_ |= ((val) & ~(mask)); \
852 WREG32(reg, tmp_); \
853 } while (0)
854#define WREG32_PLL_P(reg, val, mask) \
855 do { \
856 uint32_t tmp_ = RREG32_PLL(reg); \
857 tmp_ &= (mask); \
858 tmp_ |= ((val) & ~(mask)); \
859 WREG32_PLL(reg, tmp_); \
860 } while (0)
3ce0a23d 861#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 862
de1b2898
DA		 863/*
864 * Indirect registers accessor
865 */
866static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
867{
868 uint32_t r;
869
870 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
871 r = RREG32(RADEON_PCIE_DATA);
872 return r;
873}
874
875static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
876{
877 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
878 WREG32(RADEON_PCIE_DATA, (v));
879}
880
771fe6b9
JG		 881void r100_pll_errata_after_index(struct radeon_device *rdev);
882
883
884/*
885 * ASICs helpers.
886 */
b995e433
DA		 887#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
888 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 889#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
890 (rdev->family == CHIP_RV200) || \
891 (rdev->family == CHIP_RS100) || \
892 (rdev->family == CHIP_RS200) || \
893 (rdev->family == CHIP_RV250) || \
894 (rdev->family == CHIP_RV280) || \
895 (rdev->family == CHIP_RS300))
896#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
897 (rdev->family == CHIP_RV350) || \
898 (rdev->family == CHIP_R350) || \
899 (rdev->family == CHIP_RV380) || \
900 (rdev->family == CHIP_R420) || \
901 (rdev->family == CHIP_R423) || \
902 (rdev->family == CHIP_RV410) || \
903 (rdev->family == CHIP_RS400) || \
904 (rdev->family == CHIP_RS480))
905#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
906#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
907#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
908
909
910/*
911 * BIOS helpers.
912 */
913#define RBIOS8(i) (rdev->bios[i])
914#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
915#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
916
917int radeon_combios_init(struct radeon_device *rdev);
918void radeon_combios_fini(struct radeon_device *rdev);
919int radeon_atombios_init(struct radeon_device *rdev);
920void radeon_atombios_fini(struct radeon_device *rdev);
921
922
923/*
924 * RING helpers.
925 */
771fe6b9
JG		 926static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
927{
928#if DRM_DEBUG_CODE
929 if (rdev->cp.count_dw <= 0) {
930 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
931 }
932#endif
933 rdev->cp.ring[rdev->cp.wptr++] = v;
934 rdev->cp.wptr &= rdev->cp.ptr_mask;
935 rdev->cp.count_dw--;
936 rdev->cp.ring_free_dw--;
937}
938
939
940/*
941 * ASICs macro.
942 */
068a117c 943#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 944#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
945#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
946#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9
JG		 947#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
948#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
949#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
950#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
951#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
952#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
953#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
954#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
4aac0473
JG		 955#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
956#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
771fe6b9
JG		 957#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
958#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
959#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
960#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
961#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
962#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
963#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
3ce0a23d 964#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 965#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 966#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
967#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
968#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
771fe6b9
JG		 969#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
970#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 971#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 972#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
973#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
974#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
975#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
976#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
977#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
978#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
979#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 980#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
981#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 982#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
771fe6b9 983
6cf8a3f5 984/* Common functions */
4aac0473 985extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 986extern int radeon_modeset_init(struct radeon_device *rdev);
987extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 988extern bool radeon_card_posted(struct radeon_device *rdev);
21f9a437
JG		 989extern int radeon_clocks_init(struct radeon_device *rdev);
990extern void radeon_clocks_fini(struct radeon_device *rdev);
991extern void radeon_scratch_init(struct radeon_device *rdev);
992extern void radeon_surface_init(struct radeon_device *rdev);
993extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
6cf8a3f5 994
a18d7ea1 995/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 996struct r100_mc_save {
997 u32 GENMO_WT;
998 u32 CRTC_EXT_CNTL;
999 u32 CRTC_GEN_CNTL;
1000 u32 CRTC2_GEN_CNTL;
1001 u32 CUR_OFFSET;
1002 u32 CUR2_OFFSET;
1003};
1004extern void r100_cp_disable(struct radeon_device *rdev);
1005extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1006extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 1007extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 1008extern int r100_pci_gart_init(struct radeon_device *rdev);
1009extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 1010extern int r100_pci_gart_enable(struct radeon_device *rdev);
1011extern void r100_pci_gart_disable(struct radeon_device *rdev);
1012extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 1013extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1014extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1015extern void r100_ib_fini(struct radeon_device *rdev);
1016extern int r100_ib_init(struct radeon_device *rdev);
1017extern void r100_irq_disable(struct radeon_device *rdev);
1018extern int r100_irq_set(struct radeon_device *rdev);
1019extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1020extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1021extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1022extern void r100_wb_disable(struct radeon_device *rdev);
1023extern void r100_wb_fini(struct radeon_device *rdev);
1024extern int r100_wb_init(struct radeon_device *rdev);
1025
1026/* r300,r350,rv350,rv370,rv380 */
1027extern void r300_set_reg_safe(struct radeon_device *rdev);
1028extern void r300_mc_program(struct radeon_device *rdev);
1029extern void r300_vram_info(struct radeon_device *rdev);
4aac0473
JG		 1030extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1031extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1032extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1033extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1034
905b6822 1035/* r420,r423,rv410 */
21f9a437
JG		 1036extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1037extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1038extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
905b6822 1039
21f9a437
JG		 1040/* rv515 */
1041extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1042
1043/* rs690, rs740 */
1044extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1045 struct drm_display_mode *mode1,
1046 struct drm_display_mode *mode2);
1047
1048/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1049extern bool r600_card_posted(struct radeon_device *rdev);
1050extern void r600_cp_stop(struct radeon_device *rdev);
1051extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1052extern int r600_cp_resume(struct radeon_device *rdev);
1053extern int r600_count_pipe_bits(uint32_t val);
1054extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1055extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1056extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1057extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1058extern int r600_ib_test(struct radeon_device *rdev);
1059extern int r600_ring_test(struct radeon_device *rdev);
1060extern int r600_wb_init(struct radeon_device *rdev);
1061extern void r600_wb_fini(struct radeon_device *rdev);
1062extern void r600_scratch_init(struct radeon_device *rdev);
1063extern int r600_blit_init(struct radeon_device *rdev);
1064extern void r600_blit_fini(struct radeon_device *rdev);
1065extern int r600_cp_init_microcode(struct radeon_device *rdev);
1066
771fe6b9 1067#endif
Clone of davem's net-next-2.6 tree