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drm/radeon/kms: allow interruptible waits for objects.
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon.h
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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47#include <asm/atomic.h>
48#include <linux/wait.h>
49#include <linux/list.h>
50#include <linux/kref.h>
51
52#include "radeon_mode.h"
53#include "radeon_reg.h"
068a117c 54#include "r300.h"
771fe6b9
JG		 55
56/*
57 * Modules parameters.
58 */
59extern int radeon_no_wb;
60extern int radeon_modeset;
61extern int radeon_dynclks;
62extern int radeon_r4xx_atom;
63extern int radeon_agpmode;
64extern int radeon_vram_limit;
65extern int radeon_gart_size;
66extern int radeon_benchmarking;
67extern int radeon_connector_table;
68
69/*
70 * Copy from radeon_drv.h so we don't have to include both and have conflicting
71 * symbol;
72 */
73#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
74#define RADEON_IB_POOL_SIZE 16
75#define RADEON_DEBUGFS_MAX_NUM_FILES 32
76#define RADEONFB_CONN_LIMIT 4
77
78enum radeon_family {
79 CHIP_R100,
80 CHIP_RV100,
81 CHIP_RS100,
82 CHIP_RV200,
83 CHIP_RS200,
84 CHIP_R200,
85 CHIP_RV250,
86 CHIP_RS300,
87 CHIP_RV280,
88 CHIP_R300,
89 CHIP_R350,
90 CHIP_RV350,
91 CHIP_RV380,
92 CHIP_R420,
93 CHIP_R423,
94 CHIP_RV410,
95 CHIP_RS400,
96 CHIP_RS480,
97 CHIP_RS600,
98 CHIP_RS690,
99 CHIP_RS740,
100 CHIP_RV515,
101 CHIP_R520,
102 CHIP_RV530,
103 CHIP_RV560,
104 CHIP_RV570,
105 CHIP_R580,
106 CHIP_R600,
107 CHIP_RV610,
108 CHIP_RV630,
109 CHIP_RV620,
110 CHIP_RV635,
111 CHIP_RV670,
112 CHIP_RS780,
113 CHIP_RV770,
114 CHIP_RV730,
115 CHIP_RV710,
c93bb85b 116 CHIP_RS880,
771fe6b9
JG		 117 CHIP_LAST,
118};
119
120enum radeon_chip_flags {
121 RADEON_FAMILY_MASK = 0x0000ffffUL,
122 RADEON_FLAGS_MASK = 0xffff0000UL,
123 RADEON_IS_MOBILITY = 0x00010000UL,
124 RADEON_IS_IGP = 0x00020000UL,
125 RADEON_SINGLE_CRTC = 0x00040000UL,
126 RADEON_IS_AGP = 0x00080000UL,
127 RADEON_HAS_HIERZ = 0x00100000UL,
128 RADEON_IS_PCIE = 0x00200000UL,
129 RADEON_NEW_MEMMAP = 0x00400000UL,
130 RADEON_IS_PCI = 0x00800000UL,
131 RADEON_IS_IGPGART = 0x01000000UL,
132};
133
134
135/*
136 * Errata workarounds.
137 */
138enum radeon_pll_errata {
139 CHIP_ERRATA_R300_CG = 0x00000001,
140 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
141 CHIP_ERRATA_PLL_DELAY = 0x00000004
142};
143
144
145struct radeon_device;
146
147
148/*
149 * BIOS.
150 */
151bool radeon_get_bios(struct radeon_device *rdev);
152
153/*
154 * Clocks
155 */
156
157struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
160 struct radeon_pll spll;
161 struct radeon_pll mpll;
162 /* 10 Khz units */
163 uint32_t default_mclk;
164 uint32_t default_sclk;
165};
166
167/*
168 * Fences.
169 */
170struct radeon_fence_driver {
171 uint32_t scratch_reg;
172 atomic_t seq;
173 uint32_t last_seq;
174 unsigned long count_timeout;
175 wait_queue_head_t queue;
176 rwlock_t lock;
177 struct list_head created;
178 struct list_head emited;
179 struct list_head signaled;
180};
181
182struct radeon_fence {
183 struct radeon_device *rdev;
184 struct kref kref;
185 struct list_head list;
186 /* protected by radeon_fence.lock */
187 uint32_t seq;
188 unsigned long timeout;
189 bool emited;
190 bool signaled;
191};
192
193int radeon_fence_driver_init(struct radeon_device *rdev);
194void radeon_fence_driver_fini(struct radeon_device *rdev);
195int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
196int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
197void radeon_fence_process(struct radeon_device *rdev);
198bool radeon_fence_signaled(struct radeon_fence *fence);
199int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
200int radeon_fence_wait_next(struct radeon_device *rdev);
201int radeon_fence_wait_last(struct radeon_device *rdev);
202struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
203void radeon_fence_unref(struct radeon_fence **fence);
204
e024e110
DA		 205/*
206 * Tiling registers
207 */
208struct radeon_surface_reg {
209 struct radeon_object *robj;
210};
211
212#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 213
214/*
215 * Radeon buffer.
216 */
217struct radeon_object;
218
219struct radeon_object_list {
220 struct list_head list;
221 struct radeon_object *robj;
222 uint64_t gpu_offset;
223 unsigned rdomain;
224 unsigned wdomain;
e024e110 225 uint32_t tiling_flags;
771fe6b9
JG		 226};
227
228int radeon_object_init(struct radeon_device *rdev);
229void radeon_object_fini(struct radeon_device *rdev);
230int radeon_object_create(struct radeon_device *rdev,
231 struct drm_gem_object *gobj,
232 unsigned long size,
233 bool kernel,
234 uint32_t domain,
235 bool interruptible,
236 struct radeon_object **robj_ptr);
237int radeon_object_kmap(struct radeon_object *robj, void **ptr);
238void radeon_object_kunmap(struct radeon_object *robj);
239void radeon_object_unref(struct radeon_object **robj);
240int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
241 uint64_t *gpu_addr);
242void radeon_object_unpin(struct radeon_object *robj);
243int radeon_object_wait(struct radeon_object *robj);
244int radeon_object_evict_vram(struct radeon_device *rdev);
245int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
246void radeon_object_force_delete(struct radeon_device *rdev);
247void radeon_object_list_add_object(struct radeon_object_list *lobj,
248 struct list_head *head);
249int radeon_object_list_validate(struct list_head *head, void *fence);
250void radeon_object_list_unvalidate(struct list_head *head);
251void radeon_object_list_clean(struct list_head *head);
252int radeon_object_fbdev_mmap(struct radeon_object *robj,
253 struct vm_area_struct *vma);
254unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 255void radeon_object_clear_surface_reg(struct radeon_object *robj);
256int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
257 bool force_drop);
258void radeon_object_set_tiling_flags(struct radeon_object *robj,
259 uint32_t tiling_flags, uint32_t pitch);
260void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
261void radeon_bo_move_notify(struct ttm_buffer_object *bo,
262 struct ttm_mem_reg *mem);
263void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 264/*
265 * GEM objects.
266 */
267struct radeon_gem {
268 struct list_head objects;
269};
270
271int radeon_gem_init(struct radeon_device *rdev);
272void radeon_gem_fini(struct radeon_device *rdev);
273int radeon_gem_object_create(struct radeon_device *rdev, int size,
274 int alignment, int initial_domain,
275 bool discardable, bool kernel,
276 bool interruptible,
277 struct drm_gem_object **obj);
278int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
279 uint64_t *gpu_addr);
280void radeon_gem_object_unpin(struct drm_gem_object *obj);
281
282
283/*
284 * GART structures, functions & helpers
285 */
286struct radeon_mc;
287
288struct radeon_gart_table_ram {
289 volatile uint32_t *ptr;
290};
291
292struct radeon_gart_table_vram {
293 struct radeon_object *robj;
294 volatile uint32_t *ptr;
295};
296
297union radeon_gart_table {
298 struct radeon_gart_table_ram ram;
299 struct radeon_gart_table_vram vram;
300};
301
302struct radeon_gart {
303 dma_addr_t table_addr;
304 unsigned num_gpu_pages;
305 unsigned num_cpu_pages;
306 unsigned table_size;
307 union radeon_gart_table table;
308 struct page **pages;
309 dma_addr_t *pages_addr;
310 bool ready;
311};
312
313int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
314void radeon_gart_table_ram_free(struct radeon_device *rdev);
315int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
316void radeon_gart_table_vram_free(struct radeon_device *rdev);
317int radeon_gart_init(struct radeon_device *rdev);
318void radeon_gart_fini(struct radeon_device *rdev);
319void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
320 int pages);
321int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
322 int pages, struct page **pagelist);
323
324
325/*
326 * GPU MC structures, functions & helpers
327 */
328struct radeon_mc {
329 resource_size_t aper_size;
330 resource_size_t aper_base;
331 resource_size_t agp_base;
332 unsigned gtt_location;
333 unsigned gtt_size;
334 unsigned vram_location;
7a50f01a
DA		 335 /* for some chips with <= 32MB we need to lie
336 * about vram size near mc fb location */
337 unsigned mc_vram_size;
771fe6b9 338 unsigned vram_width;
7a50f01a 339 unsigned real_vram_size;
771fe6b9
JG		 340 int vram_mtrr;
341 bool vram_is_ddr;
342};
343
344int radeon_mc_setup(struct radeon_device *rdev);
345
346
347/*
348 * GPU scratch registers structures, functions & helpers
349 */
350struct radeon_scratch {
351 unsigned num_reg;
352 bool free[32];
353 uint32_t reg[32];
354};
355
356int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
357void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
358
359
360/*
361 * IRQS.
362 */
363struct radeon_irq {
364 bool installed;
365 bool sw_int;
366 /* FIXME: use a define max crtc rather than hardcode it */
367 bool crtc_vblank_int[2];
368};
369
370int radeon_irq_kms_init(struct radeon_device *rdev);
371void radeon_irq_kms_fini(struct radeon_device *rdev);
372
373
374/*
375 * CP & ring.
376 */
377struct radeon_ib {
378 struct list_head list;
379 unsigned long idx;
380 uint64_t gpu_addr;
381 struct radeon_fence *fence;
382 volatile uint32_t *ptr;
383 uint32_t length_dw;
384};
385
386struct radeon_ib_pool {
387 struct mutex mutex;
388 struct radeon_object *robj;
389 struct list_head scheduled_ibs;
390 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
391 bool ready;
392 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
393};
394
395struct radeon_cp {
396 struct radeon_object *ring_obj;
397 volatile uint32_t *ring;
398 unsigned rptr;
399 unsigned wptr;
400 unsigned wptr_old;
401 unsigned ring_size;
402 unsigned ring_free_dw;
403 int count_dw;
404 uint64_t gpu_addr;
405 uint32_t align_mask;
406 uint32_t ptr_mask;
407 struct mutex mutex;
408 bool ready;
409};
410
411int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
412void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
413int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
414int radeon_ib_pool_init(struct radeon_device *rdev);
415void radeon_ib_pool_fini(struct radeon_device *rdev);
416int radeon_ib_test(struct radeon_device *rdev);
417/* Ring access between begin & end cannot sleep */
418void radeon_ring_free_size(struct radeon_device *rdev);
419int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
420void radeon_ring_unlock_commit(struct radeon_device *rdev);
421void radeon_ring_unlock_undo(struct radeon_device *rdev);
422int radeon_ring_test(struct radeon_device *rdev);
423int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
424void radeon_ring_fini(struct radeon_device *rdev);
425
426
427/*
428 * CS.
429 */
430struct radeon_cs_reloc {
431 struct drm_gem_object *gobj;
432 struct radeon_object *robj;
433 struct radeon_object_list lobj;
434 uint32_t handle;
435 uint32_t flags;
436};
437
438struct radeon_cs_chunk {
439 uint32_t chunk_id;
440 uint32_t length_dw;
441 uint32_t *kdata;
442};
443
444struct radeon_cs_parser {
445 struct radeon_device *rdev;
446 struct drm_file *filp;
447 /* chunks */
448 unsigned nchunks;
449 struct radeon_cs_chunk *chunks;
450 uint64_t *chunks_array;
451 /* IB */
452 unsigned idx;
453 /* relocations */
454 unsigned nrelocs;
455 struct radeon_cs_reloc *relocs;
456 struct radeon_cs_reloc **relocs_ptr;
457 struct list_head validated;
458 /* indices of various chunks */
459 int chunk_ib_idx;
460 int chunk_relocs_idx;
461 struct radeon_ib *ib;
462 void *track;
463};
464
465struct radeon_cs_packet {
466 unsigned idx;
467 unsigned type;
468 unsigned reg;
469 unsigned opcode;
470 int count;
471 unsigned one_reg_wr;
472};
473
474typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
475 struct radeon_cs_packet *pkt,
476 unsigned idx, unsigned reg);
477typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
478 struct radeon_cs_packet *pkt);
479
480
481/*
482 * AGP
483 */
484int radeon_agp_init(struct radeon_device *rdev);
485void radeon_agp_fini(struct radeon_device *rdev);
486
487
488/*
489 * Writeback
490 */
491struct radeon_wb {
492 struct radeon_object *wb_obj;
493 volatile uint32_t *wb;
494 uint64_t gpu_addr;
495};
496
c93bb85b
JG		 497/**
498 * struct radeon_pm - power management datas
499 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
500 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
501 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
502 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
503 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
504 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
505 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
506 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
507 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
508 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
509 * @needed_bandwidth: current bandwidth needs
510 *
511 * It keeps track of various data needed to take powermanagement decision.
512 * Bandwith need is used to determine minimun clock of the GPU and memory.
513 * Equation between gpu/memory clock and available bandwidth is hw dependent
514 * (type of memory, bus size, efficiency, ...)
515 */
516struct radeon_pm {
517 fixed20_12 max_bandwidth;
518 fixed20_12 igp_sideport_mclk;
519 fixed20_12 igp_system_mclk;
520 fixed20_12 igp_ht_link_clk;
521 fixed20_12 igp_ht_link_width;
522 fixed20_12 k8_bandwidth;
523 fixed20_12 sideport_bandwidth;
524 fixed20_12 ht_bandwidth;
525 fixed20_12 core_bandwidth;
526 fixed20_12 sclk;
527 fixed20_12 needed_bandwidth;
528};
529
771fe6b9
JG		 530
531/*
532 * Benchmarking
533 */
534void radeon_benchmark(struct radeon_device *rdev);
535
536
537/*
538 * Debugfs
539 */
540int radeon_debugfs_add_files(struct radeon_device *rdev,
541 struct drm_info_list *files,
542 unsigned nfiles);
543int radeon_debugfs_fence_init(struct radeon_device *rdev);
544int r100_debugfs_rbbm_init(struct radeon_device *rdev);
545int r100_debugfs_cp_init(struct radeon_device *rdev);
546
547
548/*
549 * ASIC specific functions.
550 */
551struct radeon_asic {
068a117c 552 int (*init)(struct radeon_device *rdev);
771fe6b9
JG		 553 void (*errata)(struct radeon_device *rdev);
554 void (*vram_info)(struct radeon_device *rdev);
555 int (*gpu_reset)(struct radeon_device *rdev);
556 int (*mc_init)(struct radeon_device *rdev);
557 void (*mc_fini)(struct radeon_device *rdev);
558 int (*wb_init)(struct radeon_device *rdev);
559 void (*wb_fini)(struct radeon_device *rdev);
560 int (*gart_enable)(struct radeon_device *rdev);
561 void (*gart_disable)(struct radeon_device *rdev);
562 void (*gart_tlb_flush)(struct radeon_device *rdev);
563 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
564 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
565 void (*cp_fini)(struct radeon_device *rdev);
566 void (*cp_disable)(struct radeon_device *rdev);
567 void (*ring_start)(struct radeon_device *rdev);
568 int (*irq_set)(struct radeon_device *rdev);
569 int (*irq_process)(struct radeon_device *rdev);
570 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
571 int (*cs_parse)(struct radeon_cs_parser *p);
572 int (*copy_blit)(struct radeon_device *rdev,
573 uint64_t src_offset,
574 uint64_t dst_offset,
575 unsigned num_pages,
576 struct radeon_fence *fence);
577 int (*copy_dma)(struct radeon_device *rdev,
578 uint64_t src_offset,
579 uint64_t dst_offset,
580 unsigned num_pages,
581 struct radeon_fence *fence);
582 int (*copy)(struct radeon_device *rdev,
583 uint64_t src_offset,
584 uint64_t dst_offset,
585 unsigned num_pages,
586 struct radeon_fence *fence);
587 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
588 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
589 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
590 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 591 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
592 uint32_t tiling_flags, uint32_t pitch,
593 uint32_t offset, uint32_t obj_size);
594 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 595 void (*bandwidth_update)(struct radeon_device *rdev);
771fe6b9
JG		 596};
597
068a117c
JG		 598union radeon_asic_config {
599 struct r300_asic r300;
600};
601
771fe6b9
JG		 602
603/*
604 * IOCTL.
605 */
606int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
607 struct drm_file *filp);
608int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
609 struct drm_file *filp);
610int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
611 struct drm_file *file_priv);
612int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
613 struct drm_file *file_priv);
614int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
615 struct drm_file *file_priv);
616int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
617 struct drm_file *file_priv);
618int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
619 struct drm_file *filp);
620int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
621 struct drm_file *filp);
622int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
623 struct drm_file *filp);
624int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
625 struct drm_file *filp);
626int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 627int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
628 struct drm_file *filp);
629int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
630 struct drm_file *filp);
771fe6b9
JG		 631
632
633/*
634 * Core structure, functions and helpers.
635 */
636typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
637typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
638
639struct radeon_device {
640 struct drm_device *ddev;
641 struct pci_dev *pdev;
642 /* ASIC */
068a117c 643 union radeon_asic_config config;
771fe6b9
JG		 644 enum radeon_family family;
645 unsigned long flags;
646 int usec_timeout;
647 enum radeon_pll_errata pll_errata;
648 int num_gb_pipes;
649 int disp_priority;
650 /* BIOS */
651 uint8_t *bios;
652 bool is_atom_bios;
653 uint16_t bios_header_start;
654 struct radeon_object *stollen_vga_memory;
655 struct fb_info *fbdev_info;
656 struct radeon_object *fbdev_robj;
657 struct radeon_framebuffer *fbdev_rfb;
658 /* Register mmio */
4c9bc75c
DA		 659 resource_size_t rmmio_base;
660 resource_size_t rmmio_size;
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JG		 661 void *rmmio;
662 radeon_rreg_t mm_rreg;
663 radeon_wreg_t mm_wreg;
664 radeon_rreg_t mc_rreg;
665 radeon_wreg_t mc_wreg;
666 radeon_rreg_t pll_rreg;
667 radeon_wreg_t pll_wreg;
668 radeon_rreg_t pcie_rreg;
669 radeon_wreg_t pcie_wreg;
670 radeon_rreg_t pciep_rreg;
671 radeon_wreg_t pciep_wreg;
672 struct radeon_clock clock;
673 struct radeon_mc mc;
674 struct radeon_gart gart;
675 struct radeon_mode_info mode_info;
676 struct radeon_scratch scratch;
677 struct radeon_mman mman;
678 struct radeon_fence_driver fence_drv;
679 struct radeon_cp cp;
680 struct radeon_ib_pool ib_pool;
681 struct radeon_irq irq;
682 struct radeon_asic *asic;
683 struct radeon_gem gem;
c93bb85b 684 struct radeon_pm pm;
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JG		 685 struct mutex cs_mutex;
686 struct radeon_wb wb;
687 bool gpu_lockup;
688 bool shutdown;
689 bool suspend;
ad49f501 690 bool need_dma32;
e024e110 691 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
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JG		 692};
693
694int radeon_device_init(struct radeon_device *rdev,
695 struct drm_device *ddev,
696 struct pci_dev *pdev,
697 uint32_t flags);
698void radeon_device_fini(struct radeon_device *rdev);
699int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
700
701
702/*
703 * Registers read & write functions.
704 */
705#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
706#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
707#define RREG32(reg) rdev->mm_rreg(rdev, (reg))
708#define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v))
709#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
710#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
711#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
712#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
713#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
714#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
715#define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg))
716#define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v))
717#define WREG32_P(reg, val, mask) \
718 do { \
719 uint32_t tmp_ = RREG32(reg); \
720 tmp_ &= (mask); \
721 tmp_ |= ((val) & ~(mask)); \
722 WREG32(reg, tmp_); \
723 } while (0)
724#define WREG32_PLL_P(reg, val, mask) \
725 do { \
726 uint32_t tmp_ = RREG32_PLL(reg); \
727 tmp_ &= (mask); \
728 tmp_ |= ((val) & ~(mask)); \
729 WREG32_PLL(reg, tmp_); \
730 } while (0)
731
732void r100_pll_errata_after_index(struct radeon_device *rdev);
733
734
735/*
736 * ASICs helpers.
737 */
b995e433
DA		 738#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
739 (rdev->pdev->device == 0x5969))
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JG		 740#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
741 (rdev->family == CHIP_RV200) || \
742 (rdev->family == CHIP_RS100) || \
743 (rdev->family == CHIP_RS200) || \
744 (rdev->family == CHIP_RV250) || \
745 (rdev->family == CHIP_RV280) || \
746 (rdev->family == CHIP_RS300))
747#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
748 (rdev->family == CHIP_RV350) || \
749 (rdev->family == CHIP_R350) || \
750 (rdev->family == CHIP_RV380) || \
751 (rdev->family == CHIP_R420) || \
752 (rdev->family == CHIP_R423) || \
753 (rdev->family == CHIP_RV410) || \
754 (rdev->family == CHIP_RS400) || \
755 (rdev->family == CHIP_RS480))
756#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
757#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
758#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
759
760
761/*
762 * BIOS helpers.
763 */
764#define RBIOS8(i) (rdev->bios[i])
765#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
766#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
767
768int radeon_combios_init(struct radeon_device *rdev);
769void radeon_combios_fini(struct radeon_device *rdev);
770int radeon_atombios_init(struct radeon_device *rdev);
771void radeon_atombios_fini(struct radeon_device *rdev);
772
773
774/*
775 * RING helpers.
776 */
777#define CP_PACKET0 0x00000000
778#define PACKET0_BASE_INDEX_SHIFT 0
779#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
780#define PACKET0_COUNT_SHIFT 16
781#define PACKET0_COUNT_MASK (0x3fff << 16)
782#define CP_PACKET1 0x40000000
783#define CP_PACKET2 0x80000000
784#define PACKET2_PAD_SHIFT 0
785#define PACKET2_PAD_MASK (0x3fffffff << 0)
786#define CP_PACKET3 0xC0000000
787#define PACKET3_IT_OPCODE_SHIFT 8
788#define PACKET3_IT_OPCODE_MASK (0xff << 8)
789#define PACKET3_COUNT_SHIFT 16
790#define PACKET3_COUNT_MASK (0x3fff << 16)
791/* PACKET3 op code */
792#define PACKET3_NOP 0x10
793#define PACKET3_3D_DRAW_VBUF 0x28
794#define PACKET3_3D_DRAW_IMMD 0x29
795#define PACKET3_3D_DRAW_INDX 0x2A
796#define PACKET3_3D_LOAD_VBPNTR 0x2F
797#define PACKET3_INDX_BUFFER 0x33
798#define PACKET3_3D_DRAW_VBUF_2 0x34
799#define PACKET3_3D_DRAW_IMMD_2 0x35
800#define PACKET3_3D_DRAW_INDX_2 0x36
801#define PACKET3_BITBLT_MULTI 0x9B
802
803#define PACKET0(reg, n) (CP_PACKET0 | \
804 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
805 REG_SET(PACKET0_COUNT, (n)))
806#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
807#define PACKET3(op, n) (CP_PACKET3 | \
808 REG_SET(PACKET3_IT_OPCODE, (op)) | \
809 REG_SET(PACKET3_COUNT, (n)))
810
811#define PACKET_TYPE0 0
812#define PACKET_TYPE1 1
813#define PACKET_TYPE2 2
814#define PACKET_TYPE3 3
815
816#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
817#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
818#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
819#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
820#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
821
822static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
823{
824#if DRM_DEBUG_CODE
825 if (rdev->cp.count_dw <= 0) {
826 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
827 }
828#endif
829 rdev->cp.ring[rdev->cp.wptr++] = v;
830 rdev->cp.wptr &= rdev->cp.ptr_mask;
831 rdev->cp.count_dw--;
832 rdev->cp.ring_free_dw--;
833}
834
835
836/*
837 * ASICs macro.
838 */
068a117c 839#define radeon_init(rdev) (rdev)->asic->init((rdev))
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JG		 840#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
841#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
842#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
843#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
844#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
845#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
846#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
847#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
848#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
849#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
850#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
851#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
852#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
853#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
854#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
855#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
856#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
857#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
858#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
859#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
860#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
861#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
862#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
863#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
864#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
865#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 866#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
867#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 868#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
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JG		 869
870#endif
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