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Merge branch 'fix/asoc' into for-linus
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600_cs.c
CommitLineData
3ce0a23d
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
40e2a5c1 28#include <linux/kernel.h>
3ce0a23d
JG		 29#include "drmP.h"
30#include "radeon.h"
3ce0a23d 31#include "r600d.h"
961fb597 32#include "r600_reg_safe.h"
3ce0a23d
JG		 33
34static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
961fb597
JG		 40extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
3ce0a23d 42
c8c15ff1 43struct r600_cs_track {
961fb597
JG		 44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
5f77df36 49 u32 sq_config;
961fb597
JG		 50 u32 nsamples;
51 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8];
53 u32 cb_color_bo_offset[8];
54 struct radeon_bo *cb_color_frag_bo[8];
55 struct radeon_bo *cb_color_tile_bo[8];
56 u32 cb_color_info[8];
57 u32 cb_color_size_idx[8];
58 u32 cb_target_mask;
59 u32 cb_shader_mask;
60 u32 cb_color_size[8];
61 u32 vgt_strmout_en;
62 u32 vgt_strmout_buffer_en;
63 u32 db_depth_control;
64 u32 db_depth_info;
65 u32 db_depth_size_idx;
66 u32 db_depth_view;
67 u32 db_depth_size;
68 u32 db_offset;
69 struct radeon_bo *db_bo;
c8c15ff1
JG		 70};
71
961fb597
JG		 72static inline int r600_bpe_from_format(u32 *bpe, u32 format)
73{
74 switch (format) {
75 case V_038004_COLOR_8:
76 case V_038004_COLOR_4_4:
77 case V_038004_COLOR_3_3_2:
78 case V_038004_FMT_1:
79 *bpe = 1;
80 break;
81 case V_038004_COLOR_16:
82 case V_038004_COLOR_16_FLOAT:
83 case V_038004_COLOR_8_8:
84 case V_038004_COLOR_5_6_5:
85 case V_038004_COLOR_6_5_5:
86 case V_038004_COLOR_1_5_5_5:
87 case V_038004_COLOR_4_4_4_4:
88 case V_038004_COLOR_5_5_5_1:
89 *bpe = 2;
90 break;
91 case V_038004_FMT_8_8_8:
92 *bpe = 3;
93 break;
94 case V_038004_COLOR_32:
95 case V_038004_COLOR_32_FLOAT:
96 case V_038004_COLOR_16_16:
97 case V_038004_COLOR_16_16_FLOAT:
98 case V_038004_COLOR_8_24:
99 case V_038004_COLOR_8_24_FLOAT:
100 case V_038004_COLOR_24_8:
101 case V_038004_COLOR_24_8_FLOAT:
102 case V_038004_COLOR_10_11_11:
103 case V_038004_COLOR_10_11_11_FLOAT:
104 case V_038004_COLOR_11_11_10:
105 case V_038004_COLOR_11_11_10_FLOAT:
106 case V_038004_COLOR_2_10_10_10:
107 case V_038004_COLOR_8_8_8_8:
108 case V_038004_COLOR_10_10_10_2:
109 case V_038004_FMT_5_9_9_9_SHAREDEXP:
110 case V_038004_FMT_32_AS_8:
111 case V_038004_FMT_32_AS_8_8:
112 *bpe = 4;
113 break;
114 case V_038004_COLOR_X24_8_32_FLOAT:
115 case V_038004_COLOR_32_32:
116 case V_038004_COLOR_32_32_FLOAT:
117 case V_038004_COLOR_16_16_16_16:
118 case V_038004_COLOR_16_16_16_16_FLOAT:
119 *bpe = 8;
120 break;
121 case V_038004_FMT_16_16_16:
122 case V_038004_FMT_16_16_16_FLOAT:
123 *bpe = 6;
124 break;
125 case V_038004_FMT_32_32_32:
126 case V_038004_FMT_32_32_32_FLOAT:
127 *bpe = 12;
128 break;
129 case V_038004_COLOR_32_32_32_32:
130 case V_038004_COLOR_32_32_32_32_FLOAT:
131 *bpe = 16;
132 break;
133 case V_038004_FMT_GB_GR:
134 case V_038004_FMT_BG_RG:
135 case V_038004_COLOR_INVALID:
618145ea 136 default:
961fb597
JG		 137 *bpe = 16;
138 return -EINVAL;
139 }
140 return 0;
141}
142
143static void r600_cs_track_init(struct r600_cs_track *track)
144{
145 int i;
146
5f77df36
AD		 147 /* assume DX9 mode */
148 track->sq_config = DX9_CONSTS;
961fb597
JG		 149 for (i = 0; i < 8; i++) {
150 track->cb_color_base_last[i] = 0;
151 track->cb_color_size[i] = 0;
152 track->cb_color_size_idx[i] = 0;
153 track->cb_color_info[i] = 0;
154 track->cb_color_bo[i] = NULL;
155 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
156 }
157 track->cb_target_mask = 0xFFFFFFFF;
158 track->cb_shader_mask = 0xFFFFFFFF;
159 track->db_bo = NULL;
160 /* assume the biggest format and that htile is enabled */
161 track->db_depth_info = 7 | (1 << 25);
162 track->db_depth_view = 0xFFFFC000;
163 track->db_depth_size = 0xFFFFFFFF;
164 track->db_depth_size_idx = 0;
165 track->db_depth_control = 0xFFFFFFFF;
166}
167
168static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
169{
170 struct r600_cs_track *track = p->track;
40e2a5c1 171 u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
961fb597
JG		 172 volatile u32 *ib = p->ib->ptr;
173
174 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
175 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
176 return -EINVAL;
177 }
1729dd33 178 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
961fb597
JG		 179 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
180 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
181 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
182 i, track->cb_color_info[i]);
183 return -EINVAL;
184 }
40e2a5c1
AD		 185 /* pitch is the number of 8x8 tiles per row */
186 pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
961fb597 187 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
40e2a5c1 188 height = size / (pitch * 8 * bpe);
961fb597
JG		 189 if (height > 8192)
190 height = 8192;
40e2a5c1
AD		 191 if (height > 7)
192 height &= ~0x7;
961fb597
JG		 193 switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
194 case V_0280A0_ARRAY_LINEAR_GENERAL:
40e2a5c1
AD		 195 /* technically height & 0x7 */
196 break;
961fb597 197 case V_0280A0_ARRAY_LINEAR_ALIGNED:
40e2a5c1
AD		 198 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
199 if (!IS_ALIGNED(pitch, pitch_align)) {
200 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
201 __func__, __LINE__, pitch);
961fb597
JG		 202 return -EINVAL;
203 }
40e2a5c1
AD		 204 if (!IS_ALIGNED(height, 8)) {
205 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
206 __func__, __LINE__, height);
961fb597
JG		 207 return -EINVAL;
208 }
209 break;
210 case V_0280A0_ARRAY_1D_TILED_THIN1:
40e2a5c1
AD		 211 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
212 if (!IS_ALIGNED(pitch, pitch_align)) {
961fb597 213 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
40e2a5c1
AD		 214 __func__, __LINE__, pitch);
215 return -EINVAL;
216 }
217 if (!IS_ALIGNED(height, 8)) {
218 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
219 __func__, __LINE__, height);
961fb597
JG		 220 return -EINVAL;
221 }
961fb597
JG		 222 break;
223 case V_0280A0_ARRAY_2D_TILED_THIN1:
40e2a5c1
AD		 224 pitch_align = max((u32)track->nbanks,
225 (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks));
226 if (!IS_ALIGNED(pitch, pitch_align)) {
961fb597
JG		 227 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
228 __func__, __LINE__, pitch);
229 return -EINVAL;
230 }
40e2a5c1
AD		 231 if (!IS_ALIGNED((height / 8), track->nbanks)) {
232 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
233 __func__, __LINE__, height);
961fb597
JG		 234 return -EINVAL;
235 }
961fb597
JG		 236 break;
237 default:
238 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
239 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
240 track->cb_color_info[i]);
241 return -EINVAL;
242 }
243 /* check offset */
40e2a5c1 244 tmp = height * pitch * 8 * bpe;
961fb597 245 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
40e2a5c1
AD		 246 dev_warn(p->dev, "%s offset[%d] %d too big\n", __func__, i, track->cb_color_bo_offset[i]);
247 return -EINVAL;
248 }
249 if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
250 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
961fb597
JG		 251 return -EINVAL;
252 }
253 /* limit max tile */
40e2a5c1 254 tmp = (height * pitch * 8) >> 6;
961fb597
JG		 255 if (tmp < slice_tile_max)
256 slice_tile_max = tmp;
40e2a5c1 257 tmp = S_028060_PITCH_TILE_MAX(pitch - 1) |
961fb597
JG		 258 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
259 ib[track->cb_color_size_idx[i]] = tmp;
260 return 0;
261}
262
263static int r600_cs_track_check(struct radeon_cs_parser *p)
264{
265 struct r600_cs_track *track = p->track;
266 u32 tmp;
267 int r, i;
268 volatile u32 *ib = p->ib->ptr;
269
270 /* on legacy kernel we don't perform advanced check */
271 if (p->rdev == NULL)
272 return 0;
273 /* we don't support out buffer yet */
274 if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
275 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
276 return -EINVAL;
277 }
278 /* check that we have a cb for each enabled target, we don't check
279 * shader_mask because it seems mesa isn't always setting it :(
280 */
281 tmp = track->cb_target_mask;
282 for (i = 0; i < 8; i++) {
283 if ((tmp >> (i * 4)) & 0xF) {
284 /* at least one component is enabled */
285 if (track->cb_color_bo[i] == NULL) {
286 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
287 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
288 return -EINVAL;
289 }
290 /* perform rewrite of CB_COLOR[0-7]_SIZE */
291 r = r600_cs_track_validate_cb(p, i);
292 if (r)
293 return r;
294 }
295 }
296 /* Check depth buffer */
297 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
298 G_028800_Z_ENABLE(track->db_depth_control)) {
40e2a5c1 299 u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;
961fb597
JG		 300 if (track->db_bo == NULL) {
301 dev_warn(p->dev, "z/stencil with no depth buffer\n");
302 return -EINVAL;
303 }
304 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
305 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
306 return -EINVAL;
307 }
308 switch (G_028010_FORMAT(track->db_depth_info)) {
309 case V_028010_DEPTH_16:
310 bpe = 2;
311 break;
312 case V_028010_DEPTH_X8_24:
313 case V_028010_DEPTH_8_24:
314 case V_028010_DEPTH_X8_24_FLOAT:
315 case V_028010_DEPTH_8_24_FLOAT:
316 case V_028010_DEPTH_32_FLOAT:
317 bpe = 4;
318 break;
319 case V_028010_DEPTH_X24_8_32_FLOAT:
320 bpe = 8;
321 break;
322 default:
323 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
324 return -EINVAL;
325 }
326 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
327 if (!track->db_depth_size_idx) {
328 dev_warn(p->dev, "z/stencil buffer size not set\n");
329 return -EINVAL;
330 }
961fb597
JG		 331 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
332 tmp = (tmp / bpe) >> 6;
333 if (!tmp) {
334 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
335 track->db_depth_size, bpe, track->db_offset,
336 radeon_bo_size(track->db_bo));
337 return -EINVAL;
338 }
339 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
340 } else {
40e2a5c1
AD		 341 size = radeon_bo_size(track->db_bo);
342 pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
343 height = size / (pitch * 8 * bpe);
344 height &= ~0x7;
345 if (!height)
346 height = 8;
347
348 switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
349 case V_028010_ARRAY_1D_TILED_THIN1:
350 pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
351 if (!IS_ALIGNED(pitch, pitch_align)) {
352 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
353 __func__, __LINE__, pitch);
354 return -EINVAL;
355 }
356 if (!IS_ALIGNED(height, 8)) {
357 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
358 __func__, __LINE__, height);
359 return -EINVAL;
360 }
361 break;
362 case V_028010_ARRAY_2D_TILED_THIN1:
363 pitch_align = max((u32)track->nbanks,
364 (u32)(((track->group_size / 8) / bpe) * track->nbanks));
365 if (!IS_ALIGNED(pitch, pitch_align)) {
366 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
367 __func__, __LINE__, pitch);
368 return -EINVAL;
369 }
370 if ((height / 8) & (track->nbanks - 1)) {
371 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
372 __func__, __LINE__, height);
373 return -EINVAL;
374 }
375 break;
376 default:
377 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
378 G_028010_ARRAY_MODE(track->db_depth_info),
379 track->db_depth_info);
380 return -EINVAL;
381 }
382 if (!IS_ALIGNED(track->db_offset, track->group_size)) {
383 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset);
384 return -EINVAL;
385 }
961fb597
JG		 386 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
387 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
388 tmp = ntiles * bpe * 64 * nviews;
389 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
390 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
391 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
392 radeon_bo_size(track->db_bo));
393 return -EINVAL;
394 }
395 }
396 }
397 return 0;
398}
399
3ce0a23d
JG		 400/**
401 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
402 * @parser: parser structure holding parsing context.
403 * @pkt: where to store packet informations
404 *
405 * Assume that chunk_ib_index is properly set. Will return -EINVAL
406 * if packet is bigger than remaining ib size. or if packets is unknown.
407 **/
408int r600_cs_packet_parse(struct radeon_cs_parser *p,
409 struct radeon_cs_packet *pkt,
410 unsigned idx)
411{
412 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
413 uint32_t header;
414
415 if (idx >= ib_chunk->length_dw) {
416 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
417 idx, ib_chunk->length_dw);
418 return -EINVAL;
419 }
513bcb46 420 header = radeon_get_ib_value(p, idx);
3ce0a23d
JG		 421 pkt->idx = idx;
422 pkt->type = CP_PACKET_GET_TYPE(header);
423 pkt->count = CP_PACKET_GET_COUNT(header);
424 pkt->one_reg_wr = 0;
425 switch (pkt->type) {
426 case PACKET_TYPE0:
427 pkt->reg = CP_PACKET0_GET_REG(header);
428 break;
429 case PACKET_TYPE3:
430 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
431 break;
432 case PACKET_TYPE2:
433 pkt->count = -1;
434 break;
435 default:
436 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
437 return -EINVAL;
438 }
439 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
440 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
441 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
442 return -EINVAL;
443 }
444 return 0;
445}
446
447/**
448 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
449 * @parser: parser structure holding parsing context.
450 * @data: pointer to relocation data
451 * @offset_start: starting offset
452 * @offset_mask: offset mask (to align start offset on)
453 * @reloc: reloc informations
454 *
455 * Check next packet is relocation packet3, do bo validation and compute
456 * GPU offset using the provided start.
457 **/
458static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
459 struct radeon_cs_reloc **cs_reloc)
460{
3ce0a23d
JG		 461 struct radeon_cs_chunk *relocs_chunk;
462 struct radeon_cs_packet p3reloc;
463 unsigned idx;
464 int r;
465
466 if (p->chunk_relocs_idx == -1) {
467 DRM_ERROR("No relocation chunk !\n");
468 return -EINVAL;
469 }
470 *cs_reloc = NULL;
3ce0a23d
JG		 471 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
472 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
473 if (r) {
474 return r;
475 }
476 p->idx += p3reloc.count + 2;
477 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
478 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
479 p3reloc.idx);
480 return -EINVAL;
481 }
513bcb46 482 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 483 if (idx >= relocs_chunk->length_dw) {
484 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
485 idx, relocs_chunk->length_dw);
486 return -EINVAL;
487 }
488 /* FIXME: we assume reloc size is 4 dwords */
489 *cs_reloc = p->relocs_ptr[(idx / 4)];
490 return 0;
491}
492
493/**
494 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
495 * @parser: parser structure holding parsing context.
496 * @data: pointer to relocation data
497 * @offset_start: starting offset
498 * @offset_mask: offset mask (to align start offset on)
499 * @reloc: reloc informations
500 *
501 * Check next packet is relocation packet3, do bo validation and compute
502 * GPU offset using the provided start.
503 **/
504static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
505 struct radeon_cs_reloc **cs_reloc)
506{
3ce0a23d
JG		 507 struct radeon_cs_chunk *relocs_chunk;
508 struct radeon_cs_packet p3reloc;
509 unsigned idx;
510 int r;
511
512 if (p->chunk_relocs_idx == -1) {
513 DRM_ERROR("No relocation chunk !\n");
514 return -EINVAL;
515 }
516 *cs_reloc = NULL;
3ce0a23d
JG		 517 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
518 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
519 if (r) {
520 return r;
521 }
522 p->idx += p3reloc.count + 2;
523 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
524 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
525 p3reloc.idx);
526 return -EINVAL;
527 }
513bcb46 528 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 529 if (idx >= relocs_chunk->length_dw) {
530 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
531 idx, relocs_chunk->length_dw);
532 return -EINVAL;
533 }
e265f39e 534 *cs_reloc = p->relocs;
3ce0a23d
JG		 535 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
536 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
537 return 0;
538}
539
c8c15ff1
JG		 540/**
541 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
542 * @parser: parser structure holding parsing context.
543 *
544 * Check next packet is relocation packet3, do bo validation and compute
545 * GPU offset using the provided start.
546 **/
547static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
548{
549 struct radeon_cs_packet p3reloc;
550 int r;
551
552 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
553 if (r) {
554 return 0;
555 }
556 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
557 return 0;
558 }
559 return 1;
560}
561
2f67c6e0
AD		 562/**
563 * r600_cs_packet_next_vline() - parse userspace VLINE packet
564 * @parser: parser structure holding parsing context.
565 *
566 * Userspace sends a special sequence for VLINE waits.
567 * PACKET0 - VLINE_START_END + value
568 * PACKET3 - WAIT_REG_MEM poll vline status reg
569 * RELOC (P3) - crtc_id in reloc.
570 *
571 * This function parses this and relocates the VLINE START END
572 * and WAIT_REG_MEM packets to the correct crtc.
573 * It also detects a switched off crtc and nulls out the
574 * wait in that case.
575 */
576static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
577{
578 struct drm_mode_object *obj;
579 struct drm_crtc *crtc;
580 struct radeon_crtc *radeon_crtc;
581 struct radeon_cs_packet p3reloc, wait_reg_mem;
582 int crtc_id;
583 int r;
584 uint32_t header, h_idx, reg, wait_reg_mem_info;
585 volatile uint32_t *ib;
586
587 ib = p->ib->ptr;
588
589 /* parse the WAIT_REG_MEM */
590 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
591 if (r)
592 return r;
593
594 /* check its a WAIT_REG_MEM */
595 if (wait_reg_mem.type != PACKET_TYPE3 ||
596 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
597 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
598 r = -EINVAL;
599 return r;
600 }
601
602 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
603 /* bit 4 is reg (0) or mem (1) */
604 if (wait_reg_mem_info & 0x10) {
605 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
606 r = -EINVAL;
607 return r;
608 }
609 /* waiting for value to be equal */
610 if ((wait_reg_mem_info & 0x7) != 0x3) {
611 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
612 r = -EINVAL;
613 return r;
614 }
615 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
616 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
617 r = -EINVAL;
618 return r;
619 }
620
621 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
622 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
623 r = -EINVAL;
624 return r;
625 }
626
627 /* jump over the NOP */
628 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
629 if (r)
630 return r;
631
632 h_idx = p->idx - 2;
633 p->idx += wait_reg_mem.count + 2;
634 p->idx += p3reloc.count + 2;
635
636 header = radeon_get_ib_value(p, h_idx);
637 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
d4ac6a05 638 reg = CP_PACKET0_GET_REG(header);
29508eb6 639
2f67c6e0
AD		 640 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
641 if (!obj) {
642 DRM_ERROR("cannot find crtc %d\n", crtc_id);
643 r = -EINVAL;
644 goto out;
645 }
646 crtc = obj_to_crtc(obj);
647 radeon_crtc = to_radeon_crtc(crtc);
648 crtc_id = radeon_crtc->crtc_id;
649
650 if (!crtc->enabled) {
651 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
652 ib[h_idx + 2] = PACKET2(0);
653 ib[h_idx + 3] = PACKET2(0);
654 ib[h_idx + 4] = PACKET2(0);
655 ib[h_idx + 5] = PACKET2(0);
656 ib[h_idx + 6] = PACKET2(0);
657 ib[h_idx + 7] = PACKET2(0);
658 ib[h_idx + 8] = PACKET2(0);
659 } else if (crtc_id == 1) {
660 switch (reg) {
661 case AVIVO_D1MODE_VLINE_START_END:
662 header &= ~R600_CP_PACKET0_REG_MASK;
663 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
664 break;
665 default:
666 DRM_ERROR("unknown crtc reloc\n");
667 r = -EINVAL;
668 goto out;
669 }
670 ib[h_idx] = header;
671 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
672 }
673out:
2f67c6e0
AD		 674 return r;
675}
676
3ce0a23d
JG		 677static int r600_packet0_check(struct radeon_cs_parser *p,
678 struct radeon_cs_packet *pkt,
679 unsigned idx, unsigned reg)
680{
2f67c6e0
AD		 681 int r;
682
3ce0a23d
JG		 683 switch (reg) {
684 case AVIVO_D1MODE_VLINE_START_END:
2f67c6e0
AD		 685 r = r600_cs_packet_parse_vline(p);
686 if (r) {
687 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
688 idx, reg);
689 return r;
690 }
3ce0a23d
JG		 691 break;
692 default:
693 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
694 reg, idx);
695 return -EINVAL;
696 }
697 return 0;
698}
699
700static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
701 struct radeon_cs_packet *pkt)
702{
703 unsigned reg, i;
704 unsigned idx;
705 int r;
706
707 idx = pkt->idx + 1;
708 reg = pkt->reg;
709 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
710 r = r600_packet0_check(p, pkt, idx, reg);
711 if (r) {
712 return r;
713 }
714 }
715 return 0;
716}
717
961fb597
JG		 718/**
719 * r600_cs_check_reg() - check if register is authorized or not
720 * @parser: parser structure holding parsing context
721 * @reg: register we are testing
722 * @idx: index into the cs buffer
723 *
724 * This function will test against r600_reg_safe_bm and return 0
725 * if register is safe. If register is not flag as safe this function
726 * will test it against a list of register needind special handling.
727 */
728static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
729{
730 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
731 struct radeon_cs_reloc *reloc;
732 u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
733 u32 m, i, tmp, *ib;
734 int r;
735
736 i = (reg >> 7);
737 if (i > last_reg) {
738 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
739 return -EINVAL;
740 }
741 m = 1 << ((reg >> 2) & 31);
742 if (!(r600_reg_safe_bm[i] & m))
743 return 0;
744 ib = p->ib->ptr;
745 switch (reg) {
746 /* force following reg to 0 in an attemp to disable out buffer
747 * which will need us to better understand how it works to perform
748 * security check on it (Jerome)
749 */
750 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
751 case R_008C44_SQ_ESGS_RING_SIZE:
752 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
753 case R_008C54_SQ_ESTMP_RING_SIZE:
754 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
755 case R_008C74_SQ_FBUF_RING_SIZE:
756 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
757 case R_008C5C_SQ_GSTMP_RING_SIZE:
758 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
759 case R_008C4C_SQ_GSVS_RING_SIZE:
760 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
761 case R_008C6C_SQ_PSTMP_RING_SIZE:
762 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
763 case R_008C7C_SQ_REDUC_RING_SIZE:
764 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
765 case R_008C64_SQ_VSTMP_RING_SIZE:
766 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
767 /* get value to populate the IB don't remove */
768 tmp =radeon_get_ib_value(p, idx);
769 ib[idx] = 0;
770 break;
5f77df36
AD		 771 case SQ_CONFIG:
772 track->sq_config = radeon_get_ib_value(p, idx);
773 break;
961fb597
JG		 774 case R_028800_DB_DEPTH_CONTROL:
775 track->db_depth_control = radeon_get_ib_value(p, idx);
776 break;
777 case R_028010_DB_DEPTH_INFO:
7f813377
AD		 778 if (r600_cs_packet_next_is_pkt3_nop(p)) {
779 r = r600_cs_packet_next_reloc(p, &reloc);
780 if (r) {
781 dev_warn(p->dev, "bad SET_CONTEXT_REG "
782 "0x%04X\n", reg);
783 return -EINVAL;
784 }
785 track->db_depth_info = radeon_get_ib_value(p, idx);
786 ib[idx] &= C_028010_ARRAY_MODE;
787 track->db_depth_info &= C_028010_ARRAY_MODE;
788 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
789 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
790 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
791 } else {
792 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
793 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
794 }
795 } else
796 track->db_depth_info = radeon_get_ib_value(p, idx);
961fb597
JG		 797 break;
798 case R_028004_DB_DEPTH_VIEW:
799 track->db_depth_view = radeon_get_ib_value(p, idx);
800 break;
801 case R_028000_DB_DEPTH_SIZE:
802 track->db_depth_size = radeon_get_ib_value(p, idx);
803 track->db_depth_size_idx = idx;
804 break;
805 case R_028AB0_VGT_STRMOUT_EN:
806 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
807 break;
808 case R_028B20_VGT_STRMOUT_BUFFER_EN:
809 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
810 break;
811 case R_028238_CB_TARGET_MASK:
812 track->cb_target_mask = radeon_get_ib_value(p, idx);
813 break;
814 case R_02823C_CB_SHADER_MASK:
815 track->cb_shader_mask = radeon_get_ib_value(p, idx);
816 break;
817 case R_028C04_PA_SC_AA_CONFIG:
818 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
819 track->nsamples = 1 << tmp;
820 break;
821 case R_0280A0_CB_COLOR0_INFO:
822 case R_0280A4_CB_COLOR1_INFO:
823 case R_0280A8_CB_COLOR2_INFO:
824 case R_0280AC_CB_COLOR3_INFO:
825 case R_0280B0_CB_COLOR4_INFO:
826 case R_0280B4_CB_COLOR5_INFO:
827 case R_0280B8_CB_COLOR6_INFO:
828 case R_0280BC_CB_COLOR7_INFO:
7f813377
AD		 829 if (r600_cs_packet_next_is_pkt3_nop(p)) {
830 r = r600_cs_packet_next_reloc(p, &reloc);
831 if (r) {
832 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
833 return -EINVAL;
834 }
835 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
836 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
837 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
838 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
839 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
840 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
841 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
842 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
843 }
844 } else {
845 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
846 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
847 }
961fb597
JG		 848 break;
849 case R_028060_CB_COLOR0_SIZE:
850 case R_028064_CB_COLOR1_SIZE:
851 case R_028068_CB_COLOR2_SIZE:
852 case R_02806C_CB_COLOR3_SIZE:
853 case R_028070_CB_COLOR4_SIZE:
854 case R_028074_CB_COLOR5_SIZE:
855 case R_028078_CB_COLOR6_SIZE:
856 case R_02807C_CB_COLOR7_SIZE:
857 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
858 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
859 track->cb_color_size_idx[tmp] = idx;
860 break;
861 /* This register were added late, there is userspace
862 * which does provide relocation for those but set
863 * 0 offset. In order to avoid breaking old userspace
864 * we detect this and set address to point to last
865 * CB_COLOR0_BASE, note that if userspace doesn't set
866 * CB_COLOR0_BASE before this register we will report
867 * error. Old userspace always set CB_COLOR0_BASE
868 * before any of this.
869 */
870 case R_0280E0_CB_COLOR0_FRAG:
871 case R_0280E4_CB_COLOR1_FRAG:
872 case R_0280E8_CB_COLOR2_FRAG:
873 case R_0280EC_CB_COLOR3_FRAG:
874 case R_0280F0_CB_COLOR4_FRAG:
875 case R_0280F4_CB_COLOR5_FRAG:
876 case R_0280F8_CB_COLOR6_FRAG:
877 case R_0280FC_CB_COLOR7_FRAG:
878 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
879 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
880 if (!track->cb_color_base_last[tmp]) {
881 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
882 return -EINVAL;
883 }
884 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 885 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
886 } else {
887 r = r600_cs_packet_next_reloc(p, &reloc);
888 if (r) {
889 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
890 return -EINVAL;
891 }
892 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
893 track->cb_color_frag_bo[tmp] = reloc->robj;
894 }
895 break;
896 case R_0280C0_CB_COLOR0_TILE:
897 case R_0280C4_CB_COLOR1_TILE:
898 case R_0280C8_CB_COLOR2_TILE:
899 case R_0280CC_CB_COLOR3_TILE:
900 case R_0280D0_CB_COLOR4_TILE:
901 case R_0280D4_CB_COLOR5_TILE:
902 case R_0280D8_CB_COLOR6_TILE:
903 case R_0280DC_CB_COLOR7_TILE:
904 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
905 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
906 if (!track->cb_color_base_last[tmp]) {
907 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
908 return -EINVAL;
909 }
910 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 911 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
912 } else {
913 r = r600_cs_packet_next_reloc(p, &reloc);
914 if (r) {
915 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
916 return -EINVAL;
917 }
918 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
919 track->cb_color_tile_bo[tmp] = reloc->robj;
920 }
921 break;
922 case CB_COLOR0_BASE:
923 case CB_COLOR1_BASE:
924 case CB_COLOR2_BASE:
925 case CB_COLOR3_BASE:
926 case CB_COLOR4_BASE:
927 case CB_COLOR5_BASE:
928 case CB_COLOR6_BASE:
929 case CB_COLOR7_BASE:
930 r = r600_cs_packet_next_reloc(p, &reloc);
931 if (r) {
932 dev_warn(p->dev, "bad SET_CONTEXT_REG "
933 "0x%04X\n", reg);
934 return -EINVAL;
935 }
7cb72ef4 936 tmp = (reg - CB_COLOR0_BASE) / 4;
1729dd33 937 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
961fb597 938 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 939 track->cb_color_base_last[tmp] = ib[idx];
940 track->cb_color_bo[tmp] = reloc->robj;
941 break;
942 case DB_DEPTH_BASE:
943 r = r600_cs_packet_next_reloc(p, &reloc);
944 if (r) {
945 dev_warn(p->dev, "bad SET_CONTEXT_REG "
946 "0x%04X\n", reg);
947 return -EINVAL;
948 }
1729dd33 949 track->db_offset = radeon_get_ib_value(p, idx) << 8;
961fb597
JG		 950 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
951 track->db_bo = reloc->robj;
952 break;
953 case DB_HTILE_DATA_BASE:
954 case SQ_PGM_START_FS:
955 case SQ_PGM_START_ES:
956 case SQ_PGM_START_VS:
957 case SQ_PGM_START_GS:
958 case SQ_PGM_START_PS:
5f77df36
AD		 959 case SQ_ALU_CONST_CACHE_GS_0:
960 case SQ_ALU_CONST_CACHE_GS_1:
961 case SQ_ALU_CONST_CACHE_GS_2:
962 case SQ_ALU_CONST_CACHE_GS_3:
963 case SQ_ALU_CONST_CACHE_GS_4:
964 case SQ_ALU_CONST_CACHE_GS_5:
965 case SQ_ALU_CONST_CACHE_GS_6:
966 case SQ_ALU_CONST_CACHE_GS_7:
967 case SQ_ALU_CONST_CACHE_GS_8:
968 case SQ_ALU_CONST_CACHE_GS_9:
969 case SQ_ALU_CONST_CACHE_GS_10:
970 case SQ_ALU_CONST_CACHE_GS_11:
971 case SQ_ALU_CONST_CACHE_GS_12:
972 case SQ_ALU_CONST_CACHE_GS_13:
973 case SQ_ALU_CONST_CACHE_GS_14:
974 case SQ_ALU_CONST_CACHE_GS_15:
975 case SQ_ALU_CONST_CACHE_PS_0:
976 case SQ_ALU_CONST_CACHE_PS_1:
977 case SQ_ALU_CONST_CACHE_PS_2:
978 case SQ_ALU_CONST_CACHE_PS_3:
979 case SQ_ALU_CONST_CACHE_PS_4:
980 case SQ_ALU_CONST_CACHE_PS_5:
981 case SQ_ALU_CONST_CACHE_PS_6:
982 case SQ_ALU_CONST_CACHE_PS_7:
983 case SQ_ALU_CONST_CACHE_PS_8:
984 case SQ_ALU_CONST_CACHE_PS_9:
985 case SQ_ALU_CONST_CACHE_PS_10:
986 case SQ_ALU_CONST_CACHE_PS_11:
987 case SQ_ALU_CONST_CACHE_PS_12:
988 case SQ_ALU_CONST_CACHE_PS_13:
989 case SQ_ALU_CONST_CACHE_PS_14:
990 case SQ_ALU_CONST_CACHE_PS_15:
991 case SQ_ALU_CONST_CACHE_VS_0:
992 case SQ_ALU_CONST_CACHE_VS_1:
993 case SQ_ALU_CONST_CACHE_VS_2:
994 case SQ_ALU_CONST_CACHE_VS_3:
995 case SQ_ALU_CONST_CACHE_VS_4:
996 case SQ_ALU_CONST_CACHE_VS_5:
997 case SQ_ALU_CONST_CACHE_VS_6:
998 case SQ_ALU_CONST_CACHE_VS_7:
999 case SQ_ALU_CONST_CACHE_VS_8:
1000 case SQ_ALU_CONST_CACHE_VS_9:
1001 case SQ_ALU_CONST_CACHE_VS_10:
1002 case SQ_ALU_CONST_CACHE_VS_11:
1003 case SQ_ALU_CONST_CACHE_VS_12:
1004 case SQ_ALU_CONST_CACHE_VS_13:
1005 case SQ_ALU_CONST_CACHE_VS_14:
1006 case SQ_ALU_CONST_CACHE_VS_15:
961fb597
JG		 1007 r = r600_cs_packet_next_reloc(p, &reloc);
1008 if (r) {
1009 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1010 "0x%04X\n", reg);
1011 return -EINVAL;
1012 }
1013 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1014 break;
1015 default:
1016 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1017 return -EINVAL;
1018 }
1019 return 0;
1020}
1021
1022static inline unsigned minify(unsigned size, unsigned levels)
1023{
1024 size = size >> levels;
1025 if (size < 1)
1026 size = 1;
1027 return size;
1028}
1029
1030static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
40e2a5c1
AD		 1031 unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
1032 unsigned pitch_align,
1033 unsigned *l0_size, unsigned *mipmap_size)
961fb597
JG		 1034{
1035 unsigned offset, i, level, face;
1036 unsigned width, height, depth, rowstride, size;
1037
1038 w0 = minify(w0, 0);
1039 h0 = minify(h0, 0);
1040 d0 = minify(d0, 0);
1041 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1042 width = minify(w0, i);
1043 height = minify(h0, i);
1044 depth = minify(d0, i);
1045 for(face = 0; face < nfaces; face++) {
40e2a5c1 1046 rowstride = ALIGN((width * bpe), pitch_align);
961fb597
JG		 1047 size = height * rowstride * depth;
1048 offset += size;
1049 offset = (offset + 0x1f) & ~0x1f;
1050 }
1051 }
40e2a5c1 1052 *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
961fb597 1053 *mipmap_size = offset;
961fb597
JG		 1054 if (!nlevels)
1055 *mipmap_size = *l0_size;
1729dd33
AD		 1056 if (!blevel)
1057 *mipmap_size -= *l0_size;
961fb597
JG		 1058}
1059
1060/**
1061 * r600_check_texture_resource() - check if register is authorized or not
1062 * @p: parser structure holding parsing context
1063 * @idx: index into the cs buffer
1064 * @texture: texture's bo structure
1065 * @mipmap: mipmap's bo structure
1066 *
1067 * This function will check that the resource has valid field and that
1068 * the texture and mipmap bo object are big enough to cover this resource.
1069 */
1070static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
7f813377
AD		 1071 struct radeon_bo *texture,
1072 struct radeon_bo *mipmap,
1073 u32 tiling_flags)
961fb597 1074{
40e2a5c1 1075 struct r600_cs_track *track = p->track;
71b10d87 1076 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
40e2a5c1 1077 u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align;
961fb597
JG		 1078
1079 /* on legacy kernel we don't perform advanced check */
1080 if (p->rdev == NULL)
1081 return 0;
7f813377 1082
961fb597 1083 word0 = radeon_get_ib_value(p, idx + 0);
7f813377
AD		 1084 if (tiling_flags & RADEON_TILING_MACRO)
1085 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1086 else if (tiling_flags & RADEON_TILING_MICRO)
1087 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
961fb597
JG		 1088 word1 = radeon_get_ib_value(p, idx + 1);
1089 w0 = G_038000_TEX_WIDTH(word0) + 1;
1090 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1091 d0 = G_038004_TEX_DEPTH(word1);
1092 nfaces = 1;
1093 switch (G_038000_DIM(word0)) {
1094 case V_038000_SQ_TEX_DIM_1D:
1095 case V_038000_SQ_TEX_DIM_2D:
1096 case V_038000_SQ_TEX_DIM_3D:
1097 break;
1098 case V_038000_SQ_TEX_DIM_CUBEMAP:
1099 nfaces = 6;
1100 break;
1101 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1102 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1103 case V_038000_SQ_TEX_DIM_2D_MSAA:
1104 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1105 default:
1106 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1107 return -EINVAL;
1108 }
1109 if (r600_bpe_from_format(&bpe, G_038004_DATA_FORMAT(word1))) {
1110 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1111 __func__, __LINE__, G_038004_DATA_FORMAT(word1));
1112 return -EINVAL;
1113 }
40e2a5c1
AD		 1114
1115 pitch = G_038000_PITCH(word0) + 1;
1116 switch (G_038000_TILE_MODE(word0)) {
1117 case V_038000_ARRAY_LINEAR_GENERAL:
1118 pitch_align = 1;
1119 /* XXX check height align */
1120 break;
1121 case V_038000_ARRAY_LINEAR_ALIGNED:
1122 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
1123 if (!IS_ALIGNED(pitch, pitch_align)) {
1124 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1125 __func__, __LINE__, pitch);
1126 return -EINVAL;
1127 }
1128 /* XXX check height align */
1129 break;
1130 case V_038000_ARRAY_1D_TILED_THIN1:
1131 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8;
1132 if (!IS_ALIGNED(pitch, pitch_align)) {
1133 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1134 __func__, __LINE__, pitch);
1135 return -EINVAL;
1136 }
1137 /* XXX check height align */
1138 break;
1139 case V_038000_ARRAY_2D_TILED_THIN1:
1140 pitch_align = max((u32)track->nbanks,
1141 (u32)(((track->group_size / 8) / bpe) * track->nbanks));
1142 if (!IS_ALIGNED(pitch, pitch_align)) {
1143 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1144 __func__, __LINE__, pitch);
1145 return -EINVAL;
1146 }
1147 /* XXX check height align */
1148 break;
1149 default:
1150 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
1151 G_038000_TILE_MODE(word0), word0);
1152 return -EINVAL;
1153 }
1154 /* XXX check offset align */
1155
961fb597
JG		 1156 word0 = radeon_get_ib_value(p, idx + 4);
1157 word1 = radeon_get_ib_value(p, idx + 5);
1158 blevel = G_038010_BASE_LEVEL(word0);
1159 nlevels = G_038014_LAST_LEVEL(word1);
40e2a5c1
AD		 1160 r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe,
1161 (pitch_align * bpe),
1162 &l0_size, &mipmap_size);
961fb597 1163 /* using get ib will give us the offset into the texture bo */
1729dd33 1164 word0 = radeon_get_ib_value(p, idx + 2) << 8;
961fb597
JG		 1165 if ((l0_size + word0) > radeon_bo_size(texture)) {
1166 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1167 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
1168 return -EINVAL;
1169 }
1170 /* using get ib will give us the offset into the mipmap bo */
1729dd33 1171 word0 = radeon_get_ib_value(p, idx + 3) << 8;
961fb597 1172 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
fe725d4f
AD		 1173 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1174 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/
961fb597
JG		 1175 }
1176 return 0;
1177}
1178
3ce0a23d
JG		 1179static int r600_packet3_check(struct radeon_cs_parser *p,
1180 struct radeon_cs_packet *pkt)
1181{
3ce0a23d 1182 struct radeon_cs_reloc *reloc;
c8c15ff1 1183 struct r600_cs_track *track;
3ce0a23d
JG		 1184 volatile u32 *ib;
1185 unsigned idx;
1186 unsigned i;
1187 unsigned start_reg, end_reg, reg;
1188 int r;
adea4796 1189 u32 idx_value;
3ce0a23d 1190
c8c15ff1 1191 track = (struct r600_cs_track *)p->track;
3ce0a23d 1192 ib = p->ib->ptr;
3ce0a23d 1193 idx = pkt->idx + 1;
adea4796 1194 idx_value = radeon_get_ib_value(p, idx);
513bcb46 1195
3ce0a23d
JG		 1196 switch (pkt->opcode) {
1197 case PACKET3_START_3D_CMDBUF:
1198 if (p->family >= CHIP_RV770 || pkt->count) {
1199 DRM_ERROR("bad START_3D\n");
1200 return -EINVAL;
1201 }
1202 break;
1203 case PACKET3_CONTEXT_CONTROL:
1204 if (pkt->count != 1) {
1205 DRM_ERROR("bad CONTEXT_CONTROL\n");
1206 return -EINVAL;
1207 }
1208 break;
1209 case PACKET3_INDEX_TYPE:
1210 case PACKET3_NUM_INSTANCES:
1211 if (pkt->count) {
1212 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1213 return -EINVAL;
1214 }
1215 break;
1216 case PACKET3_DRAW_INDEX:
1217 if (pkt->count != 3) {
1218 DRM_ERROR("bad DRAW_INDEX\n");
1219 return -EINVAL;
1220 }
1221 r = r600_cs_packet_next_reloc(p, &reloc);
1222 if (r) {
1223 DRM_ERROR("bad DRAW_INDEX\n");
1224 return -EINVAL;
1225 }
adea4796 1226 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1227 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
961fb597
JG		 1228 r = r600_cs_track_check(p);
1229 if (r) {
1230 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1231 return r;
1232 }
3ce0a23d
JG		 1233 break;
1234 case PACKET3_DRAW_INDEX_AUTO:
1235 if (pkt->count != 1) {
1236 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1237 return -EINVAL;
1238 }
961fb597
JG		 1239 r = r600_cs_track_check(p);
1240 if (r) {
1241 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1242 return r;
1243 }
3ce0a23d
JG		 1244 break;
1245 case PACKET3_DRAW_INDEX_IMMD_BE:
1246 case PACKET3_DRAW_INDEX_IMMD:
1247 if (pkt->count < 2) {
1248 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1249 return -EINVAL;
1250 }
961fb597
JG		 1251 r = r600_cs_track_check(p);
1252 if (r) {
1253 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1254 return r;
1255 }
3ce0a23d
JG		 1256 break;
1257 case PACKET3_WAIT_REG_MEM:
1258 if (pkt->count != 5) {
1259 DRM_ERROR("bad WAIT_REG_MEM\n");
1260 return -EINVAL;
1261 }
1262 /* bit 4 is reg (0) or mem (1) */
adea4796 1263 if (idx_value & 0x10) {
3ce0a23d
JG		 1264 r = r600_cs_packet_next_reloc(p, &reloc);
1265 if (r) {
1266 DRM_ERROR("bad WAIT_REG_MEM\n");
1267 return -EINVAL;
1268 }
1269 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1270 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1271 }
1272 break;
1273 case PACKET3_SURFACE_SYNC:
1274 if (pkt->count != 3) {
1275 DRM_ERROR("bad SURFACE_SYNC\n");
1276 return -EINVAL;
1277 }
1278 /* 0xffffffff/0x0 is flush all cache flag */
513bcb46
DA		 1279 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1280 radeon_get_ib_value(p, idx + 2) != 0) {
3ce0a23d
JG		 1281 r = r600_cs_packet_next_reloc(p, &reloc);
1282 if (r) {
1283 DRM_ERROR("bad SURFACE_SYNC\n");
1284 return -EINVAL;
1285 }
1286 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1287 }
1288 break;
1289 case PACKET3_EVENT_WRITE:
1290 if (pkt->count != 2 && pkt->count != 0) {
1291 DRM_ERROR("bad EVENT_WRITE\n");
1292 return -EINVAL;
1293 }
1294 if (pkt->count) {
1295 r = r600_cs_packet_next_reloc(p, &reloc);
1296 if (r) {
1297 DRM_ERROR("bad EVENT_WRITE\n");
1298 return -EINVAL;
1299 }
1300 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1301 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1302 }
1303 break;
1304 case PACKET3_EVENT_WRITE_EOP:
1305 if (pkt->count != 4) {
1306 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1307 return -EINVAL;
1308 }
1309 r = r600_cs_packet_next_reloc(p, &reloc);
1310 if (r) {
1311 DRM_ERROR("bad EVENT_WRITE\n");
1312 return -EINVAL;
1313 }
1314 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1315 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1316 break;
1317 case PACKET3_SET_CONFIG_REG:
adea4796 1318 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
3ce0a23d
JG		 1319 end_reg = 4 * pkt->count + start_reg - 4;
1320 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1321 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1322 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1323 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1324 return -EINVAL;
1325 }
1326 for (i = 0; i < pkt->count; i++) {
1327 reg = start_reg + (4 * i);
961fb597
JG		 1328 r = r600_cs_check_reg(p, reg, idx+1+i);
1329 if (r)
1330 return r;
3ce0a23d
JG		 1331 }
1332 break;
1333 case PACKET3_SET_CONTEXT_REG:
adea4796 1334 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
3ce0a23d
JG		 1335 end_reg = 4 * pkt->count + start_reg - 4;
1336 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1337 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1338 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1339 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1340 return -EINVAL;
1341 }
1342 for (i = 0; i < pkt->count; i++) {
1343 reg = start_reg + (4 * i);
961fb597
JG		 1344 r = r600_cs_check_reg(p, reg, idx+1+i);
1345 if (r)
1346 return r;
3ce0a23d
JG		 1347 }
1348 break;
1349 case PACKET3_SET_RESOURCE:
1350 if (pkt->count % 7) {
1351 DRM_ERROR("bad SET_RESOURCE\n");
1352 return -EINVAL;
1353 }
adea4796 1354 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
3ce0a23d
JG		 1355 end_reg = 4 * pkt->count + start_reg - 4;
1356 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1357 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1358 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1359 DRM_ERROR("bad SET_RESOURCE\n");
1360 return -EINVAL;
1361 }
1362 for (i = 0; i < (pkt->count / 7); i++) {
961fb597 1363 struct radeon_bo *texture, *mipmap;
1729dd33 1364 u32 size, offset, base_offset, mip_offset;
961fb597 1365
adea4796 1366 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
3ce0a23d
JG		 1367 case SQ_TEX_VTX_VALID_TEXTURE:
1368 /* tex base */
1369 r = r600_cs_packet_next_reloc(p, &reloc);
1370 if (r) {
1371 DRM_ERROR("bad SET_RESOURCE\n");
1372 return -EINVAL;
1373 }
1729dd33 1374 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
7f813377
AD		 1375 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1376 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1377 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1378 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
961fb597 1379 texture = reloc->robj;
3ce0a23d
JG		 1380 /* tex mip base */
1381 r = r600_cs_packet_next_reloc(p, &reloc);
1382 if (r) {
1383 DRM_ERROR("bad SET_RESOURCE\n");
1384 return -EINVAL;
1385 }
1729dd33 1386 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 1387 mipmap = reloc->robj;
1388 r = r600_check_texture_resource(p, idx+(i*7)+1,
7f813377 1389 texture, mipmap, reloc->lobj.tiling_flags);
961fb597
JG		 1390 if (r)
1391 return r;
1729dd33
AD		 1392 ib[idx+1+(i*7)+2] += base_offset;
1393 ib[idx+1+(i*7)+3] += mip_offset;
3ce0a23d
JG		 1394 break;
1395 case SQ_TEX_VTX_VALID_BUFFER:
1396 /* vtx base */
1397 r = r600_cs_packet_next_reloc(p, &reloc);
1398 if (r) {
1399 DRM_ERROR("bad SET_RESOURCE\n");
1400 return -EINVAL;
1401 }
961fb597 1402 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1729dd33 1403 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
961fb597
JG		 1404 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1405 /* force size to size of the buffer */
1729dd33
AD		 1406 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1407 size + offset, radeon_bo_size(reloc->robj));
961fb597
JG		 1408 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1409 }
3ce0a23d 1410 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
210bed8f 1411 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1412 break;
1413 case SQ_TEX_VTX_INVALID_TEXTURE:
1414 case SQ_TEX_VTX_INVALID_BUFFER:
1415 default:
1416 DRM_ERROR("bad SET_RESOURCE\n");
1417 return -EINVAL;
1418 }
1419 }
1420 break;
1421 case PACKET3_SET_ALU_CONST:
5f77df36
AD		 1422 if (track->sq_config & DX9_CONSTS) {
1423 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1424 end_reg = 4 * pkt->count + start_reg - 4;
1425 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1426 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1427 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1428 DRM_ERROR("bad SET_ALU_CONST\n");
1429 return -EINVAL;
1430 }
3ce0a23d
JG		 1431 }
1432 break;
1433 case PACKET3_SET_BOOL_CONST:
adea4796 1434 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
3ce0a23d
JG		 1435 end_reg = 4 * pkt->count + start_reg - 4;
1436 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1437 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1438 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1439 DRM_ERROR("bad SET_BOOL_CONST\n");
1440 return -EINVAL;
1441 }
1442 break;
1443 case PACKET3_SET_LOOP_CONST:
adea4796 1444 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
3ce0a23d
JG		 1445 end_reg = 4 * pkt->count + start_reg - 4;
1446 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1447 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1448 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1449 DRM_ERROR("bad SET_LOOP_CONST\n");
1450 return -EINVAL;
1451 }
1452 break;
1453 case PACKET3_SET_CTL_CONST:
adea4796 1454 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
3ce0a23d
JG		 1455 end_reg = 4 * pkt->count + start_reg - 4;
1456 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1457 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1458 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1459 DRM_ERROR("bad SET_CTL_CONST\n");
1460 return -EINVAL;
1461 }
1462 break;
1463 case PACKET3_SET_SAMPLER:
1464 if (pkt->count % 3) {
1465 DRM_ERROR("bad SET_SAMPLER\n");
1466 return -EINVAL;
1467 }
adea4796 1468 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
3ce0a23d
JG		 1469 end_reg = 4 * pkt->count + start_reg - 4;
1470 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1471 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1472 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1473 DRM_ERROR("bad SET_SAMPLER\n");
1474 return -EINVAL;
1475 }
1476 break;
1477 case PACKET3_SURFACE_BASE_UPDATE:
1478 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1479 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1480 return -EINVAL;
1481 }
1482 if (pkt->count) {
1483 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1484 return -EINVAL;
1485 }
1486 break;
1487 case PACKET3_NOP:
1488 break;
1489 default:
1490 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1491 return -EINVAL;
1492 }
1493 return 0;
1494}
1495
1496int r600_cs_parse(struct radeon_cs_parser *p)
1497{
1498 struct radeon_cs_packet pkt;
c8c15ff1 1499 struct r600_cs_track *track;
3ce0a23d
JG		 1500 int r;
1501
961fb597
JG		 1502 if (p->track == NULL) {
1503 /* initialize tracker, we are in kms */
1504 track = kzalloc(sizeof(*track), GFP_KERNEL);
1505 if (track == NULL)
1506 return -ENOMEM;
1507 r600_cs_track_init(track);
1508 if (p->rdev->family < CHIP_RV770) {
1509 track->npipes = p->rdev->config.r600.tiling_npipes;
1510 track->nbanks = p->rdev->config.r600.tiling_nbanks;
1511 track->group_size = p->rdev->config.r600.tiling_group_size;
1512 } else if (p->rdev->family <= CHIP_RV740) {
1513 track->npipes = p->rdev->config.rv770.tiling_npipes;
1514 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1515 track->group_size = p->rdev->config.rv770.tiling_group_size;
1516 }
1517 p->track = track;
1518 }
3ce0a23d
JG		 1519 do {
1520 r = r600_cs_packet_parse(p, &pkt, p->idx);
1521 if (r) {
7cb72ef4
JG		 1522 kfree(p->track);
1523 p->track = NULL;
3ce0a23d
JG		 1524 return r;
1525 }
1526 p->idx += pkt.count + 2;
1527 switch (pkt.type) {
1528 case PACKET_TYPE0:
1529 r = r600_cs_parse_packet0(p, &pkt);
1530 break;
1531 case PACKET_TYPE2:
1532 break;
1533 case PACKET_TYPE3:
1534 r = r600_packet3_check(p, &pkt);
1535 break;
1536 default:
1537 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
961fb597 1538 kfree(p->track);
7cb72ef4 1539 p->track = NULL;
3ce0a23d
JG		 1540 return -EINVAL;
1541 }
1542 if (r) {
961fb597 1543 kfree(p->track);
7cb72ef4 1544 p->track = NULL;
3ce0a23d
JG		 1545 return r;
1546 }
1547 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1548#if 0
1549 for (r = 0; r < p->ib->length_dw; r++) {
1550 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
1551 mdelay(1);
1552 }
1553#endif
961fb597 1554 kfree(p->track);
7cb72ef4 1555 p->track = NULL;
3ce0a23d
JG		 1556 return 0;
1557}
1558
1559static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1560{
1561 if (p->chunk_relocs_idx == -1) {
1562 return 0;
1563 }
e265f39e 1564 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
3ce0a23d
JG		 1565 if (p->relocs == NULL) {
1566 return -ENOMEM;
1567 }
1568 return 0;
1569}
1570
1571/**
1572 * cs_parser_fini() - clean parser states
1573 * @parser: parser structure holding parsing context.
1574 * @error: error number
1575 *
1576 * If error is set than unvalidate buffer, otherwise just free memory
1577 * used by parsing context.
1578 **/
1579static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1580{
1581 unsigned i;
1582
1583 kfree(parser->relocs);
1584 for (i = 0; i < parser->nchunks; i++) {
1585 kfree(parser->chunks[i].kdata);
4c57edba
DA		 1586 kfree(parser->chunks[i].kpage[0]);
1587 kfree(parser->chunks[i].kpage[1]);
3ce0a23d
JG		 1588 }
1589 kfree(parser->chunks);
1590 kfree(parser->chunks_array);
1591}
1592
1593int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1594 unsigned family, u32 *ib, int *l)
1595{
1596 struct radeon_cs_parser parser;
1597 struct radeon_cs_chunk *ib_chunk;
961fb597
JG		 1598 struct radeon_ib fake_ib;
1599 struct r600_cs_track *track;
3ce0a23d
JG		 1600 int r;
1601
961fb597
JG		 1602 /* initialize tracker */
1603 track = kzalloc(sizeof(*track), GFP_KERNEL);
1604 if (track == NULL)
1605 return -ENOMEM;
1606 r600_cs_track_init(track);
1607 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
3ce0a23d
JG		 1608 /* initialize parser */
1609 memset(&parser, 0, sizeof(struct radeon_cs_parser));
1610 parser.filp = filp;
c8c15ff1 1611 parser.dev = &dev->pdev->dev;
3ce0a23d
JG		 1612 parser.rdev = NULL;
1613 parser.family = family;
1614 parser.ib = &fake_ib;
961fb597 1615 parser.track = track;
3ce0a23d
JG		 1616 fake_ib.ptr = ib;
1617 r = radeon_cs_parser_init(&parser, data);
1618 if (r) {
1619 DRM_ERROR("Failed to initialize parser !\n");
1620 r600_cs_parser_fini(&parser, r);
1621 return r;
1622 }
1623 r = r600_cs_parser_relocs_legacy(&parser);
1624 if (r) {
1625 DRM_ERROR("Failed to parse relocation !\n");
1626 r600_cs_parser_fini(&parser, r);
1627 return r;
1628 }
1629 /* Copy the packet into the IB, the parser will read from the
1630 * input memory (cached) and write to the IB (which can be
1631 * uncached). */
1632 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1633 parser.ib->length_dw = ib_chunk->length_dw;
3ce0a23d
JG		 1634 *l = parser.ib->length_dw;
1635 r = r600_cs_parse(&parser);
1636 if (r) {
1637 DRM_ERROR("Invalid command stream !\n");
1638 r600_cs_parser_fini(&parser, r);
1639 return r;
1640 }
513bcb46
DA		 1641 r = radeon_cs_finish_pages(&parser);
1642 if (r) {
1643 DRM_ERROR("Invalid command stream !\n");
1644 r600_cs_parser_fini(&parser, r);
1645 return r;
1646 }
3ce0a23d
JG		 1647 r600_cs_parser_fini(&parser, r);
1648 return r;
1649}
1650
1651void r600_cs_legacy_init(void)
1652{
1653 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1654}
Clone of davem's net-next-2.6 tree