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drm/radeon/kms: add hpd support for r5xx/rs600/rs690/rs740 asics
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/seq_file.h>
29#include <linux/firmware.h>
30#include <linux/platform_device.h>
771fe6b9 31#include "drmP.h"
3ce0a23d 32#include "radeon_drm.h"
771fe6b9 33#include "radeon.h"
3ce0a23d 34#include "radeon_mode.h"
3ce0a23d 35#include "r600d.h"
3ce0a23d 36#include "atom.h"
d39c3b89 37#include "avivod.h"
771fe6b9 38
3ce0a23d
JG		 39#define PFP_UCODE_SIZE 576
40#define PM4_UCODE_SIZE 1792
d8f60cfc 41#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 42#define R700_PFP_UCODE_SIZE 848
43#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 44#define R700_RLC_UCODE_SIZE 1024
3ce0a23d
JG		 45
46/* Firmware Names */
47MODULE_FIRMWARE("radeon/R600_pfp.bin");
48MODULE_FIRMWARE("radeon/R600_me.bin");
49MODULE_FIRMWARE("radeon/RV610_pfp.bin");
50MODULE_FIRMWARE("radeon/RV610_me.bin");
51MODULE_FIRMWARE("radeon/RV630_pfp.bin");
52MODULE_FIRMWARE("radeon/RV630_me.bin");
53MODULE_FIRMWARE("radeon/RV620_pfp.bin");
54MODULE_FIRMWARE("radeon/RV620_me.bin");
55MODULE_FIRMWARE("radeon/RV635_pfp.bin");
56MODULE_FIRMWARE("radeon/RV635_me.bin");
57MODULE_FIRMWARE("radeon/RV670_pfp.bin");
58MODULE_FIRMWARE("radeon/RV670_me.bin");
59MODULE_FIRMWARE("radeon/RS780_pfp.bin");
60MODULE_FIRMWARE("radeon/RS780_me.bin");
61MODULE_FIRMWARE("radeon/RV770_pfp.bin");
62MODULE_FIRMWARE("radeon/RV770_me.bin");
63MODULE_FIRMWARE("radeon/RV730_pfp.bin");
64MODULE_FIRMWARE("radeon/RV730_me.bin");
65MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 67MODULE_FIRMWARE("radeon/R600_rlc.bin");
68MODULE_FIRMWARE("radeon/R700_rlc.bin");
3ce0a23d
JG		 69
70int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 71
1a029b76 72/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 73int r600_mc_wait_for_idle(struct radeon_device *rdev);
74void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 75void r600_fini(struct radeon_device *rdev);
771fe6b9 76
771fe6b9 77/*
3ce0a23d 78 * R600 PCIE GART
771fe6b9 79 */
3ce0a23d 80int r600_gart_clear_page(struct radeon_device *rdev, int i)
771fe6b9 81{
3ce0a23d
JG		 82 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
83 u64 pte;
771fe6b9 84
3ce0a23d
JG		 85 if (i < 0 || i > rdev->gart.num_gpu_pages)
86 return -EINVAL;
87 pte = 0;
88 writeq(pte, ((void __iomem *)ptr) + (i * 8));
89 return 0;
90}
771fe6b9 91
3ce0a23d
JG		 92void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
93{
94 unsigned i;
95 u32 tmp;
96
97 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
98 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
99 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
100 for (i = 0; i < rdev->usec_timeout; i++) {
101 /* read MC_STATUS */
102 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
103 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
104 if (tmp == 2) {
105 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
106 return;
107 }
108 if (tmp) {
109 return;
110 }
111 udelay(1);
112 }
113}
114
4aac0473 115int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 116{
4aac0473 117 int r;
3ce0a23d 118
4aac0473
JG		 119 if (rdev->gart.table.vram.robj) {
120 WARN(1, "R600 PCIE GART already initialized.\n");
121 return 0;
122 }
3ce0a23d
JG		 123 /* Initialize common gart structure */
124 r = radeon_gart_init(rdev);
4aac0473 125 if (r)
3ce0a23d 126 return r;
3ce0a23d 127 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 128 return radeon_gart_table_vram_alloc(rdev);
129}
130
131int r600_pcie_gart_enable(struct radeon_device *rdev)
132{
133 u32 tmp;
134 int r, i;
135
136 if (rdev->gart.table.vram.robj == NULL) {
137 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
138 return -EINVAL;
771fe6b9 139 }
4aac0473
JG		 140 r = radeon_gart_table_vram_pin(rdev);
141 if (r)
142 return r;
bc1a631e 143
3ce0a23d
JG		 144 /* Setup L2 cache */
145 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
146 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
147 EFFECTIVE_L2_QUEUE_SIZE(7));
148 WREG32(VM_L2_CNTL2, 0);
149 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
150 /* Setup TLB control */
151 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
152 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
153 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
154 ENABLE_WAIT_L2_QUERY;
155 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
156 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
157 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
158 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
159 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
160 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
161 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
162 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
163 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
164 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
165 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
166 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
167 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
168 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
169 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 170 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 171 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
172 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
173 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
174 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
175 (u32)(rdev->dummy_page.addr >> 12));
176 for (i = 1; i < 7; i++)
177 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 178
3ce0a23d
JG		 179 r600_pcie_gart_tlb_flush(rdev);
180 rdev->gart.ready = true;
771fe6b9
JG		 181 return 0;
182}
183
3ce0a23d 184void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 185{
3ce0a23d 186 u32 tmp;
4c788679 187 int i, r;
771fe6b9 188
3ce0a23d
JG		 189 /* Disable all tables */
190 for (i = 0; i < 7; i++)
191 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 192
3ce0a23d
JG		 193 /* Disable L2 cache */
194 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
195 EFFECTIVE_L2_QUEUE_SIZE(7));
196 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
197 /* Setup L1 TLB control */
198 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
199 ENABLE_WAIT_L2_QUERY;
200 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
201 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
202 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
203 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
204 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
205 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
206 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
207 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
208 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
209 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
210 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
211 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
212 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
213 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 214 if (rdev->gart.table.vram.robj) {
4c788679
JG		 215 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
216 if (likely(r == 0)) {
217 radeon_bo_kunmap(rdev->gart.table.vram.robj);
218 radeon_bo_unpin(rdev->gart.table.vram.robj);
219 radeon_bo_unreserve(rdev->gart.table.vram.robj);
220 }
4aac0473
JG		 221 }
222}
223
224void r600_pcie_gart_fini(struct radeon_device *rdev)
225{
226 r600_pcie_gart_disable(rdev);
227 radeon_gart_table_vram_free(rdev);
228 radeon_gart_fini(rdev);
771fe6b9
JG		 229}
230
1a029b76
JG		 231void r600_agp_enable(struct radeon_device *rdev)
232{
233 u32 tmp;
234 int i;
235
236 /* Setup L2 cache */
237 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
238 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
239 EFFECTIVE_L2_QUEUE_SIZE(7));
240 WREG32(VM_L2_CNTL2, 0);
241 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
242 /* Setup TLB control */
243 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
244 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
245 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
246 ENABLE_WAIT_L2_QUERY;
247 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
248 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
249 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
250 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
251 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
252 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
253 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
254 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
255 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
256 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
257 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
258 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
259 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
260 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
261 for (i = 0; i < 7; i++)
262 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
263}
264
771fe6b9
JG		 265int r600_mc_wait_for_idle(struct radeon_device *rdev)
266{
3ce0a23d
JG		 267 unsigned i;
268 u32 tmp;
269
270 for (i = 0; i < rdev->usec_timeout; i++) {
271 /* read MC_STATUS */
272 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
273 if (!tmp)
274 return 0;
275 udelay(1);
276 }
277 return -1;
771fe6b9
JG		 278}
279
a3c1945a 280static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 281{
a3c1945a 282 struct rv515_mc_save save;
3ce0a23d
JG		 283 u32 tmp;
284 int i, j;
771fe6b9 285
3ce0a23d
JG		 286 /* Initialize HDP */
287 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
288 WREG32((0x2c14 + j), 0x00000000);
289 WREG32((0x2c18 + j), 0x00000000);
290 WREG32((0x2c1c + j), 0x00000000);
291 WREG32((0x2c20 + j), 0x00000000);
292 WREG32((0x2c24 + j), 0x00000000);
293 }
294 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 295
a3c1945a 296 rv515_mc_stop(rdev, &save);
3ce0a23d 297 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 298 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 299 }
a3c1945a 300 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 301 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 302 /* Update configuration */
1a029b76
JG		 303 if (rdev->flags & RADEON_IS_AGP) {
304 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
305 /* VRAM before AGP */
306 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
307 rdev->mc.vram_start >> 12);
308 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
309 rdev->mc.gtt_end >> 12);
310 } else {
311 /* VRAM after AGP */
312 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
313 rdev->mc.gtt_start >> 12);
314 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
315 rdev->mc.vram_end >> 12);
316 }
317 } else {
318 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
319 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
320 }
3ce0a23d 321 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 322 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 323 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
324 WREG32(MC_VM_FB_LOCATION, tmp);
325 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
326 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1a029b76 327 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
3ce0a23d 328 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 329 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
330 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 331 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
332 } else {
333 WREG32(MC_VM_AGP_BASE, 0);
334 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
335 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
336 }
3ce0a23d 337 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 338 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 339 }
a3c1945a 340 rv515_mc_resume(rdev, &save);
698443d9
DA		 341 /* we need to own VRAM, so turn off the VGA renderer here
342 * to stop it overwriting our objects */
d39c3b89 343 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 344}
345
346int r600_mc_init(struct radeon_device *rdev)
771fe6b9 347{
3ce0a23d
JG		 348 fixed20_12 a;
349 u32 tmp;
5885b7a9 350 int chansize, numchan;
3ce0a23d 351 int r;
771fe6b9 352
3ce0a23d 353 /* Get VRAM informations */
771fe6b9 354 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 355 tmp = RREG32(RAMCFG);
356 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 357 chansize = 16;
3ce0a23d 358 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 359 chansize = 64;
360 } else {
361 chansize = 32;
362 }
5885b7a9
AD		 363 tmp = RREG32(CHMAP);
364 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
365 case 0:
366 default:
367 numchan = 1;
368 break;
369 case 1:
370 numchan = 2;
371 break;
372 case 2:
373 numchan = 4;
374 break;
375 case 3:
376 numchan = 8;
377 break;
771fe6b9 378 }
5885b7a9 379 rdev->mc.vram_width = numchan * chansize;
3ce0a23d
JG		 380 /* Could aper size report 0 ? */
381 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
382 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
383 /* Setup GPU memory space */
384 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
385 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
974b16e3
AD		 386
387 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
388 rdev->mc.mc_vram_size = rdev->mc.aper_size;
389
390 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
391 rdev->mc.real_vram_size = rdev->mc.aper_size;
392
3ce0a23d
JG		 393 if (rdev->flags & RADEON_IS_AGP) {
394 r = radeon_agp_init(rdev);
395 if (r)
396 return r;
397 /* gtt_size is setup by radeon_agp_init */
398 rdev->mc.gtt_location = rdev->mc.agp_base;
399 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
400 /* Try to put vram before or after AGP because we
401 * we want SYSTEM_APERTURE to cover both VRAM and
402 * AGP so that GPU can catch out of VRAM/AGP access
403 */
404 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
405 /* Enought place before */
406 rdev->mc.vram_location = rdev->mc.gtt_location -
407 rdev->mc.mc_vram_size;
408 } else if (tmp > rdev->mc.mc_vram_size) {
409 /* Enought place after */
410 rdev->mc.vram_location = rdev->mc.gtt_location +
411 rdev->mc.gtt_size;
412 } else {
413 /* Try to setup VRAM then AGP might not
414 * not work on some card
415 */
416 rdev->mc.vram_location = 0x00000000UL;
417 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
418 }
419 } else {
4d357abb
DA		 420 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
421 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
422 0xFFFF) << 24;
423 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
424 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
425 /* Enough place after vram */
426 rdev->mc.gtt_location = tmp;
427 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
428 /* Enough place before vram */
429 rdev->mc.gtt_location = 0;
430 } else {
431 /* Not enough place after or before shrink
432 * gart size
433 */
434 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
3ce0a23d 435 rdev->mc.gtt_location = 0;
4d357abb 436 rdev->mc.gtt_size = rdev->mc.vram_location;
3ce0a23d 437 } else {
4d357abb
DA		 438 rdev->mc.gtt_location = tmp;
439 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
3ce0a23d 440 }
3ce0a23d 441 }
4d357abb 442 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
3ce0a23d
JG		 443 }
444 rdev->mc.vram_start = rdev->mc.vram_location;
1a029b76 445 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
3ce0a23d 446 rdev->mc.gtt_start = rdev->mc.gtt_location;
1a029b76 447 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
3ce0a23d
JG		 448 /* FIXME: we should enforce default clock in case GPU is not in
449 * default setup
450 */
451 a.full = rfixed_const(100);
452 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
453 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
454 return 0;
771fe6b9
JG		 455}
456
3ce0a23d
JG		 457/* We doesn't check that the GPU really needs a reset we simply do the
458 * reset, it's up to the caller to determine if the GPU needs one. We
459 * might add an helper function to check that.
460 */
461int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 462{
a3c1945a 463 struct rv515_mc_save save;
3ce0a23d
JG		 464 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
465 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
466 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
467 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
468 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
469 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
470 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
471 S_008010_GUI_ACTIVE(1);
472 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
473 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
474 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
475 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
476 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
477 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
478 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
479 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
480 u32 srbm_reset = 0;
a3c1945a 481 u32 tmp;
771fe6b9 482
1a029b76
JG		 483 dev_info(rdev->dev, "GPU softreset \n");
484 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
485 RREG32(R_008010_GRBM_STATUS));
486 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 487 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 488 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
489 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 490 rv515_mc_stop(rdev, &save);
491 if (r600_mc_wait_for_idle(rdev)) {
492 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
493 }
3ce0a23d
JG		 494 /* Disable CP parsing/prefetching */
495 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
496 /* Check if any of the rendering block is busy and reset it */
497 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
498 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 499 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 500 S_008020_SOFT_RESET_DB(1) |
501 S_008020_SOFT_RESET_CB(1) |
502 S_008020_SOFT_RESET_PA(1) |
503 S_008020_SOFT_RESET_SC(1) |
504 S_008020_SOFT_RESET_SMX(1) |
505 S_008020_SOFT_RESET_SPI(1) |
506 S_008020_SOFT_RESET_SX(1) |
507 S_008020_SOFT_RESET_SH(1) |
508 S_008020_SOFT_RESET_TC(1) |
509 S_008020_SOFT_RESET_TA(1) |
510 S_008020_SOFT_RESET_VC(1) |
a3c1945a 511 S_008020_SOFT_RESET_VGT(1);
1a029b76 512 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 513 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
3ce0a23d
JG		 514 (void)RREG32(R_008020_GRBM_SOFT_RESET);
515 udelay(50);
516 WREG32(R_008020_GRBM_SOFT_RESET, 0);
517 (void)RREG32(R_008020_GRBM_SOFT_RESET);
518 }
519 /* Reset CP (we always reset CP) */
a3c1945a
JG		 520 tmp = S_008020_SOFT_RESET_CP(1);
521 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
522 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
3ce0a23d
JG		 523 (void)RREG32(R_008020_GRBM_SOFT_RESET);
524 udelay(50);
525 WREG32(R_008020_GRBM_SOFT_RESET, 0);
526 (void)RREG32(R_008020_GRBM_SOFT_RESET);
527 /* Reset others GPU block if necessary */
528 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
529 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
530 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
531 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
532 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
533 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
534 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
535 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
536 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
537 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
538 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
539 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
540 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
541 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
542 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
543 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
544 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
545 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
546 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
547 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
548 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
549 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
1a029b76
JG		 550 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
551 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
552 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
553 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
554 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
555 udelay(50);
556 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
557 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
3ce0a23d
JG		 558 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
559 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
560 udelay(50);
561 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
562 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
563 /* Wait a little for things to settle down */
564 udelay(50);
1a029b76
JG		 565 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
566 RREG32(R_008010_GRBM_STATUS));
567 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
568 RREG32(R_008014_GRBM_STATUS2));
569 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
570 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 571 /* After reset we need to reinit the asic as GPU often endup in an
572 * incoherent state.
573 */
574 atom_asic_init(rdev->mode_info.atom_context);
575 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 576 return 0;
577}
578
579int r600_gpu_reset(struct radeon_device *rdev)
580{
581 return r600_gpu_soft_reset(rdev);
582}
583
584static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
585 u32 num_backends,
586 u32 backend_disable_mask)
587{
588 u32 backend_map = 0;
589 u32 enabled_backends_mask;
590 u32 enabled_backends_count;
591 u32 cur_pipe;
592 u32 swizzle_pipe[R6XX_MAX_PIPES];
593 u32 cur_backend;
594 u32 i;
595
596 if (num_tile_pipes > R6XX_MAX_PIPES)
597 num_tile_pipes = R6XX_MAX_PIPES;
598 if (num_tile_pipes < 1)
599 num_tile_pipes = 1;
600 if (num_backends > R6XX_MAX_BACKENDS)
601 num_backends = R6XX_MAX_BACKENDS;
602 if (num_backends < 1)
603 num_backends = 1;
604
605 enabled_backends_mask = 0;
606 enabled_backends_count = 0;
607 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
608 if (((backend_disable_mask >> i) & 1) == 0) {
609 enabled_backends_mask |= (1 << i);
610 ++enabled_backends_count;
611 }
612 if (enabled_backends_count == num_backends)
613 break;
614 }
615
616 if (enabled_backends_count == 0) {
617 enabled_backends_mask = 1;
618 enabled_backends_count = 1;
619 }
620
621 if (enabled_backends_count != num_backends)
622 num_backends = enabled_backends_count;
623
624 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
625 switch (num_tile_pipes) {
626 case 1:
627 swizzle_pipe[0] = 0;
628 break;
629 case 2:
630 swizzle_pipe[0] = 0;
631 swizzle_pipe[1] = 1;
632 break;
633 case 3:
634 swizzle_pipe[0] = 0;
635 swizzle_pipe[1] = 1;
636 swizzle_pipe[2] = 2;
637 break;
638 case 4:
639 swizzle_pipe[0] = 0;
640 swizzle_pipe[1] = 1;
641 swizzle_pipe[2] = 2;
642 swizzle_pipe[3] = 3;
643 break;
644 case 5:
645 swizzle_pipe[0] = 0;
646 swizzle_pipe[1] = 1;
647 swizzle_pipe[2] = 2;
648 swizzle_pipe[3] = 3;
649 swizzle_pipe[4] = 4;
650 break;
651 case 6:
652 swizzle_pipe[0] = 0;
653 swizzle_pipe[1] = 2;
654 swizzle_pipe[2] = 4;
655 swizzle_pipe[3] = 5;
656 swizzle_pipe[4] = 1;
657 swizzle_pipe[5] = 3;
658 break;
659 case 7:
660 swizzle_pipe[0] = 0;
661 swizzle_pipe[1] = 2;
662 swizzle_pipe[2] = 4;
663 swizzle_pipe[3] = 6;
664 swizzle_pipe[4] = 1;
665 swizzle_pipe[5] = 3;
666 swizzle_pipe[6] = 5;
667 break;
668 case 8:
669 swizzle_pipe[0] = 0;
670 swizzle_pipe[1] = 2;
671 swizzle_pipe[2] = 4;
672 swizzle_pipe[3] = 6;
673 swizzle_pipe[4] = 1;
674 swizzle_pipe[5] = 3;
675 swizzle_pipe[6] = 5;
676 swizzle_pipe[7] = 7;
677 break;
678 }
679
680 cur_backend = 0;
681 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
682 while (((1 << cur_backend) & enabled_backends_mask) == 0)
683 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
684
685 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
686
687 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
688 }
689
690 return backend_map;
691}
692
693int r600_count_pipe_bits(uint32_t val)
694{
695 int i, ret = 0;
696
697 for (i = 0; i < 32; i++) {
698 ret += val & 1;
699 val >>= 1;
700 }
701 return ret;
771fe6b9
JG		 702}
703
3ce0a23d
JG		 704void r600_gpu_init(struct radeon_device *rdev)
705{
706 u32 tiling_config;
707 u32 ramcfg;
708 u32 tmp;
709 int i, j;
710 u32 sq_config;
711 u32 sq_gpr_resource_mgmt_1 = 0;
712 u32 sq_gpr_resource_mgmt_2 = 0;
713 u32 sq_thread_resource_mgmt = 0;
714 u32 sq_stack_resource_mgmt_1 = 0;
715 u32 sq_stack_resource_mgmt_2 = 0;
716
717 /* FIXME: implement */
718 switch (rdev->family) {
719 case CHIP_R600:
720 rdev->config.r600.max_pipes = 4;
721 rdev->config.r600.max_tile_pipes = 8;
722 rdev->config.r600.max_simds = 4;
723 rdev->config.r600.max_backends = 4;
724 rdev->config.r600.max_gprs = 256;
725 rdev->config.r600.max_threads = 192;
726 rdev->config.r600.max_stack_entries = 256;
727 rdev->config.r600.max_hw_contexts = 8;
728 rdev->config.r600.max_gs_threads = 16;
729 rdev->config.r600.sx_max_export_size = 128;
730 rdev->config.r600.sx_max_export_pos_size = 16;
731 rdev->config.r600.sx_max_export_smx_size = 128;
732 rdev->config.r600.sq_num_cf_insts = 2;
733 break;
734 case CHIP_RV630:
735 case CHIP_RV635:
736 rdev->config.r600.max_pipes = 2;
737 rdev->config.r600.max_tile_pipes = 2;
738 rdev->config.r600.max_simds = 3;
739 rdev->config.r600.max_backends = 1;
740 rdev->config.r600.max_gprs = 128;
741 rdev->config.r600.max_threads = 192;
742 rdev->config.r600.max_stack_entries = 128;
743 rdev->config.r600.max_hw_contexts = 8;
744 rdev->config.r600.max_gs_threads = 4;
745 rdev->config.r600.sx_max_export_size = 128;
746 rdev->config.r600.sx_max_export_pos_size = 16;
747 rdev->config.r600.sx_max_export_smx_size = 128;
748 rdev->config.r600.sq_num_cf_insts = 2;
749 break;
750 case CHIP_RV610:
751 case CHIP_RV620:
752 case CHIP_RS780:
753 case CHIP_RS880:
754 rdev->config.r600.max_pipes = 1;
755 rdev->config.r600.max_tile_pipes = 1;
756 rdev->config.r600.max_simds = 2;
757 rdev->config.r600.max_backends = 1;
758 rdev->config.r600.max_gprs = 128;
759 rdev->config.r600.max_threads = 192;
760 rdev->config.r600.max_stack_entries = 128;
761 rdev->config.r600.max_hw_contexts = 4;
762 rdev->config.r600.max_gs_threads = 4;
763 rdev->config.r600.sx_max_export_size = 128;
764 rdev->config.r600.sx_max_export_pos_size = 16;
765 rdev->config.r600.sx_max_export_smx_size = 128;
766 rdev->config.r600.sq_num_cf_insts = 1;
767 break;
768 case CHIP_RV670:
769 rdev->config.r600.max_pipes = 4;
770 rdev->config.r600.max_tile_pipes = 4;
771 rdev->config.r600.max_simds = 4;
772 rdev->config.r600.max_backends = 4;
773 rdev->config.r600.max_gprs = 192;
774 rdev->config.r600.max_threads = 192;
775 rdev->config.r600.max_stack_entries = 256;
776 rdev->config.r600.max_hw_contexts = 8;
777 rdev->config.r600.max_gs_threads = 16;
778 rdev->config.r600.sx_max_export_size = 128;
779 rdev->config.r600.sx_max_export_pos_size = 16;
780 rdev->config.r600.sx_max_export_smx_size = 128;
781 rdev->config.r600.sq_num_cf_insts = 2;
782 break;
783 default:
784 break;
785 }
786
787 /* Initialize HDP */
788 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
789 WREG32((0x2c14 + j), 0x00000000);
790 WREG32((0x2c18 + j), 0x00000000);
791 WREG32((0x2c1c + j), 0x00000000);
792 WREG32((0x2c20 + j), 0x00000000);
793 WREG32((0x2c24 + j), 0x00000000);
794 }
795
796 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
797
798 /* Setup tiling */
799 tiling_config = 0;
800 ramcfg = RREG32(RAMCFG);
801 switch (rdev->config.r600.max_tile_pipes) {
802 case 1:
803 tiling_config |= PIPE_TILING(0);
804 break;
805 case 2:
806 tiling_config |= PIPE_TILING(1);
807 break;
808 case 4:
809 tiling_config |= PIPE_TILING(2);
810 break;
811 case 8:
812 tiling_config |= PIPE_TILING(3);
813 break;
814 default:
815 break;
816 }
817 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
818 tiling_config |= GROUP_SIZE(0);
819 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
820 if (tmp > 3) {
821 tiling_config |= ROW_TILING(3);
822 tiling_config |= SAMPLE_SPLIT(3);
823 } else {
824 tiling_config |= ROW_TILING(tmp);
825 tiling_config |= SAMPLE_SPLIT(tmp);
826 }
827 tiling_config |= BANK_SWAPS(1);
828 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
829 rdev->config.r600.max_backends,
830 (0xff << rdev->config.r600.max_backends) & 0xff);
831 tiling_config |= BACKEND_MAP(tmp);
832 WREG32(GB_TILING_CONFIG, tiling_config);
833 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
834 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
835
836 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
837 WREG32(CC_RB_BACKEND_DISABLE, tmp);
838
839 /* Setup pipes */
840 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
841 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
842 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
843 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
844
845 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
846 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
847 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
848
849 /* Setup some CP states */
850 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
851 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
852
853 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
854 SYNC_WALKER | SYNC_ALIGNER));
855 /* Setup various GPU states */
856 if (rdev->family == CHIP_RV670)
857 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
858
859 tmp = RREG32(SX_DEBUG_1);
860 tmp |= SMX_EVENT_RELEASE;
861 if ((rdev->family > CHIP_R600))
862 tmp |= ENABLE_NEW_SMX_ADDRESS;
863 WREG32(SX_DEBUG_1, tmp);
864
865 if (((rdev->family) == CHIP_R600) ||
866 ((rdev->family) == CHIP_RV630) ||
867 ((rdev->family) == CHIP_RV610) ||
868 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 869 ((rdev->family) == CHIP_RS780) ||
870 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 871 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
872 } else {
873 WREG32(DB_DEBUG, 0);
874 }
875 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
876 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
877
878 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
879 WREG32(VGT_NUM_INSTANCES, 0);
880
881 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
882 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
883
884 tmp = RREG32(SQ_MS_FIFO_SIZES);
885 if (((rdev->family) == CHIP_RV610) ||
886 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 887 ((rdev->family) == CHIP_RS780) ||
888 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 889 tmp = (CACHE_FIFO_SIZE(0xa) |
890 FETCH_FIFO_HIWATER(0xa) |
891 DONE_FIFO_HIWATER(0xe0) |
892 ALU_UPDATE_FIFO_HIWATER(0x8));
893 } else if (((rdev->family) == CHIP_R600) ||
894 ((rdev->family) == CHIP_RV630)) {
895 tmp &= ~DONE_FIFO_HIWATER(0xff);
896 tmp |= DONE_FIFO_HIWATER(0x4);
897 }
898 WREG32(SQ_MS_FIFO_SIZES, tmp);
899
900 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
901 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
902 */
903 sq_config = RREG32(SQ_CONFIG);
904 sq_config &= ~(PS_PRIO(3) |
905 VS_PRIO(3) |
906 GS_PRIO(3) |
907 ES_PRIO(3));
908 sq_config |= (DX9_CONSTS |
909 VC_ENABLE |
910 PS_PRIO(0) |
911 VS_PRIO(1) |
912 GS_PRIO(2) |
913 ES_PRIO(3));
914
915 if ((rdev->family) == CHIP_R600) {
916 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
917 NUM_VS_GPRS(124) |
918 NUM_CLAUSE_TEMP_GPRS(4));
919 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
920 NUM_ES_GPRS(0));
921 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
922 NUM_VS_THREADS(48) |
923 NUM_GS_THREADS(4) |
924 NUM_ES_THREADS(4));
925 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
926 NUM_VS_STACK_ENTRIES(128));
927 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
928 NUM_ES_STACK_ENTRIES(0));
929 } else if (((rdev->family) == CHIP_RV610) ||
930 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 931 ((rdev->family) == CHIP_RS780) ||
932 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 933 /* no vertex cache */
934 sq_config &= ~VC_ENABLE;
935
936 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
937 NUM_VS_GPRS(44) |
938 NUM_CLAUSE_TEMP_GPRS(2));
939 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
940 NUM_ES_GPRS(17));
941 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
942 NUM_VS_THREADS(78) |
943 NUM_GS_THREADS(4) |
944 NUM_ES_THREADS(31));
945 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
946 NUM_VS_STACK_ENTRIES(40));
947 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
948 NUM_ES_STACK_ENTRIES(16));
949 } else if (((rdev->family) == CHIP_RV630) ||
950 ((rdev->family) == CHIP_RV635)) {
951 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
952 NUM_VS_GPRS(44) |
953 NUM_CLAUSE_TEMP_GPRS(2));
954 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
955 NUM_ES_GPRS(18));
956 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
957 NUM_VS_THREADS(78) |
958 NUM_GS_THREADS(4) |
959 NUM_ES_THREADS(31));
960 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
961 NUM_VS_STACK_ENTRIES(40));
962 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
963 NUM_ES_STACK_ENTRIES(16));
964 } else if ((rdev->family) == CHIP_RV670) {
965 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
966 NUM_VS_GPRS(44) |
967 NUM_CLAUSE_TEMP_GPRS(2));
968 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
969 NUM_ES_GPRS(17));
970 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
971 NUM_VS_THREADS(78) |
972 NUM_GS_THREADS(4) |
973 NUM_ES_THREADS(31));
974 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
975 NUM_VS_STACK_ENTRIES(64));
976 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
977 NUM_ES_STACK_ENTRIES(64));
978 }
979
980 WREG32(SQ_CONFIG, sq_config);
981 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
982 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
983 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
984 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
985 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
986
987 if (((rdev->family) == CHIP_RV610) ||
988 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 989 ((rdev->family) == CHIP_RS780) ||
990 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 991 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
992 } else {
993 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
994 }
995
996 /* More default values. 2D/3D driver should adjust as needed */
997 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
998 S1_X(0x4) | S1_Y(0xc)));
999 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1000 S1_X(0x2) | S1_Y(0x2) |
1001 S2_X(0xa) | S2_Y(0x6) |
1002 S3_X(0x6) | S3_Y(0xa)));
1003 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1004 S1_X(0x4) | S1_Y(0xc) |
1005 S2_X(0x1) | S2_Y(0x6) |
1006 S3_X(0xa) | S3_Y(0xe)));
1007 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1008 S5_X(0x0) | S5_Y(0x0) |
1009 S6_X(0xb) | S6_Y(0x4) |
1010 S7_X(0x7) | S7_Y(0x8)));
1011
1012 WREG32(VGT_STRMOUT_EN, 0);
1013 tmp = rdev->config.r600.max_pipes * 16;
1014 switch (rdev->family) {
1015 case CHIP_RV610:
3ce0a23d 1016 case CHIP_RV620:
ee59f2b4
AD		 1017 case CHIP_RS780:
1018 case CHIP_RS880:
3ce0a23d
JG		 1019 tmp += 32;
1020 break;
1021 case CHIP_RV670:
1022 tmp += 128;
1023 break;
1024 default:
1025 break;
1026 }
1027 if (tmp > 256) {
1028 tmp = 256;
1029 }
1030 WREG32(VGT_ES_PER_GS, 128);
1031 WREG32(VGT_GS_PER_ES, tmp);
1032 WREG32(VGT_GS_PER_VS, 2);
1033 WREG32(VGT_GS_VERTEX_REUSE, 16);
1034
1035 /* more default values. 2D/3D driver should adjust as needed */
1036 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1037 WREG32(VGT_STRMOUT_EN, 0);
1038 WREG32(SX_MISC, 0);
1039 WREG32(PA_SC_MODE_CNTL, 0);
1040 WREG32(PA_SC_AA_CONFIG, 0);
1041 WREG32(PA_SC_LINE_STIPPLE, 0);
1042 WREG32(SPI_INPUT_Z, 0);
1043 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1044 WREG32(CB_COLOR7_FRAG, 0);
1045
1046 /* Clear render buffer base addresses */
1047 WREG32(CB_COLOR0_BASE, 0);
1048 WREG32(CB_COLOR1_BASE, 0);
1049 WREG32(CB_COLOR2_BASE, 0);
1050 WREG32(CB_COLOR3_BASE, 0);
1051 WREG32(CB_COLOR4_BASE, 0);
1052 WREG32(CB_COLOR5_BASE, 0);
1053 WREG32(CB_COLOR6_BASE, 0);
1054 WREG32(CB_COLOR7_BASE, 0);
1055 WREG32(CB_COLOR7_FRAG, 0);
1056
1057 switch (rdev->family) {
1058 case CHIP_RV610:
3ce0a23d 1059 case CHIP_RV620:
ee59f2b4
AD		 1060 case CHIP_RS780:
1061 case CHIP_RS880:
3ce0a23d
JG		 1062 tmp = TC_L2_SIZE(8);
1063 break;
1064 case CHIP_RV630:
1065 case CHIP_RV635:
1066 tmp = TC_L2_SIZE(4);
1067 break;
1068 case CHIP_R600:
1069 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1070 break;
1071 default:
1072 tmp = TC_L2_SIZE(0);
1073 break;
1074 }
1075 WREG32(TC_CNTL, tmp);
1076
1077 tmp = RREG32(HDP_HOST_PATH_CNTL);
1078 WREG32(HDP_HOST_PATH_CNTL, tmp);
1079
1080 tmp = RREG32(ARB_POP);
1081 tmp |= ENABLE_TC128;
1082 WREG32(ARB_POP, tmp);
1083
1084 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1085 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1086 NUM_CLIP_SEQ(3)));
1087 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1088}
1089
1090
771fe6b9
JG		 1091/*
1092 * Indirect registers accessor
1093 */
3ce0a23d
JG		 1094u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1095{
1096 u32 r;
1097
1098 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1099 (void)RREG32(PCIE_PORT_INDEX);
1100 r = RREG32(PCIE_PORT_DATA);
1101 return r;
1102}
1103
1104void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1105{
1106 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1107 (void)RREG32(PCIE_PORT_INDEX);
1108 WREG32(PCIE_PORT_DATA, (v));
1109 (void)RREG32(PCIE_PORT_DATA);
1110}
1111
23956dfa
DA		 1112void r600_hdp_flush(struct radeon_device *rdev)
1113{
1114 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1115}
3ce0a23d
JG		 1116
1117/*
1118 * CP & Ring
1119 */
1120void r600_cp_stop(struct radeon_device *rdev)
1121{
1122 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1123}
1124
d8f60cfc 1125int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1126{
1127 struct platform_device *pdev;
1128 const char *chip_name;
d8f60cfc
AD		 1129 const char *rlc_chip_name;
1130 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1131 char fw_name[30];
1132 int err;
1133
1134 DRM_DEBUG("\n");
1135
1136 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1137 err = IS_ERR(pdev);
1138 if (err) {
1139 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1140 return -EINVAL;
1141 }
1142
1143 switch (rdev->family) {
d8f60cfc
AD		 1144 case CHIP_R600:
1145 chip_name = "R600";
1146 rlc_chip_name = "R600";
1147 break;
1148 case CHIP_RV610:
1149 chip_name = "RV610";
1150 rlc_chip_name = "R600";
1151 break;
1152 case CHIP_RV630:
1153 chip_name = "RV630";
1154 rlc_chip_name = "R600";
1155 break;
1156 case CHIP_RV620:
1157 chip_name = "RV620";
1158 rlc_chip_name = "R600";
1159 break;
1160 case CHIP_RV635:
1161 chip_name = "RV635";
1162 rlc_chip_name = "R600";
1163 break;
1164 case CHIP_RV670:
1165 chip_name = "RV670";
1166 rlc_chip_name = "R600";
1167 break;
3ce0a23d 1168 case CHIP_RS780:
d8f60cfc
AD		 1169 case CHIP_RS880:
1170 chip_name = "RS780";
1171 rlc_chip_name = "R600";
1172 break;
1173 case CHIP_RV770:
1174 chip_name = "RV770";
1175 rlc_chip_name = "R700";
1176 break;
3ce0a23d 1177 case CHIP_RV730:
d8f60cfc
AD		 1178 case CHIP_RV740:
1179 chip_name = "RV730";
1180 rlc_chip_name = "R700";
1181 break;
1182 case CHIP_RV710:
1183 chip_name = "RV710";
1184 rlc_chip_name = "R700";
1185 break;
3ce0a23d
JG		 1186 default: BUG();
1187 }
1188
1189 if (rdev->family >= CHIP_RV770) {
1190 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1191 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 1192 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1193 } else {
1194 pfp_req_size = PFP_UCODE_SIZE * 4;
1195 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 1196 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1197 }
1198
d8f60cfc 1199 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 1200
1201 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1202 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1203 if (err)
1204 goto out;
1205 if (rdev->pfp_fw->size != pfp_req_size) {
1206 printk(KERN_ERR
1207 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1208 rdev->pfp_fw->size, fw_name);
1209 err = -EINVAL;
1210 goto out;
1211 }
1212
1213 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1214 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1215 if (err)
1216 goto out;
1217 if (rdev->me_fw->size != me_req_size) {
1218 printk(KERN_ERR
1219 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1220 rdev->me_fw->size, fw_name);
1221 err = -EINVAL;
1222 }
d8f60cfc
AD		 1223
1224 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1225 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1226 if (err)
1227 goto out;
1228 if (rdev->rlc_fw->size != rlc_req_size) {
1229 printk(KERN_ERR
1230 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1231 rdev->rlc_fw->size, fw_name);
1232 err = -EINVAL;
1233 }
1234
3ce0a23d
JG		 1235out:
1236 platform_device_unregister(pdev);
1237
1238 if (err) {
1239 if (err != -EINVAL)
1240 printk(KERN_ERR
1241 "r600_cp: Failed to load firmware \"%s\"\n",
1242 fw_name);
1243 release_firmware(rdev->pfp_fw);
1244 rdev->pfp_fw = NULL;
1245 release_firmware(rdev->me_fw);
1246 rdev->me_fw = NULL;
d8f60cfc
AD		 1247 release_firmware(rdev->rlc_fw);
1248 rdev->rlc_fw = NULL;
3ce0a23d
JG		 1249 }
1250 return err;
1251}
1252
1253static int r600_cp_load_microcode(struct radeon_device *rdev)
1254{
1255 const __be32 *fw_data;
1256 int i;
1257
1258 if (!rdev->me_fw || !rdev->pfp_fw)
1259 return -EINVAL;
1260
1261 r600_cp_stop(rdev);
1262
1263 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1264
1265 /* Reset cp */
1266 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1267 RREG32(GRBM_SOFT_RESET);
1268 mdelay(15);
1269 WREG32(GRBM_SOFT_RESET, 0);
1270
1271 WREG32(CP_ME_RAM_WADDR, 0);
1272
1273 fw_data = (const __be32 *)rdev->me_fw->data;
1274 WREG32(CP_ME_RAM_WADDR, 0);
1275 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1276 WREG32(CP_ME_RAM_DATA,
1277 be32_to_cpup(fw_data++));
1278
1279 fw_data = (const __be32 *)rdev->pfp_fw->data;
1280 WREG32(CP_PFP_UCODE_ADDR, 0);
1281 for (i = 0; i < PFP_UCODE_SIZE; i++)
1282 WREG32(CP_PFP_UCODE_DATA,
1283 be32_to_cpup(fw_data++));
1284
1285 WREG32(CP_PFP_UCODE_ADDR, 0);
1286 WREG32(CP_ME_RAM_WADDR, 0);
1287 WREG32(CP_ME_RAM_RADDR, 0);
1288 return 0;
1289}
1290
1291int r600_cp_start(struct radeon_device *rdev)
1292{
1293 int r;
1294 uint32_t cp_me;
1295
1296 r = radeon_ring_lock(rdev, 7);
1297 if (r) {
1298 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1299 return r;
1300 }
1301 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1302 radeon_ring_write(rdev, 0x1);
1303 if (rdev->family < CHIP_RV770) {
1304 radeon_ring_write(rdev, 0x3);
1305 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1306 } else {
1307 radeon_ring_write(rdev, 0x0);
1308 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1309 }
1310 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1311 radeon_ring_write(rdev, 0);
1312 radeon_ring_write(rdev, 0);
1313 radeon_ring_unlock_commit(rdev);
1314
1315 cp_me = 0xff;
1316 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1317 return 0;
1318}
1319
1320int r600_cp_resume(struct radeon_device *rdev)
1321{
1322 u32 tmp;
1323 u32 rb_bufsz;
1324 int r;
1325
1326 /* Reset cp */
1327 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1328 RREG32(GRBM_SOFT_RESET);
1329 mdelay(15);
1330 WREG32(GRBM_SOFT_RESET, 0);
1331
1332 /* Set ring buffer size */
1333 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
d6f28938 1334 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 1335#ifdef __BIG_ENDIAN
d6f28938 1336 tmp |= BUF_SWAP_32BIT;
3ce0a23d 1337#endif
d6f28938 1338 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 1339 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1340
1341 /* Set the write pointer delay */
1342 WREG32(CP_RB_WPTR_DELAY, 0);
1343
1344 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 1345 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1346 WREG32(CP_RB_RPTR_WR, 0);
1347 WREG32(CP_RB_WPTR, 0);
1348 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1349 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1350 mdelay(1);
1351 WREG32(CP_RB_CNTL, tmp);
1352
1353 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1354 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1355
1356 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1357 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1358
1359 r600_cp_start(rdev);
1360 rdev->cp.ready = true;
1361 r = radeon_ring_test(rdev);
1362 if (r) {
1363 rdev->cp.ready = false;
1364 return r;
1365 }
1366 return 0;
1367}
1368
1369void r600_cp_commit(struct radeon_device *rdev)
1370{
1371 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1372 (void)RREG32(CP_RB_WPTR);
1373}
1374
1375void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1376{
1377 u32 rb_bufsz;
1378
1379 /* Align ring size */
1380 rb_bufsz = drm_order(ring_size / 8);
1381 ring_size = (1 << (rb_bufsz + 1)) * 4;
1382 rdev->cp.ring_size = ring_size;
1383 rdev->cp.align_mask = 16 - 1;
1384}
1385
1386
1387/*
1388 * GPU scratch registers helpers function.
1389 */
1390void r600_scratch_init(struct radeon_device *rdev)
1391{
1392 int i;
1393
1394 rdev->scratch.num_reg = 7;
1395 for (i = 0; i < rdev->scratch.num_reg; i++) {
1396 rdev->scratch.free[i] = true;
1397 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1398 }
1399}
1400
1401int r600_ring_test(struct radeon_device *rdev)
1402{
1403 uint32_t scratch;
1404 uint32_t tmp = 0;
1405 unsigned i;
1406 int r;
1407
1408 r = radeon_scratch_get(rdev, &scratch);
1409 if (r) {
1410 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1411 return r;
1412 }
1413 WREG32(scratch, 0xCAFEDEAD);
1414 r = radeon_ring_lock(rdev, 3);
1415 if (r) {
1416 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1417 radeon_scratch_free(rdev, scratch);
1418 return r;
1419 }
1420 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1421 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1422 radeon_ring_write(rdev, 0xDEADBEEF);
1423 radeon_ring_unlock_commit(rdev);
1424 for (i = 0; i < rdev->usec_timeout; i++) {
1425 tmp = RREG32(scratch);
1426 if (tmp == 0xDEADBEEF)
1427 break;
1428 DRM_UDELAY(1);
1429 }
1430 if (i < rdev->usec_timeout) {
1431 DRM_INFO("ring test succeeded in %d usecs\n", i);
1432 } else {
1433 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1434 scratch, tmp);
1435 r = -EINVAL;
1436 }
1437 radeon_scratch_free(rdev, scratch);
1438 return r;
1439}
1440
81cc35bf
JG		 1441void r600_wb_disable(struct radeon_device *rdev)
1442{
4c788679
JG		 1443 int r;
1444
81cc35bf
JG		 1445 WREG32(SCRATCH_UMSK, 0);
1446 if (rdev->wb.wb_obj) {
4c788679
JG		 1447 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1448 if (unlikely(r != 0))
1449 return;
1450 radeon_bo_kunmap(rdev->wb.wb_obj);
1451 radeon_bo_unpin(rdev->wb.wb_obj);
1452 radeon_bo_unreserve(rdev->wb.wb_obj);
81cc35bf
JG		 1453 }
1454}
1455
1456void r600_wb_fini(struct radeon_device *rdev)
1457{
1458 r600_wb_disable(rdev);
1459 if (rdev->wb.wb_obj) {
4c788679 1460 radeon_bo_unref(&rdev->wb.wb_obj);
81cc35bf
JG		 1461 rdev->wb.wb = NULL;
1462 rdev->wb.wb_obj = NULL;
1463 }
1464}
1465
1466int r600_wb_enable(struct radeon_device *rdev)
3ce0a23d
JG		 1467{
1468 int r;
1469
1470 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 1471 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1472 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
3ce0a23d 1473 if (r) {
4c788679
JG		 1474 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1475 return r;
1476 }
1477 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1478 if (unlikely(r != 0)) {
1479 r600_wb_fini(rdev);
3ce0a23d
JG		 1480 return r;
1481 }
4c788679 1482 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
81cc35bf 1483 &rdev->wb.gpu_addr);
3ce0a23d 1484 if (r) {
4c788679
JG		 1485 radeon_bo_unreserve(rdev->wb.wb_obj);
1486 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
81cc35bf 1487 r600_wb_fini(rdev);
3ce0a23d
JG		 1488 return r;
1489 }
4c788679
JG		 1490 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1491 radeon_bo_unreserve(rdev->wb.wb_obj);
3ce0a23d 1492 if (r) {
4c788679 1493 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
81cc35bf 1494 r600_wb_fini(rdev);
3ce0a23d
JG		 1495 return r;
1496 }
1497 }
1498 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1499 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1500 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1501 WREG32(SCRATCH_UMSK, 0xff);
1502 return 0;
1503}
1504
3ce0a23d
JG		 1505void r600_fence_ring_emit(struct radeon_device *rdev,
1506 struct radeon_fence *fence)
1507{
d8f60cfc 1508 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
3ce0a23d
JG		 1509 /* Emit fence sequence & fire IRQ */
1510 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1511 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1512 radeon_ring_write(rdev, fence->seq);
d8f60cfc
AD		 1513 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1514 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1515 radeon_ring_write(rdev, RB_INT_STAT);
3ce0a23d
JG		 1516}
1517
1518int r600_copy_dma(struct radeon_device *rdev,
1519 uint64_t src_offset,
1520 uint64_t dst_offset,
1521 unsigned num_pages,
1522 struct radeon_fence *fence)
1523{
1524 /* FIXME: implement */
1525 return 0;
1526}
1527
1528int r600_copy_blit(struct radeon_device *rdev,
1529 uint64_t src_offset, uint64_t dst_offset,
1530 unsigned num_pages, struct radeon_fence *fence)
1531{
a77f1718
MT		 1532 r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1533 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d
JG		 1534 r600_blit_done_copy(rdev, fence);
1535 return 0;
1536}
1537
3ce0a23d
JG		 1538int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1539 uint32_t tiling_flags, uint32_t pitch,
1540 uint32_t offset, uint32_t obj_size)
1541{
1542 /* FIXME: implement */
1543 return 0;
1544}
1545
1546void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1547{
1548 /* FIXME: implement */
1549}
1550
1551
1552bool r600_card_posted(struct radeon_device *rdev)
1553{
1554 uint32_t reg;
1555
1556 /* first check CRTCs */
1557 reg = RREG32(D1CRTC_CONTROL) |
1558 RREG32(D2CRTC_CONTROL);
1559 if (reg & CRTC_EN)
1560 return true;
1561
1562 /* then check MEM_SIZE, in case the crtcs are off */
1563 if (RREG32(CONFIG_MEMSIZE))
1564 return true;
1565
1566 return false;
1567}
1568
fc30b8ef 1569int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 1570{
1571 int r;
1572
a3c1945a 1573 r600_mc_program(rdev);
1a029b76
JG		 1574 if (rdev->flags & RADEON_IS_AGP) {
1575 r600_agp_enable(rdev);
1576 } else {
1577 r = r600_pcie_gart_enable(rdev);
1578 if (r)
1579 return r;
1580 }
3ce0a23d 1581 r600_gpu_init(rdev);
bc1a631e 1582
4c788679
JG		 1583 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1584 if (unlikely(r != 0))
1585 return r;
1586 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1587 &rdev->r600_blit.shader_gpu_addr);
1588 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
bc1a631e 1589 if (r) {
4c788679 1590 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
bc1a631e
DA		 1591 return r;
1592 }
1593
d8f60cfc 1594 /* Enable IRQ */
d8f60cfc
AD		 1595 r = r600_irq_init(rdev);
1596 if (r) {
1597 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1598 radeon_irq_kms_fini(rdev);
1599 return r;
1600 }
1601 r600_irq_set(rdev);
1602
3ce0a23d
JG		 1603 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1604 if (r)
1605 return r;
1606 r = r600_cp_load_microcode(rdev);
1607 if (r)
1608 return r;
1609 r = r600_cp_resume(rdev);
1610 if (r)
1611 return r;
81cc35bf
JG		 1612 /* write back buffer are not vital so don't worry about failure */
1613 r600_wb_enable(rdev);
3ce0a23d
JG		 1614 return 0;
1615}
1616
28d52043
DA		 1617void r600_vga_set_state(struct radeon_device *rdev, bool state)
1618{
1619 uint32_t temp;
1620
1621 temp = RREG32(CONFIG_CNTL);
1622 if (state == false) {
1623 temp &= ~(1<<0);
1624 temp |= (1<<1);
1625 } else {
1626 temp &= ~(1<<1);
1627 }
1628 WREG32(CONFIG_CNTL, temp);
1629}
1630
fc30b8ef
DA		 1631int r600_resume(struct radeon_device *rdev)
1632{
1633 int r;
1634
1a029b76
JG		 1635 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1636 * posting will perform necessary task to bring back GPU into good
1637 * shape.
1638 */
fc30b8ef 1639 /* post card */
e7d40b9a 1640 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 1641 /* Initialize clocks */
1642 r = radeon_clocks_init(rdev);
1643 if (r) {
1644 return r;
1645 }
1646
1647 r = r600_startup(rdev);
1648 if (r) {
1649 DRM_ERROR("r600 startup failed on resume\n");
1650 return r;
1651 }
1652
62a8ea3f 1653 r = r600_ib_test(rdev);
fc30b8ef
DA		 1654 if (r) {
1655 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1656 return r;
1657 }
1658 return r;
1659}
1660
3ce0a23d
JG		 1661int r600_suspend(struct radeon_device *rdev)
1662{
4c788679
JG		 1663 int r;
1664
3ce0a23d
JG		 1665 /* FIXME: we should wait for ring to be empty */
1666 r600_cp_stop(rdev);
bc1a631e 1667 rdev->cp.ready = false;
81cc35bf 1668 r600_wb_disable(rdev);
4aac0473 1669 r600_pcie_gart_disable(rdev);
bc1a631e 1670 /* unpin shaders bo */
4c788679
JG		 1671 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1672 if (unlikely(r != 0))
1673 return r;
1674 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1675 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3ce0a23d
JG		 1676 return 0;
1677}
1678
1679/* Plan is to move initialization in that function and use
1680 * helper function so that radeon_device_init pretty much
1681 * do nothing more than calling asic specific function. This
1682 * should also allow to remove a bunch of callback function
1683 * like vram_info.
1684 */
1685int r600_init(struct radeon_device *rdev)
771fe6b9 1686{
3ce0a23d 1687 int r;
771fe6b9 1688
3ce0a23d
JG		 1689 r = radeon_dummy_page_init(rdev);
1690 if (r)
1691 return r;
1692 if (r600_debugfs_mc_info_init(rdev)) {
1693 DRM_ERROR("Failed to register debugfs file for mc !\n");
1694 }
1695 /* This don't do much */
1696 r = radeon_gem_init(rdev);
1697 if (r)
1698 return r;
1699 /* Read BIOS */
1700 if (!radeon_get_bios(rdev)) {
1701 if (ASIC_IS_AVIVO(rdev))
1702 return -EINVAL;
1703 }
1704 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1705 if (!rdev->is_atom_bios) {
1706 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1707 return -EINVAL;
e7d40b9a 1708 }
3ce0a23d
JG		 1709 r = radeon_atombios_init(rdev);
1710 if (r)
1711 return r;
1712 /* Post card if necessary */
72542d77
DA		 1713 if (!r600_card_posted(rdev)) {
1714 if (!rdev->bios) {
1715 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1716 return -EINVAL;
1717 }
3ce0a23d
JG		 1718 DRM_INFO("GPU not posted. posting now...\n");
1719 atom_asic_init(rdev->mode_info.atom_context);
1720 }
1721 /* Initialize scratch registers */
1722 r600_scratch_init(rdev);
1723 /* Initialize surface registers */
1724 radeon_surface_init(rdev);
7433874e 1725 /* Initialize clocks */
5e6dde7e 1726 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1727 r = radeon_clocks_init(rdev);
1728 if (r)
1729 return r;
7433874e
RM		 1730 /* Initialize power management */
1731 radeon_pm_init(rdev);
3ce0a23d
JG		 1732 /* Fence driver */
1733 r = radeon_fence_driver_init(rdev);
1734 if (r)
1735 return r;
1736 r = r600_mc_init(rdev);
b574f251 1737 if (r)
3ce0a23d 1738 return r;
3ce0a23d 1739 /* Memory manager */
4c788679 1740 r = radeon_bo_init(rdev);
3ce0a23d
JG		 1741 if (r)
1742 return r;
d8f60cfc
AD		 1743
1744 r = radeon_irq_kms_init(rdev);
1745 if (r)
1746 return r;
1747
3ce0a23d
JG		 1748 rdev->cp.ring_obj = NULL;
1749 r600_ring_init(rdev, 1024 * 1024);
1750
d8f60cfc
AD		 1751 rdev->ih.ring_obj = NULL;
1752 r600_ih_ring_init(rdev, 64 * 1024);
1753
1754 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1755 r = r600_init_microcode(rdev);
3ce0a23d
JG		 1756 if (r) {
1757 DRM_ERROR("Failed to load firmware!\n");
1758 return r;
1759 }
1760 }
1761
4aac0473
JG		 1762 r = r600_pcie_gart_init(rdev);
1763 if (r)
1764 return r;
1765
733289c2 1766 rdev->accel_working = true;
bc1a631e
DA		 1767 r = r600_blit_init(rdev);
1768 if (r) {
1769 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1770 return r;
1771 }
1772
fc30b8ef 1773 r = r600_startup(rdev);
3ce0a23d 1774 if (r) {
75c81298
JG		 1775 r600_suspend(rdev);
1776 r600_wb_fini(rdev);
75c81298
JG		 1777 radeon_ring_fini(rdev);
1778 r600_pcie_gart_fini(rdev);
733289c2 1779 rdev->accel_working = false;
3ce0a23d 1780 }
733289c2
JG		 1781 if (rdev->accel_working) {
1782 r = radeon_ib_pool_init(rdev);
1783 if (r) {
1784 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1785 rdev->accel_working = false;
1786 }
62a8ea3f 1787 r = r600_ib_test(rdev);
733289c2
JG		 1788 if (r) {
1789 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1790 rdev->accel_working = false;
1791 }
3ce0a23d
JG		 1792 }
1793 return 0;
1794}
1795
1796void r600_fini(struct radeon_device *rdev)
1797{
1798 /* Suspend operations */
1799 r600_suspend(rdev);
1800
1801 r600_blit_fini(rdev);
d8f60cfc
AD		 1802 r600_irq_fini(rdev);
1803 radeon_irq_kms_fini(rdev);
3ce0a23d 1804 radeon_ring_fini(rdev);
81cc35bf 1805 r600_wb_fini(rdev);
4aac0473 1806 r600_pcie_gart_fini(rdev);
3ce0a23d
JG		 1807 radeon_gem_fini(rdev);
1808 radeon_fence_driver_fini(rdev);
1809 radeon_clocks_fini(rdev);
3ce0a23d
JG		 1810 if (rdev->flags & RADEON_IS_AGP)
1811 radeon_agp_fini(rdev);
4c788679 1812 radeon_bo_fini(rdev);
e7d40b9a 1813 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1814 kfree(rdev->bios);
1815 rdev->bios = NULL;
1816 radeon_dummy_page_fini(rdev);
1817}
1818
1819
1820/*
1821 * CS stuff
1822 */
1823void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1824{
1825 /* FIXME: implement */
1826 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1827 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1828 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1829 radeon_ring_write(rdev, ib->length_dw);
1830}
1831
1832int r600_ib_test(struct radeon_device *rdev)
1833{
1834 struct radeon_ib *ib;
1835 uint32_t scratch;
1836 uint32_t tmp = 0;
1837 unsigned i;
1838 int r;
1839
1840 r = radeon_scratch_get(rdev, &scratch);
1841 if (r) {
1842 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1843 return r;
1844 }
1845 WREG32(scratch, 0xCAFEDEAD);
1846 r = radeon_ib_get(rdev, &ib);
1847 if (r) {
1848 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1849 return r;
1850 }
1851 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1852 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1853 ib->ptr[2] = 0xDEADBEEF;
1854 ib->ptr[3] = PACKET2(0);
1855 ib->ptr[4] = PACKET2(0);
1856 ib->ptr[5] = PACKET2(0);
1857 ib->ptr[6] = PACKET2(0);
1858 ib->ptr[7] = PACKET2(0);
1859 ib->ptr[8] = PACKET2(0);
1860 ib->ptr[9] = PACKET2(0);
1861 ib->ptr[10] = PACKET2(0);
1862 ib->ptr[11] = PACKET2(0);
1863 ib->ptr[12] = PACKET2(0);
1864 ib->ptr[13] = PACKET2(0);
1865 ib->ptr[14] = PACKET2(0);
1866 ib->ptr[15] = PACKET2(0);
1867 ib->length_dw = 16;
1868 r = radeon_ib_schedule(rdev, ib);
1869 if (r) {
1870 radeon_scratch_free(rdev, scratch);
1871 radeon_ib_free(rdev, &ib);
1872 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1873 return r;
1874 }
1875 r = radeon_fence_wait(ib->fence, false);
1876 if (r) {
1877 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1878 return r;
1879 }
1880 for (i = 0; i < rdev->usec_timeout; i++) {
1881 tmp = RREG32(scratch);
1882 if (tmp == 0xDEADBEEF)
1883 break;
1884 DRM_UDELAY(1);
1885 }
1886 if (i < rdev->usec_timeout) {
1887 DRM_INFO("ib test succeeded in %u usecs\n", i);
1888 } else {
1889 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1890 scratch, tmp);
1891 r = -EINVAL;
1892 }
1893 radeon_scratch_free(rdev, scratch);
1894 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 1895 return r;
1896}
1897
d8f60cfc
AD		 1898/*
1899 * Interrupts
1900 *
1901 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
1902 * the same as the CP ring buffer, but in reverse. Rather than the CPU
1903 * writing to the ring and the GPU consuming, the GPU writes to the ring
1904 * and host consumes. As the host irq handler processes interrupts, it
1905 * increments the rptr. When the rptr catches up with the wptr, all the
1906 * current interrupts have been processed.
1907 */
1908
1909void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
1910{
1911 u32 rb_bufsz;
1912
1913 /* Align ring size */
1914 rb_bufsz = drm_order(ring_size / 4);
1915 ring_size = (1 << rb_bufsz) * 4;
1916 rdev->ih.ring_size = ring_size;
1917 rdev->ih.align_mask = 4 - 1;
1918}
1919
1920static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
1921{
1922 int r;
1923
1924 rdev->ih.ring_size = ring_size;
1925 /* Allocate ring buffer */
1926 if (rdev->ih.ring_obj == NULL) {
4c788679
JG		 1927 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
1928 true,
1929 RADEON_GEM_DOMAIN_GTT,
1930 &rdev->ih.ring_obj);
d8f60cfc
AD		 1931 if (r) {
1932 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
1933 return r;
1934 }
4c788679
JG		 1935 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
1936 if (unlikely(r != 0))
1937 return r;
1938 r = radeon_bo_pin(rdev->ih.ring_obj,
1939 RADEON_GEM_DOMAIN_GTT,
1940 &rdev->ih.gpu_addr);
d8f60cfc 1941 if (r) {
4c788679 1942 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 1943 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
1944 return r;
1945 }
4c788679
JG		 1946 r = radeon_bo_kmap(rdev->ih.ring_obj,
1947 (void **)&rdev->ih.ring);
1948 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 1949 if (r) {
1950 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
1951 return r;
1952 }
1953 }
1954 rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
1955 rdev->ih.rptr = 0;
1956
1957 return 0;
1958}
1959
1960static void r600_ih_ring_fini(struct radeon_device *rdev)
1961{
4c788679 1962 int r;
d8f60cfc 1963 if (rdev->ih.ring_obj) {
4c788679
JG		 1964 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
1965 if (likely(r == 0)) {
1966 radeon_bo_kunmap(rdev->ih.ring_obj);
1967 radeon_bo_unpin(rdev->ih.ring_obj);
1968 radeon_bo_unreserve(rdev->ih.ring_obj);
1969 }
1970 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 1971 rdev->ih.ring = NULL;
1972 rdev->ih.ring_obj = NULL;
1973 }
1974}
1975
1976static void r600_rlc_stop(struct radeon_device *rdev)
1977{
1978
1979 if (rdev->family >= CHIP_RV770) {
1980 /* r7xx asics need to soft reset RLC before halting */
1981 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
1982 RREG32(SRBM_SOFT_RESET);
1983 udelay(15000);
1984 WREG32(SRBM_SOFT_RESET, 0);
1985 RREG32(SRBM_SOFT_RESET);
1986 }
1987
1988 WREG32(RLC_CNTL, 0);
1989}
1990
1991static void r600_rlc_start(struct radeon_device *rdev)
1992{
1993 WREG32(RLC_CNTL, RLC_ENABLE);
1994}
1995
1996static int r600_rlc_init(struct radeon_device *rdev)
1997{
1998 u32 i;
1999 const __be32 *fw_data;
2000
2001 if (!rdev->rlc_fw)
2002 return -EINVAL;
2003
2004 r600_rlc_stop(rdev);
2005
2006 WREG32(RLC_HB_BASE, 0);
2007 WREG32(RLC_HB_CNTL, 0);
2008 WREG32(RLC_HB_RPTR, 0);
2009 WREG32(RLC_HB_WPTR, 0);
2010 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2011 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2012 WREG32(RLC_MC_CNTL, 0);
2013 WREG32(RLC_UCODE_CNTL, 0);
2014
2015 fw_data = (const __be32 *)rdev->rlc_fw->data;
2016 if (rdev->family >= CHIP_RV770) {
2017 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2018 WREG32(RLC_UCODE_ADDR, i);
2019 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2020 }
2021 } else {
2022 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2023 WREG32(RLC_UCODE_ADDR, i);
2024 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2025 }
2026 }
2027 WREG32(RLC_UCODE_ADDR, 0);
2028
2029 r600_rlc_start(rdev);
2030
2031 return 0;
2032}
2033
2034static void r600_enable_interrupts(struct radeon_device *rdev)
2035{
2036 u32 ih_cntl = RREG32(IH_CNTL);
2037 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2038
2039 ih_cntl |= ENABLE_INTR;
2040 ih_rb_cntl |= IH_RB_ENABLE;
2041 WREG32(IH_CNTL, ih_cntl);
2042 WREG32(IH_RB_CNTL, ih_rb_cntl);
2043 rdev->ih.enabled = true;
2044}
2045
2046static void r600_disable_interrupts(struct radeon_device *rdev)
2047{
2048 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2049 u32 ih_cntl = RREG32(IH_CNTL);
2050
2051 ih_rb_cntl &= ~IH_RB_ENABLE;
2052 ih_cntl &= ~ENABLE_INTR;
2053 WREG32(IH_RB_CNTL, ih_rb_cntl);
2054 WREG32(IH_CNTL, ih_cntl);
2055 /* set rptr, wptr to 0 */
2056 WREG32(IH_RB_RPTR, 0);
2057 WREG32(IH_RB_WPTR, 0);
2058 rdev->ih.enabled = false;
2059 rdev->ih.wptr = 0;
2060 rdev->ih.rptr = 0;
2061}
2062
2063int r600_irq_init(struct radeon_device *rdev)
2064{
2065 int ret = 0;
2066 int rb_bufsz;
2067 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2068
2069 /* allocate ring */
2070 ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size);
2071 if (ret)
2072 return ret;
2073
2074 /* disable irqs */
2075 r600_disable_interrupts(rdev);
2076
2077 /* init rlc */
2078 ret = r600_rlc_init(rdev);
2079 if (ret) {
2080 r600_ih_ring_fini(rdev);
2081 return ret;
2082 }
2083
2084 /* setup interrupt control */
2085 /* set dummy read address to ring address */
2086 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2087 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2088 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2089 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2090 */
2091 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2092 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2093 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2094 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2095
2096 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2097 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2098
2099 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2100 IH_WPTR_OVERFLOW_CLEAR |
2101 (rb_bufsz << 1));
2102 /* WPTR writeback, not yet */
2103 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2104 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2105 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2106
2107 WREG32(IH_RB_CNTL, ih_rb_cntl);
2108
2109 /* set rptr, wptr to 0 */
2110 WREG32(IH_RB_RPTR, 0);
2111 WREG32(IH_RB_WPTR, 0);
2112
2113 /* Default settings for IH_CNTL (disabled at first) */
2114 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2115 /* RPTR_REARM only works if msi's are enabled */
2116 if (rdev->msi_enabled)
2117 ih_cntl |= RPTR_REARM;
2118
2119#ifdef __BIG_ENDIAN
2120 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2121#endif
2122 WREG32(IH_CNTL, ih_cntl);
2123
2124 /* force the active interrupt state to all disabled */
2125 WREG32(CP_INT_CNTL, 0);
2126 WREG32(GRBM_INT_CNTL, 0);
2127 WREG32(DxMODE_INT_MASK, 0);
2128
2129 /* enable irqs */
2130 r600_enable_interrupts(rdev);
2131
2132 return ret;
2133}
2134
2135void r600_irq_fini(struct radeon_device *rdev)
2136{
2137 r600_disable_interrupts(rdev);
2138 r600_rlc_stop(rdev);
2139 r600_ih_ring_fini(rdev);
2140}
2141
2142int r600_irq_set(struct radeon_device *rdev)
2143{
2144 uint32_t cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2145 uint32_t mode_int = 0;
2146
2147 /* don't enable anything if the ih is disabled */
2148 if (!rdev->ih.enabled)
2149 return 0;
2150
2151 if (rdev->irq.sw_int) {
2152 DRM_DEBUG("r600_irq_set: sw int\n");
2153 cp_int_cntl |= RB_INT_ENABLE;
2154 }
2155 if (rdev->irq.crtc_vblank_int[0]) {
2156 DRM_DEBUG("r600_irq_set: vblank 0\n");
2157 mode_int |= D1MODE_VBLANK_INT_MASK;
2158 }
2159 if (rdev->irq.crtc_vblank_int[1]) {
2160 DRM_DEBUG("r600_irq_set: vblank 1\n");
2161 mode_int |= D2MODE_VBLANK_INT_MASK;
2162 }
2163
2164 WREG32(CP_INT_CNTL, cp_int_cntl);
2165 WREG32(DxMODE_INT_MASK, mode_int);
2166
2167 return 0;
2168}
2169
2170static inline void r600_irq_ack(struct radeon_device *rdev, u32 disp_int)
2171{
2172
2173 if (disp_int & LB_D1_VBLANK_INTERRUPT)
2174 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2175 if (disp_int & LB_D1_VLINE_INTERRUPT)
2176 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2177 if (disp_int & LB_D2_VBLANK_INTERRUPT)
2178 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2179 if (disp_int & LB_D2_VLINE_INTERRUPT)
2180 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2181
2182}
2183
2184void r600_irq_disable(struct radeon_device *rdev)
2185{
2186 u32 disp_int;
2187
2188 r600_disable_interrupts(rdev);
2189 /* Wait and acknowledge irq */
2190 mdelay(1);
2191 if (ASIC_IS_DCE3(rdev))
2192 disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2193 else
2194 disp_int = RREG32(DISP_INTERRUPT_STATUS);
2195 r600_irq_ack(rdev, disp_int);
2196}
2197
2198static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2199{
2200 u32 wptr, tmp;
2201
2202 /* XXX use writeback */
2203 wptr = RREG32(IH_RB_WPTR);
2204
2205 if (wptr & RB_OVERFLOW) {
2206 WARN_ON(1);
2207 /* XXX deal with overflow */
2208 DRM_ERROR("IH RB overflow\n");
2209 tmp = RREG32(IH_RB_CNTL);
2210 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2211 WREG32(IH_RB_CNTL, tmp);
2212 }
2213 wptr = wptr & WPTR_OFFSET_MASK;
3ce0a23d 2214
d8f60cfc
AD		 2215 return wptr;
2216}
3ce0a23d 2217
d8f60cfc
AD		 2218/* r600 IV Ring
2219 * Each IV ring entry is 128 bits:
2220 * [7:0] - interrupt source id
2221 * [31:8] - reserved
2222 * [59:32] - interrupt source data
2223 * [127:60] - reserved
2224 *
2225 * The basic interrupt vector entries
2226 * are decoded as follows:
2227 * src_id src_data description
2228 * 1 0 D1 Vblank
2229 * 1 1 D1 Vline
2230 * 5 0 D2 Vblank
2231 * 5 1 D2 Vline
2232 * 19 0 FP Hot plug detection A
2233 * 19 1 FP Hot plug detection B
2234 * 19 2 DAC A auto-detection
2235 * 19 3 DAC B auto-detection
2236 * 176 - CP_INT RB
2237 * 177 - CP_INT IB1
2238 * 178 - CP_INT IB2
2239 * 181 - EOP Interrupt
2240 * 233 - GUI Idle
2241 *
2242 * Note, these are based on r600 and may need to be
2243 * adjusted or added to on newer asics
2244 */
2245
2246int r600_irq_process(struct radeon_device *rdev)
2247{
2248 u32 wptr = r600_get_ih_wptr(rdev);
2249 u32 rptr = rdev->ih.rptr;
2250 u32 src_id, src_data;
2251 u32 last_entry = rdev->ih.ring_size - 16;
2252 u32 ring_index, disp_int;
2253 unsigned long flags;
2254
2255 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2256
2257 spin_lock_irqsave(&rdev->ih.lock, flags);
2258
2259 if (rptr == wptr) {
2260 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2261 return IRQ_NONE;
2262 }
2263 if (rdev->shutdown) {
2264 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2265 return IRQ_NONE;
2266 }
2267
2268restart_ih:
2269 /* display interrupts */
2270 if (ASIC_IS_DCE3(rdev))
2271 disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2272 else
2273 disp_int = RREG32(DISP_INTERRUPT_STATUS);
2274 r600_irq_ack(rdev, disp_int);
2275
2276 rdev->ih.wptr = wptr;
2277 while (rptr != wptr) {
2278 /* wptr/rptr are in bytes! */
2279 ring_index = rptr / 4;
2280 src_id = rdev->ih.ring[ring_index] & 0xff;
2281 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2282
2283 switch (src_id) {
2284 case 1: /* D1 vblank/vline */
2285 switch (src_data) {
2286 case 0: /* D1 vblank */
2287 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2288 drm_handle_vblank(rdev->ddev, 0);
2289 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2290 DRM_DEBUG("IH: D1 vblank\n");
2291 }
2292 break;
2293 case 1: /* D1 vline */
2294 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2295 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2296 DRM_DEBUG("IH: D1 vline\n");
2297 }
2298 break;
2299 default:
2300 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2301 break;
2302 }
2303 break;
2304 case 5: /* D2 vblank/vline */
2305 switch (src_data) {
2306 case 0: /* D2 vblank */
2307 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2308 drm_handle_vblank(rdev->ddev, 1);
2309 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2310 DRM_DEBUG("IH: D2 vblank\n");
2311 }
2312 break;
2313 case 1: /* D1 vline */
2314 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2315 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2316 DRM_DEBUG("IH: D2 vline\n");
2317 }
2318 break;
2319 default:
2320 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2321 break;
2322 }
2323 break;
2324 case 176: /* CP_INT in ring buffer */
2325 case 177: /* CP_INT in IB1 */
2326 case 178: /* CP_INT in IB2 */
2327 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2328 radeon_fence_process(rdev);
2329 break;
2330 case 181: /* CP EOP event */
2331 DRM_DEBUG("IH: CP EOP\n");
2332 break;
2333 default:
2334 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2335 break;
2336 }
2337
2338 /* wptr/rptr are in bytes! */
2339 if (rptr == last_entry)
2340 rptr = 0;
2341 else
2342 rptr += 16;
2343 }
2344 /* make sure wptr hasn't changed while processing */
2345 wptr = r600_get_ih_wptr(rdev);
2346 if (wptr != rdev->ih.wptr)
2347 goto restart_ih;
2348 rdev->ih.rptr = rptr;
2349 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2350 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2351 return IRQ_HANDLED;
2352}
3ce0a23d
JG		 2353
2354/*
2355 * Debugfs info
2356 */
2357#if defined(CONFIG_DEBUG_FS)
2358
2359static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 2360{
3ce0a23d
JG		 2361 struct drm_info_node *node = (struct drm_info_node *) m->private;
2362 struct drm_device *dev = node->minor->dev;
2363 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 2364 unsigned count, i, j;
2365
2366 radeon_ring_free_size(rdev);
d6840766 2367 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 2368 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 2369 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2370 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2371 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2372 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 2373 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2374 seq_printf(m, "%u dwords in ring\n", count);
d6840766 2375 i = rdev->cp.rptr;
3ce0a23d 2376 for (j = 0; j <= count; j++) {
3ce0a23d 2377 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 2378 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 2379 }
2380 return 0;
2381}
2382
2383static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2384{
2385 struct drm_info_node *node = (struct drm_info_node *) m->private;
2386 struct drm_device *dev = node->minor->dev;
2387 struct radeon_device *rdev = dev->dev_private;
2388
2389 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2390 DREG32_SYS(m, rdev, VM_L2_STATUS);
2391 return 0;
2392}
2393
2394static struct drm_info_list r600_mc_info_list[] = {
2395 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2396 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2397};
2398#endif
2399
2400int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2401{
2402#if defined(CONFIG_DEBUG_FS)
2403 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2404#else
2405 return 0;
2406#endif
771fe6b9 2407}
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