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drm/radeon/r600: fix some issues with suspend/resume.
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/seq_file.h>
29#include <linux/firmware.h>
30#include <linux/platform_device.h>
771fe6b9 31#include "drmP.h"
3ce0a23d 32#include "radeon_drm.h"
771fe6b9 33#include "radeon.h"
3ce0a23d 34#include "radeon_mode.h"
3ce0a23d
JG		 35#include "r600d.h"
36#include "avivod.h"
37#include "atom.h"
771fe6b9 38
3ce0a23d
JG		 39#define PFP_UCODE_SIZE 576
40#define PM4_UCODE_SIZE 1792
41#define R700_PFP_UCODE_SIZE 848
42#define R700_PM4_UCODE_SIZE 1360
43
44/* Firmware Names */
45MODULE_FIRMWARE("radeon/R600_pfp.bin");
46MODULE_FIRMWARE("radeon/R600_me.bin");
47MODULE_FIRMWARE("radeon/RV610_pfp.bin");
48MODULE_FIRMWARE("radeon/RV610_me.bin");
49MODULE_FIRMWARE("radeon/RV630_pfp.bin");
50MODULE_FIRMWARE("radeon/RV630_me.bin");
51MODULE_FIRMWARE("radeon/RV620_pfp.bin");
52MODULE_FIRMWARE("radeon/RV620_me.bin");
53MODULE_FIRMWARE("radeon/RV635_pfp.bin");
54MODULE_FIRMWARE("radeon/RV635_me.bin");
55MODULE_FIRMWARE("radeon/RV670_pfp.bin");
56MODULE_FIRMWARE("radeon/RV670_me.bin");
57MODULE_FIRMWARE("radeon/RS780_pfp.bin");
58MODULE_FIRMWARE("radeon/RS780_me.bin");
59MODULE_FIRMWARE("radeon/RV770_pfp.bin");
60MODULE_FIRMWARE("radeon/RV770_me.bin");
61MODULE_FIRMWARE("radeon/RV730_pfp.bin");
62MODULE_FIRMWARE("radeon/RV730_me.bin");
63MODULE_FIRMWARE("radeon/RV710_pfp.bin");
64MODULE_FIRMWARE("radeon/RV710_me.bin");
65
66int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9
JG		 67
68/* This files gather functions specifics to:
69 * r600,rv610,rv630,rv620,rv635,rv670
70 *
71 * Some of these functions might be used by newer ASICs.
72 */
73int r600_mc_wait_for_idle(struct radeon_device *rdev);
74void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 75void r600_fini(struct radeon_device *rdev);
771fe6b9
JG		 76
77
78/*
3ce0a23d 79 * R600 PCIE GART
771fe6b9 80 */
3ce0a23d 81int r600_gart_clear_page(struct radeon_device *rdev, int i)
771fe6b9 82{
3ce0a23d
JG		 83 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
84 u64 pte;
771fe6b9 85
3ce0a23d
JG		 86 if (i < 0 || i > rdev->gart.num_gpu_pages)
87 return -EINVAL;
88 pte = 0;
89 writeq(pte, ((void __iomem *)ptr) + (i * 8));
90 return 0;
91}
771fe6b9 92
3ce0a23d
JG		 93void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
94{
95 unsigned i;
96 u32 tmp;
97
98 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
99 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
100 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
101 for (i = 0; i < rdev->usec_timeout; i++) {
102 /* read MC_STATUS */
103 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
104 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
105 if (tmp == 2) {
106 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
107 return;
108 }
109 if (tmp) {
110 return;
111 }
112 udelay(1);
113 }
114}
115
4aac0473 116int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 117{
4aac0473 118 int r;
3ce0a23d 119
4aac0473
JG		 120 if (rdev->gart.table.vram.robj) {
121 WARN(1, "R600 PCIE GART already initialized.\n");
122 return 0;
123 }
3ce0a23d
JG		 124 /* Initialize common gart structure */
125 r = radeon_gart_init(rdev);
4aac0473 126 if (r)
3ce0a23d 127 return r;
3ce0a23d 128 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 129 return radeon_gart_table_vram_alloc(rdev);
130}
131
132int r600_pcie_gart_enable(struct radeon_device *rdev)
133{
134 u32 tmp;
135 int r, i;
136
137 if (rdev->gart.table.vram.robj == NULL) {
138 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
139 return -EINVAL;
771fe6b9 140 }
4aac0473
JG		 141 r = radeon_gart_table_vram_pin(rdev);
142 if (r)
143 return r;
bc1a631e 144
3ce0a23d
JG		 145 /* Setup L2 cache */
146 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
147 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
148 EFFECTIVE_L2_QUEUE_SIZE(7));
149 WREG32(VM_L2_CNTL2, 0);
150 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
151 /* Setup TLB control */
152 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
153 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
154 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
155 ENABLE_WAIT_L2_QUERY;
156 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
157 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
158 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
159 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
160 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
161 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
162 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
163 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
164 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
165 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
166 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
167 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
168 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
169 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
170 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
171 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
172 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
173 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
174 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
175 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
176 (u32)(rdev->dummy_page.addr >> 12));
177 for (i = 1; i < 7; i++)
178 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 179
3ce0a23d
JG		 180 r600_pcie_gart_tlb_flush(rdev);
181 rdev->gart.ready = true;
771fe6b9
JG		 182 return 0;
183}
184
3ce0a23d 185void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 186{
3ce0a23d
JG		 187 u32 tmp;
188 int i;
771fe6b9 189
3ce0a23d
JG		 190 /* Disable all tables */
191 for (i = 0; i < 7; i++)
192 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 193
3ce0a23d
JG		 194 /* Disable L2 cache */
195 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
196 EFFECTIVE_L2_QUEUE_SIZE(7));
197 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
198 /* Setup L1 TLB control */
199 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
200 ENABLE_WAIT_L2_QUERY;
201 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
202 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
203 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
204 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
205 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
206 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
207 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
208 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
209 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
210 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
211 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
212 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
213 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
214 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473
JG		 215 if (rdev->gart.table.vram.robj) {
216 radeon_object_kunmap(rdev->gart.table.vram.robj);
217 radeon_object_unpin(rdev->gart.table.vram.robj);
218 }
219}
220
221void r600_pcie_gart_fini(struct radeon_device *rdev)
222{
223 r600_pcie_gart_disable(rdev);
224 radeon_gart_table_vram_free(rdev);
225 radeon_gart_fini(rdev);
771fe6b9
JG		 226}
227
228int r600_mc_wait_for_idle(struct radeon_device *rdev)
229{
3ce0a23d
JG		 230 unsigned i;
231 u32 tmp;
232
233 for (i = 0; i < rdev->usec_timeout; i++) {
234 /* read MC_STATUS */
235 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
236 if (!tmp)
237 return 0;
238 udelay(1);
239 }
240 return -1;
771fe6b9
JG		 241}
242
3ce0a23d 243static void r600_mc_resume(struct radeon_device *rdev)
771fe6b9 244{
3ce0a23d
JG		 245 u32 d1vga_control, d2vga_control;
246 u32 vga_render_control, vga_hdp_control;
247 u32 d1crtc_control, d2crtc_control;
248 u32 new_d1grph_primary, new_d1grph_secondary;
249 u32 new_d2grph_primary, new_d2grph_secondary;
250 u64 old_vram_start;
251 u32 tmp;
252 int i, j;
771fe6b9 253
3ce0a23d
JG		 254 /* Initialize HDP */
255 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
256 WREG32((0x2c14 + j), 0x00000000);
257 WREG32((0x2c18 + j), 0x00000000);
258 WREG32((0x2c1c + j), 0x00000000);
259 WREG32((0x2c20 + j), 0x00000000);
260 WREG32((0x2c24 + j), 0x00000000);
261 }
262 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 263
3ce0a23d
JG		 264 d1vga_control = RREG32(D1VGA_CONTROL);
265 d2vga_control = RREG32(D2VGA_CONTROL);
266 vga_render_control = RREG32(VGA_RENDER_CONTROL);
267 vga_hdp_control = RREG32(VGA_HDP_CONTROL);
268 d1crtc_control = RREG32(D1CRTC_CONTROL);
269 d2crtc_control = RREG32(D2CRTC_CONTROL);
270 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
271 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
272 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
273 new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
274 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
275 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
276 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
277 new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
278 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
279
280 /* Stop all video */
281 WREG32(D1VGA_CONTROL, 0);
282 WREG32(D2VGA_CONTROL, 0);
283 WREG32(VGA_RENDER_CONTROL, 0);
284 WREG32(D1CRTC_UPDATE_LOCK, 1);
285 WREG32(D2CRTC_UPDATE_LOCK, 1);
286 WREG32(D1CRTC_CONTROL, 0);
287 WREG32(D2CRTC_CONTROL, 0);
288 WREG32(D1CRTC_UPDATE_LOCK, 0);
289 WREG32(D2CRTC_UPDATE_LOCK, 0);
290
291 mdelay(1);
292 if (r600_mc_wait_for_idle(rdev)) {
293 printk(KERN_WARNING "[drm] MC not idle !\n");
294 }
295
296 /* Lockout access through VGA aperture*/
297 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
298
299 /* Update configuration */
300 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
301 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
302 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
303 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
304 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
305 WREG32(MC_VM_FB_LOCATION, tmp);
306 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
307 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
308 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
309 if (rdev->flags & RADEON_IS_AGP) {
310 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
311 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
312 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
313 } else {
314 WREG32(MC_VM_AGP_BASE, 0);
315 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
316 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
317 }
318 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
319 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
320 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
321 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
322 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
323
324 /* Unlock host access */
325 WREG32(VGA_HDP_CONTROL, vga_hdp_control);
326
327 mdelay(1);
328 if (r600_mc_wait_for_idle(rdev)) {
329 printk(KERN_WARNING "[drm] MC not idle !\n");
330 }
331
332 /* Restore video state */
333 WREG32(D1CRTC_UPDATE_LOCK, 1);
334 WREG32(D2CRTC_UPDATE_LOCK, 1);
335 WREG32(D1CRTC_CONTROL, d1crtc_control);
336 WREG32(D2CRTC_CONTROL, d2crtc_control);
337 WREG32(D1CRTC_UPDATE_LOCK, 0);
338 WREG32(D2CRTC_UPDATE_LOCK, 0);
339 WREG32(D1VGA_CONTROL, d1vga_control);
340 WREG32(D2VGA_CONTROL, d2vga_control);
341 WREG32(VGA_RENDER_CONTROL, vga_render_control);
698443d9
DA		 342
343 /* we need to own VRAM, so turn off the VGA renderer here
344 * to stop it overwriting our objects */
345 radeon_avivo_vga_render_disable(rdev);
3ce0a23d
JG		 346}
347
348int r600_mc_init(struct radeon_device *rdev)
771fe6b9 349{
3ce0a23d
JG		 350 fixed20_12 a;
351 u32 tmp;
771fe6b9 352 int chansize;
3ce0a23d 353 int r;
771fe6b9 354
3ce0a23d 355 /* Get VRAM informations */
771fe6b9
JG		 356 rdev->mc.vram_width = 128;
357 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 358 tmp = RREG32(RAMCFG);
359 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 360 chansize = 16;
3ce0a23d 361 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 362 chansize = 64;
363 } else {
364 chansize = 32;
365 }
366 if (rdev->family == CHIP_R600) {
367 rdev->mc.vram_width = 8 * chansize;
368 } else if (rdev->family == CHIP_RV670) {
369 rdev->mc.vram_width = 4 * chansize;
370 } else if ((rdev->family == CHIP_RV610) ||
371 (rdev->family == CHIP_RV620)) {
372 rdev->mc.vram_width = chansize;
373 } else if ((rdev->family == CHIP_RV630) ||
374 (rdev->family == CHIP_RV635)) {
375 rdev->mc.vram_width = 2 * chansize;
376 }
3ce0a23d
JG		 377 /* Could aper size report 0 ? */
378 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
379 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
380 /* Setup GPU memory space */
381 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
382 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
383 if (rdev->flags & RADEON_IS_AGP) {
384 r = radeon_agp_init(rdev);
385 if (r)
386 return r;
387 /* gtt_size is setup by radeon_agp_init */
388 rdev->mc.gtt_location = rdev->mc.agp_base;
389 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
390 /* Try to put vram before or after AGP because we
391 * we want SYSTEM_APERTURE to cover both VRAM and
392 * AGP so that GPU can catch out of VRAM/AGP access
393 */
394 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
395 /* Enought place before */
396 rdev->mc.vram_location = rdev->mc.gtt_location -
397 rdev->mc.mc_vram_size;
398 } else if (tmp > rdev->mc.mc_vram_size) {
399 /* Enought place after */
400 rdev->mc.vram_location = rdev->mc.gtt_location +
401 rdev->mc.gtt_size;
402 } else {
403 /* Try to setup VRAM then AGP might not
404 * not work on some card
405 */
406 rdev->mc.vram_location = 0x00000000UL;
407 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
408 }
409 } else {
410 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
411 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
412 0xFFFF) << 24;
413 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
414 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
415 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
416 /* Enough place after vram */
417 rdev->mc.gtt_location = tmp;
418 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
419 /* Enough place before vram */
420 rdev->mc.gtt_location = 0;
421 } else {
422 /* Not enough place after or before shrink
423 * gart size
424 */
425 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
426 rdev->mc.gtt_location = 0;
427 rdev->mc.gtt_size = rdev->mc.vram_location;
428 } else {
429 rdev->mc.gtt_location = tmp;
430 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
431 }
432 }
433 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
434 } else {
435 rdev->mc.vram_location = 0x00000000UL;
436 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
437 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
438 }
439 }
440 rdev->mc.vram_start = rdev->mc.vram_location;
441 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
442 rdev->mc.gtt_start = rdev->mc.gtt_location;
443 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
444 /* FIXME: we should enforce default clock in case GPU is not in
445 * default setup
446 */
447 a.full = rfixed_const(100);
448 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
449 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
450 return 0;
771fe6b9
JG		 451}
452
3ce0a23d
JG		 453/* We doesn't check that the GPU really needs a reset we simply do the
454 * reset, it's up to the caller to determine if the GPU needs one. We
455 * might add an helper function to check that.
456 */
457int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 458{
3ce0a23d
JG		 459 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
460 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
461 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
462 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
463 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
464 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
465 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
466 S_008010_GUI_ACTIVE(1);
467 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
468 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
469 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
470 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
471 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
472 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
473 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
474 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
475 u32 srbm_reset = 0;
771fe6b9 476
3ce0a23d
JG		 477 /* Disable CP parsing/prefetching */
478 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
479 /* Check if any of the rendering block is busy and reset it */
480 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
481 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
482 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
483 S_008020_SOFT_RESET_DB(1) |
484 S_008020_SOFT_RESET_CB(1) |
485 S_008020_SOFT_RESET_PA(1) |
486 S_008020_SOFT_RESET_SC(1) |
487 S_008020_SOFT_RESET_SMX(1) |
488 S_008020_SOFT_RESET_SPI(1) |
489 S_008020_SOFT_RESET_SX(1) |
490 S_008020_SOFT_RESET_SH(1) |
491 S_008020_SOFT_RESET_TC(1) |
492 S_008020_SOFT_RESET_TA(1) |
493 S_008020_SOFT_RESET_VC(1) |
494 S_008020_SOFT_RESET_VGT(1));
495 (void)RREG32(R_008020_GRBM_SOFT_RESET);
496 udelay(50);
497 WREG32(R_008020_GRBM_SOFT_RESET, 0);
498 (void)RREG32(R_008020_GRBM_SOFT_RESET);
499 }
500 /* Reset CP (we always reset CP) */
501 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
502 (void)RREG32(R_008020_GRBM_SOFT_RESET);
503 udelay(50);
504 WREG32(R_008020_GRBM_SOFT_RESET, 0);
505 (void)RREG32(R_008020_GRBM_SOFT_RESET);
506 /* Reset others GPU block if necessary */
507 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
508 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
509 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
510 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
511 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
512 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
513 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
514 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
515 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
516 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
517 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
518 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
519 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
520 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
521 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
522 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
523 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
524 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
525 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
526 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
527 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
528 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
529 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
530 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
531 udelay(50);
532 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
533 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
534 /* Wait a little for things to settle down */
535 udelay(50);
536 return 0;
537}
538
539int r600_gpu_reset(struct radeon_device *rdev)
540{
541 return r600_gpu_soft_reset(rdev);
542}
543
544static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
545 u32 num_backends,
546 u32 backend_disable_mask)
547{
548 u32 backend_map = 0;
549 u32 enabled_backends_mask;
550 u32 enabled_backends_count;
551 u32 cur_pipe;
552 u32 swizzle_pipe[R6XX_MAX_PIPES];
553 u32 cur_backend;
554 u32 i;
555
556 if (num_tile_pipes > R6XX_MAX_PIPES)
557 num_tile_pipes = R6XX_MAX_PIPES;
558 if (num_tile_pipes < 1)
559 num_tile_pipes = 1;
560 if (num_backends > R6XX_MAX_BACKENDS)
561 num_backends = R6XX_MAX_BACKENDS;
562 if (num_backends < 1)
563 num_backends = 1;
564
565 enabled_backends_mask = 0;
566 enabled_backends_count = 0;
567 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
568 if (((backend_disable_mask >> i) & 1) == 0) {
569 enabled_backends_mask |= (1 << i);
570 ++enabled_backends_count;
571 }
572 if (enabled_backends_count == num_backends)
573 break;
574 }
575
576 if (enabled_backends_count == 0) {
577 enabled_backends_mask = 1;
578 enabled_backends_count = 1;
579 }
580
581 if (enabled_backends_count != num_backends)
582 num_backends = enabled_backends_count;
583
584 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
585 switch (num_tile_pipes) {
586 case 1:
587 swizzle_pipe[0] = 0;
588 break;
589 case 2:
590 swizzle_pipe[0] = 0;
591 swizzle_pipe[1] = 1;
592 break;
593 case 3:
594 swizzle_pipe[0] = 0;
595 swizzle_pipe[1] = 1;
596 swizzle_pipe[2] = 2;
597 break;
598 case 4:
599 swizzle_pipe[0] = 0;
600 swizzle_pipe[1] = 1;
601 swizzle_pipe[2] = 2;
602 swizzle_pipe[3] = 3;
603 break;
604 case 5:
605 swizzle_pipe[0] = 0;
606 swizzle_pipe[1] = 1;
607 swizzle_pipe[2] = 2;
608 swizzle_pipe[3] = 3;
609 swizzle_pipe[4] = 4;
610 break;
611 case 6:
612 swizzle_pipe[0] = 0;
613 swizzle_pipe[1] = 2;
614 swizzle_pipe[2] = 4;
615 swizzle_pipe[3] = 5;
616 swizzle_pipe[4] = 1;
617 swizzle_pipe[5] = 3;
618 break;
619 case 7:
620 swizzle_pipe[0] = 0;
621 swizzle_pipe[1] = 2;
622 swizzle_pipe[2] = 4;
623 swizzle_pipe[3] = 6;
624 swizzle_pipe[4] = 1;
625 swizzle_pipe[5] = 3;
626 swizzle_pipe[6] = 5;
627 break;
628 case 8:
629 swizzle_pipe[0] = 0;
630 swizzle_pipe[1] = 2;
631 swizzle_pipe[2] = 4;
632 swizzle_pipe[3] = 6;
633 swizzle_pipe[4] = 1;
634 swizzle_pipe[5] = 3;
635 swizzle_pipe[6] = 5;
636 swizzle_pipe[7] = 7;
637 break;
638 }
639
640 cur_backend = 0;
641 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
642 while (((1 << cur_backend) & enabled_backends_mask) == 0)
643 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
644
645 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
646
647 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
648 }
649
650 return backend_map;
651}
652
653int r600_count_pipe_bits(uint32_t val)
654{
655 int i, ret = 0;
656
657 for (i = 0; i < 32; i++) {
658 ret += val & 1;
659 val >>= 1;
660 }
661 return ret;
771fe6b9
JG		 662}
663
3ce0a23d
JG		 664void r600_gpu_init(struct radeon_device *rdev)
665{
666 u32 tiling_config;
667 u32 ramcfg;
668 u32 tmp;
669 int i, j;
670 u32 sq_config;
671 u32 sq_gpr_resource_mgmt_1 = 0;
672 u32 sq_gpr_resource_mgmt_2 = 0;
673 u32 sq_thread_resource_mgmt = 0;
674 u32 sq_stack_resource_mgmt_1 = 0;
675 u32 sq_stack_resource_mgmt_2 = 0;
676
677 /* FIXME: implement */
678 switch (rdev->family) {
679 case CHIP_R600:
680 rdev->config.r600.max_pipes = 4;
681 rdev->config.r600.max_tile_pipes = 8;
682 rdev->config.r600.max_simds = 4;
683 rdev->config.r600.max_backends = 4;
684 rdev->config.r600.max_gprs = 256;
685 rdev->config.r600.max_threads = 192;
686 rdev->config.r600.max_stack_entries = 256;
687 rdev->config.r600.max_hw_contexts = 8;
688 rdev->config.r600.max_gs_threads = 16;
689 rdev->config.r600.sx_max_export_size = 128;
690 rdev->config.r600.sx_max_export_pos_size = 16;
691 rdev->config.r600.sx_max_export_smx_size = 128;
692 rdev->config.r600.sq_num_cf_insts = 2;
693 break;
694 case CHIP_RV630:
695 case CHIP_RV635:
696 rdev->config.r600.max_pipes = 2;
697 rdev->config.r600.max_tile_pipes = 2;
698 rdev->config.r600.max_simds = 3;
699 rdev->config.r600.max_backends = 1;
700 rdev->config.r600.max_gprs = 128;
701 rdev->config.r600.max_threads = 192;
702 rdev->config.r600.max_stack_entries = 128;
703 rdev->config.r600.max_hw_contexts = 8;
704 rdev->config.r600.max_gs_threads = 4;
705 rdev->config.r600.sx_max_export_size = 128;
706 rdev->config.r600.sx_max_export_pos_size = 16;
707 rdev->config.r600.sx_max_export_smx_size = 128;
708 rdev->config.r600.sq_num_cf_insts = 2;
709 break;
710 case CHIP_RV610:
711 case CHIP_RV620:
712 case CHIP_RS780:
713 case CHIP_RS880:
714 rdev->config.r600.max_pipes = 1;
715 rdev->config.r600.max_tile_pipes = 1;
716 rdev->config.r600.max_simds = 2;
717 rdev->config.r600.max_backends = 1;
718 rdev->config.r600.max_gprs = 128;
719 rdev->config.r600.max_threads = 192;
720 rdev->config.r600.max_stack_entries = 128;
721 rdev->config.r600.max_hw_contexts = 4;
722 rdev->config.r600.max_gs_threads = 4;
723 rdev->config.r600.sx_max_export_size = 128;
724 rdev->config.r600.sx_max_export_pos_size = 16;
725 rdev->config.r600.sx_max_export_smx_size = 128;
726 rdev->config.r600.sq_num_cf_insts = 1;
727 break;
728 case CHIP_RV670:
729 rdev->config.r600.max_pipes = 4;
730 rdev->config.r600.max_tile_pipes = 4;
731 rdev->config.r600.max_simds = 4;
732 rdev->config.r600.max_backends = 4;
733 rdev->config.r600.max_gprs = 192;
734 rdev->config.r600.max_threads = 192;
735 rdev->config.r600.max_stack_entries = 256;
736 rdev->config.r600.max_hw_contexts = 8;
737 rdev->config.r600.max_gs_threads = 16;
738 rdev->config.r600.sx_max_export_size = 128;
739 rdev->config.r600.sx_max_export_pos_size = 16;
740 rdev->config.r600.sx_max_export_smx_size = 128;
741 rdev->config.r600.sq_num_cf_insts = 2;
742 break;
743 default:
744 break;
745 }
746
747 /* Initialize HDP */
748 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
749 WREG32((0x2c14 + j), 0x00000000);
750 WREG32((0x2c18 + j), 0x00000000);
751 WREG32((0x2c1c + j), 0x00000000);
752 WREG32((0x2c20 + j), 0x00000000);
753 WREG32((0x2c24 + j), 0x00000000);
754 }
755
756 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
757
758 /* Setup tiling */
759 tiling_config = 0;
760 ramcfg = RREG32(RAMCFG);
761 switch (rdev->config.r600.max_tile_pipes) {
762 case 1:
763 tiling_config |= PIPE_TILING(0);
764 break;
765 case 2:
766 tiling_config |= PIPE_TILING(1);
767 break;
768 case 4:
769 tiling_config |= PIPE_TILING(2);
770 break;
771 case 8:
772 tiling_config |= PIPE_TILING(3);
773 break;
774 default:
775 break;
776 }
777 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
778 tiling_config |= GROUP_SIZE(0);
779 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
780 if (tmp > 3) {
781 tiling_config |= ROW_TILING(3);
782 tiling_config |= SAMPLE_SPLIT(3);
783 } else {
784 tiling_config |= ROW_TILING(tmp);
785 tiling_config |= SAMPLE_SPLIT(tmp);
786 }
787 tiling_config |= BANK_SWAPS(1);
788 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
789 rdev->config.r600.max_backends,
790 (0xff << rdev->config.r600.max_backends) & 0xff);
791 tiling_config |= BACKEND_MAP(tmp);
792 WREG32(GB_TILING_CONFIG, tiling_config);
793 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
794 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
795
796 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
797 WREG32(CC_RB_BACKEND_DISABLE, tmp);
798
799 /* Setup pipes */
800 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
801 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
802 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
803 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
804
805 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
806 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
807 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
808
809 /* Setup some CP states */
810 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
811 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
812
813 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
814 SYNC_WALKER | SYNC_ALIGNER));
815 /* Setup various GPU states */
816 if (rdev->family == CHIP_RV670)
817 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
818
819 tmp = RREG32(SX_DEBUG_1);
820 tmp |= SMX_EVENT_RELEASE;
821 if ((rdev->family > CHIP_R600))
822 tmp |= ENABLE_NEW_SMX_ADDRESS;
823 WREG32(SX_DEBUG_1, tmp);
824
825 if (((rdev->family) == CHIP_R600) ||
826 ((rdev->family) == CHIP_RV630) ||
827 ((rdev->family) == CHIP_RV610) ||
828 ((rdev->family) == CHIP_RV620) ||
829 ((rdev->family) == CHIP_RS780)) {
830 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
831 } else {
832 WREG32(DB_DEBUG, 0);
833 }
834 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
835 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
836
837 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
838 WREG32(VGT_NUM_INSTANCES, 0);
839
840 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
841 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
842
843 tmp = RREG32(SQ_MS_FIFO_SIZES);
844 if (((rdev->family) == CHIP_RV610) ||
845 ((rdev->family) == CHIP_RV620) ||
846 ((rdev->family) == CHIP_RS780)) {
847 tmp = (CACHE_FIFO_SIZE(0xa) |
848 FETCH_FIFO_HIWATER(0xa) |
849 DONE_FIFO_HIWATER(0xe0) |
850 ALU_UPDATE_FIFO_HIWATER(0x8));
851 } else if (((rdev->family) == CHIP_R600) ||
852 ((rdev->family) == CHIP_RV630)) {
853 tmp &= ~DONE_FIFO_HIWATER(0xff);
854 tmp |= DONE_FIFO_HIWATER(0x4);
855 }
856 WREG32(SQ_MS_FIFO_SIZES, tmp);
857
858 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
859 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
860 */
861 sq_config = RREG32(SQ_CONFIG);
862 sq_config &= ~(PS_PRIO(3) |
863 VS_PRIO(3) |
864 GS_PRIO(3) |
865 ES_PRIO(3));
866 sq_config |= (DX9_CONSTS |
867 VC_ENABLE |
868 PS_PRIO(0) |
869 VS_PRIO(1) |
870 GS_PRIO(2) |
871 ES_PRIO(3));
872
873 if ((rdev->family) == CHIP_R600) {
874 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
875 NUM_VS_GPRS(124) |
876 NUM_CLAUSE_TEMP_GPRS(4));
877 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
878 NUM_ES_GPRS(0));
879 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
880 NUM_VS_THREADS(48) |
881 NUM_GS_THREADS(4) |
882 NUM_ES_THREADS(4));
883 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
884 NUM_VS_STACK_ENTRIES(128));
885 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
886 NUM_ES_STACK_ENTRIES(0));
887 } else if (((rdev->family) == CHIP_RV610) ||
888 ((rdev->family) == CHIP_RV620) ||
889 ((rdev->family) == CHIP_RS780)) {
890 /* no vertex cache */
891 sq_config &= ~VC_ENABLE;
892
893 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
894 NUM_VS_GPRS(44) |
895 NUM_CLAUSE_TEMP_GPRS(2));
896 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
897 NUM_ES_GPRS(17));
898 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
899 NUM_VS_THREADS(78) |
900 NUM_GS_THREADS(4) |
901 NUM_ES_THREADS(31));
902 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
903 NUM_VS_STACK_ENTRIES(40));
904 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
905 NUM_ES_STACK_ENTRIES(16));
906 } else if (((rdev->family) == CHIP_RV630) ||
907 ((rdev->family) == CHIP_RV635)) {
908 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
909 NUM_VS_GPRS(44) |
910 NUM_CLAUSE_TEMP_GPRS(2));
911 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
912 NUM_ES_GPRS(18));
913 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
914 NUM_VS_THREADS(78) |
915 NUM_GS_THREADS(4) |
916 NUM_ES_THREADS(31));
917 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
918 NUM_VS_STACK_ENTRIES(40));
919 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
920 NUM_ES_STACK_ENTRIES(16));
921 } else if ((rdev->family) == CHIP_RV670) {
922 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
923 NUM_VS_GPRS(44) |
924 NUM_CLAUSE_TEMP_GPRS(2));
925 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
926 NUM_ES_GPRS(17));
927 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
928 NUM_VS_THREADS(78) |
929 NUM_GS_THREADS(4) |
930 NUM_ES_THREADS(31));
931 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
932 NUM_VS_STACK_ENTRIES(64));
933 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
934 NUM_ES_STACK_ENTRIES(64));
935 }
936
937 WREG32(SQ_CONFIG, sq_config);
938 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
939 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
940 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
941 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
942 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
943
944 if (((rdev->family) == CHIP_RV610) ||
945 ((rdev->family) == CHIP_RV620) ||
946 ((rdev->family) == CHIP_RS780)) {
947 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
948 } else {
949 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
950 }
951
952 /* More default values. 2D/3D driver should adjust as needed */
953 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
954 S1_X(0x4) | S1_Y(0xc)));
955 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
956 S1_X(0x2) | S1_Y(0x2) |
957 S2_X(0xa) | S2_Y(0x6) |
958 S3_X(0x6) | S3_Y(0xa)));
959 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
960 S1_X(0x4) | S1_Y(0xc) |
961 S2_X(0x1) | S2_Y(0x6) |
962 S3_X(0xa) | S3_Y(0xe)));
963 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
964 S5_X(0x0) | S5_Y(0x0) |
965 S6_X(0xb) | S6_Y(0x4) |
966 S7_X(0x7) | S7_Y(0x8)));
967
968 WREG32(VGT_STRMOUT_EN, 0);
969 tmp = rdev->config.r600.max_pipes * 16;
970 switch (rdev->family) {
971 case CHIP_RV610:
972 case CHIP_RS780:
973 case CHIP_RV620:
974 tmp += 32;
975 break;
976 case CHIP_RV670:
977 tmp += 128;
978 break;
979 default:
980 break;
981 }
982 if (tmp > 256) {
983 tmp = 256;
984 }
985 WREG32(VGT_ES_PER_GS, 128);
986 WREG32(VGT_GS_PER_ES, tmp);
987 WREG32(VGT_GS_PER_VS, 2);
988 WREG32(VGT_GS_VERTEX_REUSE, 16);
989
990 /* more default values. 2D/3D driver should adjust as needed */
991 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
992 WREG32(VGT_STRMOUT_EN, 0);
993 WREG32(SX_MISC, 0);
994 WREG32(PA_SC_MODE_CNTL, 0);
995 WREG32(PA_SC_AA_CONFIG, 0);
996 WREG32(PA_SC_LINE_STIPPLE, 0);
997 WREG32(SPI_INPUT_Z, 0);
998 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
999 WREG32(CB_COLOR7_FRAG, 0);
1000
1001 /* Clear render buffer base addresses */
1002 WREG32(CB_COLOR0_BASE, 0);
1003 WREG32(CB_COLOR1_BASE, 0);
1004 WREG32(CB_COLOR2_BASE, 0);
1005 WREG32(CB_COLOR3_BASE, 0);
1006 WREG32(CB_COLOR4_BASE, 0);
1007 WREG32(CB_COLOR5_BASE, 0);
1008 WREG32(CB_COLOR6_BASE, 0);
1009 WREG32(CB_COLOR7_BASE, 0);
1010 WREG32(CB_COLOR7_FRAG, 0);
1011
1012 switch (rdev->family) {
1013 case CHIP_RV610:
1014 case CHIP_RS780:
1015 case CHIP_RV620:
1016 tmp = TC_L2_SIZE(8);
1017 break;
1018 case CHIP_RV630:
1019 case CHIP_RV635:
1020 tmp = TC_L2_SIZE(4);
1021 break;
1022 case CHIP_R600:
1023 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1024 break;
1025 default:
1026 tmp = TC_L2_SIZE(0);
1027 break;
1028 }
1029 WREG32(TC_CNTL, tmp);
1030
1031 tmp = RREG32(HDP_HOST_PATH_CNTL);
1032 WREG32(HDP_HOST_PATH_CNTL, tmp);
1033
1034 tmp = RREG32(ARB_POP);
1035 tmp |= ENABLE_TC128;
1036 WREG32(ARB_POP, tmp);
1037
1038 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1039 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1040 NUM_CLIP_SEQ(3)));
1041 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1042}
1043
1044
771fe6b9
JG		 1045/*
1046 * Indirect registers accessor
1047 */
3ce0a23d
JG		 1048u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1049{
1050 u32 r;
1051
1052 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1053 (void)RREG32(PCIE_PORT_INDEX);
1054 r = RREG32(PCIE_PORT_DATA);
1055 return r;
1056}
1057
1058void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1059{
1060 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1061 (void)RREG32(PCIE_PORT_INDEX);
1062 WREG32(PCIE_PORT_DATA, (v));
1063 (void)RREG32(PCIE_PORT_DATA);
1064}
1065
1066
1067/*
1068 * CP & Ring
1069 */
1070void r600_cp_stop(struct radeon_device *rdev)
1071{
1072 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1073}
1074
1075int r600_cp_init_microcode(struct radeon_device *rdev)
1076{
1077 struct platform_device *pdev;
1078 const char *chip_name;
1079 size_t pfp_req_size, me_req_size;
1080 char fw_name[30];
1081 int err;
1082
1083 DRM_DEBUG("\n");
1084
1085 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1086 err = IS_ERR(pdev);
1087 if (err) {
1088 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1089 return -EINVAL;
1090 }
1091
1092 switch (rdev->family) {
1093 case CHIP_R600: chip_name = "R600"; break;
1094 case CHIP_RV610: chip_name = "RV610"; break;
1095 case CHIP_RV630: chip_name = "RV630"; break;
1096 case CHIP_RV620: chip_name = "RV620"; break;
1097 case CHIP_RV635: chip_name = "RV635"; break;
1098 case CHIP_RV670: chip_name = "RV670"; break;
1099 case CHIP_RS780:
1100 case CHIP_RS880: chip_name = "RS780"; break;
1101 case CHIP_RV770: chip_name = "RV770"; break;
1102 case CHIP_RV730:
1103 case CHIP_RV740: chip_name = "RV730"; break;
1104 case CHIP_RV710: chip_name = "RV710"; break;
1105 default: BUG();
1106 }
1107
1108 if (rdev->family >= CHIP_RV770) {
1109 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1110 me_req_size = R700_PM4_UCODE_SIZE * 4;
1111 } else {
1112 pfp_req_size = PFP_UCODE_SIZE * 4;
1113 me_req_size = PM4_UCODE_SIZE * 12;
1114 }
1115
1116 DRM_INFO("Loading %s CP Microcode\n", chip_name);
1117
1118 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1119 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1120 if (err)
1121 goto out;
1122 if (rdev->pfp_fw->size != pfp_req_size) {
1123 printk(KERN_ERR
1124 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1125 rdev->pfp_fw->size, fw_name);
1126 err = -EINVAL;
1127 goto out;
1128 }
1129
1130 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1131 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1132 if (err)
1133 goto out;
1134 if (rdev->me_fw->size != me_req_size) {
1135 printk(KERN_ERR
1136 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1137 rdev->me_fw->size, fw_name);
1138 err = -EINVAL;
1139 }
1140out:
1141 platform_device_unregister(pdev);
1142
1143 if (err) {
1144 if (err != -EINVAL)
1145 printk(KERN_ERR
1146 "r600_cp: Failed to load firmware \"%s\"\n",
1147 fw_name);
1148 release_firmware(rdev->pfp_fw);
1149 rdev->pfp_fw = NULL;
1150 release_firmware(rdev->me_fw);
1151 rdev->me_fw = NULL;
1152 }
1153 return err;
1154}
1155
1156static int r600_cp_load_microcode(struct radeon_device *rdev)
1157{
1158 const __be32 *fw_data;
1159 int i;
1160
1161 if (!rdev->me_fw || !rdev->pfp_fw)
1162 return -EINVAL;
1163
1164 r600_cp_stop(rdev);
1165
1166 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1167
1168 /* Reset cp */
1169 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1170 RREG32(GRBM_SOFT_RESET);
1171 mdelay(15);
1172 WREG32(GRBM_SOFT_RESET, 0);
1173
1174 WREG32(CP_ME_RAM_WADDR, 0);
1175
1176 fw_data = (const __be32 *)rdev->me_fw->data;
1177 WREG32(CP_ME_RAM_WADDR, 0);
1178 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1179 WREG32(CP_ME_RAM_DATA,
1180 be32_to_cpup(fw_data++));
1181
1182 fw_data = (const __be32 *)rdev->pfp_fw->data;
1183 WREG32(CP_PFP_UCODE_ADDR, 0);
1184 for (i = 0; i < PFP_UCODE_SIZE; i++)
1185 WREG32(CP_PFP_UCODE_DATA,
1186 be32_to_cpup(fw_data++));
1187
1188 WREG32(CP_PFP_UCODE_ADDR, 0);
1189 WREG32(CP_ME_RAM_WADDR, 0);
1190 WREG32(CP_ME_RAM_RADDR, 0);
1191 return 0;
1192}
1193
1194int r600_cp_start(struct radeon_device *rdev)
1195{
1196 int r;
1197 uint32_t cp_me;
1198
1199 r = radeon_ring_lock(rdev, 7);
1200 if (r) {
1201 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1202 return r;
1203 }
1204 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1205 radeon_ring_write(rdev, 0x1);
1206 if (rdev->family < CHIP_RV770) {
1207 radeon_ring_write(rdev, 0x3);
1208 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1209 } else {
1210 radeon_ring_write(rdev, 0x0);
1211 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1212 }
1213 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1214 radeon_ring_write(rdev, 0);
1215 radeon_ring_write(rdev, 0);
1216 radeon_ring_unlock_commit(rdev);
1217
1218 cp_me = 0xff;
1219 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1220 return 0;
1221}
1222
1223int r600_cp_resume(struct radeon_device *rdev)
1224{
1225 u32 tmp;
1226 u32 rb_bufsz;
1227 int r;
1228
1229 /* Reset cp */
1230 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1231 RREG32(GRBM_SOFT_RESET);
1232 mdelay(15);
1233 WREG32(GRBM_SOFT_RESET, 0);
1234
1235 /* Set ring buffer size */
1236 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1237#ifdef __BIG_ENDIAN
1238 WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
1239 (drm_order(4096/8) << 8) | rb_bufsz);
1240#else
1241 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
1242#endif
1243 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1244
1245 /* Set the write pointer delay */
1246 WREG32(CP_RB_WPTR_DELAY, 0);
1247
1248 /* Initialize the ring buffer's read and write pointers */
1249 tmp = RREG32(CP_RB_CNTL);
1250 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1251 WREG32(CP_RB_RPTR_WR, 0);
1252 WREG32(CP_RB_WPTR, 0);
1253 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1254 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1255 mdelay(1);
1256 WREG32(CP_RB_CNTL, tmp);
1257
1258 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1259 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1260
1261 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1262 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1263
1264 r600_cp_start(rdev);
1265 rdev->cp.ready = true;
1266 r = radeon_ring_test(rdev);
1267 if (r) {
1268 rdev->cp.ready = false;
1269 return r;
1270 }
1271 return 0;
1272}
1273
1274void r600_cp_commit(struct radeon_device *rdev)
1275{
1276 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1277 (void)RREG32(CP_RB_WPTR);
1278}
1279
1280void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1281{
1282 u32 rb_bufsz;
1283
1284 /* Align ring size */
1285 rb_bufsz = drm_order(ring_size / 8);
1286 ring_size = (1 << (rb_bufsz + 1)) * 4;
1287 rdev->cp.ring_size = ring_size;
1288 rdev->cp.align_mask = 16 - 1;
1289}
1290
1291
1292/*
1293 * GPU scratch registers helpers function.
1294 */
1295void r600_scratch_init(struct radeon_device *rdev)
1296{
1297 int i;
1298
1299 rdev->scratch.num_reg = 7;
1300 for (i = 0; i < rdev->scratch.num_reg; i++) {
1301 rdev->scratch.free[i] = true;
1302 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1303 }
1304}
1305
1306int r600_ring_test(struct radeon_device *rdev)
1307{
1308 uint32_t scratch;
1309 uint32_t tmp = 0;
1310 unsigned i;
1311 int r;
1312
1313 r = radeon_scratch_get(rdev, &scratch);
1314 if (r) {
1315 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1316 return r;
1317 }
1318 WREG32(scratch, 0xCAFEDEAD);
1319 r = radeon_ring_lock(rdev, 3);
1320 if (r) {
1321 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1322 radeon_scratch_free(rdev, scratch);
1323 return r;
1324 }
1325 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1326 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1327 radeon_ring_write(rdev, 0xDEADBEEF);
1328 radeon_ring_unlock_commit(rdev);
1329 for (i = 0; i < rdev->usec_timeout; i++) {
1330 tmp = RREG32(scratch);
1331 if (tmp == 0xDEADBEEF)
1332 break;
1333 DRM_UDELAY(1);
1334 }
1335 if (i < rdev->usec_timeout) {
1336 DRM_INFO("ring test succeeded in %d usecs\n", i);
1337 } else {
1338 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1339 scratch, tmp);
1340 r = -EINVAL;
1341 }
1342 radeon_scratch_free(rdev, scratch);
1343 return r;
1344}
1345
1346/*
1347 * Writeback
1348 */
1349int r600_wb_init(struct radeon_device *rdev)
1350{
1351 int r;
1352
1353 if (rdev->wb.wb_obj == NULL) {
1354 r = radeon_object_create(rdev, NULL, 4096,
1355 true,
1356 RADEON_GEM_DOMAIN_GTT,
1357 false, &rdev->wb.wb_obj);
1358 if (r) {
1359 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
1360 return r;
1361 }
1362 r = radeon_object_pin(rdev->wb.wb_obj,
1363 RADEON_GEM_DOMAIN_GTT,
1364 &rdev->wb.gpu_addr);
1365 if (r) {
1366 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
1367 return r;
1368 }
1369 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1370 if (r) {
1371 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
1372 return r;
1373 }
1374 }
1375 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1376 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1377 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1378 WREG32(SCRATCH_UMSK, 0xff);
1379 return 0;
1380}
1381
1382void r600_wb_fini(struct radeon_device *rdev)
1383{
1384 if (rdev->wb.wb_obj) {
1385 radeon_object_kunmap(rdev->wb.wb_obj);
1386 radeon_object_unpin(rdev->wb.wb_obj);
1387 radeon_object_unref(&rdev->wb.wb_obj);
1388 rdev->wb.wb = NULL;
1389 rdev->wb.wb_obj = NULL;
1390 }
1391}
1392
1393
1394/*
1395 * CS
1396 */
1397void r600_fence_ring_emit(struct radeon_device *rdev,
1398 struct radeon_fence *fence)
1399{
1400 /* Emit fence sequence & fire IRQ */
1401 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1402 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1403 radeon_ring_write(rdev, fence->seq);
1404}
1405
1406int r600_copy_dma(struct radeon_device *rdev,
1407 uint64_t src_offset,
1408 uint64_t dst_offset,
1409 unsigned num_pages,
1410 struct radeon_fence *fence)
1411{
1412 /* FIXME: implement */
1413 return 0;
1414}
1415
1416int r600_copy_blit(struct radeon_device *rdev,
1417 uint64_t src_offset, uint64_t dst_offset,
1418 unsigned num_pages, struct radeon_fence *fence)
1419{
1420 r600_blit_prepare_copy(rdev, num_pages * 4096);
1421 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
1422 r600_blit_done_copy(rdev, fence);
1423 return 0;
1424}
1425
1426int r600_irq_process(struct radeon_device *rdev)
1427{
1428 /* FIXME: implement */
1429 return 0;
1430}
1431
1432int r600_irq_set(struct radeon_device *rdev)
1433{
1434 /* FIXME: implement */
1435 return 0;
1436}
1437
1438int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1439 uint32_t tiling_flags, uint32_t pitch,
1440 uint32_t offset, uint32_t obj_size)
1441{
1442 /* FIXME: implement */
1443 return 0;
1444}
1445
1446void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1447{
1448 /* FIXME: implement */
1449}
1450
1451
1452bool r600_card_posted(struct radeon_device *rdev)
1453{
1454 uint32_t reg;
1455
1456 /* first check CRTCs */
1457 reg = RREG32(D1CRTC_CONTROL) |
1458 RREG32(D2CRTC_CONTROL);
1459 if (reg & CRTC_EN)
1460 return true;
1461
1462 /* then check MEM_SIZE, in case the crtcs are off */
1463 if (RREG32(CONFIG_MEMSIZE))
1464 return true;
1465
1466 return false;
1467}
1468
1469int r600_resume(struct radeon_device *rdev)
1470{
1471 int r;
1472
1473 r600_gpu_reset(rdev);
1474 r600_mc_resume(rdev);
1475 r = r600_pcie_gart_enable(rdev);
1476 if (r)
1477 return r;
1478 r600_gpu_init(rdev);
bc1a631e
DA		 1479
1480 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1481 &rdev->r600_blit.shader_gpu_addr);
1482 if (r) {
1483 DRM_ERROR("failed to pin blit object %d\n", r);
1484 return r;
1485 }
1486
3ce0a23d
JG		 1487 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1488 if (r)
1489 return r;
1490 r = r600_cp_load_microcode(rdev);
1491 if (r)
1492 return r;
1493 r = r600_cp_resume(rdev);
1494 if (r)
1495 return r;
1496 r = r600_wb_init(rdev);
1497 if (r)
1498 return r;
1499 return 0;
1500}
1501
1502int r600_suspend(struct radeon_device *rdev)
1503{
1504 /* FIXME: we should wait for ring to be empty */
1505 r600_cp_stop(rdev);
bc1a631e
DA		 1506 rdev->cp.ready = false;
1507
4aac0473 1508 r600_pcie_gart_disable(rdev);
bc1a631e
DA		 1509 /* unpin shaders bo */
1510 radeon_object_unpin(rdev->r600_blit.shader_obj);
3ce0a23d
JG		 1511 return 0;
1512}
1513
1514/* Plan is to move initialization in that function and use
1515 * helper function so that radeon_device_init pretty much
1516 * do nothing more than calling asic specific function. This
1517 * should also allow to remove a bunch of callback function
1518 * like vram_info.
1519 */
1520int r600_init(struct radeon_device *rdev)
771fe6b9 1521{
3ce0a23d 1522 int r;
771fe6b9 1523
3ce0a23d
JG		 1524 rdev->new_init_path = true;
1525 r = radeon_dummy_page_init(rdev);
1526 if (r)
1527 return r;
1528 if (r600_debugfs_mc_info_init(rdev)) {
1529 DRM_ERROR("Failed to register debugfs file for mc !\n");
1530 }
1531 /* This don't do much */
1532 r = radeon_gem_init(rdev);
1533 if (r)
1534 return r;
1535 /* Read BIOS */
1536 if (!radeon_get_bios(rdev)) {
1537 if (ASIC_IS_AVIVO(rdev))
1538 return -EINVAL;
1539 }
1540 /* Must be an ATOMBIOS */
1541 if (!rdev->is_atom_bios)
1542 return -EINVAL;
1543 r = radeon_atombios_init(rdev);
1544 if (r)
1545 return r;
1546 /* Post card if necessary */
1547 if (!r600_card_posted(rdev) && rdev->bios) {
1548 DRM_INFO("GPU not posted. posting now...\n");
1549 atom_asic_init(rdev->mode_info.atom_context);
1550 }
1551 /* Initialize scratch registers */
1552 r600_scratch_init(rdev);
1553 /* Initialize surface registers */
1554 radeon_surface_init(rdev);
5e6dde7e 1555 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1556 r = radeon_clocks_init(rdev);
1557 if (r)
1558 return r;
1559 /* Fence driver */
1560 r = radeon_fence_driver_init(rdev);
1561 if (r)
1562 return r;
1563 r = r600_mc_init(rdev);
1564 if (r) {
1565 if (rdev->flags & RADEON_IS_AGP) {
1566 /* Retry with disabling AGP */
1567 r600_fini(rdev);
1568 rdev->flags &= ~RADEON_IS_AGP;
1569 return r600_init(rdev);
1570 }
1571 return r;
1572 }
1573 /* Memory manager */
1574 r = radeon_object_init(rdev);
1575 if (r)
1576 return r;
1577 rdev->cp.ring_obj = NULL;
1578 r600_ring_init(rdev, 1024 * 1024);
1579
1580 if (!rdev->me_fw || !rdev->pfp_fw) {
1581 r = r600_cp_init_microcode(rdev);
1582 if (r) {
1583 DRM_ERROR("Failed to load firmware!\n");
1584 return r;
1585 }
1586 }
1587
4aac0473
JG		 1588 r = r600_pcie_gart_init(rdev);
1589 if (r)
1590 return r;
1591
733289c2 1592 rdev->accel_working = true;
bc1a631e
DA		 1593 r = r600_blit_init(rdev);
1594 if (r) {
1595 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1596 return r;
1597 }
1598
3ce0a23d
JG		 1599 r = r600_resume(rdev);
1600 if (r) {
1601 if (rdev->flags & RADEON_IS_AGP) {
1602 /* Retry with disabling AGP */
1603 r600_fini(rdev);
1604 rdev->flags &= ~RADEON_IS_AGP;
1605 return r600_init(rdev);
1606 }
733289c2 1607 rdev->accel_working = false;
3ce0a23d 1608 }
733289c2
JG		 1609 if (rdev->accel_working) {
1610 r = radeon_ib_pool_init(rdev);
1611 if (r) {
1612 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1613 rdev->accel_working = false;
1614 }
733289c2
JG		 1615 r = radeon_ib_test(rdev);
1616 if (r) {
1617 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1618 rdev->accel_working = false;
1619 }
3ce0a23d
JG		 1620 }
1621 return 0;
1622}
1623
1624void r600_fini(struct radeon_device *rdev)
1625{
1626 /* Suspend operations */
1627 r600_suspend(rdev);
1628
1629 r600_blit_fini(rdev);
1630 radeon_ring_fini(rdev);
4aac0473 1631 r600_pcie_gart_fini(rdev);
3ce0a23d
JG		 1632 radeon_gem_fini(rdev);
1633 radeon_fence_driver_fini(rdev);
1634 radeon_clocks_fini(rdev);
1635#if __OS_HAS_AGP
1636 if (rdev->flags & RADEON_IS_AGP)
1637 radeon_agp_fini(rdev);
1638#endif
1639 radeon_object_fini(rdev);
1640 if (rdev->is_atom_bios)
1641 radeon_atombios_fini(rdev);
1642 else
1643 radeon_combios_fini(rdev);
1644 kfree(rdev->bios);
1645 rdev->bios = NULL;
1646 radeon_dummy_page_fini(rdev);
1647}
1648
1649
1650/*
1651 * CS stuff
1652 */
1653void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1654{
1655 /* FIXME: implement */
1656 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1657 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1658 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1659 radeon_ring_write(rdev, ib->length_dw);
1660}
1661
1662int r600_ib_test(struct radeon_device *rdev)
1663{
1664 struct radeon_ib *ib;
1665 uint32_t scratch;
1666 uint32_t tmp = 0;
1667 unsigned i;
1668 int r;
1669
1670 r = radeon_scratch_get(rdev, &scratch);
1671 if (r) {
1672 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1673 return r;
1674 }
1675 WREG32(scratch, 0xCAFEDEAD);
1676 r = radeon_ib_get(rdev, &ib);
1677 if (r) {
1678 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1679 return r;
1680 }
1681 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1682 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1683 ib->ptr[2] = 0xDEADBEEF;
1684 ib->ptr[3] = PACKET2(0);
1685 ib->ptr[4] = PACKET2(0);
1686 ib->ptr[5] = PACKET2(0);
1687 ib->ptr[6] = PACKET2(0);
1688 ib->ptr[7] = PACKET2(0);
1689 ib->ptr[8] = PACKET2(0);
1690 ib->ptr[9] = PACKET2(0);
1691 ib->ptr[10] = PACKET2(0);
1692 ib->ptr[11] = PACKET2(0);
1693 ib->ptr[12] = PACKET2(0);
1694 ib->ptr[13] = PACKET2(0);
1695 ib->ptr[14] = PACKET2(0);
1696 ib->ptr[15] = PACKET2(0);
1697 ib->length_dw = 16;
1698 r = radeon_ib_schedule(rdev, ib);
1699 if (r) {
1700 radeon_scratch_free(rdev, scratch);
1701 radeon_ib_free(rdev, &ib);
1702 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1703 return r;
1704 }
1705 r = radeon_fence_wait(ib->fence, false);
1706 if (r) {
1707 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1708 return r;
1709 }
1710 for (i = 0; i < rdev->usec_timeout; i++) {
1711 tmp = RREG32(scratch);
1712 if (tmp == 0xDEADBEEF)
1713 break;
1714 DRM_UDELAY(1);
1715 }
1716 if (i < rdev->usec_timeout) {
1717 DRM_INFO("ib test succeeded in %u usecs\n", i);
1718 } else {
1719 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1720 scratch, tmp);
1721 r = -EINVAL;
1722 }
1723 radeon_scratch_free(rdev, scratch);
1724 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 1725 return r;
1726}
1727
3ce0a23d
JG		 1728
1729
1730
1731/*
1732 * Debugfs info
1733 */
1734#if defined(CONFIG_DEBUG_FS)
1735
1736static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 1737{
3ce0a23d
JG		 1738 struct drm_info_node *node = (struct drm_info_node *) m->private;
1739 struct drm_device *dev = node->minor->dev;
1740 struct radeon_device *rdev = dev->dev_private;
1741 uint32_t rdp, wdp;
1742 unsigned count, i, j;
1743
1744 radeon_ring_free_size(rdev);
1745 rdp = RREG32(CP_RB_RPTR);
1746 wdp = RREG32(CP_RB_WPTR);
1747 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1748 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1749 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1750 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1751 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1752 seq_printf(m, "%u dwords in ring\n", count);
1753 for (j = 0; j <= count; j++) {
1754 i = (rdp + j) & rdev->cp.ptr_mask;
1755 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1756 }
1757 return 0;
1758}
1759
1760static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1761{
1762 struct drm_info_node *node = (struct drm_info_node *) m->private;
1763 struct drm_device *dev = node->minor->dev;
1764 struct radeon_device *rdev = dev->dev_private;
1765
1766 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1767 DREG32_SYS(m, rdev, VM_L2_STATUS);
1768 return 0;
1769}
1770
1771static struct drm_info_list r600_mc_info_list[] = {
1772 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1773 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1774};
1775#endif
1776
1777int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1778{
1779#if defined(CONFIG_DEBUG_FS)
1780 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1781#else
1782 return 0;
1783#endif
771fe6b9 1784}
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