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drm/radeon/kms/evergreen: implement irq support
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/seq_file.h>
29#include <linux/firmware.h>
30#include <linux/platform_device.h>
771fe6b9 31#include "drmP.h"
3ce0a23d 32#include "radeon_drm.h"
771fe6b9 33#include "radeon.h"
e6990375 34#include "radeon_asic.h"
3ce0a23d 35#include "radeon_mode.h"
3ce0a23d 36#include "r600d.h"
3ce0a23d 37#include "atom.h"
d39c3b89 38#include "avivod.h"
771fe6b9 39
3ce0a23d
JG		 40#define PFP_UCODE_SIZE 576
41#define PM4_UCODE_SIZE 1792
d8f60cfc 42#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 43#define R700_PFP_UCODE_SIZE 848
44#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 45#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 46#define EVERGREEN_PFP_UCODE_SIZE 1120
47#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 48#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 49
50/* Firmware Names */
51MODULE_FIRMWARE("radeon/R600_pfp.bin");
52MODULE_FIRMWARE("radeon/R600_me.bin");
53MODULE_FIRMWARE("radeon/RV610_pfp.bin");
54MODULE_FIRMWARE("radeon/RV610_me.bin");
55MODULE_FIRMWARE("radeon/RV630_pfp.bin");
56MODULE_FIRMWARE("radeon/RV630_me.bin");
57MODULE_FIRMWARE("radeon/RV620_pfp.bin");
58MODULE_FIRMWARE("radeon/RV620_me.bin");
59MODULE_FIRMWARE("radeon/RV635_pfp.bin");
60MODULE_FIRMWARE("radeon/RV635_me.bin");
61MODULE_FIRMWARE("radeon/RV670_pfp.bin");
62MODULE_FIRMWARE("radeon/RV670_me.bin");
63MODULE_FIRMWARE("radeon/RS780_pfp.bin");
64MODULE_FIRMWARE("radeon/RS780_me.bin");
65MODULE_FIRMWARE("radeon/RV770_pfp.bin");
66MODULE_FIRMWARE("radeon/RV770_me.bin");
67MODULE_FIRMWARE("radeon/RV730_pfp.bin");
68MODULE_FIRMWARE("radeon/RV730_me.bin");
69MODULE_FIRMWARE("radeon/RV710_pfp.bin");
70MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 71MODULE_FIRMWARE("radeon/R600_rlc.bin");
72MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 73MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
74MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 75MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 76MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
77MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 78MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 79MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
80MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 81MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
fe251e2f
AD		 82MODULE_FIRMWARE("radeon/CYRPESS_pfp.bin");
83MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 84MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
3ce0a23d
JG		 85
86int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 87
1a029b76 88/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 89int r600_mc_wait_for_idle(struct radeon_device *rdev);
90void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 91void r600_fini(struct radeon_device *rdev);
45f9a39b 92void r600_irq_disable(struct radeon_device *rdev);
771fe6b9 93
e0df1ac5
AD		 94/* hpd for digital panel detect/disconnect */
95bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
96{
97 bool connected = false;
98
99 if (ASIC_IS_DCE3(rdev)) {
100 switch (hpd) {
101 case RADEON_HPD_1:
102 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
103 connected = true;
104 break;
105 case RADEON_HPD_2:
106 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
107 connected = true;
108 break;
109 case RADEON_HPD_3:
110 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
111 connected = true;
112 break;
113 case RADEON_HPD_4:
114 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
115 connected = true;
116 break;
117 /* DCE 3.2 */
118 case RADEON_HPD_5:
119 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
120 connected = true;
121 break;
122 case RADEON_HPD_6:
123 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
124 connected = true;
125 break;
126 default:
127 break;
128 }
129 } else {
130 switch (hpd) {
131 case RADEON_HPD_1:
132 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
133 connected = true;
134 break;
135 case RADEON_HPD_2:
136 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
137 connected = true;
138 break;
139 case RADEON_HPD_3:
140 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
141 connected = true;
142 break;
143 default:
144 break;
145 }
146 }
147 return connected;
148}
149
150void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 151 enum radeon_hpd_id hpd)
e0df1ac5
AD		 152{
153 u32 tmp;
154 bool connected = r600_hpd_sense(rdev, hpd);
155
156 if (ASIC_IS_DCE3(rdev)) {
157 switch (hpd) {
158 case RADEON_HPD_1:
159 tmp = RREG32(DC_HPD1_INT_CONTROL);
160 if (connected)
161 tmp &= ~DC_HPDx_INT_POLARITY;
162 else
163 tmp |= DC_HPDx_INT_POLARITY;
164 WREG32(DC_HPD1_INT_CONTROL, tmp);
165 break;
166 case RADEON_HPD_2:
167 tmp = RREG32(DC_HPD2_INT_CONTROL);
168 if (connected)
169 tmp &= ~DC_HPDx_INT_POLARITY;
170 else
171 tmp |= DC_HPDx_INT_POLARITY;
172 WREG32(DC_HPD2_INT_CONTROL, tmp);
173 break;
174 case RADEON_HPD_3:
175 tmp = RREG32(DC_HPD3_INT_CONTROL);
176 if (connected)
177 tmp &= ~DC_HPDx_INT_POLARITY;
178 else
179 tmp |= DC_HPDx_INT_POLARITY;
180 WREG32(DC_HPD3_INT_CONTROL, tmp);
181 break;
182 case RADEON_HPD_4:
183 tmp = RREG32(DC_HPD4_INT_CONTROL);
184 if (connected)
185 tmp &= ~DC_HPDx_INT_POLARITY;
186 else
187 tmp |= DC_HPDx_INT_POLARITY;
188 WREG32(DC_HPD4_INT_CONTROL, tmp);
189 break;
190 case RADEON_HPD_5:
191 tmp = RREG32(DC_HPD5_INT_CONTROL);
192 if (connected)
193 tmp &= ~DC_HPDx_INT_POLARITY;
194 else
195 tmp |= DC_HPDx_INT_POLARITY;
196 WREG32(DC_HPD5_INT_CONTROL, tmp);
197 break;
198 /* DCE 3.2 */
199 case RADEON_HPD_6:
200 tmp = RREG32(DC_HPD6_INT_CONTROL);
201 if (connected)
202 tmp &= ~DC_HPDx_INT_POLARITY;
203 else
204 tmp |= DC_HPDx_INT_POLARITY;
205 WREG32(DC_HPD6_INT_CONTROL, tmp);
206 break;
207 default:
208 break;
209 }
210 } else {
211 switch (hpd) {
212 case RADEON_HPD_1:
213 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
214 if (connected)
215 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
216 else
217 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
218 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
219 break;
220 case RADEON_HPD_2:
221 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
222 if (connected)
223 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
224 else
225 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
226 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
227 break;
228 case RADEON_HPD_3:
229 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
230 if (connected)
231 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
232 else
233 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
234 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
235 break;
236 default:
237 break;
238 }
239 }
240}
241
242void r600_hpd_init(struct radeon_device *rdev)
243{
244 struct drm_device *dev = rdev->ddev;
245 struct drm_connector *connector;
246
247 if (ASIC_IS_DCE3(rdev)) {
248 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
249 if (ASIC_IS_DCE32(rdev))
250 tmp |= DC_HPDx_EN;
251
252 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
253 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
254 switch (radeon_connector->hpd.hpd) {
255 case RADEON_HPD_1:
256 WREG32(DC_HPD1_CONTROL, tmp);
257 rdev->irq.hpd[0] = true;
258 break;
259 case RADEON_HPD_2:
260 WREG32(DC_HPD2_CONTROL, tmp);
261 rdev->irq.hpd[1] = true;
262 break;
263 case RADEON_HPD_3:
264 WREG32(DC_HPD3_CONTROL, tmp);
265 rdev->irq.hpd[2] = true;
266 break;
267 case RADEON_HPD_4:
268 WREG32(DC_HPD4_CONTROL, tmp);
269 rdev->irq.hpd[3] = true;
270 break;
271 /* DCE 3.2 */
272 case RADEON_HPD_5:
273 WREG32(DC_HPD5_CONTROL, tmp);
274 rdev->irq.hpd[4] = true;
275 break;
276 case RADEON_HPD_6:
277 WREG32(DC_HPD6_CONTROL, tmp);
278 rdev->irq.hpd[5] = true;
279 break;
280 default:
281 break;
282 }
283 }
284 } else {
285 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
286 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
287 switch (radeon_connector->hpd.hpd) {
288 case RADEON_HPD_1:
289 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
290 rdev->irq.hpd[0] = true;
291 break;
292 case RADEON_HPD_2:
293 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
294 rdev->irq.hpd[1] = true;
295 break;
296 case RADEON_HPD_3:
297 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
298 rdev->irq.hpd[2] = true;
299 break;
300 default:
301 break;
302 }
303 }
304 }
003e69f9
JG		 305 if (rdev->irq.installed)
306 r600_irq_set(rdev);
e0df1ac5
AD		 307}
308
309void r600_hpd_fini(struct radeon_device *rdev)
310{
311 struct drm_device *dev = rdev->ddev;
312 struct drm_connector *connector;
313
314 if (ASIC_IS_DCE3(rdev)) {
315 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
316 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
317 switch (radeon_connector->hpd.hpd) {
318 case RADEON_HPD_1:
319 WREG32(DC_HPD1_CONTROL, 0);
320 rdev->irq.hpd[0] = false;
321 break;
322 case RADEON_HPD_2:
323 WREG32(DC_HPD2_CONTROL, 0);
324 rdev->irq.hpd[1] = false;
325 break;
326 case RADEON_HPD_3:
327 WREG32(DC_HPD3_CONTROL, 0);
328 rdev->irq.hpd[2] = false;
329 break;
330 case RADEON_HPD_4:
331 WREG32(DC_HPD4_CONTROL, 0);
332 rdev->irq.hpd[3] = false;
333 break;
334 /* DCE 3.2 */
335 case RADEON_HPD_5:
336 WREG32(DC_HPD5_CONTROL, 0);
337 rdev->irq.hpd[4] = false;
338 break;
339 case RADEON_HPD_6:
340 WREG32(DC_HPD6_CONTROL, 0);
341 rdev->irq.hpd[5] = false;
342 break;
343 default:
344 break;
345 }
346 }
347 } else {
348 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
349 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
350 switch (radeon_connector->hpd.hpd) {
351 case RADEON_HPD_1:
352 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
353 rdev->irq.hpd[0] = false;
354 break;
355 case RADEON_HPD_2:
356 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
357 rdev->irq.hpd[1] = false;
358 break;
359 case RADEON_HPD_3:
360 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
361 rdev->irq.hpd[2] = false;
362 break;
363 default:
364 break;
365 }
366 }
367 }
368}
369
771fe6b9 370/*
3ce0a23d 371 * R600 PCIE GART
771fe6b9 372 */
3ce0a23d
JG		 373void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
374{
375 unsigned i;
376 u32 tmp;
377
2e98f10a
DA		 378 /* flush hdp cache so updates hit vram */
379 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
380
3ce0a23d
JG		 381 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
382 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
383 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
384 for (i = 0; i < rdev->usec_timeout; i++) {
385 /* read MC_STATUS */
386 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
387 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
388 if (tmp == 2) {
389 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
390 return;
391 }
392 if (tmp) {
393 return;
394 }
395 udelay(1);
396 }
397}
398
4aac0473 399int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 400{
4aac0473 401 int r;
3ce0a23d 402
4aac0473
JG		 403 if (rdev->gart.table.vram.robj) {
404 WARN(1, "R600 PCIE GART already initialized.\n");
405 return 0;
406 }
3ce0a23d
JG		 407 /* Initialize common gart structure */
408 r = radeon_gart_init(rdev);
4aac0473 409 if (r)
3ce0a23d 410 return r;
3ce0a23d 411 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 412 return radeon_gart_table_vram_alloc(rdev);
413}
414
415int r600_pcie_gart_enable(struct radeon_device *rdev)
416{
417 u32 tmp;
418 int r, i;
419
420 if (rdev->gart.table.vram.robj == NULL) {
421 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
422 return -EINVAL;
771fe6b9 423 }
4aac0473
JG		 424 r = radeon_gart_table_vram_pin(rdev);
425 if (r)
426 return r;
82568565 427 radeon_gart_restore(rdev);
bc1a631e 428
3ce0a23d
JG		 429 /* Setup L2 cache */
430 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
431 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
432 EFFECTIVE_L2_QUEUE_SIZE(7));
433 WREG32(VM_L2_CNTL2, 0);
434 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
435 /* Setup TLB control */
436 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
437 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
438 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
439 ENABLE_WAIT_L2_QUERY;
440 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
441 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
442 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
443 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
444 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
445 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
446 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
447 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
448 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
449 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
450 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
451 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
452 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
453 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
454 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 455 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 456 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
457 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
458 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
459 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
460 (u32)(rdev->dummy_page.addr >> 12));
461 for (i = 1; i < 7; i++)
462 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 463
3ce0a23d
JG		 464 r600_pcie_gart_tlb_flush(rdev);
465 rdev->gart.ready = true;
771fe6b9
JG		 466 return 0;
467}
468
3ce0a23d 469void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 470{
3ce0a23d 471 u32 tmp;
4c788679 472 int i, r;
771fe6b9 473
3ce0a23d
JG		 474 /* Disable all tables */
475 for (i = 0; i < 7; i++)
476 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 477
3ce0a23d
JG		 478 /* Disable L2 cache */
479 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
480 EFFECTIVE_L2_QUEUE_SIZE(7));
481 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
482 /* Setup L1 TLB control */
483 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
484 ENABLE_WAIT_L2_QUERY;
485 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
486 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
487 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
488 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
489 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
490 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
491 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
492 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
493 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
494 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
495 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
496 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
497 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
498 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 499 if (rdev->gart.table.vram.robj) {
4c788679
JG		 500 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
501 if (likely(r == 0)) {
502 radeon_bo_kunmap(rdev->gart.table.vram.robj);
503 radeon_bo_unpin(rdev->gart.table.vram.robj);
504 radeon_bo_unreserve(rdev->gart.table.vram.robj);
505 }
4aac0473
JG		 506 }
507}
508
509void r600_pcie_gart_fini(struct radeon_device *rdev)
510{
f9274562 511 radeon_gart_fini(rdev);
4aac0473
JG		 512 r600_pcie_gart_disable(rdev);
513 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 514}
515
1a029b76
JG		 516void r600_agp_enable(struct radeon_device *rdev)
517{
518 u32 tmp;
519 int i;
520
521 /* Setup L2 cache */
522 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
523 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
524 EFFECTIVE_L2_QUEUE_SIZE(7));
525 WREG32(VM_L2_CNTL2, 0);
526 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
527 /* Setup TLB control */
528 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
529 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
530 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
531 ENABLE_WAIT_L2_QUERY;
532 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
533 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
534 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
535 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
536 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
537 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
538 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
539 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
540 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
541 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
542 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
543 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
544 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
545 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
546 for (i = 0; i < 7; i++)
547 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
548}
549
771fe6b9
JG		 550int r600_mc_wait_for_idle(struct radeon_device *rdev)
551{
3ce0a23d
JG		 552 unsigned i;
553 u32 tmp;
554
555 for (i = 0; i < rdev->usec_timeout; i++) {
556 /* read MC_STATUS */
557 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
558 if (!tmp)
559 return 0;
560 udelay(1);
561 }
562 return -1;
771fe6b9
JG		 563}
564
a3c1945a 565static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 566{
a3c1945a 567 struct rv515_mc_save save;
3ce0a23d
JG		 568 u32 tmp;
569 int i, j;
771fe6b9 570
3ce0a23d
JG		 571 /* Initialize HDP */
572 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
573 WREG32((0x2c14 + j), 0x00000000);
574 WREG32((0x2c18 + j), 0x00000000);
575 WREG32((0x2c1c + j), 0x00000000);
576 WREG32((0x2c20 + j), 0x00000000);
577 WREG32((0x2c24 + j), 0x00000000);
578 }
579 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 580
a3c1945a 581 rv515_mc_stop(rdev, &save);
3ce0a23d 582 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 583 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 584 }
a3c1945a 585 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 586 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 587 /* Update configuration */
1a029b76
JG		 588 if (rdev->flags & RADEON_IS_AGP) {
589 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
590 /* VRAM before AGP */
591 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
592 rdev->mc.vram_start >> 12);
593 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
594 rdev->mc.gtt_end >> 12);
595 } else {
596 /* VRAM after AGP */
597 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
598 rdev->mc.gtt_start >> 12);
599 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
600 rdev->mc.vram_end >> 12);
601 }
602 } else {
603 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
604 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
605 }
3ce0a23d 606 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 607 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 608 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
609 WREG32(MC_VM_FB_LOCATION, tmp);
610 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
611 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1a029b76 612 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
3ce0a23d 613 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 614 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
615 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 616 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
617 } else {
618 WREG32(MC_VM_AGP_BASE, 0);
619 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
620 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
621 }
3ce0a23d 622 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 623 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 624 }
a3c1945a 625 rv515_mc_resume(rdev, &save);
698443d9
DA		 626 /* we need to own VRAM, so turn off the VGA renderer here
627 * to stop it overwriting our objects */
d39c3b89 628 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 629}
630
d594e46a
JG		 631/**
632 * r600_vram_gtt_location - try to find VRAM & GTT location
633 * @rdev: radeon device structure holding all necessary informations
634 * @mc: memory controller structure holding memory informations
635 *
636 * Function will place try to place VRAM at same place as in CPU (PCI)
637 * address space as some GPU seems to have issue when we reprogram at
638 * different address space.
639 *
640 * If there is not enough space to fit the unvisible VRAM after the
641 * aperture then we limit the VRAM size to the aperture.
642 *
643 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
644 * them to be in one from GPU point of view so that we can program GPU to
645 * catch access outside them (weird GPU policy see ??).
646 *
647 * This function will never fails, worst case are limiting VRAM or GTT.
648 *
649 * Note: GTT start, end, size should be initialized before calling this
650 * function on AGP platform.
651 */
652void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
653{
654 u64 size_bf, size_af;
655
656 if (mc->mc_vram_size > 0xE0000000) {
657 /* leave room for at least 512M GTT */
658 dev_warn(rdev->dev, "limiting VRAM\n");
659 mc->real_vram_size = 0xE0000000;
660 mc->mc_vram_size = 0xE0000000;
661 }
662 if (rdev->flags & RADEON_IS_AGP) {
663 size_bf = mc->gtt_start;
664 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
665 if (size_bf > size_af) {
666 if (mc->mc_vram_size > size_bf) {
667 dev_warn(rdev->dev, "limiting VRAM\n");
668 mc->real_vram_size = size_bf;
669 mc->mc_vram_size = size_bf;
670 }
671 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
672 } else {
673 if (mc->mc_vram_size > size_af) {
674 dev_warn(rdev->dev, "limiting VRAM\n");
675 mc->real_vram_size = size_af;
676 mc->mc_vram_size = size_af;
677 }
678 mc->vram_start = mc->gtt_end;
679 }
680 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
681 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
682 mc->mc_vram_size >> 20, mc->vram_start,
683 mc->vram_end, mc->real_vram_size >> 20);
684 } else {
685 u64 base = 0;
686 if (rdev->flags & RADEON_IS_IGP)
687 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
688 radeon_vram_location(rdev, &rdev->mc, base);
689 radeon_gtt_location(rdev, mc);
690 }
691}
692
3ce0a23d 693int r600_mc_init(struct radeon_device *rdev)
771fe6b9 694{
3ce0a23d 695 u32 tmp;
5885b7a9 696 int chansize, numchan;
771fe6b9 697
3ce0a23d 698 /* Get VRAM informations */
771fe6b9 699 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 700 tmp = RREG32(RAMCFG);
701 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 702 chansize = 16;
3ce0a23d 703 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 704 chansize = 64;
705 } else {
706 chansize = 32;
707 }
5885b7a9
AD		 708 tmp = RREG32(CHMAP);
709 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
710 case 0:
711 default:
712 numchan = 1;
713 break;
714 case 1:
715 numchan = 2;
716 break;
717 case 2:
718 numchan = 4;
719 break;
720 case 3:
721 numchan = 8;
722 break;
771fe6b9 723 }
5885b7a9 724 rdev->mc.vram_width = numchan * chansize;
3ce0a23d
JG		 725 /* Could aper size report 0 ? */
726 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
727 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
728 /* Setup GPU memory space */
729 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
730 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 731 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 732 /* FIXME remove this once we support unmappable VRAM */
733 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
974b16e3 734 rdev->mc.mc_vram_size = rdev->mc.aper_size;
974b16e3 735 rdev->mc.real_vram_size = rdev->mc.aper_size;
3ce0a23d 736 }
d594e46a 737 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 738
06b6476d
AD		 739 if (rdev->flags & RADEON_IS_IGP)
740 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f47299c5 741 radeon_update_bandwidth_info(rdev);
3ce0a23d 742 return 0;
771fe6b9
JG		 743}
744
3ce0a23d
JG		 745/* We doesn't check that the GPU really needs a reset we simply do the
746 * reset, it's up to the caller to determine if the GPU needs one. We
747 * might add an helper function to check that.
748 */
749int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 750{
a3c1945a 751 struct rv515_mc_save save;
3ce0a23d
JG		 752 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
753 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
754 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
755 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
756 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
757 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
758 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
759 S_008010_GUI_ACTIVE(1);
760 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
761 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
762 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
763 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
764 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
765 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
766 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
767 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 768 u32 tmp;
771fe6b9 769
1a029b76
JG		 770 dev_info(rdev->dev, "GPU softreset \n");
771 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
772 RREG32(R_008010_GRBM_STATUS));
773 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 774 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 775 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
776 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 777 rv515_mc_stop(rdev, &save);
778 if (r600_mc_wait_for_idle(rdev)) {
779 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
780 }
3ce0a23d 781 /* Disable CP parsing/prefetching */
90aca4d2 782 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 783 /* Check if any of the rendering block is busy and reset it */
784 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
785 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 786 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 787 S_008020_SOFT_RESET_DB(1) |
788 S_008020_SOFT_RESET_CB(1) |
789 S_008020_SOFT_RESET_PA(1) |
790 S_008020_SOFT_RESET_SC(1) |
791 S_008020_SOFT_RESET_SMX(1) |
792 S_008020_SOFT_RESET_SPI(1) |
793 S_008020_SOFT_RESET_SX(1) |
794 S_008020_SOFT_RESET_SH(1) |
795 S_008020_SOFT_RESET_TC(1) |
796 S_008020_SOFT_RESET_TA(1) |
797 S_008020_SOFT_RESET_VC(1) |
a3c1945a 798 S_008020_SOFT_RESET_VGT(1);
1a029b76 799 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 800 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 801 RREG32(R_008020_GRBM_SOFT_RESET);
802 mdelay(15);
3ce0a23d 803 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 804 }
805 /* Reset CP (we always reset CP) */
a3c1945a
JG		 806 tmp = S_008020_SOFT_RESET_CP(1);
807 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
808 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 809 RREG32(R_008020_GRBM_SOFT_RESET);
810 mdelay(15);
3ce0a23d 811 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 812 /* Wait a little for things to settle down */
225758d8 813 mdelay(1);
1a029b76
JG		 814 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
815 RREG32(R_008010_GRBM_STATUS));
816 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
817 RREG32(R_008014_GRBM_STATUS2));
818 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
819 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 820 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 821 return 0;
822}
823
225758d8
JG		 824bool r600_gpu_is_lockup(struct radeon_device *rdev)
825{
826 u32 srbm_status;
827 u32 grbm_status;
828 u32 grbm_status2;
829 int r;
830
831 srbm_status = RREG32(R_000E50_SRBM_STATUS);
832 grbm_status = RREG32(R_008010_GRBM_STATUS);
833 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
834 if (!G_008010_GUI_ACTIVE(grbm_status)) {
835 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
836 return false;
837 }
838 /* force CP activities */
839 r = radeon_ring_lock(rdev, 2);
840 if (!r) {
841 /* PACKET2 NOP */
842 radeon_ring_write(rdev, 0x80000000);
843 radeon_ring_write(rdev, 0x80000000);
844 radeon_ring_unlock_commit(rdev);
845 }
846 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
847 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
848}
849
a2d07b74 850int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 851{
852 return r600_gpu_soft_reset(rdev);
853}
854
855static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
856 u32 num_backends,
857 u32 backend_disable_mask)
858{
859 u32 backend_map = 0;
860 u32 enabled_backends_mask;
861 u32 enabled_backends_count;
862 u32 cur_pipe;
863 u32 swizzle_pipe[R6XX_MAX_PIPES];
864 u32 cur_backend;
865 u32 i;
866
867 if (num_tile_pipes > R6XX_MAX_PIPES)
868 num_tile_pipes = R6XX_MAX_PIPES;
869 if (num_tile_pipes < 1)
870 num_tile_pipes = 1;
871 if (num_backends > R6XX_MAX_BACKENDS)
872 num_backends = R6XX_MAX_BACKENDS;
873 if (num_backends < 1)
874 num_backends = 1;
875
876 enabled_backends_mask = 0;
877 enabled_backends_count = 0;
878 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
879 if (((backend_disable_mask >> i) & 1) == 0) {
880 enabled_backends_mask |= (1 << i);
881 ++enabled_backends_count;
882 }
883 if (enabled_backends_count == num_backends)
884 break;
885 }
886
887 if (enabled_backends_count == 0) {
888 enabled_backends_mask = 1;
889 enabled_backends_count = 1;
890 }
891
892 if (enabled_backends_count != num_backends)
893 num_backends = enabled_backends_count;
894
895 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
896 switch (num_tile_pipes) {
897 case 1:
898 swizzle_pipe[0] = 0;
899 break;
900 case 2:
901 swizzle_pipe[0] = 0;
902 swizzle_pipe[1] = 1;
903 break;
904 case 3:
905 swizzle_pipe[0] = 0;
906 swizzle_pipe[1] = 1;
907 swizzle_pipe[2] = 2;
908 break;
909 case 4:
910 swizzle_pipe[0] = 0;
911 swizzle_pipe[1] = 1;
912 swizzle_pipe[2] = 2;
913 swizzle_pipe[3] = 3;
914 break;
915 case 5:
916 swizzle_pipe[0] = 0;
917 swizzle_pipe[1] = 1;
918 swizzle_pipe[2] = 2;
919 swizzle_pipe[3] = 3;
920 swizzle_pipe[4] = 4;
921 break;
922 case 6:
923 swizzle_pipe[0] = 0;
924 swizzle_pipe[1] = 2;
925 swizzle_pipe[2] = 4;
926 swizzle_pipe[3] = 5;
927 swizzle_pipe[4] = 1;
928 swizzle_pipe[5] = 3;
929 break;
930 case 7:
931 swizzle_pipe[0] = 0;
932 swizzle_pipe[1] = 2;
933 swizzle_pipe[2] = 4;
934 swizzle_pipe[3] = 6;
935 swizzle_pipe[4] = 1;
936 swizzle_pipe[5] = 3;
937 swizzle_pipe[6] = 5;
938 break;
939 case 8:
940 swizzle_pipe[0] = 0;
941 swizzle_pipe[1] = 2;
942 swizzle_pipe[2] = 4;
943 swizzle_pipe[3] = 6;
944 swizzle_pipe[4] = 1;
945 swizzle_pipe[5] = 3;
946 swizzle_pipe[6] = 5;
947 swizzle_pipe[7] = 7;
948 break;
949 }
950
951 cur_backend = 0;
952 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
953 while (((1 << cur_backend) & enabled_backends_mask) == 0)
954 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
955
956 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
957
958 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
959 }
960
961 return backend_map;
962}
963
964int r600_count_pipe_bits(uint32_t val)
965{
966 int i, ret = 0;
967
968 for (i = 0; i < 32; i++) {
969 ret += val & 1;
970 val >>= 1;
971 }
972 return ret;
771fe6b9
JG		 973}
974
3ce0a23d
JG		 975void r600_gpu_init(struct radeon_device *rdev)
976{
977 u32 tiling_config;
978 u32 ramcfg;
d03f5d59
AD		 979 u32 backend_map;
980 u32 cc_rb_backend_disable;
981 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 982 u32 tmp;
983 int i, j;
984 u32 sq_config;
985 u32 sq_gpr_resource_mgmt_1 = 0;
986 u32 sq_gpr_resource_mgmt_2 = 0;
987 u32 sq_thread_resource_mgmt = 0;
988 u32 sq_stack_resource_mgmt_1 = 0;
989 u32 sq_stack_resource_mgmt_2 = 0;
990
991 /* FIXME: implement */
992 switch (rdev->family) {
993 case CHIP_R600:
994 rdev->config.r600.max_pipes = 4;
995 rdev->config.r600.max_tile_pipes = 8;
996 rdev->config.r600.max_simds = 4;
997 rdev->config.r600.max_backends = 4;
998 rdev->config.r600.max_gprs = 256;
999 rdev->config.r600.max_threads = 192;
1000 rdev->config.r600.max_stack_entries = 256;
1001 rdev->config.r600.max_hw_contexts = 8;
1002 rdev->config.r600.max_gs_threads = 16;
1003 rdev->config.r600.sx_max_export_size = 128;
1004 rdev->config.r600.sx_max_export_pos_size = 16;
1005 rdev->config.r600.sx_max_export_smx_size = 128;
1006 rdev->config.r600.sq_num_cf_insts = 2;
1007 break;
1008 case CHIP_RV630:
1009 case CHIP_RV635:
1010 rdev->config.r600.max_pipes = 2;
1011 rdev->config.r600.max_tile_pipes = 2;
1012 rdev->config.r600.max_simds = 3;
1013 rdev->config.r600.max_backends = 1;
1014 rdev->config.r600.max_gprs = 128;
1015 rdev->config.r600.max_threads = 192;
1016 rdev->config.r600.max_stack_entries = 128;
1017 rdev->config.r600.max_hw_contexts = 8;
1018 rdev->config.r600.max_gs_threads = 4;
1019 rdev->config.r600.sx_max_export_size = 128;
1020 rdev->config.r600.sx_max_export_pos_size = 16;
1021 rdev->config.r600.sx_max_export_smx_size = 128;
1022 rdev->config.r600.sq_num_cf_insts = 2;
1023 break;
1024 case CHIP_RV610:
1025 case CHIP_RV620:
1026 case CHIP_RS780:
1027 case CHIP_RS880:
1028 rdev->config.r600.max_pipes = 1;
1029 rdev->config.r600.max_tile_pipes = 1;
1030 rdev->config.r600.max_simds = 2;
1031 rdev->config.r600.max_backends = 1;
1032 rdev->config.r600.max_gprs = 128;
1033 rdev->config.r600.max_threads = 192;
1034 rdev->config.r600.max_stack_entries = 128;
1035 rdev->config.r600.max_hw_contexts = 4;
1036 rdev->config.r600.max_gs_threads = 4;
1037 rdev->config.r600.sx_max_export_size = 128;
1038 rdev->config.r600.sx_max_export_pos_size = 16;
1039 rdev->config.r600.sx_max_export_smx_size = 128;
1040 rdev->config.r600.sq_num_cf_insts = 1;
1041 break;
1042 case CHIP_RV670:
1043 rdev->config.r600.max_pipes = 4;
1044 rdev->config.r600.max_tile_pipes = 4;
1045 rdev->config.r600.max_simds = 4;
1046 rdev->config.r600.max_backends = 4;
1047 rdev->config.r600.max_gprs = 192;
1048 rdev->config.r600.max_threads = 192;
1049 rdev->config.r600.max_stack_entries = 256;
1050 rdev->config.r600.max_hw_contexts = 8;
1051 rdev->config.r600.max_gs_threads = 16;
1052 rdev->config.r600.sx_max_export_size = 128;
1053 rdev->config.r600.sx_max_export_pos_size = 16;
1054 rdev->config.r600.sx_max_export_smx_size = 128;
1055 rdev->config.r600.sq_num_cf_insts = 2;
1056 break;
1057 default:
1058 break;
1059 }
1060
1061 /* Initialize HDP */
1062 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1063 WREG32((0x2c14 + j), 0x00000000);
1064 WREG32((0x2c18 + j), 0x00000000);
1065 WREG32((0x2c1c + j), 0x00000000);
1066 WREG32((0x2c20 + j), 0x00000000);
1067 WREG32((0x2c24 + j), 0x00000000);
1068 }
1069
1070 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1071
1072 /* Setup tiling */
1073 tiling_config = 0;
1074 ramcfg = RREG32(RAMCFG);
1075 switch (rdev->config.r600.max_tile_pipes) {
1076 case 1:
1077 tiling_config |= PIPE_TILING(0);
1078 break;
1079 case 2:
1080 tiling_config |= PIPE_TILING(1);
1081 break;
1082 case 4:
1083 tiling_config |= PIPE_TILING(2);
1084 break;
1085 case 8:
1086 tiling_config |= PIPE_TILING(3);
1087 break;
1088 default:
1089 break;
1090 }
d03f5d59 1091 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1092 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d
JG		 1093 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1094 tiling_config |= GROUP_SIZE(0);
961fb597 1095 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1096 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1097 if (tmp > 3) {
1098 tiling_config |= ROW_TILING(3);
1099 tiling_config |= SAMPLE_SPLIT(3);
1100 } else {
1101 tiling_config |= ROW_TILING(tmp);
1102 tiling_config |= SAMPLE_SPLIT(tmp);
1103 }
1104 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1105
1106 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1107 cc_rb_backend_disable |=
1108 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1109
1110 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1111 cc_gc_shader_pipe_config |=
1112 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1113 cc_gc_shader_pipe_config |=
1114 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1115
1116 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1117 (R6XX_MAX_BACKENDS -
1118 r600_count_pipe_bits((cc_rb_backend_disable &
1119 R6XX_MAX_BACKENDS_MASK) >> 16)),
1120 (cc_rb_backend_disable >> 16));
1121
1122 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1123 WREG32(GB_TILING_CONFIG, tiling_config);
1124 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1125 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1126
3ce0a23d 1127 /* Setup pipes */
d03f5d59
AD		 1128 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1129 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1130 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1131
d03f5d59 1132 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1133 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1134 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1135
1136 /* Setup some CP states */
1137 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1138 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1139
1140 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1141 SYNC_WALKER | SYNC_ALIGNER));
1142 /* Setup various GPU states */
1143 if (rdev->family == CHIP_RV670)
1144 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1145
1146 tmp = RREG32(SX_DEBUG_1);
1147 tmp |= SMX_EVENT_RELEASE;
1148 if ((rdev->family > CHIP_R600))
1149 tmp |= ENABLE_NEW_SMX_ADDRESS;
1150 WREG32(SX_DEBUG_1, tmp);
1151
1152 if (((rdev->family) == CHIP_R600) ||
1153 ((rdev->family) == CHIP_RV630) ||
1154 ((rdev->family) == CHIP_RV610) ||
1155 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1156 ((rdev->family) == CHIP_RS780) ||
1157 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1158 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1159 } else {
1160 WREG32(DB_DEBUG, 0);
1161 }
1162 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1163 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1164
1165 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1166 WREG32(VGT_NUM_INSTANCES, 0);
1167
1168 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1169 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1170
1171 tmp = RREG32(SQ_MS_FIFO_SIZES);
1172 if (((rdev->family) == CHIP_RV610) ||
1173 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1174 ((rdev->family) == CHIP_RS780) ||
1175 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1176 tmp = (CACHE_FIFO_SIZE(0xa) |
1177 FETCH_FIFO_HIWATER(0xa) |
1178 DONE_FIFO_HIWATER(0xe0) |
1179 ALU_UPDATE_FIFO_HIWATER(0x8));
1180 } else if (((rdev->family) == CHIP_R600) ||
1181 ((rdev->family) == CHIP_RV630)) {
1182 tmp &= ~DONE_FIFO_HIWATER(0xff);
1183 tmp |= DONE_FIFO_HIWATER(0x4);
1184 }
1185 WREG32(SQ_MS_FIFO_SIZES, tmp);
1186
1187 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1188 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1189 */
1190 sq_config = RREG32(SQ_CONFIG);
1191 sq_config &= ~(PS_PRIO(3) |
1192 VS_PRIO(3) |
1193 GS_PRIO(3) |
1194 ES_PRIO(3));
1195 sq_config |= (DX9_CONSTS |
1196 VC_ENABLE |
1197 PS_PRIO(0) |
1198 VS_PRIO(1) |
1199 GS_PRIO(2) |
1200 ES_PRIO(3));
1201
1202 if ((rdev->family) == CHIP_R600) {
1203 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1204 NUM_VS_GPRS(124) |
1205 NUM_CLAUSE_TEMP_GPRS(4));
1206 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1207 NUM_ES_GPRS(0));
1208 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1209 NUM_VS_THREADS(48) |
1210 NUM_GS_THREADS(4) |
1211 NUM_ES_THREADS(4));
1212 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1213 NUM_VS_STACK_ENTRIES(128));
1214 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1215 NUM_ES_STACK_ENTRIES(0));
1216 } else if (((rdev->family) == CHIP_RV610) ||
1217 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1218 ((rdev->family) == CHIP_RS780) ||
1219 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1220 /* no vertex cache */
1221 sq_config &= ~VC_ENABLE;
1222
1223 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1224 NUM_VS_GPRS(44) |
1225 NUM_CLAUSE_TEMP_GPRS(2));
1226 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1227 NUM_ES_GPRS(17));
1228 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1229 NUM_VS_THREADS(78) |
1230 NUM_GS_THREADS(4) |
1231 NUM_ES_THREADS(31));
1232 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1233 NUM_VS_STACK_ENTRIES(40));
1234 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1235 NUM_ES_STACK_ENTRIES(16));
1236 } else if (((rdev->family) == CHIP_RV630) ||
1237 ((rdev->family) == CHIP_RV635)) {
1238 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1239 NUM_VS_GPRS(44) |
1240 NUM_CLAUSE_TEMP_GPRS(2));
1241 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1242 NUM_ES_GPRS(18));
1243 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1244 NUM_VS_THREADS(78) |
1245 NUM_GS_THREADS(4) |
1246 NUM_ES_THREADS(31));
1247 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1248 NUM_VS_STACK_ENTRIES(40));
1249 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1250 NUM_ES_STACK_ENTRIES(16));
1251 } else if ((rdev->family) == CHIP_RV670) {
1252 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1253 NUM_VS_GPRS(44) |
1254 NUM_CLAUSE_TEMP_GPRS(2));
1255 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1256 NUM_ES_GPRS(17));
1257 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1258 NUM_VS_THREADS(78) |
1259 NUM_GS_THREADS(4) |
1260 NUM_ES_THREADS(31));
1261 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1262 NUM_VS_STACK_ENTRIES(64));
1263 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1264 NUM_ES_STACK_ENTRIES(64));
1265 }
1266
1267 WREG32(SQ_CONFIG, sq_config);
1268 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1269 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1270 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1271 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1272 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1273
1274 if (((rdev->family) == CHIP_RV610) ||
1275 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1276 ((rdev->family) == CHIP_RS780) ||
1277 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1278 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1279 } else {
1280 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1281 }
1282
1283 /* More default values. 2D/3D driver should adjust as needed */
1284 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1285 S1_X(0x4) | S1_Y(0xc)));
1286 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1287 S1_X(0x2) | S1_Y(0x2) |
1288 S2_X(0xa) | S2_Y(0x6) |
1289 S3_X(0x6) | S3_Y(0xa)));
1290 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1291 S1_X(0x4) | S1_Y(0xc) |
1292 S2_X(0x1) | S2_Y(0x6) |
1293 S3_X(0xa) | S3_Y(0xe)));
1294 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1295 S5_X(0x0) | S5_Y(0x0) |
1296 S6_X(0xb) | S6_Y(0x4) |
1297 S7_X(0x7) | S7_Y(0x8)));
1298
1299 WREG32(VGT_STRMOUT_EN, 0);
1300 tmp = rdev->config.r600.max_pipes * 16;
1301 switch (rdev->family) {
1302 case CHIP_RV610:
3ce0a23d 1303 case CHIP_RV620:
ee59f2b4
AD		 1304 case CHIP_RS780:
1305 case CHIP_RS880:
3ce0a23d
JG		 1306 tmp += 32;
1307 break;
1308 case CHIP_RV670:
1309 tmp += 128;
1310 break;
1311 default:
1312 break;
1313 }
1314 if (tmp > 256) {
1315 tmp = 256;
1316 }
1317 WREG32(VGT_ES_PER_GS, 128);
1318 WREG32(VGT_GS_PER_ES, tmp);
1319 WREG32(VGT_GS_PER_VS, 2);
1320 WREG32(VGT_GS_VERTEX_REUSE, 16);
1321
1322 /* more default values. 2D/3D driver should adjust as needed */
1323 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1324 WREG32(VGT_STRMOUT_EN, 0);
1325 WREG32(SX_MISC, 0);
1326 WREG32(PA_SC_MODE_CNTL, 0);
1327 WREG32(PA_SC_AA_CONFIG, 0);
1328 WREG32(PA_SC_LINE_STIPPLE, 0);
1329 WREG32(SPI_INPUT_Z, 0);
1330 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1331 WREG32(CB_COLOR7_FRAG, 0);
1332
1333 /* Clear render buffer base addresses */
1334 WREG32(CB_COLOR0_BASE, 0);
1335 WREG32(CB_COLOR1_BASE, 0);
1336 WREG32(CB_COLOR2_BASE, 0);
1337 WREG32(CB_COLOR3_BASE, 0);
1338 WREG32(CB_COLOR4_BASE, 0);
1339 WREG32(CB_COLOR5_BASE, 0);
1340 WREG32(CB_COLOR6_BASE, 0);
1341 WREG32(CB_COLOR7_BASE, 0);
1342 WREG32(CB_COLOR7_FRAG, 0);
1343
1344 switch (rdev->family) {
1345 case CHIP_RV610:
3ce0a23d 1346 case CHIP_RV620:
ee59f2b4
AD		 1347 case CHIP_RS780:
1348 case CHIP_RS880:
3ce0a23d
JG		 1349 tmp = TC_L2_SIZE(8);
1350 break;
1351 case CHIP_RV630:
1352 case CHIP_RV635:
1353 tmp = TC_L2_SIZE(4);
1354 break;
1355 case CHIP_R600:
1356 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1357 break;
1358 default:
1359 tmp = TC_L2_SIZE(0);
1360 break;
1361 }
1362 WREG32(TC_CNTL, tmp);
1363
1364 tmp = RREG32(HDP_HOST_PATH_CNTL);
1365 WREG32(HDP_HOST_PATH_CNTL, tmp);
1366
1367 tmp = RREG32(ARB_POP);
1368 tmp |= ENABLE_TC128;
1369 WREG32(ARB_POP, tmp);
1370
1371 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1372 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1373 NUM_CLIP_SEQ(3)));
1374 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1375}
1376
1377
771fe6b9
JG		 1378/*
1379 * Indirect registers accessor
1380 */
3ce0a23d
JG		 1381u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1382{
1383 u32 r;
1384
1385 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1386 (void)RREG32(PCIE_PORT_INDEX);
1387 r = RREG32(PCIE_PORT_DATA);
1388 return r;
1389}
1390
1391void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1392{
1393 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1394 (void)RREG32(PCIE_PORT_INDEX);
1395 WREG32(PCIE_PORT_DATA, (v));
1396 (void)RREG32(PCIE_PORT_DATA);
1397}
1398
3ce0a23d
JG		 1399/*
1400 * CP & Ring
1401 */
1402void r600_cp_stop(struct radeon_device *rdev)
1403{
1404 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1405}
1406
d8f60cfc 1407int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1408{
1409 struct platform_device *pdev;
1410 const char *chip_name;
d8f60cfc
AD		 1411 const char *rlc_chip_name;
1412 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1413 char fw_name[30];
1414 int err;
1415
1416 DRM_DEBUG("\n");
1417
1418 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1419 err = IS_ERR(pdev);
1420 if (err) {
1421 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1422 return -EINVAL;
1423 }
1424
1425 switch (rdev->family) {
d8f60cfc
AD		 1426 case CHIP_R600:
1427 chip_name = "R600";
1428 rlc_chip_name = "R600";
1429 break;
1430 case CHIP_RV610:
1431 chip_name = "RV610";
1432 rlc_chip_name = "R600";
1433 break;
1434 case CHIP_RV630:
1435 chip_name = "RV630";
1436 rlc_chip_name = "R600";
1437 break;
1438 case CHIP_RV620:
1439 chip_name = "RV620";
1440 rlc_chip_name = "R600";
1441 break;
1442 case CHIP_RV635:
1443 chip_name = "RV635";
1444 rlc_chip_name = "R600";
1445 break;
1446 case CHIP_RV670:
1447 chip_name = "RV670";
1448 rlc_chip_name = "R600";
1449 break;
3ce0a23d 1450 case CHIP_RS780:
d8f60cfc
AD		 1451 case CHIP_RS880:
1452 chip_name = "RS780";
1453 rlc_chip_name = "R600";
1454 break;
1455 case CHIP_RV770:
1456 chip_name = "RV770";
1457 rlc_chip_name = "R700";
1458 break;
3ce0a23d 1459 case CHIP_RV730:
d8f60cfc
AD		 1460 case CHIP_RV740:
1461 chip_name = "RV730";
1462 rlc_chip_name = "R700";
1463 break;
1464 case CHIP_RV710:
1465 chip_name = "RV710";
1466 rlc_chip_name = "R700";
1467 break;
fe251e2f
AD		 1468 case CHIP_CEDAR:
1469 chip_name = "CEDAR";
45f9a39b 1470 rlc_chip_name = "CEDAR";
fe251e2f
AD		 1471 break;
1472 case CHIP_REDWOOD:
1473 chip_name = "REDWOOD";
45f9a39b 1474 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 1475 break;
1476 case CHIP_JUNIPER:
1477 chip_name = "JUNIPER";
45f9a39b 1478 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 1479 break;
1480 case CHIP_CYPRESS:
1481 case CHIP_HEMLOCK:
1482 chip_name = "CYPRESS";
45f9a39b 1483 rlc_chip_name = "CYPRESS";
fe251e2f 1484 break;
3ce0a23d
JG		 1485 default: BUG();
1486 }
1487
fe251e2f
AD		 1488 if (rdev->family >= CHIP_CEDAR) {
1489 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1490 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 1491 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 1492 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 1493 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1494 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 1495 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1496 } else {
1497 pfp_req_size = PFP_UCODE_SIZE * 4;
1498 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 1499 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1500 }
1501
d8f60cfc 1502 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 1503
1504 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1505 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1506 if (err)
1507 goto out;
1508 if (rdev->pfp_fw->size != pfp_req_size) {
1509 printk(KERN_ERR
1510 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1511 rdev->pfp_fw->size, fw_name);
1512 err = -EINVAL;
1513 goto out;
1514 }
1515
1516 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1517 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1518 if (err)
1519 goto out;
1520 if (rdev->me_fw->size != me_req_size) {
1521 printk(KERN_ERR
1522 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1523 rdev->me_fw->size, fw_name);
1524 err = -EINVAL;
1525 }
d8f60cfc
AD		 1526
1527 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1528 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1529 if (err)
1530 goto out;
1531 if (rdev->rlc_fw->size != rlc_req_size) {
1532 printk(KERN_ERR
1533 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1534 rdev->rlc_fw->size, fw_name);
1535 err = -EINVAL;
1536 }
1537
3ce0a23d
JG		 1538out:
1539 platform_device_unregister(pdev);
1540
1541 if (err) {
1542 if (err != -EINVAL)
1543 printk(KERN_ERR
1544 "r600_cp: Failed to load firmware \"%s\"\n",
1545 fw_name);
1546 release_firmware(rdev->pfp_fw);
1547 rdev->pfp_fw = NULL;
1548 release_firmware(rdev->me_fw);
1549 rdev->me_fw = NULL;
d8f60cfc
AD		 1550 release_firmware(rdev->rlc_fw);
1551 rdev->rlc_fw = NULL;
3ce0a23d
JG		 1552 }
1553 return err;
1554}
1555
1556static int r600_cp_load_microcode(struct radeon_device *rdev)
1557{
1558 const __be32 *fw_data;
1559 int i;
1560
1561 if (!rdev->me_fw || !rdev->pfp_fw)
1562 return -EINVAL;
1563
1564 r600_cp_stop(rdev);
1565
1566 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1567
1568 /* Reset cp */
1569 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1570 RREG32(GRBM_SOFT_RESET);
1571 mdelay(15);
1572 WREG32(GRBM_SOFT_RESET, 0);
1573
1574 WREG32(CP_ME_RAM_WADDR, 0);
1575
1576 fw_data = (const __be32 *)rdev->me_fw->data;
1577 WREG32(CP_ME_RAM_WADDR, 0);
1578 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1579 WREG32(CP_ME_RAM_DATA,
1580 be32_to_cpup(fw_data++));
1581
1582 fw_data = (const __be32 *)rdev->pfp_fw->data;
1583 WREG32(CP_PFP_UCODE_ADDR, 0);
1584 for (i = 0; i < PFP_UCODE_SIZE; i++)
1585 WREG32(CP_PFP_UCODE_DATA,
1586 be32_to_cpup(fw_data++));
1587
1588 WREG32(CP_PFP_UCODE_ADDR, 0);
1589 WREG32(CP_ME_RAM_WADDR, 0);
1590 WREG32(CP_ME_RAM_RADDR, 0);
1591 return 0;
1592}
1593
1594int r600_cp_start(struct radeon_device *rdev)
1595{
1596 int r;
1597 uint32_t cp_me;
1598
1599 r = radeon_ring_lock(rdev, 7);
1600 if (r) {
1601 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1602 return r;
1603 }
1604 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1605 radeon_ring_write(rdev, 0x1);
fe251e2f
AD		 1606 if (rdev->family >= CHIP_CEDAR) {
1607 radeon_ring_write(rdev, 0x0);
1608 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1609 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 1610 radeon_ring_write(rdev, 0x0);
1611 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 1612 } else {
1613 radeon_ring_write(rdev, 0x3);
1614 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 1615 }
1616 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1617 radeon_ring_write(rdev, 0);
1618 radeon_ring_write(rdev, 0);
1619 radeon_ring_unlock_commit(rdev);
1620
1621 cp_me = 0xff;
1622 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1623 return 0;
1624}
1625
1626int r600_cp_resume(struct radeon_device *rdev)
1627{
1628 u32 tmp;
1629 u32 rb_bufsz;
1630 int r;
1631
1632 /* Reset cp */
1633 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1634 RREG32(GRBM_SOFT_RESET);
1635 mdelay(15);
1636 WREG32(GRBM_SOFT_RESET, 0);
1637
1638 /* Set ring buffer size */
1639 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
d6f28938 1640 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 1641#ifdef __BIG_ENDIAN
d6f28938 1642 tmp |= BUF_SWAP_32BIT;
3ce0a23d 1643#endif
d6f28938 1644 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 1645 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1646
1647 /* Set the write pointer delay */
1648 WREG32(CP_RB_WPTR_DELAY, 0);
1649
1650 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 1651 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1652 WREG32(CP_RB_RPTR_WR, 0);
1653 WREG32(CP_RB_WPTR, 0);
1654 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1655 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1656 mdelay(1);
1657 WREG32(CP_RB_CNTL, tmp);
1658
1659 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1660 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1661
1662 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1663 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1664
1665 r600_cp_start(rdev);
1666 rdev->cp.ready = true;
1667 r = radeon_ring_test(rdev);
1668 if (r) {
1669 rdev->cp.ready = false;
1670 return r;
1671 }
1672 return 0;
1673}
1674
1675void r600_cp_commit(struct radeon_device *rdev)
1676{
1677 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1678 (void)RREG32(CP_RB_WPTR);
1679}
1680
1681void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1682{
1683 u32 rb_bufsz;
1684
1685 /* Align ring size */
1686 rb_bufsz = drm_order(ring_size / 8);
1687 ring_size = (1 << (rb_bufsz + 1)) * 4;
1688 rdev->cp.ring_size = ring_size;
1689 rdev->cp.align_mask = 16 - 1;
1690}
1691
655efd3d
JG		 1692void r600_cp_fini(struct radeon_device *rdev)
1693{
1694 r600_cp_stop(rdev);
1695 radeon_ring_fini(rdev);
1696}
1697
3ce0a23d
JG		 1698
1699/*
1700 * GPU scratch registers helpers function.
1701 */
1702void r600_scratch_init(struct radeon_device *rdev)
1703{
1704 int i;
1705
1706 rdev->scratch.num_reg = 7;
1707 for (i = 0; i < rdev->scratch.num_reg; i++) {
1708 rdev->scratch.free[i] = true;
1709 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1710 }
1711}
1712
1713int r600_ring_test(struct radeon_device *rdev)
1714{
1715 uint32_t scratch;
1716 uint32_t tmp = 0;
1717 unsigned i;
1718 int r;
1719
1720 r = radeon_scratch_get(rdev, &scratch);
1721 if (r) {
1722 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1723 return r;
1724 }
1725 WREG32(scratch, 0xCAFEDEAD);
1726 r = radeon_ring_lock(rdev, 3);
1727 if (r) {
1728 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1729 radeon_scratch_free(rdev, scratch);
1730 return r;
1731 }
1732 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1733 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1734 radeon_ring_write(rdev, 0xDEADBEEF);
1735 radeon_ring_unlock_commit(rdev);
1736 for (i = 0; i < rdev->usec_timeout; i++) {
1737 tmp = RREG32(scratch);
1738 if (tmp == 0xDEADBEEF)
1739 break;
1740 DRM_UDELAY(1);
1741 }
1742 if (i < rdev->usec_timeout) {
1743 DRM_INFO("ring test succeeded in %d usecs\n", i);
1744 } else {
1745 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1746 scratch, tmp);
1747 r = -EINVAL;
1748 }
1749 radeon_scratch_free(rdev, scratch);
1750 return r;
1751}
1752
81cc35bf
JG		 1753void r600_wb_disable(struct radeon_device *rdev)
1754{
4c788679
JG		 1755 int r;
1756
81cc35bf
JG		 1757 WREG32(SCRATCH_UMSK, 0);
1758 if (rdev->wb.wb_obj) {
4c788679
JG		 1759 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1760 if (unlikely(r != 0))
1761 return;
1762 radeon_bo_kunmap(rdev->wb.wb_obj);
1763 radeon_bo_unpin(rdev->wb.wb_obj);
1764 radeon_bo_unreserve(rdev->wb.wb_obj);
81cc35bf
JG		 1765 }
1766}
1767
1768void r600_wb_fini(struct radeon_device *rdev)
1769{
1770 r600_wb_disable(rdev);
1771 if (rdev->wb.wb_obj) {
4c788679 1772 radeon_bo_unref(&rdev->wb.wb_obj);
81cc35bf
JG		 1773 rdev->wb.wb = NULL;
1774 rdev->wb.wb_obj = NULL;
1775 }
1776}
1777
1778int r600_wb_enable(struct radeon_device *rdev)
3ce0a23d
JG		 1779{
1780 int r;
1781
1782 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 1783 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1784 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
3ce0a23d 1785 if (r) {
4c788679 1786 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
3ce0a23d
JG		 1787 return r;
1788 }
4c788679
JG		 1789 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1790 if (unlikely(r != 0)) {
1791 r600_wb_fini(rdev);
3ce0a23d
JG		 1792 return r;
1793 }
4c788679 1794 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
81cc35bf 1795 &rdev->wb.gpu_addr);
3ce0a23d 1796 if (r) {
4c788679
JG		 1797 radeon_bo_unreserve(rdev->wb.wb_obj);
1798 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
81cc35bf 1799 r600_wb_fini(rdev);
3ce0a23d
JG		 1800 return r;
1801 }
4c788679
JG		 1802 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1803 radeon_bo_unreserve(rdev->wb.wb_obj);
3ce0a23d 1804 if (r) {
4c788679 1805 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
81cc35bf 1806 r600_wb_fini(rdev);
3ce0a23d
JG		 1807 return r;
1808 }
1809 }
1810 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1811 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1812 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1813 WREG32(SCRATCH_UMSK, 0xff);
1814 return 0;
1815}
1816
3ce0a23d
JG		 1817void r600_fence_ring_emit(struct radeon_device *rdev,
1818 struct radeon_fence *fence)
1819{
d8f60cfc 1820 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
44224c3f
AD		 1821
1822 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1823 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1824 /* wait for 3D idle clean */
1825 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1826 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1827 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
3ce0a23d
JG		 1828 /* Emit fence sequence & fire IRQ */
1829 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1830 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1831 radeon_ring_write(rdev, fence->seq);
d8f60cfc
AD		 1832 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1833 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1834 radeon_ring_write(rdev, RB_INT_STAT);
3ce0a23d
JG		 1835}
1836
3ce0a23d
JG		 1837int r600_copy_blit(struct radeon_device *rdev,
1838 uint64_t src_offset, uint64_t dst_offset,
1839 unsigned num_pages, struct radeon_fence *fence)
1840{
ff82f052
JG		 1841 int r;
1842
1843 mutex_lock(&rdev->r600_blit.mutex);
1844 rdev->r600_blit.vb_ib = NULL;
1845 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1846 if (r) {
1847 if (rdev->r600_blit.vb_ib)
1848 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1849 mutex_unlock(&rdev->r600_blit.mutex);
1850 return r;
1851 }
a77f1718 1852 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 1853 r600_blit_done_copy(rdev, fence);
ff82f052 1854 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 1855 return 0;
1856}
1857
3ce0a23d
JG		 1858int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1859 uint32_t tiling_flags, uint32_t pitch,
1860 uint32_t offset, uint32_t obj_size)
1861{
1862 /* FIXME: implement */
1863 return 0;
1864}
1865
1866void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1867{
1868 /* FIXME: implement */
1869}
1870
1871
1872bool r600_card_posted(struct radeon_device *rdev)
1873{
1874 uint32_t reg;
1875
1876 /* first check CRTCs */
1877 reg = RREG32(D1CRTC_CONTROL) |
1878 RREG32(D2CRTC_CONTROL);
1879 if (reg & CRTC_EN)
1880 return true;
1881
1882 /* then check MEM_SIZE, in case the crtcs are off */
1883 if (RREG32(CONFIG_MEMSIZE))
1884 return true;
1885
1886 return false;
1887}
1888
fc30b8ef 1889int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 1890{
1891 int r;
1892
779720a3
AD		 1893 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1894 r = r600_init_microcode(rdev);
1895 if (r) {
1896 DRM_ERROR("Failed to load firmware!\n");
1897 return r;
1898 }
1899 }
1900
a3c1945a 1901 r600_mc_program(rdev);
1a029b76
JG		 1902 if (rdev->flags & RADEON_IS_AGP) {
1903 r600_agp_enable(rdev);
1904 } else {
1905 r = r600_pcie_gart_enable(rdev);
1906 if (r)
1907 return r;
1908 }
3ce0a23d 1909 r600_gpu_init(rdev);
c38c7b64
JG		 1910 r = r600_blit_init(rdev);
1911 if (r) {
1912 r600_blit_fini(rdev);
1913 rdev->asic->copy = NULL;
1914 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1915 }
ff82f052
JG		 1916 /* pin copy shader into vram */
1917 if (rdev->r600_blit.shader_obj) {
1918 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1919 if (unlikely(r != 0))
1920 return r;
1921 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1922 &rdev->r600_blit.shader_gpu_addr);
1923 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
7923c615 1924 if (r) {
ff82f052 1925 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
7923c615
AD		 1926 return r;
1927 }
1928 }
d8f60cfc 1929 /* Enable IRQ */
d8f60cfc
AD		 1930 r = r600_irq_init(rdev);
1931 if (r) {
1932 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1933 radeon_irq_kms_fini(rdev);
1934 return r;
1935 }
1936 r600_irq_set(rdev);
1937
3ce0a23d
JG		 1938 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1939 if (r)
1940 return r;
1941 r = r600_cp_load_microcode(rdev);
1942 if (r)
1943 return r;
1944 r = r600_cp_resume(rdev);
1945 if (r)
1946 return r;
81cc35bf
JG		 1947 /* write back buffer are not vital so don't worry about failure */
1948 r600_wb_enable(rdev);
3ce0a23d
JG		 1949 return 0;
1950}
1951
28d52043
DA		 1952void r600_vga_set_state(struct radeon_device *rdev, bool state)
1953{
1954 uint32_t temp;
1955
1956 temp = RREG32(CONFIG_CNTL);
1957 if (state == false) {
1958 temp &= ~(1<<0);
1959 temp |= (1<<1);
1960 } else {
1961 temp &= ~(1<<1);
1962 }
1963 WREG32(CONFIG_CNTL, temp);
1964}
1965
fc30b8ef
DA		 1966int r600_resume(struct radeon_device *rdev)
1967{
1968 int r;
1969
1a029b76
JG		 1970 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1971 * posting will perform necessary task to bring back GPU into good
1972 * shape.
1973 */
fc30b8ef 1974 /* post card */
e7d40b9a 1975 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 1976 /* Initialize clocks */
1977 r = radeon_clocks_init(rdev);
1978 if (r) {
1979 return r;
1980 }
1981
1982 r = r600_startup(rdev);
1983 if (r) {
1984 DRM_ERROR("r600 startup failed on resume\n");
1985 return r;
1986 }
1987
62a8ea3f 1988 r = r600_ib_test(rdev);
fc30b8ef
DA		 1989 if (r) {
1990 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1991 return r;
1992 }
38fd2c6f
RM		 1993
1994 r = r600_audio_init(rdev);
1995 if (r) {
1996 DRM_ERROR("radeon: audio resume failed\n");
1997 return r;
1998 }
1999
fc30b8ef
DA		 2000 return r;
2001}
2002
3ce0a23d
JG		 2003int r600_suspend(struct radeon_device *rdev)
2004{
4c788679
JG		 2005 int r;
2006
38fd2c6f 2007 r600_audio_fini(rdev);
3ce0a23d
JG		 2008 /* FIXME: we should wait for ring to be empty */
2009 r600_cp_stop(rdev);
bc1a631e 2010 rdev->cp.ready = false;
0c45249f 2011 r600_irq_suspend(rdev);
81cc35bf 2012 r600_wb_disable(rdev);
4aac0473 2013 r600_pcie_gart_disable(rdev);
bc1a631e 2014 /* unpin shaders bo */
30d2d9a5
JG		 2015 if (rdev->r600_blit.shader_obj) {
2016 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2017 if (!r) {
2018 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2019 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2020 }
2021 }
3ce0a23d
JG		 2022 return 0;
2023}
2024
2025/* Plan is to move initialization in that function and use
2026 * helper function so that radeon_device_init pretty much
2027 * do nothing more than calling asic specific function. This
2028 * should also allow to remove a bunch of callback function
2029 * like vram_info.
2030 */
2031int r600_init(struct radeon_device *rdev)
771fe6b9 2032{
3ce0a23d 2033 int r;
771fe6b9 2034
3ce0a23d
JG		 2035 r = radeon_dummy_page_init(rdev);
2036 if (r)
2037 return r;
2038 if (r600_debugfs_mc_info_init(rdev)) {
2039 DRM_ERROR("Failed to register debugfs file for mc !\n");
2040 }
2041 /* This don't do much */
2042 r = radeon_gem_init(rdev);
2043 if (r)
2044 return r;
2045 /* Read BIOS */
2046 if (!radeon_get_bios(rdev)) {
2047 if (ASIC_IS_AVIVO(rdev))
2048 return -EINVAL;
2049 }
2050 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2051 if (!rdev->is_atom_bios) {
2052 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2053 return -EINVAL;
e7d40b9a 2054 }
3ce0a23d
JG		 2055 r = radeon_atombios_init(rdev);
2056 if (r)
2057 return r;
2058 /* Post card if necessary */
72542d77
DA		 2059 if (!r600_card_posted(rdev)) {
2060 if (!rdev->bios) {
2061 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2062 return -EINVAL;
2063 }
3ce0a23d
JG		 2064 DRM_INFO("GPU not posted. posting now...\n");
2065 atom_asic_init(rdev->mode_info.atom_context);
2066 }
2067 /* Initialize scratch registers */
2068 r600_scratch_init(rdev);
2069 /* Initialize surface registers */
2070 radeon_surface_init(rdev);
7433874e 2071 /* Initialize clocks */
5e6dde7e 2072 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2073 r = radeon_clocks_init(rdev);
2074 if (r)
2075 return r;
7433874e
RM		 2076 /* Initialize power management */
2077 radeon_pm_init(rdev);
3ce0a23d
JG		 2078 /* Fence driver */
2079 r = radeon_fence_driver_init(rdev);
2080 if (r)
2081 return r;
700a0cc0
JG		 2082 if (rdev->flags & RADEON_IS_AGP) {
2083 r = radeon_agp_init(rdev);
2084 if (r)
2085 radeon_agp_disable(rdev);
2086 }
3ce0a23d 2087 r = r600_mc_init(rdev);
b574f251 2088 if (r)
3ce0a23d 2089 return r;
3ce0a23d 2090 /* Memory manager */
4c788679 2091 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2092 if (r)
2093 return r;
d8f60cfc
AD		 2094
2095 r = radeon_irq_kms_init(rdev);
2096 if (r)
2097 return r;
2098
3ce0a23d
JG		 2099 rdev->cp.ring_obj = NULL;
2100 r600_ring_init(rdev, 1024 * 1024);
2101
d8f60cfc
AD		 2102 rdev->ih.ring_obj = NULL;
2103 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2104
4aac0473
JG		 2105 r = r600_pcie_gart_init(rdev);
2106 if (r)
2107 return r;
2108
779720a3 2109 rdev->accel_working = true;
fc30b8ef 2110 r = r600_startup(rdev);
3ce0a23d 2111 if (r) {
655efd3d
JG		 2112 dev_err(rdev->dev, "disabling GPU acceleration\n");
2113 r600_cp_fini(rdev);
75c81298 2114 r600_wb_fini(rdev);
655efd3d
JG		 2115 r600_irq_fini(rdev);
2116 radeon_irq_kms_fini(rdev);
75c81298 2117 r600_pcie_gart_fini(rdev);
733289c2 2118 rdev->accel_working = false;
3ce0a23d 2119 }
733289c2
JG		 2120 if (rdev->accel_working) {
2121 r = radeon_ib_pool_init(rdev);
2122 if (r) {
db96380e 2123 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2124 rdev->accel_working = false;
db96380e
JG		 2125 } else {
2126 r = r600_ib_test(rdev);
2127 if (r) {
2128 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2129 rdev->accel_working = false;
2130 }
733289c2 2131 }
3ce0a23d 2132 }
dafc3bd5
CK		 2133
2134 r = r600_audio_init(rdev);
2135 if (r)
2136 return r; /* TODO error handling */
3ce0a23d
JG		 2137 return 0;
2138}
2139
2140void r600_fini(struct radeon_device *rdev)
2141{
29fb52ca 2142 radeon_pm_fini(rdev);
dafc3bd5 2143 r600_audio_fini(rdev);
3ce0a23d 2144 r600_blit_fini(rdev);
655efd3d
JG		 2145 r600_cp_fini(rdev);
2146 r600_wb_fini(rdev);
d8f60cfc
AD		 2147 r600_irq_fini(rdev);
2148 radeon_irq_kms_fini(rdev);
4aac0473 2149 r600_pcie_gart_fini(rdev);
655efd3d 2150 radeon_agp_fini(rdev);
3ce0a23d
JG		 2151 radeon_gem_fini(rdev);
2152 radeon_fence_driver_fini(rdev);
2153 radeon_clocks_fini(rdev);
4c788679 2154 radeon_bo_fini(rdev);
e7d40b9a 2155 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2156 kfree(rdev->bios);
2157 rdev->bios = NULL;
2158 radeon_dummy_page_fini(rdev);
2159}
2160
2161
2162/*
2163 * CS stuff
2164 */
2165void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2166{
2167 /* FIXME: implement */
2168 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2169 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2170 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2171 radeon_ring_write(rdev, ib->length_dw);
2172}
2173
2174int r600_ib_test(struct radeon_device *rdev)
2175{
2176 struct radeon_ib *ib;
2177 uint32_t scratch;
2178 uint32_t tmp = 0;
2179 unsigned i;
2180 int r;
2181
2182 r = radeon_scratch_get(rdev, &scratch);
2183 if (r) {
2184 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2185 return r;
2186 }
2187 WREG32(scratch, 0xCAFEDEAD);
2188 r = radeon_ib_get(rdev, &ib);
2189 if (r) {
2190 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2191 return r;
2192 }
2193 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2194 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2195 ib->ptr[2] = 0xDEADBEEF;
2196 ib->ptr[3] = PACKET2(0);
2197 ib->ptr[4] = PACKET2(0);
2198 ib->ptr[5] = PACKET2(0);
2199 ib->ptr[6] = PACKET2(0);
2200 ib->ptr[7] = PACKET2(0);
2201 ib->ptr[8] = PACKET2(0);
2202 ib->ptr[9] = PACKET2(0);
2203 ib->ptr[10] = PACKET2(0);
2204 ib->ptr[11] = PACKET2(0);
2205 ib->ptr[12] = PACKET2(0);
2206 ib->ptr[13] = PACKET2(0);
2207 ib->ptr[14] = PACKET2(0);
2208 ib->ptr[15] = PACKET2(0);
2209 ib->length_dw = 16;
2210 r = radeon_ib_schedule(rdev, ib);
2211 if (r) {
2212 radeon_scratch_free(rdev, scratch);
2213 radeon_ib_free(rdev, &ib);
2214 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2215 return r;
2216 }
2217 r = radeon_fence_wait(ib->fence, false);
2218 if (r) {
2219 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2220 return r;
2221 }
2222 for (i = 0; i < rdev->usec_timeout; i++) {
2223 tmp = RREG32(scratch);
2224 if (tmp == 0xDEADBEEF)
2225 break;
2226 DRM_UDELAY(1);
2227 }
2228 if (i < rdev->usec_timeout) {
2229 DRM_INFO("ib test succeeded in %u usecs\n", i);
2230 } else {
2231 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2232 scratch, tmp);
2233 r = -EINVAL;
2234 }
2235 radeon_scratch_free(rdev, scratch);
2236 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2237 return r;
2238}
2239
d8f60cfc
AD		 2240/*
2241 * Interrupts
2242 *
2243 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2244 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2245 * writing to the ring and the GPU consuming, the GPU writes to the ring
2246 * and host consumes. As the host irq handler processes interrupts, it
2247 * increments the rptr. When the rptr catches up with the wptr, all the
2248 * current interrupts have been processed.
2249 */
2250
2251void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2252{
2253 u32 rb_bufsz;
2254
2255 /* Align ring size */
2256 rb_bufsz = drm_order(ring_size / 4);
2257 ring_size = (1 << rb_bufsz) * 4;
2258 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2259 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2260 rdev->ih.rptr = 0;
d8f60cfc
AD		 2261}
2262
0c45249f 2263static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2264{
2265 int r;
2266
d8f60cfc
AD		 2267 /* Allocate ring buffer */
2268 if (rdev->ih.ring_obj == NULL) {
4c788679
JG		 2269 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2270 true,
2271 RADEON_GEM_DOMAIN_GTT,
2272 &rdev->ih.ring_obj);
d8f60cfc
AD		 2273 if (r) {
2274 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2275 return r;
2276 }
4c788679
JG		 2277 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2278 if (unlikely(r != 0))
2279 return r;
2280 r = radeon_bo_pin(rdev->ih.ring_obj,
2281 RADEON_GEM_DOMAIN_GTT,
2282 &rdev->ih.gpu_addr);
d8f60cfc 2283 if (r) {
4c788679 2284 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2285 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2286 return r;
2287 }
4c788679
JG		 2288 r = radeon_bo_kmap(rdev->ih.ring_obj,
2289 (void **)&rdev->ih.ring);
2290 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2291 if (r) {
2292 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2293 return r;
2294 }
2295 }
d8f60cfc
AD		 2296 return 0;
2297}
2298
2299static void r600_ih_ring_fini(struct radeon_device *rdev)
2300{
4c788679 2301 int r;
d8f60cfc 2302 if (rdev->ih.ring_obj) {
4c788679
JG		 2303 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2304 if (likely(r == 0)) {
2305 radeon_bo_kunmap(rdev->ih.ring_obj);
2306 radeon_bo_unpin(rdev->ih.ring_obj);
2307 radeon_bo_unreserve(rdev->ih.ring_obj);
2308 }
2309 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2310 rdev->ih.ring = NULL;
2311 rdev->ih.ring_obj = NULL;
2312 }
2313}
2314
45f9a39b 2315void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2316{
2317
45f9a39b
AD		 2318 if ((rdev->family >= CHIP_RV770) &&
2319 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2320 /* r7xx asics need to soft reset RLC before halting */
2321 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2322 RREG32(SRBM_SOFT_RESET);
2323 udelay(15000);
2324 WREG32(SRBM_SOFT_RESET, 0);
2325 RREG32(SRBM_SOFT_RESET);
2326 }
2327
2328 WREG32(RLC_CNTL, 0);
2329}
2330
2331static void r600_rlc_start(struct radeon_device *rdev)
2332{
2333 WREG32(RLC_CNTL, RLC_ENABLE);
2334}
2335
2336static int r600_rlc_init(struct radeon_device *rdev)
2337{
2338 u32 i;
2339 const __be32 *fw_data;
2340
2341 if (!rdev->rlc_fw)
2342 return -EINVAL;
2343
2344 r600_rlc_stop(rdev);
2345
2346 WREG32(RLC_HB_BASE, 0);
2347 WREG32(RLC_HB_CNTL, 0);
2348 WREG32(RLC_HB_RPTR, 0);
2349 WREG32(RLC_HB_WPTR, 0);
2350 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2351 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2352 WREG32(RLC_MC_CNTL, 0);
2353 WREG32(RLC_UCODE_CNTL, 0);
2354
2355 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2356 if (rdev->family >= CHIP_CEDAR) {
2357 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2358 WREG32(RLC_UCODE_ADDR, i);
2359 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2360 }
2361 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2362 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2363 WREG32(RLC_UCODE_ADDR, i);
2364 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2365 }
2366 } else {
2367 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2368 WREG32(RLC_UCODE_ADDR, i);
2369 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2370 }
2371 }
2372 WREG32(RLC_UCODE_ADDR, 0);
2373
2374 r600_rlc_start(rdev);
2375
2376 return 0;
2377}
2378
2379static void r600_enable_interrupts(struct radeon_device *rdev)
2380{
2381 u32 ih_cntl = RREG32(IH_CNTL);
2382 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2383
2384 ih_cntl |= ENABLE_INTR;
2385 ih_rb_cntl |= IH_RB_ENABLE;
2386 WREG32(IH_CNTL, ih_cntl);
2387 WREG32(IH_RB_CNTL, ih_rb_cntl);
2388 rdev->ih.enabled = true;
2389}
2390
45f9a39b 2391void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2392{
2393 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2394 u32 ih_cntl = RREG32(IH_CNTL);
2395
2396 ih_rb_cntl &= ~IH_RB_ENABLE;
2397 ih_cntl &= ~ENABLE_INTR;
2398 WREG32(IH_RB_CNTL, ih_rb_cntl);
2399 WREG32(IH_CNTL, ih_cntl);
2400 /* set rptr, wptr to 0 */
2401 WREG32(IH_RB_RPTR, 0);
2402 WREG32(IH_RB_WPTR, 0);
2403 rdev->ih.enabled = false;
2404 rdev->ih.wptr = 0;
2405 rdev->ih.rptr = 0;
2406}
2407
e0df1ac5
AD		 2408static void r600_disable_interrupt_state(struct radeon_device *rdev)
2409{
2410 u32 tmp;
2411
2412 WREG32(CP_INT_CNTL, 0);
2413 WREG32(GRBM_INT_CNTL, 0);
2414 WREG32(DxMODE_INT_MASK, 0);
2415 if (ASIC_IS_DCE3(rdev)) {
2416 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2417 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2418 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2419 WREG32(DC_HPD1_INT_CONTROL, tmp);
2420 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2421 WREG32(DC_HPD2_INT_CONTROL, tmp);
2422 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2423 WREG32(DC_HPD3_INT_CONTROL, tmp);
2424 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2425 WREG32(DC_HPD4_INT_CONTROL, tmp);
2426 if (ASIC_IS_DCE32(rdev)) {
2427 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2428 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2429 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2430 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2431 }
2432 } else {
2433 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2434 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2435 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2436 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2437 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2438 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2439 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2440 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2441 }
2442}
2443
d8f60cfc
AD		 2444int r600_irq_init(struct radeon_device *rdev)
2445{
2446 int ret = 0;
2447 int rb_bufsz;
2448 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2449
2450 /* allocate ring */
0c45249f 2451 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2452 if (ret)
2453 return ret;
2454
2455 /* disable irqs */
2456 r600_disable_interrupts(rdev);
2457
2458 /* init rlc */
2459 ret = r600_rlc_init(rdev);
2460 if (ret) {
2461 r600_ih_ring_fini(rdev);
2462 return ret;
2463 }
2464
2465 /* setup interrupt control */
2466 /* set dummy read address to ring address */
2467 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2468 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2469 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2470 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2471 */
2472 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2473 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2474 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2475 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2476
2477 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2478 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2479
2480 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2481 IH_WPTR_OVERFLOW_CLEAR |
2482 (rb_bufsz << 1));
2483 /* WPTR writeback, not yet */
2484 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2485 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2486 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2487
2488 WREG32(IH_RB_CNTL, ih_rb_cntl);
2489
2490 /* set rptr, wptr to 0 */
2491 WREG32(IH_RB_RPTR, 0);
2492 WREG32(IH_RB_WPTR, 0);
2493
2494 /* Default settings for IH_CNTL (disabled at first) */
2495 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2496 /* RPTR_REARM only works if msi's are enabled */
2497 if (rdev->msi_enabled)
2498 ih_cntl |= RPTR_REARM;
2499
2500#ifdef __BIG_ENDIAN
2501 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2502#endif
2503 WREG32(IH_CNTL, ih_cntl);
2504
2505 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2506 if (rdev->family >= CHIP_CEDAR)
2507 evergreen_disable_interrupt_state(rdev);
2508 else
2509 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2510
2511 /* enable irqs */
2512 r600_enable_interrupts(rdev);
2513
2514 return ret;
2515}
2516
0c45249f 2517void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 2518{
45f9a39b 2519 r600_irq_disable(rdev);
d8f60cfc 2520 r600_rlc_stop(rdev);
0c45249f
JG		 2521}
2522
2523void r600_irq_fini(struct radeon_device *rdev)
2524{
2525 r600_irq_suspend(rdev);
d8f60cfc
AD		 2526 r600_ih_ring_fini(rdev);
2527}
2528
2529int r600_irq_set(struct radeon_device *rdev)
2530{
e0df1ac5
AD		 2531 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2532 u32 mode_int = 0;
2533 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
d8f60cfc 2534
003e69f9
JG		 2535 if (!rdev->irq.installed) {
2536 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2537 return -EINVAL;
2538 }
d8f60cfc 2539 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 2540 if (!rdev->ih.enabled) {
2541 r600_disable_interrupts(rdev);
2542 /* force the active interrupt state to all disabled */
2543 r600_disable_interrupt_state(rdev);
d8f60cfc 2544 return 0;
79c2bbc5 2545 }
d8f60cfc 2546
e0df1ac5
AD		 2547 if (ASIC_IS_DCE3(rdev)) {
2548 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2549 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2550 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2551 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2552 if (ASIC_IS_DCE32(rdev)) {
2553 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2554 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2555 }
2556 } else {
2557 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2558 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2559 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2560 }
2561
d8f60cfc
AD		 2562 if (rdev->irq.sw_int) {
2563 DRM_DEBUG("r600_irq_set: sw int\n");
2564 cp_int_cntl |= RB_INT_ENABLE;
2565 }
2566 if (rdev->irq.crtc_vblank_int[0]) {
2567 DRM_DEBUG("r600_irq_set: vblank 0\n");
2568 mode_int |= D1MODE_VBLANK_INT_MASK;
2569 }
2570 if (rdev->irq.crtc_vblank_int[1]) {
2571 DRM_DEBUG("r600_irq_set: vblank 1\n");
2572 mode_int |= D2MODE_VBLANK_INT_MASK;
2573 }
e0df1ac5
AD		 2574 if (rdev->irq.hpd[0]) {
2575 DRM_DEBUG("r600_irq_set: hpd 1\n");
2576 hpd1 |= DC_HPDx_INT_EN;
2577 }
2578 if (rdev->irq.hpd[1]) {
2579 DRM_DEBUG("r600_irq_set: hpd 2\n");
2580 hpd2 |= DC_HPDx_INT_EN;
2581 }
2582 if (rdev->irq.hpd[2]) {
2583 DRM_DEBUG("r600_irq_set: hpd 3\n");
2584 hpd3 |= DC_HPDx_INT_EN;
2585 }
2586 if (rdev->irq.hpd[3]) {
2587 DRM_DEBUG("r600_irq_set: hpd 4\n");
2588 hpd4 |= DC_HPDx_INT_EN;
2589 }
2590 if (rdev->irq.hpd[4]) {
2591 DRM_DEBUG("r600_irq_set: hpd 5\n");
2592 hpd5 |= DC_HPDx_INT_EN;
2593 }
2594 if (rdev->irq.hpd[5]) {
2595 DRM_DEBUG("r600_irq_set: hpd 6\n");
2596 hpd6 |= DC_HPDx_INT_EN;
2597 }
d8f60cfc
AD		 2598
2599 WREG32(CP_INT_CNTL, cp_int_cntl);
2600 WREG32(DxMODE_INT_MASK, mode_int);
e0df1ac5
AD		 2601 if (ASIC_IS_DCE3(rdev)) {
2602 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2603 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2604 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2605 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2606 if (ASIC_IS_DCE32(rdev)) {
2607 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2608 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2609 }
2610 } else {
2611 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2612 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2613 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2614 }
d8f60cfc
AD		 2615
2616 return 0;
2617}
2618
e0df1ac5
AD		 2619static inline void r600_irq_ack(struct radeon_device *rdev,
2620 u32 *disp_int,
2621 u32 *disp_int_cont,
2622 u32 *disp_int_cont2)
d8f60cfc 2623{
e0df1ac5
AD		 2624 u32 tmp;
2625
2626 if (ASIC_IS_DCE3(rdev)) {
2627 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2628 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2629 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2630 } else {
2631 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2632 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2633 *disp_int_cont2 = 0;
2634 }
d8f60cfc 2635
e0df1ac5 2636 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 2637 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 2638 if (*disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 2639 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5 2640 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 2641 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 2642 if (*disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 2643 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5
AD		 2644 if (*disp_int & DC_HPD1_INTERRUPT) {
2645 if (ASIC_IS_DCE3(rdev)) {
2646 tmp = RREG32(DC_HPD1_INT_CONTROL);
2647 tmp |= DC_HPDx_INT_ACK;
2648 WREG32(DC_HPD1_INT_CONTROL, tmp);
2649 } else {
2650 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2651 tmp |= DC_HPDx_INT_ACK;
2652 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2653 }
2654 }
2655 if (*disp_int & DC_HPD2_INTERRUPT) {
2656 if (ASIC_IS_DCE3(rdev)) {
2657 tmp = RREG32(DC_HPD2_INT_CONTROL);
2658 tmp |= DC_HPDx_INT_ACK;
2659 WREG32(DC_HPD2_INT_CONTROL, tmp);
2660 } else {
2661 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2662 tmp |= DC_HPDx_INT_ACK;
2663 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2664 }
2665 }
2666 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2667 if (ASIC_IS_DCE3(rdev)) {
2668 tmp = RREG32(DC_HPD3_INT_CONTROL);
2669 tmp |= DC_HPDx_INT_ACK;
2670 WREG32(DC_HPD3_INT_CONTROL, tmp);
2671 } else {
2672 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2673 tmp |= DC_HPDx_INT_ACK;
2674 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2675 }
2676 }
2677 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2678 tmp = RREG32(DC_HPD4_INT_CONTROL);
2679 tmp |= DC_HPDx_INT_ACK;
2680 WREG32(DC_HPD4_INT_CONTROL, tmp);
2681 }
2682 if (ASIC_IS_DCE32(rdev)) {
2683 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2684 tmp = RREG32(DC_HPD5_INT_CONTROL);
2685 tmp |= DC_HPDx_INT_ACK;
2686 WREG32(DC_HPD5_INT_CONTROL, tmp);
2687 }
2688 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2689 tmp = RREG32(DC_HPD5_INT_CONTROL);
2690 tmp |= DC_HPDx_INT_ACK;
2691 WREG32(DC_HPD6_INT_CONTROL, tmp);
2692 }
2693 }
d8f60cfc
AD		 2694}
2695
2696void r600_irq_disable(struct radeon_device *rdev)
2697{
e0df1ac5 2698 u32 disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc
AD		 2699
2700 r600_disable_interrupts(rdev);
2701 /* Wait and acknowledge irq */
2702 mdelay(1);
e0df1ac5
AD		 2703 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2704 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2705}
2706
2707static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2708{
2709 u32 wptr, tmp;
3ce0a23d 2710
d8f60cfc
AD		 2711 /* XXX use writeback */
2712 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 2713
d8f60cfc 2714 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 2715 /* When a ring buffer overflow happen start parsing interrupt
2716 * from the last not overwritten vector (wptr + 16). Hopefully
2717 * this should allow us to catchup.
2718 */
2719 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2720 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2721 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 2722 tmp = RREG32(IH_RB_CNTL);
2723 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2724 WREG32(IH_RB_CNTL, tmp);
2725 }
0c45249f 2726 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 2727}
3ce0a23d 2728
d8f60cfc
AD		 2729/* r600 IV Ring
2730 * Each IV ring entry is 128 bits:
2731 * [7:0] - interrupt source id
2732 * [31:8] - reserved
2733 * [59:32] - interrupt source data
2734 * [127:60] - reserved
2735 *
2736 * The basic interrupt vector entries
2737 * are decoded as follows:
2738 * src_id src_data description
2739 * 1 0 D1 Vblank
2740 * 1 1 D1 Vline
2741 * 5 0 D2 Vblank
2742 * 5 1 D2 Vline
2743 * 19 0 FP Hot plug detection A
2744 * 19 1 FP Hot plug detection B
2745 * 19 2 DAC A auto-detection
2746 * 19 3 DAC B auto-detection
2747 * 176 - CP_INT RB
2748 * 177 - CP_INT IB1
2749 * 178 - CP_INT IB2
2750 * 181 - EOP Interrupt
2751 * 233 - GUI Idle
2752 *
2753 * Note, these are based on r600 and may need to be
2754 * adjusted or added to on newer asics
2755 */
2756
2757int r600_irq_process(struct radeon_device *rdev)
2758{
2759 u32 wptr = r600_get_ih_wptr(rdev);
2760 u32 rptr = rdev->ih.rptr;
2761 u32 src_id, src_data;
e0df1ac5 2762 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc 2763 unsigned long flags;
d4877cf2 2764 bool queue_hotplug = false;
d8f60cfc
AD		 2765
2766 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 2767 if (!rdev->ih.enabled)
2768 return IRQ_NONE;
d8f60cfc
AD		 2769
2770 spin_lock_irqsave(&rdev->ih.lock, flags);
2771
2772 if (rptr == wptr) {
2773 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2774 return IRQ_NONE;
2775 }
2776 if (rdev->shutdown) {
2777 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2778 return IRQ_NONE;
2779 }
2780
2781restart_ih:
2782 /* display interrupts */
e0df1ac5 2783 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
d8f60cfc
AD		 2784
2785 rdev->ih.wptr = wptr;
2786 while (rptr != wptr) {
2787 /* wptr/rptr are in bytes! */
2788 ring_index = rptr / 4;
2789 src_id = rdev->ih.ring[ring_index] & 0xff;
2790 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2791
2792 switch (src_id) {
2793 case 1: /* D1 vblank/vline */
2794 switch (src_data) {
2795 case 0: /* D1 vblank */
2796 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2797 drm_handle_vblank(rdev->ddev, 0);
839461d3 2798 rdev->pm.vblank_sync = true;
73a6d3fc 2799 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 2800 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2801 DRM_DEBUG("IH: D1 vblank\n");
2802 }
2803 break;
2804 case 1: /* D1 vline */
2805 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2806 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2807 DRM_DEBUG("IH: D1 vline\n");
2808 }
2809 break;
2810 default:
b042589c 2811 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 2812 break;
2813 }
2814 break;
2815 case 5: /* D2 vblank/vline */
2816 switch (src_data) {
2817 case 0: /* D2 vblank */
2818 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2819 drm_handle_vblank(rdev->ddev, 1);
839461d3 2820 rdev->pm.vblank_sync = true;
73a6d3fc 2821 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 2822 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2823 DRM_DEBUG("IH: D2 vblank\n");
2824 }
2825 break;
2826 case 1: /* D1 vline */
2827 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2828 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2829 DRM_DEBUG("IH: D2 vline\n");
2830 }
2831 break;
2832 default:
b042589c 2833 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 2834 break;
2835 }
2836 break;
e0df1ac5
AD		 2837 case 19: /* HPD/DAC hotplug */
2838 switch (src_data) {
2839 case 0:
2840 if (disp_int & DC_HPD1_INTERRUPT) {
2841 disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 2842 queue_hotplug = true;
2843 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 2844 }
2845 break;
2846 case 1:
2847 if (disp_int & DC_HPD2_INTERRUPT) {
2848 disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 2849 queue_hotplug = true;
2850 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 2851 }
2852 break;
2853 case 4:
2854 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2855 disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 2856 queue_hotplug = true;
2857 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 2858 }
2859 break;
2860 case 5:
2861 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2862 disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 2863 queue_hotplug = true;
2864 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 2865 }
2866 break;
2867 case 10:
2868 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
5898b1f3 2869 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 2870 queue_hotplug = true;
2871 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 2872 }
2873 break;
2874 case 12:
2875 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
5898b1f3 2876 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 2877 queue_hotplug = true;
2878 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 2879 }
2880 break;
2881 default:
b042589c 2882 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 2883 break;
2884 }
2885 break;
d8f60cfc
AD		 2886 case 176: /* CP_INT in ring buffer */
2887 case 177: /* CP_INT in IB1 */
2888 case 178: /* CP_INT in IB2 */
2889 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2890 radeon_fence_process(rdev);
2891 break;
2892 case 181: /* CP EOP event */
2893 DRM_DEBUG("IH: CP EOP\n");
2894 break;
2895 default:
b042589c 2896 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 2897 break;
2898 }
2899
2900 /* wptr/rptr are in bytes! */
0c45249f
JG		 2901 rptr += 16;
2902 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 2903 }
2904 /* make sure wptr hasn't changed while processing */
2905 wptr = r600_get_ih_wptr(rdev);
2906 if (wptr != rdev->ih.wptr)
2907 goto restart_ih;
d4877cf2
AD		 2908 if (queue_hotplug)
2909 queue_work(rdev->wq, &rdev->hotplug_work);
d8f60cfc
AD		 2910 rdev->ih.rptr = rptr;
2911 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2912 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2913 return IRQ_HANDLED;
2914}
3ce0a23d
JG		 2915
2916/*
2917 * Debugfs info
2918 */
2919#if defined(CONFIG_DEBUG_FS)
2920
2921static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 2922{
3ce0a23d
JG		 2923 struct drm_info_node *node = (struct drm_info_node *) m->private;
2924 struct drm_device *dev = node->minor->dev;
2925 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 2926 unsigned count, i, j;
2927
2928 radeon_ring_free_size(rdev);
d6840766 2929 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 2930 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 2931 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2932 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2933 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2934 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 2935 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2936 seq_printf(m, "%u dwords in ring\n", count);
d6840766 2937 i = rdev->cp.rptr;
3ce0a23d 2938 for (j = 0; j <= count; j++) {
3ce0a23d 2939 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 2940 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 2941 }
2942 return 0;
2943}
2944
2945static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2946{
2947 struct drm_info_node *node = (struct drm_info_node *) m->private;
2948 struct drm_device *dev = node->minor->dev;
2949 struct radeon_device *rdev = dev->dev_private;
2950
2951 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2952 DREG32_SYS(m, rdev, VM_L2_STATUS);
2953 return 0;
2954}
2955
2956static struct drm_info_list r600_mc_info_list[] = {
2957 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2958 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2959};
2960#endif
2961
2962int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2963{
2964#if defined(CONFIG_DEBUG_FS)
2965 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2966#else
2967 return 0;
2968#endif
771fe6b9 2969}
062b389c
JG		 2970
2971/**
2972 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2973 * rdev: radeon device structure
2974 * bo: buffer object struct which userspace is waiting for idle
2975 *
2976 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2977 * through ring buffer, this leads to corruption in rendering, see
2978 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2979 * directly perform HDP flush by writing register through MMIO.
2980 */
2981void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2982{
2983 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2984}
Clone of davem's net-next-2.6 tree