[net-next-2.6.git] / drivers / gpu / drm / radeon / r100_track.h


#define R100_TRACK_MAX_TEXTURE 3
#define R200_TRACK_MAX_TEXTURE 6
#define R300_TRACK_MAX_TEXTURE 16

#define R100_MAX_CB 1
#define R300_MAX_CB 4

/*
 * CS functions
 */
struct r100_cs_track_cb {
	struct radeon_bo	*robj;
	unsigned		pitch;
	unsigned		cpp;
	unsigned		offset;
};

struct r100_cs_track_array {
	struct radeon_bo	*robj;
	unsigned		esize;
};

struct r100_cs_cube_info {
	struct radeon_bo	*robj;
	unsigned		offset;
	unsigned		width;
	unsigned		height;
};

struct r100_cs_track_texture {
	struct radeon_bo	*robj;
	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
	unsigned		pitch;
	unsigned		width;
	unsigned		height;
	unsigned		num_levels;
	unsigned		cpp;
	unsigned		tex_coord_type;
	unsigned		txdepth;
	unsigned		width_11;
	unsigned		height_11;
	bool			use_pitch;
	bool			enabled;
	bool			roundup_w;
	bool			roundup_h;
};

struct r100_cs_track_limits {
	unsigned num_cb;
	unsigned num_texture;
	unsigned max_levels;
};

struct r100_cs_track {
	struct radeon_device *rdev;
	unsigned			num_cb;
	unsigned                        num_texture;
	unsigned			maxy;
	unsigned			vtx_size;
	unsigned			vap_vf_cntl;
	unsigned			immd_dwords;
	unsigned			num_arrays;
	unsigned			max_indx;
	struct r100_cs_track_array	arrays[11];
	struct r100_cs_track_cb 	cb[R300_MAX_CB];
	struct r100_cs_track_cb 	zb;
	struct r100_cs_track_texture	textures[R300_TRACK_MAX_TEXTURE];
	bool				z_enabled;
	bool                            separate_cube;

};

int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
			      struct radeon_cs_reloc **cs_reloc);
void r100_cs_dump_packet(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt);

int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);

int r200_packet0_check(struct radeon_cs_parser *p,
		       struct radeon_cs_packet *pkt,
		       unsigned idx, unsigned reg);


static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
					  struct radeon_cs_packet *pkt,
					  unsigned idx,
					  unsigned reg)
{
	int r;
	u32 tile_flags = 0;
	u32 tmp;
	struct radeon_cs_reloc *reloc;
	u32 value;

	r = r100_cs_packet_next_reloc(p, &reloc);
	if (r) {
		DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
			  idx, reg);
		r100_cs_dump_packet(p, pkt);
		return r;
	}
	value = radeon_get_ib_value(p, idx);
	tmp = value & 0x003fffff;
	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);

	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		tile_flags |= RADEON_DST_TILE_MACRO;
	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
		if (reg == RADEON_SRC_PITCH_OFFSET) {
			DRM_ERROR("Cannot src blit from microtiled surface\n");
			r100_cs_dump_packet(p, pkt);
			return -EINVAL;
		}
		tile_flags |= RADEON_DST_TILE_MICRO;
	}

	tmp |= tile_flags;
	p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
	return 0;
}

static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
					   struct radeon_cs_packet *pkt,
					   int idx)
{
	unsigned c, i;
	struct radeon_cs_reloc *reloc;
	struct r100_cs_track *track;
	int r = 0;
	volatile uint32_t *ib;
	u32 idx_value;

	ib = p->ib->ptr;
	track = (struct r100_cs_track *)p->track;
	c = radeon_get_ib_value(p, idx++) & 0x1F;
	track->num_arrays = c;
	for (i = 0; i < (c - 1); i+=2, idx+=3) {
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for packet3 %d\n",
				  pkt->opcode);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		idx_value = radeon_get_ib_value(p, idx);
		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);

		track->arrays[i + 0].esize = idx_value >> 8;
		track->arrays[i + 0].robj = reloc->robj;
		track->arrays[i + 0].esize &= 0x7F;
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for packet3 %d\n",
				  pkt->opcode);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
		track->arrays[i + 1].robj = reloc->robj;
		track->arrays[i + 1].esize = idx_value >> 24;
		track->arrays[i + 1].esize &= 0x7F;
	}
	if (c & 1) {
		r = r100_cs_packet_next_reloc(p, &reloc);
		if (r) {
			DRM_ERROR("No reloc for packet3 %d\n",
					  pkt->opcode);
			r100_cs_dump_packet(p, pkt);
			return r;
		}
		idx_value = radeon_get_ib_value(p, idx);
		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
		track->arrays[i + 0].robj = reloc->robj;
		track->arrays[i + 0].esize = idx_value >> 8;
		track->arrays[i + 0].esize &= 0x7F;
	}
	return r;
}
Commit	Line	Data
551ebd83 DA	1
	2	#define R100_TRACK_MAX_TEXTURE 3
	3	#define R200_TRACK_MAX_TEXTURE 6
	4	#define R300_TRACK_MAX_TEXTURE 16
	5
	6	#define R100_MAX_CB 1
	7	#define R300_MAX_CB 4
	8
	9	/*
	10	* CS functions
	11	*/
	12	struct r100_cs_track_cb {
4c788679	13	struct radeon_bo *robj;
551ebd83 DA	14	unsigned pitch;
	15	unsigned cpp;
	16	unsigned offset;
	17	};
	18
	19	struct r100_cs_track_array {
4c788679	20	struct radeon_bo *robj;
551ebd83 DA	21	unsigned esize;
	22	};
	23
	24	struct r100_cs_cube_info {
4c788679 JG	25	struct radeon_bo *robj;
4c788679 JG	26	unsigned offset;
551ebd83 DA	27	unsigned width;
	28	unsigned height;
	29	};
	30
	31	struct r100_cs_track_texture {
4c788679	32	struct radeon_bo *robj;
551ebd83 DA	33	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
	34	unsigned pitch;
	35	unsigned width;
	36	unsigned height;
	37	unsigned num_levels;
	38	unsigned cpp;
	39	unsigned tex_coord_type;
	40	unsigned txdepth;
	41	unsigned width_11;
	42	unsigned height_11;
	43	bool use_pitch;
	44	bool enabled;
	45	bool roundup_w;
	46	bool roundup_h;
	47	};
	48
	49	struct r100_cs_track_limits {
	50	unsigned num_cb;
	51	unsigned num_texture;
	52	unsigned max_levels;
	53	};
	54
	55	struct r100_cs_track {
	56	struct radeon_device *rdev;
	57	unsigned num_cb;
	58	unsigned num_texture;
	59	unsigned maxy;
	60	unsigned vtx_size;
	61	unsigned vap_vf_cntl;
	62	unsigned immd_dwords;
	63	unsigned num_arrays;
	64	unsigned max_indx;
	65	struct r100_cs_track_array arrays[11];
	66	struct r100_cs_track_cb cb[R300_MAX_CB];
	67	struct r100_cs_track_cb zb;
	68	struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
	69	bool z_enabled;
	70	bool separate_cube;
	71
	72	};
	73
	74	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track);
	75	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track);
	76	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
	77	struct radeon_cs_reloc **cs_reloc);
	78	void r100_cs_dump_packet(struct radeon_cs_parser *p,
	79	struct radeon_cs_packet *pkt);
	80
	81	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
	82
	83	int r200_packet0_check(struct radeon_cs_parser *p,
	84	struct radeon_cs_packet *pkt,
	85	unsigned idx, unsigned reg);
	86
513bcb46 DA	87
513bcb46 DA	88
551ebd83 DA	89	static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
	90	struct radeon_cs_packet *pkt,
	91	unsigned idx,
	92	unsigned reg)
	93	{
	94	int r;
	95	u32 tile_flags = 0;
	96	u32 tmp;
	97	struct radeon_cs_reloc *reloc;
513bcb46	98	u32 value;
551ebd83 DA	99
	100	r = r100_cs_packet_next_reloc(p, &reloc);
	101	if (r) {
	102	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
	103	idx, reg);
	104	r100_cs_dump_packet(p, pkt);
	105	return r;
	106	}
513bcb46 DA	107	value = radeon_get_ib_value(p, idx);
513bcb46 DA	108	tmp = value & 0x003fffff;
551ebd83 DA	109	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
	110
	111	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
	112	tile_flags \|= RADEON_DST_TILE_MACRO;
	113	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
	114	if (reg == RADEON_SRC_PITCH_OFFSET) {
	115	DRM_ERROR("Cannot src blit from microtiled surface\n");
	116	r100_cs_dump_packet(p, pkt);
	117	return -EINVAL;
	118	}
	119	tile_flags \|= RADEON_DST_TILE_MICRO;
	120	}
	121
	122	tmp \|= tile_flags;
513bcb46	123	p->ib->ptr[idx] = (value & 0x3fc00000) \| tmp;
551ebd83 DA	124	return 0;
551ebd83 DA	125	}
513bcb46 DA	126
	127	static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
	128	struct radeon_cs_packet *pkt,
	129	int idx)
	130	{
	131	unsigned c, i;
	132	struct radeon_cs_reloc *reloc;
	133	struct r100_cs_track *track;
	134	int r = 0;
	135	volatile uint32_t *ib;
	136	u32 idx_value;
	137
	138	ib = p->ib->ptr;
	139	track = (struct r100_cs_track *)p->track;
	140	c = radeon_get_ib_value(p, idx++) & 0x1F;
	141	track->num_arrays = c;
	142	for (i = 0; i < (c - 1); i+=2, idx+=3) {
	143	r = r100_cs_packet_next_reloc(p, &reloc);
	144	if (r) {
	145	DRM_ERROR("No reloc for packet3 %d\n",
	146	pkt->opcode);
	147	r100_cs_dump_packet(p, pkt);
	148	return r;
	149	}
	150	idx_value = radeon_get_ib_value(p, idx);
	151	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
	152
	153	track->arrays[i + 0].esize = idx_value >> 8;
	154	track->arrays[i + 0].robj = reloc->robj;
	155	track->arrays[i + 0].esize &= 0x7F;
	156	r = r100_cs_packet_next_reloc(p, &reloc);
	157	if (r) {
	158	DRM_ERROR("No reloc for packet3 %d\n",
	159	pkt->opcode);
	160	r100_cs_dump_packet(p, pkt);
	161	return r;
	162	}
	163	ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
	164	track->arrays[i + 1].robj = reloc->robj;
	165	track->arrays[i + 1].esize = idx_value >> 24;
	166	track->arrays[i + 1].esize &= 0x7F;
	167	}
	168	if (c & 1) {
	169	r = r100_cs_packet_next_reloc(p, &reloc);
	170	if (r) {
	171	DRM_ERROR("No reloc for packet3 %d\n",
	172	pkt->opcode);
	173	r100_cs_dump_packet(p, pkt);
	174	return r;
	175	}
	176	idx_value = radeon_get_ib_value(p, idx);
	177	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
	178	track->arrays[i + 0].robj = reloc->robj;
	179	track->arrays[i + 0].esize = idx_value >> 8;
	180	track->arrays[i + 0].esize &= 0x7F;
	181	}
	182	return r;
	183	}