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[net-next-2.6.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
3ce0a23d 34#include "r100d.h"
d4550907
JG		 35#include "rs100d.h"
36#include "rv200d.h"
37#include "rv250d.h"
3ce0a23d 38
70967ab9
BH		 39#include <linux/firmware.h>
40#include <linux/platform_device.h>
41
551ebd83
DA		 42#include "r100_reg_safe.h"
43#include "rn50_reg_safe.h"
44
70967ab9
BH		 45/* Firmware Names */
46#define FIRMWARE_R100 "radeon/R100_cp.bin"
47#define FIRMWARE_R200 "radeon/R200_cp.bin"
48#define FIRMWARE_R300 "radeon/R300_cp.bin"
49#define FIRMWARE_R420 "radeon/R420_cp.bin"
50#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52#define FIRMWARE_R520 "radeon/R520_cp.bin"
53
54MODULE_FIRMWARE(FIRMWARE_R100);
55MODULE_FIRMWARE(FIRMWARE_R200);
56MODULE_FIRMWARE(FIRMWARE_R300);
57MODULE_FIRMWARE(FIRMWARE_R420);
58MODULE_FIRMWARE(FIRMWARE_RS690);
59MODULE_FIRMWARE(FIRMWARE_RS600);
60MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 61
551ebd83
DA		 62#include "r100_track.h"
63
771fe6b9
JG		 64/* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 66 */
771fe6b9 67
05a05c50
AD		 68/* hpd for digital panel detect/disconnect */
69bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
70{
71 bool connected = false;
72
73 switch (hpd) {
74 case RADEON_HPD_1:
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
76 connected = true;
77 break;
78 case RADEON_HPD_2:
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86}
87
88void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90{
91 u32 tmp;
92 bool connected = r100_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
97 if (connected)
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
99 else
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
105 if (connected)
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
107 else
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
110 break;
111 default:
112 break;
113 }
114}
115
116void r100_hpd_init(struct radeon_device *rdev)
117{
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 rdev->irq.hpd[0] = true;
126 break;
127 case RADEON_HPD_2:
128 rdev->irq.hpd[1] = true;
129 break;
130 default:
131 break;
132 }
133 }
134 r100_irq_set(rdev);
135}
136
137void r100_hpd_fini(struct radeon_device *rdev)
138{
139 struct drm_device *dev = rdev->ddev;
140 struct drm_connector *connector;
141
142 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
143 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
144 switch (radeon_connector->hpd.hpd) {
145 case RADEON_HPD_1:
146 rdev->irq.hpd[0] = false;
147 break;
148 case RADEON_HPD_2:
149 rdev->irq.hpd[1] = false;
150 break;
151 default:
152 break;
153 }
154 }
155}
156
771fe6b9
JG		 157/*
158 * PCI GART
159 */
160void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
161{
162 /* TODO: can we do somethings here ? */
163 /* It seems hw only cache one entry so we should discard this
164 * entry otherwise if first GPU GART read hit this entry it
165 * could end up in wrong address. */
166}
167
4aac0473 168int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 169{
771fe6b9
JG		 170 int r;
171
4aac0473
JG		 172 if (rdev->gart.table.ram.ptr) {
173 WARN(1, "R100 PCI GART already initialized.\n");
174 return 0;
175 }
771fe6b9
JG		 176 /* Initialize common gart structure */
177 r = radeon_gart_init(rdev);
4aac0473 178 if (r)
771fe6b9 179 return r;
4aac0473
JG		 180 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
181 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
182 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
183 return radeon_gart_table_ram_alloc(rdev);
184}
185
17e15b0c
DA		 186/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
187void r100_enable_bm(struct radeon_device *rdev)
188{
189 uint32_t tmp;
190 /* Enable bus mastering */
191 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
192 WREG32(RADEON_BUS_CNTL, tmp);
193}
194
4aac0473
JG		 195int r100_pci_gart_enable(struct radeon_device *rdev)
196{
197 uint32_t tmp;
198
771fe6b9
JG		 199 /* discard memory request outside of configured range */
200 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
201 WREG32(RADEON_AIC_CNTL, tmp);
202 /* set address range for PCI address translate */
203 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
204 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
205 WREG32(RADEON_AIC_HI_ADDR, tmp);
771fe6b9
JG		 206 /* set PCI GART page-table base address */
207 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
208 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
209 WREG32(RADEON_AIC_CNTL, tmp);
210 r100_pci_gart_tlb_flush(rdev);
211 rdev->gart.ready = true;
212 return 0;
213}
214
215void r100_pci_gart_disable(struct radeon_device *rdev)
216{
217 uint32_t tmp;
218
219 /* discard memory request outside of configured range */
220 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
221 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
222 WREG32(RADEON_AIC_LO_ADDR, 0);
223 WREG32(RADEON_AIC_HI_ADDR, 0);
224}
225
226int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
227{
228 if (i < 0 || i > rdev->gart.num_gpu_pages) {
229 return -EINVAL;
230 }
ed10f95d 231 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 232 return 0;
233}
234
4aac0473 235void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 236{
4aac0473
JG		 237 r100_pci_gart_disable(rdev);
238 radeon_gart_table_ram_free(rdev);
239 radeon_gart_fini(rdev);
771fe6b9
JG		 240}
241
7ed220d7
MD		 242int r100_irq_set(struct radeon_device *rdev)
243{
244 uint32_t tmp = 0;
245
246 if (rdev->irq.sw_int) {
247 tmp |= RADEON_SW_INT_ENABLE;
248 }
249 if (rdev->irq.crtc_vblank_int[0]) {
250 tmp |= RADEON_CRTC_VBLANK_MASK;
251 }
252 if (rdev->irq.crtc_vblank_int[1]) {
253 tmp |= RADEON_CRTC2_VBLANK_MASK;
254 }
05a05c50
AD		 255 if (rdev->irq.hpd[0]) {
256 tmp |= RADEON_FP_DETECT_MASK;
257 }
258 if (rdev->irq.hpd[1]) {
259 tmp |= RADEON_FP2_DETECT_MASK;
260 }
7ed220d7
MD		 261 WREG32(RADEON_GEN_INT_CNTL, tmp);
262 return 0;
263}
264
9f022ddf
JG		 265void r100_irq_disable(struct radeon_device *rdev)
266{
267 u32 tmp;
268
269 WREG32(R_000040_GEN_INT_CNTL, 0);
270 /* Wait and acknowledge irq */
271 mdelay(1);
272 tmp = RREG32(R_000044_GEN_INT_STATUS);
273 WREG32(R_000044_GEN_INT_STATUS, tmp);
274}
275
7ed220d7
MD		 276static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
277{
278 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 279 uint32_t irq_mask = RADEON_SW_INT_TEST |
280 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
281 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 282
283 if (irqs) {
284 WREG32(RADEON_GEN_INT_STATUS, irqs);
285 }
286 return irqs & irq_mask;
287}
288
289int r100_irq_process(struct radeon_device *rdev)
290{
3e5cb98d 291 uint32_t status, msi_rearm;
d4877cf2 292 bool queue_hotplug = false;
7ed220d7
MD		 293
294 status = r100_irq_ack(rdev);
295 if (!status) {
296 return IRQ_NONE;
297 }
a513c184
JG		 298 if (rdev->shutdown) {
299 return IRQ_NONE;
300 }
7ed220d7
MD		 301 while (status) {
302 /* SW interrupt */
303 if (status & RADEON_SW_INT_TEST) {
304 radeon_fence_process(rdev);
305 }
306 /* Vertical blank interrupts */
307 if (status & RADEON_CRTC_VBLANK_STAT) {
308 drm_handle_vblank(rdev->ddev, 0);
309 }
310 if (status & RADEON_CRTC2_VBLANK_STAT) {
311 drm_handle_vblank(rdev->ddev, 1);
312 }
05a05c50 313 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 314 queue_hotplug = true;
315 DRM_DEBUG("HPD1\n");
05a05c50
AD		 316 }
317 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 318 queue_hotplug = true;
319 DRM_DEBUG("HPD2\n");
05a05c50 320 }
7ed220d7
MD		 321 status = r100_irq_ack(rdev);
322 }
d4877cf2
AD		 323 if (queue_hotplug)
324 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 325 if (rdev->msi_enabled) {
326 switch (rdev->family) {
327 case CHIP_RS400:
328 case CHIP_RS480:
329 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
330 WREG32(RADEON_AIC_CNTL, msi_rearm);
331 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
332 break;
333 default:
334 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
335 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
336 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
337 break;
338 }
339 }
7ed220d7
MD		 340 return IRQ_HANDLED;
341}
342
343u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
344{
345 if (crtc == 0)
346 return RREG32(RADEON_CRTC_CRNT_FRAME);
347 else
348 return RREG32(RADEON_CRTC2_CRNT_FRAME);
349}
350
771fe6b9
JG		 351void r100_fence_ring_emit(struct radeon_device *rdev,
352 struct radeon_fence *fence)
353{
354 /* Who ever call radeon_fence_emit should call ring_lock and ask
355 * for enough space (today caller are ib schedule and buffer move) */
356 /* Wait until IDLE & CLEAN */
357 radeon_ring_write(rdev, PACKET0(0x1720, 0));
358 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
cafe6609
JG		 359 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
360 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
361 RADEON_HDP_READ_BUFFER_INVALIDATE);
362 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
363 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 364 /* Emit fence sequence & fire IRQ */
365 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
366 radeon_ring_write(rdev, fence->seq);
367 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
368 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
369}
370
771fe6b9
JG		 371int r100_wb_init(struct radeon_device *rdev)
372{
373 int r;
374
375 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 376 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
377 RADEON_GEM_DOMAIN_GTT,
378 &rdev->wb.wb_obj);
771fe6b9 379 if (r) {
4c788679 380 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
771fe6b9
JG		 381 return r;
382 }
4c788679
JG		 383 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
384 if (unlikely(r != 0))
385 return r;
386 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
387 &rdev->wb.gpu_addr);
771fe6b9 388 if (r) {
4c788679
JG		 389 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
390 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9
JG		 391 return r;
392 }
4c788679
JG		 393 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
394 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9 395 if (r) {
4c788679 396 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
771fe6b9
JG		 397 return r;
398 }
399 }
9f022ddf
JG		 400 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
401 WREG32(R_00070C_CP_RB_RPTR_ADDR,
402 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
403 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 404 return 0;
405}
406
9f022ddf
JG		 407void r100_wb_disable(struct radeon_device *rdev)
408{
409 WREG32(R_000770_SCRATCH_UMSK, 0);
410}
411
771fe6b9
JG		 412void r100_wb_fini(struct radeon_device *rdev)
413{
4c788679
JG		 414 int r;
415
9f022ddf 416 r100_wb_disable(rdev);
771fe6b9 417 if (rdev->wb.wb_obj) {
4c788679
JG		 418 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
419 if (unlikely(r != 0)) {
420 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
421 return;
422 }
423 radeon_bo_kunmap(rdev->wb.wb_obj);
424 radeon_bo_unpin(rdev->wb.wb_obj);
425 radeon_bo_unreserve(rdev->wb.wb_obj);
426 radeon_bo_unref(&rdev->wb.wb_obj);
771fe6b9
JG		 427 rdev->wb.wb = NULL;
428 rdev->wb.wb_obj = NULL;
429 }
430}
431
432int r100_copy_blit(struct radeon_device *rdev,
433 uint64_t src_offset,
434 uint64_t dst_offset,
435 unsigned num_pages,
436 struct radeon_fence *fence)
437{
438 uint32_t cur_pages;
439 uint32_t stride_bytes = PAGE_SIZE;
440 uint32_t pitch;
441 uint32_t stride_pixels;
442 unsigned ndw;
443 int num_loops;
444 int r = 0;
445
446 /* radeon limited to 16k stride */
447 stride_bytes &= 0x3fff;
448 /* radeon pitch is /64 */
449 pitch = stride_bytes / 64;
450 stride_pixels = stride_bytes / 4;
451 num_loops = DIV_ROUND_UP(num_pages, 8191);
452
453 /* Ask for enough room for blit + flush + fence */
454 ndw = 64 + (10 * num_loops);
455 r = radeon_ring_lock(rdev, ndw);
456 if (r) {
457 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
458 return -EINVAL;
459 }
460 while (num_pages > 0) {
461 cur_pages = num_pages;
462 if (cur_pages > 8191) {
463 cur_pages = 8191;
464 }
465 num_pages -= cur_pages;
466
467 /* pages are in Y direction - height
468 page width in X direction - width */
469 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
470 radeon_ring_write(rdev,
471 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
472 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
473 RADEON_GMC_SRC_CLIPPING |
474 RADEON_GMC_DST_CLIPPING |
475 RADEON_GMC_BRUSH_NONE |
476 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
477 RADEON_GMC_SRC_DATATYPE_COLOR |
478 RADEON_ROP3_S |
479 RADEON_DP_SRC_SOURCE_MEMORY |
480 RADEON_GMC_CLR_CMP_CNTL_DIS |
481 RADEON_GMC_WR_MSK_DIS);
482 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
483 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
484 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
485 radeon_ring_write(rdev, 0);
486 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
487 radeon_ring_write(rdev, num_pages);
488 radeon_ring_write(rdev, num_pages);
489 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
490 }
491 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
492 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
493 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
494 radeon_ring_write(rdev,
495 RADEON_WAIT_2D_IDLECLEAN |
496 RADEON_WAIT_HOST_IDLECLEAN |
497 RADEON_WAIT_DMA_GUI_IDLE);
498 if (fence) {
499 r = radeon_fence_emit(rdev, fence);
500 }
501 radeon_ring_unlock_commit(rdev);
502 return r;
503}
504
45600232
JG		 505static int r100_cp_wait_for_idle(struct radeon_device *rdev)
506{
507 unsigned i;
508 u32 tmp;
509
510 for (i = 0; i < rdev->usec_timeout; i++) {
511 tmp = RREG32(R_000E40_RBBM_STATUS);
512 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
513 return 0;
514 }
515 udelay(1);
516 }
517 return -1;
518}
519
771fe6b9
JG		 520void r100_ring_start(struct radeon_device *rdev)
521{
522 int r;
523
524 r = radeon_ring_lock(rdev, 2);
525 if (r) {
526 return;
527 }
528 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
529 radeon_ring_write(rdev,
530 RADEON_ISYNC_ANY2D_IDLE3D |
531 RADEON_ISYNC_ANY3D_IDLE2D |
532 RADEON_ISYNC_WAIT_IDLEGUI |
533 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
534 radeon_ring_unlock_commit(rdev);
535}
536
70967ab9
BH		 537
538/* Load the microcode for the CP */
539static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 540{
70967ab9
BH		 541 struct platform_device *pdev;
542 const char *fw_name = NULL;
543 int err;
771fe6b9 544
70967ab9 545 DRM_DEBUG("\n");
771fe6b9 546
70967ab9
BH		 547 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
548 err = IS_ERR(pdev);
549 if (err) {
550 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
551 return -EINVAL;
552 }
771fe6b9
JG		 553 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
554 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
555 (rdev->family == CHIP_RS200)) {
556 DRM_INFO("Loading R100 Microcode\n");
70967ab9 557 fw_name = FIRMWARE_R100;
771fe6b9
JG		 558 } else if ((rdev->family == CHIP_R200) ||
559 (rdev->family == CHIP_RV250) ||
560 (rdev->family == CHIP_RV280) ||
561 (rdev->family == CHIP_RS300)) {
562 DRM_INFO("Loading R200 Microcode\n");
70967ab9 563 fw_name = FIRMWARE_R200;
771fe6b9
JG		 564 } else if ((rdev->family == CHIP_R300) ||
565 (rdev->family == CHIP_R350) ||
566 (rdev->family == CHIP_RV350) ||
567 (rdev->family == CHIP_RV380) ||
568 (rdev->family == CHIP_RS400) ||
569 (rdev->family == CHIP_RS480)) {
570 DRM_INFO("Loading R300 Microcode\n");
70967ab9 571 fw_name = FIRMWARE_R300;
771fe6b9
JG		 572 } else if ((rdev->family == CHIP_R420) ||
573 (rdev->family == CHIP_R423) ||
574 (rdev->family == CHIP_RV410)) {
575 DRM_INFO("Loading R400 Microcode\n");
70967ab9 576 fw_name = FIRMWARE_R420;
771fe6b9
JG		 577 } else if ((rdev->family == CHIP_RS690) ||
578 (rdev->family == CHIP_RS740)) {
579 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 580 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 581 } else if (rdev->family == CHIP_RS600) {
582 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 583 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 584 } else if ((rdev->family == CHIP_RV515) ||
585 (rdev->family == CHIP_R520) ||
586 (rdev->family == CHIP_RV530) ||
587 (rdev->family == CHIP_R580) ||
588 (rdev->family == CHIP_RV560) ||
589 (rdev->family == CHIP_RV570)) {
590 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 591 fw_name = FIRMWARE_R520;
592 }
593
3ce0a23d 594 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 595 platform_device_unregister(pdev);
596 if (err) {
597 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
598 fw_name);
3ce0a23d 599 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 600 printk(KERN_ERR
601 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 602 rdev->me_fw->size, fw_name);
70967ab9 603 err = -EINVAL;
3ce0a23d
JG		 604 release_firmware(rdev->me_fw);
605 rdev->me_fw = NULL;
70967ab9
BH		 606 }
607 return err;
608}
d4550907 609
70967ab9
BH		 610static void r100_cp_load_microcode(struct radeon_device *rdev)
611{
612 const __be32 *fw_data;
613 int i, size;
614
615 if (r100_gui_wait_for_idle(rdev)) {
616 printk(KERN_WARNING "Failed to wait GUI idle while "
617 "programming pipes. Bad things might happen.\n");
618 }
619
3ce0a23d
JG		 620 if (rdev->me_fw) {
621 size = rdev->me_fw->size / 4;
622 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 623 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
624 for (i = 0; i < size; i += 2) {
625 WREG32(RADEON_CP_ME_RAM_DATAH,
626 be32_to_cpup(&fw_data[i]));
627 WREG32(RADEON_CP_ME_RAM_DATAL,
628 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 629 }
630 }
631}
632
633int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
634{
635 unsigned rb_bufsz;
636 unsigned rb_blksz;
637 unsigned max_fetch;
638 unsigned pre_write_timer;
639 unsigned pre_write_limit;
640 unsigned indirect2_start;
641 unsigned indirect1_start;
642 uint32_t tmp;
643 int r;
644
645 if (r100_debugfs_cp_init(rdev)) {
646 DRM_ERROR("Failed to register debugfs file for CP !\n");
647 }
648 /* Reset CP */
649 tmp = RREG32(RADEON_CP_CSQ_STAT);
650 if ((tmp & (1 << 31))) {
651 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
652 WREG32(RADEON_CP_CSQ_MODE, 0);
653 WREG32(RADEON_CP_CSQ_CNTL, 0);
654 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
655 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
656 mdelay(2);
657 WREG32(RADEON_RBBM_SOFT_RESET, 0);
658 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
659 mdelay(2);
660 tmp = RREG32(RADEON_CP_CSQ_STAT);
661 if ((tmp & (1 << 31))) {
662 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
663 }
664 } else {
665 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
666 }
70967ab9 667
3ce0a23d 668 if (!rdev->me_fw) {
70967ab9
BH		 669 r = r100_cp_init_microcode(rdev);
670 if (r) {
671 DRM_ERROR("Failed to load firmware!\n");
672 return r;
673 }
674 }
675
771fe6b9
JG		 676 /* Align ring size */
677 rb_bufsz = drm_order(ring_size / 8);
678 ring_size = (1 << (rb_bufsz + 1)) * 4;
679 r100_cp_load_microcode(rdev);
680 r = radeon_ring_init(rdev, ring_size);
681 if (r) {
682 return r;
683 }
684 /* Each time the cp read 1024 bytes (16 dword/quadword) update
685 * the rptr copy in system ram */
686 rb_blksz = 9;
687 /* cp will read 128bytes at a time (4 dwords) */
688 max_fetch = 1;
689 rdev->cp.align_mask = 16 - 1;
690 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
691 pre_write_timer = 64;
692 /* Force CP_RB_WPTR write if written more than one time before the
693 * delay expire
694 */
695 pre_write_limit = 0;
696 /* Setup the cp cache like this (cache size is 96 dwords) :
697 * RING 0 to 15
698 * INDIRECT1 16 to 79
699 * INDIRECT2 80 to 95
700 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
701 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
702 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
703 * Idea being that most of the gpu cmd will be through indirect1 buffer
704 * so it gets the bigger cache.
705 */
706 indirect2_start = 80;
707 indirect1_start = 16;
708 /* cp setup */
709 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 710 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9
JG		 711 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
712 REG_SET(RADEON_MAX_FETCH, max_fetch) |
713 RADEON_RB_NO_UPDATE);
d6f28938
AD		 714#ifdef __BIG_ENDIAN
715 tmp |= RADEON_BUF_SWAP_32BIT;
716#endif
717 WREG32(RADEON_CP_RB_CNTL, tmp);
718
771fe6b9
JG		 719 /* Set ring address */
720 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
721 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
722 /* Force read & write ptr to 0 */
771fe6b9
JG		 723 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
724 WREG32(RADEON_CP_RB_RPTR_WR, 0);
725 WREG32(RADEON_CP_RB_WPTR, 0);
726 WREG32(RADEON_CP_RB_CNTL, tmp);
727 udelay(10);
728 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
729 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
730 /* Set cp mode to bus mastering & enable cp*/
731 WREG32(RADEON_CP_CSQ_MODE,
732 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
733 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
734 WREG32(0x718, 0);
735 WREG32(0x744, 0x00004D4D);
736 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
737 radeon_ring_start(rdev);
738 r = radeon_ring_test(rdev);
739 if (r) {
740 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
741 return r;
742 }
743 rdev->cp.ready = true;
744 return 0;
745}
746
747void r100_cp_fini(struct radeon_device *rdev)
748{
45600232
JG		 749 if (r100_cp_wait_for_idle(rdev)) {
750 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
751 }
771fe6b9 752 /* Disable ring */
a18d7ea1 753 r100_cp_disable(rdev);
771fe6b9
JG		 754 radeon_ring_fini(rdev);
755 DRM_INFO("radeon: cp finalized\n");
756}
757
758void r100_cp_disable(struct radeon_device *rdev)
759{
760 /* Disable ring */
761 rdev->cp.ready = false;
762 WREG32(RADEON_CP_CSQ_MODE, 0);
763 WREG32(RADEON_CP_CSQ_CNTL, 0);
764 if (r100_gui_wait_for_idle(rdev)) {
765 printk(KERN_WARNING "Failed to wait GUI idle while "
766 "programming pipes. Bad things might happen.\n");
767 }
768}
769
770int r100_cp_reset(struct radeon_device *rdev)
771{
772 uint32_t tmp;
773 bool reinit_cp;
774 int i;
775
776 reinit_cp = rdev->cp.ready;
777 rdev->cp.ready = false;
778 WREG32(RADEON_CP_CSQ_MODE, 0);
779 WREG32(RADEON_CP_CSQ_CNTL, 0);
780 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
781 (void)RREG32(RADEON_RBBM_SOFT_RESET);
782 udelay(200);
783 WREG32(RADEON_RBBM_SOFT_RESET, 0);
784 /* Wait to prevent race in RBBM_STATUS */
785 mdelay(1);
786 for (i = 0; i < rdev->usec_timeout; i++) {
787 tmp = RREG32(RADEON_RBBM_STATUS);
788 if (!(tmp & (1 << 16))) {
789 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
790 tmp);
791 if (reinit_cp) {
792 return r100_cp_init(rdev, rdev->cp.ring_size);
793 }
794 return 0;
795 }
796 DRM_UDELAY(1);
797 }
798 tmp = RREG32(RADEON_RBBM_STATUS);
799 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
800 return -1;
801}
802
3ce0a23d
JG		 803void r100_cp_commit(struct radeon_device *rdev)
804{
805 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
806 (void)RREG32(RADEON_CP_RB_WPTR);
807}
808
771fe6b9
JG		 809
810/*
811 * CS functions
812 */
813int r100_cs_parse_packet0(struct radeon_cs_parser *p,
814 struct radeon_cs_packet *pkt,
068a117c 815 const unsigned *auth, unsigned n,
771fe6b9
JG		 816 radeon_packet0_check_t check)
817{
818 unsigned reg;
819 unsigned i, j, m;
820 unsigned idx;
821 int r;
822
823 idx = pkt->idx + 1;
824 reg = pkt->reg;
068a117c
JG		 825 /* Check that register fall into register range
826 * determined by the number of entry (n) in the
827 * safe register bitmap.
828 */
771fe6b9
JG		 829 if (pkt->one_reg_wr) {
830 if ((reg >> 7) > n) {
831 return -EINVAL;
832 }
833 } else {
834 if (((reg + (pkt->count << 2)) >> 7) > n) {
835 return -EINVAL;
836 }
837 }
838 for (i = 0; i <= pkt->count; i++, idx++) {
839 j = (reg >> 7);
840 m = 1 << ((reg >> 2) & 31);
841 if (auth[j] & m) {
842 r = check(p, pkt, idx, reg);
843 if (r) {
844 return r;
845 }
846 }
847 if (pkt->one_reg_wr) {
848 if (!(auth[j] & m)) {
849 break;
850 }
851 } else {
852 reg += 4;
853 }
854 }
855 return 0;
856}
857
771fe6b9
JG		 858void r100_cs_dump_packet(struct radeon_cs_parser *p,
859 struct radeon_cs_packet *pkt)
860{
771fe6b9
JG		 861 volatile uint32_t *ib;
862 unsigned i;
863 unsigned idx;
864
865 ib = p->ib->ptr;
771fe6b9
JG		 866 idx = pkt->idx;
867 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
868 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
869 }
870}
871
872/**
873 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
874 * @parser: parser structure holding parsing context.
875 * @pkt: where to store packet informations
876 *
877 * Assume that chunk_ib_index is properly set. Will return -EINVAL
878 * if packet is bigger than remaining ib size. or if packets is unknown.
879 **/
880int r100_cs_packet_parse(struct radeon_cs_parser *p,
881 struct radeon_cs_packet *pkt,
882 unsigned idx)
883{
884 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 885 uint32_t header;
771fe6b9
JG		 886
887 if (idx >= ib_chunk->length_dw) {
888 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
889 idx, ib_chunk->length_dw);
890 return -EINVAL;
891 }
513bcb46 892 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 893 pkt->idx = idx;
894 pkt->type = CP_PACKET_GET_TYPE(header);
895 pkt->count = CP_PACKET_GET_COUNT(header);
896 switch (pkt->type) {
897 case PACKET_TYPE0:
898 pkt->reg = CP_PACKET0_GET_REG(header);
899 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
900 break;
901 case PACKET_TYPE3:
902 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
903 break;
904 case PACKET_TYPE2:
905 pkt->count = -1;
906 break;
907 default:
908 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
909 return -EINVAL;
910 }
911 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
912 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
913 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
914 return -EINVAL;
915 }
916 return 0;
917}
918
531369e6
DA		 919/**
920 * r100_cs_packet_next_vline() - parse userspace VLINE packet
921 * @parser: parser structure holding parsing context.
922 *
923 * Userspace sends a special sequence for VLINE waits.
924 * PACKET0 - VLINE_START_END + value
925 * PACKET0 - WAIT_UNTIL +_value
926 * RELOC (P3) - crtc_id in reloc.
927 *
928 * This function parses this and relocates the VLINE START END
929 * and WAIT UNTIL packets to the correct crtc.
930 * It also detects a switched off crtc and nulls out the
931 * wait in that case.
932 */
933int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
934{
531369e6
DA		 935 struct drm_mode_object *obj;
936 struct drm_crtc *crtc;
937 struct radeon_crtc *radeon_crtc;
938 struct radeon_cs_packet p3reloc, waitreloc;
939 int crtc_id;
940 int r;
941 uint32_t header, h_idx, reg;
513bcb46 942 volatile uint32_t *ib;
531369e6 943
513bcb46 944 ib = p->ib->ptr;
531369e6
DA		 945
946 /* parse the wait until */
947 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
948 if (r)
949 return r;
950
951 /* check its a wait until and only 1 count */
952 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
953 waitreloc.count != 0) {
954 DRM_ERROR("vline wait had illegal wait until segment\n");
955 r = -EINVAL;
956 return r;
957 }
958
513bcb46 959 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 960 DRM_ERROR("vline wait had illegal wait until\n");
961 r = -EINVAL;
962 return r;
963 }
964
965 /* jump over the NOP */
90ebd065 966 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 967 if (r)
968 return r;
969
970 h_idx = p->idx - 2;
90ebd065
AD		 971 p->idx += waitreloc.count + 2;
972 p->idx += p3reloc.count + 2;
531369e6 973
513bcb46
DA		 974 header = radeon_get_ib_value(p, h_idx);
975 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 976 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 977 mutex_lock(&p->rdev->ddev->mode_config.mutex);
978 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
979 if (!obj) {
980 DRM_ERROR("cannot find crtc %d\n", crtc_id);
981 r = -EINVAL;
982 goto out;
983 }
984 crtc = obj_to_crtc(obj);
985 radeon_crtc = to_radeon_crtc(crtc);
986 crtc_id = radeon_crtc->crtc_id;
987
988 if (!crtc->enabled) {
989 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 990 ib[h_idx + 2] = PACKET2(0);
991 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 992 } else if (crtc_id == 1) {
993 switch (reg) {
994 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 995 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 996 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
997 break;
998 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 999 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1000 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1001 break;
1002 default:
1003 DRM_ERROR("unknown crtc reloc\n");
1004 r = -EINVAL;
1005 goto out;
1006 }
513bcb46
DA		 1007 ib[h_idx] = header;
1008 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1009 }
1010out:
1011 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1012 return r;
1013}
1014
771fe6b9
JG		 1015/**
1016 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1017 * @parser: parser structure holding parsing context.
1018 * @data: pointer to relocation data
1019 * @offset_start: starting offset
1020 * @offset_mask: offset mask (to align start offset on)
1021 * @reloc: reloc informations
1022 *
1023 * Check next packet is relocation packet3, do bo validation and compute
1024 * GPU offset using the provided start.
1025 **/
1026int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1027 struct radeon_cs_reloc **cs_reloc)
1028{
771fe6b9
JG		 1029 struct radeon_cs_chunk *relocs_chunk;
1030 struct radeon_cs_packet p3reloc;
1031 unsigned idx;
1032 int r;
1033
1034 if (p->chunk_relocs_idx == -1) {
1035 DRM_ERROR("No relocation chunk !\n");
1036 return -EINVAL;
1037 }
1038 *cs_reloc = NULL;
771fe6b9
JG		 1039 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1040 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1041 if (r) {
1042 return r;
1043 }
1044 p->idx += p3reloc.count + 2;
1045 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1046 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1047 p3reloc.idx);
1048 r100_cs_dump_packet(p, &p3reloc);
1049 return -EINVAL;
1050 }
513bcb46 1051 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1052 if (idx >= relocs_chunk->length_dw) {
1053 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1054 idx, relocs_chunk->length_dw);
1055 r100_cs_dump_packet(p, &p3reloc);
1056 return -EINVAL;
1057 }
1058 /* FIXME: we assume reloc size is 4 dwords */
1059 *cs_reloc = p->relocs_ptr[(idx / 4)];
1060 return 0;
1061}
1062
551ebd83
DA		 1063static int r100_get_vtx_size(uint32_t vtx_fmt)
1064{
1065 int vtx_size;
1066 vtx_size = 2;
1067 /* ordered according to bits in spec */
1068 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1069 vtx_size++;
1070 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1071 vtx_size += 3;
1072 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1073 vtx_size++;
1074 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1075 vtx_size++;
1076 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1077 vtx_size += 3;
1078 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1079 vtx_size++;
1080 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1081 vtx_size++;
1082 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1083 vtx_size += 2;
1084 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1085 vtx_size += 2;
1086 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1087 vtx_size++;
1088 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1089 vtx_size += 2;
1090 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1091 vtx_size++;
1092 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1093 vtx_size += 2;
1094 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1095 vtx_size++;
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1097 vtx_size++;
1098 /* blend weight */
1099 if (vtx_fmt & (0x7 << 15))
1100 vtx_size += (vtx_fmt >> 15) & 0x7;
1101 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1102 vtx_size += 3;
1103 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1104 vtx_size += 2;
1105 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1106 vtx_size++;
1107 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1108 vtx_size++;
1109 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1110 vtx_size++;
1111 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1112 vtx_size++;
1113 return vtx_size;
1114}
1115
771fe6b9 1116static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1117 struct radeon_cs_packet *pkt,
1118 unsigned idx, unsigned reg)
771fe6b9 1119{
771fe6b9 1120 struct radeon_cs_reloc *reloc;
551ebd83 1121 struct r100_cs_track *track;
771fe6b9
JG		 1122 volatile uint32_t *ib;
1123 uint32_t tmp;
771fe6b9 1124 int r;
551ebd83 1125 int i, face;
e024e110 1126 u32 tile_flags = 0;
513bcb46 1127 u32 idx_value;
771fe6b9
JG		 1128
1129 ib = p->ib->ptr;
551ebd83
DA		 1130 track = (struct r100_cs_track *)p->track;
1131
513bcb46
DA		 1132 idx_value = radeon_get_ib_value(p, idx);
1133
551ebd83
DA		 1134 switch (reg) {
1135 case RADEON_CRTC_GUI_TRIG_VLINE:
1136 r = r100_cs_packet_parse_vline(p);
1137 if (r) {
1138 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1139 idx, reg);
1140 r100_cs_dump_packet(p, pkt);
1141 return r;
1142 }
1143 break;
771fe6b9
JG		 1144 /* FIXME: only allow PACKET3 blit? easier to check for out of
1145 * range access */
551ebd83
DA		 1146 case RADEON_DST_PITCH_OFFSET:
1147 case RADEON_SRC_PITCH_OFFSET:
1148 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1149 if (r)
1150 return r;
1151 break;
1152 case RADEON_RB3D_DEPTHOFFSET:
1153 r = r100_cs_packet_next_reloc(p, &reloc);
1154 if (r) {
1155 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1156 idx, reg);
1157 r100_cs_dump_packet(p, pkt);
1158 return r;
1159 }
1160 track->zb.robj = reloc->robj;
513bcb46
DA		 1161 track->zb.offset = idx_value;
1162 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1163 break;
1164 case RADEON_RB3D_COLOROFFSET:
1165 r = r100_cs_packet_next_reloc(p, &reloc);
1166 if (r) {
1167 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1168 idx, reg);
1169 r100_cs_dump_packet(p, pkt);
1170 return r;
1171 }
1172 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1173 track->cb[0].offset = idx_value;
1174 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1175 break;
1176 case RADEON_PP_TXOFFSET_0:
1177 case RADEON_PP_TXOFFSET_1:
1178 case RADEON_PP_TXOFFSET_2:
1179 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1180 r = r100_cs_packet_next_reloc(p, &reloc);
1181 if (r) {
1182 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1183 idx, reg);
1184 r100_cs_dump_packet(p, pkt);
1185 return r;
1186 }
513bcb46 1187 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1188 track->textures[i].robj = reloc->robj;
1189 break;
1190 case RADEON_PP_CUBIC_OFFSET_T0_0:
1191 case RADEON_PP_CUBIC_OFFSET_T0_1:
1192 case RADEON_PP_CUBIC_OFFSET_T0_2:
1193 case RADEON_PP_CUBIC_OFFSET_T0_3:
1194 case RADEON_PP_CUBIC_OFFSET_T0_4:
1195 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1196 r = r100_cs_packet_next_reloc(p, &reloc);
1197 if (r) {
1198 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1199 idx, reg);
1200 r100_cs_dump_packet(p, pkt);
1201 return r;
1202 }
513bcb46
DA		 1203 track->textures[0].cube_info[i].offset = idx_value;
1204 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1205 track->textures[0].cube_info[i].robj = reloc->robj;
1206 break;
1207 case RADEON_PP_CUBIC_OFFSET_T1_0:
1208 case RADEON_PP_CUBIC_OFFSET_T1_1:
1209 case RADEON_PP_CUBIC_OFFSET_T1_2:
1210 case RADEON_PP_CUBIC_OFFSET_T1_3:
1211 case RADEON_PP_CUBIC_OFFSET_T1_4:
1212 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1213 r = r100_cs_packet_next_reloc(p, &reloc);
1214 if (r) {
1215 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1216 idx, reg);
1217 r100_cs_dump_packet(p, pkt);
1218 return r;
1219 }
513bcb46
DA		 1220 track->textures[1].cube_info[i].offset = idx_value;
1221 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1222 track->textures[1].cube_info[i].robj = reloc->robj;
1223 break;
1224 case RADEON_PP_CUBIC_OFFSET_T2_0:
1225 case RADEON_PP_CUBIC_OFFSET_T2_1:
1226 case RADEON_PP_CUBIC_OFFSET_T2_2:
1227 case RADEON_PP_CUBIC_OFFSET_T2_3:
1228 case RADEON_PP_CUBIC_OFFSET_T2_4:
1229 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1230 r = r100_cs_packet_next_reloc(p, &reloc);
1231 if (r) {
1232 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1233 idx, reg);
1234 r100_cs_dump_packet(p, pkt);
1235 return r;
1236 }
513bcb46
DA		 1237 track->textures[2].cube_info[i].offset = idx_value;
1238 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1239 track->textures[2].cube_info[i].robj = reloc->robj;
1240 break;
1241 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1242 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1243 break;
1244 case RADEON_RB3D_COLORPITCH:
1245 r = r100_cs_packet_next_reloc(p, &reloc);
1246 if (r) {
1247 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1248 idx, reg);
1249 r100_cs_dump_packet(p, pkt);
1250 return r;
1251 }
e024e110 1252
551ebd83
DA		 1253 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1254 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1255 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1256 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1257
513bcb46 1258 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1259 tmp |= tile_flags;
1260 ib[idx] = tmp;
e024e110 1261
513bcb46 1262 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1263 break;
1264 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1265 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1266 break;
1267 case RADEON_RB3D_CNTL:
513bcb46 1268 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1269 case 7:
1270 case 8:
1271 case 9:
1272 case 11:
1273 case 12:
1274 track->cb[0].cpp = 1;
e024e110 1275 break;
551ebd83
DA		 1276 case 3:
1277 case 4:
1278 case 15:
1279 track->cb[0].cpp = 2;
1280 break;
1281 case 6:
1282 track->cb[0].cpp = 4;
1283 break;
1284 default:
1285 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1286 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1287 return -EINVAL;
1288 }
513bcb46 1289 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1290 break;
1291 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1292 switch (idx_value & 0xf) {
551ebd83
DA		 1293 case 0:
1294 track->zb.cpp = 2;
1295 break;
1296 case 2:
1297 case 3:
1298 case 4:
1299 case 5:
1300 case 9:
1301 case 11:
1302 track->zb.cpp = 4;
17782d99 1303 break;
771fe6b9 1304 default:
771fe6b9
JG		 1305 break;
1306 }
551ebd83
DA		 1307 break;
1308 case RADEON_RB3D_ZPASS_ADDR:
1309 r = r100_cs_packet_next_reloc(p, &reloc);
1310 if (r) {
1311 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1312 idx, reg);
1313 r100_cs_dump_packet(p, pkt);
1314 return r;
1315 }
513bcb46 1316 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1317 break;
1318 case RADEON_PP_CNTL:
1319 {
513bcb46 1320 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1321 for (i = 0; i < track->num_texture; i++)
1322 track->textures[i].enabled = !!(temp & (1 << i));
1323 }
1324 break;
1325 case RADEON_SE_VF_CNTL:
513bcb46 1326 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1327 break;
1328 case RADEON_SE_VTX_FMT:
513bcb46 1329 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1330 break;
1331 case RADEON_PP_TEX_SIZE_0:
1332 case RADEON_PP_TEX_SIZE_1:
1333 case RADEON_PP_TEX_SIZE_2:
1334 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1335 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1336 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1337 break;
1338 case RADEON_PP_TEX_PITCH_0:
1339 case RADEON_PP_TEX_PITCH_1:
1340 case RADEON_PP_TEX_PITCH_2:
1341 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1342 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1343 break;
1344 case RADEON_PP_TXFILTER_0:
1345 case RADEON_PP_TXFILTER_1:
1346 case RADEON_PP_TXFILTER_2:
1347 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1348 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1349 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1350 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1351 if (tmp == 2 || tmp == 6)
1352 track->textures[i].roundup_w = false;
513bcb46 1353 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1354 if (tmp == 2 || tmp == 6)
1355 track->textures[i].roundup_h = false;
1356 break;
1357 case RADEON_PP_TXFORMAT_0:
1358 case RADEON_PP_TXFORMAT_1:
1359 case RADEON_PP_TXFORMAT_2:
1360 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1361 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1362 track->textures[i].use_pitch = 1;
1363 } else {
1364 track->textures[i].use_pitch = 0;
513bcb46
DA		 1365 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1366 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1367 }
513bcb46 1368 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1369 track->textures[i].tex_coord_type = 2;
513bcb46 1370 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1371 case RADEON_TXFORMAT_I8:
1372 case RADEON_TXFORMAT_RGB332:
1373 case RADEON_TXFORMAT_Y8:
1374 track->textures[i].cpp = 1;
1375 break;
1376 case RADEON_TXFORMAT_AI88:
1377 case RADEON_TXFORMAT_ARGB1555:
1378 case RADEON_TXFORMAT_RGB565:
1379 case RADEON_TXFORMAT_ARGB4444:
1380 case RADEON_TXFORMAT_VYUY422:
1381 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1382 case RADEON_TXFORMAT_SHADOW16:
1383 case RADEON_TXFORMAT_LDUDV655:
1384 case RADEON_TXFORMAT_DUDV88:
1385 track->textures[i].cpp = 2;
771fe6b9 1386 break;
551ebd83
DA		 1387 case RADEON_TXFORMAT_ARGB8888:
1388 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1389 case RADEON_TXFORMAT_SHADOW32:
1390 case RADEON_TXFORMAT_LDUDUV8888:
1391 track->textures[i].cpp = 4;
1392 break;
d785d78b
DA		 1393 case RADEON_TXFORMAT_DXT1:
1394 track->textures[i].cpp = 1;
1395 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1396 break;
1397 case RADEON_TXFORMAT_DXT23:
1398 case RADEON_TXFORMAT_DXT45:
1399 track->textures[i].cpp = 1;
1400 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1401 break;
551ebd83 1402 }
513bcb46
DA		 1403 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1404 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1405 break;
1406 case RADEON_PP_CUBIC_FACES_0:
1407 case RADEON_PP_CUBIC_FACES_1:
1408 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1409 tmp = idx_value;
551ebd83
DA		 1410 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1411 for (face = 0; face < 4; face++) {
1412 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1413 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1414 }
551ebd83
DA		 1415 break;
1416 default:
1417 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1418 reg, idx);
1419 return -EINVAL;
771fe6b9
JG		 1420 }
1421 return 0;
1422}
1423
068a117c
JG		 1424int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1425 struct radeon_cs_packet *pkt,
4c788679 1426 struct radeon_bo *robj)
068a117c 1427{
068a117c 1428 unsigned idx;
513bcb46 1429 u32 value;
068a117c 1430 idx = pkt->idx + 1;
513bcb46 1431 value = radeon_get_ib_value(p, idx + 2);
4c788679 1432 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1433 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1434 "(need %u have %lu) !\n",
513bcb46 1435 value + 1,
4c788679 1436 radeon_bo_size(robj));
068a117c
JG		 1437 return -EINVAL;
1438 }
1439 return 0;
1440}
1441
771fe6b9
JG		 1442static int r100_packet3_check(struct radeon_cs_parser *p,
1443 struct radeon_cs_packet *pkt)
1444{
771fe6b9 1445 struct radeon_cs_reloc *reloc;
551ebd83 1446 struct r100_cs_track *track;
771fe6b9 1447 unsigned idx;
771fe6b9
JG		 1448 volatile uint32_t *ib;
1449 int r;
1450
1451 ib = p->ib->ptr;
771fe6b9 1452 idx = pkt->idx + 1;
551ebd83 1453 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1454 switch (pkt->opcode) {
1455 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1456 r = r100_packet3_load_vbpntr(p, pkt, idx);
1457 if (r)
1458 return r;
771fe6b9
JG		 1459 break;
1460 case PACKET3_INDX_BUFFER:
1461 r = r100_cs_packet_next_reloc(p, &reloc);
1462 if (r) {
1463 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1464 r100_cs_dump_packet(p, pkt);
1465 return r;
1466 }
513bcb46 1467 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1468 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1469 if (r) {
1470 return r;
1471 }
771fe6b9
JG		 1472 break;
1473 case 0x23:
771fe6b9
JG		 1474 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1475 r = r100_cs_packet_next_reloc(p, &reloc);
1476 if (r) {
1477 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1478 r100_cs_dump_packet(p, pkt);
1479 return r;
1480 }
513bcb46 1481 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1482 track->num_arrays = 1;
513bcb46 1483 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1484
1485 track->arrays[0].robj = reloc->robj;
1486 track->arrays[0].esize = track->vtx_size;
1487
513bcb46 1488 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1489
513bcb46 1490 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1491 track->immd_dwords = pkt->count - 1;
1492 r = r100_cs_track_check(p->rdev, track);
1493 if (r)
1494 return r;
771fe6b9
JG		 1495 break;
1496 case PACKET3_3D_DRAW_IMMD:
513bcb46 1497 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1498 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1499 return -EINVAL;
1500 }
513bcb46 1501 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1502 track->immd_dwords = pkt->count - 1;
1503 r = r100_cs_track_check(p->rdev, track);
1504 if (r)
1505 return r;
1506 break;
771fe6b9
JG		 1507 /* triggers drawing using in-packet vertex data */
1508 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1509 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1510 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1511 return -EINVAL;
1512 }
513bcb46 1513 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1514 track->immd_dwords = pkt->count;
1515 r = r100_cs_track_check(p->rdev, track);
1516 if (r)
1517 return r;
1518 break;
771fe6b9
JG		 1519 /* triggers drawing using in-packet vertex data */
1520 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1521 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1522 r = r100_cs_track_check(p->rdev, track);
1523 if (r)
1524 return r;
1525 break;
771fe6b9
JG		 1526 /* triggers drawing of vertex buffers setup elsewhere */
1527 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1528 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1529 r = r100_cs_track_check(p->rdev, track);
1530 if (r)
1531 return r;
1532 break;
771fe6b9
JG		 1533 /* triggers drawing using indices to vertex buffer */
1534 case PACKET3_3D_DRAW_VBUF:
513bcb46 1535 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1536 r = r100_cs_track_check(p->rdev, track);
1537 if (r)
1538 return r;
1539 break;
771fe6b9
JG		 1540 /* triggers drawing of vertex buffers setup elsewhere */
1541 case PACKET3_3D_DRAW_INDX:
513bcb46 1542 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1543 r = r100_cs_track_check(p->rdev, track);
1544 if (r)
1545 return r;
1546 break;
771fe6b9
JG		 1547 /* triggers drawing using indices to vertex buffer */
1548 case PACKET3_NOP:
1549 break;
1550 default:
1551 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1552 return -EINVAL;
1553 }
1554 return 0;
1555}
1556
1557int r100_cs_parse(struct radeon_cs_parser *p)
1558{
1559 struct radeon_cs_packet pkt;
9f022ddf 1560 struct r100_cs_track *track;
771fe6b9
JG		 1561 int r;
1562
9f022ddf
JG		 1563 track = kzalloc(sizeof(*track), GFP_KERNEL);
1564 r100_cs_track_clear(p->rdev, track);
1565 p->track = track;
771fe6b9
JG		 1566 do {
1567 r = r100_cs_packet_parse(p, &pkt, p->idx);
1568 if (r) {
1569 return r;
1570 }
1571 p->idx += pkt.count + 2;
1572 switch (pkt.type) {
068a117c 1573 case PACKET_TYPE0:
551ebd83
DA		 1574 if (p->rdev->family >= CHIP_R200)
1575 r = r100_cs_parse_packet0(p, &pkt,
1576 p->rdev->config.r100.reg_safe_bm,
1577 p->rdev->config.r100.reg_safe_bm_size,
1578 &r200_packet0_check);
1579 else
1580 r = r100_cs_parse_packet0(p, &pkt,
1581 p->rdev->config.r100.reg_safe_bm,
1582 p->rdev->config.r100.reg_safe_bm_size,
1583 &r100_packet0_check);
068a117c
JG		 1584 break;
1585 case PACKET_TYPE2:
1586 break;
1587 case PACKET_TYPE3:
1588 r = r100_packet3_check(p, &pkt);
1589 break;
1590 default:
1591 DRM_ERROR("Unknown packet type %d !\n",
1592 pkt.type);
1593 return -EINVAL;
771fe6b9
JG		 1594 }
1595 if (r) {
1596 return r;
1597 }
1598 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1599 return 0;
1600}
1601
1602
1603/*
1604 * Global GPU functions
1605 */
1606void r100_errata(struct radeon_device *rdev)
1607{
1608 rdev->pll_errata = 0;
1609
1610 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1611 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1612 }
1613
1614 if (rdev->family == CHIP_RV100 ||
1615 rdev->family == CHIP_RS100 ||
1616 rdev->family == CHIP_RS200) {
1617 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1618 }
1619}
1620
1621/* Wait for vertical sync on primary CRTC */
1622void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1623{
1624 uint32_t crtc_gen_cntl, tmp;
1625 int i;
1626
1627 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1628 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1629 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1630 return;
1631 }
1632 /* Clear the CRTC_VBLANK_SAVE bit */
1633 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1634 for (i = 0; i < rdev->usec_timeout; i++) {
1635 tmp = RREG32(RADEON_CRTC_STATUS);
1636 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1637 return;
1638 }
1639 DRM_UDELAY(1);
1640 }
1641}
1642
1643/* Wait for vertical sync on secondary CRTC */
1644void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1645{
1646 uint32_t crtc2_gen_cntl, tmp;
1647 int i;
1648
1649 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1650 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1651 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1652 return;
1653
1654 /* Clear the CRTC_VBLANK_SAVE bit */
1655 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1656 for (i = 0; i < rdev->usec_timeout; i++) {
1657 tmp = RREG32(RADEON_CRTC2_STATUS);
1658 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1659 return;
1660 }
1661 DRM_UDELAY(1);
1662 }
1663}
1664
1665int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1666{
1667 unsigned i;
1668 uint32_t tmp;
1669
1670 for (i = 0; i < rdev->usec_timeout; i++) {
1671 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1672 if (tmp >= n) {
1673 return 0;
1674 }
1675 DRM_UDELAY(1);
1676 }
1677 return -1;
1678}
1679
1680int r100_gui_wait_for_idle(struct radeon_device *rdev)
1681{
1682 unsigned i;
1683 uint32_t tmp;
1684
1685 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1686 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1687 " Bad things might happen.\n");
1688 }
1689 for (i = 0; i < rdev->usec_timeout; i++) {
1690 tmp = RREG32(RADEON_RBBM_STATUS);
1691 if (!(tmp & (1 << 31))) {
1692 return 0;
1693 }
1694 DRM_UDELAY(1);
1695 }
1696 return -1;
1697}
1698
1699int r100_mc_wait_for_idle(struct radeon_device *rdev)
1700{
1701 unsigned i;
1702 uint32_t tmp;
1703
1704 for (i = 0; i < rdev->usec_timeout; i++) {
1705 /* read MC_STATUS */
1706 tmp = RREG32(0x0150);
1707 if (tmp & (1 << 2)) {
1708 return 0;
1709 }
1710 DRM_UDELAY(1);
1711 }
1712 return -1;
1713}
1714
1715void r100_gpu_init(struct radeon_device *rdev)
1716{
1717 /* TODO: anythings to do here ? pipes ? */
1718 r100_hdp_reset(rdev);
1719}
1720
1721void r100_hdp_reset(struct radeon_device *rdev)
1722{
1723 uint32_t tmp;
1724
1725 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1726 tmp |= (7 << 28);
1727 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1728 (void)RREG32(RADEON_HOST_PATH_CNTL);
1729 udelay(200);
1730 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1731 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1732 (void)RREG32(RADEON_HOST_PATH_CNTL);
1733}
1734
1735int r100_rb2d_reset(struct radeon_device *rdev)
1736{
1737 uint32_t tmp;
1738 int i;
1739
1740 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1741 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1742 udelay(200);
1743 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1744 /* Wait to prevent race in RBBM_STATUS */
1745 mdelay(1);
1746 for (i = 0; i < rdev->usec_timeout; i++) {
1747 tmp = RREG32(RADEON_RBBM_STATUS);
1748 if (!(tmp & (1 << 26))) {
1749 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1750 tmp);
1751 return 0;
1752 }
1753 DRM_UDELAY(1);
1754 }
1755 tmp = RREG32(RADEON_RBBM_STATUS);
1756 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1757 return -1;
1758}
1759
1760int r100_gpu_reset(struct radeon_device *rdev)
1761{
1762 uint32_t status;
1763
1764 /* reset order likely matter */
1765 status = RREG32(RADEON_RBBM_STATUS);
1766 /* reset HDP */
1767 r100_hdp_reset(rdev);
1768 /* reset rb2d */
1769 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1770 r100_rb2d_reset(rdev);
1771 }
1772 /* TODO: reset 3D engine */
1773 /* reset CP */
1774 status = RREG32(RADEON_RBBM_STATUS);
1775 if (status & (1 << 16)) {
1776 r100_cp_reset(rdev);
1777 }
1778 /* Check if GPU is idle */
1779 status = RREG32(RADEON_RBBM_STATUS);
1780 if (status & (1 << 31)) {
1781 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1782 return -1;
1783 }
1784 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1785 return 0;
1786}
1787
92cde00c
AD		 1788void r100_set_common_regs(struct radeon_device *rdev)
1789{
1790 /* set these so they don't interfere with anything */
1791 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1792 WREG32(RADEON_SUBPIC_CNTL, 0);
1793 WREG32(RADEON_VIPH_CONTROL, 0);
1794 WREG32(RADEON_I2C_CNTL_1, 0);
1795 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1796 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1797 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1798}
771fe6b9
JG		 1799
1800/*
1801 * VRAM info
1802 */
1803static void r100_vram_get_type(struct radeon_device *rdev)
1804{
1805 uint32_t tmp;
1806
1807 rdev->mc.vram_is_ddr = false;
1808 if (rdev->flags & RADEON_IS_IGP)
1809 rdev->mc.vram_is_ddr = true;
1810 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1811 rdev->mc.vram_is_ddr = true;
1812 if ((rdev->family == CHIP_RV100) ||
1813 (rdev->family == CHIP_RS100) ||
1814 (rdev->family == CHIP_RS200)) {
1815 tmp = RREG32(RADEON_MEM_CNTL);
1816 if (tmp & RV100_HALF_MODE) {
1817 rdev->mc.vram_width = 32;
1818 } else {
1819 rdev->mc.vram_width = 64;
1820 }
1821 if (rdev->flags & RADEON_SINGLE_CRTC) {
1822 rdev->mc.vram_width /= 4;
1823 rdev->mc.vram_is_ddr = true;
1824 }
1825 } else if (rdev->family <= CHIP_RV280) {
1826 tmp = RREG32(RADEON_MEM_CNTL);
1827 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1828 rdev->mc.vram_width = 128;
1829 } else {
1830 rdev->mc.vram_width = 64;
1831 }
1832 } else {
1833 /* newer IGPs */
1834 rdev->mc.vram_width = 128;
1835 }
1836}
1837
2a0f8918 1838static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1839{
2a0f8918
DA		 1840 u32 aper_size;
1841 u8 byte;
1842
1843 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1844
1845 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1846 * that is has the 2nd generation multifunction PCI interface
1847 */
1848 if (rdev->family == CHIP_RV280 ||
1849 rdev->family >= CHIP_RV350) {
1850 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1851 ~RADEON_HDP_APER_CNTL);
1852 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1853 return aper_size * 2;
1854 }
1855
1856 /* Older cards have all sorts of funny issues to deal with. First
1857 * check if it's a multifunction card by reading the PCI config
1858 * header type... Limit those to one aperture size
1859 */
1860 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1861 if (byte & 0x80) {
1862 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1863 DRM_INFO("Limiting VRAM to one aperture\n");
1864 return aper_size;
1865 }
1866
1867 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1868 * have set it up. We don't write this as it's broken on some ASICs but
1869 * we expect the BIOS to have done the right thing (might be too optimistic...)
1870 */
1871 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1872 return aper_size * 2;
1873 return aper_size;
1874}
1875
1876void r100_vram_init_sizes(struct radeon_device *rdev)
1877{
1878 u64 config_aper_size;
1879 u32 accessible;
1880
1881 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1882
1883 if (rdev->flags & RADEON_IS_IGP) {
1884 uint32_t tom;
1885 /* read NB_TOM to get the amount of ram stolen for the GPU */
1886 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1887 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
3e43d821
DA		 1888 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1889 rdev->mc.vram_location = (tom & 0xffff) << 16;
7a50f01a
DA		 1890 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1891 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1892 } else {
7a50f01a 1893 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1894 /* Some production boards of m6 will report 0
1895 * if it's 8 MB
1896 */
7a50f01a
DA		 1897 if (rdev->mc.real_vram_size == 0) {
1898 rdev->mc.real_vram_size = 8192 * 1024;
1899 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1900 }
3e43d821
DA		 1901 /* let driver place VRAM */
1902 rdev->mc.vram_location = 0xFFFFFFFFUL;
2a0f8918
DA		 1903 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1904 * Novell bug 204882 + along with lots of ubuntu ones */
7a50f01a
DA		 1905 if (config_aper_size > rdev->mc.real_vram_size)
1906 rdev->mc.mc_vram_size = config_aper_size;
1907 else
1908 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 1909 }
1910
2a0f8918
DA		 1911 /* work out accessible VRAM */
1912 accessible = r100_get_accessible_vram(rdev);
1913
771fe6b9
JG		 1914 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1915 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2a0f8918
DA		 1916
1917 if (accessible > rdev->mc.aper_size)
1918 accessible = rdev->mc.aper_size;
1919
7a50f01a
DA		 1920 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1921 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1922
1923 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1924 rdev->mc.real_vram_size = rdev->mc.aper_size;
2a0f8918
DA		 1925}
1926
28d52043
DA		 1927void r100_vga_set_state(struct radeon_device *rdev, bool state)
1928{
1929 uint32_t temp;
1930
1931 temp = RREG32(RADEON_CONFIG_CNTL);
1932 if (state == false) {
1933 temp &= ~(1<<8);
1934 temp |= (1<<9);
1935 } else {
1936 temp &= ~(1<<9);
1937 }
1938 WREG32(RADEON_CONFIG_CNTL, temp);
1939}
1940
2a0f8918
DA		 1941void r100_vram_info(struct radeon_device *rdev)
1942{
1943 r100_vram_get_type(rdev);
1944
1945 r100_vram_init_sizes(rdev);
771fe6b9
JG		 1946}
1947
1948
1949/*
1950 * Indirect registers accessor
1951 */
1952void r100_pll_errata_after_index(struct radeon_device *rdev)
1953{
1954 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1955 return;
1956 }
1957 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1958 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1959}
1960
1961static void r100_pll_errata_after_data(struct radeon_device *rdev)
1962{
1963 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1964 * or the chip could hang on a subsequent access
1965 */
1966 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1967 udelay(5000);
1968 }
1969
1970 /* This function is required to workaround a hardware bug in some (all?)
1971 * revisions of the R300. This workaround should be called after every
1972 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1973 * may not be correct.
1974 */
1975 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1976 uint32_t save, tmp;
1977
1978 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1979 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1980 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1981 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1982 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1983 }
1984}
1985
1986uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1987{
1988 uint32_t data;
1989
1990 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1991 r100_pll_errata_after_index(rdev);
1992 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1993 r100_pll_errata_after_data(rdev);
1994 return data;
1995}
1996
1997void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1998{
1999 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2000 r100_pll_errata_after_index(rdev);
2001 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2002 r100_pll_errata_after_data(rdev);
2003}
2004
d4550907 2005void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2006{
551ebd83
DA		 2007 if (ASIC_IS_RN50(rdev)) {
2008 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2009 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2010 } else if (rdev->family < CHIP_R200) {
2011 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2012 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2013 } else {
d4550907 2014 r200_set_safe_registers(rdev);
551ebd83 2015 }
068a117c
JG		 2016}
2017
771fe6b9
JG		 2018/*
2019 * Debugfs info
2020 */
2021#if defined(CONFIG_DEBUG_FS)
2022static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2023{
2024 struct drm_info_node *node = (struct drm_info_node *) m->private;
2025 struct drm_device *dev = node->minor->dev;
2026 struct radeon_device *rdev = dev->dev_private;
2027 uint32_t reg, value;
2028 unsigned i;
2029
2030 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2031 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2032 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2033 for (i = 0; i < 64; i++) {
2034 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2035 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2036 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2037 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2038 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2039 }
2040 return 0;
2041}
2042
2043static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2044{
2045 struct drm_info_node *node = (struct drm_info_node *) m->private;
2046 struct drm_device *dev = node->minor->dev;
2047 struct radeon_device *rdev = dev->dev_private;
2048 uint32_t rdp, wdp;
2049 unsigned count, i, j;
2050
2051 radeon_ring_free_size(rdev);
2052 rdp = RREG32(RADEON_CP_RB_RPTR);
2053 wdp = RREG32(RADEON_CP_RB_WPTR);
2054 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2055 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2056 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2057 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2058 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2059 seq_printf(m, "%u dwords in ring\n", count);
2060 for (j = 0; j <= count; j++) {
2061 i = (rdp + j) & rdev->cp.ptr_mask;
2062 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2063 }
2064 return 0;
2065}
2066
2067
2068static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2069{
2070 struct drm_info_node *node = (struct drm_info_node *) m->private;
2071 struct drm_device *dev = node->minor->dev;
2072 struct radeon_device *rdev = dev->dev_private;
2073 uint32_t csq_stat, csq2_stat, tmp;
2074 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2075 unsigned i;
2076
2077 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2078 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2079 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2080 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2081 r_rptr = (csq_stat >> 0) & 0x3ff;
2082 r_wptr = (csq_stat >> 10) & 0x3ff;
2083 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2084 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2085 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2086 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2087 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2088 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2089 seq_printf(m, "Ring rptr %u\n", r_rptr);
2090 seq_printf(m, "Ring wptr %u\n", r_wptr);
2091 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2092 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2093 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2094 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2095 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2096 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2097 seq_printf(m, "Ring fifo:\n");
2098 for (i = 0; i < 256; i++) {
2099 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2100 tmp = RREG32(RADEON_CP_CSQ_DATA);
2101 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2102 }
2103 seq_printf(m, "Indirect1 fifo:\n");
2104 for (i = 256; i <= 512; i++) {
2105 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2106 tmp = RREG32(RADEON_CP_CSQ_DATA);
2107 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2108 }
2109 seq_printf(m, "Indirect2 fifo:\n");
2110 for (i = 640; i < ib1_wptr; i++) {
2111 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2112 tmp = RREG32(RADEON_CP_CSQ_DATA);
2113 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2114 }
2115 return 0;
2116}
2117
2118static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2119{
2120 struct drm_info_node *node = (struct drm_info_node *) m->private;
2121 struct drm_device *dev = node->minor->dev;
2122 struct radeon_device *rdev = dev->dev_private;
2123 uint32_t tmp;
2124
2125 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2126 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2127 tmp = RREG32(RADEON_MC_FB_LOCATION);
2128 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2129 tmp = RREG32(RADEON_BUS_CNTL);
2130 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2131 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2132 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2133 tmp = RREG32(RADEON_AGP_BASE);
2134 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2135 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2136 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2137 tmp = RREG32(0x01D0);
2138 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2139 tmp = RREG32(RADEON_AIC_LO_ADDR);
2140 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2141 tmp = RREG32(RADEON_AIC_HI_ADDR);
2142 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2143 tmp = RREG32(0x01E4);
2144 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2145 return 0;
2146}
2147
2148static struct drm_info_list r100_debugfs_rbbm_list[] = {
2149 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2150};
2151
2152static struct drm_info_list r100_debugfs_cp_list[] = {
2153 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2154 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2155};
2156
2157static struct drm_info_list r100_debugfs_mc_info_list[] = {
2158 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2159};
2160#endif
2161
2162int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2163{
2164#if defined(CONFIG_DEBUG_FS)
2165 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2166#else
2167 return 0;
2168#endif
2169}
2170
2171int r100_debugfs_cp_init(struct radeon_device *rdev)
2172{
2173#if defined(CONFIG_DEBUG_FS)
2174 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2175#else
2176 return 0;
2177#endif
2178}
2179
2180int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2181{
2182#if defined(CONFIG_DEBUG_FS)
2183 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2184#else
2185 return 0;
2186#endif
2187}
e024e110
DA		 2188
2189int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2190 uint32_t tiling_flags, uint32_t pitch,
2191 uint32_t offset, uint32_t obj_size)
2192{
2193 int surf_index = reg * 16;
2194 int flags = 0;
2195
2196 /* r100/r200 divide by 16 */
2197 if (rdev->family < CHIP_R300)
2198 flags = pitch / 16;
2199 else
2200 flags = pitch / 8;
2201
2202 if (rdev->family <= CHIP_RS200) {
2203 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2204 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2205 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2206 if (tiling_flags & RADEON_TILING_MACRO)
2207 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2208 } else if (rdev->family <= CHIP_RV280) {
2209 if (tiling_flags & (RADEON_TILING_MACRO))
2210 flags |= R200_SURF_TILE_COLOR_MACRO;
2211 if (tiling_flags & RADEON_TILING_MICRO)
2212 flags |= R200_SURF_TILE_COLOR_MICRO;
2213 } else {
2214 if (tiling_flags & RADEON_TILING_MACRO)
2215 flags |= R300_SURF_TILE_MACRO;
2216 if (tiling_flags & RADEON_TILING_MICRO)
2217 flags |= R300_SURF_TILE_MICRO;
2218 }
2219
c88f9f0c
MD		 2220 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2221 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2222 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2223 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2224
e024e110
DA		 2225 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2226 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2227 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2228 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2229 return 0;
2230}
2231
2232void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2233{
2234 int surf_index = reg * 16;
2235 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2236}
c93bb85b
JG		 2237
2238void r100_bandwidth_update(struct radeon_device *rdev)
2239{
2240 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2241 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2242 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2243 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2244 fixed20_12 memtcas_ff[8] = {
2245 fixed_init(1),
2246 fixed_init(2),
2247 fixed_init(3),
2248 fixed_init(0),
2249 fixed_init_half(1),
2250 fixed_init_half(2),
2251 fixed_init(0),
2252 };
2253 fixed20_12 memtcas_rs480_ff[8] = {
2254 fixed_init(0),
2255 fixed_init(1),
2256 fixed_init(2),
2257 fixed_init(3),
2258 fixed_init(0),
2259 fixed_init_half(1),
2260 fixed_init_half(2),
2261 fixed_init_half(3),
2262 };
2263 fixed20_12 memtcas2_ff[8] = {
2264 fixed_init(0),
2265 fixed_init(1),
2266 fixed_init(2),
2267 fixed_init(3),
2268 fixed_init(4),
2269 fixed_init(5),
2270 fixed_init(6),
2271 fixed_init(7),
2272 };
2273 fixed20_12 memtrbs[8] = {
2274 fixed_init(1),
2275 fixed_init_half(1),
2276 fixed_init(2),
2277 fixed_init_half(2),
2278 fixed_init(3),
2279 fixed_init_half(3),
2280 fixed_init(4),
2281 fixed_init_half(4)
2282 };
2283 fixed20_12 memtrbs_r4xx[8] = {
2284 fixed_init(4),
2285 fixed_init(5),
2286 fixed_init(6),
2287 fixed_init(7),
2288 fixed_init(8),
2289 fixed_init(9),
2290 fixed_init(10),
2291 fixed_init(11)
2292 };
2293 fixed20_12 min_mem_eff;
2294 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2295 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2296 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2297 disp_drain_rate2, read_return_rate;
2298 fixed20_12 time_disp1_drop_priority;
2299 int c;
2300 int cur_size = 16; /* in octawords */
2301 int critical_point = 0, critical_point2;
2302/* uint32_t read_return_rate, time_disp1_drop_priority; */
2303 int stop_req, max_stop_req;
2304 struct drm_display_mode *mode1 = NULL;
2305 struct drm_display_mode *mode2 = NULL;
2306 uint32_t pixel_bytes1 = 0;
2307 uint32_t pixel_bytes2 = 0;
2308
2309 if (rdev->mode_info.crtcs[0]->base.enabled) {
2310 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2311 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2312 }
dfee5614
DA		 2313 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2314 if (rdev->mode_info.crtcs[1]->base.enabled) {
2315 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2316 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2317 }
c93bb85b
JG		 2318 }
2319
2320 min_mem_eff.full = rfixed_const_8(0);
2321 /* get modes */
2322 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2323 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2324 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2325 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2326 /* check crtc enables */
2327 if (mode2)
2328 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2329 if (mode1)
2330 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2331 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2332 }
2333
2334 /*
2335 * determine is there is enough bw for current mode
2336 */
2337 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2338 temp_ff.full = rfixed_const(100);
2339 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2340 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2341 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2342
2343 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2344 temp_ff.full = rfixed_const(temp);
2345 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2346
2347 pix_clk.full = 0;
2348 pix_clk2.full = 0;
2349 peak_disp_bw.full = 0;
2350 if (mode1) {
2351 temp_ff.full = rfixed_const(1000);
2352 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2353 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2354 temp_ff.full = rfixed_const(pixel_bytes1);
2355 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2356 }
2357 if (mode2) {
2358 temp_ff.full = rfixed_const(1000);
2359 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2360 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2361 temp_ff.full = rfixed_const(pixel_bytes2);
2362 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2363 }
2364
2365 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2366 if (peak_disp_bw.full >= mem_bw.full) {
2367 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2368 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2369 }
2370
2371 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2372 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2373 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2374 mem_trcd = ((temp >> 2) & 0x3) + 1;
2375 mem_trp = ((temp & 0x3)) + 1;
2376 mem_tras = ((temp & 0x70) >> 4) + 1;
2377 } else if (rdev->family == CHIP_R300 ||
2378 rdev->family == CHIP_R350) { /* r300, r350 */
2379 mem_trcd = (temp & 0x7) + 1;
2380 mem_trp = ((temp >> 8) & 0x7) + 1;
2381 mem_tras = ((temp >> 11) & 0xf) + 4;
2382 } else if (rdev->family == CHIP_RV350 ||
2383 rdev->family <= CHIP_RV380) {
2384 /* rv3x0 */
2385 mem_trcd = (temp & 0x7) + 3;
2386 mem_trp = ((temp >> 8) & 0x7) + 3;
2387 mem_tras = ((temp >> 11) & 0xf) + 6;
2388 } else if (rdev->family == CHIP_R420 ||
2389 rdev->family == CHIP_R423 ||
2390 rdev->family == CHIP_RV410) {
2391 /* r4xx */
2392 mem_trcd = (temp & 0xf) + 3;
2393 if (mem_trcd > 15)
2394 mem_trcd = 15;
2395 mem_trp = ((temp >> 8) & 0xf) + 3;
2396 if (mem_trp > 15)
2397 mem_trp = 15;
2398 mem_tras = ((temp >> 12) & 0x1f) + 6;
2399 if (mem_tras > 31)
2400 mem_tras = 31;
2401 } else { /* RV200, R200 */
2402 mem_trcd = (temp & 0x7) + 1;
2403 mem_trp = ((temp >> 8) & 0x7) + 1;
2404 mem_tras = ((temp >> 12) & 0xf) + 4;
2405 }
2406 /* convert to FF */
2407 trcd_ff.full = rfixed_const(mem_trcd);
2408 trp_ff.full = rfixed_const(mem_trp);
2409 tras_ff.full = rfixed_const(mem_tras);
2410
2411 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2412 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2413 data = (temp & (7 << 20)) >> 20;
2414 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2415 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2416 tcas_ff = memtcas_rs480_ff[data];
2417 else
2418 tcas_ff = memtcas_ff[data];
2419 } else
2420 tcas_ff = memtcas2_ff[data];
2421
2422 if (rdev->family == CHIP_RS400 ||
2423 rdev->family == CHIP_RS480) {
2424 /* extra cas latency stored in bits 23-25 0-4 clocks */
2425 data = (temp >> 23) & 0x7;
2426 if (data < 5)
2427 tcas_ff.full += rfixed_const(data);
2428 }
2429
2430 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2431 /* on the R300, Tcas is included in Trbs.
2432 */
2433 temp = RREG32(RADEON_MEM_CNTL);
2434 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2435 if (data == 1) {
2436 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2437 temp = RREG32(R300_MC_IND_INDEX);
2438 temp &= ~R300_MC_IND_ADDR_MASK;
2439 temp |= R300_MC_READ_CNTL_CD_mcind;
2440 WREG32(R300_MC_IND_INDEX, temp);
2441 temp = RREG32(R300_MC_IND_DATA);
2442 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2443 } else {
2444 temp = RREG32(R300_MC_READ_CNTL_AB);
2445 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2446 }
2447 } else {
2448 temp = RREG32(R300_MC_READ_CNTL_AB);
2449 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2450 }
2451 if (rdev->family == CHIP_RV410 ||
2452 rdev->family == CHIP_R420 ||
2453 rdev->family == CHIP_R423)
2454 trbs_ff = memtrbs_r4xx[data];
2455 else
2456 trbs_ff = memtrbs[data];
2457 tcas_ff.full += trbs_ff.full;
2458 }
2459
2460 sclk_eff_ff.full = sclk_ff.full;
2461
2462 if (rdev->flags & RADEON_IS_AGP) {
2463 fixed20_12 agpmode_ff;
2464 agpmode_ff.full = rfixed_const(radeon_agpmode);
2465 temp_ff.full = rfixed_const_666(16);
2466 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2467 }
2468 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2469
2470 if (ASIC_IS_R300(rdev)) {
2471 sclk_delay_ff.full = rfixed_const(250);
2472 } else {
2473 if ((rdev->family == CHIP_RV100) ||
2474 rdev->flags & RADEON_IS_IGP) {
2475 if (rdev->mc.vram_is_ddr)
2476 sclk_delay_ff.full = rfixed_const(41);
2477 else
2478 sclk_delay_ff.full = rfixed_const(33);
2479 } else {
2480 if (rdev->mc.vram_width == 128)
2481 sclk_delay_ff.full = rfixed_const(57);
2482 else
2483 sclk_delay_ff.full = rfixed_const(41);
2484 }
2485 }
2486
2487 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2488
2489 if (rdev->mc.vram_is_ddr) {
2490 if (rdev->mc.vram_width == 32) {
2491 k1.full = rfixed_const(40);
2492 c = 3;
2493 } else {
2494 k1.full = rfixed_const(20);
2495 c = 1;
2496 }
2497 } else {
2498 k1.full = rfixed_const(40);
2499 c = 3;
2500 }
2501
2502 temp_ff.full = rfixed_const(2);
2503 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2504 temp_ff.full = rfixed_const(c);
2505 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2506 temp_ff.full = rfixed_const(4);
2507 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2508 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2509 mc_latency_mclk.full += k1.full;
2510
2511 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2512 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2513
2514 /*
2515 HW cursor time assuming worst case of full size colour cursor.
2516 */
2517 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2518 temp_ff.full += trcd_ff.full;
2519 if (temp_ff.full < tras_ff.full)
2520 temp_ff.full = tras_ff.full;
2521 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2522
2523 temp_ff.full = rfixed_const(cur_size);
2524 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2525 /*
2526 Find the total latency for the display data.
2527 */
b5fc9010 2528 disp_latency_overhead.full = rfixed_const(8);
c93bb85b
JG		 2529 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2530 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2531 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2532
2533 if (mc_latency_mclk.full > mc_latency_sclk.full)
2534 disp_latency.full = mc_latency_mclk.full;
2535 else
2536 disp_latency.full = mc_latency_sclk.full;
2537
2538 /* setup Max GRPH_STOP_REQ default value */
2539 if (ASIC_IS_RV100(rdev))
2540 max_stop_req = 0x5c;
2541 else
2542 max_stop_req = 0x7c;
2543
2544 if (mode1) {
2545 /* CRTC1
2546 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2547 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2548 */
2549 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2550
2551 if (stop_req > max_stop_req)
2552 stop_req = max_stop_req;
2553
2554 /*
2555 Find the drain rate of the display buffer.
2556 */
2557 temp_ff.full = rfixed_const((16/pixel_bytes1));
2558 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2559
2560 /*
2561 Find the critical point of the display buffer.
2562 */
2563 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2564 crit_point_ff.full += rfixed_const_half(0);
2565
2566 critical_point = rfixed_trunc(crit_point_ff);
2567
2568 if (rdev->disp_priority == 2) {
2569 critical_point = 0;
2570 }
2571
2572 /*
2573 The critical point should never be above max_stop_req-4. Setting
2574 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2575 */
2576 if (max_stop_req - critical_point < 4)
2577 critical_point = 0;
2578
2579 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2580 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2581 critical_point = 0x10;
2582 }
2583
2584 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2585 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2586 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2587 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2588 if ((rdev->family == CHIP_R350) &&
2589 (stop_req > 0x15)) {
2590 stop_req -= 0x10;
2591 }
2592 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2593 temp |= RADEON_GRPH_BUFFER_SIZE;
2594 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2595 RADEON_GRPH_CRITICAL_AT_SOF |
2596 RADEON_GRPH_STOP_CNTL);
2597 /*
2598 Write the result into the register.
2599 */
2600 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2601 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2602
2603#if 0
2604 if ((rdev->family == CHIP_RS400) ||
2605 (rdev->family == CHIP_RS480)) {
2606 /* attempt to program RS400 disp regs correctly ??? */
2607 temp = RREG32(RS400_DISP1_REG_CNTL);
2608 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2609 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2610 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2611 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2612 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2613 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2614 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2615 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2616 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2617 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2618 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2619 }
2620#endif
2621
2622 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2623 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2624 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2625 }
2626
2627 if (mode2) {
2628 u32 grph2_cntl;
2629 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2630
2631 if (stop_req > max_stop_req)
2632 stop_req = max_stop_req;
2633
2634 /*
2635 Find the drain rate of the display buffer.
2636 */
2637 temp_ff.full = rfixed_const((16/pixel_bytes2));
2638 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2639
2640 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2641 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2642 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2643 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2644 if ((rdev->family == CHIP_R350) &&
2645 (stop_req > 0x15)) {
2646 stop_req -= 0x10;
2647 }
2648 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2649 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2650 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2651 RADEON_GRPH_CRITICAL_AT_SOF |
2652 RADEON_GRPH_STOP_CNTL);
2653
2654 if ((rdev->family == CHIP_RS100) ||
2655 (rdev->family == CHIP_RS200))
2656 critical_point2 = 0;
2657 else {
2658 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2659 temp_ff.full = rfixed_const(temp);
2660 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2661 if (sclk_ff.full < temp_ff.full)
2662 temp_ff.full = sclk_ff.full;
2663
2664 read_return_rate.full = temp_ff.full;
2665
2666 if (mode1) {
2667 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2668 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2669 } else {
2670 time_disp1_drop_priority.full = 0;
2671 }
2672 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2673 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2674 crit_point_ff.full += rfixed_const_half(0);
2675
2676 critical_point2 = rfixed_trunc(crit_point_ff);
2677
2678 if (rdev->disp_priority == 2) {
2679 critical_point2 = 0;
2680 }
2681
2682 if (max_stop_req - critical_point2 < 4)
2683 critical_point2 = 0;
2684
2685 }
2686
2687 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2688 /* some R300 cards have problem with this set to 0 */
2689 critical_point2 = 0x10;
2690 }
2691
2692 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2693 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2694
2695 if ((rdev->family == CHIP_RS400) ||
2696 (rdev->family == CHIP_RS480)) {
2697#if 0
2698 /* attempt to program RS400 disp2 regs correctly ??? */
2699 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2700 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2701 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2702 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2703 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2704 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2705 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2706 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2707 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2708 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2709 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2710 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2711#endif
2712 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2713 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2714 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2715 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2716 }
2717
2718 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2719 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2720 }
2721}
551ebd83
DA		 2722
2723static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2724{
2725 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 2726 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 2727 DRM_ERROR("width %d\n", t->width);
ceb776bc 2728 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 2729 DRM_ERROR("height %d\n", t->height);
ceb776bc 2730 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 2731 DRM_ERROR("num levels %d\n", t->num_levels);
2732 DRM_ERROR("depth %d\n", t->txdepth);
2733 DRM_ERROR("bpp %d\n", t->cpp);
2734 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2735 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2736 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 2737 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 2738}
2739
2740static int r100_cs_track_cube(struct radeon_device *rdev,
2741 struct r100_cs_track *track, unsigned idx)
2742{
2743 unsigned face, w, h;
4c788679 2744 struct radeon_bo *cube_robj;
551ebd83
DA		 2745 unsigned long size;
2746
2747 for (face = 0; face < 5; face++) {
2748 cube_robj = track->textures[idx].cube_info[face].robj;
2749 w = track->textures[idx].cube_info[face].width;
2750 h = track->textures[idx].cube_info[face].height;
2751
2752 size = w * h;
2753 size *= track->textures[idx].cpp;
2754
2755 size += track->textures[idx].cube_info[face].offset;
2756
4c788679 2757 if (size > radeon_bo_size(cube_robj)) {
551ebd83 2758 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
4c788679 2759 size, radeon_bo_size(cube_robj));
551ebd83
DA		 2760 r100_cs_track_texture_print(&track->textures[idx]);
2761 return -1;
2762 }
2763 }
2764 return 0;
2765}
2766
d785d78b
DA		 2767static int r100_track_compress_size(int compress_format, int w, int h)
2768{
2769 int block_width, block_height, block_bytes;
2770 int wblocks, hblocks;
2771 int min_wblocks;
2772 int sz;
2773
2774 block_width = 4;
2775 block_height = 4;
2776
2777 switch (compress_format) {
2778 case R100_TRACK_COMP_DXT1:
2779 block_bytes = 8;
2780 min_wblocks = 4;
2781 break;
2782 default:
2783 case R100_TRACK_COMP_DXT35:
2784 block_bytes = 16;
2785 min_wblocks = 2;
2786 break;
2787 }
2788
2789 hblocks = (h + block_height - 1) / block_height;
2790 wblocks = (w + block_width - 1) / block_width;
2791 if (wblocks < min_wblocks)
2792 wblocks = min_wblocks;
2793 sz = wblocks * hblocks * block_bytes;
2794 return sz;
2795}
2796
551ebd83
DA		 2797static int r100_cs_track_texture_check(struct radeon_device *rdev,
2798 struct r100_cs_track *track)
2799{
4c788679 2800 struct radeon_bo *robj;
551ebd83
DA		 2801 unsigned long size;
2802 unsigned u, i, w, h;
2803 int ret;
2804
2805 for (u = 0; u < track->num_texture; u++) {
2806 if (!track->textures[u].enabled)
2807 continue;
2808 robj = track->textures[u].robj;
2809 if (robj == NULL) {
2810 DRM_ERROR("No texture bound to unit %u\n", u);
2811 return -EINVAL;
2812 }
2813 size = 0;
2814 for (i = 0; i <= track->textures[u].num_levels; i++) {
2815 if (track->textures[u].use_pitch) {
2816 if (rdev->family < CHIP_R300)
2817 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2818 else
2819 w = track->textures[u].pitch / (1 << i);
2820 } else {
ceb776bc 2821 w = track->textures[u].width;
551ebd83
DA		 2822 if (rdev->family >= CHIP_RV515)
2823 w |= track->textures[u].width_11;
ceb776bc 2824 w = w / (1 << i);
551ebd83
DA		 2825 if (track->textures[u].roundup_w)
2826 w = roundup_pow_of_two(w);
2827 }
ceb776bc 2828 h = track->textures[u].height;
551ebd83
DA		 2829 if (rdev->family >= CHIP_RV515)
2830 h |= track->textures[u].height_11;
ceb776bc 2831 h = h / (1 << i);
551ebd83
DA		 2832 if (track->textures[u].roundup_h)
2833 h = roundup_pow_of_two(h);
d785d78b
DA		 2834 if (track->textures[u].compress_format) {
2835
2836 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2837 /* compressed textures are block based */
2838 } else
2839 size += w * h;
551ebd83
DA		 2840 }
2841 size *= track->textures[u].cpp;
d785d78b 2842
551ebd83
DA		 2843 switch (track->textures[u].tex_coord_type) {
2844 case 0:
2845 break;
2846 case 1:
2847 size *= (1 << track->textures[u].txdepth);
2848 break;
2849 case 2:
2850 if (track->separate_cube) {
2851 ret = r100_cs_track_cube(rdev, track, u);
2852 if (ret)
2853 return ret;
2854 } else
2855 size *= 6;
2856 break;
2857 default:
2858 DRM_ERROR("Invalid texture coordinate type %u for unit "
2859 "%u\n", track->textures[u].tex_coord_type, u);
2860 return -EINVAL;
2861 }
4c788679 2862 if (size > radeon_bo_size(robj)) {
551ebd83 2863 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 2864 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 2865 r100_cs_track_texture_print(&track->textures[u]);
2866 return -EINVAL;
2867 }
2868 }
2869 return 0;
2870}
2871
2872int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2873{
2874 unsigned i;
2875 unsigned long size;
2876 unsigned prim_walk;
2877 unsigned nverts;
2878
2879 for (i = 0; i < track->num_cb; i++) {
2880 if (track->cb[i].robj == NULL) {
46c64d4b
MO		 2881 if (!(track->fastfill || track->color_channel_mask ||
2882 track->blend_read_enable)) {
2883 continue;
2884 }
551ebd83
DA		 2885 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2886 return -EINVAL;
2887 }
2888 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2889 size += track->cb[i].offset;
4c788679 2890 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 2891 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2892 "(need %lu have %lu) !\n", i, size,
4c788679 2893 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 2894 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2895 i, track->cb[i].pitch, track->cb[i].cpp,
2896 track->cb[i].offset, track->maxy);
2897 return -EINVAL;
2898 }
2899 }
2900 if (track->z_enabled) {
2901 if (track->zb.robj == NULL) {
2902 DRM_ERROR("[drm] No buffer for z buffer !\n");
2903 return -EINVAL;
2904 }
2905 size = track->zb.pitch * track->zb.cpp * track->maxy;
2906 size += track->zb.offset;
4c788679 2907 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 2908 DRM_ERROR("[drm] Buffer too small for z buffer "
2909 "(need %lu have %lu) !\n", size,
4c788679 2910 radeon_bo_size(track->zb.robj));
551ebd83
DA		 2911 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2912 track->zb.pitch, track->zb.cpp,
2913 track->zb.offset, track->maxy);
2914 return -EINVAL;
2915 }
2916 }
2917 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2918 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2919 switch (prim_walk) {
2920 case 1:
2921 for (i = 0; i < track->num_arrays; i++) {
2922 size = track->arrays[i].esize * track->max_indx * 4;
2923 if (track->arrays[i].robj == NULL) {
2924 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2925 "bound\n", prim_walk, i);
2926 return -EINVAL;
2927 }
4c788679
JG		 2928 if (size > radeon_bo_size(track->arrays[i].robj)) {
2929 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2930 "need %lu dwords have %lu dwords\n",
2931 prim_walk, i, size >> 2,
2932 radeon_bo_size(track->arrays[i].robj)
2933 >> 2);
551ebd83
DA		 2934 DRM_ERROR("Max indices %u\n", track->max_indx);
2935 return -EINVAL;
2936 }
2937 }
2938 break;
2939 case 2:
2940 for (i = 0; i < track->num_arrays; i++) {
2941 size = track->arrays[i].esize * (nverts - 1) * 4;
2942 if (track->arrays[i].robj == NULL) {
2943 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2944 "bound\n", prim_walk, i);
2945 return -EINVAL;
2946 }
4c788679
JG		 2947 if (size > radeon_bo_size(track->arrays[i].robj)) {
2948 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2949 "need %lu dwords have %lu dwords\n",
2950 prim_walk, i, size >> 2,
2951 radeon_bo_size(track->arrays[i].robj)
2952 >> 2);
551ebd83
DA		 2953 return -EINVAL;
2954 }
2955 }
2956 break;
2957 case 3:
2958 size = track->vtx_size * nverts;
2959 if (size != track->immd_dwords) {
2960 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2961 track->immd_dwords, size);
2962 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2963 nverts, track->vtx_size);
2964 return -EINVAL;
2965 }
2966 break;
2967 default:
2968 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2969 prim_walk);
2970 return -EINVAL;
2971 }
2972 return r100_cs_track_texture_check(rdev, track);
2973}
2974
2975void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2976{
2977 unsigned i, face;
2978
2979 if (rdev->family < CHIP_R300) {
2980 track->num_cb = 1;
2981 if (rdev->family <= CHIP_RS200)
2982 track->num_texture = 3;
2983 else
2984 track->num_texture = 6;
2985 track->maxy = 2048;
2986 track->separate_cube = 1;
2987 } else {
2988 track->num_cb = 4;
2989 track->num_texture = 16;
2990 track->maxy = 4096;
2991 track->separate_cube = 0;
2992 }
2993
2994 for (i = 0; i < track->num_cb; i++) {
2995 track->cb[i].robj = NULL;
2996 track->cb[i].pitch = 8192;
2997 track->cb[i].cpp = 16;
2998 track->cb[i].offset = 0;
2999 }
3000 track->z_enabled = true;
3001 track->zb.robj = NULL;
3002 track->zb.pitch = 8192;
3003 track->zb.cpp = 4;
3004 track->zb.offset = 0;
3005 track->vtx_size = 0x7F;
3006 track->immd_dwords = 0xFFFFFFFFUL;
3007 track->num_arrays = 11;
3008 track->max_indx = 0x00FFFFFFUL;
3009 for (i = 0; i < track->num_arrays; i++) {
3010 track->arrays[i].robj = NULL;
3011 track->arrays[i].esize = 0x7F;
3012 }
3013 for (i = 0; i < track->num_texture; i++) {
d785d78b 3014 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3015 track->textures[i].pitch = 16536;
3016 track->textures[i].width = 16536;
3017 track->textures[i].height = 16536;
3018 track->textures[i].width_11 = 1 << 11;
3019 track->textures[i].height_11 = 1 << 11;
3020 track->textures[i].num_levels = 12;
3021 if (rdev->family <= CHIP_RS200) {
3022 track->textures[i].tex_coord_type = 0;
3023 track->textures[i].txdepth = 0;
3024 } else {
3025 track->textures[i].txdepth = 16;
3026 track->textures[i].tex_coord_type = 1;
3027 }
3028 track->textures[i].cpp = 64;
3029 track->textures[i].robj = NULL;
3030 /* CS IB emission code makes sure texture unit are disabled */
3031 track->textures[i].enabled = false;
3032 track->textures[i].roundup_w = true;
3033 track->textures[i].roundup_h = true;
3034 if (track->separate_cube)
3035 for (face = 0; face < 5; face++) {
3036 track->textures[i].cube_info[face].robj = NULL;
3037 track->textures[i].cube_info[face].width = 16536;
3038 track->textures[i].cube_info[face].height = 16536;
3039 track->textures[i].cube_info[face].offset = 0;
3040 }
3041 }
3042}
3ce0a23d
JG		 3043
3044int r100_ring_test(struct radeon_device *rdev)
3045{
3046 uint32_t scratch;
3047 uint32_t tmp = 0;
3048 unsigned i;
3049 int r;
3050
3051 r = radeon_scratch_get(rdev, &scratch);
3052 if (r) {
3053 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3054 return r;
3055 }
3056 WREG32(scratch, 0xCAFEDEAD);
3057 r = radeon_ring_lock(rdev, 2);
3058 if (r) {
3059 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3060 radeon_scratch_free(rdev, scratch);
3061 return r;
3062 }
3063 radeon_ring_write(rdev, PACKET0(scratch, 0));
3064 radeon_ring_write(rdev, 0xDEADBEEF);
3065 radeon_ring_unlock_commit(rdev);
3066 for (i = 0; i < rdev->usec_timeout; i++) {
3067 tmp = RREG32(scratch);
3068 if (tmp == 0xDEADBEEF) {
3069 break;
3070 }
3071 DRM_UDELAY(1);
3072 }
3073 if (i < rdev->usec_timeout) {
3074 DRM_INFO("ring test succeeded in %d usecs\n", i);
3075 } else {
3076 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3077 scratch, tmp);
3078 r = -EINVAL;
3079 }
3080 radeon_scratch_free(rdev, scratch);
3081 return r;
3082}
3083
3084void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3085{
3086 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3087 radeon_ring_write(rdev, ib->gpu_addr);
3088 radeon_ring_write(rdev, ib->length_dw);
3089}
3090
3091int r100_ib_test(struct radeon_device *rdev)
3092{
3093 struct radeon_ib *ib;
3094 uint32_t scratch;
3095 uint32_t tmp = 0;
3096 unsigned i;
3097 int r;
3098
3099 r = radeon_scratch_get(rdev, &scratch);
3100 if (r) {
3101 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3102 return r;
3103 }
3104 WREG32(scratch, 0xCAFEDEAD);
3105 r = radeon_ib_get(rdev, &ib);
3106 if (r) {
3107 return r;
3108 }
3109 ib->ptr[0] = PACKET0(scratch, 0);
3110 ib->ptr[1] = 0xDEADBEEF;
3111 ib->ptr[2] = PACKET2(0);
3112 ib->ptr[3] = PACKET2(0);
3113 ib->ptr[4] = PACKET2(0);
3114 ib->ptr[5] = PACKET2(0);
3115 ib->ptr[6] = PACKET2(0);
3116 ib->ptr[7] = PACKET2(0);
3117 ib->length_dw = 8;
3118 r = radeon_ib_schedule(rdev, ib);
3119 if (r) {
3120 radeon_scratch_free(rdev, scratch);
3121 radeon_ib_free(rdev, &ib);
3122 return r;
3123 }
3124 r = radeon_fence_wait(ib->fence, false);
3125 if (r) {
3126 return r;
3127 }
3128 for (i = 0; i < rdev->usec_timeout; i++) {
3129 tmp = RREG32(scratch);
3130 if (tmp == 0xDEADBEEF) {
3131 break;
3132 }
3133 DRM_UDELAY(1);
3134 }
3135 if (i < rdev->usec_timeout) {
3136 DRM_INFO("ib test succeeded in %u usecs\n", i);
3137 } else {
3138 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3139 scratch, tmp);
3140 r = -EINVAL;
3141 }
3142 radeon_scratch_free(rdev, scratch);
3143 radeon_ib_free(rdev, &ib);
3144 return r;
3145}
9f022ddf
JG		 3146
3147void r100_ib_fini(struct radeon_device *rdev)
3148{
3149 radeon_ib_pool_fini(rdev);
3150}
3151
3152int r100_ib_init(struct radeon_device *rdev)
3153{
3154 int r;
3155
3156 r = radeon_ib_pool_init(rdev);
3157 if (r) {
3158 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3159 r100_ib_fini(rdev);
3160 return r;
3161 }
3162 r = r100_ib_test(rdev);
3163 if (r) {
3164 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3165 r100_ib_fini(rdev);
3166 return r;
3167 }
3168 return 0;
3169}
3170
3171void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3172{
3173 /* Shutdown CP we shouldn't need to do that but better be safe than
3174 * sorry
3175 */
3176 rdev->cp.ready = false;
3177 WREG32(R_000740_CP_CSQ_CNTL, 0);
3178
3179 /* Save few CRTC registers */
ca6ffc64 3180 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3181 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3182 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3183 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3184 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3185 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3186 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3187 }
3188
3189 /* Disable VGA aperture access */
ca6ffc64 3190 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3191 /* Disable cursor, overlay, crtc */
3192 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3193 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3194 S_000054_CRTC_DISPLAY_DIS(1));
3195 WREG32(R_000050_CRTC_GEN_CNTL,
3196 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3197 S_000050_CRTC_DISP_REQ_EN_B(1));
3198 WREG32(R_000420_OV0_SCALE_CNTL,
3199 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3200 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3201 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3202 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3203 S_000360_CUR2_LOCK(1));
3204 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3205 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3206 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3207 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3208 WREG32(R_000360_CUR2_OFFSET,
3209 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3210 }
3211}
3212
3213void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3214{
3215 /* Update base address for crtc */
3216 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3217 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3218 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3219 rdev->mc.vram_location);
3220 }
3221 /* Restore CRTC registers */
ca6ffc64 3222 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3223 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3224 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3225 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3226 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3227 }
3228}
ca6ffc64
JG		 3229
3230void r100_vga_render_disable(struct radeon_device *rdev)
3231{
d4550907 3232 u32 tmp;
ca6ffc64 3233
d4550907 3234 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3235 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3236}
d4550907
JG		 3237
3238static void r100_debugfs(struct radeon_device *rdev)
3239{
3240 int r;
3241
3242 r = r100_debugfs_mc_info_init(rdev);
3243 if (r)
3244 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3245}
3246
3247static void r100_mc_program(struct radeon_device *rdev)
3248{
3249 struct r100_mc_save save;
3250
3251 /* Stops all mc clients */
3252 r100_mc_stop(rdev, &save);
3253 if (rdev->flags & RADEON_IS_AGP) {
3254 WREG32(R_00014C_MC_AGP_LOCATION,
3255 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3256 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3257 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3258 if (rdev->family > CHIP_RV200)
3259 WREG32(R_00015C_AGP_BASE_2,
3260 upper_32_bits(rdev->mc.agp_base) & 0xff);
3261 } else {
3262 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3263 WREG32(R_000170_AGP_BASE, 0);
3264 if (rdev->family > CHIP_RV200)
3265 WREG32(R_00015C_AGP_BASE_2, 0);
3266 }
3267 /* Wait for mc idle */
3268 if (r100_mc_wait_for_idle(rdev))
3269 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3270 /* Program MC, should be a 32bits limited address space */
3271 WREG32(R_000148_MC_FB_LOCATION,
3272 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3273 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3274 r100_mc_resume(rdev, &save);
3275}
3276
3277void r100_clock_startup(struct radeon_device *rdev)
3278{
3279 u32 tmp;
3280
3281 if (radeon_dynclks != -1 && radeon_dynclks)
3282 radeon_legacy_set_clock_gating(rdev, 1);
3283 /* We need to force on some of the block */
3284 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3285 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3286 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3287 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3288 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3289}
3290
3291static int r100_startup(struct radeon_device *rdev)
3292{
3293 int r;
3294
92cde00c
AD		 3295 /* set common regs */
3296 r100_set_common_regs(rdev);
3297 /* program mc */
d4550907
JG		 3298 r100_mc_program(rdev);
3299 /* Resume clock */
3300 r100_clock_startup(rdev);
3301 /* Initialize GPU configuration (# pipes, ...) */
3302 r100_gpu_init(rdev);
3303 /* Initialize GART (initialize after TTM so we can allocate
3304 * memory through TTM but finalize after TTM) */
17e15b0c 3305 r100_enable_bm(rdev);
d4550907
JG		 3306 if (rdev->flags & RADEON_IS_PCI) {
3307 r = r100_pci_gart_enable(rdev);
3308 if (r)
3309 return r;
3310 }
3311 /* Enable IRQ */
d4550907 3312 r100_irq_set(rdev);
cafe6609 3313 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3314 /* 1M ring buffer */
3315 r = r100_cp_init(rdev, 1024 * 1024);
3316 if (r) {
3317 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3318 return r;
3319 }
3320 r = r100_wb_init(rdev);
3321 if (r)
3322 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3323 r = r100_ib_init(rdev);
3324 if (r) {
3325 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3326 return r;
3327 }
3328 return 0;
3329}
3330
3331int r100_resume(struct radeon_device *rdev)
3332{
3333 /* Make sur GART are not working */
3334 if (rdev->flags & RADEON_IS_PCI)
3335 r100_pci_gart_disable(rdev);
3336 /* Resume clock before doing reset */
3337 r100_clock_startup(rdev);
3338 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3339 if (radeon_gpu_reset(rdev)) {
3340 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3341 RREG32(R_000E40_RBBM_STATUS),
3342 RREG32(R_0007C0_CP_STAT));
3343 }
3344 /* post */
3345 radeon_combios_asic_init(rdev->ddev);
3346 /* Resume clock after posting */
3347 r100_clock_startup(rdev);
550e2d92
DA		 3348 /* Initialize surface registers */
3349 radeon_surface_init(rdev);
d4550907
JG		 3350 return r100_startup(rdev);
3351}
3352
3353int r100_suspend(struct radeon_device *rdev)
3354{
3355 r100_cp_disable(rdev);
3356 r100_wb_disable(rdev);
3357 r100_irq_disable(rdev);
3358 if (rdev->flags & RADEON_IS_PCI)
3359 r100_pci_gart_disable(rdev);
3360 return 0;
3361}
3362
3363void r100_fini(struct radeon_device *rdev)
3364{
3365 r100_suspend(rdev);
3366 r100_cp_fini(rdev);
3367 r100_wb_fini(rdev);
3368 r100_ib_fini(rdev);
3369 radeon_gem_fini(rdev);
3370 if (rdev->flags & RADEON_IS_PCI)
3371 r100_pci_gart_fini(rdev);
d0269ed8 3372 radeon_agp_fini(rdev);
d4550907
JG		 3373 radeon_irq_kms_fini(rdev);
3374 radeon_fence_driver_fini(rdev);
4c788679 3375 radeon_bo_fini(rdev);
d4550907
JG		 3376 radeon_atombios_fini(rdev);
3377 kfree(rdev->bios);
3378 rdev->bios = NULL;
3379}
3380
3381int r100_mc_init(struct radeon_device *rdev)
3382{
3383 int r;
3384 u32 tmp;
3385
3386 /* Setup GPU memory space */
3387 rdev->mc.vram_location = 0xFFFFFFFFUL;
3388 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3389 if (rdev->flags & RADEON_IS_IGP) {
3390 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3391 rdev->mc.vram_location = tmp << 16;
3392 }
3393 if (rdev->flags & RADEON_IS_AGP) {
3394 r = radeon_agp_init(rdev);
3395 if (r) {
3396 printk(KERN_WARNING "[drm] Disabling AGP\n");
3397 rdev->flags &= ~RADEON_IS_AGP;
3398 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3399 } else {
3400 rdev->mc.gtt_location = rdev->mc.agp_base;
3401 }
3402 }
3403 r = radeon_mc_setup(rdev);
3404 if (r)
3405 return r;
3406 return 0;
3407}
3408
3409int r100_init(struct radeon_device *rdev)
3410{
3411 int r;
3412
d4550907
JG		 3413 /* Register debugfs file specific to this group of asics */
3414 r100_debugfs(rdev);
3415 /* Disable VGA */
3416 r100_vga_render_disable(rdev);
3417 /* Initialize scratch registers */
3418 radeon_scratch_init(rdev);
3419 /* Initialize surface registers */
3420 radeon_surface_init(rdev);
3421 /* TODO: disable VGA need to use VGA request */
3422 /* BIOS*/
3423 if (!radeon_get_bios(rdev)) {
3424 if (ASIC_IS_AVIVO(rdev))
3425 return -EINVAL;
3426 }
3427 if (rdev->is_atom_bios) {
3428 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3429 return -EINVAL;
3430 } else {
3431 r = radeon_combios_init(rdev);
3432 if (r)
3433 return r;
3434 }
3435 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3436 if (radeon_gpu_reset(rdev)) {
3437 dev_warn(rdev->dev,
3438 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3439 RREG32(R_000E40_RBBM_STATUS),
3440 RREG32(R_0007C0_CP_STAT));
3441 }
3442 /* check if cards are posted or not */
72542d77
DA		 3443 if (radeon_boot_test_post_card(rdev) == false)
3444 return -EINVAL;
d4550907
JG		 3445 /* Set asic errata */
3446 r100_errata(rdev);
3447 /* Initialize clocks */
3448 radeon_get_clock_info(rdev->ddev);
6234077d
RM		 3449 /* Initialize power management */
3450 radeon_pm_init(rdev);
d4550907
JG		 3451 /* Get vram informations */
3452 r100_vram_info(rdev);
3453 /* Initialize memory controller (also test AGP) */
3454 r = r100_mc_init(rdev);
3455 if (r)
3456 return r;
3457 /* Fence driver */
3458 r = radeon_fence_driver_init(rdev);
3459 if (r)
3460 return r;
3461 r = radeon_irq_kms_init(rdev);
3462 if (r)
3463 return r;
3464 /* Memory manager */
4c788679 3465 r = radeon_bo_init(rdev);
d4550907
JG		 3466 if (r)
3467 return r;
3468 if (rdev->flags & RADEON_IS_PCI) {
3469 r = r100_pci_gart_init(rdev);
3470 if (r)
3471 return r;
3472 }
3473 r100_set_safe_registers(rdev);
3474 rdev->accel_working = true;
3475 r = r100_startup(rdev);
3476 if (r) {
3477 /* Somethings want wront with the accel init stop accel */
3478 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3479 r100_suspend(rdev);
3480 r100_cp_fini(rdev);
3481 r100_wb_fini(rdev);
3482 r100_ib_fini(rdev);
3483 if (rdev->flags & RADEON_IS_PCI)
3484 r100_pci_gart_fini(rdev);
3485 radeon_irq_kms_fini(rdev);
3486 rdev->accel_working = false;
3487 }
3488 return 0;
3489}
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