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drm/radeon/kms/r600: clamp vram to aperture size
[net-next-2.6.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
3ce0a23d
JG		 34#include "r100d.h"
35
70967ab9
BH		 36#include <linux/firmware.h>
37#include <linux/platform_device.h>
38
551ebd83
DA		 39#include "r100_reg_safe.h"
40#include "rn50_reg_safe.h"
41
70967ab9
BH		 42/* Firmware Names */
43#define FIRMWARE_R100 "radeon/R100_cp.bin"
44#define FIRMWARE_R200 "radeon/R200_cp.bin"
45#define FIRMWARE_R300 "radeon/R300_cp.bin"
46#define FIRMWARE_R420 "radeon/R420_cp.bin"
47#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
48#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
49#define FIRMWARE_R520 "radeon/R520_cp.bin"
50
51MODULE_FIRMWARE(FIRMWARE_R100);
52MODULE_FIRMWARE(FIRMWARE_R200);
53MODULE_FIRMWARE(FIRMWARE_R300);
54MODULE_FIRMWARE(FIRMWARE_R420);
55MODULE_FIRMWARE(FIRMWARE_RS690);
56MODULE_FIRMWARE(FIRMWARE_RS600);
57MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 58
551ebd83
DA		 59#include "r100_track.h"
60
771fe6b9
JG		 61/* This files gather functions specifics to:
62 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
63 *
64 * Some of these functions might be used by newer ASICs.
65 */
551ebd83 66int r200_init(struct radeon_device *rdev);
771fe6b9
JG		 67void r100_hdp_reset(struct radeon_device *rdev);
68void r100_gpu_init(struct radeon_device *rdev);
69int r100_gui_wait_for_idle(struct radeon_device *rdev);
70int r100_mc_wait_for_idle(struct radeon_device *rdev);
71void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
72void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
73int r100_debugfs_mc_info_init(struct radeon_device *rdev);
74
75
76/*
77 * PCI GART
78 */
79void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
80{
81 /* TODO: can we do somethings here ? */
82 /* It seems hw only cache one entry so we should discard this
83 * entry otherwise if first GPU GART read hit this entry it
84 * could end up in wrong address. */
85}
86
4aac0473 87int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 88{
771fe6b9
JG		 89 int r;
90
4aac0473
JG		 91 if (rdev->gart.table.ram.ptr) {
92 WARN(1, "R100 PCI GART already initialized.\n");
93 return 0;
94 }
771fe6b9
JG		 95 /* Initialize common gart structure */
96 r = radeon_gart_init(rdev);
4aac0473 97 if (r)
771fe6b9 98 return r;
4aac0473
JG		 99 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
100 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
101 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
102 return radeon_gart_table_ram_alloc(rdev);
103}
104
105int r100_pci_gart_enable(struct radeon_device *rdev)
106{
107 uint32_t tmp;
108
771fe6b9
JG		 109 /* discard memory request outside of configured range */
110 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
111 WREG32(RADEON_AIC_CNTL, tmp);
112 /* set address range for PCI address translate */
113 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
114 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
115 WREG32(RADEON_AIC_HI_ADDR, tmp);
116 /* Enable bus mastering */
117 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
118 WREG32(RADEON_BUS_CNTL, tmp);
119 /* set PCI GART page-table base address */
120 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
121 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
122 WREG32(RADEON_AIC_CNTL, tmp);
123 r100_pci_gart_tlb_flush(rdev);
124 rdev->gart.ready = true;
125 return 0;
126}
127
128void r100_pci_gart_disable(struct radeon_device *rdev)
129{
130 uint32_t tmp;
131
132 /* discard memory request outside of configured range */
133 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
134 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
135 WREG32(RADEON_AIC_LO_ADDR, 0);
136 WREG32(RADEON_AIC_HI_ADDR, 0);
137}
138
139int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
140{
141 if (i < 0 || i > rdev->gart.num_gpu_pages) {
142 return -EINVAL;
143 }
ed10f95d 144 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 145 return 0;
146}
147
4aac0473 148void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 149{
4aac0473
JG		 150 r100_pci_gart_disable(rdev);
151 radeon_gart_table_ram_free(rdev);
152 radeon_gart_fini(rdev);
771fe6b9
JG		 153}
154
155
156/*
157 * MC
158 */
159void r100_mc_disable_clients(struct radeon_device *rdev)
160{
161 uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
162
163 /* FIXME: is this function correct for rs100,rs200,rs300 ? */
164 if (r100_gui_wait_for_idle(rdev)) {
165 printk(KERN_WARNING "Failed to wait GUI idle while "
166 "programming pipes. Bad things might happen.\n");
167 }
168
169 /* stop display and memory access */
170 ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
171 WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
172 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
173 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
174 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
175
176 r100_gpu_wait_for_vsync(rdev);
177
178 WREG32(RADEON_CRTC_GEN_CNTL,
179 (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
180 RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
181
182 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
183 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
184
185 r100_gpu_wait_for_vsync2(rdev);
186 WREG32(RADEON_CRTC2_GEN_CNTL,
187 (crtc2_gen_cntl &
188 ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
189 RADEON_CRTC2_DISP_REQ_EN_B);
190 }
191
192 udelay(500);
193}
194
195void r100_mc_setup(struct radeon_device *rdev)
196{
197 uint32_t tmp;
198 int r;
199
200 r = r100_debugfs_mc_info_init(rdev);
201 if (r) {
202 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
203 }
204 /* Write VRAM size in case we are limiting it */
7a50f01a
DA		 205 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
206 /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
207 * if the aperture is 64MB but we have 32MB VRAM
208 * we report only 32MB VRAM but we have to set MC_FB_LOCATION
209 * to 64MB, otherwise the gpu accidentially dies */
210 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
771fe6b9
JG		 211 tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
212 tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
213 WREG32(RADEON_MC_FB_LOCATION, tmp);
214
215 /* Enable bus mastering */
216 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
217 WREG32(RADEON_BUS_CNTL, tmp);
218
219 if (rdev->flags & RADEON_IS_AGP) {
220 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
221 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
222 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
223 WREG32(RADEON_MC_AGP_LOCATION, tmp);
224 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
225 } else {
226 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
227 WREG32(RADEON_AGP_BASE, 0);
228 }
229
230 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
231 tmp |= (7 << 28);
232 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
233 (void)RREG32(RADEON_HOST_PATH_CNTL);
234 WREG32(RADEON_HOST_PATH_CNTL, tmp);
235 (void)RREG32(RADEON_HOST_PATH_CNTL);
236}
237
238int r100_mc_init(struct radeon_device *rdev)
239{
240 int r;
241
242 if (r100_debugfs_rbbm_init(rdev)) {
243 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
244 }
245
246 r100_gpu_init(rdev);
247 /* Disable gart which also disable out of gart access */
248 r100_pci_gart_disable(rdev);
249
250 /* Setup GPU memory space */
771fe6b9
JG		 251 rdev->mc.gtt_location = 0xFFFFFFFFUL;
252 if (rdev->flags & RADEON_IS_AGP) {
253 r = radeon_agp_init(rdev);
254 if (r) {
255 printk(KERN_WARNING "[drm] Disabling AGP\n");
256 rdev->flags &= ~RADEON_IS_AGP;
257 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
258 } else {
259 rdev->mc.gtt_location = rdev->mc.agp_base;
260 }
261 }
262 r = radeon_mc_setup(rdev);
263 if (r) {
264 return r;
265 }
266
267 r100_mc_disable_clients(rdev);
268 if (r100_mc_wait_for_idle(rdev)) {
269 printk(KERN_WARNING "Failed to wait MC idle while "
270 "programming pipes. Bad things might happen.\n");
271 }
272
273 r100_mc_setup(rdev);
274 return 0;
275}
276
277void r100_mc_fini(struct radeon_device *rdev)
278{
771fe6b9
JG		 279}
280
281
7ed220d7
MD		 282/*
283 * Interrupts
284 */
285int r100_irq_set(struct radeon_device *rdev)
286{
287 uint32_t tmp = 0;
288
289 if (rdev->irq.sw_int) {
290 tmp |= RADEON_SW_INT_ENABLE;
291 }
292 if (rdev->irq.crtc_vblank_int[0]) {
293 tmp |= RADEON_CRTC_VBLANK_MASK;
294 }
295 if (rdev->irq.crtc_vblank_int[1]) {
296 tmp |= RADEON_CRTC2_VBLANK_MASK;
297 }
298 WREG32(RADEON_GEN_INT_CNTL, tmp);
299 return 0;
300}
301
9f022ddf
JG		 302void r100_irq_disable(struct radeon_device *rdev)
303{
304 u32 tmp;
305
306 WREG32(R_000040_GEN_INT_CNTL, 0);
307 /* Wait and acknowledge irq */
308 mdelay(1);
309 tmp = RREG32(R_000044_GEN_INT_STATUS);
310 WREG32(R_000044_GEN_INT_STATUS, tmp);
311}
312
7ed220d7
MD		 313static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
314{
315 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
316 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
317 RADEON_CRTC2_VBLANK_STAT;
318
319 if (irqs) {
320 WREG32(RADEON_GEN_INT_STATUS, irqs);
321 }
322 return irqs & irq_mask;
323}
324
325int r100_irq_process(struct radeon_device *rdev)
326{
327 uint32_t status;
328
329 status = r100_irq_ack(rdev);
330 if (!status) {
331 return IRQ_NONE;
332 }
a513c184
JG		 333 if (rdev->shutdown) {
334 return IRQ_NONE;
335 }
7ed220d7
MD		 336 while (status) {
337 /* SW interrupt */
338 if (status & RADEON_SW_INT_TEST) {
339 radeon_fence_process(rdev);
340 }
341 /* Vertical blank interrupts */
342 if (status & RADEON_CRTC_VBLANK_STAT) {
343 drm_handle_vblank(rdev->ddev, 0);
344 }
345 if (status & RADEON_CRTC2_VBLANK_STAT) {
346 drm_handle_vblank(rdev->ddev, 1);
347 }
348 status = r100_irq_ack(rdev);
349 }
350 return IRQ_HANDLED;
351}
352
353u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
354{
355 if (crtc == 0)
356 return RREG32(RADEON_CRTC_CRNT_FRAME);
357 else
358 return RREG32(RADEON_CRTC2_CRNT_FRAME);
359}
360
361
771fe6b9
JG		 362/*
363 * Fence emission
364 */
365void r100_fence_ring_emit(struct radeon_device *rdev,
366 struct radeon_fence *fence)
367{
368 /* Who ever call radeon_fence_emit should call ring_lock and ask
369 * for enough space (today caller are ib schedule and buffer move) */
370 /* Wait until IDLE & CLEAN */
371 radeon_ring_write(rdev, PACKET0(0x1720, 0));
372 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
373 /* Emit fence sequence & fire IRQ */
374 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
375 radeon_ring_write(rdev, fence->seq);
376 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
377 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
378}
379
380
381/*
382 * Writeback
383 */
384int r100_wb_init(struct radeon_device *rdev)
385{
386 int r;
387
388 if (rdev->wb.wb_obj == NULL) {
389 r = radeon_object_create(rdev, NULL, 4096,
390 true,
391 RADEON_GEM_DOMAIN_GTT,
392 false, &rdev->wb.wb_obj);
393 if (r) {
394 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
395 return r;
396 }
397 r = radeon_object_pin(rdev->wb.wb_obj,
398 RADEON_GEM_DOMAIN_GTT,
399 &rdev->wb.gpu_addr);
400 if (r) {
401 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
402 return r;
403 }
404 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
405 if (r) {
406 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
407 return r;
408 }
409 }
9f022ddf
JG		 410 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
411 WREG32(R_00070C_CP_RB_RPTR_ADDR,
412 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
413 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 414 return 0;
415}
416
9f022ddf
JG		 417void r100_wb_disable(struct radeon_device *rdev)
418{
419 WREG32(R_000770_SCRATCH_UMSK, 0);
420}
421
771fe6b9
JG		 422void r100_wb_fini(struct radeon_device *rdev)
423{
9f022ddf 424 r100_wb_disable(rdev);
771fe6b9
JG		 425 if (rdev->wb.wb_obj) {
426 radeon_object_kunmap(rdev->wb.wb_obj);
427 radeon_object_unpin(rdev->wb.wb_obj);
428 radeon_object_unref(&rdev->wb.wb_obj);
429 rdev->wb.wb = NULL;
430 rdev->wb.wb_obj = NULL;
431 }
432}
433
434int r100_copy_blit(struct radeon_device *rdev,
435 uint64_t src_offset,
436 uint64_t dst_offset,
437 unsigned num_pages,
438 struct radeon_fence *fence)
439{
440 uint32_t cur_pages;
441 uint32_t stride_bytes = PAGE_SIZE;
442 uint32_t pitch;
443 uint32_t stride_pixels;
444 unsigned ndw;
445 int num_loops;
446 int r = 0;
447
448 /* radeon limited to 16k stride */
449 stride_bytes &= 0x3fff;
450 /* radeon pitch is /64 */
451 pitch = stride_bytes / 64;
452 stride_pixels = stride_bytes / 4;
453 num_loops = DIV_ROUND_UP(num_pages, 8191);
454
455 /* Ask for enough room for blit + flush + fence */
456 ndw = 64 + (10 * num_loops);
457 r = radeon_ring_lock(rdev, ndw);
458 if (r) {
459 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
460 return -EINVAL;
461 }
462 while (num_pages > 0) {
463 cur_pages = num_pages;
464 if (cur_pages > 8191) {
465 cur_pages = 8191;
466 }
467 num_pages -= cur_pages;
468
469 /* pages are in Y direction - height
470 page width in X direction - width */
471 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
472 radeon_ring_write(rdev,
473 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
474 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
475 RADEON_GMC_SRC_CLIPPING |
476 RADEON_GMC_DST_CLIPPING |
477 RADEON_GMC_BRUSH_NONE |
478 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
479 RADEON_GMC_SRC_DATATYPE_COLOR |
480 RADEON_ROP3_S |
481 RADEON_DP_SRC_SOURCE_MEMORY |
482 RADEON_GMC_CLR_CMP_CNTL_DIS |
483 RADEON_GMC_WR_MSK_DIS);
484 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
485 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
486 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
487 radeon_ring_write(rdev, 0);
488 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
489 radeon_ring_write(rdev, num_pages);
490 radeon_ring_write(rdev, num_pages);
491 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
492 }
493 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
494 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
495 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
496 radeon_ring_write(rdev,
497 RADEON_WAIT_2D_IDLECLEAN |
498 RADEON_WAIT_HOST_IDLECLEAN |
499 RADEON_WAIT_DMA_GUI_IDLE);
500 if (fence) {
501 r = radeon_fence_emit(rdev, fence);
502 }
503 radeon_ring_unlock_commit(rdev);
504 return r;
505}
506
507
508/*
509 * CP
510 */
45600232
JG		 511static int r100_cp_wait_for_idle(struct radeon_device *rdev)
512{
513 unsigned i;
514 u32 tmp;
515
516 for (i = 0; i < rdev->usec_timeout; i++) {
517 tmp = RREG32(R_000E40_RBBM_STATUS);
518 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
519 return 0;
520 }
521 udelay(1);
522 }
523 return -1;
524}
525
771fe6b9
JG		 526void r100_ring_start(struct radeon_device *rdev)
527{
528 int r;
529
530 r = radeon_ring_lock(rdev, 2);
531 if (r) {
532 return;
533 }
534 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
535 radeon_ring_write(rdev,
536 RADEON_ISYNC_ANY2D_IDLE3D |
537 RADEON_ISYNC_ANY3D_IDLE2D |
538 RADEON_ISYNC_WAIT_IDLEGUI |
539 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
540 radeon_ring_unlock_commit(rdev);
541}
542
70967ab9
BH		 543
544/* Load the microcode for the CP */
545static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 546{
70967ab9
BH		 547 struct platform_device *pdev;
548 const char *fw_name = NULL;
549 int err;
771fe6b9 550
70967ab9 551 DRM_DEBUG("\n");
771fe6b9 552
70967ab9
BH		 553 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
554 err = IS_ERR(pdev);
555 if (err) {
556 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
557 return -EINVAL;
558 }
771fe6b9
JG		 559 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
560 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
561 (rdev->family == CHIP_RS200)) {
562 DRM_INFO("Loading R100 Microcode\n");
70967ab9 563 fw_name = FIRMWARE_R100;
771fe6b9
JG		 564 } else if ((rdev->family == CHIP_R200) ||
565 (rdev->family == CHIP_RV250) ||
566 (rdev->family == CHIP_RV280) ||
567 (rdev->family == CHIP_RS300)) {
568 DRM_INFO("Loading R200 Microcode\n");
70967ab9 569 fw_name = FIRMWARE_R200;
771fe6b9
JG		 570 } else if ((rdev->family == CHIP_R300) ||
571 (rdev->family == CHIP_R350) ||
572 (rdev->family == CHIP_RV350) ||
573 (rdev->family == CHIP_RV380) ||
574 (rdev->family == CHIP_RS400) ||
575 (rdev->family == CHIP_RS480)) {
576 DRM_INFO("Loading R300 Microcode\n");
70967ab9 577 fw_name = FIRMWARE_R300;
771fe6b9
JG		 578 } else if ((rdev->family == CHIP_R420) ||
579 (rdev->family == CHIP_R423) ||
580 (rdev->family == CHIP_RV410)) {
581 DRM_INFO("Loading R400 Microcode\n");
70967ab9 582 fw_name = FIRMWARE_R420;
771fe6b9
JG		 583 } else if ((rdev->family == CHIP_RS690) ||
584 (rdev->family == CHIP_RS740)) {
585 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 586 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 587 } else if (rdev->family == CHIP_RS600) {
588 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 589 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 590 } else if ((rdev->family == CHIP_RV515) ||
591 (rdev->family == CHIP_R520) ||
592 (rdev->family == CHIP_RV530) ||
593 (rdev->family == CHIP_R580) ||
594 (rdev->family == CHIP_RV560) ||
595 (rdev->family == CHIP_RV570)) {
596 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 597 fw_name = FIRMWARE_R520;
598 }
599
3ce0a23d 600 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 601 platform_device_unregister(pdev);
602 if (err) {
603 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
604 fw_name);
3ce0a23d 605 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 606 printk(KERN_ERR
607 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 608 rdev->me_fw->size, fw_name);
70967ab9 609 err = -EINVAL;
3ce0a23d
JG		 610 release_firmware(rdev->me_fw);
611 rdev->me_fw = NULL;
70967ab9
BH		 612 }
613 return err;
614}
615static void r100_cp_load_microcode(struct radeon_device *rdev)
616{
617 const __be32 *fw_data;
618 int i, size;
619
620 if (r100_gui_wait_for_idle(rdev)) {
621 printk(KERN_WARNING "Failed to wait GUI idle while "
622 "programming pipes. Bad things might happen.\n");
623 }
624
3ce0a23d
JG		 625 if (rdev->me_fw) {
626 size = rdev->me_fw->size / 4;
627 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 628 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
629 for (i = 0; i < size; i += 2) {
630 WREG32(RADEON_CP_ME_RAM_DATAH,
631 be32_to_cpup(&fw_data[i]));
632 WREG32(RADEON_CP_ME_RAM_DATAL,
633 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 634 }
635 }
636}
637
638int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
639{
640 unsigned rb_bufsz;
641 unsigned rb_blksz;
642 unsigned max_fetch;
643 unsigned pre_write_timer;
644 unsigned pre_write_limit;
645 unsigned indirect2_start;
646 unsigned indirect1_start;
647 uint32_t tmp;
648 int r;
649
650 if (r100_debugfs_cp_init(rdev)) {
651 DRM_ERROR("Failed to register debugfs file for CP !\n");
652 }
653 /* Reset CP */
654 tmp = RREG32(RADEON_CP_CSQ_STAT);
655 if ((tmp & (1 << 31))) {
656 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
657 WREG32(RADEON_CP_CSQ_MODE, 0);
658 WREG32(RADEON_CP_CSQ_CNTL, 0);
659 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
660 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
661 mdelay(2);
662 WREG32(RADEON_RBBM_SOFT_RESET, 0);
663 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
664 mdelay(2);
665 tmp = RREG32(RADEON_CP_CSQ_STAT);
666 if ((tmp & (1 << 31))) {
667 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
668 }
669 } else {
670 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
671 }
70967ab9 672
3ce0a23d 673 if (!rdev->me_fw) {
70967ab9
BH		 674 r = r100_cp_init_microcode(rdev);
675 if (r) {
676 DRM_ERROR("Failed to load firmware!\n");
677 return r;
678 }
679 }
680
771fe6b9
JG		 681 /* Align ring size */
682 rb_bufsz = drm_order(ring_size / 8);
683 ring_size = (1 << (rb_bufsz + 1)) * 4;
684 r100_cp_load_microcode(rdev);
685 r = radeon_ring_init(rdev, ring_size);
686 if (r) {
687 return r;
688 }
689 /* Each time the cp read 1024 bytes (16 dword/quadword) update
690 * the rptr copy in system ram */
691 rb_blksz = 9;
692 /* cp will read 128bytes at a time (4 dwords) */
693 max_fetch = 1;
694 rdev->cp.align_mask = 16 - 1;
695 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
696 pre_write_timer = 64;
697 /* Force CP_RB_WPTR write if written more than one time before the
698 * delay expire
699 */
700 pre_write_limit = 0;
701 /* Setup the cp cache like this (cache size is 96 dwords) :
702 * RING 0 to 15
703 * INDIRECT1 16 to 79
704 * INDIRECT2 80 to 95
705 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
706 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
707 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
708 * Idea being that most of the gpu cmd will be through indirect1 buffer
709 * so it gets the bigger cache.
710 */
711 indirect2_start = 80;
712 indirect1_start = 16;
713 /* cp setup */
714 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
715 WREG32(RADEON_CP_RB_CNTL,
4e484e7d
MD		 716#ifdef __BIG_ENDIAN
717 RADEON_BUF_SWAP_32BIT |
718#endif
771fe6b9
JG		 719 REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
720 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
721 REG_SET(RADEON_MAX_FETCH, max_fetch) |
722 RADEON_RB_NO_UPDATE);
723 /* Set ring address */
724 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
725 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
726 /* Force read & write ptr to 0 */
727 tmp = RREG32(RADEON_CP_RB_CNTL);
728 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
729 WREG32(RADEON_CP_RB_RPTR_WR, 0);
730 WREG32(RADEON_CP_RB_WPTR, 0);
731 WREG32(RADEON_CP_RB_CNTL, tmp);
732 udelay(10);
733 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
734 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
735 /* Set cp mode to bus mastering & enable cp*/
736 WREG32(RADEON_CP_CSQ_MODE,
737 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
738 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
739 WREG32(0x718, 0);
740 WREG32(0x744, 0x00004D4D);
741 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
742 radeon_ring_start(rdev);
743 r = radeon_ring_test(rdev);
744 if (r) {
745 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
746 return r;
747 }
748 rdev->cp.ready = true;
749 return 0;
750}
751
752void r100_cp_fini(struct radeon_device *rdev)
753{
45600232
JG		 754 if (r100_cp_wait_for_idle(rdev)) {
755 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
756 }
771fe6b9 757 /* Disable ring */
a18d7ea1 758 r100_cp_disable(rdev);
771fe6b9
JG		 759 radeon_ring_fini(rdev);
760 DRM_INFO("radeon: cp finalized\n");
761}
762
763void r100_cp_disable(struct radeon_device *rdev)
764{
765 /* Disable ring */
766 rdev->cp.ready = false;
767 WREG32(RADEON_CP_CSQ_MODE, 0);
768 WREG32(RADEON_CP_CSQ_CNTL, 0);
769 if (r100_gui_wait_for_idle(rdev)) {
770 printk(KERN_WARNING "Failed to wait GUI idle while "
771 "programming pipes. Bad things might happen.\n");
772 }
773}
774
775int r100_cp_reset(struct radeon_device *rdev)
776{
777 uint32_t tmp;
778 bool reinit_cp;
779 int i;
780
781 reinit_cp = rdev->cp.ready;
782 rdev->cp.ready = false;
783 WREG32(RADEON_CP_CSQ_MODE, 0);
784 WREG32(RADEON_CP_CSQ_CNTL, 0);
785 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
786 (void)RREG32(RADEON_RBBM_SOFT_RESET);
787 udelay(200);
788 WREG32(RADEON_RBBM_SOFT_RESET, 0);
789 /* Wait to prevent race in RBBM_STATUS */
790 mdelay(1);
791 for (i = 0; i < rdev->usec_timeout; i++) {
792 tmp = RREG32(RADEON_RBBM_STATUS);
793 if (!(tmp & (1 << 16))) {
794 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
795 tmp);
796 if (reinit_cp) {
797 return r100_cp_init(rdev, rdev->cp.ring_size);
798 }
799 return 0;
800 }
801 DRM_UDELAY(1);
802 }
803 tmp = RREG32(RADEON_RBBM_STATUS);
804 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
805 return -1;
806}
807
3ce0a23d
JG		 808void r100_cp_commit(struct radeon_device *rdev)
809{
810 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
811 (void)RREG32(RADEON_CP_RB_WPTR);
812}
813
771fe6b9
JG		 814
815/*
816 * CS functions
817 */
818int r100_cs_parse_packet0(struct radeon_cs_parser *p,
819 struct radeon_cs_packet *pkt,
068a117c 820 const unsigned *auth, unsigned n,
771fe6b9
JG		 821 radeon_packet0_check_t check)
822{
823 unsigned reg;
824 unsigned i, j, m;
825 unsigned idx;
826 int r;
827
828 idx = pkt->idx + 1;
829 reg = pkt->reg;
068a117c
JG		 830 /* Check that register fall into register range
831 * determined by the number of entry (n) in the
832 * safe register bitmap.
833 */
771fe6b9
JG		 834 if (pkt->one_reg_wr) {
835 if ((reg >> 7) > n) {
836 return -EINVAL;
837 }
838 } else {
839 if (((reg + (pkt->count << 2)) >> 7) > n) {
840 return -EINVAL;
841 }
842 }
843 for (i = 0; i <= pkt->count; i++, idx++) {
844 j = (reg >> 7);
845 m = 1 << ((reg >> 2) & 31);
846 if (auth[j] & m) {
847 r = check(p, pkt, idx, reg);
848 if (r) {
849 return r;
850 }
851 }
852 if (pkt->one_reg_wr) {
853 if (!(auth[j] & m)) {
854 break;
855 }
856 } else {
857 reg += 4;
858 }
859 }
860 return 0;
861}
862
771fe6b9
JG		 863void r100_cs_dump_packet(struct radeon_cs_parser *p,
864 struct radeon_cs_packet *pkt)
865{
771fe6b9
JG		 866 volatile uint32_t *ib;
867 unsigned i;
868 unsigned idx;
869
870 ib = p->ib->ptr;
771fe6b9
JG		 871 idx = pkt->idx;
872 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
873 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
874 }
875}
876
877/**
878 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
879 * @parser: parser structure holding parsing context.
880 * @pkt: where to store packet informations
881 *
882 * Assume that chunk_ib_index is properly set. Will return -EINVAL
883 * if packet is bigger than remaining ib size. or if packets is unknown.
884 **/
885int r100_cs_packet_parse(struct radeon_cs_parser *p,
886 struct radeon_cs_packet *pkt,
887 unsigned idx)
888{
889 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 890 uint32_t header;
771fe6b9
JG		 891
892 if (idx >= ib_chunk->length_dw) {
893 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
894 idx, ib_chunk->length_dw);
895 return -EINVAL;
896 }
513bcb46 897 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 898 pkt->idx = idx;
899 pkt->type = CP_PACKET_GET_TYPE(header);
900 pkt->count = CP_PACKET_GET_COUNT(header);
901 switch (pkt->type) {
902 case PACKET_TYPE0:
903 pkt->reg = CP_PACKET0_GET_REG(header);
904 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
905 break;
906 case PACKET_TYPE3:
907 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
908 break;
909 case PACKET_TYPE2:
910 pkt->count = -1;
911 break;
912 default:
913 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
914 return -EINVAL;
915 }
916 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
917 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
918 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
919 return -EINVAL;
920 }
921 return 0;
922}
923
531369e6
DA		 924/**
925 * r100_cs_packet_next_vline() - parse userspace VLINE packet
926 * @parser: parser structure holding parsing context.
927 *
928 * Userspace sends a special sequence for VLINE waits.
929 * PACKET0 - VLINE_START_END + value
930 * PACKET0 - WAIT_UNTIL +_value
931 * RELOC (P3) - crtc_id in reloc.
932 *
933 * This function parses this and relocates the VLINE START END
934 * and WAIT UNTIL packets to the correct crtc.
935 * It also detects a switched off crtc and nulls out the
936 * wait in that case.
937 */
938int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
939{
531369e6
DA		 940 struct drm_mode_object *obj;
941 struct drm_crtc *crtc;
942 struct radeon_crtc *radeon_crtc;
943 struct radeon_cs_packet p3reloc, waitreloc;
944 int crtc_id;
945 int r;
946 uint32_t header, h_idx, reg;
513bcb46 947 volatile uint32_t *ib;
531369e6 948
513bcb46 949 ib = p->ib->ptr;
531369e6
DA		 950
951 /* parse the wait until */
952 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
953 if (r)
954 return r;
955
956 /* check its a wait until and only 1 count */
957 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
958 waitreloc.count != 0) {
959 DRM_ERROR("vline wait had illegal wait until segment\n");
960 r = -EINVAL;
961 return r;
962 }
963
513bcb46 964 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 965 DRM_ERROR("vline wait had illegal wait until\n");
966 r = -EINVAL;
967 return r;
968 }
969
970 /* jump over the NOP */
971 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
972 if (r)
973 return r;
974
975 h_idx = p->idx - 2;
976 p->idx += waitreloc.count;
977 p->idx += p3reloc.count;
978
513bcb46
DA		 979 header = radeon_get_ib_value(p, h_idx);
980 crtc_id = radeon_get_ib_value(p, h_idx + 5);
981 reg = header >> 2;
531369e6
DA		 982 mutex_lock(&p->rdev->ddev->mode_config.mutex);
983 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
984 if (!obj) {
985 DRM_ERROR("cannot find crtc %d\n", crtc_id);
986 r = -EINVAL;
987 goto out;
988 }
989 crtc = obj_to_crtc(obj);
990 radeon_crtc = to_radeon_crtc(crtc);
991 crtc_id = radeon_crtc->crtc_id;
992
993 if (!crtc->enabled) {
994 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 995
996 ib[h_idx + 2] = PACKET2(0);
997 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 998 } else if (crtc_id == 1) {
999 switch (reg) {
1000 case AVIVO_D1MODE_VLINE_START_END:
1001 header &= R300_CP_PACKET0_REG_MASK;
1002 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1003 break;
1004 case RADEON_CRTC_GUI_TRIG_VLINE:
1005 header &= R300_CP_PACKET0_REG_MASK;
1006 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1007 break;
1008 default:
1009 DRM_ERROR("unknown crtc reloc\n");
1010 r = -EINVAL;
1011 goto out;
1012 }
513bcb46
DA		 1013 ib[h_idx] = header;
1014 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1015 }
1016out:
1017 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1018 return r;
1019}
1020
771fe6b9
JG		 1021/**
1022 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1023 * @parser: parser structure holding parsing context.
1024 * @data: pointer to relocation data
1025 * @offset_start: starting offset
1026 * @offset_mask: offset mask (to align start offset on)
1027 * @reloc: reloc informations
1028 *
1029 * Check next packet is relocation packet3, do bo validation and compute
1030 * GPU offset using the provided start.
1031 **/
1032int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1033 struct radeon_cs_reloc **cs_reloc)
1034{
771fe6b9
JG		 1035 struct radeon_cs_chunk *relocs_chunk;
1036 struct radeon_cs_packet p3reloc;
1037 unsigned idx;
1038 int r;
1039
1040 if (p->chunk_relocs_idx == -1) {
1041 DRM_ERROR("No relocation chunk !\n");
1042 return -EINVAL;
1043 }
1044 *cs_reloc = NULL;
771fe6b9
JG		 1045 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1046 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1047 if (r) {
1048 return r;
1049 }
1050 p->idx += p3reloc.count + 2;
1051 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1052 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1053 p3reloc.idx);
1054 r100_cs_dump_packet(p, &p3reloc);
1055 return -EINVAL;
1056 }
513bcb46 1057 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1058 if (idx >= relocs_chunk->length_dw) {
1059 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1060 idx, relocs_chunk->length_dw);
1061 r100_cs_dump_packet(p, &p3reloc);
1062 return -EINVAL;
1063 }
1064 /* FIXME: we assume reloc size is 4 dwords */
1065 *cs_reloc = p->relocs_ptr[(idx / 4)];
1066 return 0;
1067}
1068
551ebd83
DA		 1069static int r100_get_vtx_size(uint32_t vtx_fmt)
1070{
1071 int vtx_size;
1072 vtx_size = 2;
1073 /* ordered according to bits in spec */
1074 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1075 vtx_size++;
1076 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1077 vtx_size += 3;
1078 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1079 vtx_size++;
1080 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1081 vtx_size++;
1082 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1083 vtx_size += 3;
1084 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1085 vtx_size++;
1086 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1087 vtx_size++;
1088 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1089 vtx_size += 2;
1090 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1091 vtx_size += 2;
1092 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1093 vtx_size++;
1094 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1095 vtx_size += 2;
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1097 vtx_size++;
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1099 vtx_size += 2;
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1101 vtx_size++;
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1103 vtx_size++;
1104 /* blend weight */
1105 if (vtx_fmt & (0x7 << 15))
1106 vtx_size += (vtx_fmt >> 15) & 0x7;
1107 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1108 vtx_size += 3;
1109 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1110 vtx_size += 2;
1111 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1112 vtx_size++;
1113 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1114 vtx_size++;
1115 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1116 vtx_size++;
1117 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1118 vtx_size++;
1119 return vtx_size;
1120}
1121
771fe6b9 1122static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1123 struct radeon_cs_packet *pkt,
1124 unsigned idx, unsigned reg)
771fe6b9 1125{
771fe6b9 1126 struct radeon_cs_reloc *reloc;
551ebd83 1127 struct r100_cs_track *track;
771fe6b9
JG		 1128 volatile uint32_t *ib;
1129 uint32_t tmp;
771fe6b9 1130 int r;
551ebd83 1131 int i, face;
e024e110 1132 u32 tile_flags = 0;
513bcb46 1133 u32 idx_value;
771fe6b9
JG		 1134
1135 ib = p->ib->ptr;
551ebd83
DA		 1136 track = (struct r100_cs_track *)p->track;
1137
513bcb46
DA		 1138 idx_value = radeon_get_ib_value(p, idx);
1139
551ebd83
DA		 1140 switch (reg) {
1141 case RADEON_CRTC_GUI_TRIG_VLINE:
1142 r = r100_cs_packet_parse_vline(p);
1143 if (r) {
1144 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1145 idx, reg);
1146 r100_cs_dump_packet(p, pkt);
1147 return r;
1148 }
1149 break;
771fe6b9
JG		 1150 /* FIXME: only allow PACKET3 blit? easier to check for out of
1151 * range access */
551ebd83
DA		 1152 case RADEON_DST_PITCH_OFFSET:
1153 case RADEON_SRC_PITCH_OFFSET:
1154 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1155 if (r)
1156 return r;
1157 break;
1158 case RADEON_RB3D_DEPTHOFFSET:
1159 r = r100_cs_packet_next_reloc(p, &reloc);
1160 if (r) {
1161 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1162 idx, reg);
1163 r100_cs_dump_packet(p, pkt);
1164 return r;
1165 }
1166 track->zb.robj = reloc->robj;
513bcb46
DA		 1167 track->zb.offset = idx_value;
1168 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1169 break;
1170 case RADEON_RB3D_COLOROFFSET:
1171 r = r100_cs_packet_next_reloc(p, &reloc);
1172 if (r) {
1173 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1174 idx, reg);
1175 r100_cs_dump_packet(p, pkt);
1176 return r;
1177 }
1178 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1179 track->cb[0].offset = idx_value;
1180 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1181 break;
1182 case RADEON_PP_TXOFFSET_0:
1183 case RADEON_PP_TXOFFSET_1:
1184 case RADEON_PP_TXOFFSET_2:
1185 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1186 r = r100_cs_packet_next_reloc(p, &reloc);
1187 if (r) {
1188 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1189 idx, reg);
1190 r100_cs_dump_packet(p, pkt);
1191 return r;
1192 }
513bcb46 1193 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1194 track->textures[i].robj = reloc->robj;
1195 break;
1196 case RADEON_PP_CUBIC_OFFSET_T0_0:
1197 case RADEON_PP_CUBIC_OFFSET_T0_1:
1198 case RADEON_PP_CUBIC_OFFSET_T0_2:
1199 case RADEON_PP_CUBIC_OFFSET_T0_3:
1200 case RADEON_PP_CUBIC_OFFSET_T0_4:
1201 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1202 r = r100_cs_packet_next_reloc(p, &reloc);
1203 if (r) {
1204 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1205 idx, reg);
1206 r100_cs_dump_packet(p, pkt);
1207 return r;
1208 }
513bcb46
DA		 1209 track->textures[0].cube_info[i].offset = idx_value;
1210 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1211 track->textures[0].cube_info[i].robj = reloc->robj;
1212 break;
1213 case RADEON_PP_CUBIC_OFFSET_T1_0:
1214 case RADEON_PP_CUBIC_OFFSET_T1_1:
1215 case RADEON_PP_CUBIC_OFFSET_T1_2:
1216 case RADEON_PP_CUBIC_OFFSET_T1_3:
1217 case RADEON_PP_CUBIC_OFFSET_T1_4:
1218 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1219 r = r100_cs_packet_next_reloc(p, &reloc);
1220 if (r) {
1221 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1222 idx, reg);
1223 r100_cs_dump_packet(p, pkt);
1224 return r;
1225 }
513bcb46
DA		 1226 track->textures[1].cube_info[i].offset = idx_value;
1227 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1228 track->textures[1].cube_info[i].robj = reloc->robj;
1229 break;
1230 case RADEON_PP_CUBIC_OFFSET_T2_0:
1231 case RADEON_PP_CUBIC_OFFSET_T2_1:
1232 case RADEON_PP_CUBIC_OFFSET_T2_2:
1233 case RADEON_PP_CUBIC_OFFSET_T2_3:
1234 case RADEON_PP_CUBIC_OFFSET_T2_4:
1235 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1236 r = r100_cs_packet_next_reloc(p, &reloc);
1237 if (r) {
1238 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1239 idx, reg);
1240 r100_cs_dump_packet(p, pkt);
1241 return r;
1242 }
513bcb46
DA		 1243 track->textures[2].cube_info[i].offset = idx_value;
1244 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1245 track->textures[2].cube_info[i].robj = reloc->robj;
1246 break;
1247 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1248 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1249 break;
1250 case RADEON_RB3D_COLORPITCH:
1251 r = r100_cs_packet_next_reloc(p, &reloc);
1252 if (r) {
1253 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1254 idx, reg);
1255 r100_cs_dump_packet(p, pkt);
1256 return r;
1257 }
e024e110 1258
551ebd83
DA		 1259 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1260 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1261 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1262 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1263
513bcb46 1264 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1265 tmp |= tile_flags;
1266 ib[idx] = tmp;
e024e110 1267
513bcb46 1268 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1269 break;
1270 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1271 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1272 break;
1273 case RADEON_RB3D_CNTL:
513bcb46 1274 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1275 case 7:
1276 case 8:
1277 case 9:
1278 case 11:
1279 case 12:
1280 track->cb[0].cpp = 1;
e024e110 1281 break;
551ebd83
DA		 1282 case 3:
1283 case 4:
1284 case 15:
1285 track->cb[0].cpp = 2;
1286 break;
1287 case 6:
1288 track->cb[0].cpp = 4;
1289 break;
1290 default:
1291 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1292 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1293 return -EINVAL;
1294 }
513bcb46 1295 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1296 break;
1297 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1298 switch (idx_value & 0xf) {
551ebd83
DA		 1299 case 0:
1300 track->zb.cpp = 2;
1301 break;
1302 case 2:
1303 case 3:
1304 case 4:
1305 case 5:
1306 case 9:
1307 case 11:
1308 track->zb.cpp = 4;
17782d99 1309 break;
771fe6b9 1310 default:
771fe6b9
JG		 1311 break;
1312 }
551ebd83
DA		 1313 break;
1314 case RADEON_RB3D_ZPASS_ADDR:
1315 r = r100_cs_packet_next_reloc(p, &reloc);
1316 if (r) {
1317 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1318 idx, reg);
1319 r100_cs_dump_packet(p, pkt);
1320 return r;
1321 }
513bcb46 1322 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1323 break;
1324 case RADEON_PP_CNTL:
1325 {
513bcb46 1326 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1327 for (i = 0; i < track->num_texture; i++)
1328 track->textures[i].enabled = !!(temp & (1 << i));
1329 }
1330 break;
1331 case RADEON_SE_VF_CNTL:
513bcb46 1332 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1333 break;
1334 case RADEON_SE_VTX_FMT:
513bcb46 1335 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1336 break;
1337 case RADEON_PP_TEX_SIZE_0:
1338 case RADEON_PP_TEX_SIZE_1:
1339 case RADEON_PP_TEX_SIZE_2:
1340 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1341 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1342 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1343 break;
1344 case RADEON_PP_TEX_PITCH_0:
1345 case RADEON_PP_TEX_PITCH_1:
1346 case RADEON_PP_TEX_PITCH_2:
1347 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1348 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1349 break;
1350 case RADEON_PP_TXFILTER_0:
1351 case RADEON_PP_TXFILTER_1:
1352 case RADEON_PP_TXFILTER_2:
1353 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1354 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1355 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1356 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1357 if (tmp == 2 || tmp == 6)
1358 track->textures[i].roundup_w = false;
513bcb46 1359 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1360 if (tmp == 2 || tmp == 6)
1361 track->textures[i].roundup_h = false;
1362 break;
1363 case RADEON_PP_TXFORMAT_0:
1364 case RADEON_PP_TXFORMAT_1:
1365 case RADEON_PP_TXFORMAT_2:
1366 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1367 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1368 track->textures[i].use_pitch = 1;
1369 } else {
1370 track->textures[i].use_pitch = 0;
513bcb46
DA		 1371 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1372 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1373 }
513bcb46 1374 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1375 track->textures[i].tex_coord_type = 2;
513bcb46 1376 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1377 case RADEON_TXFORMAT_I8:
1378 case RADEON_TXFORMAT_RGB332:
1379 case RADEON_TXFORMAT_Y8:
1380 track->textures[i].cpp = 1;
1381 break;
1382 case RADEON_TXFORMAT_AI88:
1383 case RADEON_TXFORMAT_ARGB1555:
1384 case RADEON_TXFORMAT_RGB565:
1385 case RADEON_TXFORMAT_ARGB4444:
1386 case RADEON_TXFORMAT_VYUY422:
1387 case RADEON_TXFORMAT_YVYU422:
1388 case RADEON_TXFORMAT_DXT1:
1389 case RADEON_TXFORMAT_SHADOW16:
1390 case RADEON_TXFORMAT_LDUDV655:
1391 case RADEON_TXFORMAT_DUDV88:
1392 track->textures[i].cpp = 2;
771fe6b9 1393 break;
551ebd83
DA		 1394 case RADEON_TXFORMAT_ARGB8888:
1395 case RADEON_TXFORMAT_RGBA8888:
1396 case RADEON_TXFORMAT_DXT23:
1397 case RADEON_TXFORMAT_DXT45:
1398 case RADEON_TXFORMAT_SHADOW32:
1399 case RADEON_TXFORMAT_LDUDUV8888:
1400 track->textures[i].cpp = 4;
1401 break;
1402 }
513bcb46
DA		 1403 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1404 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1405 break;
1406 case RADEON_PP_CUBIC_FACES_0:
1407 case RADEON_PP_CUBIC_FACES_1:
1408 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1409 tmp = idx_value;
551ebd83
DA		 1410 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1411 for (face = 0; face < 4; face++) {
1412 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1413 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1414 }
551ebd83
DA		 1415 break;
1416 default:
1417 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1418 reg, idx);
1419 return -EINVAL;
771fe6b9
JG		 1420 }
1421 return 0;
1422}
1423
068a117c
JG		 1424int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1425 struct radeon_cs_packet *pkt,
1426 struct radeon_object *robj)
1427{
068a117c 1428 unsigned idx;
513bcb46 1429 u32 value;
068a117c 1430 idx = pkt->idx + 1;
513bcb46
DA		 1431 value = radeon_get_ib_value(p, idx + 2);
1432 if ((value + 1) > radeon_object_size(robj)) {
068a117c
JG		 1433 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1434 "(need %u have %lu) !\n",
513bcb46 1435 value + 1,
068a117c
JG		 1436 radeon_object_size(robj));
1437 return -EINVAL;
1438 }
1439 return 0;
1440}
1441
771fe6b9
JG		 1442static int r100_packet3_check(struct radeon_cs_parser *p,
1443 struct radeon_cs_packet *pkt)
1444{
771fe6b9 1445 struct radeon_cs_reloc *reloc;
551ebd83 1446 struct r100_cs_track *track;
771fe6b9 1447 unsigned idx;
771fe6b9
JG		 1448 volatile uint32_t *ib;
1449 int r;
1450
1451 ib = p->ib->ptr;
771fe6b9 1452 idx = pkt->idx + 1;
551ebd83 1453 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1454 switch (pkt->opcode) {
1455 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1456 r = r100_packet3_load_vbpntr(p, pkt, idx);
1457 if (r)
1458 return r;
771fe6b9
JG		 1459 break;
1460 case PACKET3_INDX_BUFFER:
1461 r = r100_cs_packet_next_reloc(p, &reloc);
1462 if (r) {
1463 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1464 r100_cs_dump_packet(p, pkt);
1465 return r;
1466 }
513bcb46 1467 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1468 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1469 if (r) {
1470 return r;
1471 }
771fe6b9
JG		 1472 break;
1473 case 0x23:
771fe6b9
JG		 1474 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1475 r = r100_cs_packet_next_reloc(p, &reloc);
1476 if (r) {
1477 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1478 r100_cs_dump_packet(p, pkt);
1479 return r;
1480 }
513bcb46 1481 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1482 track->num_arrays = 1;
513bcb46 1483 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1484
1485 track->arrays[0].robj = reloc->robj;
1486 track->arrays[0].esize = track->vtx_size;
1487
513bcb46 1488 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1489
513bcb46 1490 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1491 track->immd_dwords = pkt->count - 1;
1492 r = r100_cs_track_check(p->rdev, track);
1493 if (r)
1494 return r;
771fe6b9
JG		 1495 break;
1496 case PACKET3_3D_DRAW_IMMD:
513bcb46 1497 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1498 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1499 return -EINVAL;
1500 }
513bcb46 1501 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1502 track->immd_dwords = pkt->count - 1;
1503 r = r100_cs_track_check(p->rdev, track);
1504 if (r)
1505 return r;
1506 break;
771fe6b9
JG		 1507 /* triggers drawing using in-packet vertex data */
1508 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1509 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1510 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1511 return -EINVAL;
1512 }
513bcb46 1513 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1514 track->immd_dwords = pkt->count;
1515 r = r100_cs_track_check(p->rdev, track);
1516 if (r)
1517 return r;
1518 break;
771fe6b9
JG		 1519 /* triggers drawing using in-packet vertex data */
1520 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1521 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1522 r = r100_cs_track_check(p->rdev, track);
1523 if (r)
1524 return r;
1525 break;
771fe6b9
JG		 1526 /* triggers drawing of vertex buffers setup elsewhere */
1527 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1528 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1529 r = r100_cs_track_check(p->rdev, track);
1530 if (r)
1531 return r;
1532 break;
771fe6b9
JG		 1533 /* triggers drawing using indices to vertex buffer */
1534 case PACKET3_3D_DRAW_VBUF:
513bcb46 1535 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1536 r = r100_cs_track_check(p->rdev, track);
1537 if (r)
1538 return r;
1539 break;
771fe6b9
JG		 1540 /* triggers drawing of vertex buffers setup elsewhere */
1541 case PACKET3_3D_DRAW_INDX:
513bcb46 1542 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1543 r = r100_cs_track_check(p->rdev, track);
1544 if (r)
1545 return r;
1546 break;
771fe6b9
JG		 1547 /* triggers drawing using indices to vertex buffer */
1548 case PACKET3_NOP:
1549 break;
1550 default:
1551 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1552 return -EINVAL;
1553 }
1554 return 0;
1555}
1556
1557int r100_cs_parse(struct radeon_cs_parser *p)
1558{
1559 struct radeon_cs_packet pkt;
9f022ddf 1560 struct r100_cs_track *track;
771fe6b9
JG		 1561 int r;
1562
9f022ddf
JG		 1563 track = kzalloc(sizeof(*track), GFP_KERNEL);
1564 r100_cs_track_clear(p->rdev, track);
1565 p->track = track;
771fe6b9
JG		 1566 do {
1567 r = r100_cs_packet_parse(p, &pkt, p->idx);
1568 if (r) {
1569 return r;
1570 }
1571 p->idx += pkt.count + 2;
1572 switch (pkt.type) {
068a117c 1573 case PACKET_TYPE0:
551ebd83
DA		 1574 if (p->rdev->family >= CHIP_R200)
1575 r = r100_cs_parse_packet0(p, &pkt,
1576 p->rdev->config.r100.reg_safe_bm,
1577 p->rdev->config.r100.reg_safe_bm_size,
1578 &r200_packet0_check);
1579 else
1580 r = r100_cs_parse_packet0(p, &pkt,
1581 p->rdev->config.r100.reg_safe_bm,
1582 p->rdev->config.r100.reg_safe_bm_size,
1583 &r100_packet0_check);
068a117c
JG		 1584 break;
1585 case PACKET_TYPE2:
1586 break;
1587 case PACKET_TYPE3:
1588 r = r100_packet3_check(p, &pkt);
1589 break;
1590 default:
1591 DRM_ERROR("Unknown packet type %d !\n",
1592 pkt.type);
1593 return -EINVAL;
771fe6b9
JG		 1594 }
1595 if (r) {
1596 return r;
1597 }
1598 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1599 return 0;
1600}
1601
1602
1603/*
1604 * Global GPU functions
1605 */
1606void r100_errata(struct radeon_device *rdev)
1607{
1608 rdev->pll_errata = 0;
1609
1610 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1611 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1612 }
1613
1614 if (rdev->family == CHIP_RV100 ||
1615 rdev->family == CHIP_RS100 ||
1616 rdev->family == CHIP_RS200) {
1617 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1618 }
1619}
1620
1621/* Wait for vertical sync on primary CRTC */
1622void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1623{
1624 uint32_t crtc_gen_cntl, tmp;
1625 int i;
1626
1627 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1628 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1629 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1630 return;
1631 }
1632 /* Clear the CRTC_VBLANK_SAVE bit */
1633 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1634 for (i = 0; i < rdev->usec_timeout; i++) {
1635 tmp = RREG32(RADEON_CRTC_STATUS);
1636 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1637 return;
1638 }
1639 DRM_UDELAY(1);
1640 }
1641}
1642
1643/* Wait for vertical sync on secondary CRTC */
1644void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1645{
1646 uint32_t crtc2_gen_cntl, tmp;
1647 int i;
1648
1649 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1650 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1651 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1652 return;
1653
1654 /* Clear the CRTC_VBLANK_SAVE bit */
1655 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1656 for (i = 0; i < rdev->usec_timeout; i++) {
1657 tmp = RREG32(RADEON_CRTC2_STATUS);
1658 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1659 return;
1660 }
1661 DRM_UDELAY(1);
1662 }
1663}
1664
1665int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1666{
1667 unsigned i;
1668 uint32_t tmp;
1669
1670 for (i = 0; i < rdev->usec_timeout; i++) {
1671 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1672 if (tmp >= n) {
1673 return 0;
1674 }
1675 DRM_UDELAY(1);
1676 }
1677 return -1;
1678}
1679
1680int r100_gui_wait_for_idle(struct radeon_device *rdev)
1681{
1682 unsigned i;
1683 uint32_t tmp;
1684
1685 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1686 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1687 " Bad things might happen.\n");
1688 }
1689 for (i = 0; i < rdev->usec_timeout; i++) {
1690 tmp = RREG32(RADEON_RBBM_STATUS);
1691 if (!(tmp & (1 << 31))) {
1692 return 0;
1693 }
1694 DRM_UDELAY(1);
1695 }
1696 return -1;
1697}
1698
1699int r100_mc_wait_for_idle(struct radeon_device *rdev)
1700{
1701 unsigned i;
1702 uint32_t tmp;
1703
1704 for (i = 0; i < rdev->usec_timeout; i++) {
1705 /* read MC_STATUS */
1706 tmp = RREG32(0x0150);
1707 if (tmp & (1 << 2)) {
1708 return 0;
1709 }
1710 DRM_UDELAY(1);
1711 }
1712 return -1;
1713}
1714
1715void r100_gpu_init(struct radeon_device *rdev)
1716{
1717 /* TODO: anythings to do here ? pipes ? */
1718 r100_hdp_reset(rdev);
1719}
1720
1721void r100_hdp_reset(struct radeon_device *rdev)
1722{
1723 uint32_t tmp;
1724
1725 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1726 tmp |= (7 << 28);
1727 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1728 (void)RREG32(RADEON_HOST_PATH_CNTL);
1729 udelay(200);
1730 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1731 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1732 (void)RREG32(RADEON_HOST_PATH_CNTL);
1733}
1734
1735int r100_rb2d_reset(struct radeon_device *rdev)
1736{
1737 uint32_t tmp;
1738 int i;
1739
1740 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1741 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1742 udelay(200);
1743 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1744 /* Wait to prevent race in RBBM_STATUS */
1745 mdelay(1);
1746 for (i = 0; i < rdev->usec_timeout; i++) {
1747 tmp = RREG32(RADEON_RBBM_STATUS);
1748 if (!(tmp & (1 << 26))) {
1749 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1750 tmp);
1751 return 0;
1752 }
1753 DRM_UDELAY(1);
1754 }
1755 tmp = RREG32(RADEON_RBBM_STATUS);
1756 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1757 return -1;
1758}
1759
1760int r100_gpu_reset(struct radeon_device *rdev)
1761{
1762 uint32_t status;
1763
1764 /* reset order likely matter */
1765 status = RREG32(RADEON_RBBM_STATUS);
1766 /* reset HDP */
1767 r100_hdp_reset(rdev);
1768 /* reset rb2d */
1769 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1770 r100_rb2d_reset(rdev);
1771 }
1772 /* TODO: reset 3D engine */
1773 /* reset CP */
1774 status = RREG32(RADEON_RBBM_STATUS);
1775 if (status & (1 << 16)) {
1776 r100_cp_reset(rdev);
1777 }
1778 /* Check if GPU is idle */
1779 status = RREG32(RADEON_RBBM_STATUS);
1780 if (status & (1 << 31)) {
1781 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1782 return -1;
1783 }
1784 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1785 return 0;
1786}
1787
1788
1789/*
1790 * VRAM info
1791 */
1792static void r100_vram_get_type(struct radeon_device *rdev)
1793{
1794 uint32_t tmp;
1795
1796 rdev->mc.vram_is_ddr = false;
1797 if (rdev->flags & RADEON_IS_IGP)
1798 rdev->mc.vram_is_ddr = true;
1799 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1800 rdev->mc.vram_is_ddr = true;
1801 if ((rdev->family == CHIP_RV100) ||
1802 (rdev->family == CHIP_RS100) ||
1803 (rdev->family == CHIP_RS200)) {
1804 tmp = RREG32(RADEON_MEM_CNTL);
1805 if (tmp & RV100_HALF_MODE) {
1806 rdev->mc.vram_width = 32;
1807 } else {
1808 rdev->mc.vram_width = 64;
1809 }
1810 if (rdev->flags & RADEON_SINGLE_CRTC) {
1811 rdev->mc.vram_width /= 4;
1812 rdev->mc.vram_is_ddr = true;
1813 }
1814 } else if (rdev->family <= CHIP_RV280) {
1815 tmp = RREG32(RADEON_MEM_CNTL);
1816 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1817 rdev->mc.vram_width = 128;
1818 } else {
1819 rdev->mc.vram_width = 64;
1820 }
1821 } else {
1822 /* newer IGPs */
1823 rdev->mc.vram_width = 128;
1824 }
1825}
1826
2a0f8918 1827static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1828{
2a0f8918
DA		 1829 u32 aper_size;
1830 u8 byte;
1831
1832 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1833
1834 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1835 * that is has the 2nd generation multifunction PCI interface
1836 */
1837 if (rdev->family == CHIP_RV280 ||
1838 rdev->family >= CHIP_RV350) {
1839 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1840 ~RADEON_HDP_APER_CNTL);
1841 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1842 return aper_size * 2;
1843 }
1844
1845 /* Older cards have all sorts of funny issues to deal with. First
1846 * check if it's a multifunction card by reading the PCI config
1847 * header type... Limit those to one aperture size
1848 */
1849 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1850 if (byte & 0x80) {
1851 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1852 DRM_INFO("Limiting VRAM to one aperture\n");
1853 return aper_size;
1854 }
1855
1856 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1857 * have set it up. We don't write this as it's broken on some ASICs but
1858 * we expect the BIOS to have done the right thing (might be too optimistic...)
1859 */
1860 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1861 return aper_size * 2;
1862 return aper_size;
1863}
1864
1865void r100_vram_init_sizes(struct radeon_device *rdev)
1866{
1867 u64 config_aper_size;
1868 u32 accessible;
1869
1870 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1871
1872 if (rdev->flags & RADEON_IS_IGP) {
1873 uint32_t tom;
1874 /* read NB_TOM to get the amount of ram stolen for the GPU */
1875 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1876 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
3e43d821
DA		 1877 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1878 rdev->mc.vram_location = (tom & 0xffff) << 16;
7a50f01a
DA		 1879 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1880 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1881 } else {
7a50f01a 1882 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1883 /* Some production boards of m6 will report 0
1884 * if it's 8 MB
1885 */
7a50f01a
DA		 1886 if (rdev->mc.real_vram_size == 0) {
1887 rdev->mc.real_vram_size = 8192 * 1024;
1888 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1889 }
3e43d821
DA		 1890 /* let driver place VRAM */
1891 rdev->mc.vram_location = 0xFFFFFFFFUL;
2a0f8918
DA		 1892 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1893 * Novell bug 204882 + along with lots of ubuntu ones */
7a50f01a
DA		 1894 if (config_aper_size > rdev->mc.real_vram_size)
1895 rdev->mc.mc_vram_size = config_aper_size;
1896 else
1897 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 1898 }
1899
2a0f8918
DA		 1900 /* work out accessible VRAM */
1901 accessible = r100_get_accessible_vram(rdev);
1902
771fe6b9
JG		 1903 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1904 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2a0f8918
DA		 1905
1906 if (accessible > rdev->mc.aper_size)
1907 accessible = rdev->mc.aper_size;
1908
7a50f01a
DA		 1909 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1910 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1911
1912 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1913 rdev->mc.real_vram_size = rdev->mc.aper_size;
2a0f8918
DA		 1914}
1915
1916void r100_vram_info(struct radeon_device *rdev)
1917{
1918 r100_vram_get_type(rdev);
1919
1920 r100_vram_init_sizes(rdev);
771fe6b9
JG		 1921}
1922
1923
1924/*
1925 * Indirect registers accessor
1926 */
1927void r100_pll_errata_after_index(struct radeon_device *rdev)
1928{
1929 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1930 return;
1931 }
1932 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1933 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1934}
1935
1936static void r100_pll_errata_after_data(struct radeon_device *rdev)
1937{
1938 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1939 * or the chip could hang on a subsequent access
1940 */
1941 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1942 udelay(5000);
1943 }
1944
1945 /* This function is required to workaround a hardware bug in some (all?)
1946 * revisions of the R300. This workaround should be called after every
1947 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1948 * may not be correct.
1949 */
1950 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1951 uint32_t save, tmp;
1952
1953 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1954 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1955 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1956 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1957 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1958 }
1959}
1960
1961uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1962{
1963 uint32_t data;
1964
1965 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1966 r100_pll_errata_after_index(rdev);
1967 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1968 r100_pll_errata_after_data(rdev);
1969 return data;
1970}
1971
1972void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1973{
1974 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1975 r100_pll_errata_after_index(rdev);
1976 WREG32(RADEON_CLOCK_CNTL_DATA, v);
1977 r100_pll_errata_after_data(rdev);
1978}
1979
068a117c
JG		 1980int r100_init(struct radeon_device *rdev)
1981{
551ebd83
DA		 1982 if (ASIC_IS_RN50(rdev)) {
1983 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
1984 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
1985 } else if (rdev->family < CHIP_R200) {
1986 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
1987 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
1988 } else {
1989 return r200_init(rdev);
1990 }
068a117c
JG		 1991 return 0;
1992}
1993
771fe6b9
JG		 1994/*
1995 * Debugfs info
1996 */
1997#if defined(CONFIG_DEBUG_FS)
1998static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1999{
2000 struct drm_info_node *node = (struct drm_info_node *) m->private;
2001 struct drm_device *dev = node->minor->dev;
2002 struct radeon_device *rdev = dev->dev_private;
2003 uint32_t reg, value;
2004 unsigned i;
2005
2006 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2007 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2008 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2009 for (i = 0; i < 64; i++) {
2010 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2011 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2012 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2013 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2014 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2015 }
2016 return 0;
2017}
2018
2019static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2020{
2021 struct drm_info_node *node = (struct drm_info_node *) m->private;
2022 struct drm_device *dev = node->minor->dev;
2023 struct radeon_device *rdev = dev->dev_private;
2024 uint32_t rdp, wdp;
2025 unsigned count, i, j;
2026
2027 radeon_ring_free_size(rdev);
2028 rdp = RREG32(RADEON_CP_RB_RPTR);
2029 wdp = RREG32(RADEON_CP_RB_WPTR);
2030 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2031 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2032 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2033 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2034 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2035 seq_printf(m, "%u dwords in ring\n", count);
2036 for (j = 0; j <= count; j++) {
2037 i = (rdp + j) & rdev->cp.ptr_mask;
2038 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2039 }
2040 return 0;
2041}
2042
2043
2044static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2045{
2046 struct drm_info_node *node = (struct drm_info_node *) m->private;
2047 struct drm_device *dev = node->minor->dev;
2048 struct radeon_device *rdev = dev->dev_private;
2049 uint32_t csq_stat, csq2_stat, tmp;
2050 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2051 unsigned i;
2052
2053 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2054 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2055 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2056 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2057 r_rptr = (csq_stat >> 0) & 0x3ff;
2058 r_wptr = (csq_stat >> 10) & 0x3ff;
2059 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2060 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2061 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2062 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2063 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2064 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2065 seq_printf(m, "Ring rptr %u\n", r_rptr);
2066 seq_printf(m, "Ring wptr %u\n", r_wptr);
2067 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2068 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2069 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2070 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2071 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2072 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2073 seq_printf(m, "Ring fifo:\n");
2074 for (i = 0; i < 256; i++) {
2075 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2076 tmp = RREG32(RADEON_CP_CSQ_DATA);
2077 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2078 }
2079 seq_printf(m, "Indirect1 fifo:\n");
2080 for (i = 256; i <= 512; i++) {
2081 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2082 tmp = RREG32(RADEON_CP_CSQ_DATA);
2083 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2084 }
2085 seq_printf(m, "Indirect2 fifo:\n");
2086 for (i = 640; i < ib1_wptr; i++) {
2087 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2088 tmp = RREG32(RADEON_CP_CSQ_DATA);
2089 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2090 }
2091 return 0;
2092}
2093
2094static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2095{
2096 struct drm_info_node *node = (struct drm_info_node *) m->private;
2097 struct drm_device *dev = node->minor->dev;
2098 struct radeon_device *rdev = dev->dev_private;
2099 uint32_t tmp;
2100
2101 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2102 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2103 tmp = RREG32(RADEON_MC_FB_LOCATION);
2104 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2105 tmp = RREG32(RADEON_BUS_CNTL);
2106 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2107 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2108 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2109 tmp = RREG32(RADEON_AGP_BASE);
2110 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2111 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2112 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2113 tmp = RREG32(0x01D0);
2114 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2115 tmp = RREG32(RADEON_AIC_LO_ADDR);
2116 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2117 tmp = RREG32(RADEON_AIC_HI_ADDR);
2118 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2119 tmp = RREG32(0x01E4);
2120 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2121 return 0;
2122}
2123
2124static struct drm_info_list r100_debugfs_rbbm_list[] = {
2125 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2126};
2127
2128static struct drm_info_list r100_debugfs_cp_list[] = {
2129 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2130 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2131};
2132
2133static struct drm_info_list r100_debugfs_mc_info_list[] = {
2134 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2135};
2136#endif
2137
2138int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2139{
2140#if defined(CONFIG_DEBUG_FS)
2141 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2142#else
2143 return 0;
2144#endif
2145}
2146
2147int r100_debugfs_cp_init(struct radeon_device *rdev)
2148{
2149#if defined(CONFIG_DEBUG_FS)
2150 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2151#else
2152 return 0;
2153#endif
2154}
2155
2156int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2157{
2158#if defined(CONFIG_DEBUG_FS)
2159 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2160#else
2161 return 0;
2162#endif
2163}
e024e110
DA		 2164
2165int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2166 uint32_t tiling_flags, uint32_t pitch,
2167 uint32_t offset, uint32_t obj_size)
2168{
2169 int surf_index = reg * 16;
2170 int flags = 0;
2171
2172 /* r100/r200 divide by 16 */
2173 if (rdev->family < CHIP_R300)
2174 flags = pitch / 16;
2175 else
2176 flags = pitch / 8;
2177
2178 if (rdev->family <= CHIP_RS200) {
2179 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2180 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2181 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2182 if (tiling_flags & RADEON_TILING_MACRO)
2183 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2184 } else if (rdev->family <= CHIP_RV280) {
2185 if (tiling_flags & (RADEON_TILING_MACRO))
2186 flags |= R200_SURF_TILE_COLOR_MACRO;
2187 if (tiling_flags & RADEON_TILING_MICRO)
2188 flags |= R200_SURF_TILE_COLOR_MICRO;
2189 } else {
2190 if (tiling_flags & RADEON_TILING_MACRO)
2191 flags |= R300_SURF_TILE_MACRO;
2192 if (tiling_flags & RADEON_TILING_MICRO)
2193 flags |= R300_SURF_TILE_MICRO;
2194 }
2195
c88f9f0c
MD		 2196 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2197 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2198 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2199 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2200
e024e110
DA		 2201 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2202 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2203 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2204 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2205 return 0;
2206}
2207
2208void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2209{
2210 int surf_index = reg * 16;
2211 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2212}
c93bb85b
JG		 2213
2214void r100_bandwidth_update(struct radeon_device *rdev)
2215{
2216 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2217 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2218 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2219 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2220 fixed20_12 memtcas_ff[8] = {
2221 fixed_init(1),
2222 fixed_init(2),
2223 fixed_init(3),
2224 fixed_init(0),
2225 fixed_init_half(1),
2226 fixed_init_half(2),
2227 fixed_init(0),
2228 };
2229 fixed20_12 memtcas_rs480_ff[8] = {
2230 fixed_init(0),
2231 fixed_init(1),
2232 fixed_init(2),
2233 fixed_init(3),
2234 fixed_init(0),
2235 fixed_init_half(1),
2236 fixed_init_half(2),
2237 fixed_init_half(3),
2238 };
2239 fixed20_12 memtcas2_ff[8] = {
2240 fixed_init(0),
2241 fixed_init(1),
2242 fixed_init(2),
2243 fixed_init(3),
2244 fixed_init(4),
2245 fixed_init(5),
2246 fixed_init(6),
2247 fixed_init(7),
2248 };
2249 fixed20_12 memtrbs[8] = {
2250 fixed_init(1),
2251 fixed_init_half(1),
2252 fixed_init(2),
2253 fixed_init_half(2),
2254 fixed_init(3),
2255 fixed_init_half(3),
2256 fixed_init(4),
2257 fixed_init_half(4)
2258 };
2259 fixed20_12 memtrbs_r4xx[8] = {
2260 fixed_init(4),
2261 fixed_init(5),
2262 fixed_init(6),
2263 fixed_init(7),
2264 fixed_init(8),
2265 fixed_init(9),
2266 fixed_init(10),
2267 fixed_init(11)
2268 };
2269 fixed20_12 min_mem_eff;
2270 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2271 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2272 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2273 disp_drain_rate2, read_return_rate;
2274 fixed20_12 time_disp1_drop_priority;
2275 int c;
2276 int cur_size = 16; /* in octawords */
2277 int critical_point = 0, critical_point2;
2278/* uint32_t read_return_rate, time_disp1_drop_priority; */
2279 int stop_req, max_stop_req;
2280 struct drm_display_mode *mode1 = NULL;
2281 struct drm_display_mode *mode2 = NULL;
2282 uint32_t pixel_bytes1 = 0;
2283 uint32_t pixel_bytes2 = 0;
2284
2285 if (rdev->mode_info.crtcs[0]->base.enabled) {
2286 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2287 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2288 }
2289 if (rdev->mode_info.crtcs[1]->base.enabled) {
2290 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2291 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2292 }
2293
2294 min_mem_eff.full = rfixed_const_8(0);
2295 /* get modes */
2296 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2297 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2298 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2299 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2300 /* check crtc enables */
2301 if (mode2)
2302 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2303 if (mode1)
2304 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2305 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2306 }
2307
2308 /*
2309 * determine is there is enough bw for current mode
2310 */
2311 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2312 temp_ff.full = rfixed_const(100);
2313 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2314 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2315 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2316
2317 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2318 temp_ff.full = rfixed_const(temp);
2319 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2320
2321 pix_clk.full = 0;
2322 pix_clk2.full = 0;
2323 peak_disp_bw.full = 0;
2324 if (mode1) {
2325 temp_ff.full = rfixed_const(1000);
2326 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2327 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2328 temp_ff.full = rfixed_const(pixel_bytes1);
2329 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2330 }
2331 if (mode2) {
2332 temp_ff.full = rfixed_const(1000);
2333 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2334 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2335 temp_ff.full = rfixed_const(pixel_bytes2);
2336 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2337 }
2338
2339 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2340 if (peak_disp_bw.full >= mem_bw.full) {
2341 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2342 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2343 }
2344
2345 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2346 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2347 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2348 mem_trcd = ((temp >> 2) & 0x3) + 1;
2349 mem_trp = ((temp & 0x3)) + 1;
2350 mem_tras = ((temp & 0x70) >> 4) + 1;
2351 } else if (rdev->family == CHIP_R300 ||
2352 rdev->family == CHIP_R350) { /* r300, r350 */
2353 mem_trcd = (temp & 0x7) + 1;
2354 mem_trp = ((temp >> 8) & 0x7) + 1;
2355 mem_tras = ((temp >> 11) & 0xf) + 4;
2356 } else if (rdev->family == CHIP_RV350 ||
2357 rdev->family <= CHIP_RV380) {
2358 /* rv3x0 */
2359 mem_trcd = (temp & 0x7) + 3;
2360 mem_trp = ((temp >> 8) & 0x7) + 3;
2361 mem_tras = ((temp >> 11) & 0xf) + 6;
2362 } else if (rdev->family == CHIP_R420 ||
2363 rdev->family == CHIP_R423 ||
2364 rdev->family == CHIP_RV410) {
2365 /* r4xx */
2366 mem_trcd = (temp & 0xf) + 3;
2367 if (mem_trcd > 15)
2368 mem_trcd = 15;
2369 mem_trp = ((temp >> 8) & 0xf) + 3;
2370 if (mem_trp > 15)
2371 mem_trp = 15;
2372 mem_tras = ((temp >> 12) & 0x1f) + 6;
2373 if (mem_tras > 31)
2374 mem_tras = 31;
2375 } else { /* RV200, R200 */
2376 mem_trcd = (temp & 0x7) + 1;
2377 mem_trp = ((temp >> 8) & 0x7) + 1;
2378 mem_tras = ((temp >> 12) & 0xf) + 4;
2379 }
2380 /* convert to FF */
2381 trcd_ff.full = rfixed_const(mem_trcd);
2382 trp_ff.full = rfixed_const(mem_trp);
2383 tras_ff.full = rfixed_const(mem_tras);
2384
2385 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2386 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2387 data = (temp & (7 << 20)) >> 20;
2388 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2389 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2390 tcas_ff = memtcas_rs480_ff[data];
2391 else
2392 tcas_ff = memtcas_ff[data];
2393 } else
2394 tcas_ff = memtcas2_ff[data];
2395
2396 if (rdev->family == CHIP_RS400 ||
2397 rdev->family == CHIP_RS480) {
2398 /* extra cas latency stored in bits 23-25 0-4 clocks */
2399 data = (temp >> 23) & 0x7;
2400 if (data < 5)
2401 tcas_ff.full += rfixed_const(data);
2402 }
2403
2404 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2405 /* on the R300, Tcas is included in Trbs.
2406 */
2407 temp = RREG32(RADEON_MEM_CNTL);
2408 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2409 if (data == 1) {
2410 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2411 temp = RREG32(R300_MC_IND_INDEX);
2412 temp &= ~R300_MC_IND_ADDR_MASK;
2413 temp |= R300_MC_READ_CNTL_CD_mcind;
2414 WREG32(R300_MC_IND_INDEX, temp);
2415 temp = RREG32(R300_MC_IND_DATA);
2416 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2417 } else {
2418 temp = RREG32(R300_MC_READ_CNTL_AB);
2419 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2420 }
2421 } else {
2422 temp = RREG32(R300_MC_READ_CNTL_AB);
2423 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2424 }
2425 if (rdev->family == CHIP_RV410 ||
2426 rdev->family == CHIP_R420 ||
2427 rdev->family == CHIP_R423)
2428 trbs_ff = memtrbs_r4xx[data];
2429 else
2430 trbs_ff = memtrbs[data];
2431 tcas_ff.full += trbs_ff.full;
2432 }
2433
2434 sclk_eff_ff.full = sclk_ff.full;
2435
2436 if (rdev->flags & RADEON_IS_AGP) {
2437 fixed20_12 agpmode_ff;
2438 agpmode_ff.full = rfixed_const(radeon_agpmode);
2439 temp_ff.full = rfixed_const_666(16);
2440 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2441 }
2442 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2443
2444 if (ASIC_IS_R300(rdev)) {
2445 sclk_delay_ff.full = rfixed_const(250);
2446 } else {
2447 if ((rdev->family == CHIP_RV100) ||
2448 rdev->flags & RADEON_IS_IGP) {
2449 if (rdev->mc.vram_is_ddr)
2450 sclk_delay_ff.full = rfixed_const(41);
2451 else
2452 sclk_delay_ff.full = rfixed_const(33);
2453 } else {
2454 if (rdev->mc.vram_width == 128)
2455 sclk_delay_ff.full = rfixed_const(57);
2456 else
2457 sclk_delay_ff.full = rfixed_const(41);
2458 }
2459 }
2460
2461 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2462
2463 if (rdev->mc.vram_is_ddr) {
2464 if (rdev->mc.vram_width == 32) {
2465 k1.full = rfixed_const(40);
2466 c = 3;
2467 } else {
2468 k1.full = rfixed_const(20);
2469 c = 1;
2470 }
2471 } else {
2472 k1.full = rfixed_const(40);
2473 c = 3;
2474 }
2475
2476 temp_ff.full = rfixed_const(2);
2477 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2478 temp_ff.full = rfixed_const(c);
2479 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2480 temp_ff.full = rfixed_const(4);
2481 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2482 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2483 mc_latency_mclk.full += k1.full;
2484
2485 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2486 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2487
2488 /*
2489 HW cursor time assuming worst case of full size colour cursor.
2490 */
2491 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2492 temp_ff.full += trcd_ff.full;
2493 if (temp_ff.full < tras_ff.full)
2494 temp_ff.full = tras_ff.full;
2495 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2496
2497 temp_ff.full = rfixed_const(cur_size);
2498 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2499 /*
2500 Find the total latency for the display data.
2501 */
2502 disp_latency_overhead.full = rfixed_const(80);
2503 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2504 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2505 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2506
2507 if (mc_latency_mclk.full > mc_latency_sclk.full)
2508 disp_latency.full = mc_latency_mclk.full;
2509 else
2510 disp_latency.full = mc_latency_sclk.full;
2511
2512 /* setup Max GRPH_STOP_REQ default value */
2513 if (ASIC_IS_RV100(rdev))
2514 max_stop_req = 0x5c;
2515 else
2516 max_stop_req = 0x7c;
2517
2518 if (mode1) {
2519 /* CRTC1
2520 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2521 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2522 */
2523 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2524
2525 if (stop_req > max_stop_req)
2526 stop_req = max_stop_req;
2527
2528 /*
2529 Find the drain rate of the display buffer.
2530 */
2531 temp_ff.full = rfixed_const((16/pixel_bytes1));
2532 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2533
2534 /*
2535 Find the critical point of the display buffer.
2536 */
2537 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2538 crit_point_ff.full += rfixed_const_half(0);
2539
2540 critical_point = rfixed_trunc(crit_point_ff);
2541
2542 if (rdev->disp_priority == 2) {
2543 critical_point = 0;
2544 }
2545
2546 /*
2547 The critical point should never be above max_stop_req-4. Setting
2548 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2549 */
2550 if (max_stop_req - critical_point < 4)
2551 critical_point = 0;
2552
2553 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2554 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2555 critical_point = 0x10;
2556 }
2557
2558 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2559 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2560 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2561 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2562 if ((rdev->family == CHIP_R350) &&
2563 (stop_req > 0x15)) {
2564 stop_req -= 0x10;
2565 }
2566 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2567 temp |= RADEON_GRPH_BUFFER_SIZE;
2568 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2569 RADEON_GRPH_CRITICAL_AT_SOF |
2570 RADEON_GRPH_STOP_CNTL);
2571 /*
2572 Write the result into the register.
2573 */
2574 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2575 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2576
2577#if 0
2578 if ((rdev->family == CHIP_RS400) ||
2579 (rdev->family == CHIP_RS480)) {
2580 /* attempt to program RS400 disp regs correctly ??? */
2581 temp = RREG32(RS400_DISP1_REG_CNTL);
2582 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2583 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2584 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2585 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2586 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2587 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2588 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2589 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2590 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2591 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2592 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2593 }
2594#endif
2595
2596 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2597 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2598 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2599 }
2600
2601 if (mode2) {
2602 u32 grph2_cntl;
2603 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2604
2605 if (stop_req > max_stop_req)
2606 stop_req = max_stop_req;
2607
2608 /*
2609 Find the drain rate of the display buffer.
2610 */
2611 temp_ff.full = rfixed_const((16/pixel_bytes2));
2612 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2613
2614 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2615 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2616 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2617 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2618 if ((rdev->family == CHIP_R350) &&
2619 (stop_req > 0x15)) {
2620 stop_req -= 0x10;
2621 }
2622 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2623 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2624 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2625 RADEON_GRPH_CRITICAL_AT_SOF |
2626 RADEON_GRPH_STOP_CNTL);
2627
2628 if ((rdev->family == CHIP_RS100) ||
2629 (rdev->family == CHIP_RS200))
2630 critical_point2 = 0;
2631 else {
2632 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2633 temp_ff.full = rfixed_const(temp);
2634 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2635 if (sclk_ff.full < temp_ff.full)
2636 temp_ff.full = sclk_ff.full;
2637
2638 read_return_rate.full = temp_ff.full;
2639
2640 if (mode1) {
2641 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2642 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2643 } else {
2644 time_disp1_drop_priority.full = 0;
2645 }
2646 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2647 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2648 crit_point_ff.full += rfixed_const_half(0);
2649
2650 critical_point2 = rfixed_trunc(crit_point_ff);
2651
2652 if (rdev->disp_priority == 2) {
2653 critical_point2 = 0;
2654 }
2655
2656 if (max_stop_req - critical_point2 < 4)
2657 critical_point2 = 0;
2658
2659 }
2660
2661 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2662 /* some R300 cards have problem with this set to 0 */
2663 critical_point2 = 0x10;
2664 }
2665
2666 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2667 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2668
2669 if ((rdev->family == CHIP_RS400) ||
2670 (rdev->family == CHIP_RS480)) {
2671#if 0
2672 /* attempt to program RS400 disp2 regs correctly ??? */
2673 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2674 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2675 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2676 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2677 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2678 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2679 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2680 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2681 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2682 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2683 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2684 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2685#endif
2686 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2687 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2688 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2689 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2690 }
2691
2692 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2693 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2694 }
2695}
551ebd83
DA		 2696
2697static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2698{
2699 DRM_ERROR("pitch %d\n", t->pitch);
2700 DRM_ERROR("width %d\n", t->width);
2701 DRM_ERROR("height %d\n", t->height);
2702 DRM_ERROR("num levels %d\n", t->num_levels);
2703 DRM_ERROR("depth %d\n", t->txdepth);
2704 DRM_ERROR("bpp %d\n", t->cpp);
2705 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2706 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2707 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2708}
2709
2710static int r100_cs_track_cube(struct radeon_device *rdev,
2711 struct r100_cs_track *track, unsigned idx)
2712{
2713 unsigned face, w, h;
2714 struct radeon_object *cube_robj;
2715 unsigned long size;
2716
2717 for (face = 0; face < 5; face++) {
2718 cube_robj = track->textures[idx].cube_info[face].robj;
2719 w = track->textures[idx].cube_info[face].width;
2720 h = track->textures[idx].cube_info[face].height;
2721
2722 size = w * h;
2723 size *= track->textures[idx].cpp;
2724
2725 size += track->textures[idx].cube_info[face].offset;
2726
2727 if (size > radeon_object_size(cube_robj)) {
2728 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2729 size, radeon_object_size(cube_robj));
2730 r100_cs_track_texture_print(&track->textures[idx]);
2731 return -1;
2732 }
2733 }
2734 return 0;
2735}
2736
2737static int r100_cs_track_texture_check(struct radeon_device *rdev,
2738 struct r100_cs_track *track)
2739{
2740 struct radeon_object *robj;
2741 unsigned long size;
2742 unsigned u, i, w, h;
2743 int ret;
2744
2745 for (u = 0; u < track->num_texture; u++) {
2746 if (!track->textures[u].enabled)
2747 continue;
2748 robj = track->textures[u].robj;
2749 if (robj == NULL) {
2750 DRM_ERROR("No texture bound to unit %u\n", u);
2751 return -EINVAL;
2752 }
2753 size = 0;
2754 for (i = 0; i <= track->textures[u].num_levels; i++) {
2755 if (track->textures[u].use_pitch) {
2756 if (rdev->family < CHIP_R300)
2757 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2758 else
2759 w = track->textures[u].pitch / (1 << i);
2760 } else {
2761 w = track->textures[u].width / (1 << i);
2762 if (rdev->family >= CHIP_RV515)
2763 w |= track->textures[u].width_11;
2764 if (track->textures[u].roundup_w)
2765 w = roundup_pow_of_two(w);
2766 }
2767 h = track->textures[u].height / (1 << i);
2768 if (rdev->family >= CHIP_RV515)
2769 h |= track->textures[u].height_11;
2770 if (track->textures[u].roundup_h)
2771 h = roundup_pow_of_two(h);
2772 size += w * h;
2773 }
2774 size *= track->textures[u].cpp;
2775 switch (track->textures[u].tex_coord_type) {
2776 case 0:
2777 break;
2778 case 1:
2779 size *= (1 << track->textures[u].txdepth);
2780 break;
2781 case 2:
2782 if (track->separate_cube) {
2783 ret = r100_cs_track_cube(rdev, track, u);
2784 if (ret)
2785 return ret;
2786 } else
2787 size *= 6;
2788 break;
2789 default:
2790 DRM_ERROR("Invalid texture coordinate type %u for unit "
2791 "%u\n", track->textures[u].tex_coord_type, u);
2792 return -EINVAL;
2793 }
2794 if (size > radeon_object_size(robj)) {
2795 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2796 "%lu\n", u, size, radeon_object_size(robj));
2797 r100_cs_track_texture_print(&track->textures[u]);
2798 return -EINVAL;
2799 }
2800 }
2801 return 0;
2802}
2803
2804int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2805{
2806 unsigned i;
2807 unsigned long size;
2808 unsigned prim_walk;
2809 unsigned nverts;
2810
2811 for (i = 0; i < track->num_cb; i++) {
2812 if (track->cb[i].robj == NULL) {
2813 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2814 return -EINVAL;
2815 }
2816 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2817 size += track->cb[i].offset;
2818 if (size > radeon_object_size(track->cb[i].robj)) {
2819 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2820 "(need %lu have %lu) !\n", i, size,
2821 radeon_object_size(track->cb[i].robj));
2822 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2823 i, track->cb[i].pitch, track->cb[i].cpp,
2824 track->cb[i].offset, track->maxy);
2825 return -EINVAL;
2826 }
2827 }
2828 if (track->z_enabled) {
2829 if (track->zb.robj == NULL) {
2830 DRM_ERROR("[drm] No buffer for z buffer !\n");
2831 return -EINVAL;
2832 }
2833 size = track->zb.pitch * track->zb.cpp * track->maxy;
2834 size += track->zb.offset;
2835 if (size > radeon_object_size(track->zb.robj)) {
2836 DRM_ERROR("[drm] Buffer too small for z buffer "
2837 "(need %lu have %lu) !\n", size,
2838 radeon_object_size(track->zb.robj));
2839 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2840 track->zb.pitch, track->zb.cpp,
2841 track->zb.offset, track->maxy);
2842 return -EINVAL;
2843 }
2844 }
2845 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2846 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2847 switch (prim_walk) {
2848 case 1:
2849 for (i = 0; i < track->num_arrays; i++) {
2850 size = track->arrays[i].esize * track->max_indx * 4;
2851 if (track->arrays[i].robj == NULL) {
2852 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2853 "bound\n", prim_walk, i);
2854 return -EINVAL;
2855 }
2856 if (size > radeon_object_size(track->arrays[i].robj)) {
2857 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2858 "have %lu dwords\n", prim_walk, i,
2859 size >> 2,
2860 radeon_object_size(track->arrays[i].robj) >> 2);
2861 DRM_ERROR("Max indices %u\n", track->max_indx);
2862 return -EINVAL;
2863 }
2864 }
2865 break;
2866 case 2:
2867 for (i = 0; i < track->num_arrays; i++) {
2868 size = track->arrays[i].esize * (nverts - 1) * 4;
2869 if (track->arrays[i].robj == NULL) {
2870 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2871 "bound\n", prim_walk, i);
2872 return -EINVAL;
2873 }
2874 if (size > radeon_object_size(track->arrays[i].robj)) {
2875 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2876 "have %lu dwords\n", prim_walk, i, size >> 2,
2877 radeon_object_size(track->arrays[i].robj) >> 2);
2878 return -EINVAL;
2879 }
2880 }
2881 break;
2882 case 3:
2883 size = track->vtx_size * nverts;
2884 if (size != track->immd_dwords) {
2885 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2886 track->immd_dwords, size);
2887 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2888 nverts, track->vtx_size);
2889 return -EINVAL;
2890 }
2891 break;
2892 default:
2893 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2894 prim_walk);
2895 return -EINVAL;
2896 }
2897 return r100_cs_track_texture_check(rdev, track);
2898}
2899
2900void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2901{
2902 unsigned i, face;
2903
2904 if (rdev->family < CHIP_R300) {
2905 track->num_cb = 1;
2906 if (rdev->family <= CHIP_RS200)
2907 track->num_texture = 3;
2908 else
2909 track->num_texture = 6;
2910 track->maxy = 2048;
2911 track->separate_cube = 1;
2912 } else {
2913 track->num_cb = 4;
2914 track->num_texture = 16;
2915 track->maxy = 4096;
2916 track->separate_cube = 0;
2917 }
2918
2919 for (i = 0; i < track->num_cb; i++) {
2920 track->cb[i].robj = NULL;
2921 track->cb[i].pitch = 8192;
2922 track->cb[i].cpp = 16;
2923 track->cb[i].offset = 0;
2924 }
2925 track->z_enabled = true;
2926 track->zb.robj = NULL;
2927 track->zb.pitch = 8192;
2928 track->zb.cpp = 4;
2929 track->zb.offset = 0;
2930 track->vtx_size = 0x7F;
2931 track->immd_dwords = 0xFFFFFFFFUL;
2932 track->num_arrays = 11;
2933 track->max_indx = 0x00FFFFFFUL;
2934 for (i = 0; i < track->num_arrays; i++) {
2935 track->arrays[i].robj = NULL;
2936 track->arrays[i].esize = 0x7F;
2937 }
2938 for (i = 0; i < track->num_texture; i++) {
2939 track->textures[i].pitch = 16536;
2940 track->textures[i].width = 16536;
2941 track->textures[i].height = 16536;
2942 track->textures[i].width_11 = 1 << 11;
2943 track->textures[i].height_11 = 1 << 11;
2944 track->textures[i].num_levels = 12;
2945 if (rdev->family <= CHIP_RS200) {
2946 track->textures[i].tex_coord_type = 0;
2947 track->textures[i].txdepth = 0;
2948 } else {
2949 track->textures[i].txdepth = 16;
2950 track->textures[i].tex_coord_type = 1;
2951 }
2952 track->textures[i].cpp = 64;
2953 track->textures[i].robj = NULL;
2954 /* CS IB emission code makes sure texture unit are disabled */
2955 track->textures[i].enabled = false;
2956 track->textures[i].roundup_w = true;
2957 track->textures[i].roundup_h = true;
2958 if (track->separate_cube)
2959 for (face = 0; face < 5; face++) {
2960 track->textures[i].cube_info[face].robj = NULL;
2961 track->textures[i].cube_info[face].width = 16536;
2962 track->textures[i].cube_info[face].height = 16536;
2963 track->textures[i].cube_info[face].offset = 0;
2964 }
2965 }
2966}
3ce0a23d
JG		 2967
2968int r100_ring_test(struct radeon_device *rdev)
2969{
2970 uint32_t scratch;
2971 uint32_t tmp = 0;
2972 unsigned i;
2973 int r;
2974
2975 r = radeon_scratch_get(rdev, &scratch);
2976 if (r) {
2977 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2978 return r;
2979 }
2980 WREG32(scratch, 0xCAFEDEAD);
2981 r = radeon_ring_lock(rdev, 2);
2982 if (r) {
2983 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2984 radeon_scratch_free(rdev, scratch);
2985 return r;
2986 }
2987 radeon_ring_write(rdev, PACKET0(scratch, 0));
2988 radeon_ring_write(rdev, 0xDEADBEEF);
2989 radeon_ring_unlock_commit(rdev);
2990 for (i = 0; i < rdev->usec_timeout; i++) {
2991 tmp = RREG32(scratch);
2992 if (tmp == 0xDEADBEEF) {
2993 break;
2994 }
2995 DRM_UDELAY(1);
2996 }
2997 if (i < rdev->usec_timeout) {
2998 DRM_INFO("ring test succeeded in %d usecs\n", i);
2999 } else {
3000 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3001 scratch, tmp);
3002 r = -EINVAL;
3003 }
3004 radeon_scratch_free(rdev, scratch);
3005 return r;
3006}
3007
3008void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3009{
3010 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3011 radeon_ring_write(rdev, ib->gpu_addr);
3012 radeon_ring_write(rdev, ib->length_dw);
3013}
3014
3015int r100_ib_test(struct radeon_device *rdev)
3016{
3017 struct radeon_ib *ib;
3018 uint32_t scratch;
3019 uint32_t tmp = 0;
3020 unsigned i;
3021 int r;
3022
3023 r = radeon_scratch_get(rdev, &scratch);
3024 if (r) {
3025 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3026 return r;
3027 }
3028 WREG32(scratch, 0xCAFEDEAD);
3029 r = radeon_ib_get(rdev, &ib);
3030 if (r) {
3031 return r;
3032 }
3033 ib->ptr[0] = PACKET0(scratch, 0);
3034 ib->ptr[1] = 0xDEADBEEF;
3035 ib->ptr[2] = PACKET2(0);
3036 ib->ptr[3] = PACKET2(0);
3037 ib->ptr[4] = PACKET2(0);
3038 ib->ptr[5] = PACKET2(0);
3039 ib->ptr[6] = PACKET2(0);
3040 ib->ptr[7] = PACKET2(0);
3041 ib->length_dw = 8;
3042 r = radeon_ib_schedule(rdev, ib);
3043 if (r) {
3044 radeon_scratch_free(rdev, scratch);
3045 radeon_ib_free(rdev, &ib);
3046 return r;
3047 }
3048 r = radeon_fence_wait(ib->fence, false);
3049 if (r) {
3050 return r;
3051 }
3052 for (i = 0; i < rdev->usec_timeout; i++) {
3053 tmp = RREG32(scratch);
3054 if (tmp == 0xDEADBEEF) {
3055 break;
3056 }
3057 DRM_UDELAY(1);
3058 }
3059 if (i < rdev->usec_timeout) {
3060 DRM_INFO("ib test succeeded in %u usecs\n", i);
3061 } else {
3062 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3063 scratch, tmp);
3064 r = -EINVAL;
3065 }
3066 radeon_scratch_free(rdev, scratch);
3067 radeon_ib_free(rdev, &ib);
3068 return r;
3069}
9f022ddf
JG		 3070
3071void r100_ib_fini(struct radeon_device *rdev)
3072{
3073 radeon_ib_pool_fini(rdev);
3074}
3075
3076int r100_ib_init(struct radeon_device *rdev)
3077{
3078 int r;
3079
3080 r = radeon_ib_pool_init(rdev);
3081 if (r) {
3082 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3083 r100_ib_fini(rdev);
3084 return r;
3085 }
3086 r = r100_ib_test(rdev);
3087 if (r) {
3088 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3089 r100_ib_fini(rdev);
3090 return r;
3091 }
3092 return 0;
3093}
3094
3095void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3096{
3097 /* Shutdown CP we shouldn't need to do that but better be safe than
3098 * sorry
3099 */
3100 rdev->cp.ready = false;
3101 WREG32(R_000740_CP_CSQ_CNTL, 0);
3102
3103 /* Save few CRTC registers */
3104 save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
3105 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3106 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3107 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3108 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3109 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3110 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3111 }
3112
3113 /* Disable VGA aperture access */
3114 WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
3115 /* Disable cursor, overlay, crtc */
3116 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3117 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3118 S_000054_CRTC_DISPLAY_DIS(1));
3119 WREG32(R_000050_CRTC_GEN_CNTL,
3120 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3121 S_000050_CRTC_DISP_REQ_EN_B(1));
3122 WREG32(R_000420_OV0_SCALE_CNTL,
3123 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3124 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3125 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3126 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3127 S_000360_CUR2_LOCK(1));
3128 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3129 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3130 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3131 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3132 WREG32(R_000360_CUR2_OFFSET,
3133 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3134 }
3135}
3136
3137void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3138{
3139 /* Update base address for crtc */
3140 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3141 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3142 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3143 rdev->mc.vram_location);
3144 }
3145 /* Restore CRTC registers */
3146 WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
3147 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3148 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3149 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3150 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3151 }
3152}
Clone of davem's net-next-2.6 tree