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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[net-next-2.6.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
63 } else if (a2 > a1) {
64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
5b1714d3
AD		 70 args.usOverscanRight = radeon_crtc->h_border;
71 args.usOverscanLeft = radeon_crtc->h_border;
72 args.usOverscanBottom = radeon_crtc->v_border;
73 args.usOverscanTop = radeon_crtc->v_border;
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
37b4390e 256 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 257 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 258 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
259 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 260 radeon_crtc->enabled = false;
d7311171
AD		 261 /* adjust pm to dpms changes AFTER disabling crtcs */
262 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 263 break;
264 }
771fe6b9
JG		 265}
266
267static void
268atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 269 struct drm_display_mode *mode)
771fe6b9 270{
5a9bcacc 271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 272 struct drm_device *dev = crtc->dev;
273 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 276 u16 misc = 0;
771fe6b9 277
5a9bcacc 278 memset(&args, 0, sizeof(args));
5b1714d3 279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 280 args.usH_Blanking_Time =
5b1714d3
AD		 281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 283 args.usV_Blanking_Time =
5b1714d3 284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 285 args.usH_SyncOffset =
5b1714d3 286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 287 args.usH_SyncWidth =
288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
289 args.usV_SyncOffset =
5b1714d3 290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 291 args.usV_SyncWidth =
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 293 args.ucH_Border = radeon_crtc->h_border;
294 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 295
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
306
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 309
5a9bcacc 310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 311}
312
5a9bcacc
AD		 313static void atombios_crtc_set_timing(struct drm_crtc *crtc,
314 struct drm_display_mode *mode)
771fe6b9 315{
5a9bcacc 316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 317 struct drm_device *dev = crtc->dev;
318 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 321 u16 misc = 0;
771fe6b9 322
5a9bcacc
AD		 323 memset(&args, 0, sizeof(args));
324 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
327 args.usH_SyncWidth =
328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
332 args.usV_SyncWidth =
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
334
335 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
336 misc |= ATOM_VSYNC_POLARITY;
337 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
338 misc |= ATOM_HSYNC_POLARITY;
339 if (mode->flags & DRM_MODE_FLAG_CSYNC)
340 misc |= ATOM_COMPOSITESYNC;
341 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
342 misc |= ATOM_INTERLACE;
343 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
344 misc |= ATOM_DOUBLE_CLOCK_MODE;
345
346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
347 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 348
5a9bcacc 349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 350}
351
b792210e
AD		 352static void atombios_disable_ss(struct drm_crtc *crtc)
353{
354 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
355 struct drm_device *dev = crtc->dev;
356 struct radeon_device *rdev = dev->dev_private;
357 u32 ss_cntl;
358
359 if (ASIC_IS_DCE4(rdev)) {
360 switch (radeon_crtc->pll_id) {
361 case ATOM_PPLL1:
362 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
363 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
364 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
365 break;
366 case ATOM_PPLL2:
367 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
368 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
369 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
370 break;
371 case ATOM_DCPLL:
372 case ATOM_PPLL_INVALID:
373 return;
374 }
375 } else if (ASIC_IS_AVIVO(rdev)) {
376 switch (radeon_crtc->pll_id) {
377 case ATOM_PPLL1:
378 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
379 ss_cntl &= ~1;
380 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
381 break;
382 case ATOM_PPLL2:
383 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
384 ss_cntl &= ~1;
385 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
386 break;
387 case ATOM_DCPLL:
388 case ATOM_PPLL_INVALID:
389 return;
390 }
391 }
392}
393
394
26b9fc3a
AD		 395union atom_enable_ss {
396 ENABLE_LVDS_SS_PARAMETERS legacy;
397 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
398};
399
b792210e 400static void atombios_enable_ss(struct drm_crtc *crtc)
ebbe1cb9
AD		 401{
402 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
403 struct drm_device *dev = crtc->dev;
404 struct radeon_device *rdev = dev->dev_private;
405 struct drm_encoder *encoder = NULL;
406 struct radeon_encoder *radeon_encoder = NULL;
407 struct radeon_encoder_atom_dig *dig = NULL;
408 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 409 union atom_enable_ss args;
ebbe1cb9
AD		 410 uint16_t percentage = 0;
411 uint8_t type = 0, step = 0, delay = 0, range = 0;
412
bcc1c2a1
AD		 413 /* XXX add ss support for DCE4 */
414 if (ASIC_IS_DCE4(rdev))
415 return;
416
ebbe1cb9
AD		 417 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
418 if (encoder->crtc == crtc) {
419 radeon_encoder = to_radeon_encoder(encoder);
ebbe1cb9 420 /* only enable spread spectrum on LVDS */
d11aa88b
AD		 421 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
422 dig = radeon_encoder->enc_priv;
423 if (dig && dig->ss) {
424 percentage = dig->ss->percentage;
425 type = dig->ss->type;
426 step = dig->ss->step;
427 delay = dig->ss->delay;
428 range = dig->ss->range;
b792210e 429 } else
d11aa88b 430 return;
b792210e 431 } else
ebbe1cb9
AD		 432 return;
433 break;
434 }
435 }
436
437 if (!radeon_encoder)
438 return;
439
26b9fc3a 440 memset(&args, 0, sizeof(args));
ebbe1cb9 441 if (ASIC_IS_AVIVO(rdev)) {
26b9fc3a
AD		 442 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
443 args.v1.ucSpreadSpectrumType = type;
444 args.v1.ucSpreadSpectrumStep = step;
445 args.v1.ucSpreadSpectrumDelay = delay;
446 args.v1.ucSpreadSpectrumRange = range;
447 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
b792210e 448 args.v1.ucEnable = ATOM_ENABLE;
ebbe1cb9 449 } else {
26b9fc3a
AD		 450 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
451 args.legacy.ucSpreadSpectrumType = type;
452 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
453 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
b792210e 454 args.legacy.ucEnable = ATOM_ENABLE;
ebbe1cb9 455 }
26b9fc3a 456 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 457}
458
4eaeca33
AD		 459union adjust_pixel_clock {
460 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 461 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 462};
463
464static u32 atombios_adjust_pll(struct drm_crtc *crtc,
465 struct drm_display_mode *mode,
466 struct radeon_pll *pll)
771fe6b9 467{
771fe6b9
JG		 468 struct drm_device *dev = crtc->dev;
469 struct radeon_device *rdev = dev->dev_private;
470 struct drm_encoder *encoder = NULL;
471 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 472 u32 adjusted_clock = mode->clock;
bcc1c2a1 473 int encoder_mode = 0;
fbee67a6
AD		 474 u32 dp_clock = mode->clock;
475 int bpc = 8;
fc10332b 476
4eaeca33
AD		 477 /* reset the pll flags */
478 pll->flags = 0;
771fe6b9 479
7c27f87d
AD		 480 /* select the PLL algo */
481 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 482 if (radeon_new_pll == 0)
483 pll->algo = PLL_ALGO_LEGACY;
484 else
485 pll->algo = PLL_ALGO_NEW;
486 } else {
487 if (radeon_new_pll == 1)
488 pll->algo = PLL_ALGO_NEW;
7c27f87d
AD		 489 else
490 pll->algo = PLL_ALGO_LEGACY;
383be5d1 491 }
7c27f87d 492
771fe6b9 493 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 494 if ((rdev->family == CHIP_RS600) ||
495 (rdev->family == CHIP_RS690) ||
496 (rdev->family == CHIP_RS740))
2ff776cf 497 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 498 RADEON_PLL_PREFER_CLOSEST_LOWER);
eb1300bc 499
771fe6b9 500 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
fc10332b 501 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 502 else
fc10332b 503 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9 504 } else {
fc10332b 505 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9
JG		 506
507 if (mode->clock > 200000) /* range limits??? */
fc10332b 508 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 509 else
fc10332b 510 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 511
512 }
513
514 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
515 if (encoder->crtc == crtc) {
4eaeca33 516 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 517 encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6
AD		 518 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
519 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
520 if (connector) {
521 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
522 struct radeon_connector_atom_dig *dig_connector =
523 radeon_connector->con_priv;
524
525 dp_clock = dig_connector->dp_clock;
526 }
527 }
528
4eaeca33
AD		 529 if (ASIC_IS_AVIVO(rdev)) {
530 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
531 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
532 adjusted_clock = mode->clock * 2;
a1a4b23b
AD		 533 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
534 pll->algo = PLL_ALGO_LEGACY;
535 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
536 }
4eaeca33
AD		 537 } else {
538 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 539 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 540 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 541 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 542 }
3ce0a23d 543 break;
771fe6b9
JG		 544 }
545 }
546
2606c886
AD		 547 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
548 * accordingly based on the encoder/transmitter to work around
549 * special hw requirements.
550 */
551 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 552 union adjust_pixel_clock args;
4eaeca33
AD		 553 u8 frev, crev;
554 int index;
2606c886 555
2606c886 556 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 557 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
558 &crev))
559 return adjusted_clock;
4eaeca33
AD		 560
561 memset(&args, 0, sizeof(args));
562
563 switch (frev) {
564 case 1:
565 switch (crev) {
566 case 1:
567 case 2:
568 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
569 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 570 args.v1.ucEncodeMode = encoder_mode;
fbee67a6
AD		 571 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
572 /* may want to enable SS on DP eventually */
573 /* args.v1.ucConfig |=
574 ADJUST_DISPLAY_CONFIG_SS_ENABLE;*/
575 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
576 args.v1.ucConfig |=
577 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
578 }
4eaeca33
AD		 579
580 atom_execute_table(rdev->mode_info.atom_context,
581 index, (uint32_t *)&args);
582 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
583 break;
bcc1c2a1
AD		 584 case 3:
585 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
586 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
587 args.v3.sInput.ucEncodeMode = encoder_mode;
588 args.v3.sInput.ucDispPllConfig = 0;
589 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
590 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
591
fbee67a6
AD		 592 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
593 /* may want to enable SS on DP/eDP eventually */
594 /*args.v3.sInput.ucDispPllConfig |=
595 DISPPLL_CONFIG_SS_ENABLE;*/
bcc1c2a1
AD		 596 args.v3.sInput.ucDispPllConfig |=
597 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 598 /* 16200 or 27000 */
599 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
600 } else {
601 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
602 /* deep color support */
603 args.v3.sInput.usPixelClock =
604 cpu_to_le16((mode->clock * bpc / 8) / 10);
605 }
bcc1c2a1
AD		 606 if (dig->coherent_mode)
607 args.v3.sInput.ucDispPllConfig |=
608 DISPPLL_CONFIG_COHERENT_MODE;
609 if (mode->clock > 165000)
610 args.v3.sInput.ucDispPllConfig |=
611 DISPPLL_CONFIG_DUAL_LINK;
612 }
613 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
fbee67a6
AD		 614 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
615 /* may want to enable SS on DP/eDP eventually */
616 /*args.v3.sInput.ucDispPllConfig |=
617 DISPPLL_CONFIG_SS_ENABLE;*/
bcc1c2a1 618 args.v3.sInput.ucDispPllConfig |=
9f998ad7 619 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 620 /* 16200 or 27000 */
621 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
622 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
623 /* want to enable SS on LVDS eventually */
624 /*args.v3.sInput.ucDispPllConfig |=
625 DISPPLL_CONFIG_SS_ENABLE;*/
626 } else {
9f998ad7
AD		 627 if (mode->clock > 165000)
628 args.v3.sInput.ucDispPllConfig |=
629 DISPPLL_CONFIG_DUAL_LINK;
630 }
bcc1c2a1
AD		 631 }
632 atom_execute_table(rdev->mode_info.atom_context,
633 index, (uint32_t *)&args);
634 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
635 if (args.v3.sOutput.ucRefDiv) {
636 pll->flags |= RADEON_PLL_USE_REF_DIV;
637 pll->reference_div = args.v3.sOutput.ucRefDiv;
638 }
639 if (args.v3.sOutput.ucPostDiv) {
640 pll->flags |= RADEON_PLL_USE_POST_DIV;
641 pll->post_div = args.v3.sOutput.ucPostDiv;
642 }
643 break;
4eaeca33
AD		 644 default:
645 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
646 return adjusted_clock;
647 }
648 break;
649 default:
650 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
651 return adjusted_clock;
652 }
d56ef9c8 653 }
4eaeca33
AD		 654 return adjusted_clock;
655}
656
657union set_pixel_clock {
658 SET_PIXEL_CLOCK_PS_ALLOCATION base;
659 PIXEL_CLOCK_PARAMETERS v1;
660 PIXEL_CLOCK_PARAMETERS_V2 v2;
661 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 662 PIXEL_CLOCK_PARAMETERS_V5 v5;
4eaeca33
AD		 663};
664
bcc1c2a1
AD		 665static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
666{
667 struct drm_device *dev = crtc->dev;
668 struct radeon_device *rdev = dev->dev_private;
669 u8 frev, crev;
670 int index;
671 union set_pixel_clock args;
672
673 memset(&args, 0, sizeof(args));
674
675 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 676 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
677 &crev))
678 return;
bcc1c2a1
AD		 679
680 switch (frev) {
681 case 1:
682 switch (crev) {
683 case 5:
684 /* if the default dcpll clock is specified,
685 * SetPixelClock provides the dividers
686 */
687 args.v5.ucCRTC = ATOM_CRTC_INVALID;
688 args.v5.usPixelClock = rdev->clock.default_dispclk;
689 args.v5.ucPpll = ATOM_DCPLL;
690 break;
691 default:
692 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
693 return;
694 }
695 break;
696 default:
697 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
698 return;
699 }
700 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
701}
702
37f9003b
AD		 703static void atombios_crtc_program_pll(struct drm_crtc *crtc,
704 int crtc_id,
705 int pll_id,
706 u32 encoder_mode,
707 u32 encoder_id,
708 u32 clock,
709 u32 ref_div,
710 u32 fb_div,
711 u32 frac_fb_div,
712 u32 post_div)
4eaeca33 713{
4eaeca33
AD		 714 struct drm_device *dev = crtc->dev;
715 struct radeon_device *rdev = dev->dev_private;
4eaeca33 716 u8 frev, crev;
37f9003b 717 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 718 union set_pixel_clock args;
4eaeca33
AD		 719
720 memset(&args, 0, sizeof(args));
721
a084e6ee
AD		 722 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
723 &crev))
724 return;
771fe6b9
JG		 725
726 switch (frev) {
727 case 1:
728 switch (crev) {
729 case 1:
37f9003b
AD		 730 if (clock == ATOM_DISABLE)
731 return;
732 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 733 args.v1.usRefDiv = cpu_to_le16(ref_div);
734 args.v1.usFbDiv = cpu_to_le16(fb_div);
735 args.v1.ucFracFbDiv = frac_fb_div;
736 args.v1.ucPostDiv = post_div;
37f9003b
AD		 737 args.v1.ucPpll = pll_id;
738 args.v1.ucCRTC = crtc_id;
4eaeca33 739 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 740 break;
741 case 2:
37f9003b 742 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 743 args.v2.usRefDiv = cpu_to_le16(ref_div);
744 args.v2.usFbDiv = cpu_to_le16(fb_div);
745 args.v2.ucFracFbDiv = frac_fb_div;
746 args.v2.ucPostDiv = post_div;
37f9003b
AD		 747 args.v2.ucPpll = pll_id;
748 args.v2.ucCRTC = crtc_id;
4eaeca33 749 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 750 break;
751 case 3:
37f9003b 752 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 753 args.v3.usRefDiv = cpu_to_le16(ref_div);
754 args.v3.usFbDiv = cpu_to_le16(fb_div);
755 args.v3.ucFracFbDiv = frac_fb_div;
756 args.v3.ucPostDiv = post_div;
37f9003b
AD		 757 args.v3.ucPpll = pll_id;
758 args.v3.ucMiscInfo = (pll_id << 2);
759 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 760 args.v3.ucEncoderMode = encoder_mode;
761 break;
762 case 5:
37f9003b
AD		 763 args.v5.ucCRTC = crtc_id;
764 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 765 args.v5.ucRefDiv = ref_div;
766 args.v5.usFbDiv = cpu_to_le16(fb_div);
767 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
768 args.v5.ucPostDiv = post_div;
769 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
37f9003b 770 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 771 args.v5.ucEncoderMode = encoder_mode;
37f9003b 772 args.v5.ucPpll = pll_id;
771fe6b9
JG		 773 break;
774 default:
775 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
776 return;
777 }
778 break;
779 default:
780 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
781 return;
782 }
783
771fe6b9
JG		 784 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
785}
786
37f9003b
AD		 787static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
788{
789 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
790 struct drm_device *dev = crtc->dev;
791 struct radeon_device *rdev = dev->dev_private;
792 struct drm_encoder *encoder = NULL;
793 struct radeon_encoder *radeon_encoder = NULL;
794 u32 pll_clock = mode->clock;
795 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
796 struct radeon_pll *pll;
797 u32 adjusted_clock;
798 int encoder_mode = 0;
799
800 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
801 if (encoder->crtc == crtc) {
802 radeon_encoder = to_radeon_encoder(encoder);
803 encoder_mode = atombios_get_encoder_mode(encoder);
804 break;
805 }
806 }
807
808 if (!radeon_encoder)
809 return;
810
811 switch (radeon_crtc->pll_id) {
812 case ATOM_PPLL1:
813 pll = &rdev->clock.p1pll;
814 break;
815 case ATOM_PPLL2:
816 pll = &rdev->clock.p2pll;
817 break;
818 case ATOM_DCPLL:
819 case ATOM_PPLL_INVALID:
820 default:
821 pll = &rdev->clock.dcpll;
822 break;
823 }
824
825 /* adjust pixel clock as needed */
826 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
827
828 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
829 &ref_div, &post_div);
830
831 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
832 encoder_mode, radeon_encoder->encoder_id, mode->clock,
833 ref_div, fb_div, frac_fb_div, post_div);
834
835}
836
bcc1c2a1
AD		 837static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
838 struct drm_framebuffer *old_fb)
839{
840 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
841 struct drm_device *dev = crtc->dev;
842 struct radeon_device *rdev = dev->dev_private;
843 struct radeon_framebuffer *radeon_fb;
844 struct drm_gem_object *obj;
845 struct radeon_bo *rbo;
846 uint64_t fb_location;
847 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
848 int r;
849
850 /* no fb bound */
851 if (!crtc->fb) {
d9fdaafb 852 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 853 return 0;
854 }
855
856 radeon_fb = to_radeon_framebuffer(crtc->fb);
857
858 /* Pin framebuffer & get tilling informations */
859 obj = radeon_fb->obj;
860 rbo = obj->driver_private;
861 r = radeon_bo_reserve(rbo, false);
862 if (unlikely(r != 0))
863 return r;
864 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
865 if (unlikely(r != 0)) {
866 radeon_bo_unreserve(rbo);
867 return -EINVAL;
868 }
869 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
870 radeon_bo_unreserve(rbo);
871
872 switch (crtc->fb->bits_per_pixel) {
873 case 8:
874 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
875 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
876 break;
877 case 15:
878 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
879 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
880 break;
881 case 16:
882 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
883 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
884 break;
885 case 24:
886 case 32:
887 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
888 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
889 break;
890 default:
891 DRM_ERROR("Unsupported screen depth %d\n",
892 crtc->fb->bits_per_pixel);
893 return -EINVAL;
894 }
895
97d66328
AD		 896 if (tiling_flags & RADEON_TILING_MACRO)
897 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
898 else if (tiling_flags & RADEON_TILING_MICRO)
899 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
900
bcc1c2a1
AD		 901 switch (radeon_crtc->crtc_id) {
902 case 0:
903 WREG32(AVIVO_D1VGA_CONTROL, 0);
904 break;
905 case 1:
906 WREG32(AVIVO_D2VGA_CONTROL, 0);
907 break;
908 case 2:
909 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
910 break;
911 case 3:
912 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
913 break;
914 case 4:
915 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
916 break;
917 case 5:
918 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
919 break;
920 default:
921 break;
922 }
923
924 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
925 upper_32_bits(fb_location));
926 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
927 upper_32_bits(fb_location));
928 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
929 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
930 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
931 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
932 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
933
934 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
935 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
936 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
937 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
938 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
939 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
940
941 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
942 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
943 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
944
945 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
946 crtc->mode.vdisplay);
947 x &= ~3;
948 y &= ~1;
949 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
950 (x << 16) | y);
951 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
952 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
953
954 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
955 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
956 EVERGREEN_INTERLEAVE_EN);
957 else
958 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
959
960 if (old_fb && old_fb != crtc->fb) {
961 radeon_fb = to_radeon_framebuffer(old_fb);
962 rbo = radeon_fb->obj->driver_private;
963 r = radeon_bo_reserve(rbo, false);
964 if (unlikely(r != 0))
965 return r;
966 radeon_bo_unpin(rbo);
967 radeon_bo_unreserve(rbo);
968 }
969
970 /* Bytes per pixel may have changed */
971 radeon_bandwidth_update(rdev);
972
973 return 0;
974}
975
54f088a9
AD		 976static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
977 struct drm_framebuffer *old_fb)
771fe6b9
JG		 978{
979 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
980 struct drm_device *dev = crtc->dev;
981 struct radeon_device *rdev = dev->dev_private;
982 struct radeon_framebuffer *radeon_fb;
983 struct drm_gem_object *obj;
4c788679 984 struct radeon_bo *rbo;
771fe6b9 985 uint64_t fb_location;
e024e110 986 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 987 int r;
771fe6b9 988
2de3b484
JG		 989 /* no fb bound */
990 if (!crtc->fb) {
d9fdaafb 991 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 992 return 0;
993 }
771fe6b9
JG		 994
995 radeon_fb = to_radeon_framebuffer(crtc->fb);
996
4c788679 997 /* Pin framebuffer & get tilling informations */
771fe6b9 998 obj = radeon_fb->obj;
4c788679
JG		 999 rbo = obj->driver_private;
1000 r = radeon_bo_reserve(rbo, false);
1001 if (unlikely(r != 0))
1002 return r;
1003 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1004 if (unlikely(r != 0)) {
1005 radeon_bo_unreserve(rbo);
771fe6b9
JG		 1006 return -EINVAL;
1007 }
4c788679
JG		 1008 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1009 radeon_bo_unreserve(rbo);
771fe6b9
JG		 1010
1011 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 1012 case 8:
1013 fb_format =
1014 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1015 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1016 break;
771fe6b9
JG		 1017 case 15:
1018 fb_format =
1019 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1020 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1021 break;
1022 case 16:
1023 fb_format =
1024 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1025 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1026 break;
1027 case 24:
1028 case 32:
1029 fb_format =
1030 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1031 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1032 break;
1033 default:
1034 DRM_ERROR("Unsupported screen depth %d\n",
1035 crtc->fb->bits_per_pixel);
1036 return -EINVAL;
1037 }
1038
40c4ac1c
AD		 1039 if (rdev->family >= CHIP_R600) {
1040 if (tiling_flags & RADEON_TILING_MACRO)
1041 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1042 else if (tiling_flags & RADEON_TILING_MICRO)
1043 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1044 } else {
1045 if (tiling_flags & RADEON_TILING_MACRO)
1046 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1047
40c4ac1c
AD		 1048 if (tiling_flags & RADEON_TILING_MICRO)
1049 fb_format |= AVIVO_D1GRPH_TILED;
1050 }
e024e110 1051
771fe6b9
JG		 1052 if (radeon_crtc->crtc_id == 0)
1053 WREG32(AVIVO_D1VGA_CONTROL, 0);
1054 else
1055 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1056
1057 if (rdev->family >= CHIP_RV770) {
1058 if (radeon_crtc->crtc_id) {
1059 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
1060 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
1061 } else {
1062 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
1063 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
1064 }
1065 }
771fe6b9
JG		 1066 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1067 (u32) fb_location);
1068 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1069 radeon_crtc->crtc_offset, (u32) fb_location);
1070 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1071
1072 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1073 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1074 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1075 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1076 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1077 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1078
1079 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1080 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1081 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1082
1083 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1084 crtc->mode.vdisplay);
1085 x &= ~3;
1086 y &= ~1;
1087 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1088 (x << 16) | y);
1089 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1090 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1091
1092 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1093 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1094 AVIVO_D1MODE_INTERLEAVE_EN);
1095 else
1096 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1097
1098 if (old_fb && old_fb != crtc->fb) {
1099 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 1100 rbo = radeon_fb->obj->driver_private;
1101 r = radeon_bo_reserve(rbo, false);
1102 if (unlikely(r != 0))
1103 return r;
1104 radeon_bo_unpin(rbo);
1105 radeon_bo_unreserve(rbo);
771fe6b9 1106 }
f30f37de
MD		 1107
1108 /* Bytes per pixel may have changed */
1109 radeon_bandwidth_update(rdev);
1110
771fe6b9
JG		 1111 return 0;
1112}
1113
54f088a9
AD		 1114int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1115 struct drm_framebuffer *old_fb)
1116{
1117 struct drm_device *dev = crtc->dev;
1118 struct radeon_device *rdev = dev->dev_private;
1119
bcc1c2a1
AD		 1120 if (ASIC_IS_DCE4(rdev))
1121 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1122 else if (ASIC_IS_AVIVO(rdev))
54f088a9
AD		 1123 return avivo_crtc_set_base(crtc, x, y, old_fb);
1124 else
1125 return radeon_crtc_set_base(crtc, x, y, old_fb);
1126}
1127
615e0cb6
AD		 1128/* properly set additional regs when using atombios */
1129static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1130{
1131 struct drm_device *dev = crtc->dev;
1132 struct radeon_device *rdev = dev->dev_private;
1133 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1134 u32 disp_merge_cntl;
1135
1136 switch (radeon_crtc->crtc_id) {
1137 case 0:
1138 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1139 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1140 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1141 break;
1142 case 1:
1143 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1144 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1145 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1146 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1147 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1148 break;
1149 }
1150}
1151
bcc1c2a1
AD		 1152static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1153{
1154 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1155 struct drm_device *dev = crtc->dev;
1156 struct radeon_device *rdev = dev->dev_private;
1157 struct drm_encoder *test_encoder;
1158 struct drm_crtc *test_crtc;
1159 uint32_t pll_in_use = 0;
1160
1161 if (ASIC_IS_DCE4(rdev)) {
1162 /* if crtc is driving DP and we have an ext clock, use that */
1163 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1164 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1165 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1166 if (rdev->clock.dp_extclk)
1167 return ATOM_PPLL_INVALID;
1168 }
1169 }
1170 }
1171
1172 /* otherwise, pick one of the plls */
1173 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1174 struct radeon_crtc *radeon_test_crtc;
1175
1176 if (crtc == test_crtc)
1177 continue;
1178
1179 radeon_test_crtc = to_radeon_crtc(test_crtc);
1180 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1181 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1182 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1183 }
1184 if (!(pll_in_use & 1))
1185 return ATOM_PPLL1;
1186 return ATOM_PPLL2;
1187 } else
1188 return radeon_crtc->crtc_id;
1189
1190}
1191
771fe6b9
JG		 1192int atombios_crtc_mode_set(struct drm_crtc *crtc,
1193 struct drm_display_mode *mode,
1194 struct drm_display_mode *adjusted_mode,
1195 int x, int y, struct drm_framebuffer *old_fb)
1196{
1197 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1198 struct drm_device *dev = crtc->dev;
1199 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1200
1201 /* TODO color tiling */
771fe6b9 1202
b792210e 1203 atombios_disable_ss(crtc);
bcc1c2a1
AD		 1204 /* always set DCPLL */
1205 if (ASIC_IS_DCE4(rdev))
1206 atombios_crtc_set_dcpll(crtc);
771fe6b9 1207 atombios_crtc_set_pll(crtc, adjusted_mode);
b792210e 1208 atombios_enable_ss(crtc);
771fe6b9 1209
5b1714d3 1210 if (ASIC_IS_AVIVO(rdev))
bcc1c2a1 1211 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
771fe6b9 1212 else {
bcc1c2a1 1213 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1214 if (radeon_crtc->crtc_id == 0)
1215 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1216 radeon_legacy_atom_fixup(crtc);
771fe6b9 1217 }
bcc1c2a1 1218 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1219 atombios_overscan_setup(crtc, mode, adjusted_mode);
1220 atombios_scaler_setup(crtc);
771fe6b9
JG		 1221 return 0;
1222}
1223
1224static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1225 struct drm_display_mode *mode,
1226 struct drm_display_mode *adjusted_mode)
1227{
03214bd5
AD		 1228 struct drm_device *dev = crtc->dev;
1229 struct radeon_device *rdev = dev->dev_private;
1230
1231 /* adjust pm to upcoming mode change */
1232 radeon_pm_compute_clocks(rdev);
1233
c93bb85b
JG		 1234 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1235 return false;
771fe6b9
JG		 1236 return true;
1237}
1238
1239static void atombios_crtc_prepare(struct drm_crtc *crtc)
1240{
267364ac
AD		 1241 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1242
1243 /* pick pll */
1244 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1245
37b4390e 1246 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1247 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1248}
1249
1250static void atombios_crtc_commit(struct drm_crtc *crtc)
1251{
1252 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1253 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1254}
1255
37f9003b
AD		 1256static void atombios_crtc_disable(struct drm_crtc *crtc)
1257{
1258 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1259 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1260
1261 switch (radeon_crtc->pll_id) {
1262 case ATOM_PPLL1:
1263 case ATOM_PPLL2:
1264 /* disable the ppll */
1265 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1266 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1267 break;
1268 default:
1269 break;
1270 }
1271 radeon_crtc->pll_id = -1;
1272}
1273
771fe6b9
JG		 1274static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1275 .dpms = atombios_crtc_dpms,
1276 .mode_fixup = atombios_crtc_mode_fixup,
1277 .mode_set = atombios_crtc_mode_set,
1278 .mode_set_base = atombios_crtc_set_base,
1279 .prepare = atombios_crtc_prepare,
1280 .commit = atombios_crtc_commit,
068143d3 1281 .load_lut = radeon_crtc_load_lut,
37f9003b 1282 .disable = atombios_crtc_disable,
771fe6b9
JG		 1283};
1284
1285void radeon_atombios_init_crtc(struct drm_device *dev,
1286 struct radeon_crtc *radeon_crtc)
1287{
bcc1c2a1
AD		 1288 struct radeon_device *rdev = dev->dev_private;
1289
1290 if (ASIC_IS_DCE4(rdev)) {
1291 switch (radeon_crtc->crtc_id) {
1292 case 0:
1293 default:
12d7798f 1294 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1295 break;
1296 case 1:
12d7798f 1297 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1298 break;
1299 case 2:
12d7798f 1300 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1301 break;
1302 case 3:
12d7798f 1303 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1304 break;
1305 case 4:
12d7798f 1306 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1307 break;
1308 case 5:
12d7798f 1309 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1310 break;
1311 }
1312 } else {
1313 if (radeon_crtc->crtc_id == 1)
1314 radeon_crtc->crtc_offset =
1315 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1316 else
1317 radeon_crtc->crtc_offset = 0;
1318 }
1319 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1320 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1321}
Clone of davem's net-next-2.6 tree