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Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6
[net-next-2.6.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
63 } else if (a2 > a1) {
64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
5b1714d3
AD		 70 args.usOverscanRight = radeon_crtc->h_border;
71 args.usOverscanLeft = radeon_crtc->h_border;
72 args.usOverscanBottom = radeon_crtc->v_border;
73 args.usOverscanTop = radeon_crtc->v_border;
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
37b4390e 256 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 257 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 258 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
259 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 260 radeon_crtc->enabled = false;
d7311171
AD		 261 /* adjust pm to dpms changes AFTER disabling crtcs */
262 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 263 break;
264 }
771fe6b9
JG		 265}
266
267static void
268atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 269 struct drm_display_mode *mode)
771fe6b9 270{
5a9bcacc 271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 272 struct drm_device *dev = crtc->dev;
273 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 276 u16 misc = 0;
771fe6b9 277
5a9bcacc 278 memset(&args, 0, sizeof(args));
5b1714d3 279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 280 args.usH_Blanking_Time =
5b1714d3
AD		 281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 283 args.usV_Blanking_Time =
5b1714d3 284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 285 args.usH_SyncOffset =
5b1714d3 286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 287 args.usH_SyncWidth =
288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
289 args.usV_SyncOffset =
5b1714d3 290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 291 args.usV_SyncWidth =
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 293 args.ucH_Border = radeon_crtc->h_border;
294 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 295
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
306
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 309
5a9bcacc 310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 311}
312
5a9bcacc
AD		 313static void atombios_crtc_set_timing(struct drm_crtc *crtc,
314 struct drm_display_mode *mode)
771fe6b9 315{
5a9bcacc 316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 317 struct drm_device *dev = crtc->dev;
318 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 321 u16 misc = 0;
771fe6b9 322
5a9bcacc
AD		 323 memset(&args, 0, sizeof(args));
324 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
327 args.usH_SyncWidth =
328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
332 args.usV_SyncWidth =
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
334
54bfe496
AD		 335 args.ucOverscanRight = radeon_crtc->h_border;
336 args.ucOverscanLeft = radeon_crtc->h_border;
337 args.ucOverscanBottom = radeon_crtc->v_border;
338 args.ucOverscanTop = radeon_crtc->v_border;
339
5a9bcacc
AD		 340 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
341 misc |= ATOM_VSYNC_POLARITY;
342 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
343 misc |= ATOM_HSYNC_POLARITY;
344 if (mode->flags & DRM_MODE_FLAG_CSYNC)
345 misc |= ATOM_COMPOSITESYNC;
346 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
347 misc |= ATOM_INTERLACE;
348 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
349 misc |= ATOM_DOUBLE_CLOCK_MODE;
350
351 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
352 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 353
5a9bcacc 354 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 355}
356
b792210e
AD		 357static void atombios_disable_ss(struct drm_crtc *crtc)
358{
359 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
360 struct drm_device *dev = crtc->dev;
361 struct radeon_device *rdev = dev->dev_private;
362 u32 ss_cntl;
363
364 if (ASIC_IS_DCE4(rdev)) {
365 switch (radeon_crtc->pll_id) {
366 case ATOM_PPLL1:
367 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
368 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
369 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
370 break;
371 case ATOM_PPLL2:
372 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
373 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
374 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
375 break;
376 case ATOM_DCPLL:
377 case ATOM_PPLL_INVALID:
378 return;
379 }
380 } else if (ASIC_IS_AVIVO(rdev)) {
381 switch (radeon_crtc->pll_id) {
382 case ATOM_PPLL1:
383 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
384 ss_cntl &= ~1;
385 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
386 break;
387 case ATOM_PPLL2:
388 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
389 ss_cntl &= ~1;
390 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
391 break;
392 case ATOM_DCPLL:
393 case ATOM_PPLL_INVALID:
394 return;
395 }
396 }
397}
398
399
26b9fc3a
AD		 400union atom_enable_ss {
401 ENABLE_LVDS_SS_PARAMETERS legacy;
402 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
403};
404
b792210e 405static void atombios_enable_ss(struct drm_crtc *crtc)
ebbe1cb9
AD		 406{
407 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
408 struct drm_device *dev = crtc->dev;
409 struct radeon_device *rdev = dev->dev_private;
410 struct drm_encoder *encoder = NULL;
411 struct radeon_encoder *radeon_encoder = NULL;
412 struct radeon_encoder_atom_dig *dig = NULL;
413 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 414 union atom_enable_ss args;
ebbe1cb9
AD		 415 uint16_t percentage = 0;
416 uint8_t type = 0, step = 0, delay = 0, range = 0;
417
bcc1c2a1
AD		 418 /* XXX add ss support for DCE4 */
419 if (ASIC_IS_DCE4(rdev))
420 return;
421
ebbe1cb9
AD		 422 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
423 if (encoder->crtc == crtc) {
424 radeon_encoder = to_radeon_encoder(encoder);
ebbe1cb9 425 /* only enable spread spectrum on LVDS */
d11aa88b
AD		 426 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
427 dig = radeon_encoder->enc_priv;
428 if (dig && dig->ss) {
429 percentage = dig->ss->percentage;
430 type = dig->ss->type;
431 step = dig->ss->step;
432 delay = dig->ss->delay;
433 range = dig->ss->range;
b792210e 434 } else
d11aa88b 435 return;
b792210e 436 } else
ebbe1cb9
AD		 437 return;
438 break;
439 }
440 }
441
442 if (!radeon_encoder)
443 return;
444
26b9fc3a 445 memset(&args, 0, sizeof(args));
ebbe1cb9 446 if (ASIC_IS_AVIVO(rdev)) {
26b9fc3a
AD		 447 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
448 args.v1.ucSpreadSpectrumType = type;
449 args.v1.ucSpreadSpectrumStep = step;
450 args.v1.ucSpreadSpectrumDelay = delay;
451 args.v1.ucSpreadSpectrumRange = range;
452 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
b792210e 453 args.v1.ucEnable = ATOM_ENABLE;
ebbe1cb9 454 } else {
26b9fc3a
AD		 455 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
456 args.legacy.ucSpreadSpectrumType = type;
457 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
458 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
b792210e 459 args.legacy.ucEnable = ATOM_ENABLE;
ebbe1cb9 460 }
26b9fc3a 461 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 462}
463
4eaeca33
AD		 464union adjust_pixel_clock {
465 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 466 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 467};
468
469static u32 atombios_adjust_pll(struct drm_crtc *crtc,
470 struct drm_display_mode *mode,
471 struct radeon_pll *pll)
771fe6b9 472{
771fe6b9
JG		 473 struct drm_device *dev = crtc->dev;
474 struct radeon_device *rdev = dev->dev_private;
475 struct drm_encoder *encoder = NULL;
476 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 477 u32 adjusted_clock = mode->clock;
bcc1c2a1 478 int encoder_mode = 0;
fbee67a6
AD		 479 u32 dp_clock = mode->clock;
480 int bpc = 8;
fc10332b 481
4eaeca33
AD		 482 /* reset the pll flags */
483 pll->flags = 0;
771fe6b9 484
7c27f87d
AD		 485 /* select the PLL algo */
486 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 487 if (radeon_new_pll == 0)
488 pll->algo = PLL_ALGO_LEGACY;
489 else
490 pll->algo = PLL_ALGO_NEW;
491 } else {
492 if (radeon_new_pll == 1)
493 pll->algo = PLL_ALGO_NEW;
7c27f87d
AD		 494 else
495 pll->algo = PLL_ALGO_LEGACY;
383be5d1 496 }
7c27f87d 497
771fe6b9 498 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 499 if ((rdev->family == CHIP_RS600) ||
500 (rdev->family == CHIP_RS690) ||
501 (rdev->family == CHIP_RS740))
2ff776cf 502 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 503 RADEON_PLL_PREFER_CLOSEST_LOWER);
eb1300bc 504
771fe6b9 505 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
fc10332b 506 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 507 else
fc10332b 508 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9 509 } else {
fc10332b 510 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9
JG		 511
512 if (mode->clock > 200000) /* range limits??? */
fc10332b 513 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 514 else
fc10332b 515 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 516
517 }
518
519 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
520 if (encoder->crtc == crtc) {
4eaeca33 521 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 522 encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6
AD		 523 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
524 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
525 if (connector) {
526 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
527 struct radeon_connector_atom_dig *dig_connector =
528 radeon_connector->con_priv;
529
530 dp_clock = dig_connector->dp_clock;
531 }
532 }
533
4eaeca33
AD		 534 if (ASIC_IS_AVIVO(rdev)) {
535 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
536 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
537 adjusted_clock = mode->clock * 2;
a1a4b23b
AD		 538 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
539 pll->algo = PLL_ALGO_LEGACY;
540 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
541 }
0d9958b1
AD		 542 /* There is some evidence (often anecdotal) that RV515 LVDS
543 * (on some boards at least) prefers the legacy algo. I'm not
544 * sure whether this should handled generically or on a
545 * case-by-case quirk basis. Both algos should work fine in the
546 * majority of cases.
547 */
548 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) &&
549 (rdev->family == CHIP_RV515)) {
550 /* allow the user to overrride just in case */
551 if (radeon_new_pll == 1)
552 pll->algo = PLL_ALGO_NEW;
553 else
554 pll->algo = PLL_ALGO_LEGACY;
555 }
4eaeca33
AD		 556 } else {
557 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 558 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 559 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 560 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 561 }
3ce0a23d 562 break;
771fe6b9
JG		 563 }
564 }
565
2606c886
AD		 566 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
567 * accordingly based on the encoder/transmitter to work around
568 * special hw requirements.
569 */
570 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 571 union adjust_pixel_clock args;
4eaeca33
AD		 572 u8 frev, crev;
573 int index;
2606c886 574
2606c886 575 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 576 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
577 &crev))
578 return adjusted_clock;
4eaeca33
AD		 579
580 memset(&args, 0, sizeof(args));
581
582 switch (frev) {
583 case 1:
584 switch (crev) {
585 case 1:
586 case 2:
587 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
588 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 589 args.v1.ucEncodeMode = encoder_mode;
fbee67a6
AD		 590 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
591 /* may want to enable SS on DP eventually */
592 /* args.v1.ucConfig |=
593 ADJUST_DISPLAY_CONFIG_SS_ENABLE;*/
594 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
595 args.v1.ucConfig |=
596 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
597 }
4eaeca33
AD		 598
599 atom_execute_table(rdev->mode_info.atom_context,
600 index, (uint32_t *)&args);
601 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
602 break;
bcc1c2a1
AD		 603 case 3:
604 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
605 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
606 args.v3.sInput.ucEncodeMode = encoder_mode;
607 args.v3.sInput.ucDispPllConfig = 0;
608 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
609 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
610
fbee67a6
AD		 611 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
612 /* may want to enable SS on DP/eDP eventually */
613 /*args.v3.sInput.ucDispPllConfig |=
614 DISPPLL_CONFIG_SS_ENABLE;*/
bcc1c2a1
AD		 615 args.v3.sInput.ucDispPllConfig |=
616 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 617 /* 16200 or 27000 */
618 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
619 } else {
620 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
621 /* deep color support */
622 args.v3.sInput.usPixelClock =
623 cpu_to_le16((mode->clock * bpc / 8) / 10);
624 }
bcc1c2a1
AD		 625 if (dig->coherent_mode)
626 args.v3.sInput.ucDispPllConfig |=
627 DISPPLL_CONFIG_COHERENT_MODE;
628 if (mode->clock > 165000)
629 args.v3.sInput.ucDispPllConfig |=
630 DISPPLL_CONFIG_DUAL_LINK;
631 }
632 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
fbee67a6
AD		 633 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
634 /* may want to enable SS on DP/eDP eventually */
635 /*args.v3.sInput.ucDispPllConfig |=
636 DISPPLL_CONFIG_SS_ENABLE;*/
bcc1c2a1 637 args.v3.sInput.ucDispPllConfig |=
9f998ad7 638 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 639 /* 16200 or 27000 */
640 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
641 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
642 /* want to enable SS on LVDS eventually */
643 /*args.v3.sInput.ucDispPllConfig |=
644 DISPPLL_CONFIG_SS_ENABLE;*/
645 } else {
9f998ad7
AD		 646 if (mode->clock > 165000)
647 args.v3.sInput.ucDispPllConfig |=
648 DISPPLL_CONFIG_DUAL_LINK;
649 }
bcc1c2a1
AD		 650 }
651 atom_execute_table(rdev->mode_info.atom_context,
652 index, (uint32_t *)&args);
653 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
654 if (args.v3.sOutput.ucRefDiv) {
655 pll->flags |= RADEON_PLL_USE_REF_DIV;
656 pll->reference_div = args.v3.sOutput.ucRefDiv;
657 }
658 if (args.v3.sOutput.ucPostDiv) {
659 pll->flags |= RADEON_PLL_USE_POST_DIV;
660 pll->post_div = args.v3.sOutput.ucPostDiv;
661 }
662 break;
4eaeca33
AD		 663 default:
664 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
665 return adjusted_clock;
666 }
667 break;
668 default:
669 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
670 return adjusted_clock;
671 }
d56ef9c8 672 }
4eaeca33
AD		 673 return adjusted_clock;
674}
675
676union set_pixel_clock {
677 SET_PIXEL_CLOCK_PS_ALLOCATION base;
678 PIXEL_CLOCK_PARAMETERS v1;
679 PIXEL_CLOCK_PARAMETERS_V2 v2;
680 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 681 PIXEL_CLOCK_PARAMETERS_V5 v5;
4eaeca33
AD		 682};
683
bcc1c2a1
AD		 684static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
685{
686 struct drm_device *dev = crtc->dev;
687 struct radeon_device *rdev = dev->dev_private;
688 u8 frev, crev;
689 int index;
690 union set_pixel_clock args;
691
692 memset(&args, 0, sizeof(args));
693
694 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 695 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
696 &crev))
697 return;
bcc1c2a1
AD		 698
699 switch (frev) {
700 case 1:
701 switch (crev) {
702 case 5:
703 /* if the default dcpll clock is specified,
704 * SetPixelClock provides the dividers
705 */
706 args.v5.ucCRTC = ATOM_CRTC_INVALID;
707 args.v5.usPixelClock = rdev->clock.default_dispclk;
708 args.v5.ucPpll = ATOM_DCPLL;
709 break;
710 default:
711 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
712 return;
713 }
714 break;
715 default:
716 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
717 return;
718 }
719 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
720}
721
37f9003b
AD		 722static void atombios_crtc_program_pll(struct drm_crtc *crtc,
723 int crtc_id,
724 int pll_id,
725 u32 encoder_mode,
726 u32 encoder_id,
727 u32 clock,
728 u32 ref_div,
729 u32 fb_div,
730 u32 frac_fb_div,
731 u32 post_div)
4eaeca33 732{
4eaeca33
AD		 733 struct drm_device *dev = crtc->dev;
734 struct radeon_device *rdev = dev->dev_private;
4eaeca33 735 u8 frev, crev;
37f9003b 736 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 737 union set_pixel_clock args;
4eaeca33
AD		 738
739 memset(&args, 0, sizeof(args));
740
a084e6ee
AD		 741 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
742 &crev))
743 return;
771fe6b9
JG		 744
745 switch (frev) {
746 case 1:
747 switch (crev) {
748 case 1:
37f9003b
AD		 749 if (clock == ATOM_DISABLE)
750 return;
751 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 752 args.v1.usRefDiv = cpu_to_le16(ref_div);
753 args.v1.usFbDiv = cpu_to_le16(fb_div);
754 args.v1.ucFracFbDiv = frac_fb_div;
755 args.v1.ucPostDiv = post_div;
37f9003b
AD		 756 args.v1.ucPpll = pll_id;
757 args.v1.ucCRTC = crtc_id;
4eaeca33 758 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 759 break;
760 case 2:
37f9003b 761 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 762 args.v2.usRefDiv = cpu_to_le16(ref_div);
763 args.v2.usFbDiv = cpu_to_le16(fb_div);
764 args.v2.ucFracFbDiv = frac_fb_div;
765 args.v2.ucPostDiv = post_div;
37f9003b
AD		 766 args.v2.ucPpll = pll_id;
767 args.v2.ucCRTC = crtc_id;
4eaeca33 768 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 769 break;
770 case 3:
37f9003b 771 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 772 args.v3.usRefDiv = cpu_to_le16(ref_div);
773 args.v3.usFbDiv = cpu_to_le16(fb_div);
774 args.v3.ucFracFbDiv = frac_fb_div;
775 args.v3.ucPostDiv = post_div;
37f9003b
AD		 776 args.v3.ucPpll = pll_id;
777 args.v3.ucMiscInfo = (pll_id << 2);
778 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 779 args.v3.ucEncoderMode = encoder_mode;
780 break;
781 case 5:
37f9003b
AD		 782 args.v5.ucCRTC = crtc_id;
783 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 784 args.v5.ucRefDiv = ref_div;
785 args.v5.usFbDiv = cpu_to_le16(fb_div);
786 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
787 args.v5.ucPostDiv = post_div;
788 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
37f9003b 789 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 790 args.v5.ucEncoderMode = encoder_mode;
37f9003b 791 args.v5.ucPpll = pll_id;
771fe6b9
JG		 792 break;
793 default:
794 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
795 return;
796 }
797 break;
798 default:
799 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
800 return;
801 }
802
771fe6b9
JG		 803 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
804}
805
37f9003b
AD		 806static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
807{
808 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
809 struct drm_device *dev = crtc->dev;
810 struct radeon_device *rdev = dev->dev_private;
811 struct drm_encoder *encoder = NULL;
812 struct radeon_encoder *radeon_encoder = NULL;
813 u32 pll_clock = mode->clock;
814 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
815 struct radeon_pll *pll;
816 u32 adjusted_clock;
817 int encoder_mode = 0;
818
819 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
820 if (encoder->crtc == crtc) {
821 radeon_encoder = to_radeon_encoder(encoder);
822 encoder_mode = atombios_get_encoder_mode(encoder);
823 break;
824 }
825 }
826
827 if (!radeon_encoder)
828 return;
829
830 switch (radeon_crtc->pll_id) {
831 case ATOM_PPLL1:
832 pll = &rdev->clock.p1pll;
833 break;
834 case ATOM_PPLL2:
835 pll = &rdev->clock.p2pll;
836 break;
837 case ATOM_DCPLL:
838 case ATOM_PPLL_INVALID:
839 default:
840 pll = &rdev->clock.dcpll;
841 break;
842 }
843
844 /* adjust pixel clock as needed */
845 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
846
847 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
848 &ref_div, &post_div);
849
850 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
851 encoder_mode, radeon_encoder->encoder_id, mode->clock,
852 ref_div, fb_div, frac_fb_div, post_div);
853
854}
855
bcc1c2a1
AD		 856static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
857 struct drm_framebuffer *old_fb)
858{
859 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
860 struct drm_device *dev = crtc->dev;
861 struct radeon_device *rdev = dev->dev_private;
862 struct radeon_framebuffer *radeon_fb;
863 struct drm_gem_object *obj;
864 struct radeon_bo *rbo;
865 uint64_t fb_location;
866 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
867 int r;
868
869 /* no fb bound */
870 if (!crtc->fb) {
d9fdaafb 871 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 872 return 0;
873 }
874
875 radeon_fb = to_radeon_framebuffer(crtc->fb);
876
877 /* Pin framebuffer & get tilling informations */
878 obj = radeon_fb->obj;
879 rbo = obj->driver_private;
880 r = radeon_bo_reserve(rbo, false);
881 if (unlikely(r != 0))
882 return r;
883 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
884 if (unlikely(r != 0)) {
885 radeon_bo_unreserve(rbo);
886 return -EINVAL;
887 }
888 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
889 radeon_bo_unreserve(rbo);
890
891 switch (crtc->fb->bits_per_pixel) {
892 case 8:
893 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
894 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
895 break;
896 case 15:
897 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
898 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
899 break;
900 case 16:
901 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
902 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
903 break;
904 case 24:
905 case 32:
906 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
907 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
908 break;
909 default:
910 DRM_ERROR("Unsupported screen depth %d\n",
911 crtc->fb->bits_per_pixel);
912 return -EINVAL;
913 }
914
97d66328
AD		 915 if (tiling_flags & RADEON_TILING_MACRO)
916 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
917 else if (tiling_flags & RADEON_TILING_MICRO)
918 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
919
bcc1c2a1
AD		 920 switch (radeon_crtc->crtc_id) {
921 case 0:
922 WREG32(AVIVO_D1VGA_CONTROL, 0);
923 break;
924 case 1:
925 WREG32(AVIVO_D2VGA_CONTROL, 0);
926 break;
927 case 2:
928 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
929 break;
930 case 3:
931 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
932 break;
933 case 4:
934 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
935 break;
936 case 5:
937 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
938 break;
939 default:
940 break;
941 }
942
943 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
944 upper_32_bits(fb_location));
945 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
946 upper_32_bits(fb_location));
947 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
948 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
949 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
950 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
951 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
952
953 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
954 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
955 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
956 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
957 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
958 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
959
960 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
961 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
962 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
963
964 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
965 crtc->mode.vdisplay);
966 x &= ~3;
967 y &= ~1;
968 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
969 (x << 16) | y);
970 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
971 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
972
973 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
974 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
975 EVERGREEN_INTERLEAVE_EN);
976 else
977 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
978
979 if (old_fb && old_fb != crtc->fb) {
980 radeon_fb = to_radeon_framebuffer(old_fb);
981 rbo = radeon_fb->obj->driver_private;
982 r = radeon_bo_reserve(rbo, false);
983 if (unlikely(r != 0))
984 return r;
985 radeon_bo_unpin(rbo);
986 radeon_bo_unreserve(rbo);
987 }
988
989 /* Bytes per pixel may have changed */
990 radeon_bandwidth_update(rdev);
991
992 return 0;
993}
994
54f088a9
AD		 995static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
996 struct drm_framebuffer *old_fb)
771fe6b9
JG		 997{
998 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
999 struct drm_device *dev = crtc->dev;
1000 struct radeon_device *rdev = dev->dev_private;
1001 struct radeon_framebuffer *radeon_fb;
1002 struct drm_gem_object *obj;
4c788679 1003 struct radeon_bo *rbo;
771fe6b9 1004 uint64_t fb_location;
e024e110 1005 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 1006 int r;
771fe6b9 1007
2de3b484
JG		 1008 /* no fb bound */
1009 if (!crtc->fb) {
d9fdaafb 1010 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1011 return 0;
1012 }
771fe6b9
JG		 1013
1014 radeon_fb = to_radeon_framebuffer(crtc->fb);
1015
4c788679 1016 /* Pin framebuffer & get tilling informations */
771fe6b9 1017 obj = radeon_fb->obj;
4c788679
JG		 1018 rbo = obj->driver_private;
1019 r = radeon_bo_reserve(rbo, false);
1020 if (unlikely(r != 0))
1021 return r;
1022 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1023 if (unlikely(r != 0)) {
1024 radeon_bo_unreserve(rbo);
771fe6b9
JG		 1025 return -EINVAL;
1026 }
4c788679
JG		 1027 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1028 radeon_bo_unreserve(rbo);
771fe6b9
JG		 1029
1030 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 1031 case 8:
1032 fb_format =
1033 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1034 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1035 break;
771fe6b9
JG		 1036 case 15:
1037 fb_format =
1038 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1039 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1040 break;
1041 case 16:
1042 fb_format =
1043 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1044 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1045 break;
1046 case 24:
1047 case 32:
1048 fb_format =
1049 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1050 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1051 break;
1052 default:
1053 DRM_ERROR("Unsupported screen depth %d\n",
1054 crtc->fb->bits_per_pixel);
1055 return -EINVAL;
1056 }
1057
40c4ac1c
AD		 1058 if (rdev->family >= CHIP_R600) {
1059 if (tiling_flags & RADEON_TILING_MACRO)
1060 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1061 else if (tiling_flags & RADEON_TILING_MICRO)
1062 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1063 } else {
1064 if (tiling_flags & RADEON_TILING_MACRO)
1065 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1066
40c4ac1c
AD		 1067 if (tiling_flags & RADEON_TILING_MICRO)
1068 fb_format |= AVIVO_D1GRPH_TILED;
1069 }
e024e110 1070
771fe6b9
JG		 1071 if (radeon_crtc->crtc_id == 0)
1072 WREG32(AVIVO_D1VGA_CONTROL, 0);
1073 else
1074 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1075
1076 if (rdev->family >= CHIP_RV770) {
1077 if (radeon_crtc->crtc_id) {
95347871
AD		 1078 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1079 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1080 } else {
95347871
AD		 1081 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1082 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1083 }
1084 }
771fe6b9
JG		 1085 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1086 (u32) fb_location);
1087 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1088 radeon_crtc->crtc_offset, (u32) fb_location);
1089 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1090
1091 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1092 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1093 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1094 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1095 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1096 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1097
1098 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1099 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1100 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1101
1102 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1103 crtc->mode.vdisplay);
1104 x &= ~3;
1105 y &= ~1;
1106 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1107 (x << 16) | y);
1108 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1109 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1110
1111 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1112 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1113 AVIVO_D1MODE_INTERLEAVE_EN);
1114 else
1115 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1116
1117 if (old_fb && old_fb != crtc->fb) {
1118 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 1119 rbo = radeon_fb->obj->driver_private;
1120 r = radeon_bo_reserve(rbo, false);
1121 if (unlikely(r != 0))
1122 return r;
1123 radeon_bo_unpin(rbo);
1124 radeon_bo_unreserve(rbo);
771fe6b9 1125 }
f30f37de
MD		 1126
1127 /* Bytes per pixel may have changed */
1128 radeon_bandwidth_update(rdev);
1129
771fe6b9
JG		 1130 return 0;
1131}
1132
54f088a9
AD		 1133int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1134 struct drm_framebuffer *old_fb)
1135{
1136 struct drm_device *dev = crtc->dev;
1137 struct radeon_device *rdev = dev->dev_private;
1138
bcc1c2a1
AD		 1139 if (ASIC_IS_DCE4(rdev))
1140 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1141 else if (ASIC_IS_AVIVO(rdev))
54f088a9
AD		 1142 return avivo_crtc_set_base(crtc, x, y, old_fb);
1143 else
1144 return radeon_crtc_set_base(crtc, x, y, old_fb);
1145}
1146
615e0cb6
AD		 1147/* properly set additional regs when using atombios */
1148static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1149{
1150 struct drm_device *dev = crtc->dev;
1151 struct radeon_device *rdev = dev->dev_private;
1152 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1153 u32 disp_merge_cntl;
1154
1155 switch (radeon_crtc->crtc_id) {
1156 case 0:
1157 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1158 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1159 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1160 break;
1161 case 1:
1162 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1163 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1164 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1165 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1166 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1167 break;
1168 }
1169}
1170
bcc1c2a1
AD		 1171static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1172{
1173 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1174 struct drm_device *dev = crtc->dev;
1175 struct radeon_device *rdev = dev->dev_private;
1176 struct drm_encoder *test_encoder;
1177 struct drm_crtc *test_crtc;
1178 uint32_t pll_in_use = 0;
1179
1180 if (ASIC_IS_DCE4(rdev)) {
1181 /* if crtc is driving DP and we have an ext clock, use that */
1182 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1183 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1184 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1185 if (rdev->clock.dp_extclk)
1186 return ATOM_PPLL_INVALID;
1187 }
1188 }
1189 }
1190
1191 /* otherwise, pick one of the plls */
1192 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1193 struct radeon_crtc *radeon_test_crtc;
1194
1195 if (crtc == test_crtc)
1196 continue;
1197
1198 radeon_test_crtc = to_radeon_crtc(test_crtc);
1199 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1200 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1201 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1202 }
1203 if (!(pll_in_use & 1))
1204 return ATOM_PPLL1;
1205 return ATOM_PPLL2;
1206 } else
1207 return radeon_crtc->crtc_id;
1208
1209}
1210
771fe6b9
JG		 1211int atombios_crtc_mode_set(struct drm_crtc *crtc,
1212 struct drm_display_mode *mode,
1213 struct drm_display_mode *adjusted_mode,
1214 int x, int y, struct drm_framebuffer *old_fb)
1215{
1216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1217 struct drm_device *dev = crtc->dev;
1218 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1219 struct drm_encoder *encoder;
1220 bool is_tvcv = false;
771fe6b9 1221
54bfe496
AD		 1222 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1223 /* find tv std */
1224 if (encoder->crtc == crtc) {
1225 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1226 if (radeon_encoder->active_device &
1227 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1228 is_tvcv = true;
1229 }
1230 }
771fe6b9 1231
b792210e 1232 atombios_disable_ss(crtc);
bcc1c2a1
AD		 1233 /* always set DCPLL */
1234 if (ASIC_IS_DCE4(rdev))
1235 atombios_crtc_set_dcpll(crtc);
771fe6b9 1236 atombios_crtc_set_pll(crtc, adjusted_mode);
b792210e 1237 atombios_enable_ss(crtc);
771fe6b9 1238
54bfe496 1239 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1240 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1241 else if (ASIC_IS_AVIVO(rdev)) {
1242 if (is_tvcv)
1243 atombios_crtc_set_timing(crtc, adjusted_mode);
1244 else
1245 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1246 } else {
bcc1c2a1 1247 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1248 if (radeon_crtc->crtc_id == 0)
1249 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1250 radeon_legacy_atom_fixup(crtc);
771fe6b9 1251 }
bcc1c2a1 1252 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1253 atombios_overscan_setup(crtc, mode, adjusted_mode);
1254 atombios_scaler_setup(crtc);
771fe6b9
JG		 1255 return 0;
1256}
1257
1258static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1259 struct drm_display_mode *mode,
1260 struct drm_display_mode *adjusted_mode)
1261{
03214bd5
AD		 1262 struct drm_device *dev = crtc->dev;
1263 struct radeon_device *rdev = dev->dev_private;
1264
1265 /* adjust pm to upcoming mode change */
1266 radeon_pm_compute_clocks(rdev);
1267
c93bb85b
JG		 1268 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1269 return false;
771fe6b9
JG		 1270 return true;
1271}
1272
1273static void atombios_crtc_prepare(struct drm_crtc *crtc)
1274{
267364ac
AD		 1275 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1276
1277 /* pick pll */
1278 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1279
37b4390e 1280 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1281 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1282}
1283
1284static void atombios_crtc_commit(struct drm_crtc *crtc)
1285{
1286 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1287 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1288}
1289
37f9003b
AD		 1290static void atombios_crtc_disable(struct drm_crtc *crtc)
1291{
1292 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1293 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1294
1295 switch (radeon_crtc->pll_id) {
1296 case ATOM_PPLL1:
1297 case ATOM_PPLL2:
1298 /* disable the ppll */
1299 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1300 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1301 break;
1302 default:
1303 break;
1304 }
1305 radeon_crtc->pll_id = -1;
1306}
1307
771fe6b9
JG		 1308static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1309 .dpms = atombios_crtc_dpms,
1310 .mode_fixup = atombios_crtc_mode_fixup,
1311 .mode_set = atombios_crtc_mode_set,
1312 .mode_set_base = atombios_crtc_set_base,
1313 .prepare = atombios_crtc_prepare,
1314 .commit = atombios_crtc_commit,
068143d3 1315 .load_lut = radeon_crtc_load_lut,
37f9003b 1316 .disable = atombios_crtc_disable,
771fe6b9
JG		 1317};
1318
1319void radeon_atombios_init_crtc(struct drm_device *dev,
1320 struct radeon_crtc *radeon_crtc)
1321{
bcc1c2a1
AD		 1322 struct radeon_device *rdev = dev->dev_private;
1323
1324 if (ASIC_IS_DCE4(rdev)) {
1325 switch (radeon_crtc->crtc_id) {
1326 case 0:
1327 default:
12d7798f 1328 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1329 break;
1330 case 1:
12d7798f 1331 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1332 break;
1333 case 2:
12d7798f 1334 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1335 break;
1336 case 3:
12d7798f 1337 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1338 break;
1339 case 4:
12d7798f 1340 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1341 break;
1342 case 5:
12d7798f 1343 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1344 break;
1345 }
1346 } else {
1347 if (radeon_crtc->crtc_id == 1)
1348 radeon_crtc->crtc_offset =
1349 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1350 else
1351 radeon_crtc->crtc_offset = 0;
1352 }
1353 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1354 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1355}
Clone of davem's net-next-2.6 tree