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drm/nv50: fix DP->DVI if output has been programmed for native DP previously
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv50_display.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "nv50_display.h"
28#include "nouveau_crtc.h"
29#include "nouveau_encoder.h"
30#include "nouveau_connector.h"
31#include "nouveau_fb.h"
4abe3520 32#include "nouveau_fbcon.h"
6ee73861
BS		 33#include "drm_crtc_helper.h"
34
35static void
36nv50_evo_channel_del(struct nouveau_channel **pchan)
37{
38 struct nouveau_channel *chan = *pchan;
39
40 if (!chan)
41 return;
42 *pchan = NULL;
43
44 nouveau_gpuobj_channel_takedown(chan);
45 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
46
47 if (chan->user)
48 iounmap(chan->user);
49
50 kfree(chan);
51}
52
53static int
54nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
55 uint32_t tile_flags, uint32_t magic_flags,
56 uint32_t offset, uint32_t limit)
57{
58 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
59 struct drm_device *dev = evo->dev;
60 struct nouveau_gpuobj *obj = NULL;
61 int ret;
62
63 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
64 if (ret)
65 return ret;
66 obj->engine = NVOBJ_ENGINE_DISPLAY;
67
68 ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
69 if (ret) {
70 nouveau_gpuobj_del(dev, &obj);
71 return ret;
72 }
73
74 dev_priv->engine.instmem.prepare_access(dev, true);
75 nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
76 nv_wo32(dev, obj, 1, limit);
77 nv_wo32(dev, obj, 2, offset);
78 nv_wo32(dev, obj, 3, 0x00000000);
79 nv_wo32(dev, obj, 4, 0x00000000);
80 nv_wo32(dev, obj, 5, 0x00010000);
81 dev_priv->engine.instmem.finish_access(dev);
82
83 return 0;
84}
85
86static int
87nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
88{
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 struct nouveau_channel *chan;
91 int ret;
92
93 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
94 if (!chan)
95 return -ENOMEM;
96 *pchan = chan;
97
98 chan->id = -1;
99 chan->dev = dev;
100 chan->user_get = 4;
101 chan->user_put = 0;
102
103 INIT_LIST_HEAD(&chan->ramht_refs);
104
105 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
106 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
107 if (ret) {
108 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
109 nv50_evo_channel_del(pchan);
110 return ret;
111 }
112
b833ac26
BS		 113 ret = drm_mm_init(&chan->ramin_heap,
114 chan->ramin->gpuobj->im_pramin->start, 32768);
6ee73861
BS		 115 if (ret) {
116 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
117 nv50_evo_channel_del(pchan);
118 return ret;
119 }
120
121 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
122 0, &chan->ramht);
123 if (ret) {
124 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
125 nv50_evo_channel_del(pchan);
126 return ret;
127 }
128
129 if (dev_priv->chipset != 0x50) {
130 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
131 0, 0xffffffff);
132 if (ret) {
133 nv50_evo_channel_del(pchan);
134 return ret;
135 }
136
137
138 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
139 0, 0xffffffff);
140 if (ret) {
141 nv50_evo_channel_del(pchan);
142 return ret;
143 }
144 }
145
146 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
a76fb4e8 147 0, dev_priv->vram_size);
6ee73861
BS		 148 if (ret) {
149 nv50_evo_channel_del(pchan);
150 return ret;
151 }
152
153 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
154 false, true, &chan->pushbuf_bo);
155 if (ret == 0)
156 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
157 if (ret) {
158 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
159 nv50_evo_channel_del(pchan);
160 return ret;
161 }
162
163 ret = nouveau_bo_map(chan->pushbuf_bo);
164 if (ret) {
165 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
166 nv50_evo_channel_del(pchan);
167 return ret;
168 }
169
170 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
171 NV50_PDISPLAY_USER(0), PAGE_SIZE);
172 if (!chan->user) {
173 NV_ERROR(dev, "Error mapping EVO control regs.\n");
174 nv50_evo_channel_del(pchan);
175 return -ENOMEM;
176 }
177
178 return 0;
179}
180
181int
182nv50_display_init(struct drm_device *dev)
183{
184 struct drm_nouveau_private *dev_priv = dev->dev_private;
185 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
186 struct nouveau_channel *evo = dev_priv->evo;
187 struct drm_connector *connector;
188 uint32_t val, ram_amount, hpd_en[2];
189 uint64_t start;
190 int ret, i;
191
ef2bb506 192 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 193
194 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
195 /*
196 * I think the 0x006101XX range is some kind of main control area
197 * that enables things.
198 */
199 /* CRTC? */
200 for (i = 0; i < 2; i++) {
201 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
202 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
203 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
204 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
205 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
206 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
207 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
208 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
209 }
210 /* DAC */
211 for (i = 0; i < 3; i++) {
212 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
213 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
214 }
215 /* SOR */
216 for (i = 0; i < 4; i++) {
217 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
218 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
219 }
220 /* Something not yet in use, tv-out maybe. */
221 for (i = 0; i < 3; i++) {
222 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
223 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
224 }
225
226 for (i = 0; i < 3; i++) {
227 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
228 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
229 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
230 }
231
232 /* This used to be in crtc unblank, but seems out of place there. */
233 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
234 /* RAM is clamped to 256 MiB. */
a76fb4e8 235 ram_amount = dev_priv->vram_size;
ef2bb506 236 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
6ee73861
BS		 237 if (ram_amount > 256*1024*1024)
238 ram_amount = 256*1024*1024;
239 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
240 nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
241 nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
242
243 /* The precise purpose is unknown, i suspect it has something to do
244 * with text mode.
245 */
246 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
247 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
248 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
249 if (!nv_wait(0x006194e8, 2, 0)) {
250 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
251 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
252 nv_rd32(dev, 0x6194e8));
253 return -EBUSY;
254 }
255 }
256
257 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
258 * stuck in some unspecified state
259 */
260 start = ptimer->read(dev);
261 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
262 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
263 if ((val & 0x9f0000) == 0x20000)
264 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
265 val | 0x800000);
266
267 if ((val & 0x3f0000) == 0x30000)
268 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
269 val | 0x200000);
270
271 if (ptimer->read(dev) - start > 1000000000ULL) {
272 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
273 NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
274 return -EBUSY;
275 }
276 }
277
278 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
279 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
280 if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
281 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
282 NV_ERROR(dev, "0x610200 = 0x%08x\n",
283 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
284 return -EBUSY;
285 }
286
287 for (i = 0; i < 2; i++) {
288 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
289 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
290 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
291 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
292 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
293 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
294 return -EBUSY;
295 }
296
297 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
298 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
299 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
300 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
301 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
302 NV_ERROR(dev, "timeout: "
303 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
304 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
305 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
306 return -EBUSY;
307 }
308 }
309
310 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
311
312 /* initialise fifo */
313 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
314 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
315 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
316 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
317 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
318 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
319 if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
320 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
321 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
322 return -EBUSY;
323 }
324 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
325 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
326 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
327 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
328 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
329 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
330 nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
331
332 evo->dma.max = (4096/4) - 2;
333 evo->dma.put = 0;
334 evo->dma.cur = evo->dma.put;
335 evo->dma.free = evo->dma.max - evo->dma.cur;
336
337 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
338 if (ret)
339 return ret;
340
341 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
342 OUT_RING(evo, 0);
343
344 ret = RING_SPACE(evo, 11);
345 if (ret)
346 return ret;
347 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
348 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
349 OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
350 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
351 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
352 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
353 OUT_RING(evo, 0);
354 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
355 OUT_RING(evo, 0);
356 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
357 OUT_RING(evo, 0);
358 FIRE_RING(evo);
359 if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
360 NV_ERROR(dev, "evo pushbuf stalled\n");
361
362 /* enable clock change interrupts. */
363 nv_wr32(dev, 0x610028, 0x00010001);
364 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
365 NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
366 NV50_PDISPLAY_INTR_EN_CLK_UNK40));
367
368 /* enable hotplug interrupts */
369 hpd_en[0] = hpd_en[1] = 0;
370 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
371 struct nouveau_connector *conn = nouveau_connector(connector);
372 struct dcb_gpio_entry *gpio;
373
11575639 374 if (conn->dcb->gpio_tag == 0xff)
6ee73861
BS		 375 continue;
376
377 gpio = nouveau_bios_gpio_entry(dev, conn->dcb->gpio_tag);
378 if (!gpio)
379 continue;
380
381 hpd_en[gpio->line >> 4] |= (0x00010001 << (gpio->line & 0xf));
382 }
383
384 nv_wr32(dev, 0xe054, 0xffffffff);
385 nv_wr32(dev, 0xe050, hpd_en[0]);
386 if (dev_priv->chipset >= 0x90) {
387 nv_wr32(dev, 0xe074, 0xffffffff);
388 nv_wr32(dev, 0xe070, hpd_en[1]);
389 }
390
391 return 0;
392}
393
394static int nv50_display_disable(struct drm_device *dev)
395{
396 struct drm_nouveau_private *dev_priv = dev->dev_private;
397 struct drm_crtc *drm_crtc;
398 int ret, i;
399
ef2bb506 400 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 401
402 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
403 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
404
405 nv50_crtc_blank(crtc, true);
406 }
407
408 ret = RING_SPACE(dev_priv->evo, 2);
409 if (ret == 0) {
410 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
411 OUT_RING(dev_priv->evo, 0);
412 }
413 FIRE_RING(dev_priv->evo);
414
415 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
416 * cleaning up?
417 */
418 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
419 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
420 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
421
422 if (!crtc->base.enabled)
423 continue;
424
425 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
426 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
427 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
428 "0x%08x\n", mask, mask);
429 NV_ERROR(dev, "0x610024 = 0x%08x\n",
430 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
431 }
432 }
433
434 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
435 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
436 if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
437 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
438 NV_ERROR(dev, "0x610200 = 0x%08x\n",
439 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
440 }
441
442 for (i = 0; i < 3; i++) {
443 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
444 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
445 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
446 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
447 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
448 }
449 }
450
451 /* disable interrupts. */
452 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
453
454 /* disable hotplug interrupts */
455 nv_wr32(dev, 0xe054, 0xffffffff);
456 nv_wr32(dev, 0xe050, 0x00000000);
457 if (dev_priv->chipset >= 0x90) {
458 nv_wr32(dev, 0xe074, 0xffffffff);
459 nv_wr32(dev, 0xe070, 0x00000000);
460 }
461 return 0;
462}
463
464int nv50_display_create(struct drm_device *dev)
465{
466 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 467 struct dcb_table *dcb = &dev_priv->vbios.dcb;
8f1a6086 468 struct drm_connector *connector, *ct;
6ee73861
BS		 469 int ret, i;
470
ef2bb506 471 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 472
473 /* init basic kernel modesetting */
474 drm_mode_config_init(dev);
475
476 /* Initialise some optional connector properties. */
477 drm_mode_create_scaling_mode_property(dev);
478 drm_mode_create_dithering_property(dev);
479
480 dev->mode_config.min_width = 0;
481 dev->mode_config.min_height = 0;
482
483 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
484
485 dev->mode_config.max_width = 8192;
486 dev->mode_config.max_height = 8192;
487
488 dev->mode_config.fb_base = dev_priv->fb_phys;
489
490 /* Create EVO channel */
491 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
492 if (ret) {
493 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
494 return ret;
495 }
496
497 /* Create CRTC objects */
498 for (i = 0; i < 2; i++)
499 nv50_crtc_create(dev, i);
500
501 /* We setup the encoders from the BIOS table */
502 for (i = 0 ; i < dcb->entries; i++) {
503 struct dcb_entry *entry = &dcb->entry[i];
504
505 if (entry->location != DCB_LOC_ON_CHIP) {
506 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
507 entry->type, ffs(entry->or) - 1);
508 continue;
509 }
510
8f1a6086
BS		 511 connector = nouveau_connector_create(dev, entry->connector);
512 if (IS_ERR(connector))
513 continue;
514
6ee73861
BS		 515 switch (entry->type) {
516 case OUTPUT_TMDS:
517 case OUTPUT_LVDS:
518 case OUTPUT_DP:
8f1a6086 519 nv50_sor_create(connector, entry);
6ee73861
BS		 520 break;
521 case OUTPUT_ANALOG:
8f1a6086 522 nv50_dac_create(connector, entry);
6ee73861
BS		 523 break;
524 default:
525 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
526 continue;
527 }
6ee73861
BS		 528 }
529
8f1a6086
BS		 530 list_for_each_entry_safe(connector, ct,
531 &dev->mode_config.connector_list, head) {
532 if (!connector->encoder_ids[0]) {
533 NV_WARN(dev, "%s has no encoders, removing\n",
534 drm_get_connector_name(connector));
535 connector->funcs->destroy(connector);
536 }
6ee73861
BS		 537 }
538
539 ret = nv50_display_init(dev);
a1663ed3
BS		 540 if (ret) {
541 nv50_display_destroy(dev);
6ee73861 542 return ret;
a1663ed3 543 }
6ee73861
BS		 544
545 return 0;
546}
547
548int nv50_display_destroy(struct drm_device *dev)
549{
550 struct drm_nouveau_private *dev_priv = dev->dev_private;
551
ef2bb506 552 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 553
554 drm_mode_config_cleanup(dev);
555
556 nv50_display_disable(dev);
557 nv50_evo_channel_del(&dev_priv->evo);
558
559 return 0;
560}
561
562static inline uint32_t
563nv50_display_mode_ctrl(struct drm_device *dev, bool sor, int or)
564{
565 struct drm_nouveau_private *dev_priv = dev->dev_private;
566 uint32_t mc;
567
568 if (sor) {
569 if (dev_priv->chipset < 0x90 ||
570 dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
571 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(or));
572 else
573 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(or));
574 } else {
575 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(or));
576 }
577
578 return mc;
579}
580
581static int
582nv50_display_irq_head(struct drm_device *dev, int *phead,
583 struct dcb_entry **pdcbent)
584{
585 struct drm_nouveau_private *dev_priv = dev->dev_private;
586 uint32_t unk30 = nv_rd32(dev, NV50_PDISPLAY_UNK30_CTRL);
587 uint32_t dac = 0, sor = 0;
588 int head, i, or = 0, type = OUTPUT_ANY;
589
590 /* We're assuming that head 0 *or* head 1 will be active here,
591 * and not both. I'm not sure if the hw will even signal both
592 * ever, but it definitely shouldn't for us as we commit each
593 * CRTC separately, and submission will be blocked by the GPU
594 * until we handle each in turn.
595 */
ef2bb506 596 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
6ee73861
BS		 597 head = ffs((unk30 >> 9) & 3) - 1;
598 if (head < 0)
599 return -EINVAL;
600
601 /* This assumes CRTCs are never bound to multiple encoders, which
602 * should be the case.
603 */
604 for (i = 0; i < 3 && type == OUTPUT_ANY; i++) {
605 uint32_t mc = nv50_display_mode_ctrl(dev, false, i);
606 if (!(mc & (1 << head)))
607 continue;
608
609 switch ((mc >> 8) & 0xf) {
610 case 0: type = OUTPUT_ANALOG; break;
611 case 1: type = OUTPUT_TV; break;
612 default:
613 NV_ERROR(dev, "unknown dac mode_ctrl: 0x%08x\n", dac);
614 return -1;
615 }
616
617 or = i;
618 }
619
620 for (i = 0; i < 4 && type == OUTPUT_ANY; i++) {
621 uint32_t mc = nv50_display_mode_ctrl(dev, true, i);
622 if (!(mc & (1 << head)))
623 continue;
624
625 switch ((mc >> 8) & 0xf) {
626 case 0: type = OUTPUT_LVDS; break;
627 case 1: type = OUTPUT_TMDS; break;
628 case 2: type = OUTPUT_TMDS; break;
629 case 5: type = OUTPUT_TMDS; break;
630 case 8: type = OUTPUT_DP; break;
631 case 9: type = OUTPUT_DP; break;
632 default:
633 NV_ERROR(dev, "unknown sor mode_ctrl: 0x%08x\n", sor);
634 return -1;
635 }
636
637 or = i;
638 }
639
ef2bb506 640 NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
6ee73861
BS		 641 if (type == OUTPUT_ANY) {
642 NV_ERROR(dev, "unknown encoder!!\n");
643 return -1;
644 }
645
04a39c57
BS		 646 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
647 struct dcb_entry *dcbent = &dev_priv->vbios.dcb.entry[i];
6ee73861
BS		 648
649 if (dcbent->type != type)
650 continue;
651
652 if (!(dcbent->or & (1 << or)))
653 continue;
654
655 *phead = head;
656 *pdcbent = dcbent;
657 return 0;
658 }
659
660 NV_ERROR(dev, "no DCB entry for %d %d\n", dac != 0, or);
661 return 0;
662}
663
664static uint32_t
665nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
666 int pxclk)
667{
668 struct drm_nouveau_private *dev_priv = dev->dev_private;
75c722d7
BS		 669 struct nouveau_connector *nv_connector = NULL;
670 struct drm_encoder *encoder;
04a39c57 671 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 672 uint32_t mc, script = 0, or;
673
75c722d7
BS		 674 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
675 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
676
677 if (nv_encoder->dcb != dcbent)
678 continue;
679
680 nv_connector = nouveau_encoder_connector_get(nv_encoder);
681 break;
682 }
683
6ee73861
BS		 684 or = ffs(dcbent->or) - 1;
685 mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
686 switch (dcbent->type) {
687 case OUTPUT_LVDS:
688 script = (mc >> 8) & 0xf;
04a39c57 689 if (bios->fp_no_ddc) {
6ee73861
BS		 690 if (bios->fp.dual_link)
691 script |= 0x0100;
692 if (bios->fp.if_is_24bit)
693 script |= 0x0200;
694 } else {
695 if (pxclk >= bios->fp.duallink_transition_clk) {
696 script |= 0x0100;
697 if (bios->fp.strapless_is_24bit & 2)
698 script |= 0x0200;
699 } else
700 if (bios->fp.strapless_is_24bit & 1)
701 script |= 0x0200;
75c722d7
BS		 702
703 if (nv_connector && nv_connector->edid &&
704 (nv_connector->edid->revision >= 4) &&
705 (nv_connector->edid->input & 0x70) >= 0x20)
706 script |= 0x0200;
6ee73861
BS		 707 }
708
709 if (nouveau_uscript_lvds >= 0) {
710 NV_INFO(dev, "override script 0x%04x with 0x%04x "
711 "for output LVDS-%d\n", script,
712 nouveau_uscript_lvds, or);
713 script = nouveau_uscript_lvds;
714 }
715 break;
716 case OUTPUT_TMDS:
717 script = (mc >> 8) & 0xf;
718 if (pxclk >= 165000)
719 script |= 0x0100;
720
721 if (nouveau_uscript_tmds >= 0) {
722 NV_INFO(dev, "override script 0x%04x with 0x%04x "
723 "for output TMDS-%d\n", script,
724 nouveau_uscript_tmds, or);
725 script = nouveau_uscript_tmds;
726 }
727 break;
728 case OUTPUT_DP:
729 script = (mc >> 8) & 0xf;
730 break;
731 case OUTPUT_ANALOG:
732 script = 0xff;
733 break;
734 default:
735 NV_ERROR(dev, "modeset on unsupported output type!\n");
736 break;
737 }
738
739 return script;
740}
741
742static void
743nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
744{
745 struct drm_nouveau_private *dev_priv = dev->dev_private;
746 struct nouveau_channel *chan;
747 struct list_head *entry, *tmp;
748
749 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
750 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
751
752 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
753 chan->nvsw.vblsem_rval);
754 list_del(&chan->nvsw.vbl_wait);
755 }
756}
757
758static void
759nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
760{
761 intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
762
763 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
764 nv50_display_vblank_crtc_handler(dev, 0);
765
766 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
767 nv50_display_vblank_crtc_handler(dev, 1);
768
769 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
770 NV50_PDISPLAY_INTR_EN) & ~intr);
771 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
772}
773
774static void
775nv50_display_unk10_handler(struct drm_device *dev)
776{
777 struct dcb_entry *dcbent;
778 int head, ret;
779
780 ret = nv50_display_irq_head(dev, &head, &dcbent);
781 if (ret)
782 goto ack;
783
784 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
785
786 nouveau_bios_run_display_table(dev, dcbent, 0, -1);
787
788ack:
789 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
790 nv_wr32(dev, 0x610030, 0x80000000);
791}
792
afa3b4c3
BS		 793static void
794nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
795{
796 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
797 struct drm_encoder *encoder;
798 uint32_t tmp, unk0 = 0, unk1 = 0;
799
800 if (dcb->type != OUTPUT_DP)
801 return;
802
803 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
804 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
805
806 if (nv_encoder->dcb == dcb) {
807 unk0 = nv_encoder->dp.unk0;
808 unk1 = nv_encoder->dp.unk1;
809 break;
810 }
811 }
812
813 if (unk0 || unk1) {
814 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
815 tmp &= 0xfffffe03;
816 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
817
818 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
819 tmp &= 0xfef080c0;
820 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
821 }
822}
823
7149eee8
BS		 824/* If programming a TMDS output on a SOR that can also be configured for
825 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
826 *
827 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
828 * the VBIOS scripts on at least one board I have only switch it off on
829 * link 0, causing a blank display if the output has previously been
830 * programmed for DisplayPort.
831 */
832static void
833nv50_display_unk20_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
834{
835 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
836 struct drm_encoder *encoder;
837 u32 tmp;
838
839 if (dcb->type != OUTPUT_TMDS)
840 return;
841
842 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
843 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
844
845 if (nv_encoder->dcb->type == OUTPUT_DP) {
846 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
847 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
848 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
849 break;
850 }
851 }
852}
853
6ee73861
BS		 854static void
855nv50_display_unk20_handler(struct drm_device *dev)
856{
857 struct dcb_entry *dcbent;
858 uint32_t tmp, pclk, script;
859 int head, or, ret;
860
861 ret = nv50_display_irq_head(dev, &head, &dcbent);
862 if (ret)
863 goto ack;
864 or = ffs(dcbent->or) - 1;
865 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
866 script = nv50_display_script_select(dev, dcbent, pclk);
867
ef2bb506 868 NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
6ee73861
BS		 869
870 if (dcbent->type != OUTPUT_DP)
871 nouveau_bios_run_display_table(dev, dcbent, 0, -2);
872
873 nv50_crtc_set_clock(dev, head, pclk);
874
875 nouveau_bios_run_display_table(dev, dcbent, script, pclk);
876
afa3b4c3 877 nv50_display_unk20_dp_hack(dev, dcbent);
7149eee8 878 nv50_display_unk20_dp_set_tmds(dev, dcbent);
afa3b4c3 879
6ee73861
BS		 880 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head));
881 tmp &= ~0x000000f;
882 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head), tmp);
883
884 if (dcbent->type != OUTPUT_ANALOG) {
885 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
886 tmp &= ~0x00000f0f;
887 if (script & 0x0100)
888 tmp |= 0x00000101;
889 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
890 } else {
891 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
892 }
893
894ack:
895 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
896 nv_wr32(dev, 0x610030, 0x80000000);
897}
898
899static void
900nv50_display_unk40_handler(struct drm_device *dev)
901{
902 struct dcb_entry *dcbent;
903 int head, pclk, script, ret;
904
905 ret = nv50_display_irq_head(dev, &head, &dcbent);
906 if (ret)
907 goto ack;
908 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
909 script = nv50_display_script_select(dev, dcbent, pclk);
910
911 nouveau_bios_run_display_table(dev, dcbent, script, -pclk);
912
913ack:
914 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
915 nv_wr32(dev, 0x610030, 0x80000000);
916 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
917}
918
919void
920nv50_display_irq_handler_bh(struct work_struct *work)
921{
922 struct drm_nouveau_private *dev_priv =
923 container_of(work, struct drm_nouveau_private, irq_work);
924 struct drm_device *dev = dev_priv->dev;
925
926 for (;;) {
927 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
928 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
929
ef2bb506 930 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
6ee73861
BS		 931
932 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
933 nv50_display_unk10_handler(dev);
934 else
935 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
936 nv50_display_unk20_handler(dev);
937 else
938 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
939 nv50_display_unk40_handler(dev);
940 else
941 break;
942 }
943
944 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
945}
946
947static void
948nv50_display_error_handler(struct drm_device *dev)
949{
950 uint32_t addr, data;
951
952 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
953 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
954 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
955
956 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
957 0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
958
959 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
960}
961
a5acac66
BS		 962void
963nv50_display_irq_hotplug_bh(struct work_struct *work)
6ee73861 964{
a5acac66
BS		 965 struct drm_nouveau_private *dev_priv =
966 container_of(work, struct drm_nouveau_private, hpd_work);
967 struct drm_device *dev = dev_priv->dev;
6ee73861
BS		 968 struct drm_connector *connector;
969 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
970 uint32_t unplug_mask, plug_mask, change_mask;
971 uint32_t hpd0, hpd1 = 0;
972
973 hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
974 if (dev_priv->chipset >= 0x90)
975 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
976
977 plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16);
978 unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
979 change_mask = plug_mask | unplug_mask;
980
981 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
982 struct drm_encoder_helper_funcs *helper;
983 struct nouveau_connector *nv_connector =
984 nouveau_connector(connector);
985 struct nouveau_encoder *nv_encoder;
986 struct dcb_gpio_entry *gpio;
987 uint32_t reg;
988 bool plugged;
989
990 if (!nv_connector->dcb)
991 continue;
992
993 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
994 if (!gpio || !(change_mask & (1 << gpio->line)))
995 continue;
996
997 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
998 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
999 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1000 drm_get_connector_name(connector)) ;
1001
1002 if (!connector->encoder || !connector->encoder->crtc ||
1003 !connector->encoder->crtc->enabled)
1004 continue;
1005 nv_encoder = nouveau_encoder(connector->encoder);
1006 helper = connector->encoder->helper_private;
1007
1008 if (nv_encoder->dcb->type != OUTPUT_DP)
1009 continue;
1010
1011 if (plugged)
1012 helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1013 else
1014 helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1015 }
1016
1017 nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1018 if (dev_priv->chipset >= 0x90)
1019 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
4abe3520 1020
eb1f8e4f 1021 drm_helper_hpd_irq_event(dev);
6ee73861
BS		 1022}
1023
1024void
1025nv50_display_irq_handler(struct drm_device *dev)
1026{
1027 struct drm_nouveau_private *dev_priv = dev->dev_private;
1028 uint32_t delayed = 0;
1029
a5acac66
BS		 1030 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1031 if (!work_pending(&dev_priv->hpd_work))
1032 queue_work(dev_priv->wq, &dev_priv->hpd_work);
1033 }
6ee73861
BS		 1034
1035 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1036 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1037 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1038 uint32_t clock;
1039
ef2bb506 1040 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
6ee73861
BS		 1041
1042 if (!intr0 && !(intr1 & ~delayed))
1043 break;
1044
1045 if (intr0 & 0x00010000) {
1046 nv50_display_error_handler(dev);
1047 intr0 &= ~0x00010000;
1048 }
1049
1050 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1051 nv50_display_vblank_handler(dev, intr1);
1052 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1053 }
1054
1055 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1056 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1057 NV50_PDISPLAY_INTR_1_CLK_UNK40));
1058 if (clock) {
1059 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1060 if (!work_pending(&dev_priv->irq_work))
1061 queue_work(dev_priv->wq, &dev_priv->irq_work);
1062 delayed |= clock;
1063 intr1 &= ~clock;
1064 }
1065
1066 if (intr0) {
1067 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1068 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1069 }
1070
1071 if (intr1) {
1072 NV_ERROR(dev,
1073 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1074 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1075 }
1076 }
1077}
1078
Clone of davem's net-next-2.6 tree