[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv04_tv.c

/*
 * Copyright (C) 2009 Francisco Jerez.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
#include "nouveau_crtc.h"
#include "nouveau_hw.h"
#include "drm_crtc_helper.h"

#include "i2c/ch7006.h"

static struct i2c_board_info nv04_tv_encoder_info[] = {
	{
		I2C_BOARD_INFO("ch7006", 0x75),
		.platform_data = &(struct ch7006_encoder_params) {
			CH7006_FORMAT_RGB24m12I, CH7006_CLOCK_MASTER,
			0, 0, 0,
			CH7006_SYNC_SLAVE, CH7006_SYNC_SEPARATED,
			CH7006_POUT_3_3V, CH7006_ACTIVE_HSYNC
		}
	},
	{ }
};

int nv04_tv_identify(struct drm_device *dev, int i2c_index)
{
	return nouveau_i2c_identify(dev, "TV encoder",
				    nv04_tv_encoder_info, i2c_index);
}


#define PLLSEL_TV_CRTC1_MASK				\
	(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1		\
	 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1)
#define PLLSEL_TV_CRTC2_MASK				\
	(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2		\
	 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)

static void nv04_tv_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv04_mode_state *state = &dev_priv->mode_reg;
	uint8_t crtc1A;

	NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
		mode, nv_encoder->dcb->index);

	state->pllsel &= ~(PLLSEL_TV_CRTC1_MASK | PLLSEL_TV_CRTC2_MASK);

	if (mode == DRM_MODE_DPMS_ON) {
		int head = nouveau_crtc(encoder->crtc)->index;
		crtc1A = NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX);

		state->pllsel |= head ? PLLSEL_TV_CRTC2_MASK :
					PLLSEL_TV_CRTC1_MASK;

		/* Inhibit hsync */
		crtc1A |= 0x80;

		NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
	}

	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);

	to_encoder_slave(encoder)->slave_funcs->dpms(encoder, mode);
}

static void nv04_tv_bind(struct drm_device *dev, int head, bool bind)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv04_crtc_reg *state = &dev_priv->mode_reg.crtc_reg[head];

	state->tv_setup = 0;

	if (bind) {
		state->CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
		state->CRTC[NV_CIO_CRE_49] |= 0x10;
	} else {
		state->CRTC[NV_CIO_CRE_49] &= ~0x10;
	}

	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX,
		       state->CRTC[NV_CIO_CRE_LCD__INDEX]);
	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_49,
		       state->CRTC[NV_CIO_CRE_49]);
	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP,
		      state->tv_setup);
}

static void nv04_tv_prepare(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	int head = nouveau_crtc(encoder->crtc)->index;
	struct drm_encoder_helper_funcs *helper = encoder->helper_private;

	helper->dpms(encoder, DRM_MODE_DPMS_OFF);

	nv04_dfp_disable(dev, head);

	if (nv_two_heads(dev))
		nv04_tv_bind(dev, head ^ 1, false);

	nv04_tv_bind(dev, head, true);
}

static void nv04_tv_mode_set(struct drm_encoder *encoder,
			     struct drm_display_mode *mode,
			     struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];

	regp->tv_htotal = adjusted_mode->htotal;
	regp->tv_vtotal = adjusted_mode->vtotal;

	/* These delay the TV signals with respect to the VGA port,
	 * they might be useful if we ever allow a CRTC to drive
	 * multiple outputs.
	 */
	regp->tv_hskew = 1;
	regp->tv_hsync_delay = 1;
	regp->tv_hsync_delay2 = 64;
	regp->tv_vskew = 1;
	regp->tv_vsync_delay = 1;

	to_encoder_slave(encoder)->slave_funcs->mode_set(encoder, mode, adjusted_mode);
}

static void nv04_tv_commit(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct drm_encoder_helper_funcs *helper = encoder->helper_private;

	helper->dpms(encoder, DRM_MODE_DPMS_ON);

	NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
		      drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), nv_crtc->index,
		      '@' + ffs(nv_encoder->dcb->or));
}

static void nv04_tv_destroy(struct drm_encoder *encoder)
{
	to_encoder_slave(encoder)->slave_funcs->destroy(encoder);

	drm_encoder_cleanup(encoder);

	kfree(encoder->helper_private);
	kfree(nouveau_encoder(encoder));
}

static const struct drm_encoder_funcs nv04_tv_funcs = {
	.destroy = nv04_tv_destroy,
};

int
nv04_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
{
	struct nouveau_encoder *nv_encoder;
	struct drm_encoder *encoder;
	struct drm_device *dev = connector->dev;
	struct drm_encoder_helper_funcs *hfuncs;
	struct drm_encoder_slave_funcs *sfuncs;
	struct nouveau_i2c_chan *i2c =
		nouveau_i2c_find(dev, entry->i2c_index);
	int type, ret;

	/* Ensure that we can talk to this encoder */
	type = nv04_tv_identify(dev, entry->i2c_index);
	if (type < 0)
		return type;

	/* Allocate the necessary memory */
	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
	if (!nv_encoder)
		return -ENOMEM;

	hfuncs = kzalloc(sizeof(*hfuncs), GFP_KERNEL);
	if (!hfuncs) {
		ret = -ENOMEM;
		goto fail_free;
	}

	/* Initialize the common members */
	encoder = to_drm_encoder(nv_encoder);

	drm_encoder_init(dev, encoder, &nv04_tv_funcs, DRM_MODE_ENCODER_TVDAC);
	drm_encoder_helper_add(encoder, hfuncs);

	encoder->possible_crtcs = entry->heads;
	encoder->possible_clones = 0;
	nv_encoder->dcb = entry;
	nv_encoder->or = ffs(entry->or) - 1;

	/* Run the slave-specific initialization */
	ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
				   &i2c->adapter, &nv04_tv_encoder_info[type]);
	if (ret < 0)
		goto fail_cleanup;

	/* Fill the function pointers */
	sfuncs = to_encoder_slave(encoder)->slave_funcs;

	*hfuncs = (struct drm_encoder_helper_funcs) {
		.dpms = nv04_tv_dpms,
		.save = sfuncs->save,
		.restore = sfuncs->restore,
		.mode_fixup = sfuncs->mode_fixup,
		.prepare = nv04_tv_prepare,
		.commit = nv04_tv_commit,
		.mode_set = nv04_tv_mode_set,
		.detect = sfuncs->detect,
	};

	/* Attach it to the specified connector. */
	sfuncs->set_config(encoder, nv04_tv_encoder_info[type].platform_data);
	sfuncs->create_resources(encoder, connector);
	drm_mode_connector_attach_encoder(connector, encoder);

	return 0;

fail_cleanup:
	drm_encoder_cleanup(encoder);
	kfree(hfuncs);
fail_free:
	kfree(nv_encoder);
	return ret;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2009 Francisco Jerez.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
	27	#include "drmP.h"
	28	#include "nouveau_drv.h"
	29	#include "nouveau_encoder.h"
	30	#include "nouveau_connector.h"
	31	#include "nouveau_crtc.h"
	32	#include "nouveau_hw.h"
	33	#include "drm_crtc_helper.h"
	34
	35	#include "i2c/ch7006.h"
	36
6d416d80	37	static struct i2c_board_info nv04_tv_encoder_info[] = {
6ee73861	38	{
6d416d80 FJ	39	I2C_BOARD_INFO("ch7006", 0x75),
6d416d80 FJ	40	.platform_data = &(struct ch7006_encoder_params) {
6ee73861 BS	41	CH7006_FORMAT_RGB24m12I, CH7006_CLOCK_MASTER,
	42	0, 0, 0,
	43	CH7006_SYNC_SLAVE, CH7006_SYNC_SEPARATED,
	44	CH7006_POUT_3_3V, CH7006_ACTIVE_HSYNC
6d416d80	45	}
6ee73861	46	},
6d416d80	47	{ }
6ee73861 BS	48	};
6ee73861 BS	49
6ee73861 BS	50	int nv04_tv_identify(struct drm_device *dev, int i2c_index)
6ee73861 BS	51	{
6d416d80 FJ	52	return nouveau_i2c_identify(dev, "TV encoder",
6d416d80 FJ	53	nv04_tv_encoder_info, i2c_index);
6ee73861 BS	54	}
6ee73861 BS	55
6d416d80	56
6ee73861 BS	57	#define PLLSEL_TV_CRTC1_MASK \
	58	(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
	59	\| NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1)
	60	#define PLLSEL_TV_CRTC2_MASK \
	61	(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
	62	\| NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
	63
	64	static void nv04_tv_dpms(struct drm_encoder *encoder, int mode)
	65	{
	66	struct drm_device *dev = encoder->dev;
	67	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	68	struct drm_nouveau_private *dev_priv = dev->dev_private;
	69	struct nv04_mode_state *state = &dev_priv->mode_reg;
	70	uint8_t crtc1A;
	71
	72	NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
	73	mode, nv_encoder->dcb->index);
	74
	75	state->pllsel &= ~(PLLSEL_TV_CRTC1_MASK \| PLLSEL_TV_CRTC2_MASK);
	76
	77	if (mode == DRM_MODE_DPMS_ON) {
	78	int head = nouveau_crtc(encoder->crtc)->index;
	79	crtc1A = NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX);
	80
	81	state->pllsel \|= head ? PLLSEL_TV_CRTC2_MASK :
	82	PLLSEL_TV_CRTC1_MASK;
	83
	84	/* Inhibit hsync */
	85	crtc1A \|= 0x80;
	86
	87	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
	88	}
	89
	90	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
	91
	92	to_encoder_slave(encoder)->slave_funcs->dpms(encoder, mode);
	93	}
	94
	95	static void nv04_tv_bind(struct drm_device *dev, int head, bool bind)
	96	{
	97	struct drm_nouveau_private *dev_priv = dev->dev_private;
	98	struct nv04_crtc_reg *state = &dev_priv->mode_reg.crtc_reg[head];
	99
	100	state->tv_setup = 0;
	101
	102	if (bind) {
	103	state->CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
	104	state->CRTC[NV_CIO_CRE_49] \|= 0x10;
	105	} else {
	106	state->CRTC[NV_CIO_CRE_49] &= ~0x10;
	107	}
	108
	109	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX,
	110	state->CRTC[NV_CIO_CRE_LCD__INDEX]);
	111	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_49,
	112	state->CRTC[NV_CIO_CRE_49]);
	113	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP,
	114	state->tv_setup);
	115	}
	116
	117	static void nv04_tv_prepare(struct drm_encoder *encoder)
	118	{
	119	struct drm_device *dev = encoder->dev;
	120	int head = nouveau_crtc(encoder->crtc)->index;
121	struct drm_encoder_helper_funcs *helper = encoder->helper_private;
122
123	helper->dpms(encoder, DRM_MODE_DPMS_OFF);
124
125	nv04_dfp_disable(dev, head);
126
127	if (nv_two_heads(dev))
128	nv04_tv_bind(dev, head ^ 1, false);
129
130	nv04_tv_bind(dev, head, true);
131	}
132
133	static void nv04_tv_mode_set(struct drm_encoder *encoder,
134	struct drm_display_mode *mode,
135	struct drm_display_mode *adjusted_mode)
136	{
137	struct drm_device *dev = encoder->dev;
138	struct drm_nouveau_private *dev_priv = dev->dev_private;
139	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
140	struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
141
142	regp->tv_htotal = adjusted_mode->htotal;
143	regp->tv_vtotal = adjusted_mode->vtotal;
144
145	/* These delay the TV signals with respect to the VGA port,
146	* they might be useful if we ever allow a CRTC to drive
147	* multiple outputs.
148	*/
149	regp->tv_hskew = 1;
150	regp->tv_hsync_delay = 1;
151	regp->tv_hsync_delay2 = 64;
152	regp->tv_vskew = 1;
153	regp->tv_vsync_delay = 1;
154
155	to_encoder_slave(encoder)->slave_funcs->mode_set(encoder, mode, adjusted_mode);
156	}
157
158	static void nv04_tv_commit(struct drm_encoder *encoder)
159	{
160	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
161	struct drm_device *dev = encoder->dev;
162	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
163	struct drm_encoder_helper_funcs *helper = encoder->helper_private;
164
165	helper->dpms(encoder, DRM_MODE_DPMS_ON);
166
167	NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
168	drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), nv_crtc->index,
169	'@' + ffs(nv_encoder->dcb->or));
170	}
171
172	static void nv04_tv_destroy(struct drm_encoder *encoder)
173	{
6ee73861 BS	174	to_encoder_slave(encoder)->slave_funcs->destroy(encoder);
	175
	176	drm_encoder_cleanup(encoder);
	177
6d416d80 FJ	178	kfree(encoder->helper_private);
6d416d80 FJ	179	kfree(nouveau_encoder(encoder));
6ee73861 BS	180	}
6ee73861 BS	181
6d416d80 FJ	182	static const struct drm_encoder_funcs nv04_tv_funcs = {
	183	.destroy = nv04_tv_destroy,
	184	};
	185
8f1a6086 BS	186	int
8f1a6086 BS	187	nv04_tv_create(struct drm_connector connector, struct dcb_entry entry)
6ee73861 BS	188	{
	189	struct nouveau_encoder *nv_encoder;
	190	struct drm_encoder *encoder;
8f1a6086	191	struct drm_device *dev = connector->dev;
6d416d80 FJ	192	struct drm_encoder_helper_funcs *hfuncs;
	193	struct drm_encoder_slave_funcs *sfuncs;
	194	struct nouveau_i2c_chan *i2c =
	195	nouveau_i2c_find(dev, entry->i2c_index);
6ee73861	196	int type, ret;
6ee73861 BS	197
6ee73861 BS	198	/* Ensure that we can talk to this encoder */
6d416d80	199	type = nv04_tv_identify(dev, entry->i2c_index);
6ee73861 BS	200	if (type < 0)
	201	return type;
	202
	203	/* Allocate the necessary memory */
	204	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
	205	if (!nv_encoder)
	206	return -ENOMEM;
	207
6d416d80 FJ	208	hfuncs = kzalloc(sizeof(*hfuncs), GFP_KERNEL);
	209	if (!hfuncs) {
	210	ret = -ENOMEM;
	211	goto fail_free;
	212	}
	213
6ee73861 BS	214	/* Initialize the common members */
	215	encoder = to_drm_encoder(nv_encoder);
	216
6d416d80	217	drm_encoder_init(dev, encoder, &nv04_tv_funcs, DRM_MODE_ENCODER_TVDAC);
6ee73861 BS	218	drm_encoder_helper_add(encoder, hfuncs);
	219
	220	encoder->possible_crtcs = entry->heads;
	221	encoder->possible_clones = 0;
6ee73861 BS	222	nv_encoder->dcb = entry;
	223	nv_encoder->or = ffs(entry->or) - 1;
	224
	225	/* Run the slave-specific initialization */
6d416d80 FJ	226	ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
6d416d80 FJ	227	&i2c->adapter, &nv04_tv_encoder_info[type]);
6ee73861	228	if (ret < 0)
6d416d80	229	goto fail_cleanup;
6ee73861 BS	230
	231	/* Fill the function pointers */
	232	sfuncs = to_encoder_slave(encoder)->slave_funcs;
	233
6ee73861 BS	234	*hfuncs = (struct drm_encoder_helper_funcs) {
	235	.dpms = nv04_tv_dpms,
	236	.save = sfuncs->save,
	237	.restore = sfuncs->restore,
	238	.mode_fixup = sfuncs->mode_fixup,
	239	.prepare = nv04_tv_prepare,
	240	.commit = nv04_tv_commit,
	241	.mode_set = nv04_tv_mode_set,
	242	.detect = sfuncs->detect,
	243	};
	244
6d416d80 FJ	245	/* Attach it to the specified connector. */
6d416d80 FJ	246	sfuncs->set_config(encoder, nv04_tv_encoder_info[type].platform_data);
8f1a6086	247	sfuncs->create_resources(encoder, connector);
8f1a6086	248	drm_mode_connector_attach_encoder(connector, encoder);
6d416d80	249
6ee73861 BS	250	return 0;
6ee73861 BS	251
6d416d80	252	fail_cleanup:
6ee73861	253	drm_encoder_cleanup(encoder);
6d416d80 FJ	254	kfree(hfuncs);
6d416d80 FJ	255	fail_free:
6ee73861 BS	256	kfree(nv_encoder);
	257	return ret;
	258	}