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drm/nouveau: add instmem flush() hook
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
103static inline struct nouveau_bo *
104nouveau_bo(struct ttm_buffer_object *bo)
105{
106 return container_of(bo, struct nouveau_bo, bo);
107}
108
109static inline struct nouveau_bo *
110nouveau_gem_object(struct drm_gem_object *gem)
111{
112 return gem ? gem->driver_private : NULL;
113}
114
115/* TODO: submit equivalent to TTM generic API upstream? */
116static inline void __iomem *
117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118{
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124}
125
6ee73861
BS		 126enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129};
130
131#define NVOBJ_ENGINE_SW 0
132#define NVOBJ_ENGINE_GR 1
133#define NVOBJ_ENGINE_DISPLAY 2
134#define NVOBJ_ENGINE_INT 0xdeadbeef
135
136#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
137#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
138#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
139#define NVOBJ_FLAG_FAKE (1 << 3)
140struct nouveau_gpuobj {
141 struct list_head list;
142
143 struct nouveau_channel *im_channel;
b833ac26 144 struct drm_mm_node *im_pramin;
6ee73861
BS		 145 struct nouveau_bo *im_backing;
146 uint32_t im_backing_start;
147 uint32_t *im_backing_suspend;
148 int im_bound;
149
150 uint32_t flags;
151 int refcount;
152
153 uint32_t engine;
154 uint32_t class;
155
156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
157 void *priv;
158};
159
160struct nouveau_gpuobj_ref {
161 struct list_head list;
162
163 struct nouveau_gpuobj *gpuobj;
164 uint32_t instance;
165
166 struct nouveau_channel *channel;
167 int handle;
168};
169
170struct nouveau_channel {
171 struct drm_device *dev;
172 int id;
173
174 /* owner of this fifo */
175 struct drm_file *file_priv;
176 /* mapping of the fifo itself */
177 struct drm_local_map *map;
178
179 /* mapping of the regs controling the fifo */
180 void __iomem *user;
181 uint32_t user_get;
182 uint32_t user_put;
183
184 /* Fencing */
185 struct {
186 /* lock protects the pending list only */
187 spinlock_t lock;
188 struct list_head pending;
189 uint32_t sequence;
190 uint32_t sequence_ack;
191 uint32_t last_sequence_irq;
192 } fence;
193
194 /* DMA push buffer */
195 struct nouveau_gpuobj_ref *pushbuf;
196 struct nouveau_bo *pushbuf_bo;
197 uint32_t pushbuf_base;
198
199 /* Notifier memory */
200 struct nouveau_bo *notifier_bo;
b833ac26 201 struct drm_mm notifier_heap;
6ee73861
BS		 202
203 /* PFIFO context */
204 struct nouveau_gpuobj_ref *ramfc;
205 struct nouveau_gpuobj_ref *cache;
206
207 /* PGRAPH context */
208 /* XXX may be merge 2 pointers as private data ??? */
209 struct nouveau_gpuobj_ref *ramin_grctx;
210 void *pgraph_ctx;
211
212 /* NV50 VM */
213 struct nouveau_gpuobj *vm_pd;
214 struct nouveau_gpuobj_ref *vm_gart_pt;
215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
216
217 /* Objects */
218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
b833ac26 219 struct drm_mm ramin_heap; /* Private PRAMIN heap */
6ee73861
BS		 220 struct nouveau_gpuobj_ref *ramht; /* Hash table */
221 struct list_head ramht_refs; /* Objects referenced by RAMHT */
222
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
224 uint32_t m2mf_ntfy;
225 uint32_t vram_handle;
226 uint32_t gart_handle;
227 bool accel_done;
228
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
230 struct {
231 int max;
232 int free;
233 int cur;
234 int put;
235 /* access via pushbuf_bo */
9a391ad8
BS		 236
237 int ib_base;
238 int ib_max;
239 int ib_free;
240 int ib_put;
6ee73861
BS		 241 } dma;
242
243 uint32_t sw_subchannel[8];
244
245 struct {
246 struct nouveau_gpuobj *vblsem;
247 uint32_t vblsem_offset;
248 uint32_t vblsem_rval;
249 struct list_head vbl_wait;
250 } nvsw;
251
252 struct {
253 bool active;
254 char name[32];
255 struct drm_info_list info;
256 } debugfs;
257};
258
259struct nouveau_instmem_engine {
260 void *priv;
261
262 int (*init)(struct drm_device *dev);
263 void (*takedown)(struct drm_device *dev);
264 int (*suspend)(struct drm_device *dev);
265 void (*resume)(struct drm_device *dev);
266
267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
268 uint32_t *size);
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 272 void (*flush)(struct drm_device *);
6ee73861
BS		 273};
274
275struct nouveau_mc_engine {
276 int (*init)(struct drm_device *dev);
277 void (*takedown)(struct drm_device *dev);
278};
279
280struct nouveau_timer_engine {
281 int (*init)(struct drm_device *dev);
282 void (*takedown)(struct drm_device *dev);
283 uint64_t (*read)(struct drm_device *dev);
284};
285
286struct nouveau_fb_engine {
cb00f7c1
FJ		 287 int num_tiles;
288
6ee73861
BS		 289 int (*init)(struct drm_device *dev);
290 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 291
292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
293 uint32_t size, uint32_t pitch);
6ee73861
BS		 294};
295
296struct nouveau_fifo_engine {
297 void *priv;
298
299 int channels;
300
301 int (*init)(struct drm_device *);
302 void (*takedown)(struct drm_device *);
303
304 void (*disable)(struct drm_device *);
305 void (*enable)(struct drm_device *);
306 bool (*reassign)(struct drm_device *, bool enable);
588d7d12
FJ		 307 bool (*cache_flush)(struct drm_device *dev);
308 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 309
310 int (*channel_id)(struct drm_device *);
311
312 int (*create_context)(struct nouveau_channel *);
313 void (*destroy_context)(struct nouveau_channel *);
314 int (*load_context)(struct nouveau_channel *);
315 int (*unload_context)(struct drm_device *);
316};
317
318struct nouveau_pgraph_object_method {
319 int id;
320 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
321 uint32_t data);
322};
323
324struct nouveau_pgraph_object_class {
325 int id;
326 bool software;
327 struct nouveau_pgraph_object_method *methods;
328};
329
330struct nouveau_pgraph_engine {
331 struct nouveau_pgraph_object_class *grclass;
332 bool accel_blocked;
333 void *ctxprog;
334 void *ctxvals;
054b93e4 335 int grctx_size;
6ee73861
BS		 336
337 int (*init)(struct drm_device *);
338 void (*takedown)(struct drm_device *);
339
340 void (*fifo_access)(struct drm_device *, bool);
341
342 struct nouveau_channel *(*channel)(struct drm_device *);
343 int (*create_context)(struct nouveau_channel *);
344 void (*destroy_context)(struct nouveau_channel *);
345 int (*load_context)(struct nouveau_channel *);
346 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 347
348 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
349 uint32_t size, uint32_t pitch);
6ee73861
BS		 350};
351
352struct nouveau_engine {
353 struct nouveau_instmem_engine instmem;
354 struct nouveau_mc_engine mc;
355 struct nouveau_timer_engine timer;
356 struct nouveau_fb_engine fb;
357 struct nouveau_pgraph_engine graph;
358 struct nouveau_fifo_engine fifo;
359};
360
361struct nouveau_pll_vals {
362 union {
363 struct {
364#ifdef __BIG_ENDIAN
365 uint8_t N1, M1, N2, M2;
366#else
367 uint8_t M1, N1, M2, N2;
368#endif
369 };
370 struct {
371 uint16_t NM1, NM2;
372 } __attribute__((packed));
373 };
374 int log2P;
375
376 int refclk;
377};
378
379enum nv04_fp_display_regs {
380 FP_DISPLAY_END,
381 FP_TOTAL,
382 FP_CRTC,
383 FP_SYNC_START,
384 FP_SYNC_END,
385 FP_VALID_START,
386 FP_VALID_END
387};
388
389struct nv04_crtc_reg {
390 unsigned char MiscOutReg; /* */
391 uint8_t CRTC[0x9f];
392 uint8_t CR58[0x10];
393 uint8_t Sequencer[5];
394 uint8_t Graphics[9];
395 uint8_t Attribute[21];
396 unsigned char DAC[768]; /* Internal Colorlookuptable */
397
398 /* PCRTC regs */
399 uint32_t fb_start;
400 uint32_t crtc_cfg;
401 uint32_t cursor_cfg;
402 uint32_t gpio_ext;
403 uint32_t crtc_830;
404 uint32_t crtc_834;
405 uint32_t crtc_850;
406 uint32_t crtc_eng_ctrl;
407
408 /* PRAMDAC regs */
409 uint32_t nv10_cursync;
410 struct nouveau_pll_vals pllvals;
411 uint32_t ramdac_gen_ctrl;
412 uint32_t ramdac_630;
413 uint32_t ramdac_634;
414 uint32_t tv_setup;
415 uint32_t tv_vtotal;
416 uint32_t tv_vskew;
417 uint32_t tv_vsync_delay;
418 uint32_t tv_htotal;
419 uint32_t tv_hskew;
420 uint32_t tv_hsync_delay;
421 uint32_t tv_hsync_delay2;
422 uint32_t fp_horiz_regs[7];
423 uint32_t fp_vert_regs[7];
424 uint32_t dither;
425 uint32_t fp_control;
426 uint32_t dither_regs[6];
427 uint32_t fp_debug_0;
428 uint32_t fp_debug_1;
429 uint32_t fp_debug_2;
430 uint32_t fp_margin_color;
431 uint32_t ramdac_8c0;
432 uint32_t ramdac_a20;
433 uint32_t ramdac_a24;
434 uint32_t ramdac_a34;
435 uint32_t ctv_regs[38];
436};
437
438struct nv04_output_reg {
439 uint32_t output;
440 int head;
441};
442
443struct nv04_mode_state {
444 uint32_t bpp;
445 uint32_t width;
446 uint32_t height;
447 uint32_t interlace;
448 uint32_t repaint0;
449 uint32_t repaint1;
450 uint32_t screen;
451 uint32_t scale;
452 uint32_t dither;
453 uint32_t extra;
454 uint32_t fifo;
455 uint32_t pixel;
456 uint32_t horiz;
457 int arbitration0;
458 int arbitration1;
459 uint32_t pll;
460 uint32_t pllB;
461 uint32_t vpll;
462 uint32_t vpll2;
463 uint32_t vpllB;
464 uint32_t vpll2B;
465 uint32_t pllsel;
466 uint32_t sel_clk;
467 uint32_t general;
468 uint32_t crtcOwner;
469 uint32_t head;
470 uint32_t head2;
471 uint32_t cursorConfig;
472 uint32_t cursor0;
473 uint32_t cursor1;
474 uint32_t cursor2;
475 uint32_t timingH;
476 uint32_t timingV;
477 uint32_t displayV;
478 uint32_t crtcSync;
479
480 struct nv04_crtc_reg crtc_reg[2];
481};
482
483enum nouveau_card_type {
484 NV_04 = 0x00,
485 NV_10 = 0x10,
486 NV_20 = 0x20,
487 NV_30 = 0x30,
488 NV_40 = 0x40,
489 NV_50 = 0x50,
490};
491
492struct drm_nouveau_private {
493 struct drm_device *dev;
6ee73861
BS		 494
495 /* the card type, takes NV_* as values */
496 enum nouveau_card_type card_type;
497 /* exact chipset, derived from NV_PMC_BOOT_0 */
498 int chipset;
499 int flags;
500
501 void __iomem *mmio;
502 void __iomem *ramin;
503 uint32_t ramin_size;
504
ac8fb975
BS		 505 struct nouveau_bo *vga_ram;
506
6ee73861
BS		 507 struct workqueue_struct *wq;
508 struct work_struct irq_work;
a5acac66 509 struct work_struct hpd_work;
6ee73861
BS		 510
511 struct list_head vbl_waiting;
512
513 struct {
514 struct ttm_global_reference mem_global_ref;
515 struct ttm_bo_global_ref bo_global_ref;
516 struct ttm_bo_device bdev;
517 spinlock_t bo_list_lock;
518 struct list_head bo_list;
519 atomic_t validate_sequence;
520 } ttm;
521
522 struct fb_info *fbdev_info;
523
524 int fifo_alloc_count;
525 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
526
527 struct nouveau_engine engine;
528 struct nouveau_channel *channel;
529
ff9e5279
MM		 530 /* For PFIFO and PGRAPH. */
531 spinlock_t context_switch_lock;
532
6ee73861
BS		 533 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
534 struct nouveau_gpuobj *ramht;
535 uint32_t ramin_rsvd_vram;
536 uint32_t ramht_offset;
537 uint32_t ramht_size;
538 uint32_t ramht_bits;
539 uint32_t ramfc_offset;
540 uint32_t ramfc_size;
541 uint32_t ramro_offset;
542 uint32_t ramro_size;
543
6ee73861
BS		 544 struct {
545 enum {
546 NOUVEAU_GART_NONE = 0,
547 NOUVEAU_GART_AGP,
548 NOUVEAU_GART_SGDMA
549 } type;
550 uint64_t aper_base;
551 uint64_t aper_size;
552 uint64_t aper_free;
553
554 struct nouveau_gpuobj *sg_ctxdma;
555 struct page *sg_dummy_page;
556 dma_addr_t sg_dummy_bus;
6ee73861
BS		 557 } gart_info;
558
a0af9add
FJ		 559 /* nv10-nv40 tiling regions */
560 struct {
561 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
562 spinlock_t lock;
563 } tile;
564
a76fb4e8
BS		 565 /* VRAM/fb configuration */
566 uint64_t vram_size;
567 uint64_t vram_sys_base;
568
569 uint64_t fb_phys;
570 uint64_t fb_available_size;
571 uint64_t fb_mappable_pages;
572 uint64_t fb_aper_free;
573 int fb_mtrr;
574
6ee73861
BS		 575 /* G8x/G9x virtual address space */
576 uint64_t vm_gart_base;
577 uint64_t vm_gart_size;
578 uint64_t vm_vram_base;
579 uint64_t vm_vram_size;
580 uint64_t vm_end;
581 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
582 int vm_vram_pt_nr;
6ee73861 583
b833ac26 584 struct drm_mm ramin_heap;
6ee73861
BS		 585
586 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
587 uint32_t ctx_table_size;
588 struct nouveau_gpuobj_ref *ctx_table;
589
590 struct list_head gpuobj_list;
591
04a39c57 592 struct nvbios vbios;
6ee73861
BS		 593
594 struct nv04_mode_state mode_reg;
595 struct nv04_mode_state saved_reg;
596 uint32_t saved_vga_font[4][16384];
597 uint32_t crtc_owner;
598 uint32_t dac_users[4];
599
600 struct nouveau_suspend_resume {
6ee73861 601 uint32_t *ramin_copy;
6ee73861
BS		 602 } susres;
603
604 struct backlight_device *backlight;
6ee73861
BS		 605
606 struct nouveau_channel *evo;
87c0e0e5
BS		 607 struct {
608 struct dcb_entry *dcb;
609 u16 script;
610 u32 pclk;
611 } evo_irq;
6ee73861
BS		 612
613 struct {
614 struct dentry *channel_root;
615 } debugfs;
38651674 616
8be48d92 617 struct nouveau_fbdev *nfbdev;
06415c56 618 struct apertures_struct *apertures;
6ee73861
BS		 619};
620
621static inline struct drm_nouveau_private *
622nouveau_bdev(struct ttm_bo_device *bd)
623{
624 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
625}
626
627static inline int
628nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
629{
630 struct nouveau_bo *prev;
631
632 if (!pnvbo)
633 return -EINVAL;
634 prev = *pnvbo;
635
636 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
637 if (prev) {
638 struct ttm_buffer_object *bo = &prev->bo;
639
640 ttm_bo_unref(&bo);
641 }
642
643 return 0;
644}
645
6ee73861
BS		 646#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
647 struct drm_nouveau_private *nv = dev->dev_private; \
648 if (!nouveau_channel_owner(dev, (cl), (id))) { \
649 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
650 DRM_CURRENTPID, (id)); \
651 return -EPERM; \
652 } \
653 (ch) = nv->fifos[(id)]; \
654} while (0)
655
656/* nouveau_drv.c */
657extern int nouveau_noagp;
658extern int nouveau_duallink;
659extern int nouveau_uscript_lvds;
660extern int nouveau_uscript_tmds;
661extern int nouveau_vram_pushbuf;
662extern int nouveau_vram_notify;
663extern int nouveau_fbpercrtc;
f4053509 664extern int nouveau_tv_disable;
6ee73861
BS		 665extern char *nouveau_tv_norm;
666extern int nouveau_reg_debug;
667extern char *nouveau_vbios;
054b93e4 668extern int nouveau_ctxfw;
a1470890 669extern int nouveau_ignorelid;
a32ed69d
MK		 670extern int nouveau_nofbaccel;
671extern int nouveau_noaccel;
da647d5b 672extern int nouveau_override_conntype;
6ee73861 673
6a9ee8af
DA		 674extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
675extern int nouveau_pci_resume(struct pci_dev *pdev);
676
6ee73861
BS		 677/* nouveau_state.c */
678extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
679extern int nouveau_load(struct drm_device *, unsigned long flags);
680extern int nouveau_firstopen(struct drm_device *);
681extern void nouveau_lastclose(struct drm_device *);
682extern int nouveau_unload(struct drm_device *);
683extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
684 struct drm_file *);
685extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
686 struct drm_file *);
687extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
688 uint32_t reg, uint32_t mask, uint32_t val);
689extern bool nouveau_wait_for_idle(struct drm_device *);
690extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 691
692/* nouveau_mem.c */
a76fb4e8 693extern int nouveau_mem_detect(struct drm_device *dev);
6ee73861
BS		 694extern int nouveau_mem_init(struct drm_device *);
695extern int nouveau_mem_init_agp(struct drm_device *);
696extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 697extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
698 uint32_t addr,
699 uint32_t size,
700 uint32_t pitch);
701extern void nv10_mem_expire_tiling(struct drm_device *dev,
702 struct nouveau_tile_reg *tile,
703 struct nouveau_fence *fence);
6ee73861
BS		 704extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
705 uint32_t size, uint32_t flags,
706 uint64_t phys);
707extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
708 uint32_t size);
709
710/* nouveau_notifier.c */
711extern int nouveau_notifier_init_channel(struct nouveau_channel *);
712extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
713extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
714 int cout, uint32_t *offset);
715extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
716extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
717 struct drm_file *);
718extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
719 struct drm_file *);
720
721/* nouveau_channel.c */
722extern struct drm_ioctl_desc nouveau_ioctls[];
723extern int nouveau_max_ioctl;
724extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
725extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
726 int channel);
727extern int nouveau_channel_alloc(struct drm_device *dev,
728 struct nouveau_channel **chan,
729 struct drm_file *file_priv,
730 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
731extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 732
733/* nouveau_object.c */
734extern int nouveau_gpuobj_early_init(struct drm_device *);
735extern int nouveau_gpuobj_init(struct drm_device *);
736extern void nouveau_gpuobj_takedown(struct drm_device *);
737extern void nouveau_gpuobj_late_takedown(struct drm_device *);
738extern int nouveau_gpuobj_suspend(struct drm_device *dev);
739extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
740extern void nouveau_gpuobj_resume(struct drm_device *dev);
741extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
742 uint32_t vram_h, uint32_t tt_h);
743extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
744extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
745 uint32_t size, int align, uint32_t flags,
746 struct nouveau_gpuobj **);
747extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
748extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
749 uint32_t handle, struct nouveau_gpuobj *,
750 struct nouveau_gpuobj_ref **);
751extern int nouveau_gpuobj_ref_del(struct drm_device *,
752 struct nouveau_gpuobj_ref **);
753extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
754 struct nouveau_gpuobj_ref **ref_ret);
755extern int nouveau_gpuobj_new_ref(struct drm_device *,
756 struct nouveau_channel *alloc_chan,
757 struct nouveau_channel *ref_chan,
758 uint32_t handle, uint32_t size, int align,
759 uint32_t flags, struct nouveau_gpuobj_ref **);
760extern int nouveau_gpuobj_new_fake(struct drm_device *,
761 uint32_t p_offset, uint32_t b_offset,
762 uint32_t size, uint32_t flags,
763 struct nouveau_gpuobj **,
764 struct nouveau_gpuobj_ref**);
765extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
766 uint64_t offset, uint64_t size, int access,
767 int target, struct nouveau_gpuobj **);
768extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
769 uint64_t offset, uint64_t size,
770 int access, struct nouveau_gpuobj **,
771 uint32_t *o_ret);
772extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
773 struct nouveau_gpuobj **);
f03a314b
FJ		 774extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
775 struct nouveau_gpuobj **);
6ee73861
BS		 776extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
777 struct drm_file *);
778extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
779 struct drm_file *);
780
781/* nouveau_irq.c */
782extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
783extern void nouveau_irq_preinstall(struct drm_device *);
784extern int nouveau_irq_postinstall(struct drm_device *);
785extern void nouveau_irq_uninstall(struct drm_device *);
786
787/* nouveau_sgdma.c */
788extern int nouveau_sgdma_init(struct drm_device *);
789extern void nouveau_sgdma_takedown(struct drm_device *);
790extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
791 uint32_t *page);
792extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
793
794/* nouveau_debugfs.c */
795#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
796extern int nouveau_debugfs_init(struct drm_minor *);
797extern void nouveau_debugfs_takedown(struct drm_minor *);
798extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
799extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
800#else
801static inline int
802nouveau_debugfs_init(struct drm_minor *minor)
803{
804 return 0;
805}
806
807static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
808{
809}
810
811static inline int
812nouveau_debugfs_channel_init(struct nouveau_channel *chan)
813{
814 return 0;
815}
816
817static inline void
818nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
819{
820}
821#endif
822
823/* nouveau_dma.c */
75c99da6 824extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 825extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 826extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 827
828/* nouveau_acpi.c */
afeb3e11 829#define ROM_BIOS_PAGE 4096
2f41a7f1 830#if defined(CONFIG_ACPI)
6a9ee8af
DA		 831void nouveau_register_dsm_handler(void);
832void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 833int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
834bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
8edb381d
DA		 835#else
836static inline void nouveau_register_dsm_handler(void) {}
837static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 838static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
839static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
8edb381d 840#endif
6ee73861
BS		 841
842/* nouveau_backlight.c */
843#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
844extern int nouveau_backlight_init(struct drm_device *);
845extern void nouveau_backlight_exit(struct drm_device *);
846#else
847static inline int nouveau_backlight_init(struct drm_device *dev)
848{
849 return 0;
850}
851
852static inline void nouveau_backlight_exit(struct drm_device *dev) { }
853#endif
854
855/* nouveau_bios.c */
856extern int nouveau_bios_init(struct drm_device *);
857extern void nouveau_bios_takedown(struct drm_device *dev);
858extern int nouveau_run_vbios_init(struct drm_device *);
859extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
860 struct dcb_entry *);
861extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
862 enum dcb_gpio_tag);
863extern struct dcb_connector_table_entry *
864nouveau_bios_connector_entry(struct drm_device *, int index);
865extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
866 struct pll_lims *);
867extern int nouveau_bios_run_display_table(struct drm_device *,
868 struct dcb_entry *,
869 uint32_t script, int pxclk);
870extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
871 int *length);
872extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
873extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
874extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
875 bool *dl, bool *if_is_24bit);
876extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
877 int head, int pxclk);
878extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
879 enum LVDS_script, int pxclk);
880
881/* nouveau_ttm.c */
882int nouveau_ttm_global_init(struct drm_nouveau_private *);
883void nouveau_ttm_global_release(struct drm_nouveau_private *);
884int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
885
886/* nouveau_dp.c */
887int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
888 uint8_t *data, int data_nr);
889bool nouveau_dp_detect(struct drm_encoder *);
890bool nouveau_dp_link_train(struct drm_encoder *);
891
892/* nv04_fb.c */
893extern int nv04_fb_init(struct drm_device *);
894extern void nv04_fb_takedown(struct drm_device *);
895
896/* nv10_fb.c */
897extern int nv10_fb_init(struct drm_device *);
898extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 899extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
900 uint32_t, uint32_t);
6ee73861
BS		 901
902/* nv40_fb.c */
903extern int nv40_fb_init(struct drm_device *);
904extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 905extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
906 uint32_t, uint32_t);
6ee73861 907
304424e1
MK		 908/* nv50_fb.c */
909extern int nv50_fb_init(struct drm_device *);
910extern void nv50_fb_takedown(struct drm_device *);
911
6ee73861
BS		 912/* nv04_fifo.c */
913extern int nv04_fifo_init(struct drm_device *);
914extern void nv04_fifo_disable(struct drm_device *);
915extern void nv04_fifo_enable(struct drm_device *);
916extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12
FJ		 917extern bool nv04_fifo_cache_flush(struct drm_device *);
918extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 919extern int nv04_fifo_channel_id(struct drm_device *);
920extern int nv04_fifo_create_context(struct nouveau_channel *);
921extern void nv04_fifo_destroy_context(struct nouveau_channel *);
922extern int nv04_fifo_load_context(struct nouveau_channel *);
923extern int nv04_fifo_unload_context(struct drm_device *);
924
925/* nv10_fifo.c */
926extern int nv10_fifo_init(struct drm_device *);
927extern int nv10_fifo_channel_id(struct drm_device *);
928extern int nv10_fifo_create_context(struct nouveau_channel *);
929extern void nv10_fifo_destroy_context(struct nouveau_channel *);
930extern int nv10_fifo_load_context(struct nouveau_channel *);
931extern int nv10_fifo_unload_context(struct drm_device *);
932
933/* nv40_fifo.c */
934extern int nv40_fifo_init(struct drm_device *);
935extern int nv40_fifo_create_context(struct nouveau_channel *);
936extern void nv40_fifo_destroy_context(struct nouveau_channel *);
937extern int nv40_fifo_load_context(struct nouveau_channel *);
938extern int nv40_fifo_unload_context(struct drm_device *);
939
940/* nv50_fifo.c */
941extern int nv50_fifo_init(struct drm_device *);
942extern void nv50_fifo_takedown(struct drm_device *);
943extern int nv50_fifo_channel_id(struct drm_device *);
944extern int nv50_fifo_create_context(struct nouveau_channel *);
945extern void nv50_fifo_destroy_context(struct nouveau_channel *);
946extern int nv50_fifo_load_context(struct nouveau_channel *);
947extern int nv50_fifo_unload_context(struct drm_device *);
948
949/* nv04_graph.c */
950extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
951extern int nv04_graph_init(struct drm_device *);
952extern void nv04_graph_takedown(struct drm_device *);
953extern void nv04_graph_fifo_access(struct drm_device *, bool);
954extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
955extern int nv04_graph_create_context(struct nouveau_channel *);
956extern void nv04_graph_destroy_context(struct nouveau_channel *);
957extern int nv04_graph_load_context(struct nouveau_channel *);
958extern int nv04_graph_unload_context(struct drm_device *);
959extern void nv04_graph_context_switch(struct drm_device *);
960
961/* nv10_graph.c */
962extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
963extern int nv10_graph_init(struct drm_device *);
964extern void nv10_graph_takedown(struct drm_device *);
965extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
966extern int nv10_graph_create_context(struct nouveau_channel *);
967extern void nv10_graph_destroy_context(struct nouveau_channel *);
968extern int nv10_graph_load_context(struct nouveau_channel *);
969extern int nv10_graph_unload_context(struct drm_device *);
970extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 971extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
972 uint32_t, uint32_t);
6ee73861
BS		 973
974/* nv20_graph.c */
975extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
976extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
977extern int nv20_graph_create_context(struct nouveau_channel *);
978extern void nv20_graph_destroy_context(struct nouveau_channel *);
979extern int nv20_graph_load_context(struct nouveau_channel *);
980extern int nv20_graph_unload_context(struct drm_device *);
981extern int nv20_graph_init(struct drm_device *);
982extern void nv20_graph_takedown(struct drm_device *);
983extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 984extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
985 uint32_t, uint32_t);
6ee73861
BS		 986
987/* nv40_graph.c */
988extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
989extern int nv40_graph_init(struct drm_device *);
990extern void nv40_graph_takedown(struct drm_device *);
991extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
992extern int nv40_graph_create_context(struct nouveau_channel *);
993extern void nv40_graph_destroy_context(struct nouveau_channel *);
994extern int nv40_graph_load_context(struct nouveau_channel *);
995extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 996extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 997extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
998 uint32_t, uint32_t);
6ee73861
BS		 999
1000/* nv50_graph.c */
1001extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1002extern int nv50_graph_init(struct drm_device *);
1003extern void nv50_graph_takedown(struct drm_device *);
1004extern void nv50_graph_fifo_access(struct drm_device *, bool);
1005extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1006extern int nv50_graph_create_context(struct nouveau_channel *);
1007extern void nv50_graph_destroy_context(struct nouveau_channel *);
1008extern int nv50_graph_load_context(struct nouveau_channel *);
1009extern int nv50_graph_unload_context(struct drm_device *);
1010extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1011extern int nv50_grctx_init(struct nouveau_grctx *);
6ee73861 1012
054b93e4
BS		 1013/* nouveau_grctx.c */
1014extern int nouveau_grctx_prog_load(struct drm_device *);
1015extern void nouveau_grctx_vals_load(struct drm_device *,
1016 struct nouveau_gpuobj *);
1017extern void nouveau_grctx_fini(struct drm_device *);
1018
6ee73861
BS		 1019/* nv04_instmem.c */
1020extern int nv04_instmem_init(struct drm_device *);
1021extern void nv04_instmem_takedown(struct drm_device *);
1022extern int nv04_instmem_suspend(struct drm_device *);
1023extern void nv04_instmem_resume(struct drm_device *);
1024extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1025 uint32_t *size);
1026extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1027extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1028extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1029extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1030
1031/* nv50_instmem.c */
1032extern int nv50_instmem_init(struct drm_device *);
1033extern void nv50_instmem_takedown(struct drm_device *);
1034extern int nv50_instmem_suspend(struct drm_device *);
1035extern void nv50_instmem_resume(struct drm_device *);
1036extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1037 uint32_t *size);
1038extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1039extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1040extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1041extern void nv50_instmem_flush(struct drm_device *);
6ee73861
BS		 1042
1043/* nv04_mc.c */
1044extern int nv04_mc_init(struct drm_device *);
1045extern void nv04_mc_takedown(struct drm_device *);
1046
1047/* nv40_mc.c */
1048extern int nv40_mc_init(struct drm_device *);
1049extern void nv40_mc_takedown(struct drm_device *);
1050
1051/* nv50_mc.c */
1052extern int nv50_mc_init(struct drm_device *);
1053extern void nv50_mc_takedown(struct drm_device *);
1054
1055/* nv04_timer.c */
1056extern int nv04_timer_init(struct drm_device *);
1057extern uint64_t nv04_timer_read(struct drm_device *);
1058extern void nv04_timer_takedown(struct drm_device *);
1059
1060extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1061 unsigned long arg);
1062
1063/* nv04_dac.c */
8f1a6086 1064extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1065extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1066extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1067extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1068extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1069
1070/* nv04_dfp.c */
8f1a6086 1071extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1072extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1073extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1074 int head, bool dl);
1075extern void nv04_dfp_disable(struct drm_device *dev, int head);
1076extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1077
1078/* nv04_tv.c */
1079extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1080extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1081
1082/* nv17_tv.c */
8f1a6086 1083extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1084
1085/* nv04_display.c */
1086extern int nv04_display_create(struct drm_device *);
1087extern void nv04_display_destroy(struct drm_device *);
1088extern void nv04_display_restore(struct drm_device *);
1089
1090/* nv04_crtc.c */
1091extern int nv04_crtc_create(struct drm_device *, int index);
1092
1093/* nouveau_bo.c */
1094extern struct ttm_bo_driver nouveau_bo_driver;
1095extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1096 int size, int align, uint32_t flags,
1097 uint32_t tile_mode, uint32_t tile_flags,
1098 bool no_vm, bool mappable, struct nouveau_bo **);
1099extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1100extern int nouveau_bo_unpin(struct nouveau_bo *);
1101extern int nouveau_bo_map(struct nouveau_bo *);
1102extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1103extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1104 uint32_t busy);
6ee73861
BS		 1105extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1106extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1107extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1108extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1109
1110/* nouveau_fence.c */
1111struct nouveau_fence;
1112extern int nouveau_fence_init(struct nouveau_channel *);
1113extern void nouveau_fence_fini(struct nouveau_channel *);
1114extern void nouveau_fence_update(struct nouveau_channel *);
1115extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1116 bool emit);
1117extern int nouveau_fence_emit(struct nouveau_fence *);
1118struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1119extern bool nouveau_fence_signalled(void *obj, void *arg);
1120extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1121extern int nouveau_fence_flush(void *obj, void *arg);
1122extern void nouveau_fence_unref(void **obj);
1123extern void *nouveau_fence_ref(void *obj);
1124extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1125
1126/* nouveau_gem.c */
1127extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1128 int size, int align, uint32_t flags,
1129 uint32_t tile_mode, uint32_t tile_flags,
1130 bool no_vm, bool mappable, struct nouveau_bo **);
1131extern int nouveau_gem_object_new(struct drm_gem_object *);
1132extern void nouveau_gem_object_del(struct drm_gem_object *);
1133extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1134 struct drm_file *);
1135extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1136 struct drm_file *);
6ee73861
BS		 1137extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1138 struct drm_file *);
1139extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1140 struct drm_file *);
1141extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1142 struct drm_file *);
1143
1144/* nv17_gpio.c */
1145int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1146int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1147
45284162
BS		 1148/* nv50_gpio.c */
1149int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1150int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1151
e9ebb68b
BS		 1152/* nv50_calc. */
1153int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1154 int *N1, int *M1, int *N2, int *M2, int *P);
1155int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1156 int clk, int *N, int *fN, int *M, int *P);
1157
6ee73861
BS		 1158#ifndef ioread32_native
1159#ifdef __BIG_ENDIAN
1160#define ioread16_native ioread16be
1161#define iowrite16_native iowrite16be
1162#define ioread32_native ioread32be
1163#define iowrite32_native iowrite32be
1164#else /* def __BIG_ENDIAN */
1165#define ioread16_native ioread16
1166#define iowrite16_native iowrite16
1167#define ioread32_native ioread32
1168#define iowrite32_native iowrite32
1169#endif /* def __BIG_ENDIAN else */
1170#endif /* !ioread32_native */
1171
1172/* channel control reg access */
1173static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1174{
1175 return ioread32_native(chan->user + reg);
1176}
1177
1178static inline void nvchan_wr32(struct nouveau_channel *chan,
1179 unsigned reg, u32 val)
1180{
1181 iowrite32_native(val, chan->user + reg);
1182}
1183
1184/* register access */
1185static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1186{
1187 struct drm_nouveau_private *dev_priv = dev->dev_private;
1188 return ioread32_native(dev_priv->mmio + reg);
1189}
1190
1191static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1192{
1193 struct drm_nouveau_private *dev_priv = dev->dev_private;
1194 iowrite32_native(val, dev_priv->mmio + reg);
1195}
1196
1197static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1198{
1199 struct drm_nouveau_private *dev_priv = dev->dev_private;
1200 return ioread8(dev_priv->mmio + reg);
1201}
1202
1203static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1204{
1205 struct drm_nouveau_private *dev_priv = dev->dev_private;
1206 iowrite8(val, dev_priv->mmio + reg);
1207}
1208
1209#define nv_wait(reg, mask, val) \
1210 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1211
1212/* PRAMIN access */
1213static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1214{
1215 struct drm_nouveau_private *dev_priv = dev->dev_private;
1216 return ioread32_native(dev_priv->ramin + offset);
1217}
1218
1219static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1220{
1221 struct drm_nouveau_private *dev_priv = dev->dev_private;
1222 iowrite32_native(val, dev_priv->ramin + offset);
1223}
1224
1225/* object access */
1226static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1227 unsigned index)
1228{
1229 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1230}
1231
1232static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1233 unsigned index, u32 val)
1234{
1235 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1236}
1237
1238/*
1239 * Logging
1240 * Argument d is (struct drm_device *).
1241 */
1242#define NV_PRINTK(level, d, fmt, arg...) \
1243 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1244 pci_name(d->pdev), ##arg)
1245#ifndef NV_DEBUG_NOTRACE
1246#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1247 if (drm_debug & DRM_UT_DRIVER) { \
1248 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1249 __LINE__, ##arg); \
1250 } \
1251} while (0)
1252#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1253 if (drm_debug & DRM_UT_KMS) { \
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BS		 1254 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1255 __LINE__, ##arg); \
1256 } \
1257} while (0)
1258#else
1259#define NV_DEBUG(d, fmt, arg...) do { \
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MM		 1260 if (drm_debug & DRM_UT_DRIVER) \
1261 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1262} while (0)
1263#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1264 if (drm_debug & DRM_UT_KMS) \
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BS		 1265 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1266} while (0)
1267#endif
1268#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1269#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1270#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1271#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1272#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1273
1274/* nouveau_reg_debug bitmask */
1275enum {
1276 NOUVEAU_REG_DEBUG_MC = 0x1,
1277 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1278 NOUVEAU_REG_DEBUG_FB = 0x4,
1279 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1280 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1281 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1282 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1283 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1284 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1285 NOUVEAU_REG_DEBUG_EVO = 0x200,
1286};
1287
1288#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1289 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1290 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1291} while (0)
1292
1293static inline bool
1294nv_two_heads(struct drm_device *dev)
1295{
1296 struct drm_nouveau_private *dev_priv = dev->dev_private;
1297 const int impl = dev->pci_device & 0x0ff0;
1298
1299 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1300 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1301 return true;
1302
1303 return false;
1304}
1305
1306static inline bool
1307nv_gf4_disp_arch(struct drm_device *dev)
1308{
1309 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1310}
1311
1312static inline bool
1313nv_two_reg_pll(struct drm_device *dev)
1314{
1315 struct drm_nouveau_private *dev_priv = dev->dev_private;
1316 const int impl = dev->pci_device & 0x0ff0;
1317
1318 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1319 return true;
1320 return false;
1321}
1322
f03a314b
FJ		 1323#define NV_SW 0x0000506e
1324#define NV_SW_DMA_SEMAPHORE 0x00000060
1325#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1326#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1327#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1328#define NV_SW_DMA_VBLSEM 0x0000018c
1329#define NV_SW_VBLSEM_OFFSET 0x00000400
1330#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1331#define NV_SW_VBLSEM_RELEASE 0x00000408
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BS		 1332
1333#endif /* __NOUVEAU_DRV_H__ */
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