]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/nouveau/nouveau_drv.h
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/nv50: make pushbuf dma object cover entire vm
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
37#define DRIVER_PATCHLEVEL 15
38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 struct ttm_bo_kmap_obj kmap;
80 struct list_head head;
81
82 /* protected by ttm_bo_reserve() */
83 struct drm_file *reserved_by;
84 struct list_head entry;
85 int pbbo_index;
86
87 struct nouveau_channel *channel;
88
89 bool mappable;
90 bool no_vm;
91
92 uint32_t tile_mode;
93 uint32_t tile_flags;
a0af9add 94 struct nouveau_tile_reg *tile;
6ee73861
BS		 95
96 struct drm_gem_object *gem;
97 struct drm_file *cpu_filp;
98 int pin_refcnt;
99};
100
101static inline struct nouveau_bo *
102nouveau_bo(struct ttm_buffer_object *bo)
103{
104 return container_of(bo, struct nouveau_bo, bo);
105}
106
107static inline struct nouveau_bo *
108nouveau_gem_object(struct drm_gem_object *gem)
109{
110 return gem ? gem->driver_private : NULL;
111}
112
113/* TODO: submit equivalent to TTM generic API upstream? */
114static inline void __iomem *
115nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
116{
117 bool is_iomem;
118 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
119 &nvbo->kmap, &is_iomem);
120 WARN_ON_ONCE(ioptr && !is_iomem);
121 return ioptr;
122}
123
124struct mem_block {
125 struct mem_block *next;
126 struct mem_block *prev;
127 uint64_t start;
128 uint64_t size;
129 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
130};
131
132enum nouveau_flags {
133 NV_NFORCE = 0x10000000,
134 NV_NFORCE2 = 0x20000000
135};
136
137#define NVOBJ_ENGINE_SW 0
138#define NVOBJ_ENGINE_GR 1
139#define NVOBJ_ENGINE_DISPLAY 2
140#define NVOBJ_ENGINE_INT 0xdeadbeef
141
142#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
143#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
144#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
145#define NVOBJ_FLAG_FAKE (1 << 3)
146struct nouveau_gpuobj {
147 struct list_head list;
148
149 struct nouveau_channel *im_channel;
150 struct mem_block *im_pramin;
151 struct nouveau_bo *im_backing;
152 uint32_t im_backing_start;
153 uint32_t *im_backing_suspend;
154 int im_bound;
155
156 uint32_t flags;
157 int refcount;
158
159 uint32_t engine;
160 uint32_t class;
161
162 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
163 void *priv;
164};
165
166struct nouveau_gpuobj_ref {
167 struct list_head list;
168
169 struct nouveau_gpuobj *gpuobj;
170 uint32_t instance;
171
172 struct nouveau_channel *channel;
173 int handle;
174};
175
176struct nouveau_channel {
177 struct drm_device *dev;
178 int id;
179
180 /* owner of this fifo */
181 struct drm_file *file_priv;
182 /* mapping of the fifo itself */
183 struct drm_local_map *map;
184
185 /* mapping of the regs controling the fifo */
186 void __iomem *user;
187 uint32_t user_get;
188 uint32_t user_put;
189
190 /* Fencing */
191 struct {
192 /* lock protects the pending list only */
193 spinlock_t lock;
194 struct list_head pending;
195 uint32_t sequence;
196 uint32_t sequence_ack;
197 uint32_t last_sequence_irq;
198 } fence;
199
200 /* DMA push buffer */
201 struct nouveau_gpuobj_ref *pushbuf;
202 struct nouveau_bo *pushbuf_bo;
203 uint32_t pushbuf_base;
204
205 /* Notifier memory */
206 struct nouveau_bo *notifier_bo;
207 struct mem_block *notifier_heap;
208
209 /* PFIFO context */
210 struct nouveau_gpuobj_ref *ramfc;
211 struct nouveau_gpuobj_ref *cache;
212
213 /* PGRAPH context */
214 /* XXX may be merge 2 pointers as private data ??? */
215 struct nouveau_gpuobj_ref *ramin_grctx;
216 void *pgraph_ctx;
217
218 /* NV50 VM */
219 struct nouveau_gpuobj *vm_pd;
220 struct nouveau_gpuobj_ref *vm_gart_pt;
221 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
222
223 /* Objects */
224 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
225 struct mem_block *ramin_heap; /* Private PRAMIN heap */
226 struct nouveau_gpuobj_ref *ramht; /* Hash table */
227 struct list_head ramht_refs; /* Objects referenced by RAMHT */
228
229 /* GPU object info for stuff used in-kernel (mm_enabled) */
230 uint32_t m2mf_ntfy;
231 uint32_t vram_handle;
232 uint32_t gart_handle;
233 bool accel_done;
234
235 /* Push buffer state (only for drm's channel on !mm_enabled) */
236 struct {
237 int max;
238 int free;
239 int cur;
240 int put;
241 /* access via pushbuf_bo */
9a391ad8
BS		 242
243 int ib_base;
244 int ib_max;
245 int ib_free;
246 int ib_put;
6ee73861
BS		 247 } dma;
248
249 uint32_t sw_subchannel[8];
250
251 struct {
252 struct nouveau_gpuobj *vblsem;
253 uint32_t vblsem_offset;
254 uint32_t vblsem_rval;
255 struct list_head vbl_wait;
256 } nvsw;
257
258 struct {
259 bool active;
260 char name[32];
261 struct drm_info_list info;
262 } debugfs;
263};
264
265struct nouveau_instmem_engine {
266 void *priv;
267
268 int (*init)(struct drm_device *dev);
269 void (*takedown)(struct drm_device *dev);
270 int (*suspend)(struct drm_device *dev);
271 void (*resume)(struct drm_device *dev);
272
273 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
274 uint32_t *size);
275 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
276 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
277 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
278 void (*prepare_access)(struct drm_device *, bool write);
279 void (*finish_access)(struct drm_device *);
280};
281
282struct nouveau_mc_engine {
283 int (*init)(struct drm_device *dev);
284 void (*takedown)(struct drm_device *dev);
285};
286
287struct nouveau_timer_engine {
288 int (*init)(struct drm_device *dev);
289 void (*takedown)(struct drm_device *dev);
290 uint64_t (*read)(struct drm_device *dev);
291};
292
293struct nouveau_fb_engine {
cb00f7c1
FJ		 294 int num_tiles;
295
6ee73861
BS		 296 int (*init)(struct drm_device *dev);
297 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 298
299 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
300 uint32_t size, uint32_t pitch);
6ee73861
BS		 301};
302
303struct nouveau_fifo_engine {
304 void *priv;
305
306 int channels;
307
308 int (*init)(struct drm_device *);
309 void (*takedown)(struct drm_device *);
310
311 void (*disable)(struct drm_device *);
312 void (*enable)(struct drm_device *);
313 bool (*reassign)(struct drm_device *, bool enable);
588d7d12
FJ		 314 bool (*cache_flush)(struct drm_device *dev);
315 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 316
317 int (*channel_id)(struct drm_device *);
318
319 int (*create_context)(struct nouveau_channel *);
320 void (*destroy_context)(struct nouveau_channel *);
321 int (*load_context)(struct nouveau_channel *);
322 int (*unload_context)(struct drm_device *);
323};
324
325struct nouveau_pgraph_object_method {
326 int id;
327 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
328 uint32_t data);
329};
330
331struct nouveau_pgraph_object_class {
332 int id;
333 bool software;
334 struct nouveau_pgraph_object_method *methods;
335};
336
337struct nouveau_pgraph_engine {
338 struct nouveau_pgraph_object_class *grclass;
339 bool accel_blocked;
340 void *ctxprog;
341 void *ctxvals;
054b93e4 342 int grctx_size;
6ee73861
BS		 343
344 int (*init)(struct drm_device *);
345 void (*takedown)(struct drm_device *);
346
347 void (*fifo_access)(struct drm_device *, bool);
348
349 struct nouveau_channel *(*channel)(struct drm_device *);
350 int (*create_context)(struct nouveau_channel *);
351 void (*destroy_context)(struct nouveau_channel *);
352 int (*load_context)(struct nouveau_channel *);
353 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 354
355 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
356 uint32_t size, uint32_t pitch);
6ee73861
BS		 357};
358
359struct nouveau_engine {
360 struct nouveau_instmem_engine instmem;
361 struct nouveau_mc_engine mc;
362 struct nouveau_timer_engine timer;
363 struct nouveau_fb_engine fb;
364 struct nouveau_pgraph_engine graph;
365 struct nouveau_fifo_engine fifo;
366};
367
368struct nouveau_pll_vals {
369 union {
370 struct {
371#ifdef __BIG_ENDIAN
372 uint8_t N1, M1, N2, M2;
373#else
374 uint8_t M1, N1, M2, N2;
375#endif
376 };
377 struct {
378 uint16_t NM1, NM2;
379 } __attribute__((packed));
380 };
381 int log2P;
382
383 int refclk;
384};
385
386enum nv04_fp_display_regs {
387 FP_DISPLAY_END,
388 FP_TOTAL,
389 FP_CRTC,
390 FP_SYNC_START,
391 FP_SYNC_END,
392 FP_VALID_START,
393 FP_VALID_END
394};
395
396struct nv04_crtc_reg {
397 unsigned char MiscOutReg; /* */
398 uint8_t CRTC[0x9f];
399 uint8_t CR58[0x10];
400 uint8_t Sequencer[5];
401 uint8_t Graphics[9];
402 uint8_t Attribute[21];
403 unsigned char DAC[768]; /* Internal Colorlookuptable */
404
405 /* PCRTC regs */
406 uint32_t fb_start;
407 uint32_t crtc_cfg;
408 uint32_t cursor_cfg;
409 uint32_t gpio_ext;
410 uint32_t crtc_830;
411 uint32_t crtc_834;
412 uint32_t crtc_850;
413 uint32_t crtc_eng_ctrl;
414
415 /* PRAMDAC regs */
416 uint32_t nv10_cursync;
417 struct nouveau_pll_vals pllvals;
418 uint32_t ramdac_gen_ctrl;
419 uint32_t ramdac_630;
420 uint32_t ramdac_634;
421 uint32_t tv_setup;
422 uint32_t tv_vtotal;
423 uint32_t tv_vskew;
424 uint32_t tv_vsync_delay;
425 uint32_t tv_htotal;
426 uint32_t tv_hskew;
427 uint32_t tv_hsync_delay;
428 uint32_t tv_hsync_delay2;
429 uint32_t fp_horiz_regs[7];
430 uint32_t fp_vert_regs[7];
431 uint32_t dither;
432 uint32_t fp_control;
433 uint32_t dither_regs[6];
434 uint32_t fp_debug_0;
435 uint32_t fp_debug_1;
436 uint32_t fp_debug_2;
437 uint32_t fp_margin_color;
438 uint32_t ramdac_8c0;
439 uint32_t ramdac_a20;
440 uint32_t ramdac_a24;
441 uint32_t ramdac_a34;
442 uint32_t ctv_regs[38];
443};
444
445struct nv04_output_reg {
446 uint32_t output;
447 int head;
448};
449
450struct nv04_mode_state {
451 uint32_t bpp;
452 uint32_t width;
453 uint32_t height;
454 uint32_t interlace;
455 uint32_t repaint0;
456 uint32_t repaint1;
457 uint32_t screen;
458 uint32_t scale;
459 uint32_t dither;
460 uint32_t extra;
461 uint32_t fifo;
462 uint32_t pixel;
463 uint32_t horiz;
464 int arbitration0;
465 int arbitration1;
466 uint32_t pll;
467 uint32_t pllB;
468 uint32_t vpll;
469 uint32_t vpll2;
470 uint32_t vpllB;
471 uint32_t vpll2B;
472 uint32_t pllsel;
473 uint32_t sel_clk;
474 uint32_t general;
475 uint32_t crtcOwner;
476 uint32_t head;
477 uint32_t head2;
478 uint32_t cursorConfig;
479 uint32_t cursor0;
480 uint32_t cursor1;
481 uint32_t cursor2;
482 uint32_t timingH;
483 uint32_t timingV;
484 uint32_t displayV;
485 uint32_t crtcSync;
486
487 struct nv04_crtc_reg crtc_reg[2];
488};
489
490enum nouveau_card_type {
491 NV_04 = 0x00,
492 NV_10 = 0x10,
493 NV_20 = 0x20,
494 NV_30 = 0x30,
495 NV_40 = 0x40,
496 NV_50 = 0x50,
497};
498
499struct drm_nouveau_private {
500 struct drm_device *dev;
501 enum {
502 NOUVEAU_CARD_INIT_DOWN,
503 NOUVEAU_CARD_INIT_DONE,
504 NOUVEAU_CARD_INIT_FAILED
505 } init_state;
506
507 /* the card type, takes NV_* as values */
508 enum nouveau_card_type card_type;
509 /* exact chipset, derived from NV_PMC_BOOT_0 */
510 int chipset;
511 int flags;
512
513 void __iomem *mmio;
514 void __iomem *ramin;
515 uint32_t ramin_size;
516
ac8fb975
BS		 517 struct nouveau_bo *vga_ram;
518
6ee73861
BS		 519 struct workqueue_struct *wq;
520 struct work_struct irq_work;
521
522 struct list_head vbl_waiting;
523
524 struct {
525 struct ttm_global_reference mem_global_ref;
526 struct ttm_bo_global_ref bo_global_ref;
527 struct ttm_bo_device bdev;
528 spinlock_t bo_list_lock;
529 struct list_head bo_list;
530 atomic_t validate_sequence;
531 } ttm;
532
533 struct fb_info *fbdev_info;
534
535 int fifo_alloc_count;
536 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
537
538 struct nouveau_engine engine;
539 struct nouveau_channel *channel;
540
ff9e5279
MM		 541 /* For PFIFO and PGRAPH. */
542 spinlock_t context_switch_lock;
543
6ee73861
BS		 544 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
545 struct nouveau_gpuobj *ramht;
546 uint32_t ramin_rsvd_vram;
547 uint32_t ramht_offset;
548 uint32_t ramht_size;
549 uint32_t ramht_bits;
550 uint32_t ramfc_offset;
551 uint32_t ramfc_size;
552 uint32_t ramro_offset;
553 uint32_t ramro_size;
554
555 /* base physical adresses */
556 uint64_t fb_phys;
557 uint64_t fb_available_size;
558 uint64_t fb_mappable_pages;
559 uint64_t fb_aper_free;
560
561 struct {
562 enum {
563 NOUVEAU_GART_NONE = 0,
564 NOUVEAU_GART_AGP,
565 NOUVEAU_GART_SGDMA
566 } type;
567 uint64_t aper_base;
568 uint64_t aper_size;
569 uint64_t aper_free;
570
571 struct nouveau_gpuobj *sg_ctxdma;
572 struct page *sg_dummy_page;
573 dma_addr_t sg_dummy_bus;
574
575 /* nottm hack */
576 struct drm_ttm_backend *sg_be;
577 unsigned long sg_handle;
578 } gart_info;
579
a0af9add
FJ		 580 /* nv10-nv40 tiling regions */
581 struct {
582 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
583 spinlock_t lock;
584 } tile;
585
6ee73861
BS		 586 /* G8x/G9x virtual address space */
587 uint64_t vm_gart_base;
588 uint64_t vm_gart_size;
589 uint64_t vm_vram_base;
590 uint64_t vm_vram_size;
591 uint64_t vm_end;
592 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
593 int vm_vram_pt_nr;
76befb8c 594 uint64_t vram_sys_base;
6ee73861
BS		 595
596 /* the mtrr covering the FB */
597 int fb_mtrr;
598
599 struct mem_block *ramin_heap;
600
601 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
602 uint32_t ctx_table_size;
603 struct nouveau_gpuobj_ref *ctx_table;
604
605 struct list_head gpuobj_list;
606
607 struct nvbios VBIOS;
608 struct nouveau_bios_info *vbios;
609
610 struct nv04_mode_state mode_reg;
611 struct nv04_mode_state saved_reg;
612 uint32_t saved_vga_font[4][16384];
613 uint32_t crtc_owner;
614 uint32_t dac_users[4];
615
616 struct nouveau_suspend_resume {
617 uint32_t fifo_mode;
618 uint32_t graph_ctx_control;
619 uint32_t graph_state;
620 uint32_t *ramin_copy;
621 uint64_t ramin_size;
622 } susres;
623
624 struct backlight_device *backlight;
625 bool acpi_dsm;
626
627 struct nouveau_channel *evo;
628
629 struct {
630 struct dentry *channel_root;
631 } debugfs;
632};
633
634static inline struct drm_nouveau_private *
635nouveau_bdev(struct ttm_bo_device *bd)
636{
637 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
638}
639
640static inline int
641nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
642{
643 struct nouveau_bo *prev;
644
645 if (!pnvbo)
646 return -EINVAL;
647 prev = *pnvbo;
648
649 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
650 if (prev) {
651 struct ttm_buffer_object *bo = &prev->bo;
652
653 ttm_bo_unref(&bo);
654 }
655
656 return 0;
657}
658
659#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
660 struct drm_nouveau_private *nv = dev->dev_private; \
661 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
662 NV_ERROR(dev, "called without init\n"); \
663 return -EINVAL; \
664 } \
665} while (0)
666
667#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
668 struct drm_nouveau_private *nv = dev->dev_private; \
669 if (!nouveau_channel_owner(dev, (cl), (id))) { \
670 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
671 DRM_CURRENTPID, (id)); \
672 return -EPERM; \
673 } \
674 (ch) = nv->fifos[(id)]; \
675} while (0)
676
677/* nouveau_drv.c */
678extern int nouveau_noagp;
679extern int nouveau_duallink;
680extern int nouveau_uscript_lvds;
681extern int nouveau_uscript_tmds;
682extern int nouveau_vram_pushbuf;
683extern int nouveau_vram_notify;
684extern int nouveau_fbpercrtc;
685extern char *nouveau_tv_norm;
686extern int nouveau_reg_debug;
687extern char *nouveau_vbios;
054b93e4 688extern int nouveau_ctxfw;
a1470890 689extern int nouveau_ignorelid;
a32ed69d
MK		 690extern int nouveau_nofbaccel;
691extern int nouveau_noaccel;
6ee73861
BS		 692
693/* nouveau_state.c */
694extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
695extern int nouveau_load(struct drm_device *, unsigned long flags);
696extern int nouveau_firstopen(struct drm_device *);
697extern void nouveau_lastclose(struct drm_device *);
698extern int nouveau_unload(struct drm_device *);
699extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
700 struct drm_file *);
701extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
702 struct drm_file *);
703extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
704 uint32_t reg, uint32_t mask, uint32_t val);
705extern bool nouveau_wait_for_idle(struct drm_device *);
706extern int nouveau_card_init(struct drm_device *);
707extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
708 struct drm_file *);
709extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
710 struct drm_file *);
711extern int nouveau_ioctl_resume(struct drm_device *, void *data,
712 struct drm_file *);
713
714/* nouveau_mem.c */
715extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
716 uint64_t size);
717extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
718 uint64_t size, int align2,
719 struct drm_file *, int tail);
720extern void nouveau_mem_takedown(struct mem_block **heap);
721extern void nouveau_mem_free_block(struct mem_block *);
722extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
723extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
724extern int nouveau_mem_init(struct drm_device *);
725extern int nouveau_mem_init_agp(struct drm_device *);
726extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 727extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
728 uint32_t addr,
729 uint32_t size,
730 uint32_t pitch);
731extern void nv10_mem_expire_tiling(struct drm_device *dev,
732 struct nouveau_tile_reg *tile,
733 struct nouveau_fence *fence);
6ee73861
BS		 734extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
735 uint32_t size, uint32_t flags,
736 uint64_t phys);
737extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
738 uint32_t size);
739
740/* nouveau_notifier.c */
741extern int nouveau_notifier_init_channel(struct nouveau_channel *);
742extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
743extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
744 int cout, uint32_t *offset);
745extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
746extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
747 struct drm_file *);
748extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
749 struct drm_file *);
750
751/* nouveau_channel.c */
752extern struct drm_ioctl_desc nouveau_ioctls[];
753extern int nouveau_max_ioctl;
754extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
755extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
756 int channel);
757extern int nouveau_channel_alloc(struct drm_device *dev,
758 struct nouveau_channel **chan,
759 struct drm_file *file_priv,
760 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
761extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 762
763/* nouveau_object.c */
764extern int nouveau_gpuobj_early_init(struct drm_device *);
765extern int nouveau_gpuobj_init(struct drm_device *);
766extern void nouveau_gpuobj_takedown(struct drm_device *);
767extern void nouveau_gpuobj_late_takedown(struct drm_device *);
768extern int nouveau_gpuobj_suspend(struct drm_device *dev);
769extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
770extern void nouveau_gpuobj_resume(struct drm_device *dev);
771extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
772 uint32_t vram_h, uint32_t tt_h);
773extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
774extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
775 uint32_t size, int align, uint32_t flags,
776 struct nouveau_gpuobj **);
777extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
778extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
779 uint32_t handle, struct nouveau_gpuobj *,
780 struct nouveau_gpuobj_ref **);
781extern int nouveau_gpuobj_ref_del(struct drm_device *,
782 struct nouveau_gpuobj_ref **);
783extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
784 struct nouveau_gpuobj_ref **ref_ret);
785extern int nouveau_gpuobj_new_ref(struct drm_device *,
786 struct nouveau_channel *alloc_chan,
787 struct nouveau_channel *ref_chan,
788 uint32_t handle, uint32_t size, int align,
789 uint32_t flags, struct nouveau_gpuobj_ref **);
790extern int nouveau_gpuobj_new_fake(struct drm_device *,
791 uint32_t p_offset, uint32_t b_offset,
792 uint32_t size, uint32_t flags,
793 struct nouveau_gpuobj **,
794 struct nouveau_gpuobj_ref**);
795extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
796 uint64_t offset, uint64_t size, int access,
797 int target, struct nouveau_gpuobj **);
798extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
799 uint64_t offset, uint64_t size,
800 int access, struct nouveau_gpuobj **,
801 uint32_t *o_ret);
802extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
803 struct nouveau_gpuobj **);
f03a314b
FJ		 804extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
805 struct nouveau_gpuobj **);
6ee73861
BS		 806extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
807 struct drm_file *);
808extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
809 struct drm_file *);
810
811/* nouveau_irq.c */
812extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
813extern void nouveau_irq_preinstall(struct drm_device *);
814extern int nouveau_irq_postinstall(struct drm_device *);
815extern void nouveau_irq_uninstall(struct drm_device *);
816
817/* nouveau_sgdma.c */
818extern int nouveau_sgdma_init(struct drm_device *);
819extern void nouveau_sgdma_takedown(struct drm_device *);
820extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
821 uint32_t *page);
822extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
823
824/* nouveau_debugfs.c */
825#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
826extern int nouveau_debugfs_init(struct drm_minor *);
827extern void nouveau_debugfs_takedown(struct drm_minor *);
828extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
829extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
830#else
831static inline int
832nouveau_debugfs_init(struct drm_minor *minor)
833{
834 return 0;
835}
836
837static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
838{
839}
840
841static inline int
842nouveau_debugfs_channel_init(struct nouveau_channel *chan)
843{
844 return 0;
845}
846
847static inline void
848nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
849{
850}
851#endif
852
853/* nouveau_dma.c */
75c99da6 854extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 855extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 856extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 857
858/* nouveau_acpi.c */
859#ifdef CONFIG_ACPI
860extern int nouveau_hybrid_setup(struct drm_device *dev);
861extern bool nouveau_dsm_probe(struct drm_device *dev);
862#else
863static inline int nouveau_hybrid_setup(struct drm_device *dev)
864{
865 return 0;
866}
867static inline bool nouveau_dsm_probe(struct drm_device *dev)
868{
869 return false;
870}
871#endif
872
873/* nouveau_backlight.c */
874#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
875extern int nouveau_backlight_init(struct drm_device *);
876extern void nouveau_backlight_exit(struct drm_device *);
877#else
878static inline int nouveau_backlight_init(struct drm_device *dev)
879{
880 return 0;
881}
882
883static inline void nouveau_backlight_exit(struct drm_device *dev) { }
884#endif
885
886/* nouveau_bios.c */
887extern int nouveau_bios_init(struct drm_device *);
888extern void nouveau_bios_takedown(struct drm_device *dev);
889extern int nouveau_run_vbios_init(struct drm_device *);
890extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
891 struct dcb_entry *);
892extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
893 enum dcb_gpio_tag);
894extern struct dcb_connector_table_entry *
895nouveau_bios_connector_entry(struct drm_device *, int index);
896extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
897 struct pll_lims *);
898extern int nouveau_bios_run_display_table(struct drm_device *,
899 struct dcb_entry *,
900 uint32_t script, int pxclk);
901extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
902 int *length);
903extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
904extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
905extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
906 bool *dl, bool *if_is_24bit);
907extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
908 int head, int pxclk);
909extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
910 enum LVDS_script, int pxclk);
911
912/* nouveau_ttm.c */
913int nouveau_ttm_global_init(struct drm_nouveau_private *);
914void nouveau_ttm_global_release(struct drm_nouveau_private *);
915int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
916
917/* nouveau_dp.c */
918int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
919 uint8_t *data, int data_nr);
920bool nouveau_dp_detect(struct drm_encoder *);
921bool nouveau_dp_link_train(struct drm_encoder *);
922
923/* nv04_fb.c */
924extern int nv04_fb_init(struct drm_device *);
925extern void nv04_fb_takedown(struct drm_device *);
926
927/* nv10_fb.c */
928extern int nv10_fb_init(struct drm_device *);
929extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 930extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
931 uint32_t, uint32_t);
6ee73861
BS		 932
933/* nv40_fb.c */
934extern int nv40_fb_init(struct drm_device *);
935extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 936extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
937 uint32_t, uint32_t);
6ee73861
BS		 938
939/* nv04_fifo.c */
940extern int nv04_fifo_init(struct drm_device *);
941extern void nv04_fifo_disable(struct drm_device *);
942extern void nv04_fifo_enable(struct drm_device *);
943extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12
FJ		 944extern bool nv04_fifo_cache_flush(struct drm_device *);
945extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 946extern int nv04_fifo_channel_id(struct drm_device *);
947extern int nv04_fifo_create_context(struct nouveau_channel *);
948extern void nv04_fifo_destroy_context(struct nouveau_channel *);
949extern int nv04_fifo_load_context(struct nouveau_channel *);
950extern int nv04_fifo_unload_context(struct drm_device *);
951
952/* nv10_fifo.c */
953extern int nv10_fifo_init(struct drm_device *);
954extern int nv10_fifo_channel_id(struct drm_device *);
955extern int nv10_fifo_create_context(struct nouveau_channel *);
956extern void nv10_fifo_destroy_context(struct nouveau_channel *);
957extern int nv10_fifo_load_context(struct nouveau_channel *);
958extern int nv10_fifo_unload_context(struct drm_device *);
959
960/* nv40_fifo.c */
961extern int nv40_fifo_init(struct drm_device *);
962extern int nv40_fifo_create_context(struct nouveau_channel *);
963extern void nv40_fifo_destroy_context(struct nouveau_channel *);
964extern int nv40_fifo_load_context(struct nouveau_channel *);
965extern int nv40_fifo_unload_context(struct drm_device *);
966
967/* nv50_fifo.c */
968extern int nv50_fifo_init(struct drm_device *);
969extern void nv50_fifo_takedown(struct drm_device *);
970extern int nv50_fifo_channel_id(struct drm_device *);
971extern int nv50_fifo_create_context(struct nouveau_channel *);
972extern void nv50_fifo_destroy_context(struct nouveau_channel *);
973extern int nv50_fifo_load_context(struct nouveau_channel *);
974extern int nv50_fifo_unload_context(struct drm_device *);
975
976/* nv04_graph.c */
977extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
978extern int nv04_graph_init(struct drm_device *);
979extern void nv04_graph_takedown(struct drm_device *);
980extern void nv04_graph_fifo_access(struct drm_device *, bool);
981extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
982extern int nv04_graph_create_context(struct nouveau_channel *);
983extern void nv04_graph_destroy_context(struct nouveau_channel *);
984extern int nv04_graph_load_context(struct nouveau_channel *);
985extern int nv04_graph_unload_context(struct drm_device *);
986extern void nv04_graph_context_switch(struct drm_device *);
987
988/* nv10_graph.c */
989extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
990extern int nv10_graph_init(struct drm_device *);
991extern void nv10_graph_takedown(struct drm_device *);
992extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
993extern int nv10_graph_create_context(struct nouveau_channel *);
994extern void nv10_graph_destroy_context(struct nouveau_channel *);
995extern int nv10_graph_load_context(struct nouveau_channel *);
996extern int nv10_graph_unload_context(struct drm_device *);
997extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 998extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
999 uint32_t, uint32_t);
6ee73861
BS		 1000
1001/* nv20_graph.c */
1002extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1003extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1004extern int nv20_graph_create_context(struct nouveau_channel *);
1005extern void nv20_graph_destroy_context(struct nouveau_channel *);
1006extern int nv20_graph_load_context(struct nouveau_channel *);
1007extern int nv20_graph_unload_context(struct drm_device *);
1008extern int nv20_graph_init(struct drm_device *);
1009extern void nv20_graph_takedown(struct drm_device *);
1010extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1011extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1012 uint32_t, uint32_t);
6ee73861
BS		 1013
1014/* nv40_graph.c */
1015extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1016extern int nv40_graph_init(struct drm_device *);
1017extern void nv40_graph_takedown(struct drm_device *);
1018extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1019extern int nv40_graph_create_context(struct nouveau_channel *);
1020extern void nv40_graph_destroy_context(struct nouveau_channel *);
1021extern int nv40_graph_load_context(struct nouveau_channel *);
1022extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1023extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1024extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1025 uint32_t, uint32_t);
6ee73861
BS		 1026
1027/* nv50_graph.c */
1028extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1029extern int nv50_graph_init(struct drm_device *);
1030extern void nv50_graph_takedown(struct drm_device *);
1031extern void nv50_graph_fifo_access(struct drm_device *, bool);
1032extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1033extern int nv50_graph_create_context(struct nouveau_channel *);
1034extern void nv50_graph_destroy_context(struct nouveau_channel *);
1035extern int nv50_graph_load_context(struct nouveau_channel *);
1036extern int nv50_graph_unload_context(struct drm_device *);
1037extern void nv50_graph_context_switch(struct drm_device *);
1038
054b93e4
BS		 1039/* nouveau_grctx.c */
1040extern int nouveau_grctx_prog_load(struct drm_device *);
1041extern void nouveau_grctx_vals_load(struct drm_device *,
1042 struct nouveau_gpuobj *);
1043extern void nouveau_grctx_fini(struct drm_device *);
1044
6ee73861
BS		 1045/* nv04_instmem.c */
1046extern int nv04_instmem_init(struct drm_device *);
1047extern void nv04_instmem_takedown(struct drm_device *);
1048extern int nv04_instmem_suspend(struct drm_device *);
1049extern void nv04_instmem_resume(struct drm_device *);
1050extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1051 uint32_t *size);
1052extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1053extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1054extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1055extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1056extern void nv04_instmem_finish_access(struct drm_device *);
1057
1058/* nv50_instmem.c */
1059extern int nv50_instmem_init(struct drm_device *);
1060extern void nv50_instmem_takedown(struct drm_device *);
1061extern int nv50_instmem_suspend(struct drm_device *);
1062extern void nv50_instmem_resume(struct drm_device *);
1063extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1064 uint32_t *size);
1065extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1066extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1067extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1068extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1069extern void nv50_instmem_finish_access(struct drm_device *);
1070
1071/* nv04_mc.c */
1072extern int nv04_mc_init(struct drm_device *);
1073extern void nv04_mc_takedown(struct drm_device *);
1074
1075/* nv40_mc.c */
1076extern int nv40_mc_init(struct drm_device *);
1077extern void nv40_mc_takedown(struct drm_device *);
1078
1079/* nv50_mc.c */
1080extern int nv50_mc_init(struct drm_device *);
1081extern void nv50_mc_takedown(struct drm_device *);
1082
1083/* nv04_timer.c */
1084extern int nv04_timer_init(struct drm_device *);
1085extern uint64_t nv04_timer_read(struct drm_device *);
1086extern void nv04_timer_takedown(struct drm_device *);
1087
1088extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1089 unsigned long arg);
1090
1091/* nv04_dac.c */
1092extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
11d6eb2a 1093extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1094extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1095extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1096
1097/* nv04_dfp.c */
1098extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1099extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1100extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1101 int head, bool dl);
1102extern void nv04_dfp_disable(struct drm_device *dev, int head);
1103extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1104
1105/* nv04_tv.c */
1106extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1107extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1108
1109/* nv17_tv.c */
1110extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
6ee73861
BS		 1111
1112/* nv04_display.c */
1113extern int nv04_display_create(struct drm_device *);
1114extern void nv04_display_destroy(struct drm_device *);
1115extern void nv04_display_restore(struct drm_device *);
1116
1117/* nv04_crtc.c */
1118extern int nv04_crtc_create(struct drm_device *, int index);
1119
1120/* nouveau_bo.c */
1121extern struct ttm_bo_driver nouveau_bo_driver;
1122extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1123 int size, int align, uint32_t flags,
1124 uint32_t tile_mode, uint32_t tile_flags,
1125 bool no_vm, bool mappable, struct nouveau_bo **);
1126extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1127extern int nouveau_bo_unpin(struct nouveau_bo *);
1128extern int nouveau_bo_map(struct nouveau_bo *);
1129extern void nouveau_bo_unmap(struct nouveau_bo *);
1130extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1131extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1132extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1133extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1134extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1135
1136/* nouveau_fence.c */
1137struct nouveau_fence;
1138extern int nouveau_fence_init(struct nouveau_channel *);
1139extern void nouveau_fence_fini(struct nouveau_channel *);
1140extern void nouveau_fence_update(struct nouveau_channel *);
1141extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1142 bool emit);
1143extern int nouveau_fence_emit(struct nouveau_fence *);
1144struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1145extern bool nouveau_fence_signalled(void *obj, void *arg);
1146extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1147extern int nouveau_fence_flush(void *obj, void *arg);
1148extern void nouveau_fence_unref(void **obj);
1149extern void *nouveau_fence_ref(void *obj);
1150extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1151
1152/* nouveau_gem.c */
1153extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1154 int size, int align, uint32_t flags,
1155 uint32_t tile_mode, uint32_t tile_flags,
1156 bool no_vm, bool mappable, struct nouveau_bo **);
1157extern int nouveau_gem_object_new(struct drm_gem_object *);
1158extern void nouveau_gem_object_del(struct drm_gem_object *);
1159extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1160 struct drm_file *);
1161extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1162 struct drm_file *);
1163extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
1164 struct drm_file *);
1165extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
1166 struct drm_file *);
1167extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
1168 struct drm_file *);
1169extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
1170 struct drm_file *);
1171extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
1172 struct drm_file *);
1173extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1174 struct drm_file *);
1175extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1176 struct drm_file *);
1177extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1178 struct drm_file *);
1179
1180/* nv17_gpio.c */
1181int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1182int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1183
1184#ifndef ioread32_native
1185#ifdef __BIG_ENDIAN
1186#define ioread16_native ioread16be
1187#define iowrite16_native iowrite16be
1188#define ioread32_native ioread32be
1189#define iowrite32_native iowrite32be
1190#else /* def __BIG_ENDIAN */
1191#define ioread16_native ioread16
1192#define iowrite16_native iowrite16
1193#define ioread32_native ioread32
1194#define iowrite32_native iowrite32
1195#endif /* def __BIG_ENDIAN else */
1196#endif /* !ioread32_native */
1197
1198/* channel control reg access */
1199static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1200{
1201 return ioread32_native(chan->user + reg);
1202}
1203
1204static inline void nvchan_wr32(struct nouveau_channel *chan,
1205 unsigned reg, u32 val)
1206{
1207 iowrite32_native(val, chan->user + reg);
1208}
1209
1210/* register access */
1211static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1212{
1213 struct drm_nouveau_private *dev_priv = dev->dev_private;
1214 return ioread32_native(dev_priv->mmio + reg);
1215}
1216
1217static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1218{
1219 struct drm_nouveau_private *dev_priv = dev->dev_private;
1220 iowrite32_native(val, dev_priv->mmio + reg);
1221}
1222
1223static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1224{
1225 struct drm_nouveau_private *dev_priv = dev->dev_private;
1226 return ioread8(dev_priv->mmio + reg);
1227}
1228
1229static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1230{
1231 struct drm_nouveau_private *dev_priv = dev->dev_private;
1232 iowrite8(val, dev_priv->mmio + reg);
1233}
1234
1235#define nv_wait(reg, mask, val) \
1236 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1237
1238/* PRAMIN access */
1239static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1240{
1241 struct drm_nouveau_private *dev_priv = dev->dev_private;
1242 return ioread32_native(dev_priv->ramin + offset);
1243}
1244
1245static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1246{
1247 struct drm_nouveau_private *dev_priv = dev->dev_private;
1248 iowrite32_native(val, dev_priv->ramin + offset);
1249}
1250
1251/* object access */
1252static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1253 unsigned index)
1254{
1255 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1256}
1257
1258static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1259 unsigned index, u32 val)
1260{
1261 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1262}
1263
1264/*
1265 * Logging
1266 * Argument d is (struct drm_device *).
1267 */
1268#define NV_PRINTK(level, d, fmt, arg...) \
1269 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1270 pci_name(d->pdev), ##arg)
1271#ifndef NV_DEBUG_NOTRACE
1272#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1273 if (drm_debug & DRM_UT_DRIVER) { \
1274 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1275 __LINE__, ##arg); \
1276 } \
1277} while (0)
1278#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1279 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1280 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1281 __LINE__, ##arg); \
1282 } \
1283} while (0)
1284#else
1285#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1286 if (drm_debug & DRM_UT_DRIVER) \
1287 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1288} while (0)
1289#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1290 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1291 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1292} while (0)
1293#endif
1294#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1295#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1296#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1297#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1298#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1299
1300/* nouveau_reg_debug bitmask */
1301enum {
1302 NOUVEAU_REG_DEBUG_MC = 0x1,
1303 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1304 NOUVEAU_REG_DEBUG_FB = 0x4,
1305 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1306 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1307 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1308 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1309 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1310 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1311 NOUVEAU_REG_DEBUG_EVO = 0x200,
1312};
1313
1314#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1315 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1316 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1317} while (0)
1318
1319static inline bool
1320nv_two_heads(struct drm_device *dev)
1321{
1322 struct drm_nouveau_private *dev_priv = dev->dev_private;
1323 const int impl = dev->pci_device & 0x0ff0;
1324
1325 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1326 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1327 return true;
1328
1329 return false;
1330}
1331
1332static inline bool
1333nv_gf4_disp_arch(struct drm_device *dev)
1334{
1335 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1336}
1337
1338static inline bool
1339nv_two_reg_pll(struct drm_device *dev)
1340{
1341 struct drm_nouveau_private *dev_priv = dev->dev_private;
1342 const int impl = dev->pci_device & 0x0ff0;
1343
1344 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1345 return true;
1346 return false;
1347}
1348
f03a314b
FJ		 1349#define NV_SW 0x0000506e
1350#define NV_SW_DMA_SEMAPHORE 0x00000060
1351#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1352#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1353#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1354#define NV_SW_DMA_VBLSEM 0x0000018c
1355#define NV_SW_VBLSEM_OFFSET 0x00000400
1356#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1357#define NV_SW_VBLSEM_RELEASE 0x00000408
6ee73861
BS		 1358
1359#endif /* __NOUVEAU_DRV_H__ */
Clone of davem's net-next-2.6 tree