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[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
103static inline struct nouveau_bo *
104nouveau_bo(struct ttm_buffer_object *bo)
105{
106 return container_of(bo, struct nouveau_bo, bo);
107}
108
109static inline struct nouveau_bo *
110nouveau_gem_object(struct drm_gem_object *gem)
111{
112 return gem ? gem->driver_private : NULL;
113}
114
115/* TODO: submit equivalent to TTM generic API upstream? */
116static inline void __iomem *
117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118{
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124}
125
6ee73861
BS		 126enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129};
130
131#define NVOBJ_ENGINE_SW 0
132#define NVOBJ_ENGINE_GR 1
133#define NVOBJ_ENGINE_DISPLAY 2
134#define NVOBJ_ENGINE_INT 0xdeadbeef
135
136#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
137#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
138#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
139#define NVOBJ_FLAG_FAKE (1 << 3)
140struct nouveau_gpuobj {
141 struct list_head list;
142
143 struct nouveau_channel *im_channel;
b833ac26 144 struct drm_mm_node *im_pramin;
6ee73861
BS		 145 struct nouveau_bo *im_backing;
146 uint32_t im_backing_start;
147 uint32_t *im_backing_suspend;
148 int im_bound;
149
150 uint32_t flags;
151 int refcount;
152
153 uint32_t engine;
154 uint32_t class;
155
156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
157 void *priv;
158};
159
160struct nouveau_gpuobj_ref {
161 struct list_head list;
162
163 struct nouveau_gpuobj *gpuobj;
164 uint32_t instance;
165
166 struct nouveau_channel *channel;
167 int handle;
168};
169
170struct nouveau_channel {
171 struct drm_device *dev;
172 int id;
173
174 /* owner of this fifo */
175 struct drm_file *file_priv;
176 /* mapping of the fifo itself */
177 struct drm_local_map *map;
178
179 /* mapping of the regs controling the fifo */
180 void __iomem *user;
181 uint32_t user_get;
182 uint32_t user_put;
183
184 /* Fencing */
185 struct {
186 /* lock protects the pending list only */
187 spinlock_t lock;
188 struct list_head pending;
189 uint32_t sequence;
190 uint32_t sequence_ack;
191 uint32_t last_sequence_irq;
192 } fence;
193
194 /* DMA push buffer */
195 struct nouveau_gpuobj_ref *pushbuf;
196 struct nouveau_bo *pushbuf_bo;
197 uint32_t pushbuf_base;
198
199 /* Notifier memory */
200 struct nouveau_bo *notifier_bo;
b833ac26 201 struct drm_mm notifier_heap;
6ee73861
BS		 202
203 /* PFIFO context */
204 struct nouveau_gpuobj_ref *ramfc;
205 struct nouveau_gpuobj_ref *cache;
206
207 /* PGRAPH context */
208 /* XXX may be merge 2 pointers as private data ??? */
209 struct nouveau_gpuobj_ref *ramin_grctx;
210 void *pgraph_ctx;
211
212 /* NV50 VM */
213 struct nouveau_gpuobj *vm_pd;
214 struct nouveau_gpuobj_ref *vm_gart_pt;
215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
216
217 /* Objects */
218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
b833ac26 219 struct drm_mm ramin_heap; /* Private PRAMIN heap */
6ee73861
BS		 220 struct nouveau_gpuobj_ref *ramht; /* Hash table */
221 struct list_head ramht_refs; /* Objects referenced by RAMHT */
222
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
224 uint32_t m2mf_ntfy;
225 uint32_t vram_handle;
226 uint32_t gart_handle;
227 bool accel_done;
228
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
230 struct {
231 int max;
232 int free;
233 int cur;
234 int put;
235 /* access via pushbuf_bo */
9a391ad8
BS		 236
237 int ib_base;
238 int ib_max;
239 int ib_free;
240 int ib_put;
6ee73861
BS		 241 } dma;
242
243 uint32_t sw_subchannel[8];
244
245 struct {
246 struct nouveau_gpuobj *vblsem;
247 uint32_t vblsem_offset;
248 uint32_t vblsem_rval;
249 struct list_head vbl_wait;
250 } nvsw;
251
252 struct {
253 bool active;
254 char name[32];
255 struct drm_info_list info;
256 } debugfs;
257};
258
259struct nouveau_instmem_engine {
260 void *priv;
261
262 int (*init)(struct drm_device *dev);
263 void (*takedown)(struct drm_device *dev);
264 int (*suspend)(struct drm_device *dev);
265 void (*resume)(struct drm_device *dev);
266
267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
268 uint32_t *size);
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
272 void (*prepare_access)(struct drm_device *, bool write);
273 void (*finish_access)(struct drm_device *);
274};
275
276struct nouveau_mc_engine {
277 int (*init)(struct drm_device *dev);
278 void (*takedown)(struct drm_device *dev);
279};
280
281struct nouveau_timer_engine {
282 int (*init)(struct drm_device *dev);
283 void (*takedown)(struct drm_device *dev);
284 uint64_t (*read)(struct drm_device *dev);
285};
286
287struct nouveau_fb_engine {
cb00f7c1
FJ		 288 int num_tiles;
289
6ee73861
BS		 290 int (*init)(struct drm_device *dev);
291 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 292
293 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
294 uint32_t size, uint32_t pitch);
6ee73861
BS		 295};
296
297struct nouveau_fifo_engine {
298 void *priv;
299
300 int channels;
301
302 int (*init)(struct drm_device *);
303 void (*takedown)(struct drm_device *);
304
305 void (*disable)(struct drm_device *);
306 void (*enable)(struct drm_device *);
307 bool (*reassign)(struct drm_device *, bool enable);
588d7d12
FJ		 308 bool (*cache_flush)(struct drm_device *dev);
309 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 310
311 int (*channel_id)(struct drm_device *);
312
313 int (*create_context)(struct nouveau_channel *);
314 void (*destroy_context)(struct nouveau_channel *);
315 int (*load_context)(struct nouveau_channel *);
316 int (*unload_context)(struct drm_device *);
317};
318
319struct nouveau_pgraph_object_method {
320 int id;
321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
322 uint32_t data);
323};
324
325struct nouveau_pgraph_object_class {
326 int id;
327 bool software;
328 struct nouveau_pgraph_object_method *methods;
329};
330
331struct nouveau_pgraph_engine {
332 struct nouveau_pgraph_object_class *grclass;
333 bool accel_blocked;
334 void *ctxprog;
335 void *ctxvals;
054b93e4 336 int grctx_size;
6ee73861
BS		 337
338 int (*init)(struct drm_device *);
339 void (*takedown)(struct drm_device *);
340
341 void (*fifo_access)(struct drm_device *, bool);
342
343 struct nouveau_channel *(*channel)(struct drm_device *);
344 int (*create_context)(struct nouveau_channel *);
345 void (*destroy_context)(struct nouveau_channel *);
346 int (*load_context)(struct nouveau_channel *);
347 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 348
349 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
350 uint32_t size, uint32_t pitch);
6ee73861
BS		 351};
352
353struct nouveau_engine {
354 struct nouveau_instmem_engine instmem;
355 struct nouveau_mc_engine mc;
356 struct nouveau_timer_engine timer;
357 struct nouveau_fb_engine fb;
358 struct nouveau_pgraph_engine graph;
359 struct nouveau_fifo_engine fifo;
360};
361
362struct nouveau_pll_vals {
363 union {
364 struct {
365#ifdef __BIG_ENDIAN
366 uint8_t N1, M1, N2, M2;
367#else
368 uint8_t M1, N1, M2, N2;
369#endif
370 };
371 struct {
372 uint16_t NM1, NM2;
373 } __attribute__((packed));
374 };
375 int log2P;
376
377 int refclk;
378};
379
380enum nv04_fp_display_regs {
381 FP_DISPLAY_END,
382 FP_TOTAL,
383 FP_CRTC,
384 FP_SYNC_START,
385 FP_SYNC_END,
386 FP_VALID_START,
387 FP_VALID_END
388};
389
390struct nv04_crtc_reg {
391 unsigned char MiscOutReg; /* */
392 uint8_t CRTC[0x9f];
393 uint8_t CR58[0x10];
394 uint8_t Sequencer[5];
395 uint8_t Graphics[9];
396 uint8_t Attribute[21];
397 unsigned char DAC[768]; /* Internal Colorlookuptable */
398
399 /* PCRTC regs */
400 uint32_t fb_start;
401 uint32_t crtc_cfg;
402 uint32_t cursor_cfg;
403 uint32_t gpio_ext;
404 uint32_t crtc_830;
405 uint32_t crtc_834;
406 uint32_t crtc_850;
407 uint32_t crtc_eng_ctrl;
408
409 /* PRAMDAC regs */
410 uint32_t nv10_cursync;
411 struct nouveau_pll_vals pllvals;
412 uint32_t ramdac_gen_ctrl;
413 uint32_t ramdac_630;
414 uint32_t ramdac_634;
415 uint32_t tv_setup;
416 uint32_t tv_vtotal;
417 uint32_t tv_vskew;
418 uint32_t tv_vsync_delay;
419 uint32_t tv_htotal;
420 uint32_t tv_hskew;
421 uint32_t tv_hsync_delay;
422 uint32_t tv_hsync_delay2;
423 uint32_t fp_horiz_regs[7];
424 uint32_t fp_vert_regs[7];
425 uint32_t dither;
426 uint32_t fp_control;
427 uint32_t dither_regs[6];
428 uint32_t fp_debug_0;
429 uint32_t fp_debug_1;
430 uint32_t fp_debug_2;
431 uint32_t fp_margin_color;
432 uint32_t ramdac_8c0;
433 uint32_t ramdac_a20;
434 uint32_t ramdac_a24;
435 uint32_t ramdac_a34;
436 uint32_t ctv_regs[38];
437};
438
439struct nv04_output_reg {
440 uint32_t output;
441 int head;
442};
443
444struct nv04_mode_state {
445 uint32_t bpp;
446 uint32_t width;
447 uint32_t height;
448 uint32_t interlace;
449 uint32_t repaint0;
450 uint32_t repaint1;
451 uint32_t screen;
452 uint32_t scale;
453 uint32_t dither;
454 uint32_t extra;
455 uint32_t fifo;
456 uint32_t pixel;
457 uint32_t horiz;
458 int arbitration0;
459 int arbitration1;
460 uint32_t pll;
461 uint32_t pllB;
462 uint32_t vpll;
463 uint32_t vpll2;
464 uint32_t vpllB;
465 uint32_t vpll2B;
466 uint32_t pllsel;
467 uint32_t sel_clk;
468 uint32_t general;
469 uint32_t crtcOwner;
470 uint32_t head;
471 uint32_t head2;
472 uint32_t cursorConfig;
473 uint32_t cursor0;
474 uint32_t cursor1;
475 uint32_t cursor2;
476 uint32_t timingH;
477 uint32_t timingV;
478 uint32_t displayV;
479 uint32_t crtcSync;
480
481 struct nv04_crtc_reg crtc_reg[2];
482};
483
484enum nouveau_card_type {
485 NV_04 = 0x00,
486 NV_10 = 0x10,
487 NV_20 = 0x20,
488 NV_30 = 0x30,
489 NV_40 = 0x40,
490 NV_50 = 0x50,
491};
492
493struct drm_nouveau_private {
494 struct drm_device *dev;
495 enum {
496 NOUVEAU_CARD_INIT_DOWN,
497 NOUVEAU_CARD_INIT_DONE,
498 NOUVEAU_CARD_INIT_FAILED
499 } init_state;
500
501 /* the card type, takes NV_* as values */
502 enum nouveau_card_type card_type;
503 /* exact chipset, derived from NV_PMC_BOOT_0 */
504 int chipset;
505 int flags;
506
507 void __iomem *mmio;
508 void __iomem *ramin;
509 uint32_t ramin_size;
510
ac8fb975
BS		 511 struct nouveau_bo *vga_ram;
512
6ee73861
BS		 513 struct workqueue_struct *wq;
514 struct work_struct irq_work;
a5acac66 515 struct work_struct hpd_work;
6ee73861
BS		 516
517 struct list_head vbl_waiting;
518
519 struct {
520 struct ttm_global_reference mem_global_ref;
521 struct ttm_bo_global_ref bo_global_ref;
522 struct ttm_bo_device bdev;
523 spinlock_t bo_list_lock;
524 struct list_head bo_list;
525 atomic_t validate_sequence;
526 } ttm;
527
528 struct fb_info *fbdev_info;
529
530 int fifo_alloc_count;
531 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
532
533 struct nouveau_engine engine;
534 struct nouveau_channel *channel;
535
ff9e5279
MM		 536 /* For PFIFO and PGRAPH. */
537 spinlock_t context_switch_lock;
538
6ee73861
BS		 539 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
540 struct nouveau_gpuobj *ramht;
541 uint32_t ramin_rsvd_vram;
542 uint32_t ramht_offset;
543 uint32_t ramht_size;
544 uint32_t ramht_bits;
545 uint32_t ramfc_offset;
546 uint32_t ramfc_size;
547 uint32_t ramro_offset;
548 uint32_t ramro_size;
549
6ee73861
BS		 550 struct {
551 enum {
552 NOUVEAU_GART_NONE = 0,
553 NOUVEAU_GART_AGP,
554 NOUVEAU_GART_SGDMA
555 } type;
556 uint64_t aper_base;
557 uint64_t aper_size;
558 uint64_t aper_free;
559
560 struct nouveau_gpuobj *sg_ctxdma;
561 struct page *sg_dummy_page;
562 dma_addr_t sg_dummy_bus;
6ee73861
BS		 563 } gart_info;
564
a0af9add
FJ		 565 /* nv10-nv40 tiling regions */
566 struct {
567 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
568 spinlock_t lock;
569 } tile;
570
a76fb4e8
BS		 571 /* VRAM/fb configuration */
572 uint64_t vram_size;
573 uint64_t vram_sys_base;
574
575 uint64_t fb_phys;
576 uint64_t fb_available_size;
577 uint64_t fb_mappable_pages;
578 uint64_t fb_aper_free;
579 int fb_mtrr;
580
6ee73861
BS		 581 /* G8x/G9x virtual address space */
582 uint64_t vm_gart_base;
583 uint64_t vm_gart_size;
584 uint64_t vm_vram_base;
585 uint64_t vm_vram_size;
586 uint64_t vm_end;
587 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
588 int vm_vram_pt_nr;
6ee73861 589
b833ac26 590 struct drm_mm ramin_heap;
6ee73861
BS		 591
592 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
593 uint32_t ctx_table_size;
594 struct nouveau_gpuobj_ref *ctx_table;
595
596 struct list_head gpuobj_list;
597
04a39c57 598 struct nvbios vbios;
6ee73861
BS		 599
600 struct nv04_mode_state mode_reg;
601 struct nv04_mode_state saved_reg;
602 uint32_t saved_vga_font[4][16384];
603 uint32_t crtc_owner;
604 uint32_t dac_users[4];
605
606 struct nouveau_suspend_resume {
6ee73861 607 uint32_t *ramin_copy;
6ee73861
BS		 608 } susres;
609
610 struct backlight_device *backlight;
6ee73861
BS		 611
612 struct nouveau_channel *evo;
613
614 struct {
615 struct dentry *channel_root;
616 } debugfs;
38651674 617
8be48d92 618 struct nouveau_fbdev *nfbdev;
06415c56 619 struct apertures_struct *apertures;
6ee73861
BS		 620};
621
622static inline struct drm_nouveau_private *
623nouveau_bdev(struct ttm_bo_device *bd)
624{
625 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
626}
627
628static inline int
629nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
630{
631 struct nouveau_bo *prev;
632
633 if (!pnvbo)
634 return -EINVAL;
635 prev = *pnvbo;
636
637 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
638 if (prev) {
639 struct ttm_buffer_object *bo = &prev->bo;
640
641 ttm_bo_unref(&bo);
642 }
643
644 return 0;
645}
646
647#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
648 struct drm_nouveau_private *nv = dev->dev_private; \
649 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
650 NV_ERROR(dev, "called without init\n"); \
651 return -EINVAL; \
652 } \
653} while (0)
654
655#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
656 struct drm_nouveau_private *nv = dev->dev_private; \
657 if (!nouveau_channel_owner(dev, (cl), (id))) { \
658 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
659 DRM_CURRENTPID, (id)); \
660 return -EPERM; \
661 } \
662 (ch) = nv->fifos[(id)]; \
663} while (0)
664
665/* nouveau_drv.c */
666extern int nouveau_noagp;
667extern int nouveau_duallink;
668extern int nouveau_uscript_lvds;
669extern int nouveau_uscript_tmds;
670extern int nouveau_vram_pushbuf;
671extern int nouveau_vram_notify;
672extern int nouveau_fbpercrtc;
f4053509 673extern int nouveau_tv_disable;
6ee73861
BS		 674extern char *nouveau_tv_norm;
675extern int nouveau_reg_debug;
676extern char *nouveau_vbios;
054b93e4 677extern int nouveau_ctxfw;
a1470890 678extern int nouveau_ignorelid;
a32ed69d
MK		 679extern int nouveau_nofbaccel;
680extern int nouveau_noaccel;
da647d5b 681extern int nouveau_override_conntype;
6ee73861 682
6a9ee8af
DA		 683extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
684extern int nouveau_pci_resume(struct pci_dev *pdev);
685
6ee73861
BS		 686/* nouveau_state.c */
687extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
688extern int nouveau_load(struct drm_device *, unsigned long flags);
689extern int nouveau_firstopen(struct drm_device *);
690extern void nouveau_lastclose(struct drm_device *);
691extern int nouveau_unload(struct drm_device *);
692extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
693 struct drm_file *);
694extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
695 struct drm_file *);
696extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
697 uint32_t reg, uint32_t mask, uint32_t val);
698extern bool nouveau_wait_for_idle(struct drm_device *);
699extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 700
701/* nouveau_mem.c */
a76fb4e8 702extern int nouveau_mem_detect(struct drm_device *dev);
6ee73861
BS		 703extern int nouveau_mem_init(struct drm_device *);
704extern int nouveau_mem_init_agp(struct drm_device *);
705extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 706extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
707 uint32_t addr,
708 uint32_t size,
709 uint32_t pitch);
710extern void nv10_mem_expire_tiling(struct drm_device *dev,
711 struct nouveau_tile_reg *tile,
712 struct nouveau_fence *fence);
6ee73861
BS		 713extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
714 uint32_t size, uint32_t flags,
715 uint64_t phys);
716extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
717 uint32_t size);
718
719/* nouveau_notifier.c */
720extern int nouveau_notifier_init_channel(struct nouveau_channel *);
721extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
722extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
723 int cout, uint32_t *offset);
724extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
725extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
726 struct drm_file *);
727extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
728 struct drm_file *);
729
730/* nouveau_channel.c */
731extern struct drm_ioctl_desc nouveau_ioctls[];
732extern int nouveau_max_ioctl;
733extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
734extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
735 int channel);
736extern int nouveau_channel_alloc(struct drm_device *dev,
737 struct nouveau_channel **chan,
738 struct drm_file *file_priv,
739 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
740extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 741
742/* nouveau_object.c */
743extern int nouveau_gpuobj_early_init(struct drm_device *);
744extern int nouveau_gpuobj_init(struct drm_device *);
745extern void nouveau_gpuobj_takedown(struct drm_device *);
746extern void nouveau_gpuobj_late_takedown(struct drm_device *);
747extern int nouveau_gpuobj_suspend(struct drm_device *dev);
748extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
749extern void nouveau_gpuobj_resume(struct drm_device *dev);
750extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
751 uint32_t vram_h, uint32_t tt_h);
752extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
753extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
754 uint32_t size, int align, uint32_t flags,
755 struct nouveau_gpuobj **);
756extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
757extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
758 uint32_t handle, struct nouveau_gpuobj *,
759 struct nouveau_gpuobj_ref **);
760extern int nouveau_gpuobj_ref_del(struct drm_device *,
761 struct nouveau_gpuobj_ref **);
762extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
763 struct nouveau_gpuobj_ref **ref_ret);
764extern int nouveau_gpuobj_new_ref(struct drm_device *,
765 struct nouveau_channel *alloc_chan,
766 struct nouveau_channel *ref_chan,
767 uint32_t handle, uint32_t size, int align,
768 uint32_t flags, struct nouveau_gpuobj_ref **);
769extern int nouveau_gpuobj_new_fake(struct drm_device *,
770 uint32_t p_offset, uint32_t b_offset,
771 uint32_t size, uint32_t flags,
772 struct nouveau_gpuobj **,
773 struct nouveau_gpuobj_ref**);
774extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
775 uint64_t offset, uint64_t size, int access,
776 int target, struct nouveau_gpuobj **);
777extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
778 uint64_t offset, uint64_t size,
779 int access, struct nouveau_gpuobj **,
780 uint32_t *o_ret);
781extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
782 struct nouveau_gpuobj **);
f03a314b
FJ		 783extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
784 struct nouveau_gpuobj **);
6ee73861
BS		 785extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
786 struct drm_file *);
787extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
788 struct drm_file *);
789
790/* nouveau_irq.c */
791extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
792extern void nouveau_irq_preinstall(struct drm_device *);
793extern int nouveau_irq_postinstall(struct drm_device *);
794extern void nouveau_irq_uninstall(struct drm_device *);
795
796/* nouveau_sgdma.c */
797extern int nouveau_sgdma_init(struct drm_device *);
798extern void nouveau_sgdma_takedown(struct drm_device *);
799extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
800 uint32_t *page);
801extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
802
803/* nouveau_debugfs.c */
804#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
805extern int nouveau_debugfs_init(struct drm_minor *);
806extern void nouveau_debugfs_takedown(struct drm_minor *);
807extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
808extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
809#else
810static inline int
811nouveau_debugfs_init(struct drm_minor *minor)
812{
813 return 0;
814}
815
816static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
817{
818}
819
820static inline int
821nouveau_debugfs_channel_init(struct nouveau_channel *chan)
822{
823 return 0;
824}
825
826static inline void
827nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
828{
829}
830#endif
831
832/* nouveau_dma.c */
75c99da6 833extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 834extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 835extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 836
837/* nouveau_acpi.c */
afeb3e11 838#define ROM_BIOS_PAGE 4096
2f41a7f1 839#if defined(CONFIG_ACPI)
6a9ee8af
DA		 840void nouveau_register_dsm_handler(void);
841void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 842int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
843bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
8edb381d
DA		 844#else
845static inline void nouveau_register_dsm_handler(void) {}
846static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 847static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
848static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
8edb381d 849#endif
6ee73861
BS		 850
851/* nouveau_backlight.c */
852#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
853extern int nouveau_backlight_init(struct drm_device *);
854extern void nouveau_backlight_exit(struct drm_device *);
855#else
856static inline int nouveau_backlight_init(struct drm_device *dev)
857{
858 return 0;
859}
860
861static inline void nouveau_backlight_exit(struct drm_device *dev) { }
862#endif
863
864/* nouveau_bios.c */
865extern int nouveau_bios_init(struct drm_device *);
866extern void nouveau_bios_takedown(struct drm_device *dev);
867extern int nouveau_run_vbios_init(struct drm_device *);
868extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
869 struct dcb_entry *);
870extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
871 enum dcb_gpio_tag);
872extern struct dcb_connector_table_entry *
873nouveau_bios_connector_entry(struct drm_device *, int index);
874extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
875 struct pll_lims *);
876extern int nouveau_bios_run_display_table(struct drm_device *,
877 struct dcb_entry *,
878 uint32_t script, int pxclk);
879extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
880 int *length);
881extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
882extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
883extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
884 bool *dl, bool *if_is_24bit);
885extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
886 int head, int pxclk);
887extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
888 enum LVDS_script, int pxclk);
889
890/* nouveau_ttm.c */
891int nouveau_ttm_global_init(struct drm_nouveau_private *);
892void nouveau_ttm_global_release(struct drm_nouveau_private *);
893int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
894
895/* nouveau_dp.c */
896int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
897 uint8_t *data, int data_nr);
898bool nouveau_dp_detect(struct drm_encoder *);
899bool nouveau_dp_link_train(struct drm_encoder *);
900
901/* nv04_fb.c */
902extern int nv04_fb_init(struct drm_device *);
903extern void nv04_fb_takedown(struct drm_device *);
904
905/* nv10_fb.c */
906extern int nv10_fb_init(struct drm_device *);
907extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 908extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
909 uint32_t, uint32_t);
6ee73861
BS		 910
911/* nv40_fb.c */
912extern int nv40_fb_init(struct drm_device *);
913extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 914extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
915 uint32_t, uint32_t);
6ee73861 916
304424e1
MK		 917/* nv50_fb.c */
918extern int nv50_fb_init(struct drm_device *);
919extern void nv50_fb_takedown(struct drm_device *);
920
6ee73861
BS		 921/* nv04_fifo.c */
922extern int nv04_fifo_init(struct drm_device *);
923extern void nv04_fifo_disable(struct drm_device *);
924extern void nv04_fifo_enable(struct drm_device *);
925extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12
FJ		 926extern bool nv04_fifo_cache_flush(struct drm_device *);
927extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 928extern int nv04_fifo_channel_id(struct drm_device *);
929extern int nv04_fifo_create_context(struct nouveau_channel *);
930extern void nv04_fifo_destroy_context(struct nouveau_channel *);
931extern int nv04_fifo_load_context(struct nouveau_channel *);
932extern int nv04_fifo_unload_context(struct drm_device *);
933
934/* nv10_fifo.c */
935extern int nv10_fifo_init(struct drm_device *);
936extern int nv10_fifo_channel_id(struct drm_device *);
937extern int nv10_fifo_create_context(struct nouveau_channel *);
938extern void nv10_fifo_destroy_context(struct nouveau_channel *);
939extern int nv10_fifo_load_context(struct nouveau_channel *);
940extern int nv10_fifo_unload_context(struct drm_device *);
941
942/* nv40_fifo.c */
943extern int nv40_fifo_init(struct drm_device *);
944extern int nv40_fifo_create_context(struct nouveau_channel *);
945extern void nv40_fifo_destroy_context(struct nouveau_channel *);
946extern int nv40_fifo_load_context(struct nouveau_channel *);
947extern int nv40_fifo_unload_context(struct drm_device *);
948
949/* nv50_fifo.c */
950extern int nv50_fifo_init(struct drm_device *);
951extern void nv50_fifo_takedown(struct drm_device *);
952extern int nv50_fifo_channel_id(struct drm_device *);
953extern int nv50_fifo_create_context(struct nouveau_channel *);
954extern void nv50_fifo_destroy_context(struct nouveau_channel *);
955extern int nv50_fifo_load_context(struct nouveau_channel *);
956extern int nv50_fifo_unload_context(struct drm_device *);
957
958/* nv04_graph.c */
959extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
960extern int nv04_graph_init(struct drm_device *);
961extern void nv04_graph_takedown(struct drm_device *);
962extern void nv04_graph_fifo_access(struct drm_device *, bool);
963extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
964extern int nv04_graph_create_context(struct nouveau_channel *);
965extern void nv04_graph_destroy_context(struct nouveau_channel *);
966extern int nv04_graph_load_context(struct nouveau_channel *);
967extern int nv04_graph_unload_context(struct drm_device *);
968extern void nv04_graph_context_switch(struct drm_device *);
969
970/* nv10_graph.c */
971extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
972extern int nv10_graph_init(struct drm_device *);
973extern void nv10_graph_takedown(struct drm_device *);
974extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
975extern int nv10_graph_create_context(struct nouveau_channel *);
976extern void nv10_graph_destroy_context(struct nouveau_channel *);
977extern int nv10_graph_load_context(struct nouveau_channel *);
978extern int nv10_graph_unload_context(struct drm_device *);
979extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 980extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
981 uint32_t, uint32_t);
6ee73861
BS		 982
983/* nv20_graph.c */
984extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
985extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
986extern int nv20_graph_create_context(struct nouveau_channel *);
987extern void nv20_graph_destroy_context(struct nouveau_channel *);
988extern int nv20_graph_load_context(struct nouveau_channel *);
989extern int nv20_graph_unload_context(struct drm_device *);
990extern int nv20_graph_init(struct drm_device *);
991extern void nv20_graph_takedown(struct drm_device *);
992extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 993extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
994 uint32_t, uint32_t);
6ee73861
BS		 995
996/* nv40_graph.c */
997extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
998extern int nv40_graph_init(struct drm_device *);
999extern void nv40_graph_takedown(struct drm_device *);
1000extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1001extern int nv40_graph_create_context(struct nouveau_channel *);
1002extern void nv40_graph_destroy_context(struct nouveau_channel *);
1003extern int nv40_graph_load_context(struct nouveau_channel *);
1004extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1005extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1006extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1007 uint32_t, uint32_t);
6ee73861
BS		 1008
1009/* nv50_graph.c */
1010extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1011extern int nv50_graph_init(struct drm_device *);
1012extern void nv50_graph_takedown(struct drm_device *);
1013extern void nv50_graph_fifo_access(struct drm_device *, bool);
1014extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1015extern int nv50_graph_create_context(struct nouveau_channel *);
1016extern void nv50_graph_destroy_context(struct nouveau_channel *);
1017extern int nv50_graph_load_context(struct nouveau_channel *);
1018extern int nv50_graph_unload_context(struct drm_device *);
1019extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1020extern int nv50_grctx_init(struct nouveau_grctx *);
6ee73861 1021
054b93e4
BS		 1022/* nouveau_grctx.c */
1023extern int nouveau_grctx_prog_load(struct drm_device *);
1024extern void nouveau_grctx_vals_load(struct drm_device *,
1025 struct nouveau_gpuobj *);
1026extern void nouveau_grctx_fini(struct drm_device *);
1027
6ee73861
BS		 1028/* nv04_instmem.c */
1029extern int nv04_instmem_init(struct drm_device *);
1030extern void nv04_instmem_takedown(struct drm_device *);
1031extern int nv04_instmem_suspend(struct drm_device *);
1032extern void nv04_instmem_resume(struct drm_device *);
1033extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1034 uint32_t *size);
1035extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1036extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1037extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1038extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1039extern void nv04_instmem_finish_access(struct drm_device *);
1040
1041/* nv50_instmem.c */
1042extern int nv50_instmem_init(struct drm_device *);
1043extern void nv50_instmem_takedown(struct drm_device *);
1044extern int nv50_instmem_suspend(struct drm_device *);
1045extern void nv50_instmem_resume(struct drm_device *);
1046extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1047 uint32_t *size);
1048extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1049extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1050extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1051extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1052extern void nv50_instmem_finish_access(struct drm_device *);
1053
1054/* nv04_mc.c */
1055extern int nv04_mc_init(struct drm_device *);
1056extern void nv04_mc_takedown(struct drm_device *);
1057
1058/* nv40_mc.c */
1059extern int nv40_mc_init(struct drm_device *);
1060extern void nv40_mc_takedown(struct drm_device *);
1061
1062/* nv50_mc.c */
1063extern int nv50_mc_init(struct drm_device *);
1064extern void nv50_mc_takedown(struct drm_device *);
1065
1066/* nv04_timer.c */
1067extern int nv04_timer_init(struct drm_device *);
1068extern uint64_t nv04_timer_read(struct drm_device *);
1069extern void nv04_timer_takedown(struct drm_device *);
1070
1071extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1072 unsigned long arg);
1073
1074/* nv04_dac.c */
8f1a6086 1075extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1076extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1077extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1078extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1079extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1080
1081/* nv04_dfp.c */
8f1a6086 1082extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1083extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1084extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1085 int head, bool dl);
1086extern void nv04_dfp_disable(struct drm_device *dev, int head);
1087extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1088
1089/* nv04_tv.c */
1090extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1091extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1092
1093/* nv17_tv.c */
8f1a6086 1094extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1095
1096/* nv04_display.c */
1097extern int nv04_display_create(struct drm_device *);
1098extern void nv04_display_destroy(struct drm_device *);
1099extern void nv04_display_restore(struct drm_device *);
1100
1101/* nv04_crtc.c */
1102extern int nv04_crtc_create(struct drm_device *, int index);
1103
1104/* nouveau_bo.c */
1105extern struct ttm_bo_driver nouveau_bo_driver;
1106extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1107 int size, int align, uint32_t flags,
1108 uint32_t tile_mode, uint32_t tile_flags,
1109 bool no_vm, bool mappable, struct nouveau_bo **);
1110extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1111extern int nouveau_bo_unpin(struct nouveau_bo *);
1112extern int nouveau_bo_map(struct nouveau_bo *);
1113extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1114extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1115 uint32_t busy);
6ee73861
BS		 1116extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1117extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1118extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1119extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1120
1121/* nouveau_fence.c */
1122struct nouveau_fence;
1123extern int nouveau_fence_init(struct nouveau_channel *);
1124extern void nouveau_fence_fini(struct nouveau_channel *);
1125extern void nouveau_fence_update(struct nouveau_channel *);
1126extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1127 bool emit);
1128extern int nouveau_fence_emit(struct nouveau_fence *);
1129struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1130extern bool nouveau_fence_signalled(void *obj, void *arg);
1131extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1132extern int nouveau_fence_flush(void *obj, void *arg);
1133extern void nouveau_fence_unref(void **obj);
1134extern void *nouveau_fence_ref(void *obj);
1135extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1136
1137/* nouveau_gem.c */
1138extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1139 int size, int align, uint32_t flags,
1140 uint32_t tile_mode, uint32_t tile_flags,
1141 bool no_vm, bool mappable, struct nouveau_bo **);
1142extern int nouveau_gem_object_new(struct drm_gem_object *);
1143extern void nouveau_gem_object_del(struct drm_gem_object *);
1144extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1145 struct drm_file *);
1146extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1147 struct drm_file *);
6ee73861
BS		 1148extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1149 struct drm_file *);
1150extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1151 struct drm_file *);
1152extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1153 struct drm_file *);
1154
1155/* nv17_gpio.c */
1156int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1157int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1158
45284162
BS		 1159/* nv50_gpio.c */
1160int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1161int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1162
e9ebb68b
BS		 1163/* nv50_calc. */
1164int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1165 int *N1, int *M1, int *N2, int *M2, int *P);
1166int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1167 int clk, int *N, int *fN, int *M, int *P);
1168
6ee73861
BS		 1169#ifndef ioread32_native
1170#ifdef __BIG_ENDIAN
1171#define ioread16_native ioread16be
1172#define iowrite16_native iowrite16be
1173#define ioread32_native ioread32be
1174#define iowrite32_native iowrite32be
1175#else /* def __BIG_ENDIAN */
1176#define ioread16_native ioread16
1177#define iowrite16_native iowrite16
1178#define ioread32_native ioread32
1179#define iowrite32_native iowrite32
1180#endif /* def __BIG_ENDIAN else */
1181#endif /* !ioread32_native */
1182
1183/* channel control reg access */
1184static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1185{
1186 return ioread32_native(chan->user + reg);
1187}
1188
1189static inline void nvchan_wr32(struct nouveau_channel *chan,
1190 unsigned reg, u32 val)
1191{
1192 iowrite32_native(val, chan->user + reg);
1193}
1194
1195/* register access */
1196static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1197{
1198 struct drm_nouveau_private *dev_priv = dev->dev_private;
1199 return ioread32_native(dev_priv->mmio + reg);
1200}
1201
1202static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1203{
1204 struct drm_nouveau_private *dev_priv = dev->dev_private;
1205 iowrite32_native(val, dev_priv->mmio + reg);
1206}
1207
1208static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1209{
1210 struct drm_nouveau_private *dev_priv = dev->dev_private;
1211 return ioread8(dev_priv->mmio + reg);
1212}
1213
1214static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1215{
1216 struct drm_nouveau_private *dev_priv = dev->dev_private;
1217 iowrite8(val, dev_priv->mmio + reg);
1218}
1219
1220#define nv_wait(reg, mask, val) \
1221 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1222
1223/* PRAMIN access */
1224static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1225{
1226 struct drm_nouveau_private *dev_priv = dev->dev_private;
1227 return ioread32_native(dev_priv->ramin + offset);
1228}
1229
1230static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1231{
1232 struct drm_nouveau_private *dev_priv = dev->dev_private;
1233 iowrite32_native(val, dev_priv->ramin + offset);
1234}
1235
1236/* object access */
1237static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1238 unsigned index)
1239{
1240 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1241}
1242
1243static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1244 unsigned index, u32 val)
1245{
1246 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1247}
1248
1249/*
1250 * Logging
1251 * Argument d is (struct drm_device *).
1252 */
1253#define NV_PRINTK(level, d, fmt, arg...) \
1254 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1255 pci_name(d->pdev), ##arg)
1256#ifndef NV_DEBUG_NOTRACE
1257#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1258 if (drm_debug & DRM_UT_DRIVER) { \
1259 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1260 __LINE__, ##arg); \
1261 } \
1262} while (0)
1263#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1264 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1265 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1266 __LINE__, ##arg); \
1267 } \
1268} while (0)
1269#else
1270#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1271 if (drm_debug & DRM_UT_DRIVER) \
1272 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1273} while (0)
1274#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1275 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1276 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1277} while (0)
1278#endif
1279#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1280#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1281#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1282#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1283#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1284
1285/* nouveau_reg_debug bitmask */
1286enum {
1287 NOUVEAU_REG_DEBUG_MC = 0x1,
1288 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1289 NOUVEAU_REG_DEBUG_FB = 0x4,
1290 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1291 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1292 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1293 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1294 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1295 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1296 NOUVEAU_REG_DEBUG_EVO = 0x200,
1297};
1298
1299#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1300 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1301 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1302} while (0)
1303
1304static inline bool
1305nv_two_heads(struct drm_device *dev)
1306{
1307 struct drm_nouveau_private *dev_priv = dev->dev_private;
1308 const int impl = dev->pci_device & 0x0ff0;
1309
1310 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1311 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1312 return true;
1313
1314 return false;
1315}
1316
1317static inline bool
1318nv_gf4_disp_arch(struct drm_device *dev)
1319{
1320 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1321}
1322
1323static inline bool
1324nv_two_reg_pll(struct drm_device *dev)
1325{
1326 struct drm_nouveau_private *dev_priv = dev->dev_private;
1327 const int impl = dev->pci_device & 0x0ff0;
1328
1329 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1330 return true;
1331 return false;
1332}
1333
f03a314b
FJ		 1334#define NV_SW 0x0000506e
1335#define NV_SW_DMA_SEMAPHORE 0x00000060
1336#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1337#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1338#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1339#define NV_SW_DMA_VBLSEM 0x0000018c
1340#define NV_SW_VBLSEM_OFFSET 0x00000400
1341#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1342#define NV_SW_VBLSEM_RELEASE 0x00000408
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BS		 1343
1344#endif /* __NOUVEAU_DRV_H__ */
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