[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_drv.c

/*
 * Copyright 2005 Stephane Marchesin.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/console.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc_helper.h"
#include "nouveau_drv.h"
#include "nouveau_hw.h"
#include "nouveau_fb.h"
#include "nouveau_fbcon.h"
#include "nv50_display.h"

#include "drm_pciids.h"

MODULE_PARM_DESC(noagp, "Disable AGP");
int nouveau_noagp;
module_param_named(noagp, nouveau_noagp, int, 0400);

MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
static int nouveau_modeset = -1; /* kms */
module_param_named(modeset, nouveau_modeset, int, 0400);

MODULE_PARM_DESC(vbios, "Override default VBIOS location");
char *nouveau_vbios;
module_param_named(vbios, nouveau_vbios, charp, 0400);

MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
int nouveau_vram_pushbuf;
module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);

MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
int nouveau_vram_notify = 0;
module_param_named(vram_notify, nouveau_vram_notify, int, 0400);

MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
int nouveau_duallink = 1;
module_param_named(duallink, nouveau_duallink, int, 0400);

MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
int nouveau_uscript_lvds = -1;
module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);

MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
int nouveau_uscript_tmds = -1;
module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);

MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
int nouveau_ignorelid = 0;
module_param_named(ignorelid, nouveau_ignorelid, int, 0400);

MODULE_PARM_DESC(noaccel, "Disable all acceleration");
int nouveau_noaccel = 0;
module_param_named(noaccel, nouveau_noaccel, int, 0400);

MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
int nouveau_nofbaccel = 0;
module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);

MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
int nouveau_override_conntype = 0;
module_param_named(override_conntype, nouveau_override_conntype, int, 0400);

MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
int nouveau_tv_disable = 0;
module_param_named(tv_disable, nouveau_tv_disable, int, 0400);

MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
		 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
		 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
		 "\t\tDefault: PAL\n"
		 "\t\t*NOTE* Ignored for cards with external TV encoders.");
char *nouveau_tv_norm;
module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);

MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
		"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
		"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
		"\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
int nouveau_reg_debug;
module_param_named(reg_debug, nouveau_reg_debug, int, 0600);

int nouveau_fbpercrtc;
#if 0
module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
#endif

static struct pci_device_id pciidlist[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{}
};

MODULE_DEVICE_TABLE(pci, pciidlist);

static struct drm_driver driver;

static int __devinit
nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	return drm_get_pci_dev(pdev, ent, &driver);
}

static void
nouveau_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

int
nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_channel *chan;
	struct drm_crtc *crtc;
	int ret, i;

	if (pm_state.event == PM_EVENT_PRETHAW)
		return 0;

	NV_INFO(dev, "Disabling fbcon acceleration...\n");
	nouveau_fbcon_save_disable_accel(dev);

	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_unpin(nouveau_fb->nvbo);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nouveau_bo_unmap(nv_crtc->cursor.nvbo);
		nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	}

	NV_INFO(dev, "Evicting buffers...\n");
	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);

	NV_INFO(dev, "Idling channels...\n");
	for (i = 0; i < pfifo->channels; i++) {
		struct nouveau_fence *fence = NULL;

		chan = dev_priv->fifos[i];
		if (!chan || (dev_priv->card_type >= NV_50 &&
			      chan == dev_priv->fifos[0]))
			continue;

		ret = nouveau_fence_new(chan, &fence, true);
		if (ret == 0) {
			ret = nouveau_fence_wait(fence, NULL, false, false);
			nouveau_fence_unref((void *)&fence);
		}

		if (ret) {
			NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
				 chan->id);
		}
	}

	pgraph->fifo_access(dev, false);
	nouveau_wait_for_idle(dev);
	pfifo->reassign(dev, false);
	pfifo->disable(dev);
	pfifo->unload_context(dev);
	pgraph->unload_context(dev);

	NV_INFO(dev, "Suspending GPU objects...\n");
	ret = nouveau_gpuobj_suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		goto out_abort;
	}

	ret = pinstmem->suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		nouveau_gpuobj_suspend_cleanup(dev);
		goto out_abort;
	}

	NV_INFO(dev, "And we're gone!\n");
	pci_save_state(pdev);
	if (pm_state.event == PM_EVENT_SUSPEND) {
		pci_disable_device(pdev);
		pci_set_power_state(pdev, PCI_D3hot);
	}

	acquire_console_sem();
	nouveau_fbcon_set_suspend(dev, 1);
	release_console_sem();
	nouveau_fbcon_restore_accel(dev);
	return 0;

out_abort:
	NV_INFO(dev, "Re-enabling acceleration..\n");
	pfifo->enable(dev);
	pfifo->reassign(dev, true);
	pgraph->fifo_access(dev, true);
	return ret;
}

int
nouveau_pci_resume(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	struct drm_crtc *crtc;
	int ret, i;

	nouveau_fbcon_save_disable_accel(dev);

	NV_INFO(dev, "We're back, enabling device...\n");
	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	if (pci_enable_device(pdev))
		return -1;
	pci_set_master(dev->pdev);

	/* Make sure the AGP controller is in a consistent state */
	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
		nouveau_mem_reset_agp(dev);

	NV_INFO(dev, "POSTing device...\n");
	ret = nouveau_run_vbios_init(dev);
	if (ret)
		return ret;

	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
		ret = nouveau_mem_init_agp(dev);
		if (ret) {
			NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "Reinitialising engines...\n");
	engine->instmem.resume(dev);
	engine->mc.init(dev);
	engine->timer.init(dev);
	engine->fb.init(dev);
	engine->graph.init(dev);
	engine->fifo.init(dev);

	NV_INFO(dev, "Restoring GPU objects...\n");
	nouveau_gpuobj_resume(dev);

	nouveau_irq_postinstall(dev);

	/* Re-write SKIPS, they'll have been lost over the suspend */
	if (nouveau_vram_pushbuf) {
		struct nouveau_channel *chan;
		int j;

		for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
			chan = dev_priv->fifos[i];
			if (!chan || !chan->pushbuf_bo)
				continue;

			for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
				nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
		}
	}

	NV_INFO(dev, "Restoring mode...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
		if (!ret)
			ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
		if (ret)
			NV_ERROR(dev, "Could not pin/map cursor.\n");
	}

	if (dev_priv->card_type < NV_50)
		nv04_display_restore(dev);
	else
		nv50_display_init(dev);

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nv_crtc->cursor.set_offset(nv_crtc,
					nv_crtc->cursor.nvbo->bo.offset -
					dev_priv->vm_vram_base);

		nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
			nv_crtc->cursor_saved_y);
	}

	/* Force CLUT to get re-loaded during modeset */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nv_crtc->lut.depth = 0;
	}

	acquire_console_sem();
	nouveau_fbcon_set_suspend(dev, 0);
	release_console_sem();

	nouveau_fbcon_zfill_all(dev);

	drm_helper_resume_force_mode(dev);

	nouveau_fbcon_restore_accel(dev);
	return 0;
}

static struct drm_driver driver = {
	.driver_features =
		DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
		DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
		DRIVER_MODESET,
	.load = nouveau_load,
	.firstopen = nouveau_firstopen,
	.lastclose = nouveau_lastclose,
	.unload = nouveau_unload,
	.preclose = nouveau_preclose,
#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	.debugfs_init = nouveau_debugfs_init,
	.debugfs_cleanup = nouveau_debugfs_takedown,
#endif
	.irq_preinstall = nouveau_irq_preinstall,
	.irq_postinstall = nouveau_irq_postinstall,
	.irq_uninstall = nouveau_irq_uninstall,
	.irq_handler = nouveau_irq_handler,
	.reclaim_buffers = drm_core_reclaim_buffers,
	.get_map_ofs = drm_core_get_map_ofs,
	.get_reg_ofs = drm_core_get_reg_ofs,
	.ioctls = nouveau_ioctls,
	.fops = {
		.owner = THIS_MODULE,
		.open = drm_open,
		.release = drm_release,
		.unlocked_ioctl = drm_ioctl,
		.mmap = nouveau_ttm_mmap,
		.poll = drm_poll,
		.fasync = drm_fasync,
#if defined(CONFIG_COMPAT)
		.compat_ioctl = nouveau_compat_ioctl,
#endif
	},
	.pci_driver = {
		.name = DRIVER_NAME,
		.id_table = pciidlist,
		.probe = nouveau_pci_probe,
		.remove = nouveau_pci_remove,
		.suspend = nouveau_pci_suspend,
		.resume = nouveau_pci_resume
	},

	.gem_init_object = nouveau_gem_object_new,
	.gem_free_object = nouveau_gem_object_del,

	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
#ifdef GIT_REVISION
	.date = GIT_REVISION,
#else
	.date = DRIVER_DATE,
#endif
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
};

static int __init nouveau_init(void)
{
	driver.num_ioctls = nouveau_max_ioctl;

	if (nouveau_modeset == -1) {
#ifdef CONFIG_VGA_CONSOLE
		if (vgacon_text_force())
			nouveau_modeset = 0;
		else
#endif
			nouveau_modeset = 1;
	}

	if (!nouveau_modeset)
		return 0;

	nouveau_register_dsm_handler();
	return drm_init(&driver);
}

static void __exit nouveau_exit(void)
{
	if (!nouveau_modeset)
		return;

	drm_exit(&driver);
	nouveau_unregister_dsm_handler();
}

module_init(nouveau_init);
module_exit(nouveau_exit);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include <linux/console.h>
	26
	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "drm_crtc_helper.h"
	30	#include "nouveau_drv.h"
	31	#include "nouveau_hw.h"
	32	#include "nouveau_fb.h"
	33	#include "nouveau_fbcon.h"
	34	#include "nv50_display.h"
	35
	36	#include "drm_pciids.h"
	37
	38	MODULE_PARM_DESC(noagp, "Disable AGP");
	39	int nouveau_noagp;
	40	module_param_named(noagp, nouveau_noagp, int, 0400);
	41
	42	MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
	43	static int nouveau_modeset = -1; /* kms */
	44	module_param_named(modeset, nouveau_modeset, int, 0400);
	45
	46	MODULE_PARM_DESC(vbios, "Override default VBIOS location");
	47	char *nouveau_vbios;
	48	module_param_named(vbios, nouveau_vbios, charp, 0400);
	49
	50	MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
	51	int nouveau_vram_pushbuf;
	52	module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
	53
	54	MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
2dfe36b1	55	int nouveau_vram_notify = 0;
6ee73861 BS	56	module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
	57
	58	MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
	59	int nouveau_duallink = 1;
	60	module_param_named(duallink, nouveau_duallink, int, 0400);
	61
	62	MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
	63	int nouveau_uscript_lvds = -1;
	64	module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
	65
	66	MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
	67	int nouveau_uscript_tmds = -1;
	68	module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
	69
a1470890 BS	70	MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
	71	int nouveau_ignorelid = 0;
	72	module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
	73
81e2d422	74	MODULE_PARM_DESC(noaccel, "Disable all acceleration");
a32ed69d MK	75	int nouveau_noaccel = 0;
	76	module_param_named(noaccel, nouveau_noaccel, int, 0400);
	77
81e2d422	78	MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
a32ed69d MK	79	int nouveau_nofbaccel = 0;
	80	module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
	81
da647d5b BS	82	MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
	83	int nouveau_override_conntype = 0;
	84	module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
	85
f4053509 BS	86	MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
	87	int nouveau_tv_disable = 0;
	88	module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
	89
6ee73861 BS	90	MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
	91	"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
	92	"\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
	93	"\t\tDefault: PAL\n"
	94	"\t\tNOTE Ignored for cards with external TV encoders.");
	95	char *nouveau_tv_norm;
	96	module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
	97
	98	MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
	99	"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
	100	"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
	101	"\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
	102	int nouveau_reg_debug;
	103	module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
	104
	105	int nouveau_fbpercrtc;
	106	#if 0
	107	module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
	108	#endif
	109
	110	static struct pci_device_id pciidlist[] = {
	111	{
	112	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
	113	.class = PCI_BASE_CLASS_DISPLAY << 16,
	114	.class_mask = 0xff << 16,
	115	},
	116	{
	117	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
	118	.class = PCI_BASE_CLASS_DISPLAY << 16,
	119	.class_mask = 0xff << 16,
	120	},
	121	{}
	122	};
	123
	124	MODULE_DEVICE_TABLE(pci, pciidlist);
	125
	126	static struct drm_driver driver;
	127
	128	static int __devinit
	129	nouveau_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	130	{
dcdb1674	131	return drm_get_pci_dev(pdev, ent, &driver);
6ee73861 BS	132	}
	133
	134	static void
	135	nouveau_pci_remove(struct pci_dev *pdev)
	136	{
	137	struct drm_device *dev = pci_get_drvdata(pdev);
	138
	139	drm_put_dev(dev);
	140	}
	141
6a9ee8af	142	int
6ee73861 BS	143	nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
	144	{
	145	struct drm_device *dev = pci_get_drvdata(pdev);
	146	struct drm_nouveau_private *dev_priv = dev->dev_private;
	147	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	148	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	149	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	150	struct nouveau_channel *chan;
	151	struct drm_crtc *crtc;
6ee73861 BS	152	int ret, i;
6ee73861 BS	153
6ee73861 BS	154	if (pm_state.event == PM_EVENT_PRETHAW)
	155	return 0;
	156
81441570	157	NV_INFO(dev, "Disabling fbcon acceleration...\n");
38651674	158	nouveau_fbcon_save_disable_accel(dev);
6ee73861	159
81441570	160	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
6ee73861 BS	161	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	162	struct nouveau_framebuffer *nouveau_fb;
	163
	164	nouveau_fb = nouveau_framebuffer(crtc->fb);
	165	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	166	continue;
	167
	168	nouveau_bo_unpin(nouveau_fb->nvbo);
	169	}
	170
b334f2b3 MM	171	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	172	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	173
	174	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
	175	nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	176	}
	177
6ee73861 BS	178	NV_INFO(dev, "Evicting buffers...\n");
	179	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
	180
	181	NV_INFO(dev, "Idling channels...\n");
	182	for (i = 0; i < pfifo->channels; i++) {
	183	struct nouveau_fence *fence = NULL;
	184
	185	chan = dev_priv->fifos[i];
	186	if (!chan \|\| (dev_priv->card_type >= NV_50 &&
	187	chan == dev_priv->fifos[0]))
	188	continue;
	189
	190	ret = nouveau_fence_new(chan, &fence, true);
	191	if (ret == 0) {
	192	ret = nouveau_fence_wait(fence, NULL, false, false);
	193	nouveau_fence_unref((void *)&fence);
	194	}
	195
	196	if (ret) {
	197	NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
	198	chan->id);
	199	}
	200	}
	201
	202	pgraph->fifo_access(dev, false);
	203	nouveau_wait_for_idle(dev);
	204	pfifo->reassign(dev, false);
	205	pfifo->disable(dev);
	206	pfifo->unload_context(dev);
	207	pgraph->unload_context(dev);
	208
	209	NV_INFO(dev, "Suspending GPU objects...\n");
	210	ret = nouveau_gpuobj_suspend(dev);
	211	if (ret) {
	212	NV_ERROR(dev, "... failed: %d\n", ret);
	213	goto out_abort;
	214	}
	215
	216	ret = pinstmem->suspend(dev);
	217	if (ret) {
	218	NV_ERROR(dev, "... failed: %d\n", ret);
	219	nouveau_gpuobj_suspend_cleanup(dev);
	220	goto out_abort;
	221	}
	222
	223	NV_INFO(dev, "And we're gone!\n");
	224	pci_save_state(pdev);
	225	if (pm_state.event == PM_EVENT_SUSPEND) {
	226	pci_disable_device(pdev);
	227	pci_set_power_state(pdev, PCI_D3hot);
	228	}
	229
	230	acquire_console_sem();
38651674	231	nouveau_fbcon_set_suspend(dev, 1);
6ee73861	232	release_console_sem();
38651674	233	nouveau_fbcon_restore_accel(dev);
6ee73861 BS	234	return 0;
	235
	236	out_abort:
	237	NV_INFO(dev, "Re-enabling acceleration..\n");
	238	pfifo->enable(dev);
	239	pfifo->reassign(dev, true);
	240	pgraph->fifo_access(dev, true);
	241	return ret;
	242	}
	243
6a9ee8af	244	int
6ee73861 BS	245	nouveau_pci_resume(struct pci_dev *pdev)
	246	{
	247	struct drm_device *dev = pci_get_drvdata(pdev);
	248	struct drm_nouveau_private *dev_priv = dev->dev_private;
	249	struct nouveau_engine *engine = &dev_priv->engine;
	250	struct drm_crtc *crtc;
6ee73861 BS	251	int ret, i;
6ee73861 BS	252
38651674	253	nouveau_fbcon_save_disable_accel(dev);
6ee73861 BS	254
	255	NV_INFO(dev, "We're back, enabling device...\n");
	256	pci_set_power_state(pdev, PCI_D0);
	257	pci_restore_state(pdev);
	258	if (pci_enable_device(pdev))
	259	return -1;
	260	pci_set_master(dev->pdev);
	261
e04d8e82 FJ	262	/* Make sure the AGP controller is in a consistent state */
	263	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
	264	nouveau_mem_reset_agp(dev);
	265
6ee73861 BS	266	NV_INFO(dev, "POSTing device...\n");
	267	ret = nouveau_run_vbios_init(dev);
	268	if (ret)
	269	return ret;
	270
	271	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
	272	ret = nouveau_mem_init_agp(dev);
	273	if (ret) {
	274	NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
	275	return ret;
	276	}
	277	}
	278
	279	NV_INFO(dev, "Reinitialising engines...\n");
	280	engine->instmem.resume(dev);
	281	engine->mc.init(dev);
	282	engine->timer.init(dev);
	283	engine->fb.init(dev);
	284	engine->graph.init(dev);
	285	engine->fifo.init(dev);
	286
	287	NV_INFO(dev, "Restoring GPU objects...\n");
	288	nouveau_gpuobj_resume(dev);
	289
	290	nouveau_irq_postinstall(dev);
	291
	292	/* Re-write SKIPS, they'll have been lost over the suspend */
	293	if (nouveau_vram_pushbuf) {
	294	struct nouveau_channel *chan;
	295	int j;
	296
	297	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
	298	chan = dev_priv->fifos[i];
3c8868d3	299	if (!chan \|\| !chan->pushbuf_bo)
6ee73861 BS	300	continue;
	301
	302	for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
	303	nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
	304	}
	305	}
	306
	307	NV_INFO(dev, "Restoring mode...\n");
	308	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	309	struct nouveau_framebuffer *nouveau_fb;
	310
	311	nouveau_fb = nouveau_framebuffer(crtc->fb);
	312	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	313	continue;
	314
	315	nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	316	}
	317
b334f2b3 MM	318	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
b334f2b3 MM	319	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
b334f2b3 MM	320
	321	ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
	322	if (!ret)
	323	ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
	324	if (ret)
	325	NV_ERROR(dev, "Could not pin/map cursor.\n");
	326	}
	327
03cd06ca	328	if (dev_priv->card_type < NV_50)
6ee73861	329	nv04_display_restore(dev);
03cd06ca	330	else
6ee73861 BS	331	nv50_display_init(dev);
6ee73861 BS	332
b334f2b3 MM	333	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	334	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	335
	336	nv_crtc->cursor.set_offset(nv_crtc,
	337	nv_crtc->cursor.nvbo->bo.offset -
	338	dev_priv->vm_vram_base);
	339
	340	nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
	341	nv_crtc->cursor_saved_y);
	342	}
	343
6ee73861 BS	344	/* Force CLUT to get re-loaded during modeset */
	345	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	346	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	347
	348	nv_crtc->lut.depth = 0;
	349	}
	350
	351	acquire_console_sem();
38651674	352	nouveau_fbcon_set_suspend(dev, 0);
6ee73861 BS	353	release_console_sem();
6ee73861 BS	354
38651674	355	nouveau_fbcon_zfill_all(dev);
6ee73861 BS	356
6ee73861 BS	357	drm_helper_resume_force_mode(dev);
38651674 DA	358
38651674 DA	359	nouveau_fbcon_restore_accel(dev);
6ee73861 BS	360	return 0;
	361	}
	362
	363	static struct drm_driver driver = {
	364	.driver_features =
	365	DRIVER_USE_AGP \| DRIVER_PCI_DMA \| DRIVER_SG \|
cd0b072f BS	366	DRIVER_HAVE_IRQ \| DRIVER_IRQ_SHARED \| DRIVER_GEM \|
cd0b072f BS	367	DRIVER_MODESET,
6ee73861 BS	368	.load = nouveau_load,
	369	.firstopen = nouveau_firstopen,
	370	.lastclose = nouveau_lastclose,
	371	.unload = nouveau_unload,
	372	.preclose = nouveau_preclose,
	373	#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	374	.debugfs_init = nouveau_debugfs_init,
	375	.debugfs_cleanup = nouveau_debugfs_takedown,
	376	#endif
	377	.irq_preinstall = nouveau_irq_preinstall,
	378	.irq_postinstall = nouveau_irq_postinstall,
	379	.irq_uninstall = nouveau_irq_uninstall,
	380	.irq_handler = nouveau_irq_handler,
	381	.reclaim_buffers = drm_core_reclaim_buffers,
	382	.get_map_ofs = drm_core_get_map_ofs,
	383	.get_reg_ofs = drm_core_get_reg_ofs,
	384	.ioctls = nouveau_ioctls,
	385	.fops = {
	386	.owner = THIS_MODULE,
	387	.open = drm_open,
	388	.release = drm_release,
ed8b6704	389	.unlocked_ioctl = drm_ioctl,
6ee73861 BS	390	.mmap = nouveau_ttm_mmap,
	391	.poll = drm_poll,
	392	.fasync = drm_fasync,
	393	#if defined(CONFIG_COMPAT)
	394	.compat_ioctl = nouveau_compat_ioctl,
	395	#endif
	396	},
	397	.pci_driver = {
	398	.name = DRIVER_NAME,
	399	.id_table = pciidlist,
	400	.probe = nouveau_pci_probe,
	401	.remove = nouveau_pci_remove,
	402	.suspend = nouveau_pci_suspend,
	403	.resume = nouveau_pci_resume
	404	},
	405
	406	.gem_init_object = nouveau_gem_object_new,
	407	.gem_free_object = nouveau_gem_object_del,
	408
	409	.name = DRIVER_NAME,
	410	.desc = DRIVER_DESC,
	411	#ifdef GIT_REVISION
	412	.date = GIT_REVISION,
	413	#else
	414	.date = DRIVER_DATE,
	415	#endif
	416	.major = DRIVER_MAJOR,
	417	.minor = DRIVER_MINOR,
	418	.patchlevel = DRIVER_PATCHLEVEL,
	419	};
	420
	421	static int __init nouveau_init(void)
	422	{
	423	driver.num_ioctls = nouveau_max_ioctl;
	424
	425	if (nouveau_modeset == -1) {
	426	#ifdef CONFIG_VGA_CONSOLE
	427	if (vgacon_text_force())
	428	nouveau_modeset = 0;
	429	else
	430	#endif
	431	nouveau_modeset = 1;
	432	}
	433
cd0b072f BS	434	if (!nouveau_modeset)
cd0b072f BS	435	return 0;
6ee73861	436
cd0b072f	437	nouveau_register_dsm_handler();
6ee73861 BS	438	return drm_init(&driver);
	439	}
	440
	441	static void __exit nouveau_exit(void)
	442	{
cd0b072f BS	443	if (!nouveau_modeset)
	444	return;
	445
6ee73861	446	drm_exit(&driver);
6a9ee8af	447	nouveau_unregister_dsm_handler();
6ee73861 BS	448	}
	449
	450	module_init(nouveau_init);
	451	module_exit(nouveau_exit);
	452
	453	MODULE_AUTHOR(DRIVER_AUTHOR);
	454	MODULE_DESCRIPTION(DRIVER_DESC);
	455	MODULE_LICENSE("GPL and additional rights");