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drm/nouveau: ensure we've parsed i2c table entry for INIT_*I2C* handlers
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861
BS		 30
31/* these defines are made up */
32#define NV_CIO_CRE_44_HEADA 0x0
33#define NV_CIO_CRE_44_HEADB 0x3
34#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
35#define LEGACY_I2C_CRT 0x80
36#define LEGACY_I2C_PANEL 0x81
37#define LEGACY_I2C_TV 0x82
38
39#define EDID1_LEN 128
40
41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42#define LOG_OLD_VALUE(x)
43
44#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
45#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
46
47struct init_exec {
48 bool execute;
49 bool repeat;
50};
51
52static bool nv_cksum(const uint8_t *data, unsigned int length)
53{
54 /*
55 * There's a few checksums in the BIOS, so here's a generic checking
56 * function.
57 */
58 int i;
59 uint8_t sum = 0;
60
61 for (i = 0; i < length; i++)
62 sum += data[i];
63
64 if (sum)
65 return true;
66
67 return false;
68}
69
70static int
71score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
72{
73 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
74 NV_TRACEWARN(dev, "... BIOS signature not found\n");
75 return 0;
76 }
77
78 if (nv_cksum(data, data[2] * 512)) {
79 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
80 /* if a ro image is somewhat bad, it's probably all rubbish */
81 return writeable ? 2 : 1;
82 } else
83 NV_TRACE(dev, "... appears to be valid\n");
84
85 return 3;
86}
87
88static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
89{
90 struct drm_nouveau_private *dev_priv = dev->dev_private;
91 uint32_t pci_nv_20, save_pci_nv_20;
92 int pcir_ptr;
93 int i;
94
95 if (dev_priv->card_type >= NV_50)
96 pci_nv_20 = 0x88050;
97 else
98 pci_nv_20 = NV_PBUS_PCI_NV_20;
99
100 /* enable ROM access */
101 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
102 nvWriteMC(dev, pci_nv_20,
103 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
104
105 /* bail if no rom signature */
106 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
107 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
108 goto out;
109
110 /* additional check (see note below) - read PCI record header */
111 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
112 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
113 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
117 goto out;
118
119 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
120 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
121 * each byte. we'll hope pramin has something usable instead
122 */
123 for (i = 0; i < NV_PROM_SIZE; i++)
124 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
125
126out:
127 /* disable ROM access */
128 nvWriteMC(dev, pci_nv_20,
129 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
130}
131
132static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
133{
134 struct drm_nouveau_private *dev_priv = dev->dev_private;
135 uint32_t old_bar0_pramin = 0;
136 int i;
137
138 if (dev_priv->card_type >= NV_50) {
139 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
140
141 if (!vbios_vram)
142 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
143
144 old_bar0_pramin = nv_rd32(dev, 0x1700);
145 nv_wr32(dev, 0x1700, vbios_vram >> 16);
146 }
147
148 /* bail if no rom signature */
149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
151 goto out;
152
153 for (i = 0; i < NV_PROM_SIZE; i++)
154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
155
156out:
157 if (dev_priv->card_type >= NV_50)
158 nv_wr32(dev, 0x1700, old_bar0_pramin);
159}
160
161static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
162{
163 void __iomem *rom = NULL;
164 size_t rom_len;
165 int ret;
166
167 ret = pci_enable_rom(dev->pdev);
168 if (ret)
169 return;
170
171 rom = pci_map_rom(dev->pdev, &rom_len);
172 if (!rom)
173 goto out;
174 memcpy_fromio(data, rom, rom_len);
175 pci_unmap_rom(dev->pdev, rom);
176
177out:
178 pci_disable_rom(dev->pdev);
179}
180
181struct methods {
182 const char desc[8];
183 void (*loadbios)(struct drm_device *, uint8_t *);
184 const bool rw;
6ee73861
BS		 185};
186
187static struct methods nv04_methods[] = {
188 { "PROM", load_vbios_prom, false },
189 { "PRAMIN", load_vbios_pramin, true },
190 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 191};
192
193static struct methods nv50_methods[] = {
194 { "PRAMIN", load_vbios_pramin, true },
195 { "PROM", load_vbios_prom, false },
196 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 197};
198
657b6245
MK		 199#define METHODCNT 3
200
6ee73861
BS		 201static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
202{
203 struct drm_nouveau_private *dev_priv = dev->dev_private;
657b6245
MK		 204 struct methods *methods;
205 int i;
6ee73861 206 int testscore = 3;
657b6245 207 int scores[METHODCNT];
6ee73861
BS		 208
209 if (nouveau_vbios) {
657b6245
MK		 210 methods = nv04_methods;
211 for (i = 0; i < METHODCNT; i++)
212 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 213 break;
6ee73861 214
657b6245 215 if (i < METHODCNT) {
6ee73861 216 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 217 methods[i].desc);
6ee73861 218
657b6245
MK		 219 methods[i].loadbios(dev, data);
220 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 221 return true;
222 }
223
224 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
225 }
226
227 if (dev_priv->card_type < NV_50)
228 methods = nv04_methods;
229 else
230 methods = nv50_methods;
231
657b6245 232 for (i = 0; i < METHODCNT; i++) {
6ee73861 233 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 234 methods[i].desc);
6ee73861 235 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 236 methods[i].loadbios(dev, data);
237 scores[i] = score_vbios(dev, data, methods[i].rw);
238 if (scores[i] == testscore)
6ee73861 239 return true;
6ee73861
BS		 240 }
241
242 while (--testscore > 0) {
657b6245
MK		 243 for (i = 0; i < METHODCNT; i++) {
244 if (scores[i] == testscore) {
6ee73861 245 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 246 methods[i].desc);
247 methods[i].loadbios(dev, data);
6ee73861
BS		 248 return true;
249 }
6ee73861
BS		 250 }
251 }
252
253 NV_ERROR(dev, "No valid BIOS image found\n");
254 return false;
255}
256
257struct init_tbl_entry {
258 char *name;
259 uint8_t id;
9170a824
BS		 260 /* Return:
261 * > 0: success, length of opcode
262 * 0: success, but abort further parsing of table (INIT_DONE etc)
263 * < 0: failure, table parsing will be aborted
264 */
37383650 265 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 266};
267
268struct bit_entry {
269 uint8_t id[2];
270 uint16_t length;
271 uint16_t offset;
272};
273
274static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
275
276#define MACRO_INDEX_SIZE 2
277#define MACRO_SIZE 8
278#define CONDITION_SIZE 12
279#define IO_FLAG_CONDITION_SIZE 9
280#define IO_CONDITION_SIZE 5
281#define MEM_INIT_SIZE 66
282
283static void still_alive(void)
284{
285#if 0
286 sync();
287 msleep(2);
288#endif
289}
290
291static uint32_t
292munge_reg(struct nvbios *bios, uint32_t reg)
293{
294 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
295 struct dcb_entry *dcbent = bios->display.output;
296
297 if (dev_priv->card_type < NV_50)
298 return reg;
299
300 if (reg & 0x40000000) {
301 BUG_ON(!dcbent);
302
303 reg += (ffs(dcbent->or) - 1) * 0x800;
304 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
305 reg += 0x00000080;
306 }
307
308 reg &= ~0x60000000;
309 return reg;
310}
311
312static int
313valid_reg(struct nvbios *bios, uint32_t reg)
314{
315 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
316 struct drm_device *dev = bios->dev;
317
318 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 319 if (reg & 0x2 ||
04a39c57 320 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 321 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
322
323 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 324 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 325 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
326 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
327 reg);
328
9855e584
BS		 329 if (reg >= (8*1024*1024)) {
330 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
331 return 0;
6ee73861 332 }
9855e584
BS		 333
334 return 1;
6ee73861
BS		 335}
336
337static bool
338valid_idx_port(struct nvbios *bios, uint16_t port)
339{
340 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
341 struct drm_device *dev = bios->dev;
342
343 /*
344 * If adding more ports here, the read/write functions below will need
345 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
346 * used for the port in question
347 */
348 if (dev_priv->card_type < NV_50) {
349 if (port == NV_CIO_CRX__COLOR)
350 return true;
351 if (port == NV_VIO_SRX)
352 return true;
353 } else {
354 if (port == NV_CIO_CRX__COLOR)
355 return true;
356 }
357
358 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
359 port);
360
361 return false;
362}
363
364static bool
365valid_port(struct nvbios *bios, uint16_t port)
366{
367 struct drm_device *dev = bios->dev;
368
369 /*
370 * If adding more ports here, the read/write functions below will need
371 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
372 * used for the port in question
373 */
374 if (port == NV_VIO_VSE2)
375 return true;
376
377 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
378
379 return false;
380}
381
382static uint32_t
383bios_rd32(struct nvbios *bios, uint32_t reg)
384{
385 uint32_t data;
386
387 reg = munge_reg(bios, reg);
388 if (!valid_reg(bios, reg))
389 return 0;
390
391 /*
392 * C51 sometimes uses regs with bit0 set in the address. For these
393 * cases there should exist a translation in a BIOS table to an IO
394 * port address which the BIOS uses for accessing the reg
395 *
396 * These only seem to appear for the power control regs to a flat panel,
397 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
398 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
399 * suspend-resume mmio trace from a C51 will be required to see if this
400 * is true for the power microcode in 0x14.., or whether the direct IO
401 * port access method is needed
402 */
403 if (reg & 0x1)
404 reg &= ~0x1;
405
406 data = nv_rd32(bios->dev, reg);
407
408 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
409
410 return data;
411}
412
413static void
414bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
415{
416 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
417
418 reg = munge_reg(bios, reg);
419 if (!valid_reg(bios, reg))
420 return;
421
422 /* see note in bios_rd32 */
423 if (reg & 0x1)
424 reg &= 0xfffffffe;
425
426 LOG_OLD_VALUE(bios_rd32(bios, reg));
427 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
428
04a39c57 429 if (dev_priv->vbios.execute) {
6ee73861
BS		 430 still_alive();
431 nv_wr32(bios->dev, reg, data);
432 }
433}
434
435static uint8_t
436bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
437{
438 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
439 struct drm_device *dev = bios->dev;
440 uint8_t data;
441
442 if (!valid_idx_port(bios, port))
443 return 0;
444
445 if (dev_priv->card_type < NV_50) {
446 if (port == NV_VIO_SRX)
447 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
448 else /* assume NV_CIO_CRX__COLOR */
449 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
450 } else {
451 uint32_t data32;
452
453 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
454 data = (data32 >> ((index & 3) << 3)) & 0xff;
455 }
456
457 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
458 "Head: 0x%02X, Data: 0x%02X\n",
459 port, index, bios->state.crtchead, data);
460 return data;
461}
462
463static void
464bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
465{
466 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
467 struct drm_device *dev = bios->dev;
468
469 if (!valid_idx_port(bios, port))
470 return;
471
472 /*
473 * The current head is maintained in the nvbios member state.crtchead.
474 * We trap changes to CR44 and update the head variable and hence the
475 * register set written.
476 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
477 * of the write, and to head1 after the write
478 */
479 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
480 data != NV_CIO_CRE_44_HEADB)
481 bios->state.crtchead = 0;
482
483 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
484 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
485 "Head: 0x%02X, Data: 0x%02X\n",
486 port, index, bios->state.crtchead, data);
487
488 if (bios->execute && dev_priv->card_type < NV_50) {
489 still_alive();
490 if (port == NV_VIO_SRX)
491 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
492 else /* assume NV_CIO_CRX__COLOR */
493 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
494 } else
495 if (bios->execute) {
496 uint32_t data32, shift = (index & 3) << 3;
497
498 still_alive();
499
500 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
501 data32 &= ~(0xff << shift);
502 data32 |= (data << shift);
503 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
504 }
505
506 if (port == NV_CIO_CRX__COLOR &&
507 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
508 bios->state.crtchead = 1;
509}
510
511static uint8_t
512bios_port_rd(struct nvbios *bios, uint16_t port)
513{
514 uint8_t data, head = bios->state.crtchead;
515
516 if (!valid_port(bios, port))
517 return 0;
518
519 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
520
521 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
522 port, head, data);
523
524 return data;
525}
526
527static void
528bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
529{
530 int head = bios->state.crtchead;
531
532 if (!valid_port(bios, port))
533 return;
534
535 LOG_OLD_VALUE(bios_port_rd(bios, port));
536 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
537 port, head, data);
538
539 if (!bios->execute)
540 return;
541
542 still_alive();
543 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
544}
545
546static bool
547io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
548{
549 /*
550 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
551 * for the CRTC index; 1 byte for the mask to apply to the value
552 * retrieved from the CRTC; 1 byte for the shift right to apply to the
553 * masked CRTC value; 2 bytes for the offset to the flag array, to
554 * which the shifted value is added; 1 byte for the mask applied to the
555 * value read from the flag array; and 1 byte for the value to compare
556 * against the masked byte from the flag table.
557 */
558
559 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
560 uint16_t crtcport = ROM16(bios->data[condptr]);
561 uint8_t crtcindex = bios->data[condptr + 2];
562 uint8_t mask = bios->data[condptr + 3];
563 uint8_t shift = bios->data[condptr + 4];
564 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
565 uint8_t flagarraymask = bios->data[condptr + 7];
566 uint8_t cmpval = bios->data[condptr + 8];
567 uint8_t data;
568
569 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
570 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
571 "Cmpval: 0x%02X\n",
572 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
573
574 data = bios_idxprt_rd(bios, crtcport, crtcindex);
575
576 data = bios->data[flagarray + ((data & mask) >> shift)];
577 data &= flagarraymask;
578
579 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
580 offset, data, cmpval);
581
582 return (data == cmpval);
583}
584
585static bool
586bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
587{
588 /*
589 * The condition table entry has 4 bytes for the address of the
590 * register to check, 4 bytes for a mask to apply to the register and
591 * 4 for a test comparison value
592 */
593
594 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
595 uint32_t reg = ROM32(bios->data[condptr]);
596 uint32_t mask = ROM32(bios->data[condptr + 4]);
597 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
598 uint32_t data;
599
600 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
601 offset, cond, reg, mask);
602
603 data = bios_rd32(bios, reg) & mask;
604
605 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
606 offset, data, cmpval);
607
608 return (data == cmpval);
609}
610
611static bool
612io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
613{
614 /*
615 * The IO condition entry has 2 bytes for the IO port address; 1 byte
616 * for the index to write to io_port; 1 byte for the mask to apply to
617 * the byte read from io_port+1; and 1 byte for the value to compare
618 * against the masked byte.
619 */
620
621 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
622 uint16_t io_port = ROM16(bios->data[condptr]);
623 uint8_t port_index = bios->data[condptr + 2];
624 uint8_t mask = bios->data[condptr + 3];
625 uint8_t cmpval = bios->data[condptr + 4];
626
627 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
628
629 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
630 offset, data, cmpval);
631
632 return (data == cmpval);
633}
634
635static int
636nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
637{
638 struct drm_nouveau_private *dev_priv = dev->dev_private;
639 uint32_t reg0 = nv_rd32(dev, reg + 0);
640 uint32_t reg1 = nv_rd32(dev, reg + 4);
641 struct nouveau_pll_vals pll;
642 struct pll_lims pll_limits;
643 int ret;
644
645 ret = get_pll_limits(dev, reg, &pll_limits);
646 if (ret)
647 return ret;
648
649 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
650 if (!clk)
651 return -ERANGE;
652
653 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
654 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
655
04a39c57 656 if (dev_priv->vbios.execute) {
6ee73861
BS		 657 still_alive();
658 nv_wr32(dev, reg + 4, reg1);
659 nv_wr32(dev, reg + 0, reg0);
660 }
661
662 return 0;
663}
664
665static int
666setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
667{
668 struct drm_device *dev = bios->dev;
669 struct drm_nouveau_private *dev_priv = dev->dev_private;
670 /* clk in kHz */
671 struct pll_lims pll_lim;
672 struct nouveau_pll_vals pllvals;
673 int ret;
674
675 if (dev_priv->card_type >= NV_50)
676 return nv50_pll_set(dev, reg, clk);
677
678 /* high regs (such as in the mac g5 table) are not -= 4 */
679 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
680 if (ret)
681 return ret;
682
683 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
684 if (!clk)
685 return -ERANGE;
686
687 if (bios->execute) {
688 still_alive();
689 nouveau_hw_setpll(dev, reg, &pllvals);
690 }
691
692 return 0;
693}
694
695static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
696{
697 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 698 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 699
700 /*
701 * For the results of this function to be correct, CR44 must have been
702 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
703 * and the DCB table parsed, before the script calling the function is
704 * run. run_digital_op_script is example of how to do such setup
705 */
706
707 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
708
7f245b20 709 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 710 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
711 "(%02X)\n", dcb_entry);
712 dcb_entry = 0x7f; /* unused / invalid marker */
713 }
714
715 return dcb_entry;
716}
717
f8b0be1a
BS		 718static int
719read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
720{
721 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
722 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
723 int recordoffset = 0, rdofs = 1, wrofs = 0;
724 uint8_t port_type = 0;
725
726 if (!i2ctable)
727 return -EINVAL;
728
729 if (dcb_version >= 0x30) {
730 if (i2ctable[0] != dcb_version) /* necessary? */
731 NV_WARN(dev,
732 "DCB I2C table version mismatch (%02X vs %02X)\n",
733 i2ctable[0], dcb_version);
734 dcb_i2c_ver = i2ctable[0];
735 headerlen = i2ctable[1];
736 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
737 i2c_entries = i2ctable[2];
738 else
739 NV_WARN(dev,
740 "DCB I2C table has more entries than indexable "
741 "(%d entries, max %d)\n", i2ctable[2],
742 DCB_MAX_NUM_I2C_ENTRIES);
743 entry_len = i2ctable[3];
744 /* [4] is i2c_default_indices, read in parse_dcb_table() */
745 }
746 /*
747 * It's your own fault if you call this function on a DCB 1.1 BIOS --
748 * the test below is for DCB 1.2
749 */
750 if (dcb_version < 0x14) {
751 recordoffset = 2;
752 rdofs = 0;
753 wrofs = 1;
754 }
755
756 if (index == 0xf)
757 return 0;
758 if (index >= i2c_entries) {
759 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
760 index, i2ctable[2]);
761 return -ENOENT;
762 }
763 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
764 NV_ERROR(dev, "DCB I2C entry invalid\n");
765 return -EINVAL;
766 }
767
768 if (dcb_i2c_ver >= 0x30) {
769 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
770
771 /*
772 * Fixup for chips using same address offset for read and
773 * write.
774 */
775 if (port_type == 4) /* seen on C51 */
776 rdofs = wrofs = 1;
777 if (port_type >= 5) /* G80+ */
778 rdofs = wrofs = 0;
779 }
780
781 if (dcb_i2c_ver >= 0x40) {
782 if (port_type != 5 && port_type != 6)
783 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
784
785 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
786 }
787
788 i2c->port_type = port_type;
789 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
790 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
791
792 return 0;
793}
794
6ee73861
BS		 795static struct nouveau_i2c_chan *
796init_i2c_device_find(struct drm_device *dev, int i2c_index)
797{
798 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 799 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 800
801 if (i2c_index == 0xff) {
802 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
803 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 804 int default_indices = dcb->i2c_default_indices;
6ee73861 805
7f245b20 806 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 807 shift = 4;
808
809 i2c_index = (default_indices >> shift) & 0xf;
810 }
811 if (i2c_index == 0x80) /* g80+ */
7f245b20 812 i2c_index = dcb->i2c_default_indices & 0xf;
6ee73861 813
f8b0be1a
BS		 814 if (i2c_index > DCB_MAX_NUM_I2C_ENTRIES) {
815 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
816 return NULL;
817 }
818
819 /* Make sure i2c table entry has been parsed, it may not
820 * have been if this is a bus not referenced by a DCB encoder
821 */
822 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
823 i2c_index, &dcb->i2c[i2c_index]);
824
6ee73861
BS		 825 return nouveau_i2c_find(dev, i2c_index);
826}
827
7f245b20
BS		 828static uint32_t
829get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 830{
831 /*
832 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
833 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
834 * CR58 for CR57 = 0 to index a table of offsets to the basic
835 * 0x6808b0 address.
836 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
837 * CR58 for CR57 = 0 to index a table of offsets to the basic
838 * 0x6808b0 address, and then flip the offset by 8.
839 */
840
841 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 842 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 843 const int pramdac_offset[13] = {
844 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
845 const uint32_t pramdac_table[4] = {
846 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
847
848 if (mlv >= 0x80) {
849 int dcb_entry, dacoffset;
850
851 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
852 dcb_entry = dcb_entry_idx_from_crtchead(dev);
853 if (dcb_entry == 0x7f)
854 return 0;
7f245b20 855 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 856 if (mlv == 0x81)
857 dacoffset ^= 8;
858 return 0x6808b0 + dacoffset;
859 } else {
df31ef4d 860 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 861 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
862 mlv);
863 return 0;
864 }
865 return pramdac_table[mlv];
866 }
867}
868
37383650 869static int
6ee73861
BS		 870init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
871 struct init_exec *iexec)
872{
873 /*
874 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
875 *
876 * offset (8 bit): opcode
877 * offset + 1 (16 bit): CRTC port
878 * offset + 3 (8 bit): CRTC index
879 * offset + 4 (8 bit): mask
880 * offset + 5 (8 bit): shift
881 * offset + 6 (8 bit): count
882 * offset + 7 (32 bit): register
883 * offset + 11 (32 bit): configuration 1
884 * ...
885 *
886 * Starting at offset + 11 there are "count" 32 bit values.
887 * To find out which value to use read index "CRTC index" on "CRTC
888 * port", AND this value with "mask" and then bit shift right "shift"
889 * bits. Read the appropriate value using this index and write to
890 * "register"
891 */
892
893 uint16_t crtcport = ROM16(bios->data[offset + 1]);
894 uint8_t crtcindex = bios->data[offset + 3];
895 uint8_t mask = bios->data[offset + 4];
896 uint8_t shift = bios->data[offset + 5];
897 uint8_t count = bios->data[offset + 6];
898 uint32_t reg = ROM32(bios->data[offset + 7]);
899 uint8_t config;
900 uint32_t configval;
37383650 901 int len = 11 + count * 4;
6ee73861
BS		 902
903 if (!iexec->execute)
37383650 904 return len;
6ee73861
BS		 905
906 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
907 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
908 offset, crtcport, crtcindex, mask, shift, count, reg);
909
910 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
911 if (config > count) {
912 NV_ERROR(bios->dev,
913 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
914 offset, config, count);
9170a824 915 return -EINVAL;
6ee73861
BS		 916 }
917
918 configval = ROM32(bios->data[offset + 11 + config * 4]);
919
920 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
921
922 bios_wr32(bios, reg, configval);
923
37383650 924 return len;
6ee73861
BS		 925}
926
37383650 927static int
6ee73861
BS		 928init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
929{
930 /*
931 * INIT_REPEAT opcode: 0x33 ('3')
932 *
933 * offset (8 bit): opcode
934 * offset + 1 (8 bit): count
935 *
936 * Execute script following this opcode up to INIT_REPEAT_END
937 * "count" times
938 */
939
940 uint8_t count = bios->data[offset + 1];
941 uint8_t i;
942
943 /* no iexec->execute check by design */
944
945 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
946 offset, count);
947
948 iexec->repeat = true;
949
950 /*
951 * count - 1, as the script block will execute once when we leave this
952 * opcode -- this is compatible with bios behaviour as:
953 * a) the block is always executed at least once, even if count == 0
954 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
955 * while we don't
956 */
957 for (i = 0; i < count - 1; i++)
958 parse_init_table(bios, offset + 2, iexec);
959
960 iexec->repeat = false;
961
37383650 962 return 2;
6ee73861
BS		 963}
964
37383650 965static int
6ee73861
BS		 966init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
967 struct init_exec *iexec)
968{
969 /*
970 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
971 *
972 * offset (8 bit): opcode
973 * offset + 1 (16 bit): CRTC port
974 * offset + 3 (8 bit): CRTC index
975 * offset + 4 (8 bit): mask
976 * offset + 5 (8 bit): shift
977 * offset + 6 (8 bit): IO flag condition index
978 * offset + 7 (8 bit): count
979 * offset + 8 (32 bit): register
980 * offset + 12 (16 bit): frequency 1
981 * ...
982 *
983 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
984 * Set PLL register "register" to coefficients for frequency n,
985 * selected by reading index "CRTC index" of "CRTC port" ANDed with
986 * "mask" and shifted right by "shift".
987 *
988 * If "IO flag condition index" > 0, and condition met, double
989 * frequency before setting it.
990 */
991
992 uint16_t crtcport = ROM16(bios->data[offset + 1]);
993 uint8_t crtcindex = bios->data[offset + 3];
994 uint8_t mask = bios->data[offset + 4];
995 uint8_t shift = bios->data[offset + 5];
996 int8_t io_flag_condition_idx = bios->data[offset + 6];
997 uint8_t count = bios->data[offset + 7];
998 uint32_t reg = ROM32(bios->data[offset + 8]);
999 uint8_t config;
1000 uint16_t freq;
37383650 1001 int len = 12 + count * 2;
6ee73861
BS		 1002
1003 if (!iexec->execute)
37383650 1004 return len;
6ee73861
BS		 1005
1006 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1007 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1008 "Count: 0x%02X, Reg: 0x%08X\n",
1009 offset, crtcport, crtcindex, mask, shift,
1010 io_flag_condition_idx, count, reg);
1011
1012 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1013 if (config > count) {
1014 NV_ERROR(bios->dev,
1015 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1016 offset, config, count);
9170a824 1017 return -EINVAL;
6ee73861
BS		 1018 }
1019
1020 freq = ROM16(bios->data[offset + 12 + config * 2]);
1021
1022 if (io_flag_condition_idx > 0) {
1023 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1024 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1025 "frequency doubled\n", offset);
1026 freq *= 2;
1027 } else
1028 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1029 "frequency unchanged\n", offset);
1030 }
1031
1032 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1033 offset, reg, config, freq);
1034
1035 setPLL(bios, reg, freq * 10);
1036
37383650 1037 return len;
6ee73861
BS		 1038}
1039
37383650 1040static int
6ee73861
BS		 1041init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1042{
1043 /*
1044 * INIT_END_REPEAT opcode: 0x36 ('6')
1045 *
1046 * offset (8 bit): opcode
1047 *
1048 * Marks the end of the block for INIT_REPEAT to repeat
1049 */
1050
1051 /* no iexec->execute check by design */
1052
1053 /*
1054 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1055 * we're not in repeat mode
1056 */
1057 if (iexec->repeat)
37383650 1058 return 0;
6ee73861 1059
37383650 1060 return 1;
6ee73861
BS		 1061}
1062
37383650 1063static int
6ee73861
BS		 1064init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1065{
1066 /*
1067 * INIT_COPY opcode: 0x37 ('7')
1068 *
1069 * offset (8 bit): opcode
1070 * offset + 1 (32 bit): register
1071 * offset + 5 (8 bit): shift
1072 * offset + 6 (8 bit): srcmask
1073 * offset + 7 (16 bit): CRTC port
1074 * offset + 9 (8 bit): CRTC index
1075 * offset + 10 (8 bit): mask
1076 *
1077 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1078 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1079 * port
1080 */
1081
1082 uint32_t reg = ROM32(bios->data[offset + 1]);
1083 uint8_t shift = bios->data[offset + 5];
1084 uint8_t srcmask = bios->data[offset + 6];
1085 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1086 uint8_t crtcindex = bios->data[offset + 9];
1087 uint8_t mask = bios->data[offset + 10];
1088 uint32_t data;
1089 uint8_t crtcdata;
1090
1091 if (!iexec->execute)
37383650 1092 return 11;
6ee73861
BS		 1093
1094 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1095 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1096 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1097
1098 data = bios_rd32(bios, reg);
1099
1100 if (shift < 0x80)
1101 data >>= shift;
1102 else
1103 data <<= (0x100 - shift);
1104
1105 data &= srcmask;
1106
1107 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1108 crtcdata |= (uint8_t)data;
1109 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1110
37383650 1111 return 11;
6ee73861
BS		 1112}
1113
37383650 1114static int
6ee73861
BS		 1115init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1116{
1117 /*
1118 * INIT_NOT opcode: 0x38 ('8')
1119 *
1120 * offset (8 bit): opcode
1121 *
1122 * Invert the current execute / no-execute condition (i.e. "else")
1123 */
1124 if (iexec->execute)
1125 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1126 else
1127 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1128
1129 iexec->execute = !iexec->execute;
37383650 1130 return 1;
6ee73861
BS		 1131}
1132
37383650 1133static int
6ee73861
BS		 1134init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1135 struct init_exec *iexec)
1136{
1137 /*
1138 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1139 *
1140 * offset (8 bit): opcode
1141 * offset + 1 (8 bit): condition number
1142 *
1143 * Check condition "condition number" in the IO flag condition table.
1144 * If condition not met skip subsequent opcodes until condition is
1145 * inverted (INIT_NOT), or we hit INIT_RESUME
1146 */
1147
1148 uint8_t cond = bios->data[offset + 1];
1149
1150 if (!iexec->execute)
37383650 1151 return 2;
6ee73861
BS		 1152
1153 if (io_flag_condition_met(bios, offset, cond))
1154 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1155 else {
1156 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1157 iexec->execute = false;
1158 }
1159
37383650 1160 return 2;
6ee73861
BS		 1161}
1162
25908b77
BS		 1163static int
1164init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1165{
1166 /*
1167 * INIT_DP_CONDITION opcode: 0x3A ('')
1168 *
1169 * offset (8 bit): opcode
1170 * offset + 1 (8 bit): "sub" opcode
1171 * offset + 2 (8 bit): unknown
1172 *
1173 */
1174
1175 struct bit_displayport_encoder_table *dpe = NULL;
1176 struct dcb_entry *dcb = bios->display.output;
1177 struct drm_device *dev = bios->dev;
1178 uint8_t cond = bios->data[offset + 1];
1179 int dummy;
1180
1181 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1182
1183 if (!iexec->execute)
1184 return 3;
1185
1186 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1187 if (!dpe) {
1188 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
1189 return -EINVAL;
1190 }
1191
1192 switch (cond) {
1193 case 0:
1194 {
1195 struct dcb_connector_table_entry *ent =
1196 &bios->dcb.connector.entry[dcb->connector];
1197
1198 if (ent->type != DCB_CONNECTOR_eDP)
1199 iexec->execute = false;
1200 }
1201 break;
1202 case 1:
1203 case 2:
1204 if (!(dpe->unknown & cond))
1205 iexec->execute = false;
1206 break;
1207 case 5:
1208 {
1209 struct nouveau_i2c_chan *auxch;
1210 int ret;
1211
1212 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1213 if (!auxch)
1214 return -ENODEV;
1215
1216 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1217 if (ret)
1218 return ret;
1219
1220 if (cond & 1)
1221 iexec->execute = false;
1222 }
1223 break;
1224 default:
1225 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1226 break;
1227 }
1228
1229 if (iexec->execute)
1230 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1231 else
1232 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1233
1234 return 3;
1235}
1236
1237static int
1238init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1239{
1240 /*
1241 * INIT_3B opcode: 0x3B ('')
1242 *
1243 * offset (8 bit): opcode
1244 * offset + 1 (8 bit): crtc index
1245 *
1246 */
1247
1248 uint8_t or = ffs(bios->display.output->or) - 1;
1249 uint8_t index = bios->data[offset + 1];
1250 uint8_t data;
1251
1252 if (!iexec->execute)
1253 return 2;
1254
1255 data = bios_idxprt_rd(bios, 0x3d4, index);
1256 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1257 return 2;
1258}
1259
1260static int
1261init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1262{
1263 /*
1264 * INIT_3C opcode: 0x3C ('')
1265 *
1266 * offset (8 bit): opcode
1267 * offset + 1 (8 bit): crtc index
1268 *
1269 */
1270
1271 uint8_t or = ffs(bios->display.output->or) - 1;
1272 uint8_t index = bios->data[offset + 1];
1273 uint8_t data;
1274
1275 if (!iexec->execute)
1276 return 2;
1277
1278 data = bios_idxprt_rd(bios, 0x3d4, index);
1279 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1280 return 2;
1281}
1282
37383650 1283static int
6ee73861
BS		 1284init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1285 struct init_exec *iexec)
1286{
1287 /*
1288 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1289 *
1290 * offset (8 bit): opcode
1291 * offset + 1 (32 bit): control register
1292 * offset + 5 (32 bit): data register
1293 * offset + 9 (32 bit): mask
1294 * offset + 13 (32 bit): data
1295 * offset + 17 (8 bit): count
1296 * offset + 18 (8 bit): address 1
1297 * offset + 19 (8 bit): data 1
1298 * ...
1299 *
1300 * For each of "count" address and data pairs, write "data n" to
1301 * "data register", read the current value of "control register",
1302 * and write it back once ANDed with "mask", ORed with "data",
1303 * and ORed with "address n"
1304 */
1305
1306 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1307 uint32_t datareg = ROM32(bios->data[offset + 5]);
1308 uint32_t mask = ROM32(bios->data[offset + 9]);
1309 uint32_t data = ROM32(bios->data[offset + 13]);
1310 uint8_t count = bios->data[offset + 17];
37383650 1311 int len = 18 + count * 2;
6ee73861
BS		 1312 uint32_t value;
1313 int i;
1314
1315 if (!iexec->execute)
37383650 1316 return len;
6ee73861
BS		 1317
1318 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1319 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1320 offset, controlreg, datareg, mask, data, count);
1321
1322 for (i = 0; i < count; i++) {
1323 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1324 uint8_t instdata = bios->data[offset + 19 + i * 2];
1325
1326 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1327 offset, instaddress, instdata);
1328
1329 bios_wr32(bios, datareg, instdata);
1330 value = bios_rd32(bios, controlreg) & mask;
1331 value |= data;
1332 value |= instaddress;
1333 bios_wr32(bios, controlreg, value);
1334 }
1335
37383650 1336 return len;
6ee73861
BS		 1337}
1338
37383650 1339static int
6ee73861
BS		 1340init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1341 struct init_exec *iexec)
1342{
1343 /*
1344 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1345 *
1346 * offset (8 bit): opcode
1347 * offset + 1 (16 bit): CRTC port
1348 * offset + 3 (8 bit): CRTC index
1349 * offset + 4 (8 bit): mask
1350 * offset + 5 (8 bit): shift
1351 * offset + 6 (8 bit): count
1352 * offset + 7 (32 bit): register
1353 * offset + 11 (32 bit): frequency 1
1354 * ...
1355 *
1356 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1357 * Set PLL register "register" to coefficients for frequency n,
1358 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1359 * "mask" and shifted right by "shift".
1360 */
1361
1362 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1363 uint8_t crtcindex = bios->data[offset + 3];
1364 uint8_t mask = bios->data[offset + 4];
1365 uint8_t shift = bios->data[offset + 5];
1366 uint8_t count = bios->data[offset + 6];
1367 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1368 int len = 11 + count * 4;
6ee73861
BS		 1369 uint8_t config;
1370 uint32_t freq;
1371
1372 if (!iexec->execute)
37383650 1373 return len;
6ee73861
BS		 1374
1375 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1376 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1377 offset, crtcport, crtcindex, mask, shift, count, reg);
1378
1379 if (!reg)
37383650 1380 return len;
6ee73861
BS		 1381
1382 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1383 if (config > count) {
1384 NV_ERROR(bios->dev,
1385 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1386 offset, config, count);
9170a824 1387 return -EINVAL;
6ee73861
BS		 1388 }
1389
1390 freq = ROM32(bios->data[offset + 11 + config * 4]);
1391
1392 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1393 offset, reg, config, freq);
1394
1395 setPLL(bios, reg, freq);
1396
37383650 1397 return len;
6ee73861
BS		 1398}
1399
37383650 1400static int
6ee73861
BS		 1401init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1402{
1403 /*
1404 * INIT_PLL2 opcode: 0x4B ('K')
1405 *
1406 * offset (8 bit): opcode
1407 * offset + 1 (32 bit): register
1408 * offset + 5 (32 bit): freq
1409 *
1410 * Set PLL register "register" to coefficients for frequency "freq"
1411 */
1412
1413 uint32_t reg = ROM32(bios->data[offset + 1]);
1414 uint32_t freq = ROM32(bios->data[offset + 5]);
1415
1416 if (!iexec->execute)
37383650 1417 return 9;
6ee73861
BS		 1418
1419 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1420 offset, reg, freq);
1421
1422 setPLL(bios, reg, freq);
37383650 1423 return 9;
6ee73861
BS		 1424}
1425
37383650 1426static int
6ee73861
BS		 1427init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1428{
1429 /*
1430 * INIT_I2C_BYTE opcode: 0x4C ('L')
1431 *
1432 * offset (8 bit): opcode
1433 * offset + 1 (8 bit): DCB I2C table entry index
1434 * offset + 2 (8 bit): I2C slave address
1435 * offset + 3 (8 bit): count
1436 * offset + 4 (8 bit): I2C register 1
1437 * offset + 5 (8 bit): mask 1
1438 * offset + 6 (8 bit): data 1
1439 * ...
1440 *
1441 * For each of "count" registers given by "I2C register n" on the device
1442 * addressed by "I2C slave address" on the I2C bus given by
1443 * "DCB I2C table entry index", read the register, AND the result with
1444 * "mask n" and OR it with "data n" before writing it back to the device
1445 */
1446
1447 uint8_t i2c_index = bios->data[offset + 1];
1448 uint8_t i2c_address = bios->data[offset + 2];
1449 uint8_t count = bios->data[offset + 3];
37383650 1450 int len = 4 + count * 3;
6ee73861
BS		 1451 struct nouveau_i2c_chan *chan;
1452 struct i2c_msg msg;
1453 int i;
1454
1455 if (!iexec->execute)
37383650 1456 return len;
6ee73861
BS		 1457
1458 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1459 "Count: 0x%02X\n",
1460 offset, i2c_index, i2c_address, count);
1461
1462 chan = init_i2c_device_find(bios->dev, i2c_index);
1463 if (!chan)
9170a824 1464 return -ENODEV;
6ee73861
BS		 1465
1466 for (i = 0; i < count; i++) {
1467 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
1468 uint8_t mask = bios->data[offset + 5 + i * 3];
1469 uint8_t data = bios->data[offset + 6 + i * 3];
1470 uint8_t value;
1471
1472 msg.addr = i2c_address;
1473 msg.flags = I2C_M_RD;
1474 msg.len = 1;
1475 msg.buf = &value;
1476 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1477 return -EIO;
6ee73861
BS		 1478
1479 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1480 "Mask: 0x%02X, Data: 0x%02X\n",
1481 offset, i2c_reg, value, mask, data);
1482
1483 value = (value & mask) | data;
1484
1485 if (bios->execute) {
1486 msg.addr = i2c_address;
1487 msg.flags = 0;
1488 msg.len = 1;
1489 msg.buf = &value;
1490 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1491 return -EIO;
6ee73861
BS		 1492 }
1493 }
1494
37383650 1495 return len;
6ee73861
BS		 1496}
1497
37383650 1498static int
6ee73861
BS		 1499init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1500{
1501 /*
1502 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1503 *
1504 * offset (8 bit): opcode
1505 * offset + 1 (8 bit): DCB I2C table entry index
1506 * offset + 2 (8 bit): I2C slave address
1507 * offset + 3 (8 bit): count
1508 * offset + 4 (8 bit): I2C register 1
1509 * offset + 5 (8 bit): data 1
1510 * ...
1511 *
1512 * For each of "count" registers given by "I2C register n" on the device
1513 * addressed by "I2C slave address" on the I2C bus given by
1514 * "DCB I2C table entry index", set the register to "data n"
1515 */
1516
1517 uint8_t i2c_index = bios->data[offset + 1];
1518 uint8_t i2c_address = bios->data[offset + 2];
1519 uint8_t count = bios->data[offset + 3];
37383650 1520 int len = 4 + count * 2;
6ee73861
BS		 1521 struct nouveau_i2c_chan *chan;
1522 struct i2c_msg msg;
1523 int i;
1524
1525 if (!iexec->execute)
37383650 1526 return len;
6ee73861
BS		 1527
1528 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1529 "Count: 0x%02X\n",
1530 offset, i2c_index, i2c_address, count);
1531
1532 chan = init_i2c_device_find(bios->dev, i2c_index);
1533 if (!chan)
9170a824 1534 return -ENODEV;
6ee73861
BS		 1535
1536 for (i = 0; i < count; i++) {
1537 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
1538 uint8_t data = bios->data[offset + 5 + i * 2];
1539
1540 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1541 offset, i2c_reg, data);
1542
1543 if (bios->execute) {
1544 msg.addr = i2c_address;
1545 msg.flags = 0;
1546 msg.len = 1;
1547 msg.buf = &data;
1548 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1549 return -EIO;
6ee73861
BS		 1550 }
1551 }
1552
37383650 1553 return len;
6ee73861
BS		 1554}
1555
37383650 1556static int
6ee73861
BS		 1557init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1558{
1559 /*
1560 * INIT_ZM_I2C opcode: 0x4E ('N')
1561 *
1562 * offset (8 bit): opcode
1563 * offset + 1 (8 bit): DCB I2C table entry index
1564 * offset + 2 (8 bit): I2C slave address
1565 * offset + 3 (8 bit): count
1566 * offset + 4 (8 bit): data 1
1567 * ...
1568 *
1569 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1570 * address" on the I2C bus given by "DCB I2C table entry index"
1571 */
1572
1573 uint8_t i2c_index = bios->data[offset + 1];
1574 uint8_t i2c_address = bios->data[offset + 2];
1575 uint8_t count = bios->data[offset + 3];
37383650 1576 int len = 4 + count;
6ee73861
BS		 1577 struct nouveau_i2c_chan *chan;
1578 struct i2c_msg msg;
1579 uint8_t data[256];
1580 int i;
1581
1582 if (!iexec->execute)
37383650 1583 return len;
6ee73861
BS		 1584
1585 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1586 "Count: 0x%02X\n",
1587 offset, i2c_index, i2c_address, count);
1588
1589 chan = init_i2c_device_find(bios->dev, i2c_index);
1590 if (!chan)
9170a824 1591 return -ENODEV;
6ee73861
BS		 1592
1593 for (i = 0; i < count; i++) {
1594 data[i] = bios->data[offset + 4 + i];
1595
1596 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1597 }
1598
1599 if (bios->execute) {
1600 msg.addr = i2c_address;
1601 msg.flags = 0;
1602 msg.len = count;
1603 msg.buf = data;
1604 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1605 return -EIO;
6ee73861
BS		 1606 }
1607
37383650 1608 return len;
6ee73861
BS		 1609}
1610
37383650 1611static int
6ee73861
BS		 1612init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1613{
1614 /*
1615 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1616 *
1617 * offset (8 bit): opcode
1618 * offset + 1 (8 bit): magic lookup value
1619 * offset + 2 (8 bit): TMDS address
1620 * offset + 3 (8 bit): mask
1621 * offset + 4 (8 bit): data
1622 *
1623 * Read the data reg for TMDS address "TMDS address", AND it with mask
1624 * and OR it with data, then write it back
1625 * "magic lookup value" determines which TMDS base address register is
1626 * used -- see get_tmds_index_reg()
1627 */
1628
1629 uint8_t mlv = bios->data[offset + 1];
1630 uint32_t tmdsaddr = bios->data[offset + 2];
1631 uint8_t mask = bios->data[offset + 3];
1632 uint8_t data = bios->data[offset + 4];
1633 uint32_t reg, value;
1634
1635 if (!iexec->execute)
37383650 1636 return 5;
6ee73861
BS		 1637
1638 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1639 "Mask: 0x%02X, Data: 0x%02X\n",
1640 offset, mlv, tmdsaddr, mask, data);
1641
1642 reg = get_tmds_index_reg(bios->dev, mlv);
1643 if (!reg)
9170a824 1644 return -EINVAL;
6ee73861
BS		 1645
1646 bios_wr32(bios, reg,
1647 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1648 value = (bios_rd32(bios, reg + 4) & mask) | data;
1649 bios_wr32(bios, reg + 4, value);
1650 bios_wr32(bios, reg, tmdsaddr);
1651
37383650 1652 return 5;
6ee73861
BS		 1653}
1654
37383650 1655static int
6ee73861
BS		 1656init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1657 struct init_exec *iexec)
1658{
1659 /*
1660 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1661 *
1662 * offset (8 bit): opcode
1663 * offset + 1 (8 bit): magic lookup value
1664 * offset + 2 (8 bit): count
1665 * offset + 3 (8 bit): addr 1
1666 * offset + 4 (8 bit): data 1
1667 * ...
1668 *
1669 * For each of "count" TMDS address and data pairs write "data n" to
1670 * "addr n". "magic lookup value" determines which TMDS base address
1671 * register is used -- see get_tmds_index_reg()
1672 */
1673
1674 uint8_t mlv = bios->data[offset + 1];
1675 uint8_t count = bios->data[offset + 2];
37383650 1676 int len = 3 + count * 2;
6ee73861
BS		 1677 uint32_t reg;
1678 int i;
1679
1680 if (!iexec->execute)
37383650 1681 return len;
6ee73861
BS		 1682
1683 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1684 offset, mlv, count);
1685
1686 reg = get_tmds_index_reg(bios->dev, mlv);
1687 if (!reg)
9170a824 1688 return -EINVAL;
6ee73861
BS		 1689
1690 for (i = 0; i < count; i++) {
1691 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1692 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1693
1694 bios_wr32(bios, reg + 4, tmdsdata);
1695 bios_wr32(bios, reg, tmdsaddr);
1696 }
1697
37383650 1698 return len;
6ee73861
BS		 1699}
1700
37383650 1701static int
6ee73861
BS		 1702init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1703 struct init_exec *iexec)
1704{
1705 /*
1706 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1707 *
1708 * offset (8 bit): opcode
1709 * offset + 1 (8 bit): CRTC index1
1710 * offset + 2 (8 bit): CRTC index2
1711 * offset + 3 (8 bit): baseaddr
1712 * offset + 4 (8 bit): count
1713 * offset + 5 (8 bit): data 1
1714 * ...
1715 *
1716 * For each of "count" address and data pairs, write "baseaddr + n" to
1717 * "CRTC index1" and "data n" to "CRTC index2"
1718 * Once complete, restore initial value read from "CRTC index1"
1719 */
1720 uint8_t crtcindex1 = bios->data[offset + 1];
1721 uint8_t crtcindex2 = bios->data[offset + 2];
1722 uint8_t baseaddr = bios->data[offset + 3];
1723 uint8_t count = bios->data[offset + 4];
37383650 1724 int len = 5 + count;
6ee73861
BS		 1725 uint8_t oldaddr, data;
1726 int i;
1727
1728 if (!iexec->execute)
37383650 1729 return len;
6ee73861
BS		 1730
1731 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1732 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1733 offset, crtcindex1, crtcindex2, baseaddr, count);
1734
1735 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1736
1737 for (i = 0; i < count; i++) {
1738 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1739 baseaddr + i);
1740 data = bios->data[offset + 5 + i];
1741 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1742 }
1743
1744 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1745
37383650 1746 return len;
6ee73861
BS		 1747}
1748
37383650 1749static int
6ee73861
BS		 1750init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1751{
1752 /*
1753 * INIT_CR opcode: 0x52 ('R')
1754 *
1755 * offset (8 bit): opcode
1756 * offset + 1 (8 bit): CRTC index
1757 * offset + 2 (8 bit): mask
1758 * offset + 3 (8 bit): data
1759 *
1760 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1761 * data back to "CRTC index"
1762 */
1763
1764 uint8_t crtcindex = bios->data[offset + 1];
1765 uint8_t mask = bios->data[offset + 2];
1766 uint8_t data = bios->data[offset + 3];
1767 uint8_t value;
1768
1769 if (!iexec->execute)
37383650 1770 return 4;
6ee73861
BS		 1771
1772 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1773 offset, crtcindex, mask, data);
1774
1775 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1776 value |= data;
1777 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1778
37383650 1779 return 4;
6ee73861
BS		 1780}
1781
37383650 1782static int
6ee73861
BS		 1783init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1784{
1785 /*
1786 * INIT_ZM_CR opcode: 0x53 ('S')
1787 *
1788 * offset (8 bit): opcode
1789 * offset + 1 (8 bit): CRTC index
1790 * offset + 2 (8 bit): value
1791 *
1792 * Assign "value" to CRTC register with index "CRTC index".
1793 */
1794
1795 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1796 uint8_t data = bios->data[offset + 2];
1797
1798 if (!iexec->execute)
37383650 1799 return 3;
6ee73861
BS		 1800
1801 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1802
37383650 1803 return 3;
6ee73861
BS		 1804}
1805
37383650 1806static int
6ee73861
BS		 1807init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1808{
1809 /*
1810 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1811 *
1812 * offset (8 bit): opcode
1813 * offset + 1 (8 bit): count
1814 * offset + 2 (8 bit): CRTC index 1
1815 * offset + 3 (8 bit): value 1
1816 * ...
1817 *
1818 * For "count", assign "value n" to CRTC register with index
1819 * "CRTC index n".
1820 */
1821
1822 uint8_t count = bios->data[offset + 1];
37383650 1823 int len = 2 + count * 2;
6ee73861
BS		 1824 int i;
1825
1826 if (!iexec->execute)
37383650 1827 return len;
6ee73861
BS		 1828
1829 for (i = 0; i < count; i++)
1830 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1831
37383650 1832 return len;
6ee73861
BS		 1833}
1834
37383650 1835static int
6ee73861
BS		 1836init_condition_time(struct nvbios *bios, uint16_t offset,
1837 struct init_exec *iexec)
1838{
1839 /*
1840 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1841 *
1842 * offset (8 bit): opcode
1843 * offset + 1 (8 bit): condition number
1844 * offset + 2 (8 bit): retries / 50
1845 *
1846 * Check condition "condition number" in the condition table.
1847 * Bios code then sleeps for 2ms if the condition is not met, and
1848 * repeats up to "retries" times, but on one C51 this has proved
1849 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1850 * this, and bail after "retries" times, or 2s, whichever is less.
1851 * If still not met after retries, clear execution flag for this table.
1852 */
1853
1854 uint8_t cond = bios->data[offset + 1];
1855 uint16_t retries = bios->data[offset + 2] * 50;
1856 unsigned cnt;
1857
1858 if (!iexec->execute)
37383650 1859 return 3;
6ee73861
BS		 1860
1861 if (retries > 100)
1862 retries = 100;
1863
1864 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1865 offset, cond, retries);
1866
1867 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1868 retries = 1;
1869
1870 for (cnt = 0; cnt < retries; cnt++) {
1871 if (bios_condition_met(bios, offset, cond)) {
1872 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1873 offset);
1874 break;
1875 } else {
1876 BIOSLOG(bios, "0x%04X: "
1877 "Condition not met, sleeping for 20ms\n",
1878 offset);
1879 msleep(20);
1880 }
1881 }
1882
1883 if (!bios_condition_met(bios, offset, cond)) {
1884 NV_WARN(bios->dev,
1885 "0x%04X: Condition still not met after %dms, "
1886 "skipping following opcodes\n", offset, 20 * retries);
1887 iexec->execute = false;
1888 }
1889
37383650 1890 return 3;
6ee73861
BS		 1891}
1892
37383650 1893static int
6ee73861
BS		 1894init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1895 struct init_exec *iexec)
1896{
1897 /*
1898 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1899 *
1900 * offset (8 bit): opcode
1901 * offset + 1 (32 bit): base register
1902 * offset + 5 (8 bit): count
1903 * offset + 6 (32 bit): value 1
1904 * ...
1905 *
1906 * Starting at offset + 6 there are "count" 32 bit values.
1907 * For "count" iterations set "base register" + 4 * current_iteration
1908 * to "value current_iteration"
1909 */
1910
1911 uint32_t basereg = ROM32(bios->data[offset + 1]);
1912 uint32_t count = bios->data[offset + 5];
37383650 1913 int len = 6 + count * 4;
6ee73861
BS		 1914 int i;
1915
1916 if (!iexec->execute)
37383650 1917 return len;
6ee73861
BS		 1918
1919 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1920 offset, basereg, count);
1921
1922 for (i = 0; i < count; i++) {
1923 uint32_t reg = basereg + i * 4;
1924 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1925
1926 bios_wr32(bios, reg, data);
1927 }
1928
37383650 1929 return len;
6ee73861
BS		 1930}
1931
37383650 1932static int
6ee73861
BS		 1933init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1934{
1935 /*
1936 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1937 *
1938 * offset (8 bit): opcode
1939 * offset + 1 (16 bit): subroutine offset (in bios)
1940 *
1941 * Calls a subroutine that will execute commands until INIT_DONE
1942 * is found.
1943 */
1944
1945 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1946
1947 if (!iexec->execute)
37383650 1948 return 3;
6ee73861
BS		 1949
1950 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1951 offset, sub_offset);
1952
1953 parse_init_table(bios, sub_offset, iexec);
1954
1955 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1956
37383650 1957 return 3;
6ee73861
BS		 1958}
1959
37383650 1960static int
6ee73861
BS		 1961init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1962{
1963 /*
1964 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1965 *
1966 * offset (8 bit): opcode
1967 * offset + 1 (32 bit): src reg
1968 * offset + 5 (8 bit): shift
1969 * offset + 6 (32 bit): src mask
1970 * offset + 10 (32 bit): xor
1971 * offset + 14 (32 bit): dst reg
1972 * offset + 18 (32 bit): dst mask
1973 *
1974 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1975 * "src mask", then XOR with "xor". Write this OR'd with
1976 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1977 */
1978
1979 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1980 uint8_t shift = bios->data[offset + 5];
1981 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1982 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1983 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1984 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1985 uint32_t srcvalue, dstvalue;
1986
1987 if (!iexec->execute)
37383650 1988 return 22;
6ee73861
BS		 1989
1990 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1991 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1992 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1993
1994 srcvalue = bios_rd32(bios, srcreg);
1995
1996 if (shift < 0x80)
1997 srcvalue >>= shift;
1998 else
1999 srcvalue <<= (0x100 - shift);
2000
2001 srcvalue = (srcvalue & srcmask) ^ xor;
2002
2003 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2004
2005 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2006
37383650 2007 return 22;
6ee73861
BS		 2008}
2009
37383650 2010static int
6ee73861
BS		 2011init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2012{
2013 /*
2014 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2015 *
2016 * offset (8 bit): opcode
2017 * offset + 1 (16 bit): CRTC port
2018 * offset + 3 (8 bit): CRTC index
2019 * offset + 4 (8 bit): data
2020 *
2021 * Write "data" to index "CRTC index" of "CRTC port"
2022 */
2023 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2024 uint8_t crtcindex = bios->data[offset + 3];
2025 uint8_t data = bios->data[offset + 4];
2026
2027 if (!iexec->execute)
37383650 2028 return 5;
6ee73861
BS		 2029
2030 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2031
37383650 2032 return 5;
6ee73861
BS		 2033}
2034
37383650 2035static int
6ee73861
BS		 2036init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2037{
2038 /*
2039 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2040 *
2041 * offset (8 bit): opcode
2042 *
2043 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
2044 * that the hardware can correctly calculate how much VRAM it has
2045 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
2046 *
2047 * The implementation of this opcode in general consists of two parts:
2048 * 1) determination of the memory bus width
2049 * 2) determination of how many of the card's RAM pads have ICs attached
2050 *
2051 * 1) is done by a cunning combination of writes to offsets 0x1c and
2052 * 0x3c in the framebuffer, and seeing whether the written values are
2053 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
2054 *
2055 * 2) is done by a cunning combination of writes to an offset slightly
2056 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
2057 * if the test pattern can be read back. This then affects bits 12-15 of
2058 * NV_PFB_CFG0
2059 *
2060 * In this context a "cunning combination" may include multiple reads
2061 * and writes to varying locations, often alternating the test pattern
2062 * and 0, doubtless to make sure buffers are filled, residual charges
2063 * on tracks are removed etc.
2064 *
2065 * Unfortunately, the "cunning combination"s mentioned above, and the
2066 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
2067 * trace I have.
2068 *
2069 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
2070 * we started was correct, and use that instead
2071 */
2072
2073 /* no iexec->execute check by design */
2074
2075 /*
2076 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
2077 * and kmmio traces of the binary driver POSTing the card show nothing
2078 * being done for this opcode. why is it still listed in the table?!
2079 */
2080
2081 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2082
e235c1f3 2083 if (dev_priv->card_type >= NV_40)
37383650 2084 return 1;
6ee73861
BS		 2085
2086 /*
2087 * On every card I've seen, this step gets done for us earlier in
2088 * the init scripts
2089 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
2090 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
2091 */
2092
2093 /*
2094 * This also has probably been done in the scripts, but an mmio trace of
2095 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
2096 */
2097 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
2098
2099 /* write back the saved configuration value */
2100 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
2101
37383650 2102 return 1;
6ee73861
BS		 2103}
2104
37383650 2105static int
6ee73861
BS		 2106init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2107{
2108 /*
2109 * INIT_RESET opcode: 0x65 ('e')
2110 *
2111 * offset (8 bit): opcode
2112 * offset + 1 (32 bit): register
2113 * offset + 5 (32 bit): value1
2114 * offset + 9 (32 bit): value2
2115 *
2116 * Assign "value1" to "register", then assign "value2" to "register"
2117 */
2118
2119 uint32_t reg = ROM32(bios->data[offset + 1]);
2120 uint32_t value1 = ROM32(bios->data[offset + 5]);
2121 uint32_t value2 = ROM32(bios->data[offset + 9]);
2122 uint32_t pci_nv_19, pci_nv_20;
2123
2124 /* no iexec->execute check by design */
2125
2126 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2127 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
2128 bios_wr32(bios, reg, value1);
2129
2130 udelay(10);
2131
2132 bios_wr32(bios, reg, value2);
2133 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2134
2135 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2136 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2137 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2138
37383650 2139 return 13;
6ee73861
BS		 2140}
2141
37383650 2142static int
6ee73861
BS		 2143init_configure_mem(struct nvbios *bios, uint16_t offset,
2144 struct init_exec *iexec)
2145{
2146 /*
2147 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2148 *
2149 * offset (8 bit): opcode
2150 *
2151 * Equivalent to INIT_DONE on bios version 3 or greater.
2152 * For early bios versions, sets up the memory registers, using values
2153 * taken from the memory init table
2154 */
2155
2156 /* no iexec->execute check by design */
2157
2158 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2159 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2160 uint32_t reg, data;
2161
2162 if (bios->major_version > 2)
9170a824 2163 return -ENODEV;
6ee73861
BS		 2164
2165 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2166 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2167
2168 if (bios->data[meminitoffs] & 1)
2169 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2170
2171 for (reg = ROM32(bios->data[seqtbloffs]);
2172 reg != 0xffffffff;
2173 reg = ROM32(bios->data[seqtbloffs += 4])) {
2174
2175 switch (reg) {
2176 case NV_PFB_PRE:
2177 data = NV_PFB_PRE_CMD_PRECHARGE;
2178 break;
2179 case NV_PFB_PAD:
2180 data = NV_PFB_PAD_CKE_NORMAL;
2181 break;
2182 case NV_PFB_REF:
2183 data = NV_PFB_REF_CMD_REFRESH;
2184 break;
2185 default:
2186 data = ROM32(bios->data[meminitdata]);
2187 meminitdata += 4;
2188 if (data == 0xffffffff)
2189 continue;
2190 }
2191
2192 bios_wr32(bios, reg, data);
2193 }
2194
37383650 2195 return 1;
6ee73861
BS		 2196}
2197
37383650 2198static int
6ee73861
BS		 2199init_configure_clk(struct nvbios *bios, uint16_t offset,
2200 struct init_exec *iexec)
2201{
2202 /*
2203 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2204 *
2205 * offset (8 bit): opcode
2206 *
2207 * Equivalent to INIT_DONE on bios version 3 or greater.
2208 * For early bios versions, sets up the NVClk and MClk PLLs, using
2209 * values taken from the memory init table
2210 */
2211
2212 /* no iexec->execute check by design */
2213
2214 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2215 int clock;
2216
2217 if (bios->major_version > 2)
9170a824 2218 return -ENODEV;
6ee73861
BS		 2219
2220 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2221 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2222
2223 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2224 if (bios->data[meminitoffs] & 1) /* DDR */
2225 clock *= 2;
2226 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2227
37383650 2228 return 1;
6ee73861
BS		 2229}
2230
37383650 2231static int
6ee73861
BS		 2232init_configure_preinit(struct nvbios *bios, uint16_t offset,
2233 struct init_exec *iexec)
2234{
2235 /*
2236 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2237 *
2238 * offset (8 bit): opcode
2239 *
2240 * Equivalent to INIT_DONE on bios version 3 or greater.
2241 * For early bios versions, does early init, loading ram and crystal
2242 * configuration from straps into CR3C
2243 */
2244
2245 /* no iexec->execute check by design */
2246
2247 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2248 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2249
2250 if (bios->major_version > 2)
9170a824 2251 return -ENODEV;
6ee73861
BS		 2252
2253 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2254 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2255
37383650 2256 return 1;
6ee73861
BS		 2257}
2258
37383650 2259static int
6ee73861
BS		 2260init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2261{
2262 /*
2263 * INIT_IO opcode: 0x69 ('i')
2264 *
2265 * offset (8 bit): opcode
2266 * offset + 1 (16 bit): CRTC port
2267 * offset + 3 (8 bit): mask
2268 * offset + 4 (8 bit): data
2269 *
2270 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2271 */
2272
2273 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2274 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2275 uint8_t mask = bios->data[offset + 3];
2276 uint8_t data = bios->data[offset + 4];
2277
2278 if (!iexec->execute)
37383650 2279 return 5;
6ee73861
BS		 2280
2281 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2282 offset, crtcport, mask, data);
2283
2284 /*
2285 * I have no idea what this does, but NVIDIA do this magic sequence
2286 * in the places where this INIT_IO happens..
2287 */
2288 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2289 int i;
2290
2291 bios_wr32(bios, 0x614100, (bios_rd32(
2292 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2293
2294 bios_wr32(bios, 0x00e18c, bios_rd32(
2295 bios, 0x00e18c) | 0x00020000);
2296
2297 bios_wr32(bios, 0x614900, (bios_rd32(
2298 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2299
2300 bios_wr32(bios, 0x000200, bios_rd32(
2301 bios, 0x000200) & ~0x40000000);
2302
2303 mdelay(10);
2304
2305 bios_wr32(bios, 0x00e18c, bios_rd32(
2306 bios, 0x00e18c) & ~0x00020000);
2307
2308 bios_wr32(bios, 0x000200, bios_rd32(
2309 bios, 0x000200) | 0x40000000);
2310
2311 bios_wr32(bios, 0x614100, 0x00800018);
2312 bios_wr32(bios, 0x614900, 0x00800018);
2313
2314 mdelay(10);
2315
2316 bios_wr32(bios, 0x614100, 0x10000018);
2317 bios_wr32(bios, 0x614900, 0x10000018);
2318
2319 for (i = 0; i < 3; i++)
2320 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2321 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2322
2323 for (i = 0; i < 2; i++)
2324 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2325 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2326
2327 for (i = 0; i < 3; i++)
2328 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2329 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2330
2331 for (i = 0; i < 2; i++)
2332 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2333 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2334
2335 for (i = 0; i < 2; i++)
2336 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2337 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2338 return 5;
6ee73861
BS		 2339 }
2340
2341 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2342 data);
37383650 2343 return 5;
6ee73861
BS		 2344}
2345
37383650 2346static int
6ee73861
BS		 2347init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2348{
2349 /*
2350 * INIT_SUB opcode: 0x6B ('k')
2351 *
2352 * offset (8 bit): opcode
2353 * offset + 1 (8 bit): script number
2354 *
2355 * Execute script number "script number", as a subroutine
2356 */
2357
2358 uint8_t sub = bios->data[offset + 1];
2359
2360 if (!iexec->execute)
37383650 2361 return 2;
6ee73861
BS		 2362
2363 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2364
2365 parse_init_table(bios,
2366 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2367 iexec);
2368
2369 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2370
37383650 2371 return 2;
6ee73861
BS		 2372}
2373
37383650 2374static int
6ee73861
BS		 2375init_ram_condition(struct nvbios *bios, uint16_t offset,
2376 struct init_exec *iexec)
2377{
2378 /*
2379 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2380 *
2381 * offset (8 bit): opcode
2382 * offset + 1 (8 bit): mask
2383 * offset + 2 (8 bit): cmpval
2384 *
2385 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2386 * If condition not met skip subsequent opcodes until condition is
2387 * inverted (INIT_NOT), or we hit INIT_RESUME
2388 */
2389
2390 uint8_t mask = bios->data[offset + 1];
2391 uint8_t cmpval = bios->data[offset + 2];
2392 uint8_t data;
2393
2394 if (!iexec->execute)
37383650 2395 return 3;
6ee73861
BS		 2396
2397 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2398
2399 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2400 offset, data, cmpval);
2401
2402 if (data == cmpval)
2403 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2404 else {
2405 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2406 iexec->execute = false;
2407 }
2408
37383650 2409 return 3;
6ee73861
BS		 2410}
2411
37383650 2412static int
6ee73861
BS		 2413init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2414{
2415 /*
2416 * INIT_NV_REG opcode: 0x6E ('n')
2417 *
2418 * offset (8 bit): opcode
2419 * offset + 1 (32 bit): register
2420 * offset + 5 (32 bit): mask
2421 * offset + 9 (32 bit): data
2422 *
2423 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2424 */
2425
2426 uint32_t reg = ROM32(bios->data[offset + 1]);
2427 uint32_t mask = ROM32(bios->data[offset + 5]);
2428 uint32_t data = ROM32(bios->data[offset + 9]);
2429
2430 if (!iexec->execute)
37383650 2431 return 13;
6ee73861
BS		 2432
2433 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2434 offset, reg, mask, data);
2435
2436 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2437
37383650 2438 return 13;
6ee73861
BS		 2439}
2440
37383650 2441static int
6ee73861
BS		 2442init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2443{
2444 /*
2445 * INIT_MACRO opcode: 0x6F ('o')
2446 *
2447 * offset (8 bit): opcode
2448 * offset + 1 (8 bit): macro number
2449 *
2450 * Look up macro index "macro number" in the macro index table.
2451 * The macro index table entry has 1 byte for the index in the macro
2452 * table, and 1 byte for the number of times to repeat the macro.
2453 * The macro table entry has 4 bytes for the register address and
2454 * 4 bytes for the value to write to that register
2455 */
2456
2457 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2458 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2459 uint8_t macro_tbl_idx = bios->data[tmp];
2460 uint8_t count = bios->data[tmp + 1];
2461 uint32_t reg, data;
2462 int i;
2463
2464 if (!iexec->execute)
37383650 2465 return 2;
6ee73861
BS		 2466
2467 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2468 "Count: 0x%02X\n",
2469 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2470
2471 for (i = 0; i < count; i++) {
2472 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2473
2474 reg = ROM32(bios->data[macroentryptr]);
2475 data = ROM32(bios->data[macroentryptr + 4]);
2476
2477 bios_wr32(bios, reg, data);
2478 }
2479
37383650 2480 return 2;
6ee73861
BS		 2481}
2482
37383650 2483static int
6ee73861
BS		 2484init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2485{
2486 /*
2487 * INIT_DONE opcode: 0x71 ('q')
2488 *
2489 * offset (8 bit): opcode
2490 *
2491 * End the current script
2492 */
2493
2494 /* mild retval abuse to stop parsing this table */
37383650 2495 return 0;
6ee73861
BS		 2496}
2497
37383650 2498static int
6ee73861
BS		 2499init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2500{
2501 /*
2502 * INIT_RESUME opcode: 0x72 ('r')
2503 *
2504 * offset (8 bit): opcode
2505 *
2506 * End the current execute / no-execute condition
2507 */
2508
2509 if (iexec->execute)
37383650 2510 return 1;
6ee73861
BS		 2511
2512 iexec->execute = true;
2513 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2514
37383650 2515 return 1;
6ee73861
BS		 2516}
2517
37383650 2518static int
6ee73861
BS		 2519init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2520{
2521 /*
2522 * INIT_TIME opcode: 0x74 ('t')
2523 *
2524 * offset (8 bit): opcode
2525 * offset + 1 (16 bit): time
2526 *
2527 * Sleep for "time" microseconds.
2528 */
2529
2530 unsigned time = ROM16(bios->data[offset + 1]);
2531
2532 if (!iexec->execute)
37383650 2533 return 3;
6ee73861
BS		 2534
2535 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2536 offset, time);
2537
2538 if (time < 1000)
2539 udelay(time);
2540 else
2541 msleep((time + 900) / 1000);
2542
37383650 2543 return 3;
6ee73861
BS		 2544}
2545
37383650 2546static int
6ee73861
BS		 2547init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2548{
2549 /*
2550 * INIT_CONDITION opcode: 0x75 ('u')
2551 *
2552 * offset (8 bit): opcode
2553 * offset + 1 (8 bit): condition number
2554 *
2555 * Check condition "condition number" in the condition table.
2556 * If condition not met skip subsequent opcodes until condition is
2557 * inverted (INIT_NOT), or we hit INIT_RESUME
2558 */
2559
2560 uint8_t cond = bios->data[offset + 1];
2561
2562 if (!iexec->execute)
37383650 2563 return 2;
6ee73861
BS		 2564
2565 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2566
2567 if (bios_condition_met(bios, offset, cond))
2568 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2569 else {
2570 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2571 iexec->execute = false;
2572 }
2573
37383650 2574 return 2;
6ee73861
BS		 2575}
2576
37383650 2577static int
6ee73861
BS		 2578init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2579{
2580 /*
2581 * INIT_IO_CONDITION opcode: 0x76
2582 *
2583 * offset (8 bit): opcode
2584 * offset + 1 (8 bit): condition number
2585 *
2586 * Check condition "condition number" in the io condition table.
2587 * If condition not met skip subsequent opcodes until condition is
2588 * inverted (INIT_NOT), or we hit INIT_RESUME
2589 */
2590
2591 uint8_t cond = bios->data[offset + 1];
2592
2593 if (!iexec->execute)
37383650 2594 return 2;
6ee73861
BS		 2595
2596 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2597
2598 if (io_condition_met(bios, offset, cond))
2599 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2600 else {
2601 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2602 iexec->execute = false;
2603 }
2604
37383650 2605 return 2;
6ee73861
BS		 2606}
2607
37383650 2608static int
6ee73861
BS		 2609init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2610{
2611 /*
2612 * INIT_INDEX_IO opcode: 0x78 ('x')
2613 *
2614 * offset (8 bit): opcode
2615 * offset + 1 (16 bit): CRTC port
2616 * offset + 3 (8 bit): CRTC index
2617 * offset + 4 (8 bit): mask
2618 * offset + 5 (8 bit): data
2619 *
2620 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2621 * OR with "data", write-back
2622 */
2623
2624 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2625 uint8_t crtcindex = bios->data[offset + 3];
2626 uint8_t mask = bios->data[offset + 4];
2627 uint8_t data = bios->data[offset + 5];
2628 uint8_t value;
2629
2630 if (!iexec->execute)
37383650 2631 return 6;
6ee73861
BS		 2632
2633 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2634 "Data: 0x%02X\n",
2635 offset, crtcport, crtcindex, mask, data);
2636
2637 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2638 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2639
37383650 2640 return 6;
6ee73861
BS		 2641}
2642
37383650 2643static int
6ee73861
BS		 2644init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2645{
2646 /*
2647 * INIT_PLL opcode: 0x79 ('y')
2648 *
2649 * offset (8 bit): opcode
2650 * offset + 1 (32 bit): register
2651 * offset + 5 (16 bit): freq
2652 *
2653 * Set PLL register "register" to coefficients for frequency (10kHz)
2654 * "freq"
2655 */
2656
2657 uint32_t reg = ROM32(bios->data[offset + 1]);
2658 uint16_t freq = ROM16(bios->data[offset + 5]);
2659
2660 if (!iexec->execute)
37383650 2661 return 7;
6ee73861
BS		 2662
2663 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2664
2665 setPLL(bios, reg, freq * 10);
2666
37383650 2667 return 7;
6ee73861
BS		 2668}
2669
37383650 2670static int
6ee73861
BS		 2671init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2672{
2673 /*
2674 * INIT_ZM_REG opcode: 0x7A ('z')
2675 *
2676 * offset (8 bit): opcode
2677 * offset + 1 (32 bit): register
2678 * offset + 5 (32 bit): value
2679 *
2680 * Assign "value" to "register"
2681 */
2682
2683 uint32_t reg = ROM32(bios->data[offset + 1]);
2684 uint32_t value = ROM32(bios->data[offset + 5]);
2685
2686 if (!iexec->execute)
37383650 2687 return 9;
6ee73861
BS		 2688
2689 if (reg == 0x000200)
2690 value |= 1;
2691
2692 bios_wr32(bios, reg, value);
2693
37383650 2694 return 9;
6ee73861
BS		 2695}
2696
37383650 2697static int
6ee73861
BS		 2698init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2699 struct init_exec *iexec)
2700{
2701 /*
2702 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2703 *
2704 * offset (8 bit): opcode
2705 * offset + 1 (8 bit): PLL type
2706 * offset + 2 (32 bit): frequency 0
2707 *
2708 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2709 * ram_restrict_table_ptr. The value read from there is used to select
2710 * a frequency from the table starting at 'frequency 0' to be
2711 * programmed into the PLL corresponding to 'type'.
2712 *
2713 * The PLL limits table on cards using this opcode has a mapping of
2714 * 'type' to the relevant registers.
2715 */
2716
2717 struct drm_device *dev = bios->dev;
2718 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2719 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2720 uint8_t type = bios->data[offset + 1];
2721 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2722 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 2723 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 2724 int i;
2725
2726 if (!iexec->execute)
37383650 2727 return len;
6ee73861
BS		 2728
2729 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2730 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 2731 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 2732 }
2733
2734 entry = pll_limits + pll_limits[1];
2735 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2736 if (entry[0] == type) {
2737 uint32_t reg = ROM32(entry[3]);
2738
2739 BIOSLOG(bios, "0x%04X: "
2740 "Type %02x Reg 0x%08x Freq %dKHz\n",
2741 offset, type, reg, freq);
2742
2743 setPLL(bios, reg, freq);
37383650 2744 return len;
6ee73861
BS		 2745 }
2746 }
2747
2748 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 2749 return len;
6ee73861
BS		 2750}
2751
37383650 2752static int
6ee73861
BS		 2753init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2754{
2755 /*
2756 * INIT_8C opcode: 0x8C ('')
2757 *
2758 * NOP so far....
2759 *
2760 */
2761
37383650 2762 return 1;
6ee73861
BS		 2763}
2764
37383650 2765static int
6ee73861
BS		 2766init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2767{
2768 /*
2769 * INIT_8D opcode: 0x8D ('')
2770 *
2771 * NOP so far....
2772 *
2773 */
2774
37383650 2775 return 1;
6ee73861
BS		 2776}
2777
37383650 2778static int
6ee73861
BS		 2779init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2780{
2781 /*
2782 * INIT_GPIO opcode: 0x8E ('')
2783 *
2784 * offset (8 bit): opcode
2785 *
2786 * Loop over all entries in the DCB GPIO table, and initialise
2787 * each GPIO according to various values listed in each entry
2788 */
2789
2535d71c 2790 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
6ee73861 2791 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
6ee73861
BS		 2792 int i;
2793
2535d71c
BS		 2794 if (dev_priv->card_type != NV_50) {
2795 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
2796 return -ENODEV;
6ee73861
BS		 2797 }
2798
2535d71c
BS		 2799 if (!iexec->execute)
2800 return 1;
6ee73861 2801
2535d71c
BS		 2802 for (i = 0; i < bios->dcb.gpio.entries; i++) {
2803 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
2804 uint32_t r, s, v;
6ee73861 2805
2535d71c 2806 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 2807
45284162 2808 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default);
6ee73861 2809
45284162
BS		 2810 /* The NVIDIA binary driver doesn't appear to actually do
2811 * any of this, my VBIOS does however.
2812 */
2813 /* Not a clue, needs de-magicing */
2535d71c
BS		 2814 r = nv50_gpio_ctl[gpio->line >> 4];
2815 s = (gpio->line & 0x0f);
6ee73861 2816 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2535d71c 2817 switch ((gpio->entry & 0x06000000) >> 25) {
6ee73861
BS		 2818 case 1:
2819 v |= (0x00000001 << s);
2820 break;
2821 case 2:
2822 v |= (0x00010000 << s);
2823 break;
2824 default:
2825 break;
2826 }
2827 bios_wr32(bios, r, v);
2828 }
2829
37383650 2830 return 1;
6ee73861
BS		 2831}
2832
37383650 2833static int
6ee73861
BS		 2834init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2835 struct init_exec *iexec)
2836{
2837 /*
2838 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2839 *
2840 * offset (8 bit): opcode
2841 * offset + 1 (32 bit): reg
2842 * offset + 5 (8 bit): regincrement
2843 * offset + 6 (8 bit): count
2844 * offset + 7 (32 bit): value 1,1
2845 * ...
2846 *
2847 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2848 * ram_restrict_table_ptr. The value read from here is 'n', and
2849 * "value 1,n" gets written to "reg". This repeats "count" times and on
2850 * each iteration 'm', "reg" increases by "regincrement" and
2851 * "value m,n" is used. The extent of n is limited by a number read
2852 * from the 'M' BIT table, herein called "blocklen"
2853 */
2854
2855 uint32_t reg = ROM32(bios->data[offset + 1]);
2856 uint8_t regincrement = bios->data[offset + 5];
2857 uint8_t count = bios->data[offset + 6];
2858 uint32_t strap_ramcfg, data;
37383650
MK		 2859 /* previously set by 'M' BIT table */
2860 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2861 int len = 7 + count * blocklen;
6ee73861
BS		 2862 uint8_t index;
2863 int i;
2864
6ee73861
BS		 2865
2866 if (!iexec->execute)
37383650 2867 return len;
6ee73861
BS		 2868
2869 if (!blocklen) {
2870 NV_ERROR(bios->dev,
2871 "0x%04X: Zero block length - has the M table "
2872 "been parsed?\n", offset);
9170a824 2873 return -EINVAL;
6ee73861
BS		 2874 }
2875
2876 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2877 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2878
2879 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2880 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2881 offset, reg, regincrement, count, strap_ramcfg, index);
2882
2883 for (i = 0; i < count; i++) {
2884 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2885
2886 bios_wr32(bios, reg, data);
2887
2888 reg += regincrement;
2889 }
2890
37383650 2891 return len;
6ee73861
BS		 2892}
2893
37383650 2894static int
6ee73861
BS		 2895init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2896{
2897 /*
2898 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2899 *
2900 * offset (8 bit): opcode
2901 * offset + 1 (32 bit): src reg
2902 * offset + 5 (32 bit): dst reg
2903 *
2904 * Put contents of "src reg" into "dst reg"
2905 */
2906
2907 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2908 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2909
2910 if (!iexec->execute)
37383650 2911 return 9;
6ee73861
BS		 2912
2913 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2914
37383650 2915 return 9;
6ee73861
BS		 2916}
2917
37383650 2918static int
6ee73861
BS		 2919init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2920 struct init_exec *iexec)
2921{
2922 /*
2923 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2924 *
2925 * offset (8 bit): opcode
2926 * offset + 1 (32 bit): dst reg
2927 * offset + 5 (8 bit): count
2928 * offset + 6 (32 bit): data 1
2929 * ...
2930 *
2931 * For each of "count" values write "data n" to "dst reg"
2932 */
2933
2934 uint32_t reg = ROM32(bios->data[offset + 1]);
2935 uint8_t count = bios->data[offset + 5];
37383650 2936 int len = 6 + count * 4;
6ee73861
BS		 2937 int i;
2938
2939 if (!iexec->execute)
37383650 2940 return len;
6ee73861
BS		 2941
2942 for (i = 0; i < count; i++) {
2943 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2944 bios_wr32(bios, reg, data);
2945 }
2946
37383650 2947 return len;
6ee73861
BS		 2948}
2949
37383650 2950static int
6ee73861
BS		 2951init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2952{
2953 /*
2954 * INIT_RESERVED opcode: 0x92 ('')
2955 *
2956 * offset (8 bit): opcode
2957 *
2958 * Seemingly does nothing
2959 */
2960
37383650 2961 return 1;
6ee73861
BS		 2962}
2963
37383650 2964static int
6ee73861
BS		 2965init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2966{
2967 /*
2968 * INIT_96 opcode: 0x96 ('')
2969 *
2970 * offset (8 bit): opcode
2971 * offset + 1 (32 bit): sreg
2972 * offset + 5 (8 bit): sshift
2973 * offset + 6 (8 bit): smask
2974 * offset + 7 (8 bit): index
2975 * offset + 8 (32 bit): reg
2976 * offset + 12 (32 bit): mask
2977 * offset + 16 (8 bit): shift
2978 *
2979 */
2980
2981 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2982 uint32_t reg = ROM32(bios->data[offset + 8]);
2983 uint32_t mask = ROM32(bios->data[offset + 12]);
2984 uint32_t val;
2985
2986 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2987 if (bios->data[offset + 5] < 0x80)
2988 val >>= bios->data[offset + 5];
2989 else
2990 val <<= (0x100 - bios->data[offset + 5]);
2991 val &= bios->data[offset + 6];
2992
2993 val = bios->data[ROM16(bios->data[xlatptr]) + val];
2994 val <<= bios->data[offset + 16];
2995
2996 if (!iexec->execute)
37383650 2997 return 17;
6ee73861
BS		 2998
2999 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3000 return 17;
6ee73861
BS		 3001}
3002
37383650 3003static int
6ee73861
BS		 3004init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3005{
3006 /*
3007 * INIT_97 opcode: 0x97 ('')
3008 *
3009 * offset (8 bit): opcode
3010 * offset + 1 (32 bit): register
3011 * offset + 5 (32 bit): mask
3012 * offset + 9 (32 bit): value
3013 *
3014 * Adds "value" to "register" preserving the fields specified
3015 * by "mask"
3016 */
3017
3018 uint32_t reg = ROM32(bios->data[offset + 1]);
3019 uint32_t mask = ROM32(bios->data[offset + 5]);
3020 uint32_t add = ROM32(bios->data[offset + 9]);
3021 uint32_t val;
3022
3023 val = bios_rd32(bios, reg);
3024 val = (val & mask) | ((val + add) & ~mask);
3025
3026 if (!iexec->execute)
37383650 3027 return 13;
6ee73861
BS		 3028
3029 bios_wr32(bios, reg, val);
37383650 3030 return 13;
6ee73861
BS		 3031}
3032
37383650 3033static int
6ee73861
BS		 3034init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3035{
3036 /*
3037 * INIT_AUXCH opcode: 0x98 ('')
3038 *
3039 * offset (8 bit): opcode
3040 * offset + 1 (32 bit): address
3041 * offset + 5 (8 bit): count
3042 * offset + 6 (8 bit): mask 0
3043 * offset + 7 (8 bit): data 0
3044 * ...
3045 *
3046 */
3047
3048 struct drm_device *dev = bios->dev;
3049 struct nouveau_i2c_chan *auxch;
3050 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3051 uint8_t count = bios->data[offset + 5];
3052 int len = 6 + count * 2;
6ee73861
BS		 3053 int ret, i;
3054
3055 if (!bios->display.output) {
3056 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
9170a824 3057 return -EINVAL;
6ee73861
BS		 3058 }
3059
3060 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3061 if (!auxch) {
3062 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3063 bios->display.output->i2c_index);
9170a824 3064 return -ENODEV;
6ee73861
BS		 3065 }
3066
3067 if (!iexec->execute)
37383650 3068 return len;
6ee73861
BS		 3069
3070 offset += 6;
37383650 3071 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3072 uint8_t data;
3073
3074 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3075 if (ret) {
3076 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
9170a824 3077 return ret;
6ee73861
BS		 3078 }
3079
3080 data &= bios->data[offset + 0];
3081 data |= bios->data[offset + 1];
3082
3083 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3084 if (ret) {
3085 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
9170a824 3086 return ret;
6ee73861
BS		 3087 }
3088 }
3089
37383650 3090 return len;
6ee73861
BS		 3091}
3092
37383650 3093static int
6ee73861
BS		 3094init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3095{
3096 /*
3097 * INIT_ZM_AUXCH opcode: 0x99 ('')
3098 *
3099 * offset (8 bit): opcode
3100 * offset + 1 (32 bit): address
3101 * offset + 5 (8 bit): count
3102 * offset + 6 (8 bit): data 0
3103 * ...
3104 *
3105 */
3106
3107 struct drm_device *dev = bios->dev;
3108 struct nouveau_i2c_chan *auxch;
3109 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3110 uint8_t count = bios->data[offset + 5];
3111 int len = 6 + count;
6ee73861
BS		 3112 int ret, i;
3113
3114 if (!bios->display.output) {
3115 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
9170a824 3116 return -EINVAL;
6ee73861
BS		 3117 }
3118
3119 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3120 if (!auxch) {
3121 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3122 bios->display.output->i2c_index);
9170a824 3123 return -ENODEV;
6ee73861
BS		 3124 }
3125
3126 if (!iexec->execute)
37383650 3127 return len;
6ee73861
BS		 3128
3129 offset += 6;
37383650 3130 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3131 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3132 if (ret) {
3133 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
9170a824 3134 return ret;
6ee73861
BS		 3135 }
3136 }
3137
37383650 3138 return len;
6ee73861
BS		 3139}
3140
3141static struct init_tbl_entry itbl_entry[] = {
3142 /* command name , id , length , offset , mult , command handler */
3143 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3144 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3145 { "INIT_REPEAT" , 0x33, init_repeat },
3146 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3147 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3148 { "INIT_COPY" , 0x37, init_copy },
3149 { "INIT_NOT" , 0x38, init_not },
3150 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3151 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3152 { "INIT_OP_3B" , 0x3B, init_op_3b },
3153 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3154 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3155 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3156 { "INIT_PLL2" , 0x4B, init_pll2 },
3157 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3158 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3159 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3160 { "INIT_TMDS" , 0x4F, init_tmds },
3161 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3162 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3163 { "INIT_CR" , 0x52, init_cr },
3164 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3165 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3166 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3167 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3168 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 3169 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3170 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3171 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3172 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3173 { "INIT_RESET" , 0x65, init_reset },
3174 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3175 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3176 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3177 { "INIT_IO" , 0x69, init_io },
3178 { "INIT_SUB" , 0x6B, init_sub },
3179 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3180 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3181 { "INIT_MACRO" , 0x6F, init_macro },
3182 { "INIT_DONE" , 0x71, init_done },
3183 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3184 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3185 { "INIT_TIME" , 0x74, init_time },
3186 { "INIT_CONDITION" , 0x75, init_condition },
3187 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3188 { "INIT_INDEX_IO" , 0x78, init_index_io },
3189 { "INIT_PLL" , 0x79, init_pll },
3190 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3191 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3192 { "INIT_8C" , 0x8C, init_8c },
3193 { "INIT_8D" , 0x8D, init_8d },
3194 { "INIT_GPIO" , 0x8E, init_gpio },
3195 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3196 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3197 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3198 { "INIT_RESERVED" , 0x92, init_reserved },
3199 { "INIT_96" , 0x96, init_96 },
3200 { "INIT_97" , 0x97, init_97 },
3201 { "INIT_AUXCH" , 0x98, init_auxch },
3202 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3203 { NULL , 0 , NULL }
6ee73861
BS		 3204};
3205
6ee73861
BS		 3206#define MAX_TABLE_OPS 1000
3207
3208static int
3209parse_init_table(struct nvbios *bios, unsigned int offset,
3210 struct init_exec *iexec)
3211{
3212 /*
3213 * Parses all commands in an init table.
3214 *
3215 * We start out executing all commands found in the init table. Some
3216 * opcodes may change the status of iexec->execute to SKIP, which will
3217 * cause the following opcodes to perform no operation until the value
3218 * is changed back to EXECUTE.
3219 */
3220
92b96187 3221 int count = 0, i, ret;
6ee73861
BS		 3222 uint8_t id;
3223
3224 /*
3225 * Loop until INIT_DONE causes us to break out of the loop
3226 * (or until offset > bios length just in case... )
3227 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3228 */
3229 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3230 id = bios->data[offset];
3231
3232 /* Find matching id in itbl_entry */
3233 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3234 ;
3235
92b96187 3236 if (!itbl_entry[i].name) {
6ee73861
BS		 3237 NV_ERROR(bios->dev,
3238 "0x%04X: Init table command not found: "
3239 "0x%02X\n", offset, id);
3240 return -ENOENT;
3241 }
92b96187
BS		 3242
3243 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3244 itbl_entry[i].id, itbl_entry[i].name);
3245
3246 /* execute eventual command handler */
3247 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3248 if (ret < 0) {
3249 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3250 "table opcode: %s %d\n", offset,
3251 itbl_entry[i].name, ret);
3252 }
3253
3254 if (ret <= 0)
3255 break;
3256
3257 /*
3258 * Add the offset of the current command including all data
3259 * of that command. The offset will then be pointing on the
3260 * next op code.
3261 */
3262 offset += ret;
6ee73861
BS		 3263 }
3264
3265 if (offset >= bios->length)
3266 NV_WARN(bios->dev,
3267 "Offset 0x%04X greater than known bios image length. "
3268 "Corrupt image?\n", offset);
3269 if (count >= MAX_TABLE_OPS)
3270 NV_WARN(bios->dev,
3271 "More than %d opcodes to a table is unlikely, "
3272 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3273
3274 return 0;
3275}
3276
3277static void
3278parse_init_tables(struct nvbios *bios)
3279{
3280 /* Loops and calls parse_init_table() for each present table. */
3281
3282 int i = 0;
3283 uint16_t table;
3284 struct init_exec iexec = {true, false};
3285
3286 if (bios->old_style_init) {
3287 if (bios->init_script_tbls_ptr)
3288 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3289 if (bios->extra_init_script_tbl_ptr)
3290 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3291
3292 return;
3293 }
3294
3295 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3296 NV_INFO(bios->dev,
3297 "Parsing VBIOS init table %d at offset 0x%04X\n",
3298 i / 2, table);
3299 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3300
3301 parse_init_table(bios, table, &iexec);
3302 i += 2;
3303 }
3304}
3305
3306static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3307{
3308 int compare_record_len, i = 0;
3309 uint16_t compareclk, scriptptr = 0;
3310
3311 if (bios->major_version < 5) /* pre BIT */
3312 compare_record_len = 3;
3313 else
3314 compare_record_len = 4;
3315
3316 do {
3317 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3318 if (pxclk >= compareclk * 10) {
3319 if (bios->major_version < 5) {
3320 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3321 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3322 } else
3323 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3324 break;
3325 }
3326 i++;
3327 } while (compareclk);
3328
3329 return scriptptr;
3330}
3331
3332static void
3333run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3334 struct dcb_entry *dcbent, int head, bool dl)
3335{
3336 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3337 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3338 struct init_exec iexec = {true, false};
3339
3340 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3341 scriptptr);
3342 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3343 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3344 /* note: if dcb entries have been merged, index may be misleading */
3345 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3346 parse_init_table(bios, scriptptr, &iexec);
3347
3348 nv04_dfp_bind_head(dev, dcbent, head, dl);
3349}
3350
3351static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3352{
3353 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3354 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3355 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3356 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3357
3358 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3359 return -EINVAL;
3360
3361 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3362
3363 if (script == LVDS_PANEL_OFF) {
3364 /* off-on delay in ms */
3365 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3366 }
3367#ifdef __powerpc__
3368 /* Powerbook specific quirks */
3d9aefb8
FJ		 3369 if ((dev->pci_device & 0xffff) == 0x0179 ||
3370 (dev->pci_device & 0xffff) == 0x0189 ||
3371 (dev->pci_device & 0xffff) == 0x0329) {
3372 if (script == LVDS_RESET) {
3373 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3374
3375 } else if (script == LVDS_PANEL_ON) {
3376 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3377 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3378 | (1 << 31));
3379 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3380 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3381
3382 } else if (script == LVDS_PANEL_OFF) {
3383 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3384 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3385 & ~(1 << 31));
3386 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3387 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3388 }
3389 }
3390#endif
3391
3392 return 0;
3393}
3394
3395static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3396{
3397 /*
3398 * The BIT LVDS table's header has the information to setup the
3399 * necessary registers. Following the standard 4 byte header are:
3400 * A bitmask byte and a dual-link transition pxclk value for use in
3401 * selecting the init script when not using straps; 4 script pointers
3402 * for panel power, selected by output and on/off; and 8 table pointers
3403 * for panel init, the needed one determined by output, and bits in the
3404 * conf byte. These tables are similar to the TMDS tables, consisting
3405 * of a list of pxclks and script pointers.
3406 */
3407 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3408 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3409 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3410 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3411
3412 /*
3413 * For now we assume version 3.0 table - g80 support will need some
3414 * changes
3415 */
3416
3417 switch (script) {
3418 case LVDS_INIT:
3419 return -ENOSYS;
3420 case LVDS_BACKLIGHT_ON:
3421 case LVDS_PANEL_ON:
3422 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3423 break;
3424 case LVDS_BACKLIGHT_OFF:
3425 case LVDS_PANEL_OFF:
3426 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3427 break;
3428 case LVDS_RESET:
f3bbb9cc
BS		 3429 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3430 if (dcbent->or == 4)
3431 clktable += 8;
3432
6ee73861
BS		 3433 if (dcbent->lvdsconf.use_straps_for_mode) {
3434 if (bios->fp.dual_link)
f3bbb9cc
BS		 3435 clktable += 4;
3436 if (bios->fp.if_is_24bit)
3437 clktable += 2;
6ee73861
BS		 3438 } else {
3439 /* using EDID */
f3bbb9cc 3440 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3441
3442 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3443 clktable += 4;
3444 cmpval_24bit <<= 1;
6ee73861 3445 }
f3bbb9cc
BS		 3446
3447 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3448 clktable += 2;
6ee73861
BS		 3449 }
3450
f3bbb9cc 3451 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3452 if (!clktable) {
3453 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3454 return -ENOENT;
3455 }
3456 scriptptr = clkcmptable(bios, clktable, pxclk);
3457 }
3458
3459 if (!scriptptr) {
3460 NV_ERROR(dev, "LVDS output init script not found\n");
3461 return -ENOENT;
3462 }
3463 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3464
3465 return 0;
3466}
3467
3468int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3469{
3470 /*
3471 * LVDS operations are multiplexed in an effort to present a single API
3472 * which works with two vastly differing underlying structures.
3473 * This acts as the demux
3474 */
3475
3476 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3477 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3478 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3479 uint32_t sel_clk_binding, sel_clk;
3480 int ret;
3481
3482 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3483 (lvds_ver >= 0x30 && script == LVDS_INIT))
3484 return 0;
3485
3486 if (!bios->fp.lvds_init_run) {
3487 bios->fp.lvds_init_run = true;
3488 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3489 }
3490
3491 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3492 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3493 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3494 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3495
3496 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3497
3498 /* don't let script change pll->head binding */
3499 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3500
3501 if (lvds_ver < 0x30)
3502 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3503 else
3504 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3505
3506 bios->fp.last_script_invoc = (script << 1 | head);
3507
3508 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3509 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3510 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3511 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3512
3513 return ret;
3514}
3515
3516struct lvdstableheader {
3517 uint8_t lvds_ver, headerlen, recordlen;
3518};
3519
3520static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3521{
3522 /*
3523 * BMP version (0xa) LVDS table has a simple header of version and
3524 * record length. The BIT LVDS table has the typical BIT table header:
3525 * version byte, header length byte, record length byte, and a byte for
3526 * the maximum number of records that can be held in the table.
3527 */
3528
3529 uint8_t lvds_ver, headerlen, recordlen;
3530
3531 memset(lth, 0, sizeof(struct lvdstableheader));
3532
3533 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3534 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3535 return -EINVAL;
3536 }
3537
3538 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3539
3540 switch (lvds_ver) {
3541 case 0x0a: /* pre NV40 */
3542 headerlen = 2;
3543 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3544 break;
3545 case 0x30: /* NV4x */
3546 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3547 if (headerlen < 0x1f) {
3548 NV_ERROR(dev, "LVDS table header not understood\n");
3549 return -EINVAL;
3550 }
3551 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3552 break;
3553 case 0x40: /* G80/G90 */
3554 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3555 if (headerlen < 0x7) {
3556 NV_ERROR(dev, "LVDS table header not understood\n");
3557 return -EINVAL;
3558 }
3559 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3560 break;
3561 default:
3562 NV_ERROR(dev,
3563 "LVDS table revision %d.%d not currently supported\n",
3564 lvds_ver >> 4, lvds_ver & 0xf);
3565 return -ENOSYS;
3566 }
3567
3568 lth->lvds_ver = lvds_ver;
3569 lth->headerlen = headerlen;
3570 lth->recordlen = recordlen;
3571
3572 return 0;
3573}
3574
3575static int
3576get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3577{
3578 struct drm_nouveau_private *dev_priv = dev->dev_private;
3579
3580 /*
3581 * The fp strap is normally dictated by the "User Strap" in
3582 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3583 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3584 * by the PCI subsystem ID during POST, but not before the previous user
3585 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3586 * read and used instead
3587 */
3588
3589 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3590 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3591
3592 if (dev_priv->card_type >= NV_50)
3593 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3594 else
3595 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3596}
3597
3598static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3599{
3600 uint8_t *fptable;
3601 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3602 int ret, ofs, fpstrapping;
3603 struct lvdstableheader lth;
3604
3605 if (bios->fp.fptablepointer == 0x0) {
3606 /* Apple cards don't have the fp table; the laptops use DDC */
3607 /* The table is also missing on some x86 IGPs */
3608#ifndef __powerpc__
3609 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3610#endif
04a39c57 3611 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3612 return 0;
3613 }
3614
3615 fptable = &bios->data[bios->fp.fptablepointer];
3616 fptable_ver = fptable[0];
3617
3618 switch (fptable_ver) {
3619 /*
3620 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3621 * version field, and miss one of the spread spectrum/PWM bytes.
3622 * This could affect early GF2Go parts (not seen any appropriate ROMs
3623 * though). Here we assume that a version of 0x05 matches this case
3624 * (combining with a BMP version check would be better), as the
3625 * common case for the panel type field is 0x0005, and that is in
3626 * fact what we are reading the first byte of.
3627 */
3628 case 0x05: /* some NV10, 11, 15, 16 */
3629 recordlen = 42;
3630 ofs = -1;
3631 break;
3632 case 0x10: /* some NV15/16, and NV11+ */
3633 recordlen = 44;
3634 ofs = 0;
3635 break;
3636 case 0x20: /* NV40+ */
3637 headerlen = fptable[1];
3638 recordlen = fptable[2];
3639 fpentries = fptable[3];
3640 /*
3641 * fptable[4] is the minimum
3642 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3643 */
04a39c57 3644 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 3645 ofs = -7;
3646 break;
3647 default:
3648 NV_ERROR(dev,
3649 "FP table revision %d.%d not currently supported\n",
3650 fptable_ver >> 4, fptable_ver & 0xf);
3651 return -ENOSYS;
3652 }
3653
3654 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3655 return 0;
3656
3657 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3658 if (ret)
3659 return ret;
3660
3661 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3662 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3663 lth.headerlen + 1;
3664 bios->fp.xlatwidth = lth.recordlen;
3665 }
3666 if (bios->fp.fpxlatetableptr == 0x0) {
3667 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3668 return -EINVAL;
3669 }
3670
3671 fpstrapping = get_fp_strap(dev, bios);
3672
3673 fpindex = bios->data[bios->fp.fpxlatetableptr +
3674 fpstrapping * bios->fp.xlatwidth];
3675
3676 if (fpindex > fpentries) {
3677 NV_ERROR(dev, "Bad flat panel table index\n");
3678 return -ENOENT;
3679 }
3680
3681 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3682 if (lth.lvds_ver > 0x10)
04a39c57 3683 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 3684
3685 /*
3686 * If either the strap or xlated fpindex value are 0xf there is no
3687 * panel using a strap-derived bios mode present. this condition
3688 * includes, but is different from, the DDC panel indicator above
3689 */
3690 if (fpstrapping == 0xf || fpindex == 0xf)
3691 return 0;
3692
3693 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3694 recordlen * fpindex + ofs;
3695
3696 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3697 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3698 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3699 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3700
3701 return 0;
3702}
3703
3704bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3705{
3706 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3707 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3708 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3709
3710 if (!mode) /* just checking whether we can produce a mode */
3711 return bios->fp.mode_ptr;
3712
3713 memset(mode, 0, sizeof(struct drm_display_mode));
3714 /*
3715 * For version 1.0 (version in byte 0):
3716 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3717 * single/dual link, and type (TFT etc.)
3718 * bytes 3-6 are bits per colour in RGBX
3719 */
3720 mode->clock = ROM16(mode_entry[7]) * 10;
3721 /* bytes 9-10 is HActive */
3722 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3723 /*
3724 * bytes 13-14 is HValid Start
3725 * bytes 15-16 is HValid End
3726 */
3727 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3728 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3729 mode->htotal = ROM16(mode_entry[21]) + 1;
3730 /* bytes 23-24, 27-30 similarly, but vertical */
3731 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3732 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3733 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3734 mode->vtotal = ROM16(mode_entry[35]) + 1;
3735 mode->flags |= (mode_entry[37] & 0x10) ?
3736 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3737 mode->flags |= (mode_entry[37] & 0x1) ?
3738 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3739 /*
3740 * bytes 38-39 relate to spread spectrum settings
3741 * bytes 40-43 are something to do with PWM
3742 */
3743
3744 mode->status = MODE_OK;
3745 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3746 drm_mode_set_name(mode);
3747 return bios->fp.mode_ptr;
3748}
3749
3750int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3751{
3752 /*
3753 * The LVDS table header is (mostly) described in
3754 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3755 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3756 * straps are not being used for the panel, this specifies the frequency
3757 * at which modes should be set up in the dual link style.
3758 *
3759 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 3760 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 3761 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3762 * numbers for use by INIT_SUB which controlled panel init and power,
3763 * and finally a dword of ms to sleep between power off and on
3764 * operations.
3765 *
3766 * In the BIT versions, the table following the header serves as an
3767 * integrated config and xlat table: the records in the table are
3768 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3769 * two bytes - the first as a config byte, the second for indexing the
3770 * fp mode table pointed to by the BIT 'D' table
3771 *
3772 * DDC is not used until after card init, so selecting the correct table
3773 * entry and setting the dual link flag for EDID equipped panels,
3774 * requiring tests against the native-mode pixel clock, cannot be done
3775 * until later, when this function should be called with non-zero pxclk
3776 */
3777 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3778 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3779 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3780 struct lvdstableheader lth;
3781 uint16_t lvdsofs;
04a39c57 3782 int ret, chip_version = bios->chip_version;
6ee73861
BS		 3783
3784 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3785 if (ret)
3786 return ret;
3787
3788 switch (lth.lvds_ver) {
3789 case 0x0a: /* pre NV40 */
3790 lvdsmanufacturerindex = bios->data[
3791 bios->fp.fpxlatemanufacturertableptr +
3792 fpstrapping];
3793
3794 /* we're done if this isn't the EDID panel case */
3795 if (!pxclk)
3796 break;
3797
3798 if (chip_version < 0x25) {
3799 /* nv17 behaviour
3800 *
3801 * It seems the old style lvds script pointer is reused
3802 * to select 18/24 bit colour depth for EDID panels.
3803 */
3804 lvdsmanufacturerindex =
3805 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3806 2 : 0;
3807 if (pxclk >= bios->fp.duallink_transition_clk)
3808 lvdsmanufacturerindex++;
3809 } else if (chip_version < 0x30) {
3810 /* nv28 behaviour (off-chip encoder)
3811 *
3812 * nv28 does a complex dance of first using byte 121 of
3813 * the EDID to choose the lvdsmanufacturerindex, then
3814 * later attempting to match the EDID manufacturer and
3815 * product IDs in a table (signature 'pidt' (panel id
3816 * table?)), setting an lvdsmanufacturerindex of 0 and
3817 * an fp strap of the match index (or 0xf if none)
3818 */
3819 lvdsmanufacturerindex = 0;
3820 } else {
3821 /* nv31, nv34 behaviour */
3822 lvdsmanufacturerindex = 0;
3823 if (pxclk >= bios->fp.duallink_transition_clk)
3824 lvdsmanufacturerindex = 2;
3825 if (pxclk >= 140000)
3826 lvdsmanufacturerindex = 3;
3827 }
3828
3829 /*
3830 * nvidia set the high nibble of (cr57=f, cr58) to
3831 * lvdsmanufacturerindex in this case; we don't
3832 */
3833 break;
3834 case 0x30: /* NV4x */
3835 case 0x40: /* G80/G90 */
3836 lvdsmanufacturerindex = fpstrapping;
3837 break;
3838 default:
3839 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3840 return -ENOSYS;
3841 }
3842
3843 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3844 switch (lth.lvds_ver) {
3845 case 0x0a:
3846 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3847 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3848 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3849 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3850 *if_is_24bit = bios->data[lvdsofs] & 16;
3851 break;
3852 case 0x30:
f3bbb9cc 3853 case 0x40:
6ee73861
BS		 3854 /*
3855 * No sign of the "power off for reset" or "reset for panel
3856 * on" bits, but it's safer to assume we should
3857 */
3858 bios->fp.power_off_for_reset = true;
3859 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 3860
6ee73861
BS		 3861 /*
3862 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 3863 * over-written, and if_is_24bit isn't used
6ee73861
BS		 3864 */
3865 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 3866 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3867 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3868 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3869 break;
3870 }
3871
2eb92c80
BS		 3872 /* Dell Latitude D620 reports a too-high value for the dual-link
3873 * transition freq, causing us to program the panel incorrectly.
3874 *
3875 * It doesn't appear the VBIOS actually uses its transition freq
3876 * (90000kHz), instead it uses the "Number of LVDS channels" field
3877 * out of the panel ID structure (http://www.spwg.org/).
3878 *
3879 * For the moment, a quirk will do :)
3880 */
3881 if ((dev->pdev->device == 0x01d7) &&
3882 (dev->pdev->subsystem_vendor == 0x1028) &&
3883 (dev->pdev->subsystem_device == 0x01c2)) {
3884 bios->fp.duallink_transition_clk = 80000;
3885 }
3886
6ee73861
BS		 3887 /* set dual_link flag for EDID case */
3888 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3889 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3890
3891 *dl = bios->fp.dual_link;
3892
3893 return 0;
3894}
3895
3896static uint8_t *
3897bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3898 uint16_t record, int record_len, int record_nr)
3899{
3900 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3901 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3902 uint32_t entry;
3903 uint16_t table;
3904 int i, v;
3905
3906 for (i = 0; i < record_nr; i++, record += record_len) {
3907 table = ROM16(bios->data[record]);
3908 if (!table)
3909 continue;
3910 entry = ROM32(bios->data[table]);
3911
3912 v = (entry & 0x000f0000) >> 16;
3913 if (!(v & dcbent->or))
3914 continue;
3915
3916 v = (entry & 0x000000f0) >> 4;
3917 if (v != dcbent->location)
3918 continue;
3919
3920 v = (entry & 0x0000000f);
3921 if (v != dcbent->type)
3922 continue;
3923
3924 return &bios->data[table];
3925 }
3926
3927 return NULL;
3928}
3929
3930void *
3931nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3932 int *length)
3933{
3934 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3935 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3936 uint8_t *table;
3937
3938 if (!bios->display.dp_table_ptr) {
3939 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3940 return NULL;
3941 }
3942 table = &bios->data[bios->display.dp_table_ptr];
3943
c52e53fd 3944 if (table[0] != 0x20 && table[0] != 0x21) {
6ee73861
BS		 3945 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3946 table[0]);
3947 return NULL;
3948 }
3949
3950 *length = table[4];
3951 return bios_output_config_match(dev, dcbent,
3952 bios->display.dp_table_ptr + table[1],
3953 table[2], table[3]);
3954}
3955
3956int
3957nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3958 uint32_t sub, int pxclk)
3959{
3960 /*
3961 * The display script table is located by the BIT 'U' table.
3962 *
3963 * It contains an array of pointers to various tables describing
3964 * a particular output type. The first 32-bits of the output
3965 * tables contains similar information to a DCB entry, and is
3966 * used to decide whether that particular table is suitable for
3967 * the output you want to access.
3968 *
3969 * The "record header length" field here seems to indicate the
3970 * offset of the first configuration entry in the output tables.
3971 * This is 10 on most cards I've seen, but 12 has been witnessed
3972 * on DP cards, and there's another script pointer within the
3973 * header.
3974 *
3975 * offset + 0 ( 8 bits): version
3976 * offset + 1 ( 8 bits): header length
3977 * offset + 2 ( 8 bits): record length
3978 * offset + 3 ( 8 bits): number of records
3979 * offset + 4 ( 8 bits): record header length
3980 * offset + 5 (16 bits): pointer to first output script table
3981 */
3982
3983 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3984 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3985 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3986 uint8_t *otable = NULL;
3987 uint16_t script;
3988 int i = 0;
3989
3990 if (!bios->display.script_table_ptr) {
3991 NV_ERROR(dev, "No pointer to output script table\n");
3992 return 1;
3993 }
3994
3995 /*
3996 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3997 * so until they are, we really don't need to care.
3998 */
3999 if (table[0] < 0x20)
4000 return 1;
4001
4002 if (table[0] != 0x20 && table[0] != 0x21) {
4003 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4004 table[0]);
4005 return 1;
4006 }
4007
4008 /*
4009 * The output script tables describing a particular output type
4010 * look as follows:
4011 *
4012 * offset + 0 (32 bits): output this table matches (hash of DCB)
4013 * offset + 4 ( 8 bits): unknown
4014 * offset + 5 ( 8 bits): number of configurations
4015 * offset + 6 (16 bits): pointer to some script
4016 * offset + 8 (16 bits): pointer to some script
4017 *
4018 * headerlen == 10
4019 * offset + 10 : configuration 0
4020 *
4021 * headerlen == 12
4022 * offset + 10 : pointer to some script
4023 * offset + 12 : configuration 0
4024 *
4025 * Each config entry is as follows:
4026 *
4027 * offset + 0 (16 bits): unknown, assumed to be a match value
4028 * offset + 2 (16 bits): pointer to script table (clock set?)
4029 * offset + 4 (16 bits): pointer to script table (reset?)
4030 *
4031 * There doesn't appear to be a count value to say how many
4032 * entries exist in each script table, instead, a 0 value in
4033 * the first 16-bit word seems to indicate both the end of the
4034 * list and the default entry. The second 16-bit word in the
4035 * script tables is a pointer to the script to execute.
4036 */
4037
ef2bb506 4038 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 4039 dcbent->type, dcbent->location, dcbent->or);
4040 otable = bios_output_config_match(dev, dcbent, table[1] +
4041 bios->display.script_table_ptr,
4042 table[2], table[3]);
4043 if (!otable) {
4044 NV_ERROR(dev, "Couldn't find matching output script table\n");
4045 return 1;
4046 }
4047
4048 if (pxclk < -2 || pxclk > 0) {
4049 /* Try to find matching script table entry */
4050 for (i = 0; i < otable[5]; i++) {
4051 if (ROM16(otable[table[4] + i*6]) == sub)
4052 break;
4053 }
4054
4055 if (i == otable[5]) {
4056 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4057 "using first\n",
4058 sub, dcbent->type, dcbent->or);
4059 i = 0;
4060 }
4061 }
4062
6ee73861
BS		 4063 if (pxclk == 0) {
4064 script = ROM16(otable[6]);
4065 if (!script) {
ef2bb506 4066 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4067 return 1;
4068 }
4069
4070 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 4071 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4072 } else
4073 if (pxclk == -1) {
4074 script = ROM16(otable[8]);
4075 if (!script) {
ef2bb506 4076 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4077 return 1;
4078 }
4079
4080 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 4081 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4082 } else
4083 if (pxclk == -2) {
4084 if (table[4] >= 12)
4085 script = ROM16(otable[10]);
4086 else
4087 script = 0;
4088 if (!script) {
ef2bb506 4089 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4090 return 1;
4091 }
4092
4093 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 4094 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4095 } else
4096 if (pxclk > 0) {
4097 script = ROM16(otable[table[4] + i*6 + 2]);
4098 if (script)
4099 script = clkcmptable(bios, script, pxclk);
4100 if (!script) {
4101 NV_ERROR(dev, "clock script 0 not found\n");
4102 return 1;
4103 }
4104
4105 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 4106 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4107 } else
4108 if (pxclk < 0) {
4109 script = ROM16(otable[table[4] + i*6 + 4]);
4110 if (script)
4111 script = clkcmptable(bios, script, -pxclk);
4112 if (!script) {
ef2bb506 4113 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4114 return 1;
4115 }
4116
4117 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 4118 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4119 }
4120
4121 return 0;
4122}
4123
4124
4125int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4126{
4127 /*
4128 * the pxclk parameter is in kHz
4129 *
4130 * This runs the TMDS regs setting code found on BIT bios cards
4131 *
4132 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4133 * ffs(or) == 3, use the second.
4134 */
4135
4136 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4137 struct nvbios *bios = &dev_priv->vbios;
4138 int cv = bios->chip_version;
6ee73861
BS		 4139 uint16_t clktable = 0, scriptptr;
4140 uint32_t sel_clk_binding, sel_clk;
4141
4142 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4143 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4144 dcbent->location != DCB_LOC_ON_CHIP)
4145 return 0;
4146
4147 switch (ffs(dcbent->or)) {
4148 case 1:
4149 clktable = bios->tmds.output0_script_ptr;
4150 break;
4151 case 2:
4152 case 3:
4153 clktable = bios->tmds.output1_script_ptr;
4154 break;
4155 }
4156
4157 if (!clktable) {
4158 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4159 return -EINVAL;
4160 }
4161
4162 scriptptr = clkcmptable(bios, clktable, pxclk);
4163
4164 if (!scriptptr) {
4165 NV_ERROR(dev, "TMDS output init script not found\n");
4166 return -ENOENT;
4167 }
4168
4169 /* don't let script change pll->head binding */
4170 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4171 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4172 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4173 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4174
4175 return 0;
4176}
4177
4178int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4179{
4180 /*
4181 * PLL limits table
4182 *
4183 * Version 0x10: NV30, NV31
4184 * One byte header (version), one record of 24 bytes
4185 * Version 0x11: NV36 - Not implemented
4186 * Seems to have same record style as 0x10, but 3 records rather than 1
4187 * Version 0x20: Found on Geforce 6 cards
4188 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4189 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4190 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4191 * length in general, some (integrated) have an extra configuration byte
4192 * Version 0x30: Found on Geforce 8, separates the register mapping
4193 * from the limits tables.
4194 */
4195
4196 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4197 struct nvbios *bios = &dev_priv->vbios;
4198 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4199 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4200 uint32_t crystal_strap_mask, crystal_straps;
4201
4202 if (!bios->pll_limit_tbl_ptr) {
4203 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4204 cv >= 0x40) {
4205 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4206 return -EINVAL;
4207 }
4208 } else
4209 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4210
4211 crystal_strap_mask = 1 << 6;
4212 /* open coded dev->twoHeads test */
4213 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4214 crystal_strap_mask |= 1 << 22;
4215 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4216 crystal_strap_mask;
4217
4218 switch (pll_lim_ver) {
4219 /*
4220 * We use version 0 to indicate a pre limit table bios (single stage
4221 * pll) and load the hard coded limits instead.
4222 */
4223 case 0:
4224 break;
4225 case 0x10:
4226 case 0x11:
4227 /*
4228 * Strictly v0x11 has 3 entries, but the last two don't seem
4229 * to get used.
4230 */
4231 headerlen = 1;
4232 recordlen = 0x18;
4233 entries = 1;
4234 pllindex = 0;
4235 break;
4236 case 0x20:
4237 case 0x21:
4238 case 0x30:
4239 case 0x40:
4240 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4241 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4242 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4243 break;
4244 default:
4245 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4246 "supported\n", pll_lim_ver);
4247 return -ENOSYS;
4248 }
4249
4250 /* initialize all members to zero */
4251 memset(pll_lim, 0, sizeof(struct pll_lims));
4252
4253 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4254 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4255
4256 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4257 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4258 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4259 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4260 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4261 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4262 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4263
4264 /* these values taken from nv30/31/36 */
4265 pll_lim->vco1.min_n = 0x1;
4266 if (cv == 0x36)
4267 pll_lim->vco1.min_n = 0x5;
4268 pll_lim->vco1.max_n = 0xff;
4269 pll_lim->vco1.min_m = 0x1;
4270 pll_lim->vco1.max_m = 0xd;
4271 pll_lim->vco2.min_n = 0x4;
4272 /*
4273 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4274 * table version (apart from nv35)), N2 is compared to
4275 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4276 * save a comparison
4277 */
4278 pll_lim->vco2.max_n = 0x28;
4279 if (cv == 0x30 || cv == 0x35)
4280 /* only 5 bits available for N2 on nv30/35 */
4281 pll_lim->vco2.max_n = 0x1f;
4282 pll_lim->vco2.min_m = 0x1;
4283 pll_lim->vco2.max_m = 0x4;
4284 pll_lim->max_log2p = 0x7;
4285 pll_lim->max_usable_log2p = 0x6;
4286 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4287 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4288 uint32_t reg = 0; /* default match */
4289 uint8_t *pll_rec;
4290 int i;
4291
4292 /*
4293 * First entry is default match, if nothing better. warn if
4294 * reg field nonzero
4295 */
4296 if (ROM32(bios->data[plloffs]))
4297 NV_WARN(dev, "Default PLL limit entry has non-zero "
4298 "register field\n");
4299
4300 if (limit_match > MAX_PLL_TYPES)
4301 /* we've been passed a reg as the match */
4302 reg = limit_match;
4303 else /* limit match is a pll type */
4304 for (i = 1; i < entries && !reg; i++) {
4305 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4306
4307 if (limit_match == NVPLL &&
4308 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4309 reg = cmpreg;
4310 if (limit_match == MPLL &&
4311 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4312 reg = cmpreg;
4313 if (limit_match == VPLL1 &&
4314 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4315 reg = cmpreg;
4316 if (limit_match == VPLL2 &&
4317 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4318 reg = cmpreg;
4319 }
4320
4321 for (i = 1; i < entries; i++)
4322 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4323 pllindex = i;
4324 break;
4325 }
4326
4327 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4328
4329 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4330 pllindex ? reg : 0);
4331
4332 /*
4333 * Frequencies are stored in tables in MHz, kHz are more
4334 * useful, so we convert.
4335 */
4336
4337 /* What output frequencies can each VCO generate? */
4338 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4339 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4340 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4341 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4342
4343 /* What input frequencies they accept (past the m-divider)? */
4344 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4345 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4346 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4347 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4348
4349 /* What values are accepted as multiplier and divider? */
4350 pll_lim->vco1.min_n = pll_rec[20];
4351 pll_lim->vco1.max_n = pll_rec[21];
4352 pll_lim->vco1.min_m = pll_rec[22];
4353 pll_lim->vco1.max_m = pll_rec[23];
4354 pll_lim->vco2.min_n = pll_rec[24];
4355 pll_lim->vco2.max_n = pll_rec[25];
4356 pll_lim->vco2.min_m = pll_rec[26];
4357 pll_lim->vco2.max_m = pll_rec[27];
4358
4359 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4360 if (pll_lim->max_log2p > 0x7)
4361 /* pll decoding in nv_hw.c assumes never > 7 */
4362 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4363 pll_lim->max_log2p);
4364 if (cv < 0x60)
4365 pll_lim->max_usable_log2p = 0x6;
4366 pll_lim->log2p_bias = pll_rec[30];
4367
4368 if (recordlen > 0x22)
4369 pll_lim->refclk = ROM32(pll_rec[31]);
4370
4371 if (recordlen > 0x23 && pll_rec[35])
4372 NV_WARN(dev,
4373 "Bits set in PLL configuration byte (%x)\n",
4374 pll_rec[35]);
4375
4376 /* C51 special not seen elsewhere */
4377 if (cv == 0x51 && !pll_lim->refclk) {
4378 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4379
4380 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4381 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4382 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4383 pll_lim->refclk = 200000;
4384 else
4385 pll_lim->refclk = 25000;
4386 }
4387 }
4388 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4389 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4390 uint8_t *record = NULL;
4391 int i;
4392
4393 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4394 limit_match);
4395
4396 for (i = 0; i < entries; i++, entry += recordlen) {
4397 if (ROM32(entry[3]) == limit_match) {
4398 record = &bios->data[ROM16(entry[1])];
4399 break;
4400 }
4401 }
4402
4403 if (!record) {
4404 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4405 "limits table", limit_match);
4406 return -ENOENT;
4407 }
4408
4409 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4410 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4411 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4412 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4413 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4414 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4415 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4416 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4417 pll_lim->vco1.min_n = record[16];
4418 pll_lim->vco1.max_n = record[17];
4419 pll_lim->vco1.min_m = record[18];
4420 pll_lim->vco1.max_m = record[19];
4421 pll_lim->vco2.min_n = record[20];
4422 pll_lim->vco2.max_n = record[21];
4423 pll_lim->vco2.min_m = record[22];
4424 pll_lim->vco2.max_m = record[23];
4425 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4426 pll_lim->log2p_bias = record[27];
4427 pll_lim->refclk = ROM32(record[28]);
4428 } else if (pll_lim_ver) { /* ver 0x40 */
4429 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4430 uint8_t *record = NULL;
4431 int i;
4432
4433 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4434 limit_match);
4435
4436 for (i = 0; i < entries; i++, entry += recordlen) {
4437 if (ROM32(entry[3]) == limit_match) {
4438 record = &bios->data[ROM16(entry[1])];
4439 break;
4440 }
4441 }
4442
4443 if (!record) {
4444 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4445 "limits table", limit_match);
4446 return -ENOENT;
4447 }
4448
4449 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4450 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4451 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4452 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4453 pll_lim->vco1.min_m = record[8];
4454 pll_lim->vco1.max_m = record[9];
4455 pll_lim->vco1.min_n = record[10];
4456 pll_lim->vco1.max_n = record[11];
4457 pll_lim->min_p = record[12];
4458 pll_lim->max_p = record[13];
4459 /* where did this go to?? */
4460 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4461 pll_lim->refclk = 27000;
4462 else
4463 pll_lim->refclk = 100000;
4464 }
4465
4466 /*
4467 * By now any valid limit table ought to have set a max frequency for
4468 * vco1, so if it's zero it's either a pre limit table bios, or one
4469 * with an empty limit table (seen on nv18)
4470 */
4471 if (!pll_lim->vco1.maxfreq) {
4472 pll_lim->vco1.minfreq = bios->fminvco;
4473 pll_lim->vco1.maxfreq = bios->fmaxvco;
4474 pll_lim->vco1.min_inputfreq = 0;
4475 pll_lim->vco1.max_inputfreq = INT_MAX;
4476 pll_lim->vco1.min_n = 0x1;
4477 pll_lim->vco1.max_n = 0xff;
4478 pll_lim->vco1.min_m = 0x1;
4479 if (crystal_straps == 0) {
4480 /* nv05 does this, nv11 doesn't, nv10 unknown */
4481 if (cv < 0x11)
4482 pll_lim->vco1.min_m = 0x7;
4483 pll_lim->vco1.max_m = 0xd;
4484 } else {
4485 if (cv < 0x11)
4486 pll_lim->vco1.min_m = 0x8;
4487 pll_lim->vco1.max_m = 0xe;
4488 }
4489 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4490 pll_lim->max_log2p = 4;
4491 else
4492 pll_lim->max_log2p = 5;
4493 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4494 }
4495
4496 if (!pll_lim->refclk)
4497 switch (crystal_straps) {
4498 case 0:
4499 pll_lim->refclk = 13500;
4500 break;
4501 case (1 << 6):
4502 pll_lim->refclk = 14318;
4503 break;
4504 case (1 << 22):
4505 pll_lim->refclk = 27000;
4506 break;
4507 case (1 << 22 | 1 << 6):
4508 pll_lim->refclk = 25000;
4509 break;
4510 }
4511
4c389f00
BS		 4512 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4513 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4514 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4515 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4516 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4517 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4518 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4519 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4520 if (pll_lim->vco2.maxfreq) {
4521 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4522 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4523 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4524 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4525 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4526 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4527 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4528 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4529 }
4530 if (!pll_lim->max_p) {
4531 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4532 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4533 } else {
4534 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4535 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4536 }
4537 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 4538
4539 return 0;
4540}
4541
4542static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4543{
4544 /*
4545 * offset + 0 (8 bits): Micro version
4546 * offset + 1 (8 bits): Minor version
4547 * offset + 2 (8 bits): Chip version
4548 * offset + 3 (8 bits): Major version
4549 */
4550
4551 bios->major_version = bios->data[offset + 3];
04a39c57 4552 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4553 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4554 bios->data[offset + 3], bios->data[offset + 2],
4555 bios->data[offset + 1], bios->data[offset]);
4556}
4557
4558static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4559{
4560 /*
4561 * Parses the init table segment for pointers used in script execution.
4562 *
4563 * offset + 0 (16 bits): init script tables pointer
4564 * offset + 2 (16 bits): macro index table pointer
4565 * offset + 4 (16 bits): macro table pointer
4566 * offset + 6 (16 bits): condition table pointer
4567 * offset + 8 (16 bits): io condition table pointer
4568 * offset + 10 (16 bits): io flag condition table pointer
4569 * offset + 12 (16 bits): init function table pointer
4570 */
4571
4572 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4573 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4574 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4575 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4576 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4577 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4578 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4579}
4580
4581static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4582{
4583 /*
4584 * Parses the load detect values for g80 cards.
4585 *
4586 * offset + 0 (16 bits): loadval table pointer
4587 */
4588
4589 uint16_t load_table_ptr;
4590 uint8_t version, headerlen, entrylen, num_entries;
4591
4592 if (bitentry->length != 3) {
4593 NV_ERROR(dev, "Do not understand BIT A table\n");
4594 return -EINVAL;
4595 }
4596
4597 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4598
4599 if (load_table_ptr == 0x0) {
4600 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4601 return -EINVAL;
4602 }
4603
4604 version = bios->data[load_table_ptr];
4605
4606 if (version != 0x10) {
4607 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4608 version >> 4, version & 0xF);
4609 return -ENOSYS;
4610 }
4611
4612 headerlen = bios->data[load_table_ptr + 1];
4613 entrylen = bios->data[load_table_ptr + 2];
4614 num_entries = bios->data[load_table_ptr + 3];
4615
4616 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4617 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4618 return -EINVAL;
4619 }
4620
4621 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 4622 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 4623
4624 return 0;
4625}
4626
4627static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4628{
4629 /*
4630 * offset + 8 (16 bits): PLL limits table pointer
4631 *
4632 * There's more in here, but that's unknown.
4633 */
4634
4635 if (bitentry->length < 10) {
4636 NV_ERROR(dev, "Do not understand BIT C table\n");
4637 return -EINVAL;
4638 }
4639
4640 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4641
4642 return 0;
4643}
4644
4645static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4646{
4647 /*
4648 * Parses the flat panel table segment that the bit entry points to.
4649 * Starting at bitentry->offset:
4650 *
4651 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4652 * records beginning with a freq.
4653 * offset + 2 (16 bits): mode table pointer
4654 */
4655
4656 if (bitentry->length != 4) {
4657 NV_ERROR(dev, "Do not understand BIT display table\n");
4658 return -EINVAL;
4659 }
4660
4661 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4662
4663 return 0;
4664}
4665
4666static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4667{
4668 /*
4669 * Parses the init table segment that the bit entry points to.
4670 *
4671 * See parse_script_table_pointers for layout
4672 */
4673
4674 if (bitentry->length < 14) {
4675 NV_ERROR(dev, "Do not understand init table\n");
4676 return -EINVAL;
4677 }
4678
4679 parse_script_table_pointers(bios, bitentry->offset);
4680
4681 if (bitentry->length >= 16)
4682 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4683 if (bitentry->length >= 18)
4684 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4685
4686 return 0;
4687}
4688
4689static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4690{
4691 /*
4692 * BIT 'i' (info?) table
4693 *
4694 * offset + 0 (32 bits): BIOS version dword (as in B table)
4695 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4696 * offset + 13 (16 bits): pointer to table containing DAC load
4697 * detection comparison values
4698 *
4699 * There's other things in the table, purpose unknown
4700 */
4701
4702 uint16_t daccmpoffset;
4703 uint8_t dacver, dacheaderlen;
4704
4705 if (bitentry->length < 6) {
4706 NV_ERROR(dev, "BIT i table too short for needed information\n");
4707 return -EINVAL;
4708 }
4709
4710 parse_bios_version(dev, bios, bitentry->offset);
4711
4712 /*
4713 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4714 * Quadro identity crisis), other bits possibly as for BMP feature byte
4715 */
4716 bios->feature_byte = bios->data[bitentry->offset + 5];
4717 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4718
4719 if (bitentry->length < 15) {
4720 NV_WARN(dev, "BIT i table not long enough for DAC load "
4721 "detection comparison table\n");
4722 return -EINVAL;
4723 }
4724
4725 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4726
4727 /* doesn't exist on g80 */
4728 if (!daccmpoffset)
4729 return 0;
4730
4731 /*
4732 * The first value in the table, following the header, is the
4733 * comparison value, the second entry is a comparison value for
4734 * TV load detection.
4735 */
4736
4737 dacver = bios->data[daccmpoffset];
4738 dacheaderlen = bios->data[daccmpoffset + 1];
4739
4740 if (dacver != 0x00 && dacver != 0x10) {
4741 NV_WARN(dev, "DAC load detection comparison table version "
4742 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4743 return -ENOSYS;
4744 }
4745
04a39c57
BS		 4746 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4747 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 4748
4749 return 0;
4750}
4751
4752static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4753{
4754 /*
4755 * Parses the LVDS table segment that the bit entry points to.
4756 * Starting at bitentry->offset:
4757 *
4758 * offset + 0 (16 bits): LVDS strap xlate table pointer
4759 */
4760
4761 if (bitentry->length != 2) {
4762 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4763 return -EINVAL;
4764 }
4765
4766 /*
4767 * No idea if it's still called the LVDS manufacturer table, but
4768 * the concept's close enough.
4769 */
4770 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4771
4772 return 0;
4773}
4774
4775static int
4776parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4777 struct bit_entry *bitentry)
4778{
4779 /*
4780 * offset + 2 (8 bits): number of options in an
4781 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4782 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4783 * restrict option selection
4784 *
4785 * There's a bunch of bits in this table other than the RAM restrict
4786 * stuff that we don't use - their use currently unknown
4787 */
4788
6ee73861
BS		 4789 /*
4790 * Older bios versions don't have a sufficiently long table for
4791 * what we want
4792 */
4793 if (bitentry->length < 0x5)
4794 return 0;
4795
4796 if (bitentry->id[1] < 2) {
37383650
MK		 4797 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4798 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 4799 } else {
37383650
MK		 4800 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4801 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 4802 }
4803
6ee73861
BS		 4804 return 0;
4805}
4806
4807static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4808{
4809 /*
4810 * Parses the pointer to the TMDS table
4811 *
4812 * Starting at bitentry->offset:
4813 *
4814 * offset + 0 (16 bits): TMDS table pointer
4815 *
4816 * The TMDS table is typically found just before the DCB table, with a
4817 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4818 * length?)
4819 *
4820 * At offset +7 is a pointer to a script, which I don't know how to
4821 * run yet.
4822 * At offset +9 is a pointer to another script, likewise
4823 * Offset +11 has a pointer to a table where the first word is a pxclk
4824 * frequency and the second word a pointer to a script, which should be
4825 * run if the comparison pxclk frequency is less than the pxclk desired.
4826 * This repeats for decreasing comparison frequencies
4827 * Offset +13 has a pointer to a similar table
4828 * The selection of table (and possibly +7/+9 script) is dictated by
4829 * "or" from the DCB.
4830 */
4831
4832 uint16_t tmdstableptr, script1, script2;
4833
4834 if (bitentry->length != 2) {
4835 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4836 return -EINVAL;
4837 }
4838
4839 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4840
4841 if (tmdstableptr == 0x0) {
4842 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4843 return -EINVAL;
4844 }
4845
4846 /* nv50+ has v2.0, but we don't parse it atm */
4847 if (bios->data[tmdstableptr] != 0x11) {
4848 NV_WARN(dev,
4849 "TMDS table revision %d.%d not currently supported\n",
4850 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4851 return -ENOSYS;
4852 }
4853
4854 /*
4855 * These two scripts are odd: they don't seem to get run even when
4856 * they are not stubbed.
4857 */
4858 script1 = ROM16(bios->data[tmdstableptr + 7]);
4859 script2 = ROM16(bios->data[tmdstableptr + 9]);
4860 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4861 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4862
4863 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4864 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4865
4866 return 0;
4867}
4868
4869static int
4870parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4871 struct bit_entry *bitentry)
4872{
4873 /*
4874 * Parses the pointer to the G80 output script tables
4875 *
4876 * Starting at bitentry->offset:
4877 *
4878 * offset + 0 (16 bits): output script table pointer
4879 */
4880
4881 uint16_t outputscripttableptr;
4882
4883 if (bitentry->length != 3) {
4884 NV_ERROR(dev, "Do not understand BIT U table\n");
4885 return -EINVAL;
4886 }
4887
4888 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4889 bios->display.script_table_ptr = outputscripttableptr;
4890 return 0;
4891}
4892
4893static int
4894parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4895 struct bit_entry *bitentry)
4896{
4897 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4898 return 0;
4899}
4900
4901struct bit_table {
4902 const char id;
4903 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4904};
4905
4906#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4907
4908static int
4909parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4910 struct bit_table *table)
4911{
4912 struct drm_device *dev = bios->dev;
4913 uint8_t maxentries = bios->data[bitoffset + 4];
4914 int i, offset;
4915 struct bit_entry bitentry;
4916
4917 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4918 bitentry.id[0] = bios->data[offset];
4919
4920 if (bitentry.id[0] != table->id)
4921 continue;
4922
4923 bitentry.id[1] = bios->data[offset + 1];
4924 bitentry.length = ROM16(bios->data[offset + 2]);
4925 bitentry.offset = ROM16(bios->data[offset + 4]);
4926
4927 return table->parse_fn(dev, bios, &bitentry);
4928 }
4929
4930 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4931 return -ENOSYS;
4932}
4933
4934static int
4935parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4936{
4937 int ret;
4938
4939 /*
4940 * The only restriction on parsing order currently is having 'i' first
4941 * for use of bios->*_version or bios->feature_byte while parsing;
4942 * functions shouldn't be actually *doing* anything apart from pulling
4943 * data from the image into the bios struct, thus no interdependencies
4944 */
4945 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4946 if (ret) /* info? */
4947 return ret;
4948 if (bios->major_version >= 0x60) /* g80+ */
4949 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4950 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4951 if (ret)
4952 return ret;
4953 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4954 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4955 if (ret)
4956 return ret;
4957 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4958 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4959 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4960 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4961 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4962
4963 return 0;
4964}
4965
4966static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4967{
4968 /*
4969 * Parses the BMP structure for useful things, but does not act on them
4970 *
4971 * offset + 5: BMP major version
4972 * offset + 6: BMP minor version
4973 * offset + 9: BMP feature byte
4974 * offset + 10: BCD encoded BIOS version
4975 *
4976 * offset + 18: init script table pointer (for bios versions < 5.10h)
4977 * offset + 20: extra init script table pointer (for bios
4978 * versions < 5.10h)
4979 *
4980 * offset + 24: memory init table pointer (used on early bios versions)
4981 * offset + 26: SDR memory sequencing setup data table
4982 * offset + 28: DDR memory sequencing setup data table
4983 *
4984 * offset + 54: index of I2C CRTC pair to use for CRT output
4985 * offset + 55: index of I2C CRTC pair to use for TV output
4986 * offset + 56: index of I2C CRTC pair to use for flat panel output
4987 * offset + 58: write CRTC index for I2C pair 0
4988 * offset + 59: read CRTC index for I2C pair 0
4989 * offset + 60: write CRTC index for I2C pair 1
4990 * offset + 61: read CRTC index for I2C pair 1
4991 *
4992 * offset + 67: maximum internal PLL frequency (single stage PLL)
4993 * offset + 71: minimum internal PLL frequency (single stage PLL)
4994 *
4995 * offset + 75: script table pointers, as described in
4996 * parse_script_table_pointers
4997 *
4998 * offset + 89: TMDS single link output A table pointer
4999 * offset + 91: TMDS single link output B table pointer
5000 * offset + 95: LVDS single link output A table pointer
5001 * offset + 105: flat panel timings table pointer
5002 * offset + 107: flat panel strapping translation table pointer
5003 * offset + 117: LVDS manufacturer panel config table pointer
5004 * offset + 119: LVDS manufacturer strapping translation table pointer
5005 *
5006 * offset + 142: PLL limits table pointer
5007 *
5008 * offset + 156: minimum pixel clock for LVDS dual link
5009 */
5010
5011 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5012 uint16_t bmplength;
5013 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5014
5015 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 5016 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5017 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5018 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5019 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 5020 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5021 bios->fmaxvco = 256000;
5022 bios->fminvco = 128000;
5023 bios->fp.duallink_transition_clk = 90000;
5024
5025 bmp_version_major = bmp[5];
5026 bmp_version_minor = bmp[6];
5027
5028 NV_TRACE(dev, "BMP version %d.%d\n",
5029 bmp_version_major, bmp_version_minor);
5030
5031 /*
5032 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5033 * pointer on early versions
5034 */
5035 if (bmp_version_major < 5)
5036 *(uint16_t *)&bios->data[0x36] = 0;
5037
5038 /*
5039 * Seems that the minor version was 1 for all major versions prior
5040 * to 5. Version 6 could theoretically exist, but I suspect BIT
5041 * happened instead.
5042 */
5043 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5044 NV_ERROR(dev, "You have an unsupported BMP version. "
5045 "Please send in your bios\n");
5046 return -ENOSYS;
5047 }
5048
5049 if (bmp_version_major == 0)
5050 /* nothing that's currently useful in this version */
5051 return 0;
5052 else if (bmp_version_major == 1)
5053 bmplength = 44; /* exact for 1.01 */
5054 else if (bmp_version_major == 2)
5055 bmplength = 48; /* exact for 2.01 */
5056 else if (bmp_version_major == 3)
5057 bmplength = 54;
5058 /* guessed - mem init tables added in this version */
5059 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5060 /* don't know if 5.0 exists... */
5061 bmplength = 62;
5062 /* guessed - BMP I2C indices added in version 4*/
5063 else if (bmp_version_minor < 0x6)
5064 bmplength = 67; /* exact for 5.01 */
5065 else if (bmp_version_minor < 0x10)
5066 bmplength = 75; /* exact for 5.06 */
5067 else if (bmp_version_minor == 0x10)
5068 bmplength = 89; /* exact for 5.10h */
5069 else if (bmp_version_minor < 0x14)
5070 bmplength = 118; /* exact for 5.11h */
5071 else if (bmp_version_minor < 0x24)
5072 /*
5073 * Not sure of version where pll limits came in;
5074 * certainly exist by 0x24 though.
5075 */
5076 /* length not exact: this is long enough to get lvds members */
5077 bmplength = 123;
5078 else if (bmp_version_minor < 0x27)
5079 /*
5080 * Length not exact: this is long enough to get pll limit
5081 * member
5082 */
5083 bmplength = 144;
5084 else
5085 /*
5086 * Length not exact: this is long enough to get dual link
5087 * transition clock.
5088 */
5089 bmplength = 158;
5090
5091 /* checksum */
5092 if (nv_cksum(bmp, 8)) {
5093 NV_ERROR(dev, "Bad BMP checksum\n");
5094 return -EINVAL;
5095 }
5096
5097 /*
5098 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5099 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5100 * (not nv10gl), bit 5 that the flat panel tables are present, and
5101 * bit 6 a tv bios.
5102 */
5103 bios->feature_byte = bmp[9];
5104
5105 parse_bios_version(dev, bios, offset + 10);
5106
5107 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5108 bios->old_style_init = true;
5109 legacy_scripts_offset = 18;
5110 if (bmp_version_major < 2)
5111 legacy_scripts_offset -= 4;
5112 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5113 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5114
5115 if (bmp_version_major > 2) { /* appears in BMP 3 */
5116 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5117 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5118 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5119 }
5120
5121 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5122 if (bmplength > 61)
5123 legacy_i2c_offset = offset + 54;
5124 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5125 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5126 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
7f245b20
BS		 5127 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5128 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5129 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5130 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5131
5132 if (bmplength > 74) {
5133 bios->fmaxvco = ROM32(bmp[67]);
5134 bios->fminvco = ROM32(bmp[71]);
5135 }
5136 if (bmplength > 88)
5137 parse_script_table_pointers(bios, offset + 75);
5138 if (bmplength > 94) {
5139 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5140 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5141 /*
5142 * Never observed in use with lvds scripts, but is reused for
5143 * 18/24 bit panel interface default for EDID equipped panels
5144 * (if_is_24bit not set directly to avoid any oscillation).
5145 */
5146 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5147 }
5148 if (bmplength > 108) {
5149 bios->fp.fptablepointer = ROM16(bmp[105]);
5150 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5151 bios->fp.xlatwidth = 1;
5152 }
5153 if (bmplength > 120) {
5154 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5155 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5156 }
5157 if (bmplength > 143)
5158 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5159
5160 if (bmplength > 157)
5161 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5162
5163 return 0;
5164}
5165
5166static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5167{
5168 int i, j;
5169
5170 for (i = 0; i <= (n - len); i++) {
5171 for (j = 0; j < len; j++)
5172 if (data[i + j] != str[j])
5173 break;
5174 if (j == len)
5175 return i;
5176 }
5177
5178 return 0;
5179}
5180
6ee73861
BS		 5181static struct dcb_gpio_entry *
5182new_gpio_entry(struct nvbios *bios)
5183{
7f245b20 5184 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861
BS		 5185
5186 return &gpio->entry[gpio->entries++];
5187}
5188
5189struct dcb_gpio_entry *
5190nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5191{
5192 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5193 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5194 int i;
5195
7f245b20
BS		 5196 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5197 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5198 continue;
5199
7f245b20 5200 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5201 }
5202
5203 return NULL;
5204}
5205
5206static void
5207parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5208{
5209 struct dcb_gpio_entry *gpio;
5210 uint16_t ent = ROM16(bios->data[offset]);
5211 uint8_t line = ent & 0x1f,
5212 tag = ent >> 5 & 0x3f,
5213 flags = ent >> 11 & 0x1f;
5214
5215 if (tag == 0x3f)
5216 return;
5217
5218 gpio = new_gpio_entry(bios);
5219
5220 gpio->tag = tag;
5221 gpio->line = line;
5222 gpio->invert = flags != 4;
2535d71c 5223 gpio->entry = ent;
6ee73861
BS		 5224}
5225
5226static void
5227parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5228{
02faec09 5229 uint32_t entry = ROM32(bios->data[offset]);
6ee73861 5230 struct dcb_gpio_entry *gpio;
6ee73861 5231
02faec09 5232 if ((entry & 0x0000ff00) == 0x0000ff00)
6ee73861
BS		 5233 return;
5234
5235 gpio = new_gpio_entry(bios);
02faec09
BS		 5236 gpio->tag = (entry & 0x0000ff00) >> 8;
5237 gpio->line = (entry & 0x0000001f) >> 0;
5238 gpio->state_default = (entry & 0x01000000) >> 24;
5239 gpio->state[0] = (entry & 0x18000000) >> 27;
5240 gpio->state[1] = (entry & 0x60000000) >> 29;
5241 gpio->entry = entry;
6ee73861
BS		 5242}
5243
5244static void
5245parse_dcb_gpio_table(struct nvbios *bios)
5246{
5247 struct drm_device *dev = bios->dev;
7f245b20 5248 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr;
6ee73861
BS		 5249 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5250 int header_len = gpio_table[1],
5251 entries = gpio_table[2],
5252 entry_len = gpio_table[3];
5253 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5254 int i;
5255
7f245b20 5256 if (bios->dcb.version >= 0x40) {
6ee73861
BS		 5257 if (gpio_table_ptr && entry_len != 4) {
5258 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5259 return;
5260 }
5261
5262 parse_entry = parse_dcb40_gpio_entry;
5263
7f245b20 5264 } else if (bios->dcb.version >= 0x30) {
6ee73861
BS		 5265 if (gpio_table_ptr && entry_len != 2) {
5266 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5267 return;
5268 }
5269
5270 parse_entry = parse_dcb30_gpio_entry;
5271
7f245b20 5272 } else if (bios->dcb.version >= 0x22) {
6ee73861
BS		 5273 /*
5274 * DCBs older than v3.0 don't really have a GPIO
5275 * table, instead they keep some GPIO info at fixed
5276 * locations.
5277 */
5278 uint16_t dcbptr = ROM16(bios->data[0x36]);
5279 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5280
5281 if (tvdac_gpio[0] & 1) {
5282 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5283
5284 gpio->tag = DCB_GPIO_TVDAC0;
5285 gpio->line = tvdac_gpio[1] >> 4;
5286 gpio->invert = tvdac_gpio[0] & 2;
5287 }
5288 }
5289
5290 if (!gpio_table_ptr)
5291 return;
5292
5293 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5294 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5295 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5296 }
5297
5298 for (i = 0; i < entries; i++)
5299 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5300}
5301
5302struct dcb_connector_table_entry *
5303nouveau_bios_connector_entry(struct drm_device *dev, int index)
5304{
5305 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5306 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5307 struct dcb_connector_table_entry *cte;
5308
7f245b20 5309 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5310 return NULL;
5311
7f245b20 5312 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5313 if (cte->type == 0xff)
5314 return NULL;
5315
5316 return cte;
5317}
5318
f66fa771
BS		 5319static enum dcb_connector_type
5320divine_connector_type(struct nvbios *bios, int index)
5321{
5322 struct dcb_table *dcb = &bios->dcb;
5323 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5324 int i;
5325
5326 for (i = 0; i < dcb->entries; i++) {
5327 if (dcb->entry[i].connector == index)
5328 encoders |= (1 << dcb->entry[i].type);
5329 }
5330
5331 if (encoders & (1 << OUTPUT_DP)) {
5332 if (encoders & (1 << OUTPUT_TMDS))
5333 type = DCB_CONNECTOR_DP;
5334 else
5335 type = DCB_CONNECTOR_eDP;
5336 } else
5337 if (encoders & (1 << OUTPUT_TMDS)) {
5338 if (encoders & (1 << OUTPUT_ANALOG))
5339 type = DCB_CONNECTOR_DVI_I;
5340 else
5341 type = DCB_CONNECTOR_DVI_D;
5342 } else
5343 if (encoders & (1 << OUTPUT_ANALOG)) {
5344 type = DCB_CONNECTOR_VGA;
5345 } else
5346 if (encoders & (1 << OUTPUT_LVDS)) {
5347 type = DCB_CONNECTOR_LVDS;
5348 } else
5349 if (encoders & (1 << OUTPUT_TV)) {
5350 type = DCB_CONNECTOR_TV_0;
5351 }
5352
5353 return type;
5354}
5355
53c44c3a
BS		 5356static void
5357apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5358{
5359 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5360 struct drm_device *dev = bios->dev;
5361
5362 /* Gigabyte NX85T */
5363 if ((dev->pdev->device == 0x0421) &&
5364 (dev->pdev->subsystem_vendor == 0x1458) &&
5365 (dev->pdev->subsystem_device == 0x344c)) {
5366 if (cte->type == DCB_CONNECTOR_HDMI_1)
5367 cte->type = DCB_CONNECTOR_DVI_I;
5368 }
5369}
5370
6ee73861
BS		 5371static void
5372parse_dcb_connector_table(struct nvbios *bios)
5373{
5374 struct drm_device *dev = bios->dev;
7f245b20 5375 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5376 struct dcb_connector_table_entry *cte;
7f245b20 5377 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5378 uint8_t *entry;
5379 int i;
5380
7f245b20 5381 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5382 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5383 return;
5384 }
5385
5386 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5387 conntab[0], conntab[1], conntab[2], conntab[3]);
5388 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5389 (conntab[3] != 2 && conntab[3] != 4)) {
5390 NV_ERROR(dev, " Unknown! Please report.\n");
5391 return;
5392 }
5393
5394 ct->entries = conntab[2];
5395
5396 entry = conntab + conntab[1];
5397 cte = &ct->entry[0];
5398 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5399 cte->index = i;
6ee73861
BS		 5400 if (conntab[3] == 2)
5401 cte->entry = ROM16(entry[0]);
5402 else
5403 cte->entry = ROM32(entry[0]);
f66fa771 5404
6ee73861 5405 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 5406 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6ee73861
BS		 5407 switch (cte->entry & 0x00033000) {
5408 case 0x00001000:
5409 cte->gpio_tag = 0x07;
5410 break;
5411 case 0x00002000:
5412 cte->gpio_tag = 0x08;
5413 break;
5414 case 0x00010000:
5415 cte->gpio_tag = 0x51;
5416 break;
5417 case 0x00020000:
5418 cte->gpio_tag = 0x52;
5419 break;
5420 default:
5421 cte->gpio_tag = 0xff;
5422 break;
5423 }
5424
5425 if (cte->type == 0xff)
5426 continue;
5427
53c44c3a
BS		 5428 apply_dcb_connector_quirks(bios, i);
5429
6ee73861
BS		 5430 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5431 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5432
5433 /* check for known types, fallback to guessing the type
5434 * from attached encoders if we hit an unknown.
5435 */
5436 switch (cte->type) {
5437 case DCB_CONNECTOR_VGA:
5438 case DCB_CONNECTOR_TV_0:
5439 case DCB_CONNECTOR_TV_1:
5440 case DCB_CONNECTOR_TV_3:
5441 case DCB_CONNECTOR_DVI_I:
5442 case DCB_CONNECTOR_DVI_D:
5443 case DCB_CONNECTOR_LVDS:
5444 case DCB_CONNECTOR_DP:
5445 case DCB_CONNECTOR_eDP:
5446 case DCB_CONNECTOR_HDMI_0:
5447 case DCB_CONNECTOR_HDMI_1:
5448 break;
5449 default:
5450 cte->type = divine_connector_type(bios, cte->index);
da647d5b 5451 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 5452 break;
5453 }
5454
da647d5b
BS		 5455 if (nouveau_override_conntype) {
5456 int type = divine_connector_type(bios, cte->index);
5457 if (type != cte->type)
5458 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5459 }
5460
6ee73861
BS		 5461 }
5462}
5463
7f245b20 5464static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5465{
5466 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5467
5468 memset(entry, 0, sizeof(struct dcb_entry));
5469 entry->index = dcb->entries++;
5470
5471 return entry;
5472}
5473
7f245b20 5474static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
6ee73861
BS		 5475{
5476 struct dcb_entry *entry = new_dcb_entry(dcb);
5477
5478 entry->type = 0;
5479 entry->i2c_index = i2c;
5480 entry->heads = heads;
5481 entry->location = DCB_LOC_ON_CHIP;
5482 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5483}
5484
7f245b20 5485static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5486{
5487 struct dcb_entry *entry = new_dcb_entry(dcb);
5488
5489 entry->type = 2;
5490 entry->i2c_index = LEGACY_I2C_PANEL;
5491 entry->heads = twoHeads ? 3 : 1;
5492 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5493 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5494 entry->duallink_possible = false; /* SiI164 and co. are single link */
5495
5496#if 0
5497 /*
5498 * For dvi-a either crtc probably works, but my card appears to only
5499 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5500 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5501 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5502 * the monitor picks up the mode res ok and lights up, but no pixel
5503 * data appears, so the board manufacturer probably connected up the
5504 * sync lines, but missed the video traces / components
5505 *
5506 * with this introduction, dvi-a left as an exercise for the reader.
5507 */
5508 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5509#endif
5510}
5511
7f245b20 5512static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5513{
5514 struct dcb_entry *entry = new_dcb_entry(dcb);
5515
5516 entry->type = 1;
5517 entry->i2c_index = LEGACY_I2C_TV;
5518 entry->heads = twoHeads ? 3 : 1;
5519 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5520}
5521
5522static bool
7f245b20 5523parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5524 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5525{
5526 entry->type = conn & 0xf;
5527 entry->i2c_index = (conn >> 4) & 0xf;
5528 entry->heads = (conn >> 8) & 0xf;
7f245b20 5529 if (dcb->version >= 0x40)
6ee73861
BS		 5530 entry->connector = (conn >> 12) & 0xf;
5531 entry->bus = (conn >> 16) & 0xf;
5532 entry->location = (conn >> 20) & 0x3;
5533 entry->or = (conn >> 24) & 0xf;
5534 /*
5535 * Normal entries consist of a single bit, but dual link has the
5536 * next most significant bit set too
5537 */
5538 entry->duallink_possible =
5539 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5540
5541 switch (entry->type) {
5542 case OUTPUT_ANALOG:
5543 /*
5544 * Although the rest of a CRT conf dword is usually
5545 * zeros, mac biosen have stuff there so we must mask
5546 */
7f245b20 5547 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5548 (conf & 0xffff) * 10 :
5549 (conf & 0xff) * 10000;
5550 break;
5551 case OUTPUT_LVDS:
5552 {
5553 uint32_t mask;
5554 if (conf & 0x1)
5555 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5556 if (dcb->version < 0x22) {
6ee73861
BS		 5557 mask = ~0xd;
5558 /*
5559 * The laptop in bug 14567 lies and claims to not use
5560 * straps when it does, so assume all DCB 2.0 laptops
5561 * use straps, until a broken EDID using one is produced
5562 */
5563 entry->lvdsconf.use_straps_for_mode = true;
5564 /*
5565 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5566 * mean the same thing (probably wrong, but might work)
5567 */
5568 if (conf & 0x4 || conf & 0x8)
5569 entry->lvdsconf.use_power_scripts = true;
5570 } else {
5571 mask = ~0x5;
5572 if (conf & 0x4)
5573 entry->lvdsconf.use_power_scripts = true;
5574 }
5575 if (conf & mask) {
5576 /*
5577 * Until we even try to use these on G8x, it's
5578 * useless reporting unknown bits. They all are.
5579 */
7f245b20 5580 if (dcb->version >= 0x40)
6ee73861
BS		 5581 break;
5582
5583 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5584 "please report\n");
5585 }
5586 break;
5587 }
5588 case OUTPUT_TV:
5589 {
7f245b20 5590 if (dcb->version >= 0x30)
6ee73861
BS		 5591 entry->tvconf.has_component_output = conf & (0x8 << 4);
5592 else
5593 entry->tvconf.has_component_output = false;
5594
5595 break;
5596 }
5597 case OUTPUT_DP:
5598 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5599 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5600 switch ((conf & 0x0f000000) >> 24) {
5601 case 0xf:
5602 entry->dpconf.link_nr = 4;
5603 break;
5604 case 0x3:
5605 entry->dpconf.link_nr = 2;
5606 break;
5607 default:
5608 entry->dpconf.link_nr = 1;
5609 break;
5610 }
5611 break;
5612 case OUTPUT_TMDS:
5613 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5614 break;
5615 case 0xe:
5616 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 5617 dcb->entries--;
6ee73861 5618 return false;
e7cc51c5
BS		 5619 default:
5620 break;
6ee73861
BS		 5621 }
5622
5623 /* unsure what DCB version introduces this, 3.0? */
5624 if (conf & 0x100000)
5625 entry->i2c_upper_default = true;
5626
5627 return true;
5628}
5629
5630static bool
7f245b20 5631parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5632 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5633{
b0d2de86
BS		 5634 switch (conn & 0x0000000f) {
5635 case 0:
5636 entry->type = OUTPUT_ANALOG;
5637 break;
5638 case 1:
5639 entry->type = OUTPUT_TV;
5640 break;
5641 case 2:
5642 case 3:
6ee73861 5643 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 5644 break;
5645 case 4:
5646 switch ((conn & 0x000000f0) >> 4) {
5647 case 0:
6ee73861 5648 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 5649 break;
5650 case 1:
5651 entry->type = OUTPUT_LVDS;
5652 break;
5653 default:
5654 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5655 (conn & 0x000000f0) >> 4);
5656 return false;
5657 }
5658 break;
5659 default:
5660 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5661 return false;
6ee73861 5662 }
b0d2de86
BS		 5663
5664 entry->i2c_index = (conn & 0x0003c000) >> 14;
5665 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5666 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5667 entry->location = (conn & 0x01e00000) >> 21;
5668 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 5669 entry->duallink_possible = false;
5670
5671 switch (entry->type) {
5672 case OUTPUT_ANALOG:
5673 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5674 break;
b0d2de86
BS		 5675 case OUTPUT_TV:
5676 entry->tvconf.has_component_output = false;
6ee73861
BS		 5677 break;
5678 case OUTPUT_TMDS:
5679 /*
5680 * Invent a DVI-A output, by copying the fields of the DVI-D
5681 * output; reported to work by math_b on an NV20(!).
5682 */
5683 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5684 break;
b0d2de86
BS		 5685 case OUTPUT_LVDS:
5686 if ((conn & 0x00003f00) != 0x10)
5687 entry->lvdsconf.use_straps_for_mode = true;
5688 entry->lvdsconf.use_power_scripts = true;
5689 break;
5690 default:
6ee73861
BS		 5691 break;
5692 }
5693
5694 return true;
5695}
5696
7f245b20 5697static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5698 uint32_t conn, uint32_t conf)
5699{
7f245b20 5700 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 5701 bool ret;
5702
7f245b20
BS		 5703 if (dcb->version >= 0x20)
5704 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 5705 else
7f245b20 5706 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 5707 if (!ret)
5708 return ret;
5709
7f245b20
BS		 5710 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
5711 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 5712
5713 return true;
5714}
5715
5716static
7f245b20 5717void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 5718{
5719 /*
5720 * DCB v2.0 lists each output combination separately.
5721 * Here we merge compatible entries to have fewer outputs, with
5722 * more options
5723 */
5724
5725 int i, newentries = 0;
5726
5727 for (i = 0; i < dcb->entries; i++) {
5728 struct dcb_entry *ient = &dcb->entry[i];
5729 int j;
5730
5731 for (j = i + 1; j < dcb->entries; j++) {
5732 struct dcb_entry *jent = &dcb->entry[j];
5733
5734 if (jent->type == 100) /* already merged entry */
5735 continue;
5736
5737 /* merge heads field when all other fields the same */
5738 if (jent->i2c_index == ient->i2c_index &&
5739 jent->type == ient->type &&
5740 jent->location == ient->location &&
5741 jent->or == ient->or) {
5742 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5743 i, j);
5744 ient->heads |= jent->heads;
5745 jent->type = 100; /* dummy value */
5746 }
5747 }
5748 }
5749
5750 /* Compact entries merged into others out of dcb */
5751 for (i = 0; i < dcb->entries; i++) {
5752 if (dcb->entry[i].type == 100)
5753 continue;
5754
5755 if (newentries != i) {
5756 dcb->entry[newentries] = dcb->entry[i];
5757 dcb->entry[newentries].index = newentries;
5758 }
5759 newentries++;
5760 }
5761
5762 dcb->entries = newentries;
5763}
5764
ed42f824
BS		 5765static int
5766parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 5767{
ed42f824 5768 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 5769 struct dcb_table *dcb = &bios->dcb;
ed42f824 5770 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 5771 uint8_t *dcbtable;
5772 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5773 bool configblock = true;
5774 int recordlength = 8, confofs = 4;
5775 int i;
5776
6ee73861 5777 /* get the offset from 0x36 */
ed42f824
BS		 5778 if (dev_priv->card_type > NV_04) {
5779 dcbptr = ROM16(bios->data[0x36]);
5780 if (dcbptr == 0x0000)
5781 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5782 }
6ee73861 5783
ed42f824 5784 /* this situation likely means a really old card, pre DCB */
6ee73861 5785 if (dcbptr == 0x0) {
ed42f824 5786 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 5787 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5788
ed42f824 5789 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 5790 fabricate_tv_output(dcb, twoHeads);
5791
5792 return 0;
5793 }
5794
5795 dcbtable = &bios->data[dcbptr];
5796
5797 /* get DCB version */
7f245b20 5798 dcb->version = dcbtable[0];
6ee73861 5799 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 5800 dcb->version >> 4, dcb->version & 0xf);
6ee73861 5801
7f245b20 5802 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 5803 uint32_t sig;
5804
7f245b20 5805 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 5806 headerlen = dcbtable[1];
5807 entries = dcbtable[2];
5808 recordlength = dcbtable[3];
5809 i2ctabptr = ROM16(dcbtable[4]);
5810 sig = ROM32(dcbtable[6]);
7f245b20
BS		 5811 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
5812 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 5813 } else {
5814 i2ctabptr = ROM16(dcbtable[2]);
5815 sig = ROM32(dcbtable[4]);
5816 headerlen = 8;
5817 }
5818
5819 if (sig != 0x4edcbdcb) {
5820 NV_ERROR(dev, "Bad Display Configuration Block "
5821 "signature (%08X)\n", sig);
5822 return -EINVAL;
5823 }
7f245b20 5824 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 5825 char sig[8] = { 0 };
5826
5827 strncpy(sig, (char *)&dcbtable[-7], 7);
5828 i2ctabptr = ROM16(dcbtable[2]);
5829 recordlength = 10;
5830 confofs = 6;
5831
5832 if (strcmp(sig, "DEV_REC")) {
5833 NV_ERROR(dev, "Bad Display Configuration Block "
5834 "signature (%s)\n", sig);
5835 return -EINVAL;
5836 }
5837 } else {
5838 /*
5839 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5840 * has the same single (crt) entry, even when tv-out present, so
5841 * the conclusion is this version cannot really be used.
5842 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5843 * 5 entries, which are not specific to the card and so no use.
5844 * v1.2 does have an I2C table that read_dcb_i2c_table can
5845 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5846 * pointer, so use the indices parsed in parse_bmp_structure.
5847 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5848 */
5849 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5850 "adding all possible outputs\n");
5851 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5852
5853 /*
5854 * Attempt to detect TV before DVI because the test
5855 * for the former is more accurate and it rules the
5856 * latter out.
5857 */
5858 if (nv04_tv_identify(dev,
5859 bios->legacy.i2c_indices.tv) >= 0)
5860 fabricate_tv_output(dcb, twoHeads);
5861
5862 else if (bios->tmds.output0_script_ptr ||
5863 bios->tmds.output1_script_ptr)
5864 fabricate_dvi_i_output(dcb, twoHeads);
5865
5866 return 0;
5867 }
5868
5869 if (!i2ctabptr)
5870 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5871 else {
7f245b20
BS		 5872 dcb->i2c_table = &bios->data[i2ctabptr];
5873 if (dcb->version >= 0x30)
5874 dcb->i2c_default_indices = dcb->i2c_table[4];
6ee73861
BS		 5875 }
5876
6ee73861
BS		 5877 if (entries > DCB_MAX_NUM_ENTRIES)
5878 entries = DCB_MAX_NUM_ENTRIES;
5879
5880 for (i = 0; i < entries; i++) {
5881 uint32_t connection, config = 0;
5882
5883 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5884 if (configblock)
5885 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5886
5887 /* seen on an NV11 with DCB v1.5 */
5888 if (connection == 0x00000000)
5889 break;
5890
5891 /* seen on an NV17 with DCB v2.0 */
5892 if (connection == 0xffffffff)
5893 break;
5894
5895 if ((connection & 0x0000000f) == 0x0000000f)
5896 continue;
5897
5898 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5899 dcb->entries, connection, config);
5900
7f245b20 5901 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 5902 break;
5903 }
5904
5905 /*
5906 * apart for v2.1+ not being known for requiring merging, this
5907 * guarantees dcbent->index is the index of the entry in the rom image
5908 */
7f245b20 5909 if (dcb->version < 0x21)
6ee73861
BS		 5910 merge_like_dcb_entries(dev, dcb);
5911
54abb5dd
BS		 5912 if (!dcb->entries)
5913 return -ENXIO;
5914
5915 parse_dcb_gpio_table(bios);
5916 parse_dcb_connector_table(bios);
5917 return 0;
6ee73861
BS		 5918}
5919
5920static void
5921fixup_legacy_connector(struct nvbios *bios)
5922{
7f245b20 5923 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 5924 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 5925
5926 /*
5927 * DCB 3.0 also has the table in most cases, but there are some cards
5928 * where the table is filled with stub entries, and the DCB entriy
5929 * indices are all 0. We don't need the connector indices on pre-G80
5930 * chips (yet?) so limit the use to DCB 4.0 and above.
5931 */
7f245b20 5932 if (dcb->version >= 0x40)
6ee73861
BS		 5933 return;
5934
dc5bc4ed
BS		 5935 dcb->connector.entries = 0;
5936
6ee73861
BS		 5937 /*
5938 * No known connector info before v3.0, so make it up. the rule here
5939 * is: anything on the same i2c bus is considered to be on the same
5940 * connector. any output without an associated i2c bus is assigned
5941 * its own unique connector index.
5942 */
5943 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 5944 /*
5945 * Ignore the I2C index for on-chip TV-out, as there
5946 * are cards with bogus values (nv31m in bug 23212),
5947 * and it's otherwise useless.
5948 */
5949 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 5950 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 5951 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 5952 i2c = dcb->entry[i].i2c_index;
5953
5954 if (i2c_conn[i2c]) {
5955 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 5956 continue;
5957 }
5958
dc5bc4ed
BS		 5959 dcb->entry[i].connector = dcb->connector.entries++;
5960 if (i2c != 0xf)
5961 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 5962 }
5963
dc5bc4ed
BS		 5964 /* Fake the connector table as well as just connector indices */
5965 for (i = 0; i < dcb->connector.entries; i++) {
5966 dcb->connector.entry[i].index = i;
5967 dcb->connector.entry[i].type = divine_connector_type(bios, i);
5968 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 5969 }
5970}
5971
5972static void
5973fixup_legacy_i2c(struct nvbios *bios)
5974{
7f245b20 5975 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 5976 int i;
5977
5978 for (i = 0; i < dcb->entries; i++) {
5979 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
5980 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
5981 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
5982 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
5983 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
5984 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
5985 }
5986}
5987
5988static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5989{
5990 /*
5991 * The header following the "HWSQ" signature has the number of entries,
5992 * and the entry size
5993 *
5994 * An entry consists of a dword to write to the sequencer control reg
5995 * (0x00001304), followed by the ucode bytes, written sequentially,
5996 * starting at reg 0x00001400
5997 */
5998
5999 uint8_t bytes_to_write;
6000 uint16_t hwsq_entry_offset;
6001 int i;
6002
6003 if (bios->data[hwsq_offset] <= entry) {
6004 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6005 "requested entry\n");
6006 return -ENOENT;
6007 }
6008
6009 bytes_to_write = bios->data[hwsq_offset + 1];
6010
6011 if (bytes_to_write != 36) {
6012 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6013 return -EINVAL;
6014 }
6015
6016 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6017
6018 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6019
6020 /* set sequencer control */
6021 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6022 bytes_to_write -= 4;
6023
6024 /* write ucode */
6025 for (i = 0; i < bytes_to_write; i += 4)
6026 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6027
6028 /* twiddle NV_PBUS_DEBUG_4 */
6029 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6030
6031 return 0;
6032}
6033
6034static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6035 struct nvbios *bios)
6036{
6037 /*
6038 * BMP based cards, from NV17, need a microcode loading to correctly
6039 * control the GPIO etc for LVDS panels
6040 *
6041 * BIT based cards seem to do this directly in the init scripts
6042 *
6043 * The microcode entries are found by the "HWSQ" signature.
6044 */
6045
6046 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6047 const int sz = sizeof(hwsq_signature);
6048 int hwsq_offset;
6049
6050 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6051 if (!hwsq_offset)
6052 return 0;
6053
6054 /* always use entry 0? */
6055 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6056}
6057
6058uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6059{
6060 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6061 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6062 const uint8_t edid_sig[] = {
6063 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6064 uint16_t offset = 0;
6065 uint16_t newoffset;
6066 int searchlen = NV_PROM_SIZE;
6067
6068 if (bios->fp.edid)
6069 return bios->fp.edid;
6070
6071 while (searchlen) {
6072 newoffset = findstr(&bios->data[offset], searchlen,
6073 edid_sig, 8);
6074 if (!newoffset)
6075 return NULL;
6076 offset += newoffset;
6077 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6078 break;
6079
6080 searchlen -= offset;
6081 offset++;
6082 }
6083
6084 NV_TRACE(dev, "Found EDID in BIOS\n");
6085
6086 return bios->fp.edid = &bios->data[offset];
6087}
6088
6089void
6090nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6091 struct dcb_entry *dcbent)
6092{
6093 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6094 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6095 struct init_exec iexec = { true, false };
6096
d9184fa9 6097 mutex_lock(&bios->lock);
6ee73861
BS		 6098 bios->display.output = dcbent;
6099 parse_init_table(bios, table, &iexec);
6100 bios->display.output = NULL;
d9184fa9 6101 mutex_unlock(&bios->lock);
6ee73861
BS		 6102}
6103
6104static bool NVInitVBIOS(struct drm_device *dev)
6105{
6106 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6107 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6108
6109 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 6110 mutex_init(&bios->lock);
6ee73861
BS		 6111 bios->dev = dev;
6112
6113 if (!NVShadowVBIOS(dev, bios->data))
6114 return false;
6115
6116 bios->length = NV_PROM_SIZE;
6117 return true;
6118}
6119
6120static int nouveau_parse_vbios_struct(struct drm_device *dev)
6121{
6122 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6123 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6124 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6125 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6126 int offset;
6127
6128 offset = findstr(bios->data, bios->length,
6129 bit_signature, sizeof(bit_signature));
6130 if (offset) {
6131 NV_TRACE(dev, "BIT BIOS found\n");
6132 return parse_bit_structure(bios, offset + 6);
6133 }
6134
6135 offset = findstr(bios->data, bios->length,
6136 bmp_signature, sizeof(bmp_signature));
6137 if (offset) {
6138 NV_TRACE(dev, "BMP BIOS found\n");
6139 return parse_bmp_structure(dev, bios, offset);
6140 }
6141
6142 NV_ERROR(dev, "No known BIOS signature found\n");
6143 return -ENODEV;
6144}
6145
6146int
6147nouveau_run_vbios_init(struct drm_device *dev)
6148{
6149 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6150 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6151 int i, ret = 0;
6152
6153 NVLockVgaCrtcs(dev, false);
6154 if (nv_two_heads(dev))
6155 NVSetOwner(dev, bios->state.crtchead);
6156
6157 if (bios->major_version < 5) /* BMP only */
6158 load_nv17_hw_sequencer_ucode(dev, bios);
6159
6160 if (bios->execute) {
6161 bios->fp.last_script_invoc = 0;
6162 bios->fp.lvds_init_run = false;
6163 }
6164
6165 parse_init_tables(bios);
6166
6167 /*
6168 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6169 * parser will run this right after the init tables, the binary
6170 * driver appears to run it at some point later.
6171 */
6172 if (bios->some_script_ptr) {
6173 struct init_exec iexec = {true, false};
6174
6175 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6176 bios->some_script_ptr);
6177 parse_init_table(bios, bios->some_script_ptr, &iexec);
6178 }
6179
6180 if (dev_priv->card_type >= NV_50) {
7f245b20 6181 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6182 nouveau_bios_run_display_table(dev,
7f245b20 6183 &bios->dcb.entry[i],
6ee73861
BS		 6184 0, 0);
6185 }
6186 }
6187
6188 NVLockVgaCrtcs(dev, true);
6189
6190 return ret;
6191}
6192
6193static void
6194nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6195{
6196 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6197 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6198 struct dcb_i2c_entry *entry;
6199 int i;
6200
7f245b20 6201 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6202 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6203 nouveau_i2c_fini(dev, entry);
6204}
6205
6206int
6207nouveau_bios_init(struct drm_device *dev)
6208{
6209 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6210 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6211 uint32_t saved_nv_pextdev_boot_0;
6212 bool was_locked;
6213 int ret;
6214
6ee73861
BS		 6215 if (!NVInitVBIOS(dev))
6216 return -ENODEV;
6217
6218 ret = nouveau_parse_vbios_struct(dev);
6219 if (ret)
6220 return ret;
6221
6222 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6223 if (ret)
6224 return ret;
6225
6226 fixup_legacy_i2c(bios);
6227 fixup_legacy_connector(bios);
6228
6229 if (!bios->major_version) /* we don't run version 0 bios */
6230 return 0;
6231
6232 /* these will need remembering across a suspend */
6233 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6234 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6235
6236 /* init script execution disabled */
6237 bios->execute = false;
6238
6239 /* ... unless card isn't POSTed already */
6240 if (dev_priv->card_type >= NV_10 &&
6241 NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6242 NVReadVgaCrtc(dev, 0, 0x1a) == 0) {
6243 NV_INFO(dev, "Adaptor not initialised\n");
6244 if (dev_priv->card_type < NV_50) {
6245 NV_ERROR(dev, "Unable to POST this chipset\n");
6246 return -ENODEV;
6247 }
6248
6249 NV_INFO(dev, "Running VBIOS init tables\n");
6250 bios->execute = true;
6251 }
6252
6253 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6254
6255 ret = nouveau_run_vbios_init(dev);
04a39c57 6256 if (ret)
6ee73861 6257 return ret;
6ee73861
BS		 6258
6259 /* feature_byte on BMP is poor, but init always sets CR4B */
6260 was_locked = NVLockVgaCrtcs(dev, false);
6261 if (bios->major_version < 5)
6262 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6263
6264 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6265 if (bios->is_mobile || bios->major_version >= 5)
6266 ret = parse_fp_mode_table(dev, bios);
6267 NVLockVgaCrtcs(dev, was_locked);
6268
6269 /* allow subsequent scripts to execute */
6270 bios->execute = true;
6271
6272 return 0;
6273}
6274
6275void
6276nouveau_bios_takedown(struct drm_device *dev)
6277{
6278 nouveau_bios_i2c_devices_takedown(dev);
6279}
Clone of davem's net-next-2.6 tree