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drm/nouveau: new gem pushbuf interface, bump to 0.0.16
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
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6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
29
30/* these defines are made up */
31#define NV_CIO_CRE_44_HEADA 0x0
32#define NV_CIO_CRE_44_HEADB 0x3
33#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
34#define LEGACY_I2C_CRT 0x80
35#define LEGACY_I2C_PANEL 0x81
36#define LEGACY_I2C_TV 0x82
37
38#define EDID1_LEN 128
39
40#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41#define LOG_OLD_VALUE(x)
42
43#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
44#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
45
46struct init_exec {
47 bool execute;
48 bool repeat;
49};
50
51static bool nv_cksum(const uint8_t *data, unsigned int length)
52{
53 /*
54 * There's a few checksums in the BIOS, so here's a generic checking
55 * function.
56 */
57 int i;
58 uint8_t sum = 0;
59
60 for (i = 0; i < length; i++)
61 sum += data[i];
62
63 if (sum)
64 return true;
65
66 return false;
67}
68
69static int
70score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
71{
72 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
73 NV_TRACEWARN(dev, "... BIOS signature not found\n");
74 return 0;
75 }
76
77 if (nv_cksum(data, data[2] * 512)) {
78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable ? 2 : 1;
81 } else
82 NV_TRACE(dev, "... appears to be valid\n");
83
84 return 3;
85}
86
87static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
88{
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 uint32_t pci_nv_20, save_pci_nv_20;
91 int pcir_ptr;
92 int i;
93
94 if (dev_priv->card_type >= NV_50)
95 pci_nv_20 = 0x88050;
96 else
97 pci_nv_20 = NV_PBUS_PCI_NV_20;
98
99 /* enable ROM access */
100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
101 nvWriteMC(dev, pci_nv_20,
102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
103
104 /* bail if no rom signature */
105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
107 goto out;
108
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
116 goto out;
117
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
121 */
122 for (i = 0; i < NV_PROM_SIZE; i++)
123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
124
125out:
126 /* disable ROM access */
127 nvWriteMC(dev, pci_nv_20,
128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
129}
130
131static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
132{
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 uint32_t old_bar0_pramin = 0;
135 int i;
136
137 if (dev_priv->card_type >= NV_50) {
138 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
139
140 if (!vbios_vram)
141 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
142
143 old_bar0_pramin = nv_rd32(dev, 0x1700);
144 nv_wr32(dev, 0x1700, vbios_vram >> 16);
145 }
146
147 /* bail if no rom signature */
148 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
149 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
150 goto out;
151
152 for (i = 0; i < NV_PROM_SIZE; i++)
153 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
154
155out:
156 if (dev_priv->card_type >= NV_50)
157 nv_wr32(dev, 0x1700, old_bar0_pramin);
158}
159
160static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
161{
162 void __iomem *rom = NULL;
163 size_t rom_len;
164 int ret;
165
166 ret = pci_enable_rom(dev->pdev);
167 if (ret)
168 return;
169
170 rom = pci_map_rom(dev->pdev, &rom_len);
171 if (!rom)
172 goto out;
173 memcpy_fromio(data, rom, rom_len);
174 pci_unmap_rom(dev->pdev, rom);
175
176out:
177 pci_disable_rom(dev->pdev);
178}
179
180struct methods {
181 const char desc[8];
182 void (*loadbios)(struct drm_device *, uint8_t *);
183 const bool rw;
6ee73861
BS		 184};
185
186static struct methods nv04_methods[] = {
187 { "PROM", load_vbios_prom, false },
188 { "PRAMIN", load_vbios_pramin, true },
189 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 190};
191
192static struct methods nv50_methods[] = {
193 { "PRAMIN", load_vbios_pramin, true },
194 { "PROM", load_vbios_prom, false },
195 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 196};
197
657b6245
MK		 198#define METHODCNT 3
199
6ee73861
BS		 200static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
201{
202 struct drm_nouveau_private *dev_priv = dev->dev_private;
657b6245
MK		 203 struct methods *methods;
204 int i;
6ee73861 205 int testscore = 3;
657b6245 206 int scores[METHODCNT];
6ee73861
BS		 207
208 if (nouveau_vbios) {
657b6245
MK		 209 methods = nv04_methods;
210 for (i = 0; i < METHODCNT; i++)
211 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 212 break;
6ee73861 213
657b6245 214 if (i < METHODCNT) {
6ee73861 215 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 216 methods[i].desc);
6ee73861 217
657b6245
MK		 218 methods[i].loadbios(dev, data);
219 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 220 return true;
221 }
222
223 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
224 }
225
226 if (dev_priv->card_type < NV_50)
227 methods = nv04_methods;
228 else
229 methods = nv50_methods;
230
657b6245 231 for (i = 0; i < METHODCNT; i++) {
6ee73861 232 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 233 methods[i].desc);
6ee73861 234 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 235 methods[i].loadbios(dev, data);
236 scores[i] = score_vbios(dev, data, methods[i].rw);
237 if (scores[i] == testscore)
6ee73861 238 return true;
6ee73861
BS		 239 }
240
241 while (--testscore > 0) {
657b6245
MK		 242 for (i = 0; i < METHODCNT; i++) {
243 if (scores[i] == testscore) {
6ee73861 244 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 245 methods[i].desc);
246 methods[i].loadbios(dev, data);
6ee73861
BS		 247 return true;
248 }
6ee73861
BS		 249 }
250 }
251
252 NV_ERROR(dev, "No valid BIOS image found\n");
253 return false;
254}
255
256struct init_tbl_entry {
257 char *name;
258 uint8_t id;
37383650 259 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 260};
261
262struct bit_entry {
263 uint8_t id[2];
264 uint16_t length;
265 uint16_t offset;
266};
267
268static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
269
270#define MACRO_INDEX_SIZE 2
271#define MACRO_SIZE 8
272#define CONDITION_SIZE 12
273#define IO_FLAG_CONDITION_SIZE 9
274#define IO_CONDITION_SIZE 5
275#define MEM_INIT_SIZE 66
276
277static void still_alive(void)
278{
279#if 0
280 sync();
281 msleep(2);
282#endif
283}
284
285static uint32_t
286munge_reg(struct nvbios *bios, uint32_t reg)
287{
288 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
289 struct dcb_entry *dcbent = bios->display.output;
290
291 if (dev_priv->card_type < NV_50)
292 return reg;
293
294 if (reg & 0x40000000) {
295 BUG_ON(!dcbent);
296
297 reg += (ffs(dcbent->or) - 1) * 0x800;
298 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
299 reg += 0x00000080;
300 }
301
302 reg &= ~0x60000000;
303 return reg;
304}
305
306static int
307valid_reg(struct nvbios *bios, uint32_t reg)
308{
309 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
310 struct drm_device *dev = bios->dev;
311
312 /* C51 has misaligned regs on purpose. Marvellous */
9855e584
BS		 313 if (reg & 0x2 ||
314 (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51))
315 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
316
317 /* warn on C51 regs that haven't been verified accessible in tracing */
6ee73861
BS		 318 if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 &&
319 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
320 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
321 reg);
322
9855e584
BS		 323 if (reg >= (8*1024*1024)) {
324 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
325 return 0;
6ee73861 326 }
9855e584
BS		 327
328 return 1;
6ee73861
BS		 329}
330
331static bool
332valid_idx_port(struct nvbios *bios, uint16_t port)
333{
334 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
335 struct drm_device *dev = bios->dev;
336
337 /*
338 * If adding more ports here, the read/write functions below will need
339 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
340 * used for the port in question
341 */
342 if (dev_priv->card_type < NV_50) {
343 if (port == NV_CIO_CRX__COLOR)
344 return true;
345 if (port == NV_VIO_SRX)
346 return true;
347 } else {
348 if (port == NV_CIO_CRX__COLOR)
349 return true;
350 }
351
352 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
353 port);
354
355 return false;
356}
357
358static bool
359valid_port(struct nvbios *bios, uint16_t port)
360{
361 struct drm_device *dev = bios->dev;
362
363 /*
364 * If adding more ports here, the read/write functions below will need
365 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
366 * used for the port in question
367 */
368 if (port == NV_VIO_VSE2)
369 return true;
370
371 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
372
373 return false;
374}
375
376static uint32_t
377bios_rd32(struct nvbios *bios, uint32_t reg)
378{
379 uint32_t data;
380
381 reg = munge_reg(bios, reg);
382 if (!valid_reg(bios, reg))
383 return 0;
384
385 /*
386 * C51 sometimes uses regs with bit0 set in the address. For these
387 * cases there should exist a translation in a BIOS table to an IO
388 * port address which the BIOS uses for accessing the reg
389 *
390 * These only seem to appear for the power control regs to a flat panel,
391 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
392 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
393 * suspend-resume mmio trace from a C51 will be required to see if this
394 * is true for the power microcode in 0x14.., or whether the direct IO
395 * port access method is needed
396 */
397 if (reg & 0x1)
398 reg &= ~0x1;
399
400 data = nv_rd32(bios->dev, reg);
401
402 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
403
404 return data;
405}
406
407static void
408bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
409{
410 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
411
412 reg = munge_reg(bios, reg);
413 if (!valid_reg(bios, reg))
414 return;
415
416 /* see note in bios_rd32 */
417 if (reg & 0x1)
418 reg &= 0xfffffffe;
419
420 LOG_OLD_VALUE(bios_rd32(bios, reg));
421 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
422
423 if (dev_priv->VBIOS.execute) {
424 still_alive();
425 nv_wr32(bios->dev, reg, data);
426 }
427}
428
429static uint8_t
430bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
431{
432 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
433 struct drm_device *dev = bios->dev;
434 uint8_t data;
435
436 if (!valid_idx_port(bios, port))
437 return 0;
438
439 if (dev_priv->card_type < NV_50) {
440 if (port == NV_VIO_SRX)
441 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
442 else /* assume NV_CIO_CRX__COLOR */
443 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
444 } else {
445 uint32_t data32;
446
447 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
448 data = (data32 >> ((index & 3) << 3)) & 0xff;
449 }
450
451 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
452 "Head: 0x%02X, Data: 0x%02X\n",
453 port, index, bios->state.crtchead, data);
454 return data;
455}
456
457static void
458bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
459{
460 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
461 struct drm_device *dev = bios->dev;
462
463 if (!valid_idx_port(bios, port))
464 return;
465
466 /*
467 * The current head is maintained in the nvbios member state.crtchead.
468 * We trap changes to CR44 and update the head variable and hence the
469 * register set written.
470 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
471 * of the write, and to head1 after the write
472 */
473 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
474 data != NV_CIO_CRE_44_HEADB)
475 bios->state.crtchead = 0;
476
477 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
478 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
479 "Head: 0x%02X, Data: 0x%02X\n",
480 port, index, bios->state.crtchead, data);
481
482 if (bios->execute && dev_priv->card_type < NV_50) {
483 still_alive();
484 if (port == NV_VIO_SRX)
485 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
486 else /* assume NV_CIO_CRX__COLOR */
487 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
488 } else
489 if (bios->execute) {
490 uint32_t data32, shift = (index & 3) << 3;
491
492 still_alive();
493
494 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
495 data32 &= ~(0xff << shift);
496 data32 |= (data << shift);
497 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
498 }
499
500 if (port == NV_CIO_CRX__COLOR &&
501 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
502 bios->state.crtchead = 1;
503}
504
505static uint8_t
506bios_port_rd(struct nvbios *bios, uint16_t port)
507{
508 uint8_t data, head = bios->state.crtchead;
509
510 if (!valid_port(bios, port))
511 return 0;
512
513 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
514
515 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
516 port, head, data);
517
518 return data;
519}
520
521static void
522bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
523{
524 int head = bios->state.crtchead;
525
526 if (!valid_port(bios, port))
527 return;
528
529 LOG_OLD_VALUE(bios_port_rd(bios, port));
530 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
531 port, head, data);
532
533 if (!bios->execute)
534 return;
535
536 still_alive();
537 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
538}
539
540static bool
541io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
542{
543 /*
544 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
545 * for the CRTC index; 1 byte for the mask to apply to the value
546 * retrieved from the CRTC; 1 byte for the shift right to apply to the
547 * masked CRTC value; 2 bytes for the offset to the flag array, to
548 * which the shifted value is added; 1 byte for the mask applied to the
549 * value read from the flag array; and 1 byte for the value to compare
550 * against the masked byte from the flag table.
551 */
552
553 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
554 uint16_t crtcport = ROM16(bios->data[condptr]);
555 uint8_t crtcindex = bios->data[condptr + 2];
556 uint8_t mask = bios->data[condptr + 3];
557 uint8_t shift = bios->data[condptr + 4];
558 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
559 uint8_t flagarraymask = bios->data[condptr + 7];
560 uint8_t cmpval = bios->data[condptr + 8];
561 uint8_t data;
562
563 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
564 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
565 "Cmpval: 0x%02X\n",
566 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
567
568 data = bios_idxprt_rd(bios, crtcport, crtcindex);
569
570 data = bios->data[flagarray + ((data & mask) >> shift)];
571 data &= flagarraymask;
572
573 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
574 offset, data, cmpval);
575
576 return (data == cmpval);
577}
578
579static bool
580bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
581{
582 /*
583 * The condition table entry has 4 bytes for the address of the
584 * register to check, 4 bytes for a mask to apply to the register and
585 * 4 for a test comparison value
586 */
587
588 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
589 uint32_t reg = ROM32(bios->data[condptr]);
590 uint32_t mask = ROM32(bios->data[condptr + 4]);
591 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
592 uint32_t data;
593
594 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
595 offset, cond, reg, mask);
596
597 data = bios_rd32(bios, reg) & mask;
598
599 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
600 offset, data, cmpval);
601
602 return (data == cmpval);
603}
604
605static bool
606io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
607{
608 /*
609 * The IO condition entry has 2 bytes for the IO port address; 1 byte
610 * for the index to write to io_port; 1 byte for the mask to apply to
611 * the byte read from io_port+1; and 1 byte for the value to compare
612 * against the masked byte.
613 */
614
615 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
616 uint16_t io_port = ROM16(bios->data[condptr]);
617 uint8_t port_index = bios->data[condptr + 2];
618 uint8_t mask = bios->data[condptr + 3];
619 uint8_t cmpval = bios->data[condptr + 4];
620
621 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
622
623 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
624 offset, data, cmpval);
625
626 return (data == cmpval);
627}
628
629static int
630nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
631{
632 struct drm_nouveau_private *dev_priv = dev->dev_private;
633 uint32_t reg0 = nv_rd32(dev, reg + 0);
634 uint32_t reg1 = nv_rd32(dev, reg + 4);
635 struct nouveau_pll_vals pll;
636 struct pll_lims pll_limits;
637 int ret;
638
639 ret = get_pll_limits(dev, reg, &pll_limits);
640 if (ret)
641 return ret;
642
643 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
644 if (!clk)
645 return -ERANGE;
646
647 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
648 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
649
650 if (dev_priv->VBIOS.execute) {
651 still_alive();
652 nv_wr32(dev, reg + 4, reg1);
653 nv_wr32(dev, reg + 0, reg0);
654 }
655
656 return 0;
657}
658
659static int
660setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
661{
662 struct drm_device *dev = bios->dev;
663 struct drm_nouveau_private *dev_priv = dev->dev_private;
664 /* clk in kHz */
665 struct pll_lims pll_lim;
666 struct nouveau_pll_vals pllvals;
667 int ret;
668
669 if (dev_priv->card_type >= NV_50)
670 return nv50_pll_set(dev, reg, clk);
671
672 /* high regs (such as in the mac g5 table) are not -= 4 */
673 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
674 if (ret)
675 return ret;
676
677 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
678 if (!clk)
679 return -ERANGE;
680
681 if (bios->execute) {
682 still_alive();
683 nouveau_hw_setpll(dev, reg, &pllvals);
684 }
685
686 return 0;
687}
688
689static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
690{
691 struct drm_nouveau_private *dev_priv = dev->dev_private;
692 struct nvbios *bios = &dev_priv->VBIOS;
693
694 /*
695 * For the results of this function to be correct, CR44 must have been
696 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
697 * and the DCB table parsed, before the script calling the function is
698 * run. run_digital_op_script is example of how to do such setup
699 */
700
701 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
702
703 if (dcb_entry > bios->bdcb.dcb.entries) {
704 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
705 "(%02X)\n", dcb_entry);
706 dcb_entry = 0x7f; /* unused / invalid marker */
707 }
708
709 return dcb_entry;
710}
711
712static struct nouveau_i2c_chan *
713init_i2c_device_find(struct drm_device *dev, int i2c_index)
714{
715 struct drm_nouveau_private *dev_priv = dev->dev_private;
716 struct bios_parsed_dcb *bdcb = &dev_priv->VBIOS.bdcb;
717
718 if (i2c_index == 0xff) {
719 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
720 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
721 int default_indices = bdcb->i2c_default_indices;
722
723 if (idx != 0x7f && bdcb->dcb.entry[idx].i2c_upper_default)
724 shift = 4;
725
726 i2c_index = (default_indices >> shift) & 0xf;
727 }
728 if (i2c_index == 0x80) /* g80+ */
729 i2c_index = bdcb->i2c_default_indices & 0xf;
730
731 return nouveau_i2c_find(dev, i2c_index);
732}
733
734static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
735{
736 /*
737 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
738 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
739 * CR58 for CR57 = 0 to index a table of offsets to the basic
740 * 0x6808b0 address.
741 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
742 * CR58 for CR57 = 0 to index a table of offsets to the basic
743 * 0x6808b0 address, and then flip the offset by 8.
744 */
745
746 struct drm_nouveau_private *dev_priv = dev->dev_private;
747 const int pramdac_offset[13] = {
748 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
749 const uint32_t pramdac_table[4] = {
750 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
751
752 if (mlv >= 0x80) {
753 int dcb_entry, dacoffset;
754
755 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
756 dcb_entry = dcb_entry_idx_from_crtchead(dev);
757 if (dcb_entry == 0x7f)
758 return 0;
759 dacoffset = pramdac_offset[
760 dev_priv->VBIOS.bdcb.dcb.entry[dcb_entry].or];
761 if (mlv == 0x81)
762 dacoffset ^= 8;
763 return 0x6808b0 + dacoffset;
764 } else {
765 if (mlv > ARRAY_SIZE(pramdac_table)) {
766 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
767 mlv);
768 return 0;
769 }
770 return pramdac_table[mlv];
771 }
772}
773
37383650 774static int
6ee73861
BS		 775init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
776 struct init_exec *iexec)
777{
778 /*
779 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
780 *
781 * offset (8 bit): opcode
782 * offset + 1 (16 bit): CRTC port
783 * offset + 3 (8 bit): CRTC index
784 * offset + 4 (8 bit): mask
785 * offset + 5 (8 bit): shift
786 * offset + 6 (8 bit): count
787 * offset + 7 (32 bit): register
788 * offset + 11 (32 bit): configuration 1
789 * ...
790 *
791 * Starting at offset + 11 there are "count" 32 bit values.
792 * To find out which value to use read index "CRTC index" on "CRTC
793 * port", AND this value with "mask" and then bit shift right "shift"
794 * bits. Read the appropriate value using this index and write to
795 * "register"
796 */
797
798 uint16_t crtcport = ROM16(bios->data[offset + 1]);
799 uint8_t crtcindex = bios->data[offset + 3];
800 uint8_t mask = bios->data[offset + 4];
801 uint8_t shift = bios->data[offset + 5];
802 uint8_t count = bios->data[offset + 6];
803 uint32_t reg = ROM32(bios->data[offset + 7]);
804 uint8_t config;
805 uint32_t configval;
37383650 806 int len = 11 + count * 4;
6ee73861
BS		 807
808 if (!iexec->execute)
37383650 809 return len;
6ee73861
BS		 810
811 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
812 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
813 offset, crtcport, crtcindex, mask, shift, count, reg);
814
815 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
816 if (config > count) {
817 NV_ERROR(bios->dev,
818 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
819 offset, config, count);
37383650 820 return 0;
6ee73861
BS		 821 }
822
823 configval = ROM32(bios->data[offset + 11 + config * 4]);
824
825 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
826
827 bios_wr32(bios, reg, configval);
828
37383650 829 return len;
6ee73861
BS		 830}
831
37383650 832static int
6ee73861
BS		 833init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
834{
835 /*
836 * INIT_REPEAT opcode: 0x33 ('3')
837 *
838 * offset (8 bit): opcode
839 * offset + 1 (8 bit): count
840 *
841 * Execute script following this opcode up to INIT_REPEAT_END
842 * "count" times
843 */
844
845 uint8_t count = bios->data[offset + 1];
846 uint8_t i;
847
848 /* no iexec->execute check by design */
849
850 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
851 offset, count);
852
853 iexec->repeat = true;
854
855 /*
856 * count - 1, as the script block will execute once when we leave this
857 * opcode -- this is compatible with bios behaviour as:
858 * a) the block is always executed at least once, even if count == 0
859 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
860 * while we don't
861 */
862 for (i = 0; i < count - 1; i++)
863 parse_init_table(bios, offset + 2, iexec);
864
865 iexec->repeat = false;
866
37383650 867 return 2;
6ee73861
BS		 868}
869
37383650 870static int
6ee73861
BS		 871init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
872 struct init_exec *iexec)
873{
874 /*
875 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
876 *
877 * offset (8 bit): opcode
878 * offset + 1 (16 bit): CRTC port
879 * offset + 3 (8 bit): CRTC index
880 * offset + 4 (8 bit): mask
881 * offset + 5 (8 bit): shift
882 * offset + 6 (8 bit): IO flag condition index
883 * offset + 7 (8 bit): count
884 * offset + 8 (32 bit): register
885 * offset + 12 (16 bit): frequency 1
886 * ...
887 *
888 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
889 * Set PLL register "register" to coefficients for frequency n,
890 * selected by reading index "CRTC index" of "CRTC port" ANDed with
891 * "mask" and shifted right by "shift".
892 *
893 * If "IO flag condition index" > 0, and condition met, double
894 * frequency before setting it.
895 */
896
897 uint16_t crtcport = ROM16(bios->data[offset + 1]);
898 uint8_t crtcindex = bios->data[offset + 3];
899 uint8_t mask = bios->data[offset + 4];
900 uint8_t shift = bios->data[offset + 5];
901 int8_t io_flag_condition_idx = bios->data[offset + 6];
902 uint8_t count = bios->data[offset + 7];
903 uint32_t reg = ROM32(bios->data[offset + 8]);
904 uint8_t config;
905 uint16_t freq;
37383650 906 int len = 12 + count * 2;
6ee73861
BS		 907
908 if (!iexec->execute)
37383650 909 return len;
6ee73861
BS		 910
911 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
912 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
913 "Count: 0x%02X, Reg: 0x%08X\n",
914 offset, crtcport, crtcindex, mask, shift,
915 io_flag_condition_idx, count, reg);
916
917 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
918 if (config > count) {
919 NV_ERROR(bios->dev,
920 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
921 offset, config, count);
37383650 922 return 0;
6ee73861
BS		 923 }
924
925 freq = ROM16(bios->data[offset + 12 + config * 2]);
926
927 if (io_flag_condition_idx > 0) {
928 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
929 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
930 "frequency doubled\n", offset);
931 freq *= 2;
932 } else
933 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
934 "frequency unchanged\n", offset);
935 }
936
937 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
938 offset, reg, config, freq);
939
940 setPLL(bios, reg, freq * 10);
941
37383650 942 return len;
6ee73861
BS		 943}
944
37383650 945static int
6ee73861
BS		 946init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
947{
948 /*
949 * INIT_END_REPEAT opcode: 0x36 ('6')
950 *
951 * offset (8 bit): opcode
952 *
953 * Marks the end of the block for INIT_REPEAT to repeat
954 */
955
956 /* no iexec->execute check by design */
957
958 /*
959 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
960 * we're not in repeat mode
961 */
962 if (iexec->repeat)
37383650 963 return 0;
6ee73861 964
37383650 965 return 1;
6ee73861
BS		 966}
967
37383650 968static int
6ee73861
BS		 969init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
970{
971 /*
972 * INIT_COPY opcode: 0x37 ('7')
973 *
974 * offset (8 bit): opcode
975 * offset + 1 (32 bit): register
976 * offset + 5 (8 bit): shift
977 * offset + 6 (8 bit): srcmask
978 * offset + 7 (16 bit): CRTC port
979 * offset + 9 (8 bit): CRTC index
980 * offset + 10 (8 bit): mask
981 *
982 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
983 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
984 * port
985 */
986
987 uint32_t reg = ROM32(bios->data[offset + 1]);
988 uint8_t shift = bios->data[offset + 5];
989 uint8_t srcmask = bios->data[offset + 6];
990 uint16_t crtcport = ROM16(bios->data[offset + 7]);
991 uint8_t crtcindex = bios->data[offset + 9];
992 uint8_t mask = bios->data[offset + 10];
993 uint32_t data;
994 uint8_t crtcdata;
995
996 if (!iexec->execute)
37383650 997 return 11;
6ee73861
BS		 998
999 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1000 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1001 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1002
1003 data = bios_rd32(bios, reg);
1004
1005 if (shift < 0x80)
1006 data >>= shift;
1007 else
1008 data <<= (0x100 - shift);
1009
1010 data &= srcmask;
1011
1012 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1013 crtcdata |= (uint8_t)data;
1014 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1015
37383650 1016 return 11;
6ee73861
BS		 1017}
1018
37383650 1019static int
6ee73861
BS		 1020init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1021{
1022 /*
1023 * INIT_NOT opcode: 0x38 ('8')
1024 *
1025 * offset (8 bit): opcode
1026 *
1027 * Invert the current execute / no-execute condition (i.e. "else")
1028 */
1029 if (iexec->execute)
1030 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1031 else
1032 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1033
1034 iexec->execute = !iexec->execute;
37383650 1035 return 1;
6ee73861
BS		 1036}
1037
37383650 1038static int
6ee73861
BS		 1039init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1040 struct init_exec *iexec)
1041{
1042 /*
1043 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1044 *
1045 * offset (8 bit): opcode
1046 * offset + 1 (8 bit): condition number
1047 *
1048 * Check condition "condition number" in the IO flag condition table.
1049 * If condition not met skip subsequent opcodes until condition is
1050 * inverted (INIT_NOT), or we hit INIT_RESUME
1051 */
1052
1053 uint8_t cond = bios->data[offset + 1];
1054
1055 if (!iexec->execute)
37383650 1056 return 2;
6ee73861
BS		 1057
1058 if (io_flag_condition_met(bios, offset, cond))
1059 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1060 else {
1061 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1062 iexec->execute = false;
1063 }
1064
37383650 1065 return 2;
6ee73861
BS		 1066}
1067
37383650 1068static int
6ee73861
BS		 1069init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1070 struct init_exec *iexec)
1071{
1072 /*
1073 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1074 *
1075 * offset (8 bit): opcode
1076 * offset + 1 (32 bit): control register
1077 * offset + 5 (32 bit): data register
1078 * offset + 9 (32 bit): mask
1079 * offset + 13 (32 bit): data
1080 * offset + 17 (8 bit): count
1081 * offset + 18 (8 bit): address 1
1082 * offset + 19 (8 bit): data 1
1083 * ...
1084 *
1085 * For each of "count" address and data pairs, write "data n" to
1086 * "data register", read the current value of "control register",
1087 * and write it back once ANDed with "mask", ORed with "data",
1088 * and ORed with "address n"
1089 */
1090
1091 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1092 uint32_t datareg = ROM32(bios->data[offset + 5]);
1093 uint32_t mask = ROM32(bios->data[offset + 9]);
1094 uint32_t data = ROM32(bios->data[offset + 13]);
1095 uint8_t count = bios->data[offset + 17];
37383650 1096 int len = 18 + count * 2;
6ee73861
BS		 1097 uint32_t value;
1098 int i;
1099
1100 if (!iexec->execute)
37383650 1101 return len;
6ee73861
BS		 1102
1103 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1104 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1105 offset, controlreg, datareg, mask, data, count);
1106
1107 for (i = 0; i < count; i++) {
1108 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1109 uint8_t instdata = bios->data[offset + 19 + i * 2];
1110
1111 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1112 offset, instaddress, instdata);
1113
1114 bios_wr32(bios, datareg, instdata);
1115 value = bios_rd32(bios, controlreg) & mask;
1116 value |= data;
1117 value |= instaddress;
1118 bios_wr32(bios, controlreg, value);
1119 }
1120
37383650 1121 return len;
6ee73861
BS		 1122}
1123
37383650 1124static int
6ee73861
BS		 1125init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1126 struct init_exec *iexec)
1127{
1128 /*
1129 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1130 *
1131 * offset (8 bit): opcode
1132 * offset + 1 (16 bit): CRTC port
1133 * offset + 3 (8 bit): CRTC index
1134 * offset + 4 (8 bit): mask
1135 * offset + 5 (8 bit): shift
1136 * offset + 6 (8 bit): count
1137 * offset + 7 (32 bit): register
1138 * offset + 11 (32 bit): frequency 1
1139 * ...
1140 *
1141 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1142 * Set PLL register "register" to coefficients for frequency n,
1143 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1144 * "mask" and shifted right by "shift".
1145 */
1146
1147 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1148 uint8_t crtcindex = bios->data[offset + 3];
1149 uint8_t mask = bios->data[offset + 4];
1150 uint8_t shift = bios->data[offset + 5];
1151 uint8_t count = bios->data[offset + 6];
1152 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1153 int len = 11 + count * 4;
6ee73861
BS		 1154 uint8_t config;
1155 uint32_t freq;
1156
1157 if (!iexec->execute)
37383650 1158 return len;
6ee73861
BS		 1159
1160 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1161 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1162 offset, crtcport, crtcindex, mask, shift, count, reg);
1163
1164 if (!reg)
37383650 1165 return len;
6ee73861
BS		 1166
1167 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1168 if (config > count) {
1169 NV_ERROR(bios->dev,
1170 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1171 offset, config, count);
37383650 1172 return 0;
6ee73861
BS		 1173 }
1174
1175 freq = ROM32(bios->data[offset + 11 + config * 4]);
1176
1177 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1178 offset, reg, config, freq);
1179
1180 setPLL(bios, reg, freq);
1181
37383650 1182 return len;
6ee73861
BS		 1183}
1184
37383650 1185static int
6ee73861
BS		 1186init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1187{
1188 /*
1189 * INIT_PLL2 opcode: 0x4B ('K')
1190 *
1191 * offset (8 bit): opcode
1192 * offset + 1 (32 bit): register
1193 * offset + 5 (32 bit): freq
1194 *
1195 * Set PLL register "register" to coefficients for frequency "freq"
1196 */
1197
1198 uint32_t reg = ROM32(bios->data[offset + 1]);
1199 uint32_t freq = ROM32(bios->data[offset + 5]);
1200
1201 if (!iexec->execute)
37383650 1202 return 9;
6ee73861
BS		 1203
1204 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1205 offset, reg, freq);
1206
1207 setPLL(bios, reg, freq);
37383650 1208 return 9;
6ee73861
BS		 1209}
1210
37383650 1211static int
6ee73861
BS		 1212init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1213{
1214 /*
1215 * INIT_I2C_BYTE opcode: 0x4C ('L')
1216 *
1217 * offset (8 bit): opcode
1218 * offset + 1 (8 bit): DCB I2C table entry index
1219 * offset + 2 (8 bit): I2C slave address
1220 * offset + 3 (8 bit): count
1221 * offset + 4 (8 bit): I2C register 1
1222 * offset + 5 (8 bit): mask 1
1223 * offset + 6 (8 bit): data 1
1224 * ...
1225 *
1226 * For each of "count" registers given by "I2C register n" on the device
1227 * addressed by "I2C slave address" on the I2C bus given by
1228 * "DCB I2C table entry index", read the register, AND the result with
1229 * "mask n" and OR it with "data n" before writing it back to the device
1230 */
1231
1232 uint8_t i2c_index = bios->data[offset + 1];
1233 uint8_t i2c_address = bios->data[offset + 2];
1234 uint8_t count = bios->data[offset + 3];
37383650 1235 int len = 4 + count * 3;
6ee73861
BS		 1236 struct nouveau_i2c_chan *chan;
1237 struct i2c_msg msg;
1238 int i;
1239
1240 if (!iexec->execute)
37383650 1241 return len;
6ee73861
BS		 1242
1243 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1244 "Count: 0x%02X\n",
1245 offset, i2c_index, i2c_address, count);
1246
1247 chan = init_i2c_device_find(bios->dev, i2c_index);
1248 if (!chan)
37383650 1249 return 0;
6ee73861
BS		 1250
1251 for (i = 0; i < count; i++) {
1252 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
1253 uint8_t mask = bios->data[offset + 5 + i * 3];
1254 uint8_t data = bios->data[offset + 6 + i * 3];
1255 uint8_t value;
1256
1257 msg.addr = i2c_address;
1258 msg.flags = I2C_M_RD;
1259 msg.len = 1;
1260 msg.buf = &value;
1261 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1262 return 0;
6ee73861
BS		 1263
1264 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1265 "Mask: 0x%02X, Data: 0x%02X\n",
1266 offset, i2c_reg, value, mask, data);
1267
1268 value = (value & mask) | data;
1269
1270 if (bios->execute) {
1271 msg.addr = i2c_address;
1272 msg.flags = 0;
1273 msg.len = 1;
1274 msg.buf = &value;
1275 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1276 return 0;
6ee73861
BS		 1277 }
1278 }
1279
37383650 1280 return len;
6ee73861
BS		 1281}
1282
37383650 1283static int
6ee73861
BS		 1284init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1285{
1286 /*
1287 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1288 *
1289 * offset (8 bit): opcode
1290 * offset + 1 (8 bit): DCB I2C table entry index
1291 * offset + 2 (8 bit): I2C slave address
1292 * offset + 3 (8 bit): count
1293 * offset + 4 (8 bit): I2C register 1
1294 * offset + 5 (8 bit): data 1
1295 * ...
1296 *
1297 * For each of "count" registers given by "I2C register n" on the device
1298 * addressed by "I2C slave address" on the I2C bus given by
1299 * "DCB I2C table entry index", set the register to "data n"
1300 */
1301
1302 uint8_t i2c_index = bios->data[offset + 1];
1303 uint8_t i2c_address = bios->data[offset + 2];
1304 uint8_t count = bios->data[offset + 3];
37383650 1305 int len = 4 + count * 2;
6ee73861
BS		 1306 struct nouveau_i2c_chan *chan;
1307 struct i2c_msg msg;
1308 int i;
1309
1310 if (!iexec->execute)
37383650 1311 return len;
6ee73861
BS		 1312
1313 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1314 "Count: 0x%02X\n",
1315 offset, i2c_index, i2c_address, count);
1316
1317 chan = init_i2c_device_find(bios->dev, i2c_index);
1318 if (!chan)
37383650 1319 return 0;
6ee73861
BS		 1320
1321 for (i = 0; i < count; i++) {
1322 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
1323 uint8_t data = bios->data[offset + 5 + i * 2];
1324
1325 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1326 offset, i2c_reg, data);
1327
1328 if (bios->execute) {
1329 msg.addr = i2c_address;
1330 msg.flags = 0;
1331 msg.len = 1;
1332 msg.buf = &data;
1333 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1334 return 0;
6ee73861
BS		 1335 }
1336 }
1337
37383650 1338 return len;
6ee73861
BS		 1339}
1340
37383650 1341static int
6ee73861
BS		 1342init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1343{
1344 /*
1345 * INIT_ZM_I2C opcode: 0x4E ('N')
1346 *
1347 * offset (8 bit): opcode
1348 * offset + 1 (8 bit): DCB I2C table entry index
1349 * offset + 2 (8 bit): I2C slave address
1350 * offset + 3 (8 bit): count
1351 * offset + 4 (8 bit): data 1
1352 * ...
1353 *
1354 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1355 * address" on the I2C bus given by "DCB I2C table entry index"
1356 */
1357
1358 uint8_t i2c_index = bios->data[offset + 1];
1359 uint8_t i2c_address = bios->data[offset + 2];
1360 uint8_t count = bios->data[offset + 3];
37383650 1361 int len = 4 + count;
6ee73861
BS		 1362 struct nouveau_i2c_chan *chan;
1363 struct i2c_msg msg;
1364 uint8_t data[256];
1365 int i;
1366
1367 if (!iexec->execute)
37383650 1368 return len;
6ee73861
BS		 1369
1370 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1371 "Count: 0x%02X\n",
1372 offset, i2c_index, i2c_address, count);
1373
1374 chan = init_i2c_device_find(bios->dev, i2c_index);
1375 if (!chan)
37383650 1376 return 0;
6ee73861
BS		 1377
1378 for (i = 0; i < count; i++) {
1379 data[i] = bios->data[offset + 4 + i];
1380
1381 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1382 }
1383
1384 if (bios->execute) {
1385 msg.addr = i2c_address;
1386 msg.flags = 0;
1387 msg.len = count;
1388 msg.buf = data;
1389 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1390 return 0;
6ee73861
BS		 1391 }
1392
37383650 1393 return len;
6ee73861
BS		 1394}
1395
37383650 1396static int
6ee73861
BS		 1397init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1398{
1399 /*
1400 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1401 *
1402 * offset (8 bit): opcode
1403 * offset + 1 (8 bit): magic lookup value
1404 * offset + 2 (8 bit): TMDS address
1405 * offset + 3 (8 bit): mask
1406 * offset + 4 (8 bit): data
1407 *
1408 * Read the data reg for TMDS address "TMDS address", AND it with mask
1409 * and OR it with data, then write it back
1410 * "magic lookup value" determines which TMDS base address register is
1411 * used -- see get_tmds_index_reg()
1412 */
1413
1414 uint8_t mlv = bios->data[offset + 1];
1415 uint32_t tmdsaddr = bios->data[offset + 2];
1416 uint8_t mask = bios->data[offset + 3];
1417 uint8_t data = bios->data[offset + 4];
1418 uint32_t reg, value;
1419
1420 if (!iexec->execute)
37383650 1421 return 5;
6ee73861
BS		 1422
1423 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1424 "Mask: 0x%02X, Data: 0x%02X\n",
1425 offset, mlv, tmdsaddr, mask, data);
1426
1427 reg = get_tmds_index_reg(bios->dev, mlv);
1428 if (!reg)
37383650 1429 return 0;
6ee73861
BS		 1430
1431 bios_wr32(bios, reg,
1432 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1433 value = (bios_rd32(bios, reg + 4) & mask) | data;
1434 bios_wr32(bios, reg + 4, value);
1435 bios_wr32(bios, reg, tmdsaddr);
1436
37383650 1437 return 5;
6ee73861
BS		 1438}
1439
37383650 1440static int
6ee73861
BS		 1441init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1442 struct init_exec *iexec)
1443{
1444 /*
1445 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1446 *
1447 * offset (8 bit): opcode
1448 * offset + 1 (8 bit): magic lookup value
1449 * offset + 2 (8 bit): count
1450 * offset + 3 (8 bit): addr 1
1451 * offset + 4 (8 bit): data 1
1452 * ...
1453 *
1454 * For each of "count" TMDS address and data pairs write "data n" to
1455 * "addr n". "magic lookup value" determines which TMDS base address
1456 * register is used -- see get_tmds_index_reg()
1457 */
1458
1459 uint8_t mlv = bios->data[offset + 1];
1460 uint8_t count = bios->data[offset + 2];
37383650 1461 int len = 3 + count * 2;
6ee73861
BS		 1462 uint32_t reg;
1463 int i;
1464
1465 if (!iexec->execute)
37383650 1466 return len;
6ee73861
BS		 1467
1468 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1469 offset, mlv, count);
1470
1471 reg = get_tmds_index_reg(bios->dev, mlv);
1472 if (!reg)
37383650 1473 return 0;
6ee73861
BS		 1474
1475 for (i = 0; i < count; i++) {
1476 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1477 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1478
1479 bios_wr32(bios, reg + 4, tmdsdata);
1480 bios_wr32(bios, reg, tmdsaddr);
1481 }
1482
37383650 1483 return len;
6ee73861
BS		 1484}
1485
37383650 1486static int
6ee73861
BS		 1487init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1488 struct init_exec *iexec)
1489{
1490 /*
1491 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1492 *
1493 * offset (8 bit): opcode
1494 * offset + 1 (8 bit): CRTC index1
1495 * offset + 2 (8 bit): CRTC index2
1496 * offset + 3 (8 bit): baseaddr
1497 * offset + 4 (8 bit): count
1498 * offset + 5 (8 bit): data 1
1499 * ...
1500 *
1501 * For each of "count" address and data pairs, write "baseaddr + n" to
1502 * "CRTC index1" and "data n" to "CRTC index2"
1503 * Once complete, restore initial value read from "CRTC index1"
1504 */
1505 uint8_t crtcindex1 = bios->data[offset + 1];
1506 uint8_t crtcindex2 = bios->data[offset + 2];
1507 uint8_t baseaddr = bios->data[offset + 3];
1508 uint8_t count = bios->data[offset + 4];
37383650 1509 int len = 5 + count;
6ee73861
BS		 1510 uint8_t oldaddr, data;
1511 int i;
1512
1513 if (!iexec->execute)
37383650 1514 return len;
6ee73861
BS		 1515
1516 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1517 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1518 offset, crtcindex1, crtcindex2, baseaddr, count);
1519
1520 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1521
1522 for (i = 0; i < count; i++) {
1523 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1524 baseaddr + i);
1525 data = bios->data[offset + 5 + i];
1526 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1527 }
1528
1529 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1530
37383650 1531 return len;
6ee73861
BS		 1532}
1533
37383650 1534static int
6ee73861
BS		 1535init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1536{
1537 /*
1538 * INIT_CR opcode: 0x52 ('R')
1539 *
1540 * offset (8 bit): opcode
1541 * offset + 1 (8 bit): CRTC index
1542 * offset + 2 (8 bit): mask
1543 * offset + 3 (8 bit): data
1544 *
1545 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1546 * data back to "CRTC index"
1547 */
1548
1549 uint8_t crtcindex = bios->data[offset + 1];
1550 uint8_t mask = bios->data[offset + 2];
1551 uint8_t data = bios->data[offset + 3];
1552 uint8_t value;
1553
1554 if (!iexec->execute)
37383650 1555 return 4;
6ee73861
BS		 1556
1557 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1558 offset, crtcindex, mask, data);
1559
1560 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1561 value |= data;
1562 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1563
37383650 1564 return 4;
6ee73861
BS		 1565}
1566
37383650 1567static int
6ee73861
BS		 1568init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1569{
1570 /*
1571 * INIT_ZM_CR opcode: 0x53 ('S')
1572 *
1573 * offset (8 bit): opcode
1574 * offset + 1 (8 bit): CRTC index
1575 * offset + 2 (8 bit): value
1576 *
1577 * Assign "value" to CRTC register with index "CRTC index".
1578 */
1579
1580 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1581 uint8_t data = bios->data[offset + 2];
1582
1583 if (!iexec->execute)
37383650 1584 return 3;
6ee73861
BS		 1585
1586 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1587
37383650 1588 return 3;
6ee73861
BS		 1589}
1590
37383650 1591static int
6ee73861
BS		 1592init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1593{
1594 /*
1595 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1596 *
1597 * offset (8 bit): opcode
1598 * offset + 1 (8 bit): count
1599 * offset + 2 (8 bit): CRTC index 1
1600 * offset + 3 (8 bit): value 1
1601 * ...
1602 *
1603 * For "count", assign "value n" to CRTC register with index
1604 * "CRTC index n".
1605 */
1606
1607 uint8_t count = bios->data[offset + 1];
37383650 1608 int len = 2 + count * 2;
6ee73861
BS		 1609 int i;
1610
1611 if (!iexec->execute)
37383650 1612 return len;
6ee73861
BS		 1613
1614 for (i = 0; i < count; i++)
1615 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1616
37383650 1617 return len;
6ee73861
BS		 1618}
1619
37383650 1620static int
6ee73861
BS		 1621init_condition_time(struct nvbios *bios, uint16_t offset,
1622 struct init_exec *iexec)
1623{
1624 /*
1625 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1626 *
1627 * offset (8 bit): opcode
1628 * offset + 1 (8 bit): condition number
1629 * offset + 2 (8 bit): retries / 50
1630 *
1631 * Check condition "condition number" in the condition table.
1632 * Bios code then sleeps for 2ms if the condition is not met, and
1633 * repeats up to "retries" times, but on one C51 this has proved
1634 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1635 * this, and bail after "retries" times, or 2s, whichever is less.
1636 * If still not met after retries, clear execution flag for this table.
1637 */
1638
1639 uint8_t cond = bios->data[offset + 1];
1640 uint16_t retries = bios->data[offset + 2] * 50;
1641 unsigned cnt;
1642
1643 if (!iexec->execute)
37383650 1644 return 3;
6ee73861
BS		 1645
1646 if (retries > 100)
1647 retries = 100;
1648
1649 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1650 offset, cond, retries);
1651
1652 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1653 retries = 1;
1654
1655 for (cnt = 0; cnt < retries; cnt++) {
1656 if (bios_condition_met(bios, offset, cond)) {
1657 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1658 offset);
1659 break;
1660 } else {
1661 BIOSLOG(bios, "0x%04X: "
1662 "Condition not met, sleeping for 20ms\n",
1663 offset);
1664 msleep(20);
1665 }
1666 }
1667
1668 if (!bios_condition_met(bios, offset, cond)) {
1669 NV_WARN(bios->dev,
1670 "0x%04X: Condition still not met after %dms, "
1671 "skipping following opcodes\n", offset, 20 * retries);
1672 iexec->execute = false;
1673 }
1674
37383650 1675 return 3;
6ee73861
BS		 1676}
1677
37383650 1678static int
6ee73861
BS		 1679init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1680 struct init_exec *iexec)
1681{
1682 /*
1683 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1684 *
1685 * offset (8 bit): opcode
1686 * offset + 1 (32 bit): base register
1687 * offset + 5 (8 bit): count
1688 * offset + 6 (32 bit): value 1
1689 * ...
1690 *
1691 * Starting at offset + 6 there are "count" 32 bit values.
1692 * For "count" iterations set "base register" + 4 * current_iteration
1693 * to "value current_iteration"
1694 */
1695
1696 uint32_t basereg = ROM32(bios->data[offset + 1]);
1697 uint32_t count = bios->data[offset + 5];
37383650 1698 int len = 6 + count * 4;
6ee73861
BS		 1699 int i;
1700
1701 if (!iexec->execute)
37383650 1702 return len;
6ee73861
BS		 1703
1704 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1705 offset, basereg, count);
1706
1707 for (i = 0; i < count; i++) {
1708 uint32_t reg = basereg + i * 4;
1709 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1710
1711 bios_wr32(bios, reg, data);
1712 }
1713
37383650 1714 return len;
6ee73861
BS		 1715}
1716
37383650 1717static int
6ee73861
BS		 1718init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1719{
1720 /*
1721 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1722 *
1723 * offset (8 bit): opcode
1724 * offset + 1 (16 bit): subroutine offset (in bios)
1725 *
1726 * Calls a subroutine that will execute commands until INIT_DONE
1727 * is found.
1728 */
1729
1730 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1731
1732 if (!iexec->execute)
37383650 1733 return 3;
6ee73861
BS		 1734
1735 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1736 offset, sub_offset);
1737
1738 parse_init_table(bios, sub_offset, iexec);
1739
1740 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1741
37383650 1742 return 3;
6ee73861
BS		 1743}
1744
37383650 1745static int
6ee73861
BS		 1746init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1747{
1748 /*
1749 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1750 *
1751 * offset (8 bit): opcode
1752 * offset + 1 (32 bit): src reg
1753 * offset + 5 (8 bit): shift
1754 * offset + 6 (32 bit): src mask
1755 * offset + 10 (32 bit): xor
1756 * offset + 14 (32 bit): dst reg
1757 * offset + 18 (32 bit): dst mask
1758 *
1759 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1760 * "src mask", then XOR with "xor". Write this OR'd with
1761 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1762 */
1763
1764 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1765 uint8_t shift = bios->data[offset + 5];
1766 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1767 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1768 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1769 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1770 uint32_t srcvalue, dstvalue;
1771
1772 if (!iexec->execute)
37383650 1773 return 22;
6ee73861
BS		 1774
1775 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1776 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1777 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1778
1779 srcvalue = bios_rd32(bios, srcreg);
1780
1781 if (shift < 0x80)
1782 srcvalue >>= shift;
1783 else
1784 srcvalue <<= (0x100 - shift);
1785
1786 srcvalue = (srcvalue & srcmask) ^ xor;
1787
1788 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1789
1790 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1791
37383650 1792 return 22;
6ee73861
BS		 1793}
1794
37383650 1795static int
6ee73861
BS		 1796init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1797{
1798 /*
1799 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1800 *
1801 * offset (8 bit): opcode
1802 * offset + 1 (16 bit): CRTC port
1803 * offset + 3 (8 bit): CRTC index
1804 * offset + 4 (8 bit): data
1805 *
1806 * Write "data" to index "CRTC index" of "CRTC port"
1807 */
1808 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1809 uint8_t crtcindex = bios->data[offset + 3];
1810 uint8_t data = bios->data[offset + 4];
1811
1812 if (!iexec->execute)
37383650 1813 return 5;
6ee73861
BS		 1814
1815 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1816
37383650 1817 return 5;
6ee73861
BS		 1818}
1819
37383650 1820static int
6ee73861
BS		 1821init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1822{
1823 /*
1824 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
1825 *
1826 * offset (8 bit): opcode
1827 *
1828 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1829 * that the hardware can correctly calculate how much VRAM it has
1830 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
1831 *
1832 * The implementation of this opcode in general consists of two parts:
1833 * 1) determination of the memory bus width
1834 * 2) determination of how many of the card's RAM pads have ICs attached
1835 *
1836 * 1) is done by a cunning combination of writes to offsets 0x1c and
1837 * 0x3c in the framebuffer, and seeing whether the written values are
1838 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1839 *
1840 * 2) is done by a cunning combination of writes to an offset slightly
1841 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
1842 * if the test pattern can be read back. This then affects bits 12-15 of
1843 * NV_PFB_CFG0
1844 *
1845 * In this context a "cunning combination" may include multiple reads
1846 * and writes to varying locations, often alternating the test pattern
1847 * and 0, doubtless to make sure buffers are filled, residual charges
1848 * on tracks are removed etc.
1849 *
1850 * Unfortunately, the "cunning combination"s mentioned above, and the
1851 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1852 * trace I have.
1853 *
1854 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1855 * we started was correct, and use that instead
1856 */
1857
1858 /* no iexec->execute check by design */
1859
1860 /*
1861 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
1862 * and kmmio traces of the binary driver POSTing the card show nothing
1863 * being done for this opcode. why is it still listed in the table?!
1864 */
1865
1866 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1867
e235c1f3 1868 if (dev_priv->card_type >= NV_40)
37383650 1869 return 1;
6ee73861
BS		 1870
1871 /*
1872 * On every card I've seen, this step gets done for us earlier in
1873 * the init scripts
1874 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
1875 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
1876 */
1877
1878 /*
1879 * This also has probably been done in the scripts, but an mmio trace of
1880 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
1881 */
1882 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1883
1884 /* write back the saved configuration value */
1885 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
1886
37383650 1887 return 1;
6ee73861
BS		 1888}
1889
37383650 1890static int
6ee73861
BS		 1891init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1892{
1893 /*
1894 * INIT_RESET opcode: 0x65 ('e')
1895 *
1896 * offset (8 bit): opcode
1897 * offset + 1 (32 bit): register
1898 * offset + 5 (32 bit): value1
1899 * offset + 9 (32 bit): value2
1900 *
1901 * Assign "value1" to "register", then assign "value2" to "register"
1902 */
1903
1904 uint32_t reg = ROM32(bios->data[offset + 1]);
1905 uint32_t value1 = ROM32(bios->data[offset + 5]);
1906 uint32_t value2 = ROM32(bios->data[offset + 9]);
1907 uint32_t pci_nv_19, pci_nv_20;
1908
1909 /* no iexec->execute check by design */
1910
1911 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
1912 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
1913 bios_wr32(bios, reg, value1);
1914
1915 udelay(10);
1916
1917 bios_wr32(bios, reg, value2);
1918 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
1919
1920 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
1921 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1922 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
1923
37383650 1924 return 13;
6ee73861
BS		 1925}
1926
37383650 1927static int
6ee73861
BS		 1928init_configure_mem(struct nvbios *bios, uint16_t offset,
1929 struct init_exec *iexec)
1930{
1931 /*
1932 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1933 *
1934 * offset (8 bit): opcode
1935 *
1936 * Equivalent to INIT_DONE on bios version 3 or greater.
1937 * For early bios versions, sets up the memory registers, using values
1938 * taken from the memory init table
1939 */
1940
1941 /* no iexec->execute check by design */
1942
1943 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
1944 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
1945 uint32_t reg, data;
1946
1947 if (bios->major_version > 2)
37383650 1948 return 0;
6ee73861
BS		 1949
1950 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
1951 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
1952
1953 if (bios->data[meminitoffs] & 1)
1954 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
1955
1956 for (reg = ROM32(bios->data[seqtbloffs]);
1957 reg != 0xffffffff;
1958 reg = ROM32(bios->data[seqtbloffs += 4])) {
1959
1960 switch (reg) {
1961 case NV_PFB_PRE:
1962 data = NV_PFB_PRE_CMD_PRECHARGE;
1963 break;
1964 case NV_PFB_PAD:
1965 data = NV_PFB_PAD_CKE_NORMAL;
1966 break;
1967 case NV_PFB_REF:
1968 data = NV_PFB_REF_CMD_REFRESH;
1969 break;
1970 default:
1971 data = ROM32(bios->data[meminitdata]);
1972 meminitdata += 4;
1973 if (data == 0xffffffff)
1974 continue;
1975 }
1976
1977 bios_wr32(bios, reg, data);
1978 }
1979
37383650 1980 return 1;
6ee73861
BS		 1981}
1982
37383650 1983static int
6ee73861
BS		 1984init_configure_clk(struct nvbios *bios, uint16_t offset,
1985 struct init_exec *iexec)
1986{
1987 /*
1988 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
1989 *
1990 * offset (8 bit): opcode
1991 *
1992 * Equivalent to INIT_DONE on bios version 3 or greater.
1993 * For early bios versions, sets up the NVClk and MClk PLLs, using
1994 * values taken from the memory init table
1995 */
1996
1997 /* no iexec->execute check by design */
1998
1999 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2000 int clock;
2001
2002 if (bios->major_version > 2)
37383650 2003 return 0;
6ee73861
BS		 2004
2005 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2006 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2007
2008 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2009 if (bios->data[meminitoffs] & 1) /* DDR */
2010 clock *= 2;
2011 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2012
37383650 2013 return 1;
6ee73861
BS		 2014}
2015
37383650 2016static int
6ee73861
BS		 2017init_configure_preinit(struct nvbios *bios, uint16_t offset,
2018 struct init_exec *iexec)
2019{
2020 /*
2021 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2022 *
2023 * offset (8 bit): opcode
2024 *
2025 * Equivalent to INIT_DONE on bios version 3 or greater.
2026 * For early bios versions, does early init, loading ram and crystal
2027 * configuration from straps into CR3C
2028 */
2029
2030 /* no iexec->execute check by design */
2031
2032 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2033 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2034
2035 if (bios->major_version > 2)
37383650 2036 return 0;
6ee73861
BS		 2037
2038 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2039 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2040
37383650 2041 return 1;
6ee73861
BS		 2042}
2043
37383650 2044static int
6ee73861
BS		 2045init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2046{
2047 /*
2048 * INIT_IO opcode: 0x69 ('i')
2049 *
2050 * offset (8 bit): opcode
2051 * offset + 1 (16 bit): CRTC port
2052 * offset + 3 (8 bit): mask
2053 * offset + 4 (8 bit): data
2054 *
2055 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2056 */
2057
2058 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2059 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2060 uint8_t mask = bios->data[offset + 3];
2061 uint8_t data = bios->data[offset + 4];
2062
2063 if (!iexec->execute)
37383650 2064 return 5;
6ee73861
BS		 2065
2066 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2067 offset, crtcport, mask, data);
2068
2069 /*
2070 * I have no idea what this does, but NVIDIA do this magic sequence
2071 * in the places where this INIT_IO happens..
2072 */
2073 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2074 int i;
2075
2076 bios_wr32(bios, 0x614100, (bios_rd32(
2077 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2078
2079 bios_wr32(bios, 0x00e18c, bios_rd32(
2080 bios, 0x00e18c) | 0x00020000);
2081
2082 bios_wr32(bios, 0x614900, (bios_rd32(
2083 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2084
2085 bios_wr32(bios, 0x000200, bios_rd32(
2086 bios, 0x000200) & ~0x40000000);
2087
2088 mdelay(10);
2089
2090 bios_wr32(bios, 0x00e18c, bios_rd32(
2091 bios, 0x00e18c) & ~0x00020000);
2092
2093 bios_wr32(bios, 0x000200, bios_rd32(
2094 bios, 0x000200) | 0x40000000);
2095
2096 bios_wr32(bios, 0x614100, 0x00800018);
2097 bios_wr32(bios, 0x614900, 0x00800018);
2098
2099 mdelay(10);
2100
2101 bios_wr32(bios, 0x614100, 0x10000018);
2102 bios_wr32(bios, 0x614900, 0x10000018);
2103
2104 for (i = 0; i < 3; i++)
2105 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2106 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2107
2108 for (i = 0; i < 2; i++)
2109 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2110 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2111
2112 for (i = 0; i < 3; i++)
2113 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2114 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2115
2116 for (i = 0; i < 2; i++)
2117 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2118 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2119
2120 for (i = 0; i < 2; i++)
2121 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2122 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2123 return 5;
6ee73861
BS		 2124 }
2125
2126 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2127 data);
37383650 2128 return 5;
6ee73861
BS		 2129}
2130
37383650 2131static int
6ee73861
BS		 2132init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2133{
2134 /*
2135 * INIT_SUB opcode: 0x6B ('k')
2136 *
2137 * offset (8 bit): opcode
2138 * offset + 1 (8 bit): script number
2139 *
2140 * Execute script number "script number", as a subroutine
2141 */
2142
2143 uint8_t sub = bios->data[offset + 1];
2144
2145 if (!iexec->execute)
37383650 2146 return 2;
6ee73861
BS		 2147
2148 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2149
2150 parse_init_table(bios,
2151 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2152 iexec);
2153
2154 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2155
37383650 2156 return 2;
6ee73861
BS		 2157}
2158
37383650 2159static int
6ee73861
BS		 2160init_ram_condition(struct nvbios *bios, uint16_t offset,
2161 struct init_exec *iexec)
2162{
2163 /*
2164 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2165 *
2166 * offset (8 bit): opcode
2167 * offset + 1 (8 bit): mask
2168 * offset + 2 (8 bit): cmpval
2169 *
2170 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2171 * If condition not met skip subsequent opcodes until condition is
2172 * inverted (INIT_NOT), or we hit INIT_RESUME
2173 */
2174
2175 uint8_t mask = bios->data[offset + 1];
2176 uint8_t cmpval = bios->data[offset + 2];
2177 uint8_t data;
2178
2179 if (!iexec->execute)
37383650 2180 return 3;
6ee73861
BS		 2181
2182 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2183
2184 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2185 offset, data, cmpval);
2186
2187 if (data == cmpval)
2188 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2189 else {
2190 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2191 iexec->execute = false;
2192 }
2193
37383650 2194 return 3;
6ee73861
BS		 2195}
2196
37383650 2197static int
6ee73861
BS		 2198init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2199{
2200 /*
2201 * INIT_NV_REG opcode: 0x6E ('n')
2202 *
2203 * offset (8 bit): opcode
2204 * offset + 1 (32 bit): register
2205 * offset + 5 (32 bit): mask
2206 * offset + 9 (32 bit): data
2207 *
2208 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2209 */
2210
2211 uint32_t reg = ROM32(bios->data[offset + 1]);
2212 uint32_t mask = ROM32(bios->data[offset + 5]);
2213 uint32_t data = ROM32(bios->data[offset + 9]);
2214
2215 if (!iexec->execute)
37383650 2216 return 13;
6ee73861
BS		 2217
2218 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2219 offset, reg, mask, data);
2220
2221 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2222
37383650 2223 return 13;
6ee73861
BS		 2224}
2225
37383650 2226static int
6ee73861
BS		 2227init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2228{
2229 /*
2230 * INIT_MACRO opcode: 0x6F ('o')
2231 *
2232 * offset (8 bit): opcode
2233 * offset + 1 (8 bit): macro number
2234 *
2235 * Look up macro index "macro number" in the macro index table.
2236 * The macro index table entry has 1 byte for the index in the macro
2237 * table, and 1 byte for the number of times to repeat the macro.
2238 * The macro table entry has 4 bytes for the register address and
2239 * 4 bytes for the value to write to that register
2240 */
2241
2242 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2243 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2244 uint8_t macro_tbl_idx = bios->data[tmp];
2245 uint8_t count = bios->data[tmp + 1];
2246 uint32_t reg, data;
2247 int i;
2248
2249 if (!iexec->execute)
37383650 2250 return 2;
6ee73861
BS		 2251
2252 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2253 "Count: 0x%02X\n",
2254 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2255
2256 for (i = 0; i < count; i++) {
2257 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2258
2259 reg = ROM32(bios->data[macroentryptr]);
2260 data = ROM32(bios->data[macroentryptr + 4]);
2261
2262 bios_wr32(bios, reg, data);
2263 }
2264
37383650 2265 return 2;
6ee73861
BS		 2266}
2267
37383650 2268static int
6ee73861
BS		 2269init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2270{
2271 /*
2272 * INIT_DONE opcode: 0x71 ('q')
2273 *
2274 * offset (8 bit): opcode
2275 *
2276 * End the current script
2277 */
2278
2279 /* mild retval abuse to stop parsing this table */
37383650 2280 return 0;
6ee73861
BS		 2281}
2282
37383650 2283static int
6ee73861
BS		 2284init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2285{
2286 /*
2287 * INIT_RESUME opcode: 0x72 ('r')
2288 *
2289 * offset (8 bit): opcode
2290 *
2291 * End the current execute / no-execute condition
2292 */
2293
2294 if (iexec->execute)
37383650 2295 return 1;
6ee73861
BS		 2296
2297 iexec->execute = true;
2298 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2299
37383650 2300 return 1;
6ee73861
BS		 2301}
2302
37383650 2303static int
6ee73861
BS		 2304init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2305{
2306 /*
2307 * INIT_TIME opcode: 0x74 ('t')
2308 *
2309 * offset (8 bit): opcode
2310 * offset + 1 (16 bit): time
2311 *
2312 * Sleep for "time" microseconds.
2313 */
2314
2315 unsigned time = ROM16(bios->data[offset + 1]);
2316
2317 if (!iexec->execute)
37383650 2318 return 3;
6ee73861
BS		 2319
2320 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2321 offset, time);
2322
2323 if (time < 1000)
2324 udelay(time);
2325 else
2326 msleep((time + 900) / 1000);
2327
37383650 2328 return 3;
6ee73861
BS		 2329}
2330
37383650 2331static int
6ee73861
BS		 2332init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2333{
2334 /*
2335 * INIT_CONDITION opcode: 0x75 ('u')
2336 *
2337 * offset (8 bit): opcode
2338 * offset + 1 (8 bit): condition number
2339 *
2340 * Check condition "condition number" in the condition table.
2341 * If condition not met skip subsequent opcodes until condition is
2342 * inverted (INIT_NOT), or we hit INIT_RESUME
2343 */
2344
2345 uint8_t cond = bios->data[offset + 1];
2346
2347 if (!iexec->execute)
37383650 2348 return 2;
6ee73861
BS		 2349
2350 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2351
2352 if (bios_condition_met(bios, offset, cond))
2353 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2354 else {
2355 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2356 iexec->execute = false;
2357 }
2358
37383650 2359 return 2;
6ee73861
BS		 2360}
2361
37383650 2362static int
6ee73861
BS		 2363init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2364{
2365 /*
2366 * INIT_IO_CONDITION opcode: 0x76
2367 *
2368 * offset (8 bit): opcode
2369 * offset + 1 (8 bit): condition number
2370 *
2371 * Check condition "condition number" in the io condition table.
2372 * If condition not met skip subsequent opcodes until condition is
2373 * inverted (INIT_NOT), or we hit INIT_RESUME
2374 */
2375
2376 uint8_t cond = bios->data[offset + 1];
2377
2378 if (!iexec->execute)
37383650 2379 return 2;
6ee73861
BS		 2380
2381 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2382
2383 if (io_condition_met(bios, offset, cond))
2384 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2385 else {
2386 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2387 iexec->execute = false;
2388 }
2389
37383650 2390 return 2;
6ee73861
BS		 2391}
2392
37383650 2393static int
6ee73861
BS		 2394init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2395{
2396 /*
2397 * INIT_INDEX_IO opcode: 0x78 ('x')
2398 *
2399 * offset (8 bit): opcode
2400 * offset + 1 (16 bit): CRTC port
2401 * offset + 3 (8 bit): CRTC index
2402 * offset + 4 (8 bit): mask
2403 * offset + 5 (8 bit): data
2404 *
2405 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2406 * OR with "data", write-back
2407 */
2408
2409 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2410 uint8_t crtcindex = bios->data[offset + 3];
2411 uint8_t mask = bios->data[offset + 4];
2412 uint8_t data = bios->data[offset + 5];
2413 uint8_t value;
2414
2415 if (!iexec->execute)
37383650 2416 return 6;
6ee73861
BS		 2417
2418 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2419 "Data: 0x%02X\n",
2420 offset, crtcport, crtcindex, mask, data);
2421
2422 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2423 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2424
37383650 2425 return 6;
6ee73861
BS		 2426}
2427
37383650 2428static int
6ee73861
BS		 2429init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2430{
2431 /*
2432 * INIT_PLL opcode: 0x79 ('y')
2433 *
2434 * offset (8 bit): opcode
2435 * offset + 1 (32 bit): register
2436 * offset + 5 (16 bit): freq
2437 *
2438 * Set PLL register "register" to coefficients for frequency (10kHz)
2439 * "freq"
2440 */
2441
2442 uint32_t reg = ROM32(bios->data[offset + 1]);
2443 uint16_t freq = ROM16(bios->data[offset + 5]);
2444
2445 if (!iexec->execute)
37383650 2446 return 7;
6ee73861
BS		 2447
2448 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2449
2450 setPLL(bios, reg, freq * 10);
2451
37383650 2452 return 7;
6ee73861
BS		 2453}
2454
37383650 2455static int
6ee73861
BS		 2456init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2457{
2458 /*
2459 * INIT_ZM_REG opcode: 0x7A ('z')
2460 *
2461 * offset (8 bit): opcode
2462 * offset + 1 (32 bit): register
2463 * offset + 5 (32 bit): value
2464 *
2465 * Assign "value" to "register"
2466 */
2467
2468 uint32_t reg = ROM32(bios->data[offset + 1]);
2469 uint32_t value = ROM32(bios->data[offset + 5]);
2470
2471 if (!iexec->execute)
37383650 2472 return 9;
6ee73861
BS		 2473
2474 if (reg == 0x000200)
2475 value |= 1;
2476
2477 bios_wr32(bios, reg, value);
2478
37383650 2479 return 9;
6ee73861
BS		 2480}
2481
37383650 2482static int
6ee73861
BS		 2483init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2484 struct init_exec *iexec)
2485{
2486 /*
2487 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2488 *
2489 * offset (8 bit): opcode
2490 * offset + 1 (8 bit): PLL type
2491 * offset + 2 (32 bit): frequency 0
2492 *
2493 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2494 * ram_restrict_table_ptr. The value read from there is used to select
2495 * a frequency from the table starting at 'frequency 0' to be
2496 * programmed into the PLL corresponding to 'type'.
2497 *
2498 * The PLL limits table on cards using this opcode has a mapping of
2499 * 'type' to the relevant registers.
2500 */
2501
2502 struct drm_device *dev = bios->dev;
2503 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2504 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2505 uint8_t type = bios->data[offset + 1];
2506 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2507 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 2508 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 2509 int i;
2510
2511 if (!iexec->execute)
37383650 2512 return len;
6ee73861
BS		 2513
2514 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2515 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 2516 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 2517 }
2518
2519 entry = pll_limits + pll_limits[1];
2520 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2521 if (entry[0] == type) {
2522 uint32_t reg = ROM32(entry[3]);
2523
2524 BIOSLOG(bios, "0x%04X: "
2525 "Type %02x Reg 0x%08x Freq %dKHz\n",
2526 offset, type, reg, freq);
2527
2528 setPLL(bios, reg, freq);
37383650 2529 return len;
6ee73861
BS		 2530 }
2531 }
2532
2533 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 2534 return len;
6ee73861
BS		 2535}
2536
37383650 2537static int
6ee73861
BS		 2538init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2539{
2540 /*
2541 * INIT_8C opcode: 0x8C ('')
2542 *
2543 * NOP so far....
2544 *
2545 */
2546
37383650 2547 return 1;
6ee73861
BS		 2548}
2549
37383650 2550static int
6ee73861
BS		 2551init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2552{
2553 /*
2554 * INIT_8D opcode: 0x8D ('')
2555 *
2556 * NOP so far....
2557 *
2558 */
2559
37383650 2560 return 1;
6ee73861
BS		 2561}
2562
37383650 2563static int
6ee73861
BS		 2564init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2565{
2566 /*
2567 * INIT_GPIO opcode: 0x8E ('')
2568 *
2569 * offset (8 bit): opcode
2570 *
2571 * Loop over all entries in the DCB GPIO table, and initialise
2572 * each GPIO according to various values listed in each entry
2573 */
2574
2575 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
2576 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
2577 const uint8_t *gpio_table = &bios->data[bios->bdcb.gpio_table_ptr];
2578 const uint8_t *gpio_entry;
2579 int i;
2580
37383650
MK		 2581 if (!iexec->execute)
2582 return 1;
2583
6ee73861
BS		 2584 if (bios->bdcb.version != 0x40) {
2585 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
37383650 2586 return 0;
6ee73861
BS		 2587 }
2588
2589 if (!bios->bdcb.gpio_table_ptr) {
2590 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n");
37383650 2591 return 0;
6ee73861
BS		 2592 }
2593
2594 gpio_entry = gpio_table + gpio_table[1];
2595 for (i = 0; i < gpio_table[2]; i++, gpio_entry += gpio_table[3]) {
2596 uint32_t entry = ROM32(gpio_entry[0]), r, s, v;
2597 int line = (entry & 0x0000001f);
2598
2599 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, entry);
2600
2601 if ((entry & 0x0000ff00) == 0x0000ff00)
2602 continue;
2603
2604 r = nv50_gpio_reg[line >> 3];
2605 s = (line & 0x07) << 2;
2606 v = bios_rd32(bios, r) & ~(0x00000003 << s);
2607 if (entry & 0x01000000)
2608 v |= (((entry & 0x60000000) >> 29) ^ 2) << s;
2609 else
2610 v |= (((entry & 0x18000000) >> 27) ^ 2) << s;
2611 bios_wr32(bios, r, v);
2612
2613 r = nv50_gpio_ctl[line >> 4];
2614 s = (line & 0x0f);
2615 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2616 switch ((entry & 0x06000000) >> 25) {
2617 case 1:
2618 v |= (0x00000001 << s);
2619 break;
2620 case 2:
2621 v |= (0x00010000 << s);
2622 break;
2623 default:
2624 break;
2625 }
2626 bios_wr32(bios, r, v);
2627 }
2628
37383650 2629 return 1;
6ee73861
BS		 2630}
2631
37383650 2632static int
6ee73861
BS		 2633init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2634 struct init_exec *iexec)
2635{
2636 /*
2637 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2638 *
2639 * offset (8 bit): opcode
2640 * offset + 1 (32 bit): reg
2641 * offset + 5 (8 bit): regincrement
2642 * offset + 6 (8 bit): count
2643 * offset + 7 (32 bit): value 1,1
2644 * ...
2645 *
2646 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2647 * ram_restrict_table_ptr. The value read from here is 'n', and
2648 * "value 1,n" gets written to "reg". This repeats "count" times and on
2649 * each iteration 'm', "reg" increases by "regincrement" and
2650 * "value m,n" is used. The extent of n is limited by a number read
2651 * from the 'M' BIT table, herein called "blocklen"
2652 */
2653
2654 uint32_t reg = ROM32(bios->data[offset + 1]);
2655 uint8_t regincrement = bios->data[offset + 5];
2656 uint8_t count = bios->data[offset + 6];
2657 uint32_t strap_ramcfg, data;
37383650
MK		 2658 /* previously set by 'M' BIT table */
2659 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2660 int len = 7 + count * blocklen;
6ee73861
BS		 2661 uint8_t index;
2662 int i;
2663
6ee73861
BS		 2664
2665 if (!iexec->execute)
37383650 2666 return len;
6ee73861
BS		 2667
2668 if (!blocklen) {
2669 NV_ERROR(bios->dev,
2670 "0x%04X: Zero block length - has the M table "
2671 "been parsed?\n", offset);
37383650 2672 return 0;
6ee73861
BS		 2673 }
2674
2675 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2676 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2677
2678 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2679 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2680 offset, reg, regincrement, count, strap_ramcfg, index);
2681
2682 for (i = 0; i < count; i++) {
2683 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2684
2685 bios_wr32(bios, reg, data);
2686
2687 reg += regincrement;
2688 }
2689
37383650 2690 return len;
6ee73861
BS		 2691}
2692
37383650 2693static int
6ee73861
BS		 2694init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2695{
2696 /*
2697 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2698 *
2699 * offset (8 bit): opcode
2700 * offset + 1 (32 bit): src reg
2701 * offset + 5 (32 bit): dst reg
2702 *
2703 * Put contents of "src reg" into "dst reg"
2704 */
2705
2706 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2707 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2708
2709 if (!iexec->execute)
37383650 2710 return 9;
6ee73861
BS		 2711
2712 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2713
37383650 2714 return 9;
6ee73861
BS		 2715}
2716
37383650 2717static int
6ee73861
BS		 2718init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2719 struct init_exec *iexec)
2720{
2721 /*
2722 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2723 *
2724 * offset (8 bit): opcode
2725 * offset + 1 (32 bit): dst reg
2726 * offset + 5 (8 bit): count
2727 * offset + 6 (32 bit): data 1
2728 * ...
2729 *
2730 * For each of "count" values write "data n" to "dst reg"
2731 */
2732
2733 uint32_t reg = ROM32(bios->data[offset + 1]);
2734 uint8_t count = bios->data[offset + 5];
37383650 2735 int len = 6 + count * 4;
6ee73861
BS		 2736 int i;
2737
2738 if (!iexec->execute)
37383650 2739 return len;
6ee73861
BS		 2740
2741 for (i = 0; i < count; i++) {
2742 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2743 bios_wr32(bios, reg, data);
2744 }
2745
37383650 2746 return len;
6ee73861
BS		 2747}
2748
37383650 2749static int
6ee73861
BS		 2750init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2751{
2752 /*
2753 * INIT_RESERVED opcode: 0x92 ('')
2754 *
2755 * offset (8 bit): opcode
2756 *
2757 * Seemingly does nothing
2758 */
2759
37383650 2760 return 1;
6ee73861
BS		 2761}
2762
37383650 2763static int
6ee73861
BS		 2764init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2765{
2766 /*
2767 * INIT_96 opcode: 0x96 ('')
2768 *
2769 * offset (8 bit): opcode
2770 * offset + 1 (32 bit): sreg
2771 * offset + 5 (8 bit): sshift
2772 * offset + 6 (8 bit): smask
2773 * offset + 7 (8 bit): index
2774 * offset + 8 (32 bit): reg
2775 * offset + 12 (32 bit): mask
2776 * offset + 16 (8 bit): shift
2777 *
2778 */
2779
2780 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2781 uint32_t reg = ROM32(bios->data[offset + 8]);
2782 uint32_t mask = ROM32(bios->data[offset + 12]);
2783 uint32_t val;
2784
2785 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2786 if (bios->data[offset + 5] < 0x80)
2787 val >>= bios->data[offset + 5];
2788 else
2789 val <<= (0x100 - bios->data[offset + 5]);
2790 val &= bios->data[offset + 6];
2791
2792 val = bios->data[ROM16(bios->data[xlatptr]) + val];
2793 val <<= bios->data[offset + 16];
2794
2795 if (!iexec->execute)
37383650 2796 return 17;
6ee73861
BS		 2797
2798 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 2799 return 17;
6ee73861
BS		 2800}
2801
37383650 2802static int
6ee73861
BS		 2803init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2804{
2805 /*
2806 * INIT_97 opcode: 0x97 ('')
2807 *
2808 * offset (8 bit): opcode
2809 * offset + 1 (32 bit): register
2810 * offset + 5 (32 bit): mask
2811 * offset + 9 (32 bit): value
2812 *
2813 * Adds "value" to "register" preserving the fields specified
2814 * by "mask"
2815 */
2816
2817 uint32_t reg = ROM32(bios->data[offset + 1]);
2818 uint32_t mask = ROM32(bios->data[offset + 5]);
2819 uint32_t add = ROM32(bios->data[offset + 9]);
2820 uint32_t val;
2821
2822 val = bios_rd32(bios, reg);
2823 val = (val & mask) | ((val + add) & ~mask);
2824
2825 if (!iexec->execute)
37383650 2826 return 13;
6ee73861
BS		 2827
2828 bios_wr32(bios, reg, val);
37383650 2829 return 13;
6ee73861
BS		 2830}
2831
37383650 2832static int
6ee73861
BS		 2833init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2834{
2835 /*
2836 * INIT_AUXCH opcode: 0x98 ('')
2837 *
2838 * offset (8 bit): opcode
2839 * offset + 1 (32 bit): address
2840 * offset + 5 (8 bit): count
2841 * offset + 6 (8 bit): mask 0
2842 * offset + 7 (8 bit): data 0
2843 * ...
2844 *
2845 */
2846
2847 struct drm_device *dev = bios->dev;
2848 struct nouveau_i2c_chan *auxch;
2849 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 2850 uint8_t count = bios->data[offset + 5];
2851 int len = 6 + count * 2;
6ee73861
BS		 2852 int ret, i;
2853
2854 if (!bios->display.output) {
2855 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
37383650 2856 return 0;
6ee73861
BS		 2857 }
2858
2859 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2860 if (!auxch) {
2861 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
2862 bios->display.output->i2c_index);
37383650 2863 return 0;
6ee73861
BS		 2864 }
2865
2866 if (!iexec->execute)
37383650 2867 return len;
6ee73861
BS		 2868
2869 offset += 6;
37383650 2870 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 2871 uint8_t data;
2872
2873 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
2874 if (ret) {
2875 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
37383650 2876 return 0;
6ee73861
BS		 2877 }
2878
2879 data &= bios->data[offset + 0];
2880 data |= bios->data[offset + 1];
2881
2882 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
2883 if (ret) {
2884 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
37383650 2885 return 0;
6ee73861
BS		 2886 }
2887 }
2888
37383650 2889 return len;
6ee73861
BS		 2890}
2891
37383650 2892static int
6ee73861
BS		 2893init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2894{
2895 /*
2896 * INIT_ZM_AUXCH opcode: 0x99 ('')
2897 *
2898 * offset (8 bit): opcode
2899 * offset + 1 (32 bit): address
2900 * offset + 5 (8 bit): count
2901 * offset + 6 (8 bit): data 0
2902 * ...
2903 *
2904 */
2905
2906 struct drm_device *dev = bios->dev;
2907 struct nouveau_i2c_chan *auxch;
2908 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 2909 uint8_t count = bios->data[offset + 5];
2910 int len = 6 + count;
6ee73861
BS		 2911 int ret, i;
2912
2913 if (!bios->display.output) {
2914 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
37383650 2915 return 0;
6ee73861
BS		 2916 }
2917
2918 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2919 if (!auxch) {
2920 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
2921 bios->display.output->i2c_index);
37383650 2922 return 0;
6ee73861
BS		 2923 }
2924
2925 if (!iexec->execute)
37383650 2926 return len;
6ee73861
BS		 2927
2928 offset += 6;
37383650 2929 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 2930 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
2931 if (ret) {
2932 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
37383650 2933 return 0;
6ee73861
BS		 2934 }
2935 }
2936
37383650 2937 return len;
6ee73861
BS		 2938}
2939
2940static struct init_tbl_entry itbl_entry[] = {
2941 /* command name , id , length , offset , mult , command handler */
2942 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 2943 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
2944 { "INIT_REPEAT" , 0x33, init_repeat },
2945 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
2946 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
2947 { "INIT_COPY" , 0x37, init_copy },
2948 { "INIT_NOT" , 0x38, init_not },
2949 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
2950 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
2951 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
2952 { "INIT_PLL2" , 0x4B, init_pll2 },
2953 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
2954 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
2955 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
2956 { "INIT_TMDS" , 0x4F, init_tmds },
2957 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
2958 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
2959 { "INIT_CR" , 0x52, init_cr },
2960 { "INIT_ZM_CR" , 0x53, init_zm_cr },
2961 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
2962 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
2963 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 2964 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 2965 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
2966 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
2967 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
2968 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
2969 { "INIT_RESET" , 0x65, init_reset },
2970 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
2971 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
2972 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
2973 { "INIT_IO" , 0x69, init_io },
2974 { "INIT_SUB" , 0x6B, init_sub },
2975 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
2976 { "INIT_NV_REG" , 0x6E, init_nv_reg },
2977 { "INIT_MACRO" , 0x6F, init_macro },
2978 { "INIT_DONE" , 0x71, init_done },
2979 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 2980 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 2981 { "INIT_TIME" , 0x74, init_time },
2982 { "INIT_CONDITION" , 0x75, init_condition },
2983 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
2984 { "INIT_INDEX_IO" , 0x78, init_index_io },
2985 { "INIT_PLL" , 0x79, init_pll },
2986 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
2987 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
2988 { "INIT_8C" , 0x8C, init_8c },
2989 { "INIT_8D" , 0x8D, init_8d },
2990 { "INIT_GPIO" , 0x8E, init_gpio },
2991 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
2992 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
2993 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
2994 { "INIT_RESERVED" , 0x92, init_reserved },
2995 { "INIT_96" , 0x96, init_96 },
2996 { "INIT_97" , 0x97, init_97 },
2997 { "INIT_AUXCH" , 0x98, init_auxch },
2998 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
2999 { NULL , 0 , NULL }
6ee73861
BS		 3000};
3001
6ee73861
BS		 3002#define MAX_TABLE_OPS 1000
3003
3004static int
3005parse_init_table(struct nvbios *bios, unsigned int offset,
3006 struct init_exec *iexec)
3007{
3008 /*
3009 * Parses all commands in an init table.
3010 *
3011 * We start out executing all commands found in the init table. Some
3012 * opcodes may change the status of iexec->execute to SKIP, which will
3013 * cause the following opcodes to perform no operation until the value
3014 * is changed back to EXECUTE.
3015 */
3016
37383650 3017 int count = 0, i, res;
6ee73861
BS		 3018 uint8_t id;
3019
3020 /*
3021 * Loop until INIT_DONE causes us to break out of the loop
3022 * (or until offset > bios length just in case... )
3023 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3024 */
3025 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3026 id = bios->data[offset];
3027
3028 /* Find matching id in itbl_entry */
3029 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3030 ;
3031
3032 if (itbl_entry[i].name) {
3033 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n",
3034 offset, itbl_entry[i].id, itbl_entry[i].name);
3035
3036 /* execute eventual command handler */
37383650
MK		 3037 res = (*itbl_entry[i].handler)(bios, offset, iexec);
3038 if (!res)
3039 break;
3040 /*
3041 * Add the offset of the current command including all data
3042 * of that command. The offset will then be pointing on the
3043 * next op code.
3044 */
3045 offset += res;
6ee73861
BS		 3046 } else {
3047 NV_ERROR(bios->dev,
3048 "0x%04X: Init table command not found: "
3049 "0x%02X\n", offset, id);
3050 return -ENOENT;
3051 }
6ee73861
BS		 3052 }
3053
3054 if (offset >= bios->length)
3055 NV_WARN(bios->dev,
3056 "Offset 0x%04X greater than known bios image length. "
3057 "Corrupt image?\n", offset);
3058 if (count >= MAX_TABLE_OPS)
3059 NV_WARN(bios->dev,
3060 "More than %d opcodes to a table is unlikely, "
3061 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3062
3063 return 0;
3064}
3065
3066static void
3067parse_init_tables(struct nvbios *bios)
3068{
3069 /* Loops and calls parse_init_table() for each present table. */
3070
3071 int i = 0;
3072 uint16_t table;
3073 struct init_exec iexec = {true, false};
3074
3075 if (bios->old_style_init) {
3076 if (bios->init_script_tbls_ptr)
3077 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3078 if (bios->extra_init_script_tbl_ptr)
3079 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3080
3081 return;
3082 }
3083
3084 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3085 NV_INFO(bios->dev,
3086 "Parsing VBIOS init table %d at offset 0x%04X\n",
3087 i / 2, table);
3088 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3089
3090 parse_init_table(bios, table, &iexec);
3091 i += 2;
3092 }
3093}
3094
3095static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3096{
3097 int compare_record_len, i = 0;
3098 uint16_t compareclk, scriptptr = 0;
3099
3100 if (bios->major_version < 5) /* pre BIT */
3101 compare_record_len = 3;
3102 else
3103 compare_record_len = 4;
3104
3105 do {
3106 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3107 if (pxclk >= compareclk * 10) {
3108 if (bios->major_version < 5) {
3109 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3110 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3111 } else
3112 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3113 break;
3114 }
3115 i++;
3116 } while (compareclk);
3117
3118 return scriptptr;
3119}
3120
3121static void
3122run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3123 struct dcb_entry *dcbent, int head, bool dl)
3124{
3125 struct drm_nouveau_private *dev_priv = dev->dev_private;
3126 struct nvbios *bios = &dev_priv->VBIOS;
3127 struct init_exec iexec = {true, false};
3128
3129 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3130 scriptptr);
3131 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3132 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3133 /* note: if dcb entries have been merged, index may be misleading */
3134 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3135 parse_init_table(bios, scriptptr, &iexec);
3136
3137 nv04_dfp_bind_head(dev, dcbent, head, dl);
3138}
3139
3140static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3141{
3142 struct drm_nouveau_private *dev_priv = dev->dev_private;
3143 struct nvbios *bios = &dev_priv->VBIOS;
3144 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3145 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3146
3147 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3148 return -EINVAL;
3149
3150 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3151
3152 if (script == LVDS_PANEL_OFF) {
3153 /* off-on delay in ms */
3154 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3155 }
3156#ifdef __powerpc__
3157 /* Powerbook specific quirks */
3d9aefb8
FJ		 3158 if ((dev->pci_device & 0xffff) == 0x0179 ||
3159 (dev->pci_device & 0xffff) == 0x0189 ||
3160 (dev->pci_device & 0xffff) == 0x0329) {
3161 if (script == LVDS_RESET) {
3162 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3163
3164 } else if (script == LVDS_PANEL_ON) {
3165 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3166 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3167 | (1 << 31));
3168 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3169 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3170
3171 } else if (script == LVDS_PANEL_OFF) {
3172 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3173 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3174 & ~(1 << 31));
3175 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3176 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3177 }
3178 }
3179#endif
3180
3181 return 0;
3182}
3183
3184static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3185{
3186 /*
3187 * The BIT LVDS table's header has the information to setup the
3188 * necessary registers. Following the standard 4 byte header are:
3189 * A bitmask byte and a dual-link transition pxclk value for use in
3190 * selecting the init script when not using straps; 4 script pointers
3191 * for panel power, selected by output and on/off; and 8 table pointers
3192 * for panel init, the needed one determined by output, and bits in the
3193 * conf byte. These tables are similar to the TMDS tables, consisting
3194 * of a list of pxclks and script pointers.
3195 */
3196 struct drm_nouveau_private *dev_priv = dev->dev_private;
3197 struct nvbios *bios = &dev_priv->VBIOS;
3198 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3199 uint16_t scriptptr = 0, clktable;
3200 uint8_t clktableptr = 0;
3201
3202 /*
3203 * For now we assume version 3.0 table - g80 support will need some
3204 * changes
3205 */
3206
3207 switch (script) {
3208 case LVDS_INIT:
3209 return -ENOSYS;
3210 case LVDS_BACKLIGHT_ON:
3211 case LVDS_PANEL_ON:
3212 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3213 break;
3214 case LVDS_BACKLIGHT_OFF:
3215 case LVDS_PANEL_OFF:
3216 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3217 break;
3218 case LVDS_RESET:
3219 if (dcbent->lvdsconf.use_straps_for_mode) {
3220 if (bios->fp.dual_link)
3221 clktableptr += 2;
3222 if (bios->fp.BITbit1)
3223 clktableptr++;
3224 } else {
3225 /* using EDID */
3226 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3227 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
3228
3229 if (bios->fp.dual_link) {
3230 clktableptr += 2;
3231 fallbackcmpval *= 2;
3232 }
3233 if (fallbackcmpval & fallback)
3234 clktableptr++;
3235 }
3236
3237 /* adding outputset * 8 may not be correct */
3238 clktable = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
3239 if (!clktable) {
3240 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3241 return -ENOENT;
3242 }
3243 scriptptr = clkcmptable(bios, clktable, pxclk);
3244 }
3245
3246 if (!scriptptr) {
3247 NV_ERROR(dev, "LVDS output init script not found\n");
3248 return -ENOENT;
3249 }
3250 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3251
3252 return 0;
3253}
3254
3255int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3256{
3257 /*
3258 * LVDS operations are multiplexed in an effort to present a single API
3259 * which works with two vastly differing underlying structures.
3260 * This acts as the demux
3261 */
3262
3263 struct drm_nouveau_private *dev_priv = dev->dev_private;
3264 struct nvbios *bios = &dev_priv->VBIOS;
3265 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3266 uint32_t sel_clk_binding, sel_clk;
3267 int ret;
3268
3269 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3270 (lvds_ver >= 0x30 && script == LVDS_INIT))
3271 return 0;
3272
3273 if (!bios->fp.lvds_init_run) {
3274 bios->fp.lvds_init_run = true;
3275 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3276 }
3277
3278 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3279 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3280 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3281 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3282
3283 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3284
3285 /* don't let script change pll->head binding */
3286 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3287
3288 if (lvds_ver < 0x30)
3289 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3290 else
3291 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3292
3293 bios->fp.last_script_invoc = (script << 1 | head);
3294
3295 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3296 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3297 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3298 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3299
3300 return ret;
3301}
3302
3303struct lvdstableheader {
3304 uint8_t lvds_ver, headerlen, recordlen;
3305};
3306
3307static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3308{
3309 /*
3310 * BMP version (0xa) LVDS table has a simple header of version and
3311 * record length. The BIT LVDS table has the typical BIT table header:
3312 * version byte, header length byte, record length byte, and a byte for
3313 * the maximum number of records that can be held in the table.
3314 */
3315
3316 uint8_t lvds_ver, headerlen, recordlen;
3317
3318 memset(lth, 0, sizeof(struct lvdstableheader));
3319
3320 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3321 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3322 return -EINVAL;
3323 }
3324
3325 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3326
3327 switch (lvds_ver) {
3328 case 0x0a: /* pre NV40 */
3329 headerlen = 2;
3330 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3331 break;
3332 case 0x30: /* NV4x */
3333 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3334 if (headerlen < 0x1f) {
3335 NV_ERROR(dev, "LVDS table header not understood\n");
3336 return -EINVAL;
3337 }
3338 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3339 break;
3340 case 0x40: /* G80/G90 */
3341 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3342 if (headerlen < 0x7) {
3343 NV_ERROR(dev, "LVDS table header not understood\n");
3344 return -EINVAL;
3345 }
3346 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3347 break;
3348 default:
3349 NV_ERROR(dev,
3350 "LVDS table revision %d.%d not currently supported\n",
3351 lvds_ver >> 4, lvds_ver & 0xf);
3352 return -ENOSYS;
3353 }
3354
3355 lth->lvds_ver = lvds_ver;
3356 lth->headerlen = headerlen;
3357 lth->recordlen = recordlen;
3358
3359 return 0;
3360}
3361
3362static int
3363get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3364{
3365 struct drm_nouveau_private *dev_priv = dev->dev_private;
3366
3367 /*
3368 * The fp strap is normally dictated by the "User Strap" in
3369 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3370 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3371 * by the PCI subsystem ID during POST, but not before the previous user
3372 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3373 * read and used instead
3374 */
3375
3376 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3377 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3378
3379 if (dev_priv->card_type >= NV_50)
3380 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3381 else
3382 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3383}
3384
3385static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3386{
3387 uint8_t *fptable;
3388 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3389 int ret, ofs, fpstrapping;
3390 struct lvdstableheader lth;
3391
3392 if (bios->fp.fptablepointer == 0x0) {
3393 /* Apple cards don't have the fp table; the laptops use DDC */
3394 /* The table is also missing on some x86 IGPs */
3395#ifndef __powerpc__
3396 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3397#endif
3398 bios->pub.digital_min_front_porch = 0x4b;
3399 return 0;
3400 }
3401
3402 fptable = &bios->data[bios->fp.fptablepointer];
3403 fptable_ver = fptable[0];
3404
3405 switch (fptable_ver) {
3406 /*
3407 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3408 * version field, and miss one of the spread spectrum/PWM bytes.
3409 * This could affect early GF2Go parts (not seen any appropriate ROMs
3410 * though). Here we assume that a version of 0x05 matches this case
3411 * (combining with a BMP version check would be better), as the
3412 * common case for the panel type field is 0x0005, and that is in
3413 * fact what we are reading the first byte of.
3414 */
3415 case 0x05: /* some NV10, 11, 15, 16 */
3416 recordlen = 42;
3417 ofs = -1;
3418 break;
3419 case 0x10: /* some NV15/16, and NV11+ */
3420 recordlen = 44;
3421 ofs = 0;
3422 break;
3423 case 0x20: /* NV40+ */
3424 headerlen = fptable[1];
3425 recordlen = fptable[2];
3426 fpentries = fptable[3];
3427 /*
3428 * fptable[4] is the minimum
3429 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3430 */
3431 bios->pub.digital_min_front_porch = fptable[4];
3432 ofs = -7;
3433 break;
3434 default:
3435 NV_ERROR(dev,
3436 "FP table revision %d.%d not currently supported\n",
3437 fptable_ver >> 4, fptable_ver & 0xf);
3438 return -ENOSYS;
3439 }
3440
3441 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3442 return 0;
3443
3444 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3445 if (ret)
3446 return ret;
3447
3448 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3449 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3450 lth.headerlen + 1;
3451 bios->fp.xlatwidth = lth.recordlen;
3452 }
3453 if (bios->fp.fpxlatetableptr == 0x0) {
3454 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3455 return -EINVAL;
3456 }
3457
3458 fpstrapping = get_fp_strap(dev, bios);
3459
3460 fpindex = bios->data[bios->fp.fpxlatetableptr +
3461 fpstrapping * bios->fp.xlatwidth];
3462
3463 if (fpindex > fpentries) {
3464 NV_ERROR(dev, "Bad flat panel table index\n");
3465 return -ENOENT;
3466 }
3467
3468 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3469 if (lth.lvds_ver > 0x10)
3470 bios->pub.fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
3471
3472 /*
3473 * If either the strap or xlated fpindex value are 0xf there is no
3474 * panel using a strap-derived bios mode present. this condition
3475 * includes, but is different from, the DDC panel indicator above
3476 */
3477 if (fpstrapping == 0xf || fpindex == 0xf)
3478 return 0;
3479
3480 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3481 recordlen * fpindex + ofs;
3482
3483 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3484 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3485 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3486 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3487
3488 return 0;
3489}
3490
3491bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3492{
3493 struct drm_nouveau_private *dev_priv = dev->dev_private;
3494 struct nvbios *bios = &dev_priv->VBIOS;
3495 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3496
3497 if (!mode) /* just checking whether we can produce a mode */
3498 return bios->fp.mode_ptr;
3499
3500 memset(mode, 0, sizeof(struct drm_display_mode));
3501 /*
3502 * For version 1.0 (version in byte 0):
3503 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3504 * single/dual link, and type (TFT etc.)
3505 * bytes 3-6 are bits per colour in RGBX
3506 */
3507 mode->clock = ROM16(mode_entry[7]) * 10;
3508 /* bytes 9-10 is HActive */
3509 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3510 /*
3511 * bytes 13-14 is HValid Start
3512 * bytes 15-16 is HValid End
3513 */
3514 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3515 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3516 mode->htotal = ROM16(mode_entry[21]) + 1;
3517 /* bytes 23-24, 27-30 similarly, but vertical */
3518 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3519 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3520 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3521 mode->vtotal = ROM16(mode_entry[35]) + 1;
3522 mode->flags |= (mode_entry[37] & 0x10) ?
3523 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3524 mode->flags |= (mode_entry[37] & 0x1) ?
3525 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3526 /*
3527 * bytes 38-39 relate to spread spectrum settings
3528 * bytes 40-43 are something to do with PWM
3529 */
3530
3531 mode->status = MODE_OK;
3532 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3533 drm_mode_set_name(mode);
3534 return bios->fp.mode_ptr;
3535}
3536
3537int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3538{
3539 /*
3540 * The LVDS table header is (mostly) described in
3541 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3542 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3543 * straps are not being used for the panel, this specifies the frequency
3544 * at which modes should be set up in the dual link style.
3545 *
3546 * Following the header, the BMP (ver 0xa) table has several records,
3547 * indexed by a seperate xlat table, indexed in turn by the fp strap in
3548 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3549 * numbers for use by INIT_SUB which controlled panel init and power,
3550 * and finally a dword of ms to sleep between power off and on
3551 * operations.
3552 *
3553 * In the BIT versions, the table following the header serves as an
3554 * integrated config and xlat table: the records in the table are
3555 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3556 * two bytes - the first as a config byte, the second for indexing the
3557 * fp mode table pointed to by the BIT 'D' table
3558 *
3559 * DDC is not used until after card init, so selecting the correct table
3560 * entry and setting the dual link flag for EDID equipped panels,
3561 * requiring tests against the native-mode pixel clock, cannot be done
3562 * until later, when this function should be called with non-zero pxclk
3563 */
3564 struct drm_nouveau_private *dev_priv = dev->dev_private;
3565 struct nvbios *bios = &dev_priv->VBIOS;
3566 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3567 struct lvdstableheader lth;
3568 uint16_t lvdsofs;
3569 int ret, chip_version = bios->pub.chip_version;
3570
3571 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3572 if (ret)
3573 return ret;
3574
3575 switch (lth.lvds_ver) {
3576 case 0x0a: /* pre NV40 */
3577 lvdsmanufacturerindex = bios->data[
3578 bios->fp.fpxlatemanufacturertableptr +
3579 fpstrapping];
3580
3581 /* we're done if this isn't the EDID panel case */
3582 if (!pxclk)
3583 break;
3584
3585 if (chip_version < 0x25) {
3586 /* nv17 behaviour
3587 *
3588 * It seems the old style lvds script pointer is reused
3589 * to select 18/24 bit colour depth for EDID panels.
3590 */
3591 lvdsmanufacturerindex =
3592 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3593 2 : 0;
3594 if (pxclk >= bios->fp.duallink_transition_clk)
3595 lvdsmanufacturerindex++;
3596 } else if (chip_version < 0x30) {
3597 /* nv28 behaviour (off-chip encoder)
3598 *
3599 * nv28 does a complex dance of first using byte 121 of
3600 * the EDID to choose the lvdsmanufacturerindex, then
3601 * later attempting to match the EDID manufacturer and
3602 * product IDs in a table (signature 'pidt' (panel id
3603 * table?)), setting an lvdsmanufacturerindex of 0 and
3604 * an fp strap of the match index (or 0xf if none)
3605 */
3606 lvdsmanufacturerindex = 0;
3607 } else {
3608 /* nv31, nv34 behaviour */
3609 lvdsmanufacturerindex = 0;
3610 if (pxclk >= bios->fp.duallink_transition_clk)
3611 lvdsmanufacturerindex = 2;
3612 if (pxclk >= 140000)
3613 lvdsmanufacturerindex = 3;
3614 }
3615
3616 /*
3617 * nvidia set the high nibble of (cr57=f, cr58) to
3618 * lvdsmanufacturerindex in this case; we don't
3619 */
3620 break;
3621 case 0x30: /* NV4x */
3622 case 0x40: /* G80/G90 */
3623 lvdsmanufacturerindex = fpstrapping;
3624 break;
3625 default:
3626 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3627 return -ENOSYS;
3628 }
3629
3630 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3631 switch (lth.lvds_ver) {
3632 case 0x0a:
3633 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3634 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3635 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3636 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3637 *if_is_24bit = bios->data[lvdsofs] & 16;
3638 break;
3639 case 0x30:
3640 /*
3641 * My money would be on there being a 24 bit interface bit in
3642 * this table, but I have no example of a laptop bios with a
3643 * 24 bit panel to confirm that. Hence we shout loudly if any
3644 * bit other than bit 0 is set (I've not even seen bit 1)
3645 */
3646 if (bios->data[lvdsofs] > 1)
3647 NV_ERROR(dev,
3648 "You have a very unusual laptop display; please report it\n");
3649 /*
3650 * No sign of the "power off for reset" or "reset for panel
3651 * on" bits, but it's safer to assume we should
3652 */
3653 bios->fp.power_off_for_reset = true;
3654 bios->fp.reset_after_pclk_change = true;
3655 /*
3656 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
3657 * over-written, and BITbit1 isn't used
3658 */
3659 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3660 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3661 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3662 break;
3663 case 0x40:
3664 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3665 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3666 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3667 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3668 break;
3669 }
3670
3671 /* set dual_link flag for EDID case */
3672 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3673 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3674
3675 *dl = bios->fp.dual_link;
3676
3677 return 0;
3678}
3679
3680static uint8_t *
3681bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3682 uint16_t record, int record_len, int record_nr)
3683{
3684 struct drm_nouveau_private *dev_priv = dev->dev_private;
3685 struct nvbios *bios = &dev_priv->VBIOS;
3686 uint32_t entry;
3687 uint16_t table;
3688 int i, v;
3689
3690 for (i = 0; i < record_nr; i++, record += record_len) {
3691 table = ROM16(bios->data[record]);
3692 if (!table)
3693 continue;
3694 entry = ROM32(bios->data[table]);
3695
3696 v = (entry & 0x000f0000) >> 16;
3697 if (!(v & dcbent->or))
3698 continue;
3699
3700 v = (entry & 0x000000f0) >> 4;
3701 if (v != dcbent->location)
3702 continue;
3703
3704 v = (entry & 0x0000000f);
3705 if (v != dcbent->type)
3706 continue;
3707
3708 return &bios->data[table];
3709 }
3710
3711 return NULL;
3712}
3713
3714void *
3715nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3716 int *length)
3717{
3718 struct drm_nouveau_private *dev_priv = dev->dev_private;
3719 struct nvbios *bios = &dev_priv->VBIOS;
3720 uint8_t *table;
3721
3722 if (!bios->display.dp_table_ptr) {
3723 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3724 return NULL;
3725 }
3726 table = &bios->data[bios->display.dp_table_ptr];
3727
3728 if (table[0] != 0x21) {
3729 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3730 table[0]);
3731 return NULL;
3732 }
3733
3734 *length = table[4];
3735 return bios_output_config_match(dev, dcbent,
3736 bios->display.dp_table_ptr + table[1],
3737 table[2], table[3]);
3738}
3739
3740int
3741nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3742 uint32_t sub, int pxclk)
3743{
3744 /*
3745 * The display script table is located by the BIT 'U' table.
3746 *
3747 * It contains an array of pointers to various tables describing
3748 * a particular output type. The first 32-bits of the output
3749 * tables contains similar information to a DCB entry, and is
3750 * used to decide whether that particular table is suitable for
3751 * the output you want to access.
3752 *
3753 * The "record header length" field here seems to indicate the
3754 * offset of the first configuration entry in the output tables.
3755 * This is 10 on most cards I've seen, but 12 has been witnessed
3756 * on DP cards, and there's another script pointer within the
3757 * header.
3758 *
3759 * offset + 0 ( 8 bits): version
3760 * offset + 1 ( 8 bits): header length
3761 * offset + 2 ( 8 bits): record length
3762 * offset + 3 ( 8 bits): number of records
3763 * offset + 4 ( 8 bits): record header length
3764 * offset + 5 (16 bits): pointer to first output script table
3765 */
3766
3767 struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861
BS		 3768 struct nvbios *bios = &dev_priv->VBIOS;
3769 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3770 uint8_t *otable = NULL;
3771 uint16_t script;
3772 int i = 0;
3773
3774 if (!bios->display.script_table_ptr) {
3775 NV_ERROR(dev, "No pointer to output script table\n");
3776 return 1;
3777 }
3778
3779 /*
3780 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3781 * so until they are, we really don't need to care.
3782 */
3783 if (table[0] < 0x20)
3784 return 1;
3785
3786 if (table[0] != 0x20 && table[0] != 0x21) {
3787 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
3788 table[0]);
3789 return 1;
3790 }
3791
3792 /*
3793 * The output script tables describing a particular output type
3794 * look as follows:
3795 *
3796 * offset + 0 (32 bits): output this table matches (hash of DCB)
3797 * offset + 4 ( 8 bits): unknown
3798 * offset + 5 ( 8 bits): number of configurations
3799 * offset + 6 (16 bits): pointer to some script
3800 * offset + 8 (16 bits): pointer to some script
3801 *
3802 * headerlen == 10
3803 * offset + 10 : configuration 0
3804 *
3805 * headerlen == 12
3806 * offset + 10 : pointer to some script
3807 * offset + 12 : configuration 0
3808 *
3809 * Each config entry is as follows:
3810 *
3811 * offset + 0 (16 bits): unknown, assumed to be a match value
3812 * offset + 2 (16 bits): pointer to script table (clock set?)
3813 * offset + 4 (16 bits): pointer to script table (reset?)
3814 *
3815 * There doesn't appear to be a count value to say how many
3816 * entries exist in each script table, instead, a 0 value in
3817 * the first 16-bit word seems to indicate both the end of the
3818 * list and the default entry. The second 16-bit word in the
3819 * script tables is a pointer to the script to execute.
3820 */
3821
ef2bb506 3822 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 3823 dcbent->type, dcbent->location, dcbent->or);
3824 otable = bios_output_config_match(dev, dcbent, table[1] +
3825 bios->display.script_table_ptr,
3826 table[2], table[3]);
3827 if (!otable) {
3828 NV_ERROR(dev, "Couldn't find matching output script table\n");
3829 return 1;
3830 }
3831
3832 if (pxclk < -2 || pxclk > 0) {
3833 /* Try to find matching script table entry */
3834 for (i = 0; i < otable[5]; i++) {
3835 if (ROM16(otable[table[4] + i*6]) == sub)
3836 break;
3837 }
3838
3839 if (i == otable[5]) {
3840 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
3841 "using first\n",
3842 sub, dcbent->type, dcbent->or);
3843 i = 0;
3844 }
3845 }
3846
6ee73861
BS		 3847 if (pxclk == 0) {
3848 script = ROM16(otable[6]);
3849 if (!script) {
ef2bb506 3850 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 3851 return 1;
3852 }
3853
3854 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 3855 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3856 } else
3857 if (pxclk == -1) {
3858 script = ROM16(otable[8]);
3859 if (!script) {
ef2bb506 3860 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 3861 return 1;
3862 }
3863
3864 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 3865 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3866 } else
3867 if (pxclk == -2) {
3868 if (table[4] >= 12)
3869 script = ROM16(otable[10]);
3870 else
3871 script = 0;
3872 if (!script) {
ef2bb506 3873 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 3874 return 1;
3875 }
3876
3877 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 3878 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3879 } else
3880 if (pxclk > 0) {
3881 script = ROM16(otable[table[4] + i*6 + 2]);
3882 if (script)
3883 script = clkcmptable(bios, script, pxclk);
3884 if (!script) {
3885 NV_ERROR(dev, "clock script 0 not found\n");
3886 return 1;
3887 }
3888
3889 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 3890 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3891 } else
3892 if (pxclk < 0) {
3893 script = ROM16(otable[table[4] + i*6 + 4]);
3894 if (script)
3895 script = clkcmptable(bios, script, -pxclk);
3896 if (!script) {
ef2bb506 3897 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 3898 return 1;
3899 }
3900
3901 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 3902 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3903 }
3904
3905 return 0;
3906}
3907
3908
3909int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
3910{
3911 /*
3912 * the pxclk parameter is in kHz
3913 *
3914 * This runs the TMDS regs setting code found on BIT bios cards
3915 *
3916 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3917 * ffs(or) == 3, use the second.
3918 */
3919
3920 struct drm_nouveau_private *dev_priv = dev->dev_private;
3921 struct nvbios *bios = &dev_priv->VBIOS;
3922 int cv = bios->pub.chip_version;
3923 uint16_t clktable = 0, scriptptr;
3924 uint32_t sel_clk_binding, sel_clk;
3925
3926 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
3927 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
3928 dcbent->location != DCB_LOC_ON_CHIP)
3929 return 0;
3930
3931 switch (ffs(dcbent->or)) {
3932 case 1:
3933 clktable = bios->tmds.output0_script_ptr;
3934 break;
3935 case 2:
3936 case 3:
3937 clktable = bios->tmds.output1_script_ptr;
3938 break;
3939 }
3940
3941 if (!clktable) {
3942 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3943 return -EINVAL;
3944 }
3945
3946 scriptptr = clkcmptable(bios, clktable, pxclk);
3947
3948 if (!scriptptr) {
3949 NV_ERROR(dev, "TMDS output init script not found\n");
3950 return -ENOENT;
3951 }
3952
3953 /* don't let script change pll->head binding */
3954 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3955 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
3956 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3957 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3958
3959 return 0;
3960}
3961
3962int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
3963{
3964 /*
3965 * PLL limits table
3966 *
3967 * Version 0x10: NV30, NV31
3968 * One byte header (version), one record of 24 bytes
3969 * Version 0x11: NV36 - Not implemented
3970 * Seems to have same record style as 0x10, but 3 records rather than 1
3971 * Version 0x20: Found on Geforce 6 cards
3972 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3973 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3974 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
3975 * length in general, some (integrated) have an extra configuration byte
3976 * Version 0x30: Found on Geforce 8, separates the register mapping
3977 * from the limits tables.
3978 */
3979
3980 struct drm_nouveau_private *dev_priv = dev->dev_private;
3981 struct nvbios *bios = &dev_priv->VBIOS;
3982 int cv = bios->pub.chip_version, pllindex = 0;
3983 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
3984 uint32_t crystal_strap_mask, crystal_straps;
3985
3986 if (!bios->pll_limit_tbl_ptr) {
3987 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
3988 cv >= 0x40) {
3989 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
3990 return -EINVAL;
3991 }
3992 } else
3993 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3994
3995 crystal_strap_mask = 1 << 6;
3996 /* open coded dev->twoHeads test */
3997 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
3998 crystal_strap_mask |= 1 << 22;
3999 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4000 crystal_strap_mask;
4001
4002 switch (pll_lim_ver) {
4003 /*
4004 * We use version 0 to indicate a pre limit table bios (single stage
4005 * pll) and load the hard coded limits instead.
4006 */
4007 case 0:
4008 break;
4009 case 0x10:
4010 case 0x11:
4011 /*
4012 * Strictly v0x11 has 3 entries, but the last two don't seem
4013 * to get used.
4014 */
4015 headerlen = 1;
4016 recordlen = 0x18;
4017 entries = 1;
4018 pllindex = 0;
4019 break;
4020 case 0x20:
4021 case 0x21:
4022 case 0x30:
4023 case 0x40:
4024 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4025 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4026 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4027 break;
4028 default:
4029 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4030 "supported\n", pll_lim_ver);
4031 return -ENOSYS;
4032 }
4033
4034 /* initialize all members to zero */
4035 memset(pll_lim, 0, sizeof(struct pll_lims));
4036
4037 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4038 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4039
4040 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4041 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4042 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4043 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4044 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4045 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4046 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4047
4048 /* these values taken from nv30/31/36 */
4049 pll_lim->vco1.min_n = 0x1;
4050 if (cv == 0x36)
4051 pll_lim->vco1.min_n = 0x5;
4052 pll_lim->vco1.max_n = 0xff;
4053 pll_lim->vco1.min_m = 0x1;
4054 pll_lim->vco1.max_m = 0xd;
4055 pll_lim->vco2.min_n = 0x4;
4056 /*
4057 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4058 * table version (apart from nv35)), N2 is compared to
4059 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4060 * save a comparison
4061 */
4062 pll_lim->vco2.max_n = 0x28;
4063 if (cv == 0x30 || cv == 0x35)
4064 /* only 5 bits available for N2 on nv30/35 */
4065 pll_lim->vco2.max_n = 0x1f;
4066 pll_lim->vco2.min_m = 0x1;
4067 pll_lim->vco2.max_m = 0x4;
4068 pll_lim->max_log2p = 0x7;
4069 pll_lim->max_usable_log2p = 0x6;
4070 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4071 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4072 uint32_t reg = 0; /* default match */
4073 uint8_t *pll_rec;
4074 int i;
4075
4076 /*
4077 * First entry is default match, if nothing better. warn if
4078 * reg field nonzero
4079 */
4080 if (ROM32(bios->data[plloffs]))
4081 NV_WARN(dev, "Default PLL limit entry has non-zero "
4082 "register field\n");
4083
4084 if (limit_match > MAX_PLL_TYPES)
4085 /* we've been passed a reg as the match */
4086 reg = limit_match;
4087 else /* limit match is a pll type */
4088 for (i = 1; i < entries && !reg; i++) {
4089 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4090
4091 if (limit_match == NVPLL &&
4092 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4093 reg = cmpreg;
4094 if (limit_match == MPLL &&
4095 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4096 reg = cmpreg;
4097 if (limit_match == VPLL1 &&
4098 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4099 reg = cmpreg;
4100 if (limit_match == VPLL2 &&
4101 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4102 reg = cmpreg;
4103 }
4104
4105 for (i = 1; i < entries; i++)
4106 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4107 pllindex = i;
4108 break;
4109 }
4110
4111 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4112
4113 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4114 pllindex ? reg : 0);
4115
4116 /*
4117 * Frequencies are stored in tables in MHz, kHz are more
4118 * useful, so we convert.
4119 */
4120
4121 /* What output frequencies can each VCO generate? */
4122 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4123 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4124 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4125 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4126
4127 /* What input frequencies they accept (past the m-divider)? */
4128 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4129 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4130 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4131 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4132
4133 /* What values are accepted as multiplier and divider? */
4134 pll_lim->vco1.min_n = pll_rec[20];
4135 pll_lim->vco1.max_n = pll_rec[21];
4136 pll_lim->vco1.min_m = pll_rec[22];
4137 pll_lim->vco1.max_m = pll_rec[23];
4138 pll_lim->vco2.min_n = pll_rec[24];
4139 pll_lim->vco2.max_n = pll_rec[25];
4140 pll_lim->vco2.min_m = pll_rec[26];
4141 pll_lim->vco2.max_m = pll_rec[27];
4142
4143 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4144 if (pll_lim->max_log2p > 0x7)
4145 /* pll decoding in nv_hw.c assumes never > 7 */
4146 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4147 pll_lim->max_log2p);
4148 if (cv < 0x60)
4149 pll_lim->max_usable_log2p = 0x6;
4150 pll_lim->log2p_bias = pll_rec[30];
4151
4152 if (recordlen > 0x22)
4153 pll_lim->refclk = ROM32(pll_rec[31]);
4154
4155 if (recordlen > 0x23 && pll_rec[35])
4156 NV_WARN(dev,
4157 "Bits set in PLL configuration byte (%x)\n",
4158 pll_rec[35]);
4159
4160 /* C51 special not seen elsewhere */
4161 if (cv == 0x51 && !pll_lim->refclk) {
4162 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4163
4164 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4165 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4166 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4167 pll_lim->refclk = 200000;
4168 else
4169 pll_lim->refclk = 25000;
4170 }
4171 }
4172 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4173 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4174 uint8_t *record = NULL;
4175 int i;
4176
4177 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4178 limit_match);
4179
4180 for (i = 0; i < entries; i++, entry += recordlen) {
4181 if (ROM32(entry[3]) == limit_match) {
4182 record = &bios->data[ROM16(entry[1])];
4183 break;
4184 }
4185 }
4186
4187 if (!record) {
4188 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4189 "limits table", limit_match);
4190 return -ENOENT;
4191 }
4192
4193 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4194 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4195 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4196 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4197 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4198 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4199 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4200 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4201 pll_lim->vco1.min_n = record[16];
4202 pll_lim->vco1.max_n = record[17];
4203 pll_lim->vco1.min_m = record[18];
4204 pll_lim->vco1.max_m = record[19];
4205 pll_lim->vco2.min_n = record[20];
4206 pll_lim->vco2.max_n = record[21];
4207 pll_lim->vco2.min_m = record[22];
4208 pll_lim->vco2.max_m = record[23];
4209 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4210 pll_lim->log2p_bias = record[27];
4211 pll_lim->refclk = ROM32(record[28]);
4212 } else if (pll_lim_ver) { /* ver 0x40 */
4213 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4214 uint8_t *record = NULL;
4215 int i;
4216
4217 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4218 limit_match);
4219
4220 for (i = 0; i < entries; i++, entry += recordlen) {
4221 if (ROM32(entry[3]) == limit_match) {
4222 record = &bios->data[ROM16(entry[1])];
4223 break;
4224 }
4225 }
4226
4227 if (!record) {
4228 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4229 "limits table", limit_match);
4230 return -ENOENT;
4231 }
4232
4233 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4234 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4235 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4236 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4237 pll_lim->vco1.min_m = record[8];
4238 pll_lim->vco1.max_m = record[9];
4239 pll_lim->vco1.min_n = record[10];
4240 pll_lim->vco1.max_n = record[11];
4241 pll_lim->min_p = record[12];
4242 pll_lim->max_p = record[13];
4243 /* where did this go to?? */
4244 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4245 pll_lim->refclk = 27000;
4246 else
4247 pll_lim->refclk = 100000;
4248 }
4249
4250 /*
4251 * By now any valid limit table ought to have set a max frequency for
4252 * vco1, so if it's zero it's either a pre limit table bios, or one
4253 * with an empty limit table (seen on nv18)
4254 */
4255 if (!pll_lim->vco1.maxfreq) {
4256 pll_lim->vco1.minfreq = bios->fminvco;
4257 pll_lim->vco1.maxfreq = bios->fmaxvco;
4258 pll_lim->vco1.min_inputfreq = 0;
4259 pll_lim->vco1.max_inputfreq = INT_MAX;
4260 pll_lim->vco1.min_n = 0x1;
4261 pll_lim->vco1.max_n = 0xff;
4262 pll_lim->vco1.min_m = 0x1;
4263 if (crystal_straps == 0) {
4264 /* nv05 does this, nv11 doesn't, nv10 unknown */
4265 if (cv < 0x11)
4266 pll_lim->vco1.min_m = 0x7;
4267 pll_lim->vco1.max_m = 0xd;
4268 } else {
4269 if (cv < 0x11)
4270 pll_lim->vco1.min_m = 0x8;
4271 pll_lim->vco1.max_m = 0xe;
4272 }
4273 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4274 pll_lim->max_log2p = 4;
4275 else
4276 pll_lim->max_log2p = 5;
4277 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4278 }
4279
4280 if (!pll_lim->refclk)
4281 switch (crystal_straps) {
4282 case 0:
4283 pll_lim->refclk = 13500;
4284 break;
4285 case (1 << 6):
4286 pll_lim->refclk = 14318;
4287 break;
4288 case (1 << 22):
4289 pll_lim->refclk = 27000;
4290 break;
4291 case (1 << 22 | 1 << 6):
4292 pll_lim->refclk = 25000;
4293 break;
4294 }
4295
4296#if 0 /* for easy debugging */
4297 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4298 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4299 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4300 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4301
4302 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4303 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4304 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4305 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4306
4307 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4308 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4309 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4310 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4311 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4312 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4313 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4314 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4315
4316 ErrorF("pll.max_log2p: %d\n", pll_lim->max_log2p);
4317 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4318
4319 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
4320#endif
4321
4322 return 0;
4323}
4324
4325static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4326{
4327 /*
4328 * offset + 0 (8 bits): Micro version
4329 * offset + 1 (8 bits): Minor version
4330 * offset + 2 (8 bits): Chip version
4331 * offset + 3 (8 bits): Major version
4332 */
4333
4334 bios->major_version = bios->data[offset + 3];
4335 bios->pub.chip_version = bios->data[offset + 2];
4336 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4337 bios->data[offset + 3], bios->data[offset + 2],
4338 bios->data[offset + 1], bios->data[offset]);
4339}
4340
4341static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4342{
4343 /*
4344 * Parses the init table segment for pointers used in script execution.
4345 *
4346 * offset + 0 (16 bits): init script tables pointer
4347 * offset + 2 (16 bits): macro index table pointer
4348 * offset + 4 (16 bits): macro table pointer
4349 * offset + 6 (16 bits): condition table pointer
4350 * offset + 8 (16 bits): io condition table pointer
4351 * offset + 10 (16 bits): io flag condition table pointer
4352 * offset + 12 (16 bits): init function table pointer
4353 */
4354
4355 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4356 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4357 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4358 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4359 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4360 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4361 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4362}
4363
4364static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4365{
4366 /*
4367 * Parses the load detect values for g80 cards.
4368 *
4369 * offset + 0 (16 bits): loadval table pointer
4370 */
4371
4372 uint16_t load_table_ptr;
4373 uint8_t version, headerlen, entrylen, num_entries;
4374
4375 if (bitentry->length != 3) {
4376 NV_ERROR(dev, "Do not understand BIT A table\n");
4377 return -EINVAL;
4378 }
4379
4380 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4381
4382 if (load_table_ptr == 0x0) {
4383 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4384 return -EINVAL;
4385 }
4386
4387 version = bios->data[load_table_ptr];
4388
4389 if (version != 0x10) {
4390 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4391 version >> 4, version & 0xF);
4392 return -ENOSYS;
4393 }
4394
4395 headerlen = bios->data[load_table_ptr + 1];
4396 entrylen = bios->data[load_table_ptr + 2];
4397 num_entries = bios->data[load_table_ptr + 3];
4398
4399 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4400 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4401 return -EINVAL;
4402 }
4403
4404 /* First entry is normal dac, 2nd tv-out perhaps? */
4405 bios->pub.dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
4406
4407 return 0;
4408}
4409
4410static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4411{
4412 /*
4413 * offset + 8 (16 bits): PLL limits table pointer
4414 *
4415 * There's more in here, but that's unknown.
4416 */
4417
4418 if (bitentry->length < 10) {
4419 NV_ERROR(dev, "Do not understand BIT C table\n");
4420 return -EINVAL;
4421 }
4422
4423 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4424
4425 return 0;
4426}
4427
4428static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4429{
4430 /*
4431 * Parses the flat panel table segment that the bit entry points to.
4432 * Starting at bitentry->offset:
4433 *
4434 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4435 * records beginning with a freq.
4436 * offset + 2 (16 bits): mode table pointer
4437 */
4438
4439 if (bitentry->length != 4) {
4440 NV_ERROR(dev, "Do not understand BIT display table\n");
4441 return -EINVAL;
4442 }
4443
4444 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4445
4446 return 0;
4447}
4448
4449static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4450{
4451 /*
4452 * Parses the init table segment that the bit entry points to.
4453 *
4454 * See parse_script_table_pointers for layout
4455 */
4456
4457 if (bitentry->length < 14) {
4458 NV_ERROR(dev, "Do not understand init table\n");
4459 return -EINVAL;
4460 }
4461
4462 parse_script_table_pointers(bios, bitentry->offset);
4463
4464 if (bitentry->length >= 16)
4465 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4466 if (bitentry->length >= 18)
4467 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4468
4469 return 0;
4470}
4471
4472static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4473{
4474 /*
4475 * BIT 'i' (info?) table
4476 *
4477 * offset + 0 (32 bits): BIOS version dword (as in B table)
4478 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4479 * offset + 13 (16 bits): pointer to table containing DAC load
4480 * detection comparison values
4481 *
4482 * There's other things in the table, purpose unknown
4483 */
4484
4485 uint16_t daccmpoffset;
4486 uint8_t dacver, dacheaderlen;
4487
4488 if (bitentry->length < 6) {
4489 NV_ERROR(dev, "BIT i table too short for needed information\n");
4490 return -EINVAL;
4491 }
4492
4493 parse_bios_version(dev, bios, bitentry->offset);
4494
4495 /*
4496 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4497 * Quadro identity crisis), other bits possibly as for BMP feature byte
4498 */
4499 bios->feature_byte = bios->data[bitentry->offset + 5];
4500 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4501
4502 if (bitentry->length < 15) {
4503 NV_WARN(dev, "BIT i table not long enough for DAC load "
4504 "detection comparison table\n");
4505 return -EINVAL;
4506 }
4507
4508 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4509
4510 /* doesn't exist on g80 */
4511 if (!daccmpoffset)
4512 return 0;
4513
4514 /*
4515 * The first value in the table, following the header, is the
4516 * comparison value, the second entry is a comparison value for
4517 * TV load detection.
4518 */
4519
4520 dacver = bios->data[daccmpoffset];
4521 dacheaderlen = bios->data[daccmpoffset + 1];
4522
4523 if (dacver != 0x00 && dacver != 0x10) {
4524 NV_WARN(dev, "DAC load detection comparison table version "
4525 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4526 return -ENOSYS;
4527 }
4528
4529 bios->pub.dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4530 bios->pub.tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
4531
4532 return 0;
4533}
4534
4535static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4536{
4537 /*
4538 * Parses the LVDS table segment that the bit entry points to.
4539 * Starting at bitentry->offset:
4540 *
4541 * offset + 0 (16 bits): LVDS strap xlate table pointer
4542 */
4543
4544 if (bitentry->length != 2) {
4545 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4546 return -EINVAL;
4547 }
4548
4549 /*
4550 * No idea if it's still called the LVDS manufacturer table, but
4551 * the concept's close enough.
4552 */
4553 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4554
4555 return 0;
4556}
4557
4558static int
4559parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4560 struct bit_entry *bitentry)
4561{
4562 /*
4563 * offset + 2 (8 bits): number of options in an
4564 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4565 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4566 * restrict option selection
4567 *
4568 * There's a bunch of bits in this table other than the RAM restrict
4569 * stuff that we don't use - their use currently unknown
4570 */
4571
6ee73861
BS		 4572 /*
4573 * Older bios versions don't have a sufficiently long table for
4574 * what we want
4575 */
4576 if (bitentry->length < 0x5)
4577 return 0;
4578
4579 if (bitentry->id[1] < 2) {
37383650
MK		 4580 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4581 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 4582 } else {
37383650
MK		 4583 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4584 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 4585 }
4586
6ee73861
BS		 4587 return 0;
4588}
4589
4590static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4591{
4592 /*
4593 * Parses the pointer to the TMDS table
4594 *
4595 * Starting at bitentry->offset:
4596 *
4597 * offset + 0 (16 bits): TMDS table pointer
4598 *
4599 * The TMDS table is typically found just before the DCB table, with a
4600 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4601 * length?)
4602 *
4603 * At offset +7 is a pointer to a script, which I don't know how to
4604 * run yet.
4605 * At offset +9 is a pointer to another script, likewise
4606 * Offset +11 has a pointer to a table where the first word is a pxclk
4607 * frequency and the second word a pointer to a script, which should be
4608 * run if the comparison pxclk frequency is less than the pxclk desired.
4609 * This repeats for decreasing comparison frequencies
4610 * Offset +13 has a pointer to a similar table
4611 * The selection of table (and possibly +7/+9 script) is dictated by
4612 * "or" from the DCB.
4613 */
4614
4615 uint16_t tmdstableptr, script1, script2;
4616
4617 if (bitentry->length != 2) {
4618 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4619 return -EINVAL;
4620 }
4621
4622 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4623
4624 if (tmdstableptr == 0x0) {
4625 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4626 return -EINVAL;
4627 }
4628
4629 /* nv50+ has v2.0, but we don't parse it atm */
4630 if (bios->data[tmdstableptr] != 0x11) {
4631 NV_WARN(dev,
4632 "TMDS table revision %d.%d not currently supported\n",
4633 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4634 return -ENOSYS;
4635 }
4636
4637 /*
4638 * These two scripts are odd: they don't seem to get run even when
4639 * they are not stubbed.
4640 */
4641 script1 = ROM16(bios->data[tmdstableptr + 7]);
4642 script2 = ROM16(bios->data[tmdstableptr + 9]);
4643 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4644 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4645
4646 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4647 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4648
4649 return 0;
4650}
4651
4652static int
4653parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4654 struct bit_entry *bitentry)
4655{
4656 /*
4657 * Parses the pointer to the G80 output script tables
4658 *
4659 * Starting at bitentry->offset:
4660 *
4661 * offset + 0 (16 bits): output script table pointer
4662 */
4663
4664 uint16_t outputscripttableptr;
4665
4666 if (bitentry->length != 3) {
4667 NV_ERROR(dev, "Do not understand BIT U table\n");
4668 return -EINVAL;
4669 }
4670
4671 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4672 bios->display.script_table_ptr = outputscripttableptr;
4673 return 0;
4674}
4675
4676static int
4677parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4678 struct bit_entry *bitentry)
4679{
4680 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4681 return 0;
4682}
4683
4684struct bit_table {
4685 const char id;
4686 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4687};
4688
4689#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4690
4691static int
4692parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4693 struct bit_table *table)
4694{
4695 struct drm_device *dev = bios->dev;
4696 uint8_t maxentries = bios->data[bitoffset + 4];
4697 int i, offset;
4698 struct bit_entry bitentry;
4699
4700 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4701 bitentry.id[0] = bios->data[offset];
4702
4703 if (bitentry.id[0] != table->id)
4704 continue;
4705
4706 bitentry.id[1] = bios->data[offset + 1];
4707 bitentry.length = ROM16(bios->data[offset + 2]);
4708 bitentry.offset = ROM16(bios->data[offset + 4]);
4709
4710 return table->parse_fn(dev, bios, &bitentry);
4711 }
4712
4713 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4714 return -ENOSYS;
4715}
4716
4717static int
4718parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4719{
4720 int ret;
4721
4722 /*
4723 * The only restriction on parsing order currently is having 'i' first
4724 * for use of bios->*_version or bios->feature_byte while parsing;
4725 * functions shouldn't be actually *doing* anything apart from pulling
4726 * data from the image into the bios struct, thus no interdependencies
4727 */
4728 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4729 if (ret) /* info? */
4730 return ret;
4731 if (bios->major_version >= 0x60) /* g80+ */
4732 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4733 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4734 if (ret)
4735 return ret;
4736 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4737 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4738 if (ret)
4739 return ret;
4740 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4741 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4742 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4743 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4744 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4745
4746 return 0;
4747}
4748
4749static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4750{
4751 /*
4752 * Parses the BMP structure for useful things, but does not act on them
4753 *
4754 * offset + 5: BMP major version
4755 * offset + 6: BMP minor version
4756 * offset + 9: BMP feature byte
4757 * offset + 10: BCD encoded BIOS version
4758 *
4759 * offset + 18: init script table pointer (for bios versions < 5.10h)
4760 * offset + 20: extra init script table pointer (for bios
4761 * versions < 5.10h)
4762 *
4763 * offset + 24: memory init table pointer (used on early bios versions)
4764 * offset + 26: SDR memory sequencing setup data table
4765 * offset + 28: DDR memory sequencing setup data table
4766 *
4767 * offset + 54: index of I2C CRTC pair to use for CRT output
4768 * offset + 55: index of I2C CRTC pair to use for TV output
4769 * offset + 56: index of I2C CRTC pair to use for flat panel output
4770 * offset + 58: write CRTC index for I2C pair 0
4771 * offset + 59: read CRTC index for I2C pair 0
4772 * offset + 60: write CRTC index for I2C pair 1
4773 * offset + 61: read CRTC index for I2C pair 1
4774 *
4775 * offset + 67: maximum internal PLL frequency (single stage PLL)
4776 * offset + 71: minimum internal PLL frequency (single stage PLL)
4777 *
4778 * offset + 75: script table pointers, as described in
4779 * parse_script_table_pointers
4780 *
4781 * offset + 89: TMDS single link output A table pointer
4782 * offset + 91: TMDS single link output B table pointer
4783 * offset + 95: LVDS single link output A table pointer
4784 * offset + 105: flat panel timings table pointer
4785 * offset + 107: flat panel strapping translation table pointer
4786 * offset + 117: LVDS manufacturer panel config table pointer
4787 * offset + 119: LVDS manufacturer strapping translation table pointer
4788 *
4789 * offset + 142: PLL limits table pointer
4790 *
4791 * offset + 156: minimum pixel clock for LVDS dual link
4792 */
4793
4794 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
4795 uint16_t bmplength;
4796 uint16_t legacy_scripts_offset, legacy_i2c_offset;
4797
4798 /* load needed defaults in case we can't parse this info */
4799 bios->bdcb.dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
4800 bios->bdcb.dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
4801 bios->bdcb.dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
4802 bios->bdcb.dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
4803 bios->pub.digital_min_front_porch = 0x4b;
4804 bios->fmaxvco = 256000;
4805 bios->fminvco = 128000;
4806 bios->fp.duallink_transition_clk = 90000;
4807
4808 bmp_version_major = bmp[5];
4809 bmp_version_minor = bmp[6];
4810
4811 NV_TRACE(dev, "BMP version %d.%d\n",
4812 bmp_version_major, bmp_version_minor);
4813
4814 /*
4815 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4816 * pointer on early versions
4817 */
4818 if (bmp_version_major < 5)
4819 *(uint16_t *)&bios->data[0x36] = 0;
4820
4821 /*
4822 * Seems that the minor version was 1 for all major versions prior
4823 * to 5. Version 6 could theoretically exist, but I suspect BIT
4824 * happened instead.
4825 */
4826 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
4827 NV_ERROR(dev, "You have an unsupported BMP version. "
4828 "Please send in your bios\n");
4829 return -ENOSYS;
4830 }
4831
4832 if (bmp_version_major == 0)
4833 /* nothing that's currently useful in this version */
4834 return 0;
4835 else if (bmp_version_major == 1)
4836 bmplength = 44; /* exact for 1.01 */
4837 else if (bmp_version_major == 2)
4838 bmplength = 48; /* exact for 2.01 */
4839 else if (bmp_version_major == 3)
4840 bmplength = 54;
4841 /* guessed - mem init tables added in this version */
4842 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
4843 /* don't know if 5.0 exists... */
4844 bmplength = 62;
4845 /* guessed - BMP I2C indices added in version 4*/
4846 else if (bmp_version_minor < 0x6)
4847 bmplength = 67; /* exact for 5.01 */
4848 else if (bmp_version_minor < 0x10)
4849 bmplength = 75; /* exact for 5.06 */
4850 else if (bmp_version_minor == 0x10)
4851 bmplength = 89; /* exact for 5.10h */
4852 else if (bmp_version_minor < 0x14)
4853 bmplength = 118; /* exact for 5.11h */
4854 else if (bmp_version_minor < 0x24)
4855 /*
4856 * Not sure of version where pll limits came in;
4857 * certainly exist by 0x24 though.
4858 */
4859 /* length not exact: this is long enough to get lvds members */
4860 bmplength = 123;
4861 else if (bmp_version_minor < 0x27)
4862 /*
4863 * Length not exact: this is long enough to get pll limit
4864 * member
4865 */
4866 bmplength = 144;
4867 else
4868 /*
4869 * Length not exact: this is long enough to get dual link
4870 * transition clock.
4871 */
4872 bmplength = 158;
4873
4874 /* checksum */
4875 if (nv_cksum(bmp, 8)) {
4876 NV_ERROR(dev, "Bad BMP checksum\n");
4877 return -EINVAL;
4878 }
4879
4880 /*
4881 * Bit 4 seems to indicate either a mobile bios or a quadro card --
4882 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
4883 * (not nv10gl), bit 5 that the flat panel tables are present, and
4884 * bit 6 a tv bios.
4885 */
4886 bios->feature_byte = bmp[9];
4887
4888 parse_bios_version(dev, bios, offset + 10);
4889
4890 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
4891 bios->old_style_init = true;
4892 legacy_scripts_offset = 18;
4893 if (bmp_version_major < 2)
4894 legacy_scripts_offset -= 4;
4895 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
4896 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
4897
4898 if (bmp_version_major > 2) { /* appears in BMP 3 */
4899 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
4900 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
4901 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
4902 }
4903
4904 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
4905 if (bmplength > 61)
4906 legacy_i2c_offset = offset + 54;
4907 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
4908 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
4909 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
4910 bios->bdcb.dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
4911 bios->bdcb.dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
4912 bios->bdcb.dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
4913 bios->bdcb.dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
4914
4915 if (bmplength > 74) {
4916 bios->fmaxvco = ROM32(bmp[67]);
4917 bios->fminvco = ROM32(bmp[71]);
4918 }
4919 if (bmplength > 88)
4920 parse_script_table_pointers(bios, offset + 75);
4921 if (bmplength > 94) {
4922 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
4923 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
4924 /*
4925 * Never observed in use with lvds scripts, but is reused for
4926 * 18/24 bit panel interface default for EDID equipped panels
4927 * (if_is_24bit not set directly to avoid any oscillation).
4928 */
4929 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
4930 }
4931 if (bmplength > 108) {
4932 bios->fp.fptablepointer = ROM16(bmp[105]);
4933 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
4934 bios->fp.xlatwidth = 1;
4935 }
4936 if (bmplength > 120) {
4937 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
4938 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
4939 }
4940 if (bmplength > 143)
4941 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
4942
4943 if (bmplength > 157)
4944 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
4945
4946 return 0;
4947}
4948
4949static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
4950{
4951 int i, j;
4952
4953 for (i = 0; i <= (n - len); i++) {
4954 for (j = 0; j < len; j++)
4955 if (data[i + j] != str[j])
4956 break;
4957 if (j == len)
4958 return i;
4959 }
4960
4961 return 0;
4962}
4963
4964static int
4965read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
4966{
4967 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
4968 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
4969 int recordoffset = 0, rdofs = 1, wrofs = 0;
4970 uint8_t port_type = 0;
4971
4972 if (!i2ctable)
4973 return -EINVAL;
4974
4975 if (dcb_version >= 0x30) {
4976 if (i2ctable[0] != dcb_version) /* necessary? */
4977 NV_WARN(dev,
4978 "DCB I2C table version mismatch (%02X vs %02X)\n",
4979 i2ctable[0], dcb_version);
4980 dcb_i2c_ver = i2ctable[0];
4981 headerlen = i2ctable[1];
4982 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
4983 i2c_entries = i2ctable[2];
4984 else
4985 NV_WARN(dev,
4986 "DCB I2C table has more entries than indexable "
4987 "(%d entries, max index 15)\n", i2ctable[2]);
4988 entry_len = i2ctable[3];
4989 /* [4] is i2c_default_indices, read in parse_dcb_table() */
4990 }
4991 /*
4992 * It's your own fault if you call this function on a DCB 1.1 BIOS --
4993 * the test below is for DCB 1.2
4994 */
4995 if (dcb_version < 0x14) {
4996 recordoffset = 2;
4997 rdofs = 0;
4998 wrofs = 1;
4999 }
5000
5001 if (index == 0xf)
5002 return 0;
5003 if (index > i2c_entries) {
5004 NV_ERROR(dev, "DCB I2C index too big (%d > %d)\n",
5005 index, i2ctable[2]);
5006 return -ENOENT;
5007 }
5008 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
5009 NV_ERROR(dev, "DCB I2C entry invalid\n");
5010 return -EINVAL;
5011 }
5012
5013 if (dcb_i2c_ver >= 0x30) {
5014 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
5015
5016 /*
5017 * Fixup for chips using same address offset for read and
5018 * write.
5019 */
5020 if (port_type == 4) /* seen on C51 */
5021 rdofs = wrofs = 1;
5022 if (port_type >= 5) /* G80+ */
5023 rdofs = wrofs = 0;
5024 }
5025
5026 if (dcb_i2c_ver >= 0x40 && port_type != 5 && port_type != 6)
5027 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
5028
5029 i2c->port_type = port_type;
5030 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
5031 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
5032
5033 return 0;
5034}
5035
5036static struct dcb_gpio_entry *
5037new_gpio_entry(struct nvbios *bios)
5038{
5039 struct parsed_dcb_gpio *gpio = &bios->bdcb.gpio;
5040
5041 return &gpio->entry[gpio->entries++];
5042}
5043
5044struct dcb_gpio_entry *
5045nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5046{
5047 struct drm_nouveau_private *dev_priv = dev->dev_private;
5048 struct nvbios *bios = &dev_priv->VBIOS;
5049 int i;
5050
5051 for (i = 0; i < bios->bdcb.gpio.entries; i++) {
5052 if (bios->bdcb.gpio.entry[i].tag != tag)
5053 continue;
5054
5055 return &bios->bdcb.gpio.entry[i];
5056 }
5057
5058 return NULL;
5059}
5060
5061static void
5062parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5063{
5064 struct dcb_gpio_entry *gpio;
5065 uint16_t ent = ROM16(bios->data[offset]);
5066 uint8_t line = ent & 0x1f,
5067 tag = ent >> 5 & 0x3f,
5068 flags = ent >> 11 & 0x1f;
5069
5070 if (tag == 0x3f)
5071 return;
5072
5073 gpio = new_gpio_entry(bios);
5074
5075 gpio->tag = tag;
5076 gpio->line = line;
5077 gpio->invert = flags != 4;
5078}
5079
5080static void
5081parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5082{
5083 struct dcb_gpio_entry *gpio;
5084 uint32_t ent = ROM32(bios->data[offset]);
5085 uint8_t line = ent & 0x1f,
5086 tag = ent >> 8 & 0xff;
5087
5088 if (tag == 0xff)
5089 return;
5090
5091 gpio = new_gpio_entry(bios);
5092
5093 /* Currently unused, we may need more fields parsed at some
5094 * point. */
5095 gpio->tag = tag;
5096 gpio->line = line;
5097}
5098
5099static void
5100parse_dcb_gpio_table(struct nvbios *bios)
5101{
5102 struct drm_device *dev = bios->dev;
5103 uint16_t gpio_table_ptr = bios->bdcb.gpio_table_ptr;
5104 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5105 int header_len = gpio_table[1],
5106 entries = gpio_table[2],
5107 entry_len = gpio_table[3];
5108 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5109 int i;
5110
5111 if (bios->bdcb.version >= 0x40) {
5112 if (gpio_table_ptr && entry_len != 4) {
5113 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5114 return;
5115 }
5116
5117 parse_entry = parse_dcb40_gpio_entry;
5118
5119 } else if (bios->bdcb.version >= 0x30) {
5120 if (gpio_table_ptr && entry_len != 2) {
5121 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5122 return;
5123 }
5124
5125 parse_entry = parse_dcb30_gpio_entry;
5126
5127 } else if (bios->bdcb.version >= 0x22) {
5128 /*
5129 * DCBs older than v3.0 don't really have a GPIO
5130 * table, instead they keep some GPIO info at fixed
5131 * locations.
5132 */
5133 uint16_t dcbptr = ROM16(bios->data[0x36]);
5134 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5135
5136 if (tvdac_gpio[0] & 1) {
5137 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5138
5139 gpio->tag = DCB_GPIO_TVDAC0;
5140 gpio->line = tvdac_gpio[1] >> 4;
5141 gpio->invert = tvdac_gpio[0] & 2;
5142 }
5143 }
5144
5145 if (!gpio_table_ptr)
5146 return;
5147
5148 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5149 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5150 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5151 }
5152
5153 for (i = 0; i < entries; i++)
5154 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5155}
5156
5157struct dcb_connector_table_entry *
5158nouveau_bios_connector_entry(struct drm_device *dev, int index)
5159{
5160 struct drm_nouveau_private *dev_priv = dev->dev_private;
5161 struct nvbios *bios = &dev_priv->VBIOS;
5162 struct dcb_connector_table_entry *cte;
5163
5164 if (index >= bios->bdcb.connector.entries)
5165 return NULL;
5166
5167 cte = &bios->bdcb.connector.entry[index];
5168 if (cte->type == 0xff)
5169 return NULL;
5170
5171 return cte;
5172}
5173
5174static void
5175parse_dcb_connector_table(struct nvbios *bios)
5176{
5177 struct drm_device *dev = bios->dev;
5178 struct dcb_connector_table *ct = &bios->bdcb.connector;
5179 struct dcb_connector_table_entry *cte;
5180 uint8_t *conntab = &bios->data[bios->bdcb.connector_table_ptr];
5181 uint8_t *entry;
5182 int i;
5183
5184 if (!bios->bdcb.connector_table_ptr) {
ef2bb506 5185 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5186 return;
5187 }
5188
5189 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5190 conntab[0], conntab[1], conntab[2], conntab[3]);
5191 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5192 (conntab[3] != 2 && conntab[3] != 4)) {
5193 NV_ERROR(dev, " Unknown! Please report.\n");
5194 return;
5195 }
5196
5197 ct->entries = conntab[2];
5198
5199 entry = conntab + conntab[1];
5200 cte = &ct->entry[0];
5201 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
5202 if (conntab[3] == 2)
5203 cte->entry = ROM16(entry[0]);
5204 else
5205 cte->entry = ROM32(entry[0]);
5206 cte->type = (cte->entry & 0x000000ff) >> 0;
5207 cte->index = (cte->entry & 0x00000f00) >> 8;
5208 switch (cte->entry & 0x00033000) {
5209 case 0x00001000:
5210 cte->gpio_tag = 0x07;
5211 break;
5212 case 0x00002000:
5213 cte->gpio_tag = 0x08;
5214 break;
5215 case 0x00010000:
5216 cte->gpio_tag = 0x51;
5217 break;
5218 case 0x00020000:
5219 cte->gpio_tag = 0x52;
5220 break;
5221 default:
5222 cte->gpio_tag = 0xff;
5223 break;
5224 }
5225
5226 if (cte->type == 0xff)
5227 continue;
5228
5229 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5230 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
5231 }
5232}
5233
5234static struct dcb_entry *new_dcb_entry(struct parsed_dcb *dcb)
5235{
5236 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5237
5238 memset(entry, 0, sizeof(struct dcb_entry));
5239 entry->index = dcb->entries++;
5240
5241 return entry;
5242}
5243
5244static void fabricate_vga_output(struct parsed_dcb *dcb, int i2c, int heads)
5245{
5246 struct dcb_entry *entry = new_dcb_entry(dcb);
5247
5248 entry->type = 0;
5249 entry->i2c_index = i2c;
5250 entry->heads = heads;
5251 entry->location = DCB_LOC_ON_CHIP;
5252 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5253}
5254
5255static void fabricate_dvi_i_output(struct parsed_dcb *dcb, bool twoHeads)
5256{
5257 struct dcb_entry *entry = new_dcb_entry(dcb);
5258
5259 entry->type = 2;
5260 entry->i2c_index = LEGACY_I2C_PANEL;
5261 entry->heads = twoHeads ? 3 : 1;
5262 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5263 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5264 entry->duallink_possible = false; /* SiI164 and co. are single link */
5265
5266#if 0
5267 /*
5268 * For dvi-a either crtc probably works, but my card appears to only
5269 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5270 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5271 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5272 * the monitor picks up the mode res ok and lights up, but no pixel
5273 * data appears, so the board manufacturer probably connected up the
5274 * sync lines, but missed the video traces / components
5275 *
5276 * with this introduction, dvi-a left as an exercise for the reader.
5277 */
5278 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5279#endif
5280}
5281
5282static void fabricate_tv_output(struct parsed_dcb *dcb, bool twoHeads)
5283{
5284 struct dcb_entry *entry = new_dcb_entry(dcb);
5285
5286 entry->type = 1;
5287 entry->i2c_index = LEGACY_I2C_TV;
5288 entry->heads = twoHeads ? 3 : 1;
5289 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5290}
5291
5292static bool
5293parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb,
5294 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5295{
5296 entry->type = conn & 0xf;
5297 entry->i2c_index = (conn >> 4) & 0xf;
5298 entry->heads = (conn >> 8) & 0xf;
5299 if (bdcb->version >= 0x40)
5300 entry->connector = (conn >> 12) & 0xf;
5301 entry->bus = (conn >> 16) & 0xf;
5302 entry->location = (conn >> 20) & 0x3;
5303 entry->or = (conn >> 24) & 0xf;
5304 /*
5305 * Normal entries consist of a single bit, but dual link has the
5306 * next most significant bit set too
5307 */
5308 entry->duallink_possible =
5309 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5310
5311 switch (entry->type) {
5312 case OUTPUT_ANALOG:
5313 /*
5314 * Although the rest of a CRT conf dword is usually
5315 * zeros, mac biosen have stuff there so we must mask
5316 */
5317 entry->crtconf.maxfreq = (bdcb->version < 0x30) ?
5318 (conf & 0xffff) * 10 :
5319 (conf & 0xff) * 10000;
5320 break;
5321 case OUTPUT_LVDS:
5322 {
5323 uint32_t mask;
5324 if (conf & 0x1)
5325 entry->lvdsconf.use_straps_for_mode = true;
5326 if (bdcb->version < 0x22) {
5327 mask = ~0xd;
5328 /*
5329 * The laptop in bug 14567 lies and claims to not use
5330 * straps when it does, so assume all DCB 2.0 laptops
5331 * use straps, until a broken EDID using one is produced
5332 */
5333 entry->lvdsconf.use_straps_for_mode = true;
5334 /*
5335 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5336 * mean the same thing (probably wrong, but might work)
5337 */
5338 if (conf & 0x4 || conf & 0x8)
5339 entry->lvdsconf.use_power_scripts = true;
5340 } else {
5341 mask = ~0x5;
5342 if (conf & 0x4)
5343 entry->lvdsconf.use_power_scripts = true;
5344 }
5345 if (conf & mask) {
5346 /*
5347 * Until we even try to use these on G8x, it's
5348 * useless reporting unknown bits. They all are.
5349 */
5350 if (bdcb->version >= 0x40)
5351 break;
5352
5353 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5354 "please report\n");
5355 }
5356 break;
5357 }
5358 case OUTPUT_TV:
5359 {
5360 if (bdcb->version >= 0x30)
5361 entry->tvconf.has_component_output = conf & (0x8 << 4);
5362 else
5363 entry->tvconf.has_component_output = false;
5364
5365 break;
5366 }
5367 case OUTPUT_DP:
5368 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5369 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5370 switch ((conf & 0x0f000000) >> 24) {
5371 case 0xf:
5372 entry->dpconf.link_nr = 4;
5373 break;
5374 case 0x3:
5375 entry->dpconf.link_nr = 2;
5376 break;
5377 default:
5378 entry->dpconf.link_nr = 1;
5379 break;
5380 }
5381 break;
5382 case OUTPUT_TMDS:
5383 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5384 break;
5385 case 0xe:
5386 /* weird g80 mobile type that "nv" treats as a terminator */
5387 bdcb->dcb.entries--;
5388 return false;
5389 }
5390
5391 /* unsure what DCB version introduces this, 3.0? */
5392 if (conf & 0x100000)
5393 entry->i2c_upper_default = true;
5394
5395 return true;
5396}
5397
5398static bool
5399parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb,
5400 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5401{
b0d2de86
BS		 5402 switch (conn & 0x0000000f) {
5403 case 0:
5404 entry->type = OUTPUT_ANALOG;
5405 break;
5406 case 1:
5407 entry->type = OUTPUT_TV;
5408 break;
5409 case 2:
5410 case 3:
6ee73861 5411 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 5412 break;
5413 case 4:
5414 switch ((conn & 0x000000f0) >> 4) {
5415 case 0:
6ee73861 5416 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 5417 break;
5418 case 1:
5419 entry->type = OUTPUT_LVDS;
5420 break;
5421 default:
5422 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5423 (conn & 0x000000f0) >> 4);
5424 return false;
5425 }
5426 break;
5427 default:
5428 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5429 return false;
6ee73861 5430 }
b0d2de86
BS		 5431
5432 entry->i2c_index = (conn & 0x0003c000) >> 14;
5433 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5434 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5435 entry->location = (conn & 0x01e00000) >> 21;
5436 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 5437 entry->duallink_possible = false;
5438
5439 switch (entry->type) {
5440 case OUTPUT_ANALOG:
5441 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5442 break;
b0d2de86
BS		 5443 case OUTPUT_TV:
5444 entry->tvconf.has_component_output = false;
6ee73861
BS		 5445 break;
5446 case OUTPUT_TMDS:
5447 /*
5448 * Invent a DVI-A output, by copying the fields of the DVI-D
5449 * output; reported to work by math_b on an NV20(!).
5450 */
5451 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5452 break;
b0d2de86
BS		 5453 case OUTPUT_LVDS:
5454 if ((conn & 0x00003f00) != 0x10)
5455 entry->lvdsconf.use_straps_for_mode = true;
5456 entry->lvdsconf.use_power_scripts = true;
5457 break;
5458 default:
6ee73861
BS		 5459 break;
5460 }
5461
5462 return true;
5463}
5464
5465static bool parse_dcb_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb,
5466 uint32_t conn, uint32_t conf)
5467{
5468 struct dcb_entry *entry = new_dcb_entry(&bdcb->dcb);
5469 bool ret;
5470
5471 if (bdcb->version >= 0x20)
5472 ret = parse_dcb20_entry(dev, bdcb, conn, conf, entry);
5473 else
5474 ret = parse_dcb15_entry(dev, &bdcb->dcb, conn, conf, entry);
5475 if (!ret)
5476 return ret;
5477
5478 read_dcb_i2c_entry(dev, bdcb->version, bdcb->i2c_table,
5479 entry->i2c_index, &bdcb->dcb.i2c[entry->i2c_index]);
5480
5481 return true;
5482}
5483
5484static
5485void merge_like_dcb_entries(struct drm_device *dev, struct parsed_dcb *dcb)
5486{
5487 /*
5488 * DCB v2.0 lists each output combination separately.
5489 * Here we merge compatible entries to have fewer outputs, with
5490 * more options
5491 */
5492
5493 int i, newentries = 0;
5494
5495 for (i = 0; i < dcb->entries; i++) {
5496 struct dcb_entry *ient = &dcb->entry[i];
5497 int j;
5498
5499 for (j = i + 1; j < dcb->entries; j++) {
5500 struct dcb_entry *jent = &dcb->entry[j];
5501
5502 if (jent->type == 100) /* already merged entry */
5503 continue;
5504
5505 /* merge heads field when all other fields the same */
5506 if (jent->i2c_index == ient->i2c_index &&
5507 jent->type == ient->type &&
5508 jent->location == ient->location &&
5509 jent->or == ient->or) {
5510 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5511 i, j);
5512 ient->heads |= jent->heads;
5513 jent->type = 100; /* dummy value */
5514 }
5515 }
5516 }
5517
5518 /* Compact entries merged into others out of dcb */
5519 for (i = 0; i < dcb->entries; i++) {
5520 if (dcb->entry[i].type == 100)
5521 continue;
5522
5523 if (newentries != i) {
5524 dcb->entry[newentries] = dcb->entry[i];
5525 dcb->entry[newentries].index = newentries;
5526 }
5527 newentries++;
5528 }
5529
5530 dcb->entries = newentries;
5531}
5532
ed42f824
BS		 5533static int
5534parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 5535{
ed42f824 5536 struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861
BS		 5537 struct bios_parsed_dcb *bdcb = &bios->bdcb;
5538 struct parsed_dcb *dcb;
ed42f824 5539 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 5540 uint8_t *dcbtable;
5541 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5542 bool configblock = true;
5543 int recordlength = 8, confofs = 4;
5544 int i;
5545
5546 dcb = bios->pub.dcb = &bdcb->dcb;
5547 dcb->entries = 0;
5548
5549 /* get the offset from 0x36 */
ed42f824
BS		 5550 if (dev_priv->card_type > NV_04) {
5551 dcbptr = ROM16(bios->data[0x36]);
5552 if (dcbptr == 0x0000)
5553 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5554 }
6ee73861 5555
ed42f824 5556 /* this situation likely means a really old card, pre DCB */
6ee73861 5557 if (dcbptr == 0x0) {
ed42f824 5558 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 5559 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5560
ed42f824 5561 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 5562 fabricate_tv_output(dcb, twoHeads);
5563
5564 return 0;
5565 }
5566
5567 dcbtable = &bios->data[dcbptr];
5568
5569 /* get DCB version */
5570 bdcb->version = dcbtable[0];
5571 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
5572 bdcb->version >> 4, bdcb->version & 0xf);
5573
5574 if (bdcb->version >= 0x20) { /* NV17+ */
5575 uint32_t sig;
5576
5577 if (bdcb->version >= 0x30) { /* NV40+ */
5578 headerlen = dcbtable[1];
5579 entries = dcbtable[2];
5580 recordlength = dcbtable[3];
5581 i2ctabptr = ROM16(dcbtable[4]);
5582 sig = ROM32(dcbtable[6]);
5583 bdcb->gpio_table_ptr = ROM16(dcbtable[10]);
5584 bdcb->connector_table_ptr = ROM16(dcbtable[20]);
5585 } else {
5586 i2ctabptr = ROM16(dcbtable[2]);
5587 sig = ROM32(dcbtable[4]);
5588 headerlen = 8;
5589 }
5590
5591 if (sig != 0x4edcbdcb) {
5592 NV_ERROR(dev, "Bad Display Configuration Block "
5593 "signature (%08X)\n", sig);
5594 return -EINVAL;
5595 }
5596 } else if (bdcb->version >= 0x15) { /* some NV11 and NV20 */
5597 char sig[8] = { 0 };
5598
5599 strncpy(sig, (char *)&dcbtable[-7], 7);
5600 i2ctabptr = ROM16(dcbtable[2]);
5601 recordlength = 10;
5602 confofs = 6;
5603
5604 if (strcmp(sig, "DEV_REC")) {
5605 NV_ERROR(dev, "Bad Display Configuration Block "
5606 "signature (%s)\n", sig);
5607 return -EINVAL;
5608 }
5609 } else {
5610 /*
5611 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5612 * has the same single (crt) entry, even when tv-out present, so
5613 * the conclusion is this version cannot really be used.
5614 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5615 * 5 entries, which are not specific to the card and so no use.
5616 * v1.2 does have an I2C table that read_dcb_i2c_table can
5617 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5618 * pointer, so use the indices parsed in parse_bmp_structure.
5619 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5620 */
5621 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5622 "adding all possible outputs\n");
5623 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5624
5625 /*
5626 * Attempt to detect TV before DVI because the test
5627 * for the former is more accurate and it rules the
5628 * latter out.
5629 */
5630 if (nv04_tv_identify(dev,
5631 bios->legacy.i2c_indices.tv) >= 0)
5632 fabricate_tv_output(dcb, twoHeads);
5633
5634 else if (bios->tmds.output0_script_ptr ||
5635 bios->tmds.output1_script_ptr)
5636 fabricate_dvi_i_output(dcb, twoHeads);
5637
5638 return 0;
5639 }
5640
5641 if (!i2ctabptr)
5642 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5643 else {
5644 bdcb->i2c_table = &bios->data[i2ctabptr];
5645 if (bdcb->version >= 0x30)
5646 bdcb->i2c_default_indices = bdcb->i2c_table[4];
5647 }
5648
5649 parse_dcb_gpio_table(bios);
5650 parse_dcb_connector_table(bios);
5651
5652 if (entries > DCB_MAX_NUM_ENTRIES)
5653 entries = DCB_MAX_NUM_ENTRIES;
5654
5655 for (i = 0; i < entries; i++) {
5656 uint32_t connection, config = 0;
5657
5658 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5659 if (configblock)
5660 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5661
5662 /* seen on an NV11 with DCB v1.5 */
5663 if (connection == 0x00000000)
5664 break;
5665
5666 /* seen on an NV17 with DCB v2.0 */
5667 if (connection == 0xffffffff)
5668 break;
5669
5670 if ((connection & 0x0000000f) == 0x0000000f)
5671 continue;
5672
5673 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5674 dcb->entries, connection, config);
5675
5676 if (!parse_dcb_entry(dev, bdcb, connection, config))
5677 break;
5678 }
5679
5680 /*
5681 * apart for v2.1+ not being known for requiring merging, this
5682 * guarantees dcbent->index is the index of the entry in the rom image
5683 */
5684 if (bdcb->version < 0x21)
5685 merge_like_dcb_entries(dev, dcb);
5686
5687 return dcb->entries ? 0 : -ENXIO;
5688}
5689
5690static void
5691fixup_legacy_connector(struct nvbios *bios)
5692{
5693 struct bios_parsed_dcb *bdcb = &bios->bdcb;
5694 struct parsed_dcb *dcb = &bdcb->dcb;
5695 int high = 0, i;
5696
5697 /*
5698 * DCB 3.0 also has the table in most cases, but there are some cards
5699 * where the table is filled with stub entries, and the DCB entriy
5700 * indices are all 0. We don't need the connector indices on pre-G80
5701 * chips (yet?) so limit the use to DCB 4.0 and above.
5702 */
5703 if (bdcb->version >= 0x40)
5704 return;
5705
5706 /*
5707 * No known connector info before v3.0, so make it up. the rule here
5708 * is: anything on the same i2c bus is considered to be on the same
5709 * connector. any output without an associated i2c bus is assigned
5710 * its own unique connector index.
5711 */
5712 for (i = 0; i < dcb->entries; i++) {
5713 if (dcb->entry[i].i2c_index == 0xf)
5714 continue;
5715
5716 /*
5717 * Ignore the I2C index for on-chip TV-out, as there
5718 * are cards with bogus values (nv31m in bug 23212),
5719 * and it's otherwise useless.
5720 */
5721 if (dcb->entry[i].type == OUTPUT_TV &&
5722 dcb->entry[i].location == DCB_LOC_ON_CHIP) {
5723 dcb->entry[i].i2c_index = 0xf;
5724 continue;
5725 }
5726
5727 dcb->entry[i].connector = dcb->entry[i].i2c_index;
5728 if (dcb->entry[i].connector > high)
5729 high = dcb->entry[i].connector;
5730 }
5731
5732 for (i = 0; i < dcb->entries; i++) {
5733 if (dcb->entry[i].i2c_index != 0xf)
5734 continue;
5735
5736 dcb->entry[i].connector = ++high;
5737 }
5738}
5739
5740static void
5741fixup_legacy_i2c(struct nvbios *bios)
5742{
5743 struct parsed_dcb *dcb = &bios->bdcb.dcb;
5744 int i;
5745
5746 for (i = 0; i < dcb->entries; i++) {
5747 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
5748 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
5749 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
5750 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
5751 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
5752 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
5753 }
5754}
5755
5756static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5757{
5758 /*
5759 * The header following the "HWSQ" signature has the number of entries,
5760 * and the entry size
5761 *
5762 * An entry consists of a dword to write to the sequencer control reg
5763 * (0x00001304), followed by the ucode bytes, written sequentially,
5764 * starting at reg 0x00001400
5765 */
5766
5767 uint8_t bytes_to_write;
5768 uint16_t hwsq_entry_offset;
5769 int i;
5770
5771 if (bios->data[hwsq_offset] <= entry) {
5772 NV_ERROR(dev, "Too few entries in HW sequencer table for "
5773 "requested entry\n");
5774 return -ENOENT;
5775 }
5776
5777 bytes_to_write = bios->data[hwsq_offset + 1];
5778
5779 if (bytes_to_write != 36) {
5780 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
5781 return -EINVAL;
5782 }
5783
5784 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
5785
5786 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
5787
5788 /* set sequencer control */
5789 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
5790 bytes_to_write -= 4;
5791
5792 /* write ucode */
5793 for (i = 0; i < bytes_to_write; i += 4)
5794 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
5795
5796 /* twiddle NV_PBUS_DEBUG_4 */
5797 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
5798
5799 return 0;
5800}
5801
5802static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
5803 struct nvbios *bios)
5804{
5805 /*
5806 * BMP based cards, from NV17, need a microcode loading to correctly
5807 * control the GPIO etc for LVDS panels
5808 *
5809 * BIT based cards seem to do this directly in the init scripts
5810 *
5811 * The microcode entries are found by the "HWSQ" signature.
5812 */
5813
5814 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
5815 const int sz = sizeof(hwsq_signature);
5816 int hwsq_offset;
5817
5818 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
5819 if (!hwsq_offset)
5820 return 0;
5821
5822 /* always use entry 0? */
5823 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
5824}
5825
5826uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
5827{
5828 struct drm_nouveau_private *dev_priv = dev->dev_private;
5829 struct nvbios *bios = &dev_priv->VBIOS;
5830 const uint8_t edid_sig[] = {
5831 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
5832 uint16_t offset = 0;
5833 uint16_t newoffset;
5834 int searchlen = NV_PROM_SIZE;
5835
5836 if (bios->fp.edid)
5837 return bios->fp.edid;
5838
5839 while (searchlen) {
5840 newoffset = findstr(&bios->data[offset], searchlen,
5841 edid_sig, 8);
5842 if (!newoffset)
5843 return NULL;
5844 offset += newoffset;
5845 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
5846 break;
5847
5848 searchlen -= offset;
5849 offset++;
5850 }
5851
5852 NV_TRACE(dev, "Found EDID in BIOS\n");
5853
5854 return bios->fp.edid = &bios->data[offset];
5855}
5856
5857void
5858nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
5859 struct dcb_entry *dcbent)
5860{
5861 struct drm_nouveau_private *dev_priv = dev->dev_private;
5862 struct nvbios *bios = &dev_priv->VBIOS;
5863 struct init_exec iexec = { true, false };
5864
d9184fa9 5865 mutex_lock(&bios->lock);
6ee73861
BS		 5866 bios->display.output = dcbent;
5867 parse_init_table(bios, table, &iexec);
5868 bios->display.output = NULL;
d9184fa9 5869 mutex_unlock(&bios->lock);
6ee73861
BS		 5870}
5871
5872static bool NVInitVBIOS(struct drm_device *dev)
5873{
5874 struct drm_nouveau_private *dev_priv = dev->dev_private;
5875 struct nvbios *bios = &dev_priv->VBIOS;
5876
5877 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 5878 mutex_init(&bios->lock);
6ee73861
BS		 5879 bios->dev = dev;
5880
5881 if (!NVShadowVBIOS(dev, bios->data))
5882 return false;
5883
5884 bios->length = NV_PROM_SIZE;
5885 return true;
5886}
5887
5888static int nouveau_parse_vbios_struct(struct drm_device *dev)
5889{
5890 struct drm_nouveau_private *dev_priv = dev->dev_private;
5891 struct nvbios *bios = &dev_priv->VBIOS;
5892 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
5893 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
5894 int offset;
5895
5896 offset = findstr(bios->data, bios->length,
5897 bit_signature, sizeof(bit_signature));
5898 if (offset) {
5899 NV_TRACE(dev, "BIT BIOS found\n");
5900 return parse_bit_structure(bios, offset + 6);
5901 }
5902
5903 offset = findstr(bios->data, bios->length,
5904 bmp_signature, sizeof(bmp_signature));
5905 if (offset) {
5906 NV_TRACE(dev, "BMP BIOS found\n");
5907 return parse_bmp_structure(dev, bios, offset);
5908 }
5909
5910 NV_ERROR(dev, "No known BIOS signature found\n");
5911 return -ENODEV;
5912}
5913
5914int
5915nouveau_run_vbios_init(struct drm_device *dev)
5916{
5917 struct drm_nouveau_private *dev_priv = dev->dev_private;
5918 struct nvbios *bios = &dev_priv->VBIOS;
5919 int i, ret = 0;
5920
5921 NVLockVgaCrtcs(dev, false);
5922 if (nv_two_heads(dev))
5923 NVSetOwner(dev, bios->state.crtchead);
5924
5925 if (bios->major_version < 5) /* BMP only */
5926 load_nv17_hw_sequencer_ucode(dev, bios);
5927
5928 if (bios->execute) {
5929 bios->fp.last_script_invoc = 0;
5930 bios->fp.lvds_init_run = false;
5931 }
5932
5933 parse_init_tables(bios);
5934
5935 /*
5936 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
5937 * parser will run this right after the init tables, the binary
5938 * driver appears to run it at some point later.
5939 */
5940 if (bios->some_script_ptr) {
5941 struct init_exec iexec = {true, false};
5942
5943 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
5944 bios->some_script_ptr);
5945 parse_init_table(bios, bios->some_script_ptr, &iexec);
5946 }
5947
5948 if (dev_priv->card_type >= NV_50) {
5949 for (i = 0; i < bios->bdcb.dcb.entries; i++) {
5950 nouveau_bios_run_display_table(dev,
5951 &bios->bdcb.dcb.entry[i],
5952 0, 0);
5953 }
5954 }
5955
5956 NVLockVgaCrtcs(dev, true);
5957
5958 return ret;
5959}
5960
5961static void
5962nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
5963{
5964 struct drm_nouveau_private *dev_priv = dev->dev_private;
5965 struct nvbios *bios = &dev_priv->VBIOS;
5966 struct dcb_i2c_entry *entry;
5967 int i;
5968
5969 entry = &bios->bdcb.dcb.i2c[0];
5970 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
5971 nouveau_i2c_fini(dev, entry);
5972}
5973
5974int
5975nouveau_bios_init(struct drm_device *dev)
5976{
5977 struct drm_nouveau_private *dev_priv = dev->dev_private;
5978 struct nvbios *bios = &dev_priv->VBIOS;
5979 uint32_t saved_nv_pextdev_boot_0;
5980 bool was_locked;
5981 int ret;
5982
5983 dev_priv->vbios = &bios->pub;
5984
5985 if (!NVInitVBIOS(dev))
5986 return -ENODEV;
5987
5988 ret = nouveau_parse_vbios_struct(dev);
5989 if (ret)
5990 return ret;
5991
5992 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
5993 if (ret)
5994 return ret;
5995
5996 fixup_legacy_i2c(bios);
5997 fixup_legacy_connector(bios);
5998
5999 if (!bios->major_version) /* we don't run version 0 bios */
6000 return 0;
6001
6002 /* these will need remembering across a suspend */
6003 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6004 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6005
6006 /* init script execution disabled */
6007 bios->execute = false;
6008
6009 /* ... unless card isn't POSTed already */
6010 if (dev_priv->card_type >= NV_10 &&
6011 NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6012 NVReadVgaCrtc(dev, 0, 0x1a) == 0) {
6013 NV_INFO(dev, "Adaptor not initialised\n");
6014 if (dev_priv->card_type < NV_50) {
6015 NV_ERROR(dev, "Unable to POST this chipset\n");
6016 return -ENODEV;
6017 }
6018
6019 NV_INFO(dev, "Running VBIOS init tables\n");
6020 bios->execute = true;
6021 }
6022
6023 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6024
6025 ret = nouveau_run_vbios_init(dev);
6026 if (ret) {
6027 dev_priv->vbios = NULL;
6028 return ret;
6029 }
6030
6031 /* feature_byte on BMP is poor, but init always sets CR4B */
6032 was_locked = NVLockVgaCrtcs(dev, false);
6033 if (bios->major_version < 5)
6034 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6035
6036 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6037 if (bios->is_mobile || bios->major_version >= 5)
6038 ret = parse_fp_mode_table(dev, bios);
6039 NVLockVgaCrtcs(dev, was_locked);
6040
6041 /* allow subsequent scripts to execute */
6042 bios->execute = true;
6043
6044 return 0;
6045}
6046
6047void
6048nouveau_bios_takedown(struct drm_device *dev)
6049{
6050 nouveau_bios_i2c_devices_takedown(dev);
6051}
Clone of davem's net-next-2.6 tree