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drm/nouveau: display error message for any failed init table opcode
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861
BS		 30
31/* these defines are made up */
32#define NV_CIO_CRE_44_HEADA 0x0
33#define NV_CIO_CRE_44_HEADB 0x3
34#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
35#define LEGACY_I2C_CRT 0x80
36#define LEGACY_I2C_PANEL 0x81
37#define LEGACY_I2C_TV 0x82
38
39#define EDID1_LEN 128
40
41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42#define LOG_OLD_VALUE(x)
43
44#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
45#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
46
47struct init_exec {
48 bool execute;
49 bool repeat;
50};
51
52static bool nv_cksum(const uint8_t *data, unsigned int length)
53{
54 /*
55 * There's a few checksums in the BIOS, so here's a generic checking
56 * function.
57 */
58 int i;
59 uint8_t sum = 0;
60
61 for (i = 0; i < length; i++)
62 sum += data[i];
63
64 if (sum)
65 return true;
66
67 return false;
68}
69
70static int
71score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
72{
73 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
74 NV_TRACEWARN(dev, "... BIOS signature not found\n");
75 return 0;
76 }
77
78 if (nv_cksum(data, data[2] * 512)) {
79 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
80 /* if a ro image is somewhat bad, it's probably all rubbish */
81 return writeable ? 2 : 1;
82 } else
83 NV_TRACE(dev, "... appears to be valid\n");
84
85 return 3;
86}
87
88static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
89{
90 struct drm_nouveau_private *dev_priv = dev->dev_private;
91 uint32_t pci_nv_20, save_pci_nv_20;
92 int pcir_ptr;
93 int i;
94
95 if (dev_priv->card_type >= NV_50)
96 pci_nv_20 = 0x88050;
97 else
98 pci_nv_20 = NV_PBUS_PCI_NV_20;
99
100 /* enable ROM access */
101 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
102 nvWriteMC(dev, pci_nv_20,
103 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
104
105 /* bail if no rom signature */
106 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
107 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
108 goto out;
109
110 /* additional check (see note below) - read PCI record header */
111 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
112 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
113 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
117 goto out;
118
119 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
120 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
121 * each byte. we'll hope pramin has something usable instead
122 */
123 for (i = 0; i < NV_PROM_SIZE; i++)
124 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
125
126out:
127 /* disable ROM access */
128 nvWriteMC(dev, pci_nv_20,
129 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
130}
131
132static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
133{
134 struct drm_nouveau_private *dev_priv = dev->dev_private;
135 uint32_t old_bar0_pramin = 0;
136 int i;
137
138 if (dev_priv->card_type >= NV_50) {
139 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
140
141 if (!vbios_vram)
142 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
143
144 old_bar0_pramin = nv_rd32(dev, 0x1700);
145 nv_wr32(dev, 0x1700, vbios_vram >> 16);
146 }
147
148 /* bail if no rom signature */
149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
151 goto out;
152
153 for (i = 0; i < NV_PROM_SIZE; i++)
154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
155
156out:
157 if (dev_priv->card_type >= NV_50)
158 nv_wr32(dev, 0x1700, old_bar0_pramin);
159}
160
161static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
162{
163 void __iomem *rom = NULL;
164 size_t rom_len;
165 int ret;
166
167 ret = pci_enable_rom(dev->pdev);
168 if (ret)
169 return;
170
171 rom = pci_map_rom(dev->pdev, &rom_len);
172 if (!rom)
173 goto out;
174 memcpy_fromio(data, rom, rom_len);
175 pci_unmap_rom(dev->pdev, rom);
176
177out:
178 pci_disable_rom(dev->pdev);
179}
180
181struct methods {
182 const char desc[8];
183 void (*loadbios)(struct drm_device *, uint8_t *);
184 const bool rw;
6ee73861
BS		 185};
186
187static struct methods nv04_methods[] = {
188 { "PROM", load_vbios_prom, false },
189 { "PRAMIN", load_vbios_pramin, true },
190 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 191};
192
193static struct methods nv50_methods[] = {
194 { "PRAMIN", load_vbios_pramin, true },
195 { "PROM", load_vbios_prom, false },
196 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 197};
198
657b6245
MK		 199#define METHODCNT 3
200
6ee73861
BS		 201static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
202{
203 struct drm_nouveau_private *dev_priv = dev->dev_private;
657b6245
MK		 204 struct methods *methods;
205 int i;
6ee73861 206 int testscore = 3;
657b6245 207 int scores[METHODCNT];
6ee73861
BS		 208
209 if (nouveau_vbios) {
657b6245
MK		 210 methods = nv04_methods;
211 for (i = 0; i < METHODCNT; i++)
212 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 213 break;
6ee73861 214
657b6245 215 if (i < METHODCNT) {
6ee73861 216 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 217 methods[i].desc);
6ee73861 218
657b6245
MK		 219 methods[i].loadbios(dev, data);
220 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 221 return true;
222 }
223
224 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
225 }
226
227 if (dev_priv->card_type < NV_50)
228 methods = nv04_methods;
229 else
230 methods = nv50_methods;
231
657b6245 232 for (i = 0; i < METHODCNT; i++) {
6ee73861 233 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 234 methods[i].desc);
6ee73861 235 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 236 methods[i].loadbios(dev, data);
237 scores[i] = score_vbios(dev, data, methods[i].rw);
238 if (scores[i] == testscore)
6ee73861 239 return true;
6ee73861
BS		 240 }
241
242 while (--testscore > 0) {
657b6245
MK		 243 for (i = 0; i < METHODCNT; i++) {
244 if (scores[i] == testscore) {
6ee73861 245 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 246 methods[i].desc);
247 methods[i].loadbios(dev, data);
6ee73861
BS		 248 return true;
249 }
6ee73861
BS		 250 }
251 }
252
253 NV_ERROR(dev, "No valid BIOS image found\n");
254 return false;
255}
256
257struct init_tbl_entry {
258 char *name;
259 uint8_t id;
9170a824
BS		 260 /* Return:
261 * > 0: success, length of opcode
262 * 0: success, but abort further parsing of table (INIT_DONE etc)
263 * < 0: failure, table parsing will be aborted
264 */
37383650 265 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 266};
267
268struct bit_entry {
269 uint8_t id[2];
270 uint16_t length;
271 uint16_t offset;
272};
273
274static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
275
276#define MACRO_INDEX_SIZE 2
277#define MACRO_SIZE 8
278#define CONDITION_SIZE 12
279#define IO_FLAG_CONDITION_SIZE 9
280#define IO_CONDITION_SIZE 5
281#define MEM_INIT_SIZE 66
282
283static void still_alive(void)
284{
285#if 0
286 sync();
287 msleep(2);
288#endif
289}
290
291static uint32_t
292munge_reg(struct nvbios *bios, uint32_t reg)
293{
294 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
295 struct dcb_entry *dcbent = bios->display.output;
296
297 if (dev_priv->card_type < NV_50)
298 return reg;
299
300 if (reg & 0x40000000) {
301 BUG_ON(!dcbent);
302
303 reg += (ffs(dcbent->or) - 1) * 0x800;
304 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
305 reg += 0x00000080;
306 }
307
308 reg &= ~0x60000000;
309 return reg;
310}
311
312static int
313valid_reg(struct nvbios *bios, uint32_t reg)
314{
315 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
316 struct drm_device *dev = bios->dev;
317
318 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 319 if (reg & 0x2 ||
04a39c57 320 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 321 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
322
323 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 324 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 325 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
326 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
327 reg);
328
9855e584
BS		 329 if (reg >= (8*1024*1024)) {
330 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
331 return 0;
6ee73861 332 }
9855e584
BS		 333
334 return 1;
6ee73861
BS		 335}
336
337static bool
338valid_idx_port(struct nvbios *bios, uint16_t port)
339{
340 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
341 struct drm_device *dev = bios->dev;
342
343 /*
344 * If adding more ports here, the read/write functions below will need
345 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
346 * used for the port in question
347 */
348 if (dev_priv->card_type < NV_50) {
349 if (port == NV_CIO_CRX__COLOR)
350 return true;
351 if (port == NV_VIO_SRX)
352 return true;
353 } else {
354 if (port == NV_CIO_CRX__COLOR)
355 return true;
356 }
357
358 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
359 port);
360
361 return false;
362}
363
364static bool
365valid_port(struct nvbios *bios, uint16_t port)
366{
367 struct drm_device *dev = bios->dev;
368
369 /*
370 * If adding more ports here, the read/write functions below will need
371 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
372 * used for the port in question
373 */
374 if (port == NV_VIO_VSE2)
375 return true;
376
377 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
378
379 return false;
380}
381
382static uint32_t
383bios_rd32(struct nvbios *bios, uint32_t reg)
384{
385 uint32_t data;
386
387 reg = munge_reg(bios, reg);
388 if (!valid_reg(bios, reg))
389 return 0;
390
391 /*
392 * C51 sometimes uses regs with bit0 set in the address. For these
393 * cases there should exist a translation in a BIOS table to an IO
394 * port address which the BIOS uses for accessing the reg
395 *
396 * These only seem to appear for the power control regs to a flat panel,
397 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
398 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
399 * suspend-resume mmio trace from a C51 will be required to see if this
400 * is true for the power microcode in 0x14.., or whether the direct IO
401 * port access method is needed
402 */
403 if (reg & 0x1)
404 reg &= ~0x1;
405
406 data = nv_rd32(bios->dev, reg);
407
408 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
409
410 return data;
411}
412
413static void
414bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
415{
416 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
417
418 reg = munge_reg(bios, reg);
419 if (!valid_reg(bios, reg))
420 return;
421
422 /* see note in bios_rd32 */
423 if (reg & 0x1)
424 reg &= 0xfffffffe;
425
426 LOG_OLD_VALUE(bios_rd32(bios, reg));
427 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
428
04a39c57 429 if (dev_priv->vbios.execute) {
6ee73861
BS		 430 still_alive();
431 nv_wr32(bios->dev, reg, data);
432 }
433}
434
435static uint8_t
436bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
437{
438 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
439 struct drm_device *dev = bios->dev;
440 uint8_t data;
441
442 if (!valid_idx_port(bios, port))
443 return 0;
444
445 if (dev_priv->card_type < NV_50) {
446 if (port == NV_VIO_SRX)
447 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
448 else /* assume NV_CIO_CRX__COLOR */
449 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
450 } else {
451 uint32_t data32;
452
453 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
454 data = (data32 >> ((index & 3) << 3)) & 0xff;
455 }
456
457 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
458 "Head: 0x%02X, Data: 0x%02X\n",
459 port, index, bios->state.crtchead, data);
460 return data;
461}
462
463static void
464bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
465{
466 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
467 struct drm_device *dev = bios->dev;
468
469 if (!valid_idx_port(bios, port))
470 return;
471
472 /*
473 * The current head is maintained in the nvbios member state.crtchead.
474 * We trap changes to CR44 and update the head variable and hence the
475 * register set written.
476 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
477 * of the write, and to head1 after the write
478 */
479 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
480 data != NV_CIO_CRE_44_HEADB)
481 bios->state.crtchead = 0;
482
483 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
484 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
485 "Head: 0x%02X, Data: 0x%02X\n",
486 port, index, bios->state.crtchead, data);
487
488 if (bios->execute && dev_priv->card_type < NV_50) {
489 still_alive();
490 if (port == NV_VIO_SRX)
491 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
492 else /* assume NV_CIO_CRX__COLOR */
493 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
494 } else
495 if (bios->execute) {
496 uint32_t data32, shift = (index & 3) << 3;
497
498 still_alive();
499
500 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
501 data32 &= ~(0xff << shift);
502 data32 |= (data << shift);
503 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
504 }
505
506 if (port == NV_CIO_CRX__COLOR &&
507 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
508 bios->state.crtchead = 1;
509}
510
511static uint8_t
512bios_port_rd(struct nvbios *bios, uint16_t port)
513{
514 uint8_t data, head = bios->state.crtchead;
515
516 if (!valid_port(bios, port))
517 return 0;
518
519 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
520
521 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
522 port, head, data);
523
524 return data;
525}
526
527static void
528bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
529{
530 int head = bios->state.crtchead;
531
532 if (!valid_port(bios, port))
533 return;
534
535 LOG_OLD_VALUE(bios_port_rd(bios, port));
536 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
537 port, head, data);
538
539 if (!bios->execute)
540 return;
541
542 still_alive();
543 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
544}
545
546static bool
547io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
548{
549 /*
550 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
551 * for the CRTC index; 1 byte for the mask to apply to the value
552 * retrieved from the CRTC; 1 byte for the shift right to apply to the
553 * masked CRTC value; 2 bytes for the offset to the flag array, to
554 * which the shifted value is added; 1 byte for the mask applied to the
555 * value read from the flag array; and 1 byte for the value to compare
556 * against the masked byte from the flag table.
557 */
558
559 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
560 uint16_t crtcport = ROM16(bios->data[condptr]);
561 uint8_t crtcindex = bios->data[condptr + 2];
562 uint8_t mask = bios->data[condptr + 3];
563 uint8_t shift = bios->data[condptr + 4];
564 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
565 uint8_t flagarraymask = bios->data[condptr + 7];
566 uint8_t cmpval = bios->data[condptr + 8];
567 uint8_t data;
568
569 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
570 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
571 "Cmpval: 0x%02X\n",
572 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
573
574 data = bios_idxprt_rd(bios, crtcport, crtcindex);
575
576 data = bios->data[flagarray + ((data & mask) >> shift)];
577 data &= flagarraymask;
578
579 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
580 offset, data, cmpval);
581
582 return (data == cmpval);
583}
584
585static bool
586bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
587{
588 /*
589 * The condition table entry has 4 bytes for the address of the
590 * register to check, 4 bytes for a mask to apply to the register and
591 * 4 for a test comparison value
592 */
593
594 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
595 uint32_t reg = ROM32(bios->data[condptr]);
596 uint32_t mask = ROM32(bios->data[condptr + 4]);
597 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
598 uint32_t data;
599
600 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
601 offset, cond, reg, mask);
602
603 data = bios_rd32(bios, reg) & mask;
604
605 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
606 offset, data, cmpval);
607
608 return (data == cmpval);
609}
610
611static bool
612io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
613{
614 /*
615 * The IO condition entry has 2 bytes for the IO port address; 1 byte
616 * for the index to write to io_port; 1 byte for the mask to apply to
617 * the byte read from io_port+1; and 1 byte for the value to compare
618 * against the masked byte.
619 */
620
621 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
622 uint16_t io_port = ROM16(bios->data[condptr]);
623 uint8_t port_index = bios->data[condptr + 2];
624 uint8_t mask = bios->data[condptr + 3];
625 uint8_t cmpval = bios->data[condptr + 4];
626
627 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
628
629 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
630 offset, data, cmpval);
631
632 return (data == cmpval);
633}
634
635static int
636nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
637{
638 struct drm_nouveau_private *dev_priv = dev->dev_private;
639 uint32_t reg0 = nv_rd32(dev, reg + 0);
640 uint32_t reg1 = nv_rd32(dev, reg + 4);
641 struct nouveau_pll_vals pll;
642 struct pll_lims pll_limits;
643 int ret;
644
645 ret = get_pll_limits(dev, reg, &pll_limits);
646 if (ret)
647 return ret;
648
649 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
650 if (!clk)
651 return -ERANGE;
652
653 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
654 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
655
04a39c57 656 if (dev_priv->vbios.execute) {
6ee73861
BS		 657 still_alive();
658 nv_wr32(dev, reg + 4, reg1);
659 nv_wr32(dev, reg + 0, reg0);
660 }
661
662 return 0;
663}
664
665static int
666setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
667{
668 struct drm_device *dev = bios->dev;
669 struct drm_nouveau_private *dev_priv = dev->dev_private;
670 /* clk in kHz */
671 struct pll_lims pll_lim;
672 struct nouveau_pll_vals pllvals;
673 int ret;
674
675 if (dev_priv->card_type >= NV_50)
676 return nv50_pll_set(dev, reg, clk);
677
678 /* high regs (such as in the mac g5 table) are not -= 4 */
679 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
680 if (ret)
681 return ret;
682
683 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
684 if (!clk)
685 return -ERANGE;
686
687 if (bios->execute) {
688 still_alive();
689 nouveau_hw_setpll(dev, reg, &pllvals);
690 }
691
692 return 0;
693}
694
695static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
696{
697 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 698 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 699
700 /*
701 * For the results of this function to be correct, CR44 must have been
702 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
703 * and the DCB table parsed, before the script calling the function is
704 * run. run_digital_op_script is example of how to do such setup
705 */
706
707 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
708
7f245b20 709 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 710 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
711 "(%02X)\n", dcb_entry);
712 dcb_entry = 0x7f; /* unused / invalid marker */
713 }
714
715 return dcb_entry;
716}
717
718static struct nouveau_i2c_chan *
719init_i2c_device_find(struct drm_device *dev, int i2c_index)
720{
721 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 722 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 723
724 if (i2c_index == 0xff) {
725 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
726 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 727 int default_indices = dcb->i2c_default_indices;
6ee73861 728
7f245b20 729 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 730 shift = 4;
731
732 i2c_index = (default_indices >> shift) & 0xf;
733 }
734 if (i2c_index == 0x80) /* g80+ */
7f245b20 735 i2c_index = dcb->i2c_default_indices & 0xf;
6ee73861
BS		 736
737 return nouveau_i2c_find(dev, i2c_index);
738}
739
7f245b20
BS		 740static uint32_t
741get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 742{
743 /*
744 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
745 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
746 * CR58 for CR57 = 0 to index a table of offsets to the basic
747 * 0x6808b0 address.
748 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
749 * CR58 for CR57 = 0 to index a table of offsets to the basic
750 * 0x6808b0 address, and then flip the offset by 8.
751 */
752
753 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 754 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 755 const int pramdac_offset[13] = {
756 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
757 const uint32_t pramdac_table[4] = {
758 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
759
760 if (mlv >= 0x80) {
761 int dcb_entry, dacoffset;
762
763 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
764 dcb_entry = dcb_entry_idx_from_crtchead(dev);
765 if (dcb_entry == 0x7f)
766 return 0;
7f245b20 767 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 768 if (mlv == 0x81)
769 dacoffset ^= 8;
770 return 0x6808b0 + dacoffset;
771 } else {
df31ef4d 772 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 773 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
774 mlv);
775 return 0;
776 }
777 return pramdac_table[mlv];
778 }
779}
780
37383650 781static int
6ee73861
BS		 782init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
783 struct init_exec *iexec)
784{
785 /*
786 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
787 *
788 * offset (8 bit): opcode
789 * offset + 1 (16 bit): CRTC port
790 * offset + 3 (8 bit): CRTC index
791 * offset + 4 (8 bit): mask
792 * offset + 5 (8 bit): shift
793 * offset + 6 (8 bit): count
794 * offset + 7 (32 bit): register
795 * offset + 11 (32 bit): configuration 1
796 * ...
797 *
798 * Starting at offset + 11 there are "count" 32 bit values.
799 * To find out which value to use read index "CRTC index" on "CRTC
800 * port", AND this value with "mask" and then bit shift right "shift"
801 * bits. Read the appropriate value using this index and write to
802 * "register"
803 */
804
805 uint16_t crtcport = ROM16(bios->data[offset + 1]);
806 uint8_t crtcindex = bios->data[offset + 3];
807 uint8_t mask = bios->data[offset + 4];
808 uint8_t shift = bios->data[offset + 5];
809 uint8_t count = bios->data[offset + 6];
810 uint32_t reg = ROM32(bios->data[offset + 7]);
811 uint8_t config;
812 uint32_t configval;
37383650 813 int len = 11 + count * 4;
6ee73861
BS		 814
815 if (!iexec->execute)
37383650 816 return len;
6ee73861
BS		 817
818 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
819 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
820 offset, crtcport, crtcindex, mask, shift, count, reg);
821
822 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
823 if (config > count) {
824 NV_ERROR(bios->dev,
825 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
826 offset, config, count);
9170a824 827 return -EINVAL;
6ee73861
BS		 828 }
829
830 configval = ROM32(bios->data[offset + 11 + config * 4]);
831
832 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
833
834 bios_wr32(bios, reg, configval);
835
37383650 836 return len;
6ee73861
BS		 837}
838
37383650 839static int
6ee73861
BS		 840init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
841{
842 /*
843 * INIT_REPEAT opcode: 0x33 ('3')
844 *
845 * offset (8 bit): opcode
846 * offset + 1 (8 bit): count
847 *
848 * Execute script following this opcode up to INIT_REPEAT_END
849 * "count" times
850 */
851
852 uint8_t count = bios->data[offset + 1];
853 uint8_t i;
854
855 /* no iexec->execute check by design */
856
857 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
858 offset, count);
859
860 iexec->repeat = true;
861
862 /*
863 * count - 1, as the script block will execute once when we leave this
864 * opcode -- this is compatible with bios behaviour as:
865 * a) the block is always executed at least once, even if count == 0
866 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
867 * while we don't
868 */
869 for (i = 0; i < count - 1; i++)
870 parse_init_table(bios, offset + 2, iexec);
871
872 iexec->repeat = false;
873
37383650 874 return 2;
6ee73861
BS		 875}
876
37383650 877static int
6ee73861
BS		 878init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
879 struct init_exec *iexec)
880{
881 /*
882 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
883 *
884 * offset (8 bit): opcode
885 * offset + 1 (16 bit): CRTC port
886 * offset + 3 (8 bit): CRTC index
887 * offset + 4 (8 bit): mask
888 * offset + 5 (8 bit): shift
889 * offset + 6 (8 bit): IO flag condition index
890 * offset + 7 (8 bit): count
891 * offset + 8 (32 bit): register
892 * offset + 12 (16 bit): frequency 1
893 * ...
894 *
895 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
896 * Set PLL register "register" to coefficients for frequency n,
897 * selected by reading index "CRTC index" of "CRTC port" ANDed with
898 * "mask" and shifted right by "shift".
899 *
900 * If "IO flag condition index" > 0, and condition met, double
901 * frequency before setting it.
902 */
903
904 uint16_t crtcport = ROM16(bios->data[offset + 1]);
905 uint8_t crtcindex = bios->data[offset + 3];
906 uint8_t mask = bios->data[offset + 4];
907 uint8_t shift = bios->data[offset + 5];
908 int8_t io_flag_condition_idx = bios->data[offset + 6];
909 uint8_t count = bios->data[offset + 7];
910 uint32_t reg = ROM32(bios->data[offset + 8]);
911 uint8_t config;
912 uint16_t freq;
37383650 913 int len = 12 + count * 2;
6ee73861
BS		 914
915 if (!iexec->execute)
37383650 916 return len;
6ee73861
BS		 917
918 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
919 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
920 "Count: 0x%02X, Reg: 0x%08X\n",
921 offset, crtcport, crtcindex, mask, shift,
922 io_flag_condition_idx, count, reg);
923
924 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
925 if (config > count) {
926 NV_ERROR(bios->dev,
927 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
928 offset, config, count);
9170a824 929 return -EINVAL;
6ee73861
BS		 930 }
931
932 freq = ROM16(bios->data[offset + 12 + config * 2]);
933
934 if (io_flag_condition_idx > 0) {
935 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
936 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
937 "frequency doubled\n", offset);
938 freq *= 2;
939 } else
940 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
941 "frequency unchanged\n", offset);
942 }
943
944 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
945 offset, reg, config, freq);
946
947 setPLL(bios, reg, freq * 10);
948
37383650 949 return len;
6ee73861
BS		 950}
951
37383650 952static int
6ee73861
BS		 953init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
954{
955 /*
956 * INIT_END_REPEAT opcode: 0x36 ('6')
957 *
958 * offset (8 bit): opcode
959 *
960 * Marks the end of the block for INIT_REPEAT to repeat
961 */
962
963 /* no iexec->execute check by design */
964
965 /*
966 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
967 * we're not in repeat mode
968 */
969 if (iexec->repeat)
37383650 970 return 0;
6ee73861 971
37383650 972 return 1;
6ee73861
BS		 973}
974
37383650 975static int
6ee73861
BS		 976init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
977{
978 /*
979 * INIT_COPY opcode: 0x37 ('7')
980 *
981 * offset (8 bit): opcode
982 * offset + 1 (32 bit): register
983 * offset + 5 (8 bit): shift
984 * offset + 6 (8 bit): srcmask
985 * offset + 7 (16 bit): CRTC port
986 * offset + 9 (8 bit): CRTC index
987 * offset + 10 (8 bit): mask
988 *
989 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
990 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
991 * port
992 */
993
994 uint32_t reg = ROM32(bios->data[offset + 1]);
995 uint8_t shift = bios->data[offset + 5];
996 uint8_t srcmask = bios->data[offset + 6];
997 uint16_t crtcport = ROM16(bios->data[offset + 7]);
998 uint8_t crtcindex = bios->data[offset + 9];
999 uint8_t mask = bios->data[offset + 10];
1000 uint32_t data;
1001 uint8_t crtcdata;
1002
1003 if (!iexec->execute)
37383650 1004 return 11;
6ee73861
BS		 1005
1006 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1007 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1008 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1009
1010 data = bios_rd32(bios, reg);
1011
1012 if (shift < 0x80)
1013 data >>= shift;
1014 else
1015 data <<= (0x100 - shift);
1016
1017 data &= srcmask;
1018
1019 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1020 crtcdata |= (uint8_t)data;
1021 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1022
37383650 1023 return 11;
6ee73861
BS		 1024}
1025
37383650 1026static int
6ee73861
BS		 1027init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1028{
1029 /*
1030 * INIT_NOT opcode: 0x38 ('8')
1031 *
1032 * offset (8 bit): opcode
1033 *
1034 * Invert the current execute / no-execute condition (i.e. "else")
1035 */
1036 if (iexec->execute)
1037 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1038 else
1039 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1040
1041 iexec->execute = !iexec->execute;
37383650 1042 return 1;
6ee73861
BS		 1043}
1044
37383650 1045static int
6ee73861
BS		 1046init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1047 struct init_exec *iexec)
1048{
1049 /*
1050 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1051 *
1052 * offset (8 bit): opcode
1053 * offset + 1 (8 bit): condition number
1054 *
1055 * Check condition "condition number" in the IO flag condition table.
1056 * If condition not met skip subsequent opcodes until condition is
1057 * inverted (INIT_NOT), or we hit INIT_RESUME
1058 */
1059
1060 uint8_t cond = bios->data[offset + 1];
1061
1062 if (!iexec->execute)
37383650 1063 return 2;
6ee73861
BS		 1064
1065 if (io_flag_condition_met(bios, offset, cond))
1066 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1067 else {
1068 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1069 iexec->execute = false;
1070 }
1071
37383650 1072 return 2;
6ee73861
BS		 1073}
1074
25908b77
BS		 1075static int
1076init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1077{
1078 /*
1079 * INIT_DP_CONDITION opcode: 0x3A ('')
1080 *
1081 * offset (8 bit): opcode
1082 * offset + 1 (8 bit): "sub" opcode
1083 * offset + 2 (8 bit): unknown
1084 *
1085 */
1086
1087 struct bit_displayport_encoder_table *dpe = NULL;
1088 struct dcb_entry *dcb = bios->display.output;
1089 struct drm_device *dev = bios->dev;
1090 uint8_t cond = bios->data[offset + 1];
1091 int dummy;
1092
1093 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1094
1095 if (!iexec->execute)
1096 return 3;
1097
1098 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1099 if (!dpe) {
1100 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
1101 return -EINVAL;
1102 }
1103
1104 switch (cond) {
1105 case 0:
1106 {
1107 struct dcb_connector_table_entry *ent =
1108 &bios->dcb.connector.entry[dcb->connector];
1109
1110 if (ent->type != DCB_CONNECTOR_eDP)
1111 iexec->execute = false;
1112 }
1113 break;
1114 case 1:
1115 case 2:
1116 if (!(dpe->unknown & cond))
1117 iexec->execute = false;
1118 break;
1119 case 5:
1120 {
1121 struct nouveau_i2c_chan *auxch;
1122 int ret;
1123
1124 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1125 if (!auxch)
1126 return -ENODEV;
1127
1128 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1129 if (ret)
1130 return ret;
1131
1132 if (cond & 1)
1133 iexec->execute = false;
1134 }
1135 break;
1136 default:
1137 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1138 break;
1139 }
1140
1141 if (iexec->execute)
1142 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1143 else
1144 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1145
1146 return 3;
1147}
1148
1149static int
1150init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1151{
1152 /*
1153 * INIT_3B opcode: 0x3B ('')
1154 *
1155 * offset (8 bit): opcode
1156 * offset + 1 (8 bit): crtc index
1157 *
1158 */
1159
1160 uint8_t or = ffs(bios->display.output->or) - 1;
1161 uint8_t index = bios->data[offset + 1];
1162 uint8_t data;
1163
1164 if (!iexec->execute)
1165 return 2;
1166
1167 data = bios_idxprt_rd(bios, 0x3d4, index);
1168 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1169 return 2;
1170}
1171
1172static int
1173init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1174{
1175 /*
1176 * INIT_3C opcode: 0x3C ('')
1177 *
1178 * offset (8 bit): opcode
1179 * offset + 1 (8 bit): crtc index
1180 *
1181 */
1182
1183 uint8_t or = ffs(bios->display.output->or) - 1;
1184 uint8_t index = bios->data[offset + 1];
1185 uint8_t data;
1186
1187 if (!iexec->execute)
1188 return 2;
1189
1190 data = bios_idxprt_rd(bios, 0x3d4, index);
1191 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1192 return 2;
1193}
1194
37383650 1195static int
6ee73861
BS		 1196init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1197 struct init_exec *iexec)
1198{
1199 /*
1200 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1201 *
1202 * offset (8 bit): opcode
1203 * offset + 1 (32 bit): control register
1204 * offset + 5 (32 bit): data register
1205 * offset + 9 (32 bit): mask
1206 * offset + 13 (32 bit): data
1207 * offset + 17 (8 bit): count
1208 * offset + 18 (8 bit): address 1
1209 * offset + 19 (8 bit): data 1
1210 * ...
1211 *
1212 * For each of "count" address and data pairs, write "data n" to
1213 * "data register", read the current value of "control register",
1214 * and write it back once ANDed with "mask", ORed with "data",
1215 * and ORed with "address n"
1216 */
1217
1218 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1219 uint32_t datareg = ROM32(bios->data[offset + 5]);
1220 uint32_t mask = ROM32(bios->data[offset + 9]);
1221 uint32_t data = ROM32(bios->data[offset + 13]);
1222 uint8_t count = bios->data[offset + 17];
37383650 1223 int len = 18 + count * 2;
6ee73861
BS		 1224 uint32_t value;
1225 int i;
1226
1227 if (!iexec->execute)
37383650 1228 return len;
6ee73861
BS		 1229
1230 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1231 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1232 offset, controlreg, datareg, mask, data, count);
1233
1234 for (i = 0; i < count; i++) {
1235 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1236 uint8_t instdata = bios->data[offset + 19 + i * 2];
1237
1238 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1239 offset, instaddress, instdata);
1240
1241 bios_wr32(bios, datareg, instdata);
1242 value = bios_rd32(bios, controlreg) & mask;
1243 value |= data;
1244 value |= instaddress;
1245 bios_wr32(bios, controlreg, value);
1246 }
1247
37383650 1248 return len;
6ee73861
BS		 1249}
1250
37383650 1251static int
6ee73861
BS		 1252init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1253 struct init_exec *iexec)
1254{
1255 /*
1256 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1257 *
1258 * offset (8 bit): opcode
1259 * offset + 1 (16 bit): CRTC port
1260 * offset + 3 (8 bit): CRTC index
1261 * offset + 4 (8 bit): mask
1262 * offset + 5 (8 bit): shift
1263 * offset + 6 (8 bit): count
1264 * offset + 7 (32 bit): register
1265 * offset + 11 (32 bit): frequency 1
1266 * ...
1267 *
1268 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1269 * Set PLL register "register" to coefficients for frequency n,
1270 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1271 * "mask" and shifted right by "shift".
1272 */
1273
1274 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1275 uint8_t crtcindex = bios->data[offset + 3];
1276 uint8_t mask = bios->data[offset + 4];
1277 uint8_t shift = bios->data[offset + 5];
1278 uint8_t count = bios->data[offset + 6];
1279 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1280 int len = 11 + count * 4;
6ee73861
BS		 1281 uint8_t config;
1282 uint32_t freq;
1283
1284 if (!iexec->execute)
37383650 1285 return len;
6ee73861
BS		 1286
1287 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1288 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1289 offset, crtcport, crtcindex, mask, shift, count, reg);
1290
1291 if (!reg)
37383650 1292 return len;
6ee73861
BS		 1293
1294 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1295 if (config > count) {
1296 NV_ERROR(bios->dev,
1297 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1298 offset, config, count);
9170a824 1299 return -EINVAL;
6ee73861
BS		 1300 }
1301
1302 freq = ROM32(bios->data[offset + 11 + config * 4]);
1303
1304 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1305 offset, reg, config, freq);
1306
1307 setPLL(bios, reg, freq);
1308
37383650 1309 return len;
6ee73861
BS		 1310}
1311
37383650 1312static int
6ee73861
BS		 1313init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1314{
1315 /*
1316 * INIT_PLL2 opcode: 0x4B ('K')
1317 *
1318 * offset (8 bit): opcode
1319 * offset + 1 (32 bit): register
1320 * offset + 5 (32 bit): freq
1321 *
1322 * Set PLL register "register" to coefficients for frequency "freq"
1323 */
1324
1325 uint32_t reg = ROM32(bios->data[offset + 1]);
1326 uint32_t freq = ROM32(bios->data[offset + 5]);
1327
1328 if (!iexec->execute)
37383650 1329 return 9;
6ee73861
BS		 1330
1331 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1332 offset, reg, freq);
1333
1334 setPLL(bios, reg, freq);
37383650 1335 return 9;
6ee73861
BS		 1336}
1337
37383650 1338static int
6ee73861
BS		 1339init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1340{
1341 /*
1342 * INIT_I2C_BYTE opcode: 0x4C ('L')
1343 *
1344 * offset (8 bit): opcode
1345 * offset + 1 (8 bit): DCB I2C table entry index
1346 * offset + 2 (8 bit): I2C slave address
1347 * offset + 3 (8 bit): count
1348 * offset + 4 (8 bit): I2C register 1
1349 * offset + 5 (8 bit): mask 1
1350 * offset + 6 (8 bit): data 1
1351 * ...
1352 *
1353 * For each of "count" registers given by "I2C register n" on the device
1354 * addressed by "I2C slave address" on the I2C bus given by
1355 * "DCB I2C table entry index", read the register, AND the result with
1356 * "mask n" and OR it with "data n" before writing it back to the device
1357 */
1358
1359 uint8_t i2c_index = bios->data[offset + 1];
1360 uint8_t i2c_address = bios->data[offset + 2];
1361 uint8_t count = bios->data[offset + 3];
37383650 1362 int len = 4 + count * 3;
6ee73861
BS		 1363 struct nouveau_i2c_chan *chan;
1364 struct i2c_msg msg;
1365 int i;
1366
1367 if (!iexec->execute)
37383650 1368 return len;
6ee73861
BS		 1369
1370 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1371 "Count: 0x%02X\n",
1372 offset, i2c_index, i2c_address, count);
1373
1374 chan = init_i2c_device_find(bios->dev, i2c_index);
1375 if (!chan)
9170a824 1376 return -ENODEV;
6ee73861
BS		 1377
1378 for (i = 0; i < count; i++) {
1379 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
1380 uint8_t mask = bios->data[offset + 5 + i * 3];
1381 uint8_t data = bios->data[offset + 6 + i * 3];
1382 uint8_t value;
1383
1384 msg.addr = i2c_address;
1385 msg.flags = I2C_M_RD;
1386 msg.len = 1;
1387 msg.buf = &value;
1388 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1389 return -EIO;
6ee73861
BS		 1390
1391 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1392 "Mask: 0x%02X, Data: 0x%02X\n",
1393 offset, i2c_reg, value, mask, data);
1394
1395 value = (value & mask) | data;
1396
1397 if (bios->execute) {
1398 msg.addr = i2c_address;
1399 msg.flags = 0;
1400 msg.len = 1;
1401 msg.buf = &value;
1402 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1403 return -EIO;
6ee73861
BS		 1404 }
1405 }
1406
37383650 1407 return len;
6ee73861
BS		 1408}
1409
37383650 1410static int
6ee73861
BS		 1411init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1412{
1413 /*
1414 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1415 *
1416 * offset (8 bit): opcode
1417 * offset + 1 (8 bit): DCB I2C table entry index
1418 * offset + 2 (8 bit): I2C slave address
1419 * offset + 3 (8 bit): count
1420 * offset + 4 (8 bit): I2C register 1
1421 * offset + 5 (8 bit): data 1
1422 * ...
1423 *
1424 * For each of "count" registers given by "I2C register n" on the device
1425 * addressed by "I2C slave address" on the I2C bus given by
1426 * "DCB I2C table entry index", set the register to "data n"
1427 */
1428
1429 uint8_t i2c_index = bios->data[offset + 1];
1430 uint8_t i2c_address = bios->data[offset + 2];
1431 uint8_t count = bios->data[offset + 3];
37383650 1432 int len = 4 + count * 2;
6ee73861
BS		 1433 struct nouveau_i2c_chan *chan;
1434 struct i2c_msg msg;
1435 int i;
1436
1437 if (!iexec->execute)
37383650 1438 return len;
6ee73861
BS		 1439
1440 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1441 "Count: 0x%02X\n",
1442 offset, i2c_index, i2c_address, count);
1443
1444 chan = init_i2c_device_find(bios->dev, i2c_index);
1445 if (!chan)
9170a824 1446 return -ENODEV;
6ee73861
BS		 1447
1448 for (i = 0; i < count; i++) {
1449 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
1450 uint8_t data = bios->data[offset + 5 + i * 2];
1451
1452 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1453 offset, i2c_reg, data);
1454
1455 if (bios->execute) {
1456 msg.addr = i2c_address;
1457 msg.flags = 0;
1458 msg.len = 1;
1459 msg.buf = &data;
1460 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1461 return -EIO;
6ee73861
BS		 1462 }
1463 }
1464
37383650 1465 return len;
6ee73861
BS		 1466}
1467
37383650 1468static int
6ee73861
BS		 1469init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1470{
1471 /*
1472 * INIT_ZM_I2C opcode: 0x4E ('N')
1473 *
1474 * offset (8 bit): opcode
1475 * offset + 1 (8 bit): DCB I2C table entry index
1476 * offset + 2 (8 bit): I2C slave address
1477 * offset + 3 (8 bit): count
1478 * offset + 4 (8 bit): data 1
1479 * ...
1480 *
1481 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1482 * address" on the I2C bus given by "DCB I2C table entry index"
1483 */
1484
1485 uint8_t i2c_index = bios->data[offset + 1];
1486 uint8_t i2c_address = bios->data[offset + 2];
1487 uint8_t count = bios->data[offset + 3];
37383650 1488 int len = 4 + count;
6ee73861
BS		 1489 struct nouveau_i2c_chan *chan;
1490 struct i2c_msg msg;
1491 uint8_t data[256];
1492 int i;
1493
1494 if (!iexec->execute)
37383650 1495 return len;
6ee73861
BS		 1496
1497 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1498 "Count: 0x%02X\n",
1499 offset, i2c_index, i2c_address, count);
1500
1501 chan = init_i2c_device_find(bios->dev, i2c_index);
1502 if (!chan)
9170a824 1503 return -ENODEV;
6ee73861
BS		 1504
1505 for (i = 0; i < count; i++) {
1506 data[i] = bios->data[offset + 4 + i];
1507
1508 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1509 }
1510
1511 if (bios->execute) {
1512 msg.addr = i2c_address;
1513 msg.flags = 0;
1514 msg.len = count;
1515 msg.buf = data;
1516 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
9170a824 1517 return -EIO;
6ee73861
BS		 1518 }
1519
37383650 1520 return len;
6ee73861
BS		 1521}
1522
37383650 1523static int
6ee73861
BS		 1524init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1525{
1526 /*
1527 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1528 *
1529 * offset (8 bit): opcode
1530 * offset + 1 (8 bit): magic lookup value
1531 * offset + 2 (8 bit): TMDS address
1532 * offset + 3 (8 bit): mask
1533 * offset + 4 (8 bit): data
1534 *
1535 * Read the data reg for TMDS address "TMDS address", AND it with mask
1536 * and OR it with data, then write it back
1537 * "magic lookup value" determines which TMDS base address register is
1538 * used -- see get_tmds_index_reg()
1539 */
1540
1541 uint8_t mlv = bios->data[offset + 1];
1542 uint32_t tmdsaddr = bios->data[offset + 2];
1543 uint8_t mask = bios->data[offset + 3];
1544 uint8_t data = bios->data[offset + 4];
1545 uint32_t reg, value;
1546
1547 if (!iexec->execute)
37383650 1548 return 5;
6ee73861
BS		 1549
1550 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1551 "Mask: 0x%02X, Data: 0x%02X\n",
1552 offset, mlv, tmdsaddr, mask, data);
1553
1554 reg = get_tmds_index_reg(bios->dev, mlv);
1555 if (!reg)
9170a824 1556 return -EINVAL;
6ee73861
BS		 1557
1558 bios_wr32(bios, reg,
1559 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1560 value = (bios_rd32(bios, reg + 4) & mask) | data;
1561 bios_wr32(bios, reg + 4, value);
1562 bios_wr32(bios, reg, tmdsaddr);
1563
37383650 1564 return 5;
6ee73861
BS		 1565}
1566
37383650 1567static int
6ee73861
BS		 1568init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1569 struct init_exec *iexec)
1570{
1571 /*
1572 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1573 *
1574 * offset (8 bit): opcode
1575 * offset + 1 (8 bit): magic lookup value
1576 * offset + 2 (8 bit): count
1577 * offset + 3 (8 bit): addr 1
1578 * offset + 4 (8 bit): data 1
1579 * ...
1580 *
1581 * For each of "count" TMDS address and data pairs write "data n" to
1582 * "addr n". "magic lookup value" determines which TMDS base address
1583 * register is used -- see get_tmds_index_reg()
1584 */
1585
1586 uint8_t mlv = bios->data[offset + 1];
1587 uint8_t count = bios->data[offset + 2];
37383650 1588 int len = 3 + count * 2;
6ee73861
BS		 1589 uint32_t reg;
1590 int i;
1591
1592 if (!iexec->execute)
37383650 1593 return len;
6ee73861
BS		 1594
1595 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1596 offset, mlv, count);
1597
1598 reg = get_tmds_index_reg(bios->dev, mlv);
1599 if (!reg)
9170a824 1600 return -EINVAL;
6ee73861
BS		 1601
1602 for (i = 0; i < count; i++) {
1603 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1604 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1605
1606 bios_wr32(bios, reg + 4, tmdsdata);
1607 bios_wr32(bios, reg, tmdsaddr);
1608 }
1609
37383650 1610 return len;
6ee73861
BS		 1611}
1612
37383650 1613static int
6ee73861
BS		 1614init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1615 struct init_exec *iexec)
1616{
1617 /*
1618 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1619 *
1620 * offset (8 bit): opcode
1621 * offset + 1 (8 bit): CRTC index1
1622 * offset + 2 (8 bit): CRTC index2
1623 * offset + 3 (8 bit): baseaddr
1624 * offset + 4 (8 bit): count
1625 * offset + 5 (8 bit): data 1
1626 * ...
1627 *
1628 * For each of "count" address and data pairs, write "baseaddr + n" to
1629 * "CRTC index1" and "data n" to "CRTC index2"
1630 * Once complete, restore initial value read from "CRTC index1"
1631 */
1632 uint8_t crtcindex1 = bios->data[offset + 1];
1633 uint8_t crtcindex2 = bios->data[offset + 2];
1634 uint8_t baseaddr = bios->data[offset + 3];
1635 uint8_t count = bios->data[offset + 4];
37383650 1636 int len = 5 + count;
6ee73861
BS		 1637 uint8_t oldaddr, data;
1638 int i;
1639
1640 if (!iexec->execute)
37383650 1641 return len;
6ee73861
BS		 1642
1643 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1644 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1645 offset, crtcindex1, crtcindex2, baseaddr, count);
1646
1647 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1648
1649 for (i = 0; i < count; i++) {
1650 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1651 baseaddr + i);
1652 data = bios->data[offset + 5 + i];
1653 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1654 }
1655
1656 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1657
37383650 1658 return len;
6ee73861
BS		 1659}
1660
37383650 1661static int
6ee73861
BS		 1662init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1663{
1664 /*
1665 * INIT_CR opcode: 0x52 ('R')
1666 *
1667 * offset (8 bit): opcode
1668 * offset + 1 (8 bit): CRTC index
1669 * offset + 2 (8 bit): mask
1670 * offset + 3 (8 bit): data
1671 *
1672 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1673 * data back to "CRTC index"
1674 */
1675
1676 uint8_t crtcindex = bios->data[offset + 1];
1677 uint8_t mask = bios->data[offset + 2];
1678 uint8_t data = bios->data[offset + 3];
1679 uint8_t value;
1680
1681 if (!iexec->execute)
37383650 1682 return 4;
6ee73861
BS		 1683
1684 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1685 offset, crtcindex, mask, data);
1686
1687 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1688 value |= data;
1689 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1690
37383650 1691 return 4;
6ee73861
BS		 1692}
1693
37383650 1694static int
6ee73861
BS		 1695init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1696{
1697 /*
1698 * INIT_ZM_CR opcode: 0x53 ('S')
1699 *
1700 * offset (8 bit): opcode
1701 * offset + 1 (8 bit): CRTC index
1702 * offset + 2 (8 bit): value
1703 *
1704 * Assign "value" to CRTC register with index "CRTC index".
1705 */
1706
1707 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1708 uint8_t data = bios->data[offset + 2];
1709
1710 if (!iexec->execute)
37383650 1711 return 3;
6ee73861
BS		 1712
1713 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1714
37383650 1715 return 3;
6ee73861
BS		 1716}
1717
37383650 1718static int
6ee73861
BS		 1719init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1720{
1721 /*
1722 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1723 *
1724 * offset (8 bit): opcode
1725 * offset + 1 (8 bit): count
1726 * offset + 2 (8 bit): CRTC index 1
1727 * offset + 3 (8 bit): value 1
1728 * ...
1729 *
1730 * For "count", assign "value n" to CRTC register with index
1731 * "CRTC index n".
1732 */
1733
1734 uint8_t count = bios->data[offset + 1];
37383650 1735 int len = 2 + count * 2;
6ee73861
BS		 1736 int i;
1737
1738 if (!iexec->execute)
37383650 1739 return len;
6ee73861
BS		 1740
1741 for (i = 0; i < count; i++)
1742 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1743
37383650 1744 return len;
6ee73861
BS		 1745}
1746
37383650 1747static int
6ee73861
BS		 1748init_condition_time(struct nvbios *bios, uint16_t offset,
1749 struct init_exec *iexec)
1750{
1751 /*
1752 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1753 *
1754 * offset (8 bit): opcode
1755 * offset + 1 (8 bit): condition number
1756 * offset + 2 (8 bit): retries / 50
1757 *
1758 * Check condition "condition number" in the condition table.
1759 * Bios code then sleeps for 2ms if the condition is not met, and
1760 * repeats up to "retries" times, but on one C51 this has proved
1761 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1762 * this, and bail after "retries" times, or 2s, whichever is less.
1763 * If still not met after retries, clear execution flag for this table.
1764 */
1765
1766 uint8_t cond = bios->data[offset + 1];
1767 uint16_t retries = bios->data[offset + 2] * 50;
1768 unsigned cnt;
1769
1770 if (!iexec->execute)
37383650 1771 return 3;
6ee73861
BS		 1772
1773 if (retries > 100)
1774 retries = 100;
1775
1776 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1777 offset, cond, retries);
1778
1779 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1780 retries = 1;
1781
1782 for (cnt = 0; cnt < retries; cnt++) {
1783 if (bios_condition_met(bios, offset, cond)) {
1784 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1785 offset);
1786 break;
1787 } else {
1788 BIOSLOG(bios, "0x%04X: "
1789 "Condition not met, sleeping for 20ms\n",
1790 offset);
1791 msleep(20);
1792 }
1793 }
1794
1795 if (!bios_condition_met(bios, offset, cond)) {
1796 NV_WARN(bios->dev,
1797 "0x%04X: Condition still not met after %dms, "
1798 "skipping following opcodes\n", offset, 20 * retries);
1799 iexec->execute = false;
1800 }
1801
37383650 1802 return 3;
6ee73861
BS		 1803}
1804
37383650 1805static int
6ee73861
BS		 1806init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1807 struct init_exec *iexec)
1808{
1809 /*
1810 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1811 *
1812 * offset (8 bit): opcode
1813 * offset + 1 (32 bit): base register
1814 * offset + 5 (8 bit): count
1815 * offset + 6 (32 bit): value 1
1816 * ...
1817 *
1818 * Starting at offset + 6 there are "count" 32 bit values.
1819 * For "count" iterations set "base register" + 4 * current_iteration
1820 * to "value current_iteration"
1821 */
1822
1823 uint32_t basereg = ROM32(bios->data[offset + 1]);
1824 uint32_t count = bios->data[offset + 5];
37383650 1825 int len = 6 + count * 4;
6ee73861
BS		 1826 int i;
1827
1828 if (!iexec->execute)
37383650 1829 return len;
6ee73861
BS		 1830
1831 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1832 offset, basereg, count);
1833
1834 for (i = 0; i < count; i++) {
1835 uint32_t reg = basereg + i * 4;
1836 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1837
1838 bios_wr32(bios, reg, data);
1839 }
1840
37383650 1841 return len;
6ee73861
BS		 1842}
1843
37383650 1844static int
6ee73861
BS		 1845init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1846{
1847 /*
1848 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1849 *
1850 * offset (8 bit): opcode
1851 * offset + 1 (16 bit): subroutine offset (in bios)
1852 *
1853 * Calls a subroutine that will execute commands until INIT_DONE
1854 * is found.
1855 */
1856
1857 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1858
1859 if (!iexec->execute)
37383650 1860 return 3;
6ee73861
BS		 1861
1862 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1863 offset, sub_offset);
1864
1865 parse_init_table(bios, sub_offset, iexec);
1866
1867 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1868
37383650 1869 return 3;
6ee73861
BS		 1870}
1871
37383650 1872static int
6ee73861
BS		 1873init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1874{
1875 /*
1876 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1877 *
1878 * offset (8 bit): opcode
1879 * offset + 1 (32 bit): src reg
1880 * offset + 5 (8 bit): shift
1881 * offset + 6 (32 bit): src mask
1882 * offset + 10 (32 bit): xor
1883 * offset + 14 (32 bit): dst reg
1884 * offset + 18 (32 bit): dst mask
1885 *
1886 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1887 * "src mask", then XOR with "xor". Write this OR'd with
1888 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1889 */
1890
1891 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1892 uint8_t shift = bios->data[offset + 5];
1893 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1894 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1895 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1896 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1897 uint32_t srcvalue, dstvalue;
1898
1899 if (!iexec->execute)
37383650 1900 return 22;
6ee73861
BS		 1901
1902 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1903 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1904 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1905
1906 srcvalue = bios_rd32(bios, srcreg);
1907
1908 if (shift < 0x80)
1909 srcvalue >>= shift;
1910 else
1911 srcvalue <<= (0x100 - shift);
1912
1913 srcvalue = (srcvalue & srcmask) ^ xor;
1914
1915 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1916
1917 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1918
37383650 1919 return 22;
6ee73861
BS		 1920}
1921
37383650 1922static int
6ee73861
BS		 1923init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1924{
1925 /*
1926 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1927 *
1928 * offset (8 bit): opcode
1929 * offset + 1 (16 bit): CRTC port
1930 * offset + 3 (8 bit): CRTC index
1931 * offset + 4 (8 bit): data
1932 *
1933 * Write "data" to index "CRTC index" of "CRTC port"
1934 */
1935 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1936 uint8_t crtcindex = bios->data[offset + 3];
1937 uint8_t data = bios->data[offset + 4];
1938
1939 if (!iexec->execute)
37383650 1940 return 5;
6ee73861
BS		 1941
1942 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1943
37383650 1944 return 5;
6ee73861
BS		 1945}
1946
37383650 1947static int
6ee73861
BS		 1948init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1949{
1950 /*
1951 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
1952 *
1953 * offset (8 bit): opcode
1954 *
1955 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1956 * that the hardware can correctly calculate how much VRAM it has
1957 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
1958 *
1959 * The implementation of this opcode in general consists of two parts:
1960 * 1) determination of the memory bus width
1961 * 2) determination of how many of the card's RAM pads have ICs attached
1962 *
1963 * 1) is done by a cunning combination of writes to offsets 0x1c and
1964 * 0x3c in the framebuffer, and seeing whether the written values are
1965 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1966 *
1967 * 2) is done by a cunning combination of writes to an offset slightly
1968 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
1969 * if the test pattern can be read back. This then affects bits 12-15 of
1970 * NV_PFB_CFG0
1971 *
1972 * In this context a "cunning combination" may include multiple reads
1973 * and writes to varying locations, often alternating the test pattern
1974 * and 0, doubtless to make sure buffers are filled, residual charges
1975 * on tracks are removed etc.
1976 *
1977 * Unfortunately, the "cunning combination"s mentioned above, and the
1978 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1979 * trace I have.
1980 *
1981 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1982 * we started was correct, and use that instead
1983 */
1984
1985 /* no iexec->execute check by design */
1986
1987 /*
1988 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
1989 * and kmmio traces of the binary driver POSTing the card show nothing
1990 * being done for this opcode. why is it still listed in the table?!
1991 */
1992
1993 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1994
e235c1f3 1995 if (dev_priv->card_type >= NV_40)
37383650 1996 return 1;
6ee73861
BS		 1997
1998 /*
1999 * On every card I've seen, this step gets done for us earlier in
2000 * the init scripts
2001 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
2002 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
2003 */
2004
2005 /*
2006 * This also has probably been done in the scripts, but an mmio trace of
2007 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
2008 */
2009 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
2010
2011 /* write back the saved configuration value */
2012 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
2013
37383650 2014 return 1;
6ee73861
BS		 2015}
2016
37383650 2017static int
6ee73861
BS		 2018init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2019{
2020 /*
2021 * INIT_RESET opcode: 0x65 ('e')
2022 *
2023 * offset (8 bit): opcode
2024 * offset + 1 (32 bit): register
2025 * offset + 5 (32 bit): value1
2026 * offset + 9 (32 bit): value2
2027 *
2028 * Assign "value1" to "register", then assign "value2" to "register"
2029 */
2030
2031 uint32_t reg = ROM32(bios->data[offset + 1]);
2032 uint32_t value1 = ROM32(bios->data[offset + 5]);
2033 uint32_t value2 = ROM32(bios->data[offset + 9]);
2034 uint32_t pci_nv_19, pci_nv_20;
2035
2036 /* no iexec->execute check by design */
2037
2038 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2039 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
2040 bios_wr32(bios, reg, value1);
2041
2042 udelay(10);
2043
2044 bios_wr32(bios, reg, value2);
2045 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2046
2047 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2048 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2049 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2050
37383650 2051 return 13;
6ee73861
BS		 2052}
2053
37383650 2054static int
6ee73861
BS		 2055init_configure_mem(struct nvbios *bios, uint16_t offset,
2056 struct init_exec *iexec)
2057{
2058 /*
2059 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2060 *
2061 * offset (8 bit): opcode
2062 *
2063 * Equivalent to INIT_DONE on bios version 3 or greater.
2064 * For early bios versions, sets up the memory registers, using values
2065 * taken from the memory init table
2066 */
2067
2068 /* no iexec->execute check by design */
2069
2070 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2071 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2072 uint32_t reg, data;
2073
2074 if (bios->major_version > 2)
9170a824 2075 return -ENODEV;
6ee73861
BS		 2076
2077 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2078 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2079
2080 if (bios->data[meminitoffs] & 1)
2081 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2082
2083 for (reg = ROM32(bios->data[seqtbloffs]);
2084 reg != 0xffffffff;
2085 reg = ROM32(bios->data[seqtbloffs += 4])) {
2086
2087 switch (reg) {
2088 case NV_PFB_PRE:
2089 data = NV_PFB_PRE_CMD_PRECHARGE;
2090 break;
2091 case NV_PFB_PAD:
2092 data = NV_PFB_PAD_CKE_NORMAL;
2093 break;
2094 case NV_PFB_REF:
2095 data = NV_PFB_REF_CMD_REFRESH;
2096 break;
2097 default:
2098 data = ROM32(bios->data[meminitdata]);
2099 meminitdata += 4;
2100 if (data == 0xffffffff)
2101 continue;
2102 }
2103
2104 bios_wr32(bios, reg, data);
2105 }
2106
37383650 2107 return 1;
6ee73861
BS		 2108}
2109
37383650 2110static int
6ee73861
BS		 2111init_configure_clk(struct nvbios *bios, uint16_t offset,
2112 struct init_exec *iexec)
2113{
2114 /*
2115 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2116 *
2117 * offset (8 bit): opcode
2118 *
2119 * Equivalent to INIT_DONE on bios version 3 or greater.
2120 * For early bios versions, sets up the NVClk and MClk PLLs, using
2121 * values taken from the memory init table
2122 */
2123
2124 /* no iexec->execute check by design */
2125
2126 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2127 int clock;
2128
2129 if (bios->major_version > 2)
9170a824 2130 return -ENODEV;
6ee73861
BS		 2131
2132 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2133 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2134
2135 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2136 if (bios->data[meminitoffs] & 1) /* DDR */
2137 clock *= 2;
2138 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2139
37383650 2140 return 1;
6ee73861
BS		 2141}
2142
37383650 2143static int
6ee73861
BS		 2144init_configure_preinit(struct nvbios *bios, uint16_t offset,
2145 struct init_exec *iexec)
2146{
2147 /*
2148 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2149 *
2150 * offset (8 bit): opcode
2151 *
2152 * Equivalent to INIT_DONE on bios version 3 or greater.
2153 * For early bios versions, does early init, loading ram and crystal
2154 * configuration from straps into CR3C
2155 */
2156
2157 /* no iexec->execute check by design */
2158
2159 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2160 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2161
2162 if (bios->major_version > 2)
9170a824 2163 return -ENODEV;
6ee73861
BS		 2164
2165 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2166 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2167
37383650 2168 return 1;
6ee73861
BS		 2169}
2170
37383650 2171static int
6ee73861
BS		 2172init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2173{
2174 /*
2175 * INIT_IO opcode: 0x69 ('i')
2176 *
2177 * offset (8 bit): opcode
2178 * offset + 1 (16 bit): CRTC port
2179 * offset + 3 (8 bit): mask
2180 * offset + 4 (8 bit): data
2181 *
2182 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2183 */
2184
2185 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2186 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2187 uint8_t mask = bios->data[offset + 3];
2188 uint8_t data = bios->data[offset + 4];
2189
2190 if (!iexec->execute)
37383650 2191 return 5;
6ee73861
BS		 2192
2193 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2194 offset, crtcport, mask, data);
2195
2196 /*
2197 * I have no idea what this does, but NVIDIA do this magic sequence
2198 * in the places where this INIT_IO happens..
2199 */
2200 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2201 int i;
2202
2203 bios_wr32(bios, 0x614100, (bios_rd32(
2204 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2205
2206 bios_wr32(bios, 0x00e18c, bios_rd32(
2207 bios, 0x00e18c) | 0x00020000);
2208
2209 bios_wr32(bios, 0x614900, (bios_rd32(
2210 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2211
2212 bios_wr32(bios, 0x000200, bios_rd32(
2213 bios, 0x000200) & ~0x40000000);
2214
2215 mdelay(10);
2216
2217 bios_wr32(bios, 0x00e18c, bios_rd32(
2218 bios, 0x00e18c) & ~0x00020000);
2219
2220 bios_wr32(bios, 0x000200, bios_rd32(
2221 bios, 0x000200) | 0x40000000);
2222
2223 bios_wr32(bios, 0x614100, 0x00800018);
2224 bios_wr32(bios, 0x614900, 0x00800018);
2225
2226 mdelay(10);
2227
2228 bios_wr32(bios, 0x614100, 0x10000018);
2229 bios_wr32(bios, 0x614900, 0x10000018);
2230
2231 for (i = 0; i < 3; i++)
2232 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2233 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2234
2235 for (i = 0; i < 2; i++)
2236 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2237 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2238
2239 for (i = 0; i < 3; i++)
2240 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2241 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2242
2243 for (i = 0; i < 2; i++)
2244 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2245 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2246
2247 for (i = 0; i < 2; i++)
2248 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2249 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2250 return 5;
6ee73861
BS		 2251 }
2252
2253 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2254 data);
37383650 2255 return 5;
6ee73861
BS		 2256}
2257
37383650 2258static int
6ee73861
BS		 2259init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2260{
2261 /*
2262 * INIT_SUB opcode: 0x6B ('k')
2263 *
2264 * offset (8 bit): opcode
2265 * offset + 1 (8 bit): script number
2266 *
2267 * Execute script number "script number", as a subroutine
2268 */
2269
2270 uint8_t sub = bios->data[offset + 1];
2271
2272 if (!iexec->execute)
37383650 2273 return 2;
6ee73861
BS		 2274
2275 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2276
2277 parse_init_table(bios,
2278 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2279 iexec);
2280
2281 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2282
37383650 2283 return 2;
6ee73861
BS		 2284}
2285
37383650 2286static int
6ee73861
BS		 2287init_ram_condition(struct nvbios *bios, uint16_t offset,
2288 struct init_exec *iexec)
2289{
2290 /*
2291 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2292 *
2293 * offset (8 bit): opcode
2294 * offset + 1 (8 bit): mask
2295 * offset + 2 (8 bit): cmpval
2296 *
2297 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2298 * If condition not met skip subsequent opcodes until condition is
2299 * inverted (INIT_NOT), or we hit INIT_RESUME
2300 */
2301
2302 uint8_t mask = bios->data[offset + 1];
2303 uint8_t cmpval = bios->data[offset + 2];
2304 uint8_t data;
2305
2306 if (!iexec->execute)
37383650 2307 return 3;
6ee73861
BS		 2308
2309 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2310
2311 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2312 offset, data, cmpval);
2313
2314 if (data == cmpval)
2315 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2316 else {
2317 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2318 iexec->execute = false;
2319 }
2320
37383650 2321 return 3;
6ee73861
BS		 2322}
2323
37383650 2324static int
6ee73861
BS		 2325init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2326{
2327 /*
2328 * INIT_NV_REG opcode: 0x6E ('n')
2329 *
2330 * offset (8 bit): opcode
2331 * offset + 1 (32 bit): register
2332 * offset + 5 (32 bit): mask
2333 * offset + 9 (32 bit): data
2334 *
2335 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2336 */
2337
2338 uint32_t reg = ROM32(bios->data[offset + 1]);
2339 uint32_t mask = ROM32(bios->data[offset + 5]);
2340 uint32_t data = ROM32(bios->data[offset + 9]);
2341
2342 if (!iexec->execute)
37383650 2343 return 13;
6ee73861
BS		 2344
2345 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2346 offset, reg, mask, data);
2347
2348 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2349
37383650 2350 return 13;
6ee73861
BS		 2351}
2352
37383650 2353static int
6ee73861
BS		 2354init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2355{
2356 /*
2357 * INIT_MACRO opcode: 0x6F ('o')
2358 *
2359 * offset (8 bit): opcode
2360 * offset + 1 (8 bit): macro number
2361 *
2362 * Look up macro index "macro number" in the macro index table.
2363 * The macro index table entry has 1 byte for the index in the macro
2364 * table, and 1 byte for the number of times to repeat the macro.
2365 * The macro table entry has 4 bytes for the register address and
2366 * 4 bytes for the value to write to that register
2367 */
2368
2369 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2370 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2371 uint8_t macro_tbl_idx = bios->data[tmp];
2372 uint8_t count = bios->data[tmp + 1];
2373 uint32_t reg, data;
2374 int i;
2375
2376 if (!iexec->execute)
37383650 2377 return 2;
6ee73861
BS		 2378
2379 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2380 "Count: 0x%02X\n",
2381 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2382
2383 for (i = 0; i < count; i++) {
2384 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2385
2386 reg = ROM32(bios->data[macroentryptr]);
2387 data = ROM32(bios->data[macroentryptr + 4]);
2388
2389 bios_wr32(bios, reg, data);
2390 }
2391
37383650 2392 return 2;
6ee73861
BS		 2393}
2394
37383650 2395static int
6ee73861
BS		 2396init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2397{
2398 /*
2399 * INIT_DONE opcode: 0x71 ('q')
2400 *
2401 * offset (8 bit): opcode
2402 *
2403 * End the current script
2404 */
2405
2406 /* mild retval abuse to stop parsing this table */
37383650 2407 return 0;
6ee73861
BS		 2408}
2409
37383650 2410static int
6ee73861
BS		 2411init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2412{
2413 /*
2414 * INIT_RESUME opcode: 0x72 ('r')
2415 *
2416 * offset (8 bit): opcode
2417 *
2418 * End the current execute / no-execute condition
2419 */
2420
2421 if (iexec->execute)
37383650 2422 return 1;
6ee73861
BS		 2423
2424 iexec->execute = true;
2425 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2426
37383650 2427 return 1;
6ee73861
BS		 2428}
2429
37383650 2430static int
6ee73861
BS		 2431init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2432{
2433 /*
2434 * INIT_TIME opcode: 0x74 ('t')
2435 *
2436 * offset (8 bit): opcode
2437 * offset + 1 (16 bit): time
2438 *
2439 * Sleep for "time" microseconds.
2440 */
2441
2442 unsigned time = ROM16(bios->data[offset + 1]);
2443
2444 if (!iexec->execute)
37383650 2445 return 3;
6ee73861
BS		 2446
2447 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2448 offset, time);
2449
2450 if (time < 1000)
2451 udelay(time);
2452 else
2453 msleep((time + 900) / 1000);
2454
37383650 2455 return 3;
6ee73861
BS		 2456}
2457
37383650 2458static int
6ee73861
BS		 2459init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2460{
2461 /*
2462 * INIT_CONDITION opcode: 0x75 ('u')
2463 *
2464 * offset (8 bit): opcode
2465 * offset + 1 (8 bit): condition number
2466 *
2467 * Check condition "condition number" in the condition table.
2468 * If condition not met skip subsequent opcodes until condition is
2469 * inverted (INIT_NOT), or we hit INIT_RESUME
2470 */
2471
2472 uint8_t cond = bios->data[offset + 1];
2473
2474 if (!iexec->execute)
37383650 2475 return 2;
6ee73861
BS		 2476
2477 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2478
2479 if (bios_condition_met(bios, offset, cond))
2480 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2481 else {
2482 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2483 iexec->execute = false;
2484 }
2485
37383650 2486 return 2;
6ee73861
BS		 2487}
2488
37383650 2489static int
6ee73861
BS		 2490init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2491{
2492 /*
2493 * INIT_IO_CONDITION opcode: 0x76
2494 *
2495 * offset (8 bit): opcode
2496 * offset + 1 (8 bit): condition number
2497 *
2498 * Check condition "condition number" in the io condition table.
2499 * If condition not met skip subsequent opcodes until condition is
2500 * inverted (INIT_NOT), or we hit INIT_RESUME
2501 */
2502
2503 uint8_t cond = bios->data[offset + 1];
2504
2505 if (!iexec->execute)
37383650 2506 return 2;
6ee73861
BS		 2507
2508 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2509
2510 if (io_condition_met(bios, offset, cond))
2511 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2512 else {
2513 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2514 iexec->execute = false;
2515 }
2516
37383650 2517 return 2;
6ee73861
BS		 2518}
2519
37383650 2520static int
6ee73861
BS		 2521init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2522{
2523 /*
2524 * INIT_INDEX_IO opcode: 0x78 ('x')
2525 *
2526 * offset (8 bit): opcode
2527 * offset + 1 (16 bit): CRTC port
2528 * offset + 3 (8 bit): CRTC index
2529 * offset + 4 (8 bit): mask
2530 * offset + 5 (8 bit): data
2531 *
2532 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2533 * OR with "data", write-back
2534 */
2535
2536 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2537 uint8_t crtcindex = bios->data[offset + 3];
2538 uint8_t mask = bios->data[offset + 4];
2539 uint8_t data = bios->data[offset + 5];
2540 uint8_t value;
2541
2542 if (!iexec->execute)
37383650 2543 return 6;
6ee73861
BS		 2544
2545 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2546 "Data: 0x%02X\n",
2547 offset, crtcport, crtcindex, mask, data);
2548
2549 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2550 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2551
37383650 2552 return 6;
6ee73861
BS		 2553}
2554
37383650 2555static int
6ee73861
BS		 2556init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2557{
2558 /*
2559 * INIT_PLL opcode: 0x79 ('y')
2560 *
2561 * offset (8 bit): opcode
2562 * offset + 1 (32 bit): register
2563 * offset + 5 (16 bit): freq
2564 *
2565 * Set PLL register "register" to coefficients for frequency (10kHz)
2566 * "freq"
2567 */
2568
2569 uint32_t reg = ROM32(bios->data[offset + 1]);
2570 uint16_t freq = ROM16(bios->data[offset + 5]);
2571
2572 if (!iexec->execute)
37383650 2573 return 7;
6ee73861
BS		 2574
2575 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2576
2577 setPLL(bios, reg, freq * 10);
2578
37383650 2579 return 7;
6ee73861
BS		 2580}
2581
37383650 2582static int
6ee73861
BS		 2583init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2584{
2585 /*
2586 * INIT_ZM_REG opcode: 0x7A ('z')
2587 *
2588 * offset (8 bit): opcode
2589 * offset + 1 (32 bit): register
2590 * offset + 5 (32 bit): value
2591 *
2592 * Assign "value" to "register"
2593 */
2594
2595 uint32_t reg = ROM32(bios->data[offset + 1]);
2596 uint32_t value = ROM32(bios->data[offset + 5]);
2597
2598 if (!iexec->execute)
37383650 2599 return 9;
6ee73861
BS		 2600
2601 if (reg == 0x000200)
2602 value |= 1;
2603
2604 bios_wr32(bios, reg, value);
2605
37383650 2606 return 9;
6ee73861
BS		 2607}
2608
37383650 2609static int
6ee73861
BS		 2610init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2611 struct init_exec *iexec)
2612{
2613 /*
2614 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2615 *
2616 * offset (8 bit): opcode
2617 * offset + 1 (8 bit): PLL type
2618 * offset + 2 (32 bit): frequency 0
2619 *
2620 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2621 * ram_restrict_table_ptr. The value read from there is used to select
2622 * a frequency from the table starting at 'frequency 0' to be
2623 * programmed into the PLL corresponding to 'type'.
2624 *
2625 * The PLL limits table on cards using this opcode has a mapping of
2626 * 'type' to the relevant registers.
2627 */
2628
2629 struct drm_device *dev = bios->dev;
2630 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2631 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2632 uint8_t type = bios->data[offset + 1];
2633 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2634 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 2635 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 2636 int i;
2637
2638 if (!iexec->execute)
37383650 2639 return len;
6ee73861
BS		 2640
2641 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2642 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 2643 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 2644 }
2645
2646 entry = pll_limits + pll_limits[1];
2647 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2648 if (entry[0] == type) {
2649 uint32_t reg = ROM32(entry[3]);
2650
2651 BIOSLOG(bios, "0x%04X: "
2652 "Type %02x Reg 0x%08x Freq %dKHz\n",
2653 offset, type, reg, freq);
2654
2655 setPLL(bios, reg, freq);
37383650 2656 return len;
6ee73861
BS		 2657 }
2658 }
2659
2660 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 2661 return len;
6ee73861
BS		 2662}
2663
37383650 2664static int
6ee73861
BS		 2665init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2666{
2667 /*
2668 * INIT_8C opcode: 0x8C ('')
2669 *
2670 * NOP so far....
2671 *
2672 */
2673
37383650 2674 return 1;
6ee73861
BS		 2675}
2676
37383650 2677static int
6ee73861
BS		 2678init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2679{
2680 /*
2681 * INIT_8D opcode: 0x8D ('')
2682 *
2683 * NOP so far....
2684 *
2685 */
2686
37383650 2687 return 1;
6ee73861
BS		 2688}
2689
37383650 2690static int
6ee73861
BS		 2691init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2692{
2693 /*
2694 * INIT_GPIO opcode: 0x8E ('')
2695 *
2696 * offset (8 bit): opcode
2697 *
2698 * Loop over all entries in the DCB GPIO table, and initialise
2699 * each GPIO according to various values listed in each entry
2700 */
2701
2535d71c 2702 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
6ee73861 2703 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
6ee73861
BS		 2704 int i;
2705
2535d71c
BS		 2706 if (dev_priv->card_type != NV_50) {
2707 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
2708 return -ENODEV;
6ee73861
BS		 2709 }
2710
2535d71c
BS		 2711 if (!iexec->execute)
2712 return 1;
6ee73861 2713
2535d71c
BS		 2714 for (i = 0; i < bios->dcb.gpio.entries; i++) {
2715 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
2716 uint32_t r, s, v;
6ee73861 2717
2535d71c 2718 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 2719
45284162 2720 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default);
6ee73861 2721
45284162
BS		 2722 /* The NVIDIA binary driver doesn't appear to actually do
2723 * any of this, my VBIOS does however.
2724 */
2725 /* Not a clue, needs de-magicing */
2535d71c
BS		 2726 r = nv50_gpio_ctl[gpio->line >> 4];
2727 s = (gpio->line & 0x0f);
6ee73861 2728 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2535d71c 2729 switch ((gpio->entry & 0x06000000) >> 25) {
6ee73861
BS		 2730 case 1:
2731 v |= (0x00000001 << s);
2732 break;
2733 case 2:
2734 v |= (0x00010000 << s);
2735 break;
2736 default:
2737 break;
2738 }
2739 bios_wr32(bios, r, v);
2740 }
2741
37383650 2742 return 1;
6ee73861
BS		 2743}
2744
37383650 2745static int
6ee73861
BS		 2746init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2747 struct init_exec *iexec)
2748{
2749 /*
2750 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2751 *
2752 * offset (8 bit): opcode
2753 * offset + 1 (32 bit): reg
2754 * offset + 5 (8 bit): regincrement
2755 * offset + 6 (8 bit): count
2756 * offset + 7 (32 bit): value 1,1
2757 * ...
2758 *
2759 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2760 * ram_restrict_table_ptr. The value read from here is 'n', and
2761 * "value 1,n" gets written to "reg". This repeats "count" times and on
2762 * each iteration 'm', "reg" increases by "regincrement" and
2763 * "value m,n" is used. The extent of n is limited by a number read
2764 * from the 'M' BIT table, herein called "blocklen"
2765 */
2766
2767 uint32_t reg = ROM32(bios->data[offset + 1]);
2768 uint8_t regincrement = bios->data[offset + 5];
2769 uint8_t count = bios->data[offset + 6];
2770 uint32_t strap_ramcfg, data;
37383650
MK		 2771 /* previously set by 'M' BIT table */
2772 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2773 int len = 7 + count * blocklen;
6ee73861
BS		 2774 uint8_t index;
2775 int i;
2776
6ee73861
BS		 2777
2778 if (!iexec->execute)
37383650 2779 return len;
6ee73861
BS		 2780
2781 if (!blocklen) {
2782 NV_ERROR(bios->dev,
2783 "0x%04X: Zero block length - has the M table "
2784 "been parsed?\n", offset);
9170a824 2785 return -EINVAL;
6ee73861
BS		 2786 }
2787
2788 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2789 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2790
2791 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2792 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2793 offset, reg, regincrement, count, strap_ramcfg, index);
2794
2795 for (i = 0; i < count; i++) {
2796 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2797
2798 bios_wr32(bios, reg, data);
2799
2800 reg += regincrement;
2801 }
2802
37383650 2803 return len;
6ee73861
BS		 2804}
2805
37383650 2806static int
6ee73861
BS		 2807init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2808{
2809 /*
2810 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2811 *
2812 * offset (8 bit): opcode
2813 * offset + 1 (32 bit): src reg
2814 * offset + 5 (32 bit): dst reg
2815 *
2816 * Put contents of "src reg" into "dst reg"
2817 */
2818
2819 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2820 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2821
2822 if (!iexec->execute)
37383650 2823 return 9;
6ee73861
BS		 2824
2825 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2826
37383650 2827 return 9;
6ee73861
BS		 2828}
2829
37383650 2830static int
6ee73861
BS		 2831init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2832 struct init_exec *iexec)
2833{
2834 /*
2835 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2836 *
2837 * offset (8 bit): opcode
2838 * offset + 1 (32 bit): dst reg
2839 * offset + 5 (8 bit): count
2840 * offset + 6 (32 bit): data 1
2841 * ...
2842 *
2843 * For each of "count" values write "data n" to "dst reg"
2844 */
2845
2846 uint32_t reg = ROM32(bios->data[offset + 1]);
2847 uint8_t count = bios->data[offset + 5];
37383650 2848 int len = 6 + count * 4;
6ee73861
BS		 2849 int i;
2850
2851 if (!iexec->execute)
37383650 2852 return len;
6ee73861
BS		 2853
2854 for (i = 0; i < count; i++) {
2855 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2856 bios_wr32(bios, reg, data);
2857 }
2858
37383650 2859 return len;
6ee73861
BS		 2860}
2861
37383650 2862static int
6ee73861
BS		 2863init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2864{
2865 /*
2866 * INIT_RESERVED opcode: 0x92 ('')
2867 *
2868 * offset (8 bit): opcode
2869 *
2870 * Seemingly does nothing
2871 */
2872
37383650 2873 return 1;
6ee73861
BS		 2874}
2875
37383650 2876static int
6ee73861
BS		 2877init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2878{
2879 /*
2880 * INIT_96 opcode: 0x96 ('')
2881 *
2882 * offset (8 bit): opcode
2883 * offset + 1 (32 bit): sreg
2884 * offset + 5 (8 bit): sshift
2885 * offset + 6 (8 bit): smask
2886 * offset + 7 (8 bit): index
2887 * offset + 8 (32 bit): reg
2888 * offset + 12 (32 bit): mask
2889 * offset + 16 (8 bit): shift
2890 *
2891 */
2892
2893 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2894 uint32_t reg = ROM32(bios->data[offset + 8]);
2895 uint32_t mask = ROM32(bios->data[offset + 12]);
2896 uint32_t val;
2897
2898 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2899 if (bios->data[offset + 5] < 0x80)
2900 val >>= bios->data[offset + 5];
2901 else
2902 val <<= (0x100 - bios->data[offset + 5]);
2903 val &= bios->data[offset + 6];
2904
2905 val = bios->data[ROM16(bios->data[xlatptr]) + val];
2906 val <<= bios->data[offset + 16];
2907
2908 if (!iexec->execute)
37383650 2909 return 17;
6ee73861
BS		 2910
2911 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 2912 return 17;
6ee73861
BS		 2913}
2914
37383650 2915static int
6ee73861
BS		 2916init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2917{
2918 /*
2919 * INIT_97 opcode: 0x97 ('')
2920 *
2921 * offset (8 bit): opcode
2922 * offset + 1 (32 bit): register
2923 * offset + 5 (32 bit): mask
2924 * offset + 9 (32 bit): value
2925 *
2926 * Adds "value" to "register" preserving the fields specified
2927 * by "mask"
2928 */
2929
2930 uint32_t reg = ROM32(bios->data[offset + 1]);
2931 uint32_t mask = ROM32(bios->data[offset + 5]);
2932 uint32_t add = ROM32(bios->data[offset + 9]);
2933 uint32_t val;
2934
2935 val = bios_rd32(bios, reg);
2936 val = (val & mask) | ((val + add) & ~mask);
2937
2938 if (!iexec->execute)
37383650 2939 return 13;
6ee73861
BS		 2940
2941 bios_wr32(bios, reg, val);
37383650 2942 return 13;
6ee73861
BS		 2943}
2944
37383650 2945static int
6ee73861
BS		 2946init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2947{
2948 /*
2949 * INIT_AUXCH opcode: 0x98 ('')
2950 *
2951 * offset (8 bit): opcode
2952 * offset + 1 (32 bit): address
2953 * offset + 5 (8 bit): count
2954 * offset + 6 (8 bit): mask 0
2955 * offset + 7 (8 bit): data 0
2956 * ...
2957 *
2958 */
2959
2960 struct drm_device *dev = bios->dev;
2961 struct nouveau_i2c_chan *auxch;
2962 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 2963 uint8_t count = bios->data[offset + 5];
2964 int len = 6 + count * 2;
6ee73861
BS		 2965 int ret, i;
2966
2967 if (!bios->display.output) {
2968 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
9170a824 2969 return -EINVAL;
6ee73861
BS		 2970 }
2971
2972 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2973 if (!auxch) {
2974 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
2975 bios->display.output->i2c_index);
9170a824 2976 return -ENODEV;
6ee73861
BS		 2977 }
2978
2979 if (!iexec->execute)
37383650 2980 return len;
6ee73861
BS		 2981
2982 offset += 6;
37383650 2983 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 2984 uint8_t data;
2985
2986 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
2987 if (ret) {
2988 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
9170a824 2989 return ret;
6ee73861
BS		 2990 }
2991
2992 data &= bios->data[offset + 0];
2993 data |= bios->data[offset + 1];
2994
2995 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
2996 if (ret) {
2997 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
9170a824 2998 return ret;
6ee73861
BS		 2999 }
3000 }
3001
37383650 3002 return len;
6ee73861
BS		 3003}
3004
37383650 3005static int
6ee73861
BS		 3006init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3007{
3008 /*
3009 * INIT_ZM_AUXCH opcode: 0x99 ('')
3010 *
3011 * offset (8 bit): opcode
3012 * offset + 1 (32 bit): address
3013 * offset + 5 (8 bit): count
3014 * offset + 6 (8 bit): data 0
3015 * ...
3016 *
3017 */
3018
3019 struct drm_device *dev = bios->dev;
3020 struct nouveau_i2c_chan *auxch;
3021 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3022 uint8_t count = bios->data[offset + 5];
3023 int len = 6 + count;
6ee73861
BS		 3024 int ret, i;
3025
3026 if (!bios->display.output) {
3027 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
9170a824 3028 return -EINVAL;
6ee73861
BS		 3029 }
3030
3031 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3032 if (!auxch) {
3033 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3034 bios->display.output->i2c_index);
9170a824 3035 return -ENODEV;
6ee73861
BS		 3036 }
3037
3038 if (!iexec->execute)
37383650 3039 return len;
6ee73861
BS		 3040
3041 offset += 6;
37383650 3042 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3043 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3044 if (ret) {
3045 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
9170a824 3046 return ret;
6ee73861
BS		 3047 }
3048 }
3049
37383650 3050 return len;
6ee73861
BS		 3051}
3052
3053static struct init_tbl_entry itbl_entry[] = {
3054 /* command name , id , length , offset , mult , command handler */
3055 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3056 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3057 { "INIT_REPEAT" , 0x33, init_repeat },
3058 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3059 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3060 { "INIT_COPY" , 0x37, init_copy },
3061 { "INIT_NOT" , 0x38, init_not },
3062 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3063 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3064 { "INIT_OP_3B" , 0x3B, init_op_3b },
3065 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3066 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3067 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3068 { "INIT_PLL2" , 0x4B, init_pll2 },
3069 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3070 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3071 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3072 { "INIT_TMDS" , 0x4F, init_tmds },
3073 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3074 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3075 { "INIT_CR" , 0x52, init_cr },
3076 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3077 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3078 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3079 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3080 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 3081 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3082 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3083 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3084 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3085 { "INIT_RESET" , 0x65, init_reset },
3086 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3087 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3088 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3089 { "INIT_IO" , 0x69, init_io },
3090 { "INIT_SUB" , 0x6B, init_sub },
3091 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3092 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3093 { "INIT_MACRO" , 0x6F, init_macro },
3094 { "INIT_DONE" , 0x71, init_done },
3095 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3096 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3097 { "INIT_TIME" , 0x74, init_time },
3098 { "INIT_CONDITION" , 0x75, init_condition },
3099 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3100 { "INIT_INDEX_IO" , 0x78, init_index_io },
3101 { "INIT_PLL" , 0x79, init_pll },
3102 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3103 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3104 { "INIT_8C" , 0x8C, init_8c },
3105 { "INIT_8D" , 0x8D, init_8d },
3106 { "INIT_GPIO" , 0x8E, init_gpio },
3107 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3108 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3109 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3110 { "INIT_RESERVED" , 0x92, init_reserved },
3111 { "INIT_96" , 0x96, init_96 },
3112 { "INIT_97" , 0x97, init_97 },
3113 { "INIT_AUXCH" , 0x98, init_auxch },
3114 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3115 { NULL , 0 , NULL }
6ee73861
BS		 3116};
3117
6ee73861
BS		 3118#define MAX_TABLE_OPS 1000
3119
3120static int
3121parse_init_table(struct nvbios *bios, unsigned int offset,
3122 struct init_exec *iexec)
3123{
3124 /*
3125 * Parses all commands in an init table.
3126 *
3127 * We start out executing all commands found in the init table. Some
3128 * opcodes may change the status of iexec->execute to SKIP, which will
3129 * cause the following opcodes to perform no operation until the value
3130 * is changed back to EXECUTE.
3131 */
3132
92b96187 3133 int count = 0, i, ret;
6ee73861
BS		 3134 uint8_t id;
3135
3136 /*
3137 * Loop until INIT_DONE causes us to break out of the loop
3138 * (or until offset > bios length just in case... )
3139 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3140 */
3141 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3142 id = bios->data[offset];
3143
3144 /* Find matching id in itbl_entry */
3145 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3146 ;
3147
92b96187 3148 if (!itbl_entry[i].name) {
6ee73861
BS		 3149 NV_ERROR(bios->dev,
3150 "0x%04X: Init table command not found: "
3151 "0x%02X\n", offset, id);
3152 return -ENOENT;
3153 }
92b96187
BS		 3154
3155 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3156 itbl_entry[i].id, itbl_entry[i].name);
3157
3158 /* execute eventual command handler */
3159 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3160 if (ret < 0) {
3161 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3162 "table opcode: %s %d\n", offset,
3163 itbl_entry[i].name, ret);
3164 }
3165
3166 if (ret <= 0)
3167 break;
3168
3169 /*
3170 * Add the offset of the current command including all data
3171 * of that command. The offset will then be pointing on the
3172 * next op code.
3173 */
3174 offset += ret;
6ee73861
BS		 3175 }
3176
3177 if (offset >= bios->length)
3178 NV_WARN(bios->dev,
3179 "Offset 0x%04X greater than known bios image length. "
3180 "Corrupt image?\n", offset);
3181 if (count >= MAX_TABLE_OPS)
3182 NV_WARN(bios->dev,
3183 "More than %d opcodes to a table is unlikely, "
3184 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3185
3186 return 0;
3187}
3188
3189static void
3190parse_init_tables(struct nvbios *bios)
3191{
3192 /* Loops and calls parse_init_table() for each present table. */
3193
3194 int i = 0;
3195 uint16_t table;
3196 struct init_exec iexec = {true, false};
3197
3198 if (bios->old_style_init) {
3199 if (bios->init_script_tbls_ptr)
3200 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3201 if (bios->extra_init_script_tbl_ptr)
3202 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3203
3204 return;
3205 }
3206
3207 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3208 NV_INFO(bios->dev,
3209 "Parsing VBIOS init table %d at offset 0x%04X\n",
3210 i / 2, table);
3211 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3212
3213 parse_init_table(bios, table, &iexec);
3214 i += 2;
3215 }
3216}
3217
3218static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3219{
3220 int compare_record_len, i = 0;
3221 uint16_t compareclk, scriptptr = 0;
3222
3223 if (bios->major_version < 5) /* pre BIT */
3224 compare_record_len = 3;
3225 else
3226 compare_record_len = 4;
3227
3228 do {
3229 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3230 if (pxclk >= compareclk * 10) {
3231 if (bios->major_version < 5) {
3232 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3233 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3234 } else
3235 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3236 break;
3237 }
3238 i++;
3239 } while (compareclk);
3240
3241 return scriptptr;
3242}
3243
3244static void
3245run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3246 struct dcb_entry *dcbent, int head, bool dl)
3247{
3248 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3249 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3250 struct init_exec iexec = {true, false};
3251
3252 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3253 scriptptr);
3254 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3255 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3256 /* note: if dcb entries have been merged, index may be misleading */
3257 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3258 parse_init_table(bios, scriptptr, &iexec);
3259
3260 nv04_dfp_bind_head(dev, dcbent, head, dl);
3261}
3262
3263static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3264{
3265 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3266 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3267 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3268 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3269
3270 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3271 return -EINVAL;
3272
3273 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3274
3275 if (script == LVDS_PANEL_OFF) {
3276 /* off-on delay in ms */
3277 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3278 }
3279#ifdef __powerpc__
3280 /* Powerbook specific quirks */
3d9aefb8
FJ		 3281 if ((dev->pci_device & 0xffff) == 0x0179 ||
3282 (dev->pci_device & 0xffff) == 0x0189 ||
3283 (dev->pci_device & 0xffff) == 0x0329) {
3284 if (script == LVDS_RESET) {
3285 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3286
3287 } else if (script == LVDS_PANEL_ON) {
3288 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3289 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3290 | (1 << 31));
3291 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3292 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3293
3294 } else if (script == LVDS_PANEL_OFF) {
3295 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3296 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3297 & ~(1 << 31));
3298 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3299 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3300 }
3301 }
3302#endif
3303
3304 return 0;
3305}
3306
3307static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3308{
3309 /*
3310 * The BIT LVDS table's header has the information to setup the
3311 * necessary registers. Following the standard 4 byte header are:
3312 * A bitmask byte and a dual-link transition pxclk value for use in
3313 * selecting the init script when not using straps; 4 script pointers
3314 * for panel power, selected by output and on/off; and 8 table pointers
3315 * for panel init, the needed one determined by output, and bits in the
3316 * conf byte. These tables are similar to the TMDS tables, consisting
3317 * of a list of pxclks and script pointers.
3318 */
3319 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3320 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3321 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3322 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3323
3324 /*
3325 * For now we assume version 3.0 table - g80 support will need some
3326 * changes
3327 */
3328
3329 switch (script) {
3330 case LVDS_INIT:
3331 return -ENOSYS;
3332 case LVDS_BACKLIGHT_ON:
3333 case LVDS_PANEL_ON:
3334 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3335 break;
3336 case LVDS_BACKLIGHT_OFF:
3337 case LVDS_PANEL_OFF:
3338 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3339 break;
3340 case LVDS_RESET:
f3bbb9cc
BS		 3341 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3342 if (dcbent->or == 4)
3343 clktable += 8;
3344
6ee73861
BS		 3345 if (dcbent->lvdsconf.use_straps_for_mode) {
3346 if (bios->fp.dual_link)
f3bbb9cc
BS		 3347 clktable += 4;
3348 if (bios->fp.if_is_24bit)
3349 clktable += 2;
6ee73861
BS		 3350 } else {
3351 /* using EDID */
f3bbb9cc 3352 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3353
3354 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3355 clktable += 4;
3356 cmpval_24bit <<= 1;
6ee73861 3357 }
f3bbb9cc
BS		 3358
3359 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3360 clktable += 2;
6ee73861
BS		 3361 }
3362
f3bbb9cc 3363 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3364 if (!clktable) {
3365 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3366 return -ENOENT;
3367 }
3368 scriptptr = clkcmptable(bios, clktable, pxclk);
3369 }
3370
3371 if (!scriptptr) {
3372 NV_ERROR(dev, "LVDS output init script not found\n");
3373 return -ENOENT;
3374 }
3375 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3376
3377 return 0;
3378}
3379
3380int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3381{
3382 /*
3383 * LVDS operations are multiplexed in an effort to present a single API
3384 * which works with two vastly differing underlying structures.
3385 * This acts as the demux
3386 */
3387
3388 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3389 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3390 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3391 uint32_t sel_clk_binding, sel_clk;
3392 int ret;
3393
3394 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3395 (lvds_ver >= 0x30 && script == LVDS_INIT))
3396 return 0;
3397
3398 if (!bios->fp.lvds_init_run) {
3399 bios->fp.lvds_init_run = true;
3400 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3401 }
3402
3403 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3404 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3405 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3406 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3407
3408 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3409
3410 /* don't let script change pll->head binding */
3411 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3412
3413 if (lvds_ver < 0x30)
3414 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3415 else
3416 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3417
3418 bios->fp.last_script_invoc = (script << 1 | head);
3419
3420 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3421 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3422 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3423 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3424
3425 return ret;
3426}
3427
3428struct lvdstableheader {
3429 uint8_t lvds_ver, headerlen, recordlen;
3430};
3431
3432static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3433{
3434 /*
3435 * BMP version (0xa) LVDS table has a simple header of version and
3436 * record length. The BIT LVDS table has the typical BIT table header:
3437 * version byte, header length byte, record length byte, and a byte for
3438 * the maximum number of records that can be held in the table.
3439 */
3440
3441 uint8_t lvds_ver, headerlen, recordlen;
3442
3443 memset(lth, 0, sizeof(struct lvdstableheader));
3444
3445 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3446 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3447 return -EINVAL;
3448 }
3449
3450 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3451
3452 switch (lvds_ver) {
3453 case 0x0a: /* pre NV40 */
3454 headerlen = 2;
3455 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3456 break;
3457 case 0x30: /* NV4x */
3458 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3459 if (headerlen < 0x1f) {
3460 NV_ERROR(dev, "LVDS table header not understood\n");
3461 return -EINVAL;
3462 }
3463 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3464 break;
3465 case 0x40: /* G80/G90 */
3466 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3467 if (headerlen < 0x7) {
3468 NV_ERROR(dev, "LVDS table header not understood\n");
3469 return -EINVAL;
3470 }
3471 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3472 break;
3473 default:
3474 NV_ERROR(dev,
3475 "LVDS table revision %d.%d not currently supported\n",
3476 lvds_ver >> 4, lvds_ver & 0xf);
3477 return -ENOSYS;
3478 }
3479
3480 lth->lvds_ver = lvds_ver;
3481 lth->headerlen = headerlen;
3482 lth->recordlen = recordlen;
3483
3484 return 0;
3485}
3486
3487static int
3488get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3489{
3490 struct drm_nouveau_private *dev_priv = dev->dev_private;
3491
3492 /*
3493 * The fp strap is normally dictated by the "User Strap" in
3494 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3495 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3496 * by the PCI subsystem ID during POST, but not before the previous user
3497 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3498 * read and used instead
3499 */
3500
3501 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3502 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3503
3504 if (dev_priv->card_type >= NV_50)
3505 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3506 else
3507 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3508}
3509
3510static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3511{
3512 uint8_t *fptable;
3513 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3514 int ret, ofs, fpstrapping;
3515 struct lvdstableheader lth;
3516
3517 if (bios->fp.fptablepointer == 0x0) {
3518 /* Apple cards don't have the fp table; the laptops use DDC */
3519 /* The table is also missing on some x86 IGPs */
3520#ifndef __powerpc__
3521 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3522#endif
04a39c57 3523 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3524 return 0;
3525 }
3526
3527 fptable = &bios->data[bios->fp.fptablepointer];
3528 fptable_ver = fptable[0];
3529
3530 switch (fptable_ver) {
3531 /*
3532 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3533 * version field, and miss one of the spread spectrum/PWM bytes.
3534 * This could affect early GF2Go parts (not seen any appropriate ROMs
3535 * though). Here we assume that a version of 0x05 matches this case
3536 * (combining with a BMP version check would be better), as the
3537 * common case for the panel type field is 0x0005, and that is in
3538 * fact what we are reading the first byte of.
3539 */
3540 case 0x05: /* some NV10, 11, 15, 16 */
3541 recordlen = 42;
3542 ofs = -1;
3543 break;
3544 case 0x10: /* some NV15/16, and NV11+ */
3545 recordlen = 44;
3546 ofs = 0;
3547 break;
3548 case 0x20: /* NV40+ */
3549 headerlen = fptable[1];
3550 recordlen = fptable[2];
3551 fpentries = fptable[3];
3552 /*
3553 * fptable[4] is the minimum
3554 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3555 */
04a39c57 3556 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 3557 ofs = -7;
3558 break;
3559 default:
3560 NV_ERROR(dev,
3561 "FP table revision %d.%d not currently supported\n",
3562 fptable_ver >> 4, fptable_ver & 0xf);
3563 return -ENOSYS;
3564 }
3565
3566 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3567 return 0;
3568
3569 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3570 if (ret)
3571 return ret;
3572
3573 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3574 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3575 lth.headerlen + 1;
3576 bios->fp.xlatwidth = lth.recordlen;
3577 }
3578 if (bios->fp.fpxlatetableptr == 0x0) {
3579 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3580 return -EINVAL;
3581 }
3582
3583 fpstrapping = get_fp_strap(dev, bios);
3584
3585 fpindex = bios->data[bios->fp.fpxlatetableptr +
3586 fpstrapping * bios->fp.xlatwidth];
3587
3588 if (fpindex > fpentries) {
3589 NV_ERROR(dev, "Bad flat panel table index\n");
3590 return -ENOENT;
3591 }
3592
3593 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3594 if (lth.lvds_ver > 0x10)
04a39c57 3595 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 3596
3597 /*
3598 * If either the strap or xlated fpindex value are 0xf there is no
3599 * panel using a strap-derived bios mode present. this condition
3600 * includes, but is different from, the DDC panel indicator above
3601 */
3602 if (fpstrapping == 0xf || fpindex == 0xf)
3603 return 0;
3604
3605 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3606 recordlen * fpindex + ofs;
3607
3608 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3609 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3610 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3611 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3612
3613 return 0;
3614}
3615
3616bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3617{
3618 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3619 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3620 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3621
3622 if (!mode) /* just checking whether we can produce a mode */
3623 return bios->fp.mode_ptr;
3624
3625 memset(mode, 0, sizeof(struct drm_display_mode));
3626 /*
3627 * For version 1.0 (version in byte 0):
3628 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3629 * single/dual link, and type (TFT etc.)
3630 * bytes 3-6 are bits per colour in RGBX
3631 */
3632 mode->clock = ROM16(mode_entry[7]) * 10;
3633 /* bytes 9-10 is HActive */
3634 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3635 /*
3636 * bytes 13-14 is HValid Start
3637 * bytes 15-16 is HValid End
3638 */
3639 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3640 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3641 mode->htotal = ROM16(mode_entry[21]) + 1;
3642 /* bytes 23-24, 27-30 similarly, but vertical */
3643 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3644 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3645 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3646 mode->vtotal = ROM16(mode_entry[35]) + 1;
3647 mode->flags |= (mode_entry[37] & 0x10) ?
3648 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3649 mode->flags |= (mode_entry[37] & 0x1) ?
3650 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3651 /*
3652 * bytes 38-39 relate to spread spectrum settings
3653 * bytes 40-43 are something to do with PWM
3654 */
3655
3656 mode->status = MODE_OK;
3657 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3658 drm_mode_set_name(mode);
3659 return bios->fp.mode_ptr;
3660}
3661
3662int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3663{
3664 /*
3665 * The LVDS table header is (mostly) described in
3666 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3667 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3668 * straps are not being used for the panel, this specifies the frequency
3669 * at which modes should be set up in the dual link style.
3670 *
3671 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 3672 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 3673 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3674 * numbers for use by INIT_SUB which controlled panel init and power,
3675 * and finally a dword of ms to sleep between power off and on
3676 * operations.
3677 *
3678 * In the BIT versions, the table following the header serves as an
3679 * integrated config and xlat table: the records in the table are
3680 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3681 * two bytes - the first as a config byte, the second for indexing the
3682 * fp mode table pointed to by the BIT 'D' table
3683 *
3684 * DDC is not used until after card init, so selecting the correct table
3685 * entry and setting the dual link flag for EDID equipped panels,
3686 * requiring tests against the native-mode pixel clock, cannot be done
3687 * until later, when this function should be called with non-zero pxclk
3688 */
3689 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3690 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3691 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3692 struct lvdstableheader lth;
3693 uint16_t lvdsofs;
04a39c57 3694 int ret, chip_version = bios->chip_version;
6ee73861
BS		 3695
3696 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3697 if (ret)
3698 return ret;
3699
3700 switch (lth.lvds_ver) {
3701 case 0x0a: /* pre NV40 */
3702 lvdsmanufacturerindex = bios->data[
3703 bios->fp.fpxlatemanufacturertableptr +
3704 fpstrapping];
3705
3706 /* we're done if this isn't the EDID panel case */
3707 if (!pxclk)
3708 break;
3709
3710 if (chip_version < 0x25) {
3711 /* nv17 behaviour
3712 *
3713 * It seems the old style lvds script pointer is reused
3714 * to select 18/24 bit colour depth for EDID panels.
3715 */
3716 lvdsmanufacturerindex =
3717 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3718 2 : 0;
3719 if (pxclk >= bios->fp.duallink_transition_clk)
3720 lvdsmanufacturerindex++;
3721 } else if (chip_version < 0x30) {
3722 /* nv28 behaviour (off-chip encoder)
3723 *
3724 * nv28 does a complex dance of first using byte 121 of
3725 * the EDID to choose the lvdsmanufacturerindex, then
3726 * later attempting to match the EDID manufacturer and
3727 * product IDs in a table (signature 'pidt' (panel id
3728 * table?)), setting an lvdsmanufacturerindex of 0 and
3729 * an fp strap of the match index (or 0xf if none)
3730 */
3731 lvdsmanufacturerindex = 0;
3732 } else {
3733 /* nv31, nv34 behaviour */
3734 lvdsmanufacturerindex = 0;
3735 if (pxclk >= bios->fp.duallink_transition_clk)
3736 lvdsmanufacturerindex = 2;
3737 if (pxclk >= 140000)
3738 lvdsmanufacturerindex = 3;
3739 }
3740
3741 /*
3742 * nvidia set the high nibble of (cr57=f, cr58) to
3743 * lvdsmanufacturerindex in this case; we don't
3744 */
3745 break;
3746 case 0x30: /* NV4x */
3747 case 0x40: /* G80/G90 */
3748 lvdsmanufacturerindex = fpstrapping;
3749 break;
3750 default:
3751 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3752 return -ENOSYS;
3753 }
3754
3755 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3756 switch (lth.lvds_ver) {
3757 case 0x0a:
3758 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3759 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3760 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3761 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3762 *if_is_24bit = bios->data[lvdsofs] & 16;
3763 break;
3764 case 0x30:
f3bbb9cc 3765 case 0x40:
6ee73861
BS		 3766 /*
3767 * No sign of the "power off for reset" or "reset for panel
3768 * on" bits, but it's safer to assume we should
3769 */
3770 bios->fp.power_off_for_reset = true;
3771 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 3772
6ee73861
BS		 3773 /*
3774 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 3775 * over-written, and if_is_24bit isn't used
6ee73861
BS		 3776 */
3777 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 3778 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3779 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3780 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3781 break;
3782 }
3783
2eb92c80
BS		 3784 /* Dell Latitude D620 reports a too-high value for the dual-link
3785 * transition freq, causing us to program the panel incorrectly.
3786 *
3787 * It doesn't appear the VBIOS actually uses its transition freq
3788 * (90000kHz), instead it uses the "Number of LVDS channels" field
3789 * out of the panel ID structure (http://www.spwg.org/).
3790 *
3791 * For the moment, a quirk will do :)
3792 */
3793 if ((dev->pdev->device == 0x01d7) &&
3794 (dev->pdev->subsystem_vendor == 0x1028) &&
3795 (dev->pdev->subsystem_device == 0x01c2)) {
3796 bios->fp.duallink_transition_clk = 80000;
3797 }
3798
6ee73861
BS		 3799 /* set dual_link flag for EDID case */
3800 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3801 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3802
3803 *dl = bios->fp.dual_link;
3804
3805 return 0;
3806}
3807
3808static uint8_t *
3809bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3810 uint16_t record, int record_len, int record_nr)
3811{
3812 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3813 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3814 uint32_t entry;
3815 uint16_t table;
3816 int i, v;
3817
3818 for (i = 0; i < record_nr; i++, record += record_len) {
3819 table = ROM16(bios->data[record]);
3820 if (!table)
3821 continue;
3822 entry = ROM32(bios->data[table]);
3823
3824 v = (entry & 0x000f0000) >> 16;
3825 if (!(v & dcbent->or))
3826 continue;
3827
3828 v = (entry & 0x000000f0) >> 4;
3829 if (v != dcbent->location)
3830 continue;
3831
3832 v = (entry & 0x0000000f);
3833 if (v != dcbent->type)
3834 continue;
3835
3836 return &bios->data[table];
3837 }
3838
3839 return NULL;
3840}
3841
3842void *
3843nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3844 int *length)
3845{
3846 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3847 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3848 uint8_t *table;
3849
3850 if (!bios->display.dp_table_ptr) {
3851 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3852 return NULL;
3853 }
3854 table = &bios->data[bios->display.dp_table_ptr];
3855
c52e53fd 3856 if (table[0] != 0x20 && table[0] != 0x21) {
6ee73861
BS		 3857 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3858 table[0]);
3859 return NULL;
3860 }
3861
3862 *length = table[4];
3863 return bios_output_config_match(dev, dcbent,
3864 bios->display.dp_table_ptr + table[1],
3865 table[2], table[3]);
3866}
3867
3868int
3869nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3870 uint32_t sub, int pxclk)
3871{
3872 /*
3873 * The display script table is located by the BIT 'U' table.
3874 *
3875 * It contains an array of pointers to various tables describing
3876 * a particular output type. The first 32-bits of the output
3877 * tables contains similar information to a DCB entry, and is
3878 * used to decide whether that particular table is suitable for
3879 * the output you want to access.
3880 *
3881 * The "record header length" field here seems to indicate the
3882 * offset of the first configuration entry in the output tables.
3883 * This is 10 on most cards I've seen, but 12 has been witnessed
3884 * on DP cards, and there's another script pointer within the
3885 * header.
3886 *
3887 * offset + 0 ( 8 bits): version
3888 * offset + 1 ( 8 bits): header length
3889 * offset + 2 ( 8 bits): record length
3890 * offset + 3 ( 8 bits): number of records
3891 * offset + 4 ( 8 bits): record header length
3892 * offset + 5 (16 bits): pointer to first output script table
3893 */
3894
3895 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3896 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3897 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3898 uint8_t *otable = NULL;
3899 uint16_t script;
3900 int i = 0;
3901
3902 if (!bios->display.script_table_ptr) {
3903 NV_ERROR(dev, "No pointer to output script table\n");
3904 return 1;
3905 }
3906
3907 /*
3908 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3909 * so until they are, we really don't need to care.
3910 */
3911 if (table[0] < 0x20)
3912 return 1;
3913
3914 if (table[0] != 0x20 && table[0] != 0x21) {
3915 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
3916 table[0]);
3917 return 1;
3918 }
3919
3920 /*
3921 * The output script tables describing a particular output type
3922 * look as follows:
3923 *
3924 * offset + 0 (32 bits): output this table matches (hash of DCB)
3925 * offset + 4 ( 8 bits): unknown
3926 * offset + 5 ( 8 bits): number of configurations
3927 * offset + 6 (16 bits): pointer to some script
3928 * offset + 8 (16 bits): pointer to some script
3929 *
3930 * headerlen == 10
3931 * offset + 10 : configuration 0
3932 *
3933 * headerlen == 12
3934 * offset + 10 : pointer to some script
3935 * offset + 12 : configuration 0
3936 *
3937 * Each config entry is as follows:
3938 *
3939 * offset + 0 (16 bits): unknown, assumed to be a match value
3940 * offset + 2 (16 bits): pointer to script table (clock set?)
3941 * offset + 4 (16 bits): pointer to script table (reset?)
3942 *
3943 * There doesn't appear to be a count value to say how many
3944 * entries exist in each script table, instead, a 0 value in
3945 * the first 16-bit word seems to indicate both the end of the
3946 * list and the default entry. The second 16-bit word in the
3947 * script tables is a pointer to the script to execute.
3948 */
3949
ef2bb506 3950 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 3951 dcbent->type, dcbent->location, dcbent->or);
3952 otable = bios_output_config_match(dev, dcbent, table[1] +
3953 bios->display.script_table_ptr,
3954 table[2], table[3]);
3955 if (!otable) {
3956 NV_ERROR(dev, "Couldn't find matching output script table\n");
3957 return 1;
3958 }
3959
3960 if (pxclk < -2 || pxclk > 0) {
3961 /* Try to find matching script table entry */
3962 for (i = 0; i < otable[5]; i++) {
3963 if (ROM16(otable[table[4] + i*6]) == sub)
3964 break;
3965 }
3966
3967 if (i == otable[5]) {
3968 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
3969 "using first\n",
3970 sub, dcbent->type, dcbent->or);
3971 i = 0;
3972 }
3973 }
3974
6ee73861
BS		 3975 if (pxclk == 0) {
3976 script = ROM16(otable[6]);
3977 if (!script) {
ef2bb506 3978 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 3979 return 1;
3980 }
3981
3982 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 3983 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3984 } else
3985 if (pxclk == -1) {
3986 script = ROM16(otable[8]);
3987 if (!script) {
ef2bb506 3988 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 3989 return 1;
3990 }
3991
3992 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 3993 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3994 } else
3995 if (pxclk == -2) {
3996 if (table[4] >= 12)
3997 script = ROM16(otable[10]);
3998 else
3999 script = 0;
4000 if (!script) {
ef2bb506 4001 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4002 return 1;
4003 }
4004
4005 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 4006 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4007 } else
4008 if (pxclk > 0) {
4009 script = ROM16(otable[table[4] + i*6 + 2]);
4010 if (script)
4011 script = clkcmptable(bios, script, pxclk);
4012 if (!script) {
4013 NV_ERROR(dev, "clock script 0 not found\n");
4014 return 1;
4015 }
4016
4017 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 4018 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4019 } else
4020 if (pxclk < 0) {
4021 script = ROM16(otable[table[4] + i*6 + 4]);
4022 if (script)
4023 script = clkcmptable(bios, script, -pxclk);
4024 if (!script) {
ef2bb506 4025 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4026 return 1;
4027 }
4028
4029 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 4030 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4031 }
4032
4033 return 0;
4034}
4035
4036
4037int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4038{
4039 /*
4040 * the pxclk parameter is in kHz
4041 *
4042 * This runs the TMDS regs setting code found on BIT bios cards
4043 *
4044 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4045 * ffs(or) == 3, use the second.
4046 */
4047
4048 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4049 struct nvbios *bios = &dev_priv->vbios;
4050 int cv = bios->chip_version;
6ee73861
BS		 4051 uint16_t clktable = 0, scriptptr;
4052 uint32_t sel_clk_binding, sel_clk;
4053
4054 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4055 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4056 dcbent->location != DCB_LOC_ON_CHIP)
4057 return 0;
4058
4059 switch (ffs(dcbent->or)) {
4060 case 1:
4061 clktable = bios->tmds.output0_script_ptr;
4062 break;
4063 case 2:
4064 case 3:
4065 clktable = bios->tmds.output1_script_ptr;
4066 break;
4067 }
4068
4069 if (!clktable) {
4070 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4071 return -EINVAL;
4072 }
4073
4074 scriptptr = clkcmptable(bios, clktable, pxclk);
4075
4076 if (!scriptptr) {
4077 NV_ERROR(dev, "TMDS output init script not found\n");
4078 return -ENOENT;
4079 }
4080
4081 /* don't let script change pll->head binding */
4082 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4083 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4084 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4085 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4086
4087 return 0;
4088}
4089
4090int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4091{
4092 /*
4093 * PLL limits table
4094 *
4095 * Version 0x10: NV30, NV31
4096 * One byte header (version), one record of 24 bytes
4097 * Version 0x11: NV36 - Not implemented
4098 * Seems to have same record style as 0x10, but 3 records rather than 1
4099 * Version 0x20: Found on Geforce 6 cards
4100 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4101 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4102 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4103 * length in general, some (integrated) have an extra configuration byte
4104 * Version 0x30: Found on Geforce 8, separates the register mapping
4105 * from the limits tables.
4106 */
4107
4108 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4109 struct nvbios *bios = &dev_priv->vbios;
4110 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4111 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4112 uint32_t crystal_strap_mask, crystal_straps;
4113
4114 if (!bios->pll_limit_tbl_ptr) {
4115 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4116 cv >= 0x40) {
4117 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4118 return -EINVAL;
4119 }
4120 } else
4121 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4122
4123 crystal_strap_mask = 1 << 6;
4124 /* open coded dev->twoHeads test */
4125 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4126 crystal_strap_mask |= 1 << 22;
4127 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4128 crystal_strap_mask;
4129
4130 switch (pll_lim_ver) {
4131 /*
4132 * We use version 0 to indicate a pre limit table bios (single stage
4133 * pll) and load the hard coded limits instead.
4134 */
4135 case 0:
4136 break;
4137 case 0x10:
4138 case 0x11:
4139 /*
4140 * Strictly v0x11 has 3 entries, but the last two don't seem
4141 * to get used.
4142 */
4143 headerlen = 1;
4144 recordlen = 0x18;
4145 entries = 1;
4146 pllindex = 0;
4147 break;
4148 case 0x20:
4149 case 0x21:
4150 case 0x30:
4151 case 0x40:
4152 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4153 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4154 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4155 break;
4156 default:
4157 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4158 "supported\n", pll_lim_ver);
4159 return -ENOSYS;
4160 }
4161
4162 /* initialize all members to zero */
4163 memset(pll_lim, 0, sizeof(struct pll_lims));
4164
4165 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4166 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4167
4168 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4169 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4170 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4171 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4172 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4173 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4174 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4175
4176 /* these values taken from nv30/31/36 */
4177 pll_lim->vco1.min_n = 0x1;
4178 if (cv == 0x36)
4179 pll_lim->vco1.min_n = 0x5;
4180 pll_lim->vco1.max_n = 0xff;
4181 pll_lim->vco1.min_m = 0x1;
4182 pll_lim->vco1.max_m = 0xd;
4183 pll_lim->vco2.min_n = 0x4;
4184 /*
4185 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4186 * table version (apart from nv35)), N2 is compared to
4187 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4188 * save a comparison
4189 */
4190 pll_lim->vco2.max_n = 0x28;
4191 if (cv == 0x30 || cv == 0x35)
4192 /* only 5 bits available for N2 on nv30/35 */
4193 pll_lim->vco2.max_n = 0x1f;
4194 pll_lim->vco2.min_m = 0x1;
4195 pll_lim->vco2.max_m = 0x4;
4196 pll_lim->max_log2p = 0x7;
4197 pll_lim->max_usable_log2p = 0x6;
4198 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4199 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4200 uint32_t reg = 0; /* default match */
4201 uint8_t *pll_rec;
4202 int i;
4203
4204 /*
4205 * First entry is default match, if nothing better. warn if
4206 * reg field nonzero
4207 */
4208 if (ROM32(bios->data[plloffs]))
4209 NV_WARN(dev, "Default PLL limit entry has non-zero "
4210 "register field\n");
4211
4212 if (limit_match > MAX_PLL_TYPES)
4213 /* we've been passed a reg as the match */
4214 reg = limit_match;
4215 else /* limit match is a pll type */
4216 for (i = 1; i < entries && !reg; i++) {
4217 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4218
4219 if (limit_match == NVPLL &&
4220 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4221 reg = cmpreg;
4222 if (limit_match == MPLL &&
4223 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4224 reg = cmpreg;
4225 if (limit_match == VPLL1 &&
4226 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4227 reg = cmpreg;
4228 if (limit_match == VPLL2 &&
4229 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4230 reg = cmpreg;
4231 }
4232
4233 for (i = 1; i < entries; i++)
4234 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4235 pllindex = i;
4236 break;
4237 }
4238
4239 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4240
4241 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4242 pllindex ? reg : 0);
4243
4244 /*
4245 * Frequencies are stored in tables in MHz, kHz are more
4246 * useful, so we convert.
4247 */
4248
4249 /* What output frequencies can each VCO generate? */
4250 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4251 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4252 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4253 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4254
4255 /* What input frequencies they accept (past the m-divider)? */
4256 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4257 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4258 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4259 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4260
4261 /* What values are accepted as multiplier and divider? */
4262 pll_lim->vco1.min_n = pll_rec[20];
4263 pll_lim->vco1.max_n = pll_rec[21];
4264 pll_lim->vco1.min_m = pll_rec[22];
4265 pll_lim->vco1.max_m = pll_rec[23];
4266 pll_lim->vco2.min_n = pll_rec[24];
4267 pll_lim->vco2.max_n = pll_rec[25];
4268 pll_lim->vco2.min_m = pll_rec[26];
4269 pll_lim->vco2.max_m = pll_rec[27];
4270
4271 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4272 if (pll_lim->max_log2p > 0x7)
4273 /* pll decoding in nv_hw.c assumes never > 7 */
4274 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4275 pll_lim->max_log2p);
4276 if (cv < 0x60)
4277 pll_lim->max_usable_log2p = 0x6;
4278 pll_lim->log2p_bias = pll_rec[30];
4279
4280 if (recordlen > 0x22)
4281 pll_lim->refclk = ROM32(pll_rec[31]);
4282
4283 if (recordlen > 0x23 && pll_rec[35])
4284 NV_WARN(dev,
4285 "Bits set in PLL configuration byte (%x)\n",
4286 pll_rec[35]);
4287
4288 /* C51 special not seen elsewhere */
4289 if (cv == 0x51 && !pll_lim->refclk) {
4290 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4291
4292 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4293 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4294 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4295 pll_lim->refclk = 200000;
4296 else
4297 pll_lim->refclk = 25000;
4298 }
4299 }
4300 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4301 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4302 uint8_t *record = NULL;
4303 int i;
4304
4305 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4306 limit_match);
4307
4308 for (i = 0; i < entries; i++, entry += recordlen) {
4309 if (ROM32(entry[3]) == limit_match) {
4310 record = &bios->data[ROM16(entry[1])];
4311 break;
4312 }
4313 }
4314
4315 if (!record) {
4316 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4317 "limits table", limit_match);
4318 return -ENOENT;
4319 }
4320
4321 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4322 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4323 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4324 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4325 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4326 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4327 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4328 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4329 pll_lim->vco1.min_n = record[16];
4330 pll_lim->vco1.max_n = record[17];
4331 pll_lim->vco1.min_m = record[18];
4332 pll_lim->vco1.max_m = record[19];
4333 pll_lim->vco2.min_n = record[20];
4334 pll_lim->vco2.max_n = record[21];
4335 pll_lim->vco2.min_m = record[22];
4336 pll_lim->vco2.max_m = record[23];
4337 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4338 pll_lim->log2p_bias = record[27];
4339 pll_lim->refclk = ROM32(record[28]);
4340 } else if (pll_lim_ver) { /* ver 0x40 */
4341 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4342 uint8_t *record = NULL;
4343 int i;
4344
4345 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4346 limit_match);
4347
4348 for (i = 0; i < entries; i++, entry += recordlen) {
4349 if (ROM32(entry[3]) == limit_match) {
4350 record = &bios->data[ROM16(entry[1])];
4351 break;
4352 }
4353 }
4354
4355 if (!record) {
4356 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4357 "limits table", limit_match);
4358 return -ENOENT;
4359 }
4360
4361 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4362 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4363 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4364 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4365 pll_lim->vco1.min_m = record[8];
4366 pll_lim->vco1.max_m = record[9];
4367 pll_lim->vco1.min_n = record[10];
4368 pll_lim->vco1.max_n = record[11];
4369 pll_lim->min_p = record[12];
4370 pll_lim->max_p = record[13];
4371 /* where did this go to?? */
4372 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4373 pll_lim->refclk = 27000;
4374 else
4375 pll_lim->refclk = 100000;
4376 }
4377
4378 /*
4379 * By now any valid limit table ought to have set a max frequency for
4380 * vco1, so if it's zero it's either a pre limit table bios, or one
4381 * with an empty limit table (seen on nv18)
4382 */
4383 if (!pll_lim->vco1.maxfreq) {
4384 pll_lim->vco1.minfreq = bios->fminvco;
4385 pll_lim->vco1.maxfreq = bios->fmaxvco;
4386 pll_lim->vco1.min_inputfreq = 0;
4387 pll_lim->vco1.max_inputfreq = INT_MAX;
4388 pll_lim->vco1.min_n = 0x1;
4389 pll_lim->vco1.max_n = 0xff;
4390 pll_lim->vco1.min_m = 0x1;
4391 if (crystal_straps == 0) {
4392 /* nv05 does this, nv11 doesn't, nv10 unknown */
4393 if (cv < 0x11)
4394 pll_lim->vco1.min_m = 0x7;
4395 pll_lim->vco1.max_m = 0xd;
4396 } else {
4397 if (cv < 0x11)
4398 pll_lim->vco1.min_m = 0x8;
4399 pll_lim->vco1.max_m = 0xe;
4400 }
4401 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4402 pll_lim->max_log2p = 4;
4403 else
4404 pll_lim->max_log2p = 5;
4405 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4406 }
4407
4408 if (!pll_lim->refclk)
4409 switch (crystal_straps) {
4410 case 0:
4411 pll_lim->refclk = 13500;
4412 break;
4413 case (1 << 6):
4414 pll_lim->refclk = 14318;
4415 break;
4416 case (1 << 22):
4417 pll_lim->refclk = 27000;
4418 break;
4419 case (1 << 22 | 1 << 6):
4420 pll_lim->refclk = 25000;
4421 break;
4422 }
4423
4c389f00
BS		 4424 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4425 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4426 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4427 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4428 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4429 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4430 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4431 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4432 if (pll_lim->vco2.maxfreq) {
4433 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4434 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4435 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4436 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4437 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4438 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4439 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4440 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4441 }
4442 if (!pll_lim->max_p) {
4443 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4444 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4445 } else {
4446 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4447 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4448 }
4449 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 4450
4451 return 0;
4452}
4453
4454static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4455{
4456 /*
4457 * offset + 0 (8 bits): Micro version
4458 * offset + 1 (8 bits): Minor version
4459 * offset + 2 (8 bits): Chip version
4460 * offset + 3 (8 bits): Major version
4461 */
4462
4463 bios->major_version = bios->data[offset + 3];
04a39c57 4464 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4465 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4466 bios->data[offset + 3], bios->data[offset + 2],
4467 bios->data[offset + 1], bios->data[offset]);
4468}
4469
4470static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4471{
4472 /*
4473 * Parses the init table segment for pointers used in script execution.
4474 *
4475 * offset + 0 (16 bits): init script tables pointer
4476 * offset + 2 (16 bits): macro index table pointer
4477 * offset + 4 (16 bits): macro table pointer
4478 * offset + 6 (16 bits): condition table pointer
4479 * offset + 8 (16 bits): io condition table pointer
4480 * offset + 10 (16 bits): io flag condition table pointer
4481 * offset + 12 (16 bits): init function table pointer
4482 */
4483
4484 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4485 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4486 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4487 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4488 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4489 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4490 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4491}
4492
4493static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4494{
4495 /*
4496 * Parses the load detect values for g80 cards.
4497 *
4498 * offset + 0 (16 bits): loadval table pointer
4499 */
4500
4501 uint16_t load_table_ptr;
4502 uint8_t version, headerlen, entrylen, num_entries;
4503
4504 if (bitentry->length != 3) {
4505 NV_ERROR(dev, "Do not understand BIT A table\n");
4506 return -EINVAL;
4507 }
4508
4509 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4510
4511 if (load_table_ptr == 0x0) {
4512 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4513 return -EINVAL;
4514 }
4515
4516 version = bios->data[load_table_ptr];
4517
4518 if (version != 0x10) {
4519 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4520 version >> 4, version & 0xF);
4521 return -ENOSYS;
4522 }
4523
4524 headerlen = bios->data[load_table_ptr + 1];
4525 entrylen = bios->data[load_table_ptr + 2];
4526 num_entries = bios->data[load_table_ptr + 3];
4527
4528 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4529 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4530 return -EINVAL;
4531 }
4532
4533 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 4534 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 4535
4536 return 0;
4537}
4538
4539static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4540{
4541 /*
4542 * offset + 8 (16 bits): PLL limits table pointer
4543 *
4544 * There's more in here, but that's unknown.
4545 */
4546
4547 if (bitentry->length < 10) {
4548 NV_ERROR(dev, "Do not understand BIT C table\n");
4549 return -EINVAL;
4550 }
4551
4552 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4553
4554 return 0;
4555}
4556
4557static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4558{
4559 /*
4560 * Parses the flat panel table segment that the bit entry points to.
4561 * Starting at bitentry->offset:
4562 *
4563 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4564 * records beginning with a freq.
4565 * offset + 2 (16 bits): mode table pointer
4566 */
4567
4568 if (bitentry->length != 4) {
4569 NV_ERROR(dev, "Do not understand BIT display table\n");
4570 return -EINVAL;
4571 }
4572
4573 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4574
4575 return 0;
4576}
4577
4578static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4579{
4580 /*
4581 * Parses the init table segment that the bit entry points to.
4582 *
4583 * See parse_script_table_pointers for layout
4584 */
4585
4586 if (bitentry->length < 14) {
4587 NV_ERROR(dev, "Do not understand init table\n");
4588 return -EINVAL;
4589 }
4590
4591 parse_script_table_pointers(bios, bitentry->offset);
4592
4593 if (bitentry->length >= 16)
4594 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4595 if (bitentry->length >= 18)
4596 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4597
4598 return 0;
4599}
4600
4601static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4602{
4603 /*
4604 * BIT 'i' (info?) table
4605 *
4606 * offset + 0 (32 bits): BIOS version dword (as in B table)
4607 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4608 * offset + 13 (16 bits): pointer to table containing DAC load
4609 * detection comparison values
4610 *
4611 * There's other things in the table, purpose unknown
4612 */
4613
4614 uint16_t daccmpoffset;
4615 uint8_t dacver, dacheaderlen;
4616
4617 if (bitentry->length < 6) {
4618 NV_ERROR(dev, "BIT i table too short for needed information\n");
4619 return -EINVAL;
4620 }
4621
4622 parse_bios_version(dev, bios, bitentry->offset);
4623
4624 /*
4625 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4626 * Quadro identity crisis), other bits possibly as for BMP feature byte
4627 */
4628 bios->feature_byte = bios->data[bitentry->offset + 5];
4629 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4630
4631 if (bitentry->length < 15) {
4632 NV_WARN(dev, "BIT i table not long enough for DAC load "
4633 "detection comparison table\n");
4634 return -EINVAL;
4635 }
4636
4637 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4638
4639 /* doesn't exist on g80 */
4640 if (!daccmpoffset)
4641 return 0;
4642
4643 /*
4644 * The first value in the table, following the header, is the
4645 * comparison value, the second entry is a comparison value for
4646 * TV load detection.
4647 */
4648
4649 dacver = bios->data[daccmpoffset];
4650 dacheaderlen = bios->data[daccmpoffset + 1];
4651
4652 if (dacver != 0x00 && dacver != 0x10) {
4653 NV_WARN(dev, "DAC load detection comparison table version "
4654 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4655 return -ENOSYS;
4656 }
4657
04a39c57
BS		 4658 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4659 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 4660
4661 return 0;
4662}
4663
4664static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4665{
4666 /*
4667 * Parses the LVDS table segment that the bit entry points to.
4668 * Starting at bitentry->offset:
4669 *
4670 * offset + 0 (16 bits): LVDS strap xlate table pointer
4671 */
4672
4673 if (bitentry->length != 2) {
4674 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4675 return -EINVAL;
4676 }
4677
4678 /*
4679 * No idea if it's still called the LVDS manufacturer table, but
4680 * the concept's close enough.
4681 */
4682 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4683
4684 return 0;
4685}
4686
4687static int
4688parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4689 struct bit_entry *bitentry)
4690{
4691 /*
4692 * offset + 2 (8 bits): number of options in an
4693 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4694 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4695 * restrict option selection
4696 *
4697 * There's a bunch of bits in this table other than the RAM restrict
4698 * stuff that we don't use - their use currently unknown
4699 */
4700
6ee73861
BS		 4701 /*
4702 * Older bios versions don't have a sufficiently long table for
4703 * what we want
4704 */
4705 if (bitentry->length < 0x5)
4706 return 0;
4707
4708 if (bitentry->id[1] < 2) {
37383650
MK		 4709 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4710 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 4711 } else {
37383650
MK		 4712 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4713 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 4714 }
4715
6ee73861
BS		 4716 return 0;
4717}
4718
4719static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4720{
4721 /*
4722 * Parses the pointer to the TMDS table
4723 *
4724 * Starting at bitentry->offset:
4725 *
4726 * offset + 0 (16 bits): TMDS table pointer
4727 *
4728 * The TMDS table is typically found just before the DCB table, with a
4729 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4730 * length?)
4731 *
4732 * At offset +7 is a pointer to a script, which I don't know how to
4733 * run yet.
4734 * At offset +9 is a pointer to another script, likewise
4735 * Offset +11 has a pointer to a table where the first word is a pxclk
4736 * frequency and the second word a pointer to a script, which should be
4737 * run if the comparison pxclk frequency is less than the pxclk desired.
4738 * This repeats for decreasing comparison frequencies
4739 * Offset +13 has a pointer to a similar table
4740 * The selection of table (and possibly +7/+9 script) is dictated by
4741 * "or" from the DCB.
4742 */
4743
4744 uint16_t tmdstableptr, script1, script2;
4745
4746 if (bitentry->length != 2) {
4747 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4748 return -EINVAL;
4749 }
4750
4751 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4752
4753 if (tmdstableptr == 0x0) {
4754 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4755 return -EINVAL;
4756 }
4757
4758 /* nv50+ has v2.0, but we don't parse it atm */
4759 if (bios->data[tmdstableptr] != 0x11) {
4760 NV_WARN(dev,
4761 "TMDS table revision %d.%d not currently supported\n",
4762 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4763 return -ENOSYS;
4764 }
4765
4766 /*
4767 * These two scripts are odd: they don't seem to get run even when
4768 * they are not stubbed.
4769 */
4770 script1 = ROM16(bios->data[tmdstableptr + 7]);
4771 script2 = ROM16(bios->data[tmdstableptr + 9]);
4772 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4773 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4774
4775 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4776 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4777
4778 return 0;
4779}
4780
4781static int
4782parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4783 struct bit_entry *bitentry)
4784{
4785 /*
4786 * Parses the pointer to the G80 output script tables
4787 *
4788 * Starting at bitentry->offset:
4789 *
4790 * offset + 0 (16 bits): output script table pointer
4791 */
4792
4793 uint16_t outputscripttableptr;
4794
4795 if (bitentry->length != 3) {
4796 NV_ERROR(dev, "Do not understand BIT U table\n");
4797 return -EINVAL;
4798 }
4799
4800 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4801 bios->display.script_table_ptr = outputscripttableptr;
4802 return 0;
4803}
4804
4805static int
4806parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4807 struct bit_entry *bitentry)
4808{
4809 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4810 return 0;
4811}
4812
4813struct bit_table {
4814 const char id;
4815 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4816};
4817
4818#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4819
4820static int
4821parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4822 struct bit_table *table)
4823{
4824 struct drm_device *dev = bios->dev;
4825 uint8_t maxentries = bios->data[bitoffset + 4];
4826 int i, offset;
4827 struct bit_entry bitentry;
4828
4829 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4830 bitentry.id[0] = bios->data[offset];
4831
4832 if (bitentry.id[0] != table->id)
4833 continue;
4834
4835 bitentry.id[1] = bios->data[offset + 1];
4836 bitentry.length = ROM16(bios->data[offset + 2]);
4837 bitentry.offset = ROM16(bios->data[offset + 4]);
4838
4839 return table->parse_fn(dev, bios, &bitentry);
4840 }
4841
4842 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4843 return -ENOSYS;
4844}
4845
4846static int
4847parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4848{
4849 int ret;
4850
4851 /*
4852 * The only restriction on parsing order currently is having 'i' first
4853 * for use of bios->*_version or bios->feature_byte while parsing;
4854 * functions shouldn't be actually *doing* anything apart from pulling
4855 * data from the image into the bios struct, thus no interdependencies
4856 */
4857 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4858 if (ret) /* info? */
4859 return ret;
4860 if (bios->major_version >= 0x60) /* g80+ */
4861 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4862 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4863 if (ret)
4864 return ret;
4865 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4866 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4867 if (ret)
4868 return ret;
4869 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4870 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4871 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4872 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4873 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4874
4875 return 0;
4876}
4877
4878static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4879{
4880 /*
4881 * Parses the BMP structure for useful things, but does not act on them
4882 *
4883 * offset + 5: BMP major version
4884 * offset + 6: BMP minor version
4885 * offset + 9: BMP feature byte
4886 * offset + 10: BCD encoded BIOS version
4887 *
4888 * offset + 18: init script table pointer (for bios versions < 5.10h)
4889 * offset + 20: extra init script table pointer (for bios
4890 * versions < 5.10h)
4891 *
4892 * offset + 24: memory init table pointer (used on early bios versions)
4893 * offset + 26: SDR memory sequencing setup data table
4894 * offset + 28: DDR memory sequencing setup data table
4895 *
4896 * offset + 54: index of I2C CRTC pair to use for CRT output
4897 * offset + 55: index of I2C CRTC pair to use for TV output
4898 * offset + 56: index of I2C CRTC pair to use for flat panel output
4899 * offset + 58: write CRTC index for I2C pair 0
4900 * offset + 59: read CRTC index for I2C pair 0
4901 * offset + 60: write CRTC index for I2C pair 1
4902 * offset + 61: read CRTC index for I2C pair 1
4903 *
4904 * offset + 67: maximum internal PLL frequency (single stage PLL)
4905 * offset + 71: minimum internal PLL frequency (single stage PLL)
4906 *
4907 * offset + 75: script table pointers, as described in
4908 * parse_script_table_pointers
4909 *
4910 * offset + 89: TMDS single link output A table pointer
4911 * offset + 91: TMDS single link output B table pointer
4912 * offset + 95: LVDS single link output A table pointer
4913 * offset + 105: flat panel timings table pointer
4914 * offset + 107: flat panel strapping translation table pointer
4915 * offset + 117: LVDS manufacturer panel config table pointer
4916 * offset + 119: LVDS manufacturer strapping translation table pointer
4917 *
4918 * offset + 142: PLL limits table pointer
4919 *
4920 * offset + 156: minimum pixel clock for LVDS dual link
4921 */
4922
4923 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
4924 uint16_t bmplength;
4925 uint16_t legacy_scripts_offset, legacy_i2c_offset;
4926
4927 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 4928 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
4929 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
4930 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
4931 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 4932 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 4933 bios->fmaxvco = 256000;
4934 bios->fminvco = 128000;
4935 bios->fp.duallink_transition_clk = 90000;
4936
4937 bmp_version_major = bmp[5];
4938 bmp_version_minor = bmp[6];
4939
4940 NV_TRACE(dev, "BMP version %d.%d\n",
4941 bmp_version_major, bmp_version_minor);
4942
4943 /*
4944 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4945 * pointer on early versions
4946 */
4947 if (bmp_version_major < 5)
4948 *(uint16_t *)&bios->data[0x36] = 0;
4949
4950 /*
4951 * Seems that the minor version was 1 for all major versions prior
4952 * to 5. Version 6 could theoretically exist, but I suspect BIT
4953 * happened instead.
4954 */
4955 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
4956 NV_ERROR(dev, "You have an unsupported BMP version. "
4957 "Please send in your bios\n");
4958 return -ENOSYS;
4959 }
4960
4961 if (bmp_version_major == 0)
4962 /* nothing that's currently useful in this version */
4963 return 0;
4964 else if (bmp_version_major == 1)
4965 bmplength = 44; /* exact for 1.01 */
4966 else if (bmp_version_major == 2)
4967 bmplength = 48; /* exact for 2.01 */
4968 else if (bmp_version_major == 3)
4969 bmplength = 54;
4970 /* guessed - mem init tables added in this version */
4971 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
4972 /* don't know if 5.0 exists... */
4973 bmplength = 62;
4974 /* guessed - BMP I2C indices added in version 4*/
4975 else if (bmp_version_minor < 0x6)
4976 bmplength = 67; /* exact for 5.01 */
4977 else if (bmp_version_minor < 0x10)
4978 bmplength = 75; /* exact for 5.06 */
4979 else if (bmp_version_minor == 0x10)
4980 bmplength = 89; /* exact for 5.10h */
4981 else if (bmp_version_minor < 0x14)
4982 bmplength = 118; /* exact for 5.11h */
4983 else if (bmp_version_minor < 0x24)
4984 /*
4985 * Not sure of version where pll limits came in;
4986 * certainly exist by 0x24 though.
4987 */
4988 /* length not exact: this is long enough to get lvds members */
4989 bmplength = 123;
4990 else if (bmp_version_minor < 0x27)
4991 /*
4992 * Length not exact: this is long enough to get pll limit
4993 * member
4994 */
4995 bmplength = 144;
4996 else
4997 /*
4998 * Length not exact: this is long enough to get dual link
4999 * transition clock.
5000 */
5001 bmplength = 158;
5002
5003 /* checksum */
5004 if (nv_cksum(bmp, 8)) {
5005 NV_ERROR(dev, "Bad BMP checksum\n");
5006 return -EINVAL;
5007 }
5008
5009 /*
5010 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5011 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5012 * (not nv10gl), bit 5 that the flat panel tables are present, and
5013 * bit 6 a tv bios.
5014 */
5015 bios->feature_byte = bmp[9];
5016
5017 parse_bios_version(dev, bios, offset + 10);
5018
5019 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5020 bios->old_style_init = true;
5021 legacy_scripts_offset = 18;
5022 if (bmp_version_major < 2)
5023 legacy_scripts_offset -= 4;
5024 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5025 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5026
5027 if (bmp_version_major > 2) { /* appears in BMP 3 */
5028 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5029 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5030 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5031 }
5032
5033 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5034 if (bmplength > 61)
5035 legacy_i2c_offset = offset + 54;
5036 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5037 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5038 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
7f245b20
BS		 5039 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5040 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5041 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5042 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5043
5044 if (bmplength > 74) {
5045 bios->fmaxvco = ROM32(bmp[67]);
5046 bios->fminvco = ROM32(bmp[71]);
5047 }
5048 if (bmplength > 88)
5049 parse_script_table_pointers(bios, offset + 75);
5050 if (bmplength > 94) {
5051 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5052 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5053 /*
5054 * Never observed in use with lvds scripts, but is reused for
5055 * 18/24 bit panel interface default for EDID equipped panels
5056 * (if_is_24bit not set directly to avoid any oscillation).
5057 */
5058 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5059 }
5060 if (bmplength > 108) {
5061 bios->fp.fptablepointer = ROM16(bmp[105]);
5062 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5063 bios->fp.xlatwidth = 1;
5064 }
5065 if (bmplength > 120) {
5066 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5067 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5068 }
5069 if (bmplength > 143)
5070 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5071
5072 if (bmplength > 157)
5073 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5074
5075 return 0;
5076}
5077
5078static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5079{
5080 int i, j;
5081
5082 for (i = 0; i <= (n - len); i++) {
5083 for (j = 0; j < len; j++)
5084 if (data[i + j] != str[j])
5085 break;
5086 if (j == len)
5087 return i;
5088 }
5089
5090 return 0;
5091}
5092
5093static int
5094read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
5095{
5096 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
5097 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
5098 int recordoffset = 0, rdofs = 1, wrofs = 0;
5099 uint8_t port_type = 0;
5100
5101 if (!i2ctable)
5102 return -EINVAL;
5103
5104 if (dcb_version >= 0x30) {
5105 if (i2ctable[0] != dcb_version) /* necessary? */
5106 NV_WARN(dev,
5107 "DCB I2C table version mismatch (%02X vs %02X)\n",
5108 i2ctable[0], dcb_version);
5109 dcb_i2c_ver = i2ctable[0];
5110 headerlen = i2ctable[1];
5111 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
5112 i2c_entries = i2ctable[2];
5113 else
5114 NV_WARN(dev,
5115 "DCB I2C table has more entries than indexable "
761c5a69
MS		 5116 "(%d entries, max %d)\n", i2ctable[2],
5117 DCB_MAX_NUM_I2C_ENTRIES);
6ee73861
BS		 5118 entry_len = i2ctable[3];
5119 /* [4] is i2c_default_indices, read in parse_dcb_table() */
5120 }
5121 /*
5122 * It's your own fault if you call this function on a DCB 1.1 BIOS --
5123 * the test below is for DCB 1.2
5124 */
5125 if (dcb_version < 0x14) {
5126 recordoffset = 2;
5127 rdofs = 0;
5128 wrofs = 1;
5129 }
5130
5131 if (index == 0xf)
5132 return 0;
761c5a69
MS		 5133 if (index >= i2c_entries) {
5134 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
6ee73861
BS		 5135 index, i2ctable[2]);
5136 return -ENOENT;
5137 }
5138 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
5139 NV_ERROR(dev, "DCB I2C entry invalid\n");
5140 return -EINVAL;
5141 }
5142
5143 if (dcb_i2c_ver >= 0x30) {
5144 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
5145
5146 /*
5147 * Fixup for chips using same address offset for read and
5148 * write.
5149 */
5150 if (port_type == 4) /* seen on C51 */
5151 rdofs = wrofs = 1;
5152 if (port_type >= 5) /* G80+ */
5153 rdofs = wrofs = 0;
5154 }
5155
07fee3d5
BS		 5156 if (dcb_i2c_ver >= 0x40) {
5157 if (port_type != 5 && port_type != 6)
5158 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
5159
5160 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
5161 }
6ee73861
BS		 5162
5163 i2c->port_type = port_type;
5164 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
5165 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
5166
5167 return 0;
5168}
5169
5170static struct dcb_gpio_entry *
5171new_gpio_entry(struct nvbios *bios)
5172{
7f245b20 5173 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861
BS		 5174
5175 return &gpio->entry[gpio->entries++];
5176}
5177
5178struct dcb_gpio_entry *
5179nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5180{
5181 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5182 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5183 int i;
5184
7f245b20
BS		 5185 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5186 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5187 continue;
5188
7f245b20 5189 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5190 }
5191
5192 return NULL;
5193}
5194
5195static void
5196parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5197{
5198 struct dcb_gpio_entry *gpio;
5199 uint16_t ent = ROM16(bios->data[offset]);
5200 uint8_t line = ent & 0x1f,
5201 tag = ent >> 5 & 0x3f,
5202 flags = ent >> 11 & 0x1f;
5203
5204 if (tag == 0x3f)
5205 return;
5206
5207 gpio = new_gpio_entry(bios);
5208
5209 gpio->tag = tag;
5210 gpio->line = line;
5211 gpio->invert = flags != 4;
2535d71c 5212 gpio->entry = ent;
6ee73861
BS		 5213}
5214
5215static void
5216parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5217{
02faec09 5218 uint32_t entry = ROM32(bios->data[offset]);
6ee73861 5219 struct dcb_gpio_entry *gpio;
6ee73861 5220
02faec09 5221 if ((entry & 0x0000ff00) == 0x0000ff00)
6ee73861
BS		 5222 return;
5223
5224 gpio = new_gpio_entry(bios);
02faec09
BS		 5225 gpio->tag = (entry & 0x0000ff00) >> 8;
5226 gpio->line = (entry & 0x0000001f) >> 0;
5227 gpio->state_default = (entry & 0x01000000) >> 24;
5228 gpio->state[0] = (entry & 0x18000000) >> 27;
5229 gpio->state[1] = (entry & 0x60000000) >> 29;
5230 gpio->entry = entry;
6ee73861
BS		 5231}
5232
5233static void
5234parse_dcb_gpio_table(struct nvbios *bios)
5235{
5236 struct drm_device *dev = bios->dev;
7f245b20 5237 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr;
6ee73861
BS		 5238 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5239 int header_len = gpio_table[1],
5240 entries = gpio_table[2],
5241 entry_len = gpio_table[3];
5242 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5243 int i;
5244
7f245b20 5245 if (bios->dcb.version >= 0x40) {
6ee73861
BS		 5246 if (gpio_table_ptr && entry_len != 4) {
5247 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5248 return;
5249 }
5250
5251 parse_entry = parse_dcb40_gpio_entry;
5252
7f245b20 5253 } else if (bios->dcb.version >= 0x30) {
6ee73861
BS		 5254 if (gpio_table_ptr && entry_len != 2) {
5255 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5256 return;
5257 }
5258
5259 parse_entry = parse_dcb30_gpio_entry;
5260
7f245b20 5261 } else if (bios->dcb.version >= 0x22) {
6ee73861
BS		 5262 /*
5263 * DCBs older than v3.0 don't really have a GPIO
5264 * table, instead they keep some GPIO info at fixed
5265 * locations.
5266 */
5267 uint16_t dcbptr = ROM16(bios->data[0x36]);
5268 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5269
5270 if (tvdac_gpio[0] & 1) {
5271 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5272
5273 gpio->tag = DCB_GPIO_TVDAC0;
5274 gpio->line = tvdac_gpio[1] >> 4;
5275 gpio->invert = tvdac_gpio[0] & 2;
5276 }
5277 }
5278
5279 if (!gpio_table_ptr)
5280 return;
5281
5282 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5283 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5284 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5285 }
5286
5287 for (i = 0; i < entries; i++)
5288 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5289}
5290
5291struct dcb_connector_table_entry *
5292nouveau_bios_connector_entry(struct drm_device *dev, int index)
5293{
5294 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5295 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5296 struct dcb_connector_table_entry *cte;
5297
7f245b20 5298 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5299 return NULL;
5300
7f245b20 5301 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5302 if (cte->type == 0xff)
5303 return NULL;
5304
5305 return cte;
5306}
5307
f66fa771
BS		 5308static enum dcb_connector_type
5309divine_connector_type(struct nvbios *bios, int index)
5310{
5311 struct dcb_table *dcb = &bios->dcb;
5312 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5313 int i;
5314
5315 for (i = 0; i < dcb->entries; i++) {
5316 if (dcb->entry[i].connector == index)
5317 encoders |= (1 << dcb->entry[i].type);
5318 }
5319
5320 if (encoders & (1 << OUTPUT_DP)) {
5321 if (encoders & (1 << OUTPUT_TMDS))
5322 type = DCB_CONNECTOR_DP;
5323 else
5324 type = DCB_CONNECTOR_eDP;
5325 } else
5326 if (encoders & (1 << OUTPUT_TMDS)) {
5327 if (encoders & (1 << OUTPUT_ANALOG))
5328 type = DCB_CONNECTOR_DVI_I;
5329 else
5330 type = DCB_CONNECTOR_DVI_D;
5331 } else
5332 if (encoders & (1 << OUTPUT_ANALOG)) {
5333 type = DCB_CONNECTOR_VGA;
5334 } else
5335 if (encoders & (1 << OUTPUT_LVDS)) {
5336 type = DCB_CONNECTOR_LVDS;
5337 } else
5338 if (encoders & (1 << OUTPUT_TV)) {
5339 type = DCB_CONNECTOR_TV_0;
5340 }
5341
5342 return type;
5343}
5344
53c44c3a
BS		 5345static void
5346apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5347{
5348 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5349 struct drm_device *dev = bios->dev;
5350
5351 /* Gigabyte NX85T */
5352 if ((dev->pdev->device == 0x0421) &&
5353 (dev->pdev->subsystem_vendor == 0x1458) &&
5354 (dev->pdev->subsystem_device == 0x344c)) {
5355 if (cte->type == DCB_CONNECTOR_HDMI_1)
5356 cte->type = DCB_CONNECTOR_DVI_I;
5357 }
5358}
5359
6ee73861
BS		 5360static void
5361parse_dcb_connector_table(struct nvbios *bios)
5362{
5363 struct drm_device *dev = bios->dev;
7f245b20 5364 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5365 struct dcb_connector_table_entry *cte;
7f245b20 5366 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5367 uint8_t *entry;
5368 int i;
5369
7f245b20 5370 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5371 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5372 return;
5373 }
5374
5375 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5376 conntab[0], conntab[1], conntab[2], conntab[3]);
5377 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5378 (conntab[3] != 2 && conntab[3] != 4)) {
5379 NV_ERROR(dev, " Unknown! Please report.\n");
5380 return;
5381 }
5382
5383 ct->entries = conntab[2];
5384
5385 entry = conntab + conntab[1];
5386 cte = &ct->entry[0];
5387 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5388 cte->index = i;
6ee73861
BS		 5389 if (conntab[3] == 2)
5390 cte->entry = ROM16(entry[0]);
5391 else
5392 cte->entry = ROM32(entry[0]);
f66fa771 5393
6ee73861 5394 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 5395 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6ee73861
BS		 5396 switch (cte->entry & 0x00033000) {
5397 case 0x00001000:
5398 cte->gpio_tag = 0x07;
5399 break;
5400 case 0x00002000:
5401 cte->gpio_tag = 0x08;
5402 break;
5403 case 0x00010000:
5404 cte->gpio_tag = 0x51;
5405 break;
5406 case 0x00020000:
5407 cte->gpio_tag = 0x52;
5408 break;
5409 default:
5410 cte->gpio_tag = 0xff;
5411 break;
5412 }
5413
5414 if (cte->type == 0xff)
5415 continue;
5416
53c44c3a
BS		 5417 apply_dcb_connector_quirks(bios, i);
5418
6ee73861
BS		 5419 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5420 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5421
5422 /* check for known types, fallback to guessing the type
5423 * from attached encoders if we hit an unknown.
5424 */
5425 switch (cte->type) {
5426 case DCB_CONNECTOR_VGA:
5427 case DCB_CONNECTOR_TV_0:
5428 case DCB_CONNECTOR_TV_1:
5429 case DCB_CONNECTOR_TV_3:
5430 case DCB_CONNECTOR_DVI_I:
5431 case DCB_CONNECTOR_DVI_D:
5432 case DCB_CONNECTOR_LVDS:
5433 case DCB_CONNECTOR_DP:
5434 case DCB_CONNECTOR_eDP:
5435 case DCB_CONNECTOR_HDMI_0:
5436 case DCB_CONNECTOR_HDMI_1:
5437 break;
5438 default:
5439 cte->type = divine_connector_type(bios, cte->index);
da647d5b 5440 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 5441 break;
5442 }
5443
da647d5b
BS		 5444 if (nouveau_override_conntype) {
5445 int type = divine_connector_type(bios, cte->index);
5446 if (type != cte->type)
5447 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5448 }
5449
6ee73861
BS		 5450 }
5451}
5452
7f245b20 5453static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5454{
5455 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5456
5457 memset(entry, 0, sizeof(struct dcb_entry));
5458 entry->index = dcb->entries++;
5459
5460 return entry;
5461}
5462
7f245b20 5463static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
6ee73861
BS		 5464{
5465 struct dcb_entry *entry = new_dcb_entry(dcb);
5466
5467 entry->type = 0;
5468 entry->i2c_index = i2c;
5469 entry->heads = heads;
5470 entry->location = DCB_LOC_ON_CHIP;
5471 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5472}
5473
7f245b20 5474static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5475{
5476 struct dcb_entry *entry = new_dcb_entry(dcb);
5477
5478 entry->type = 2;
5479 entry->i2c_index = LEGACY_I2C_PANEL;
5480 entry->heads = twoHeads ? 3 : 1;
5481 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5482 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5483 entry->duallink_possible = false; /* SiI164 and co. are single link */
5484
5485#if 0
5486 /*
5487 * For dvi-a either crtc probably works, but my card appears to only
5488 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5489 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5490 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5491 * the monitor picks up the mode res ok and lights up, but no pixel
5492 * data appears, so the board manufacturer probably connected up the
5493 * sync lines, but missed the video traces / components
5494 *
5495 * with this introduction, dvi-a left as an exercise for the reader.
5496 */
5497 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5498#endif
5499}
5500
7f245b20 5501static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5502{
5503 struct dcb_entry *entry = new_dcb_entry(dcb);
5504
5505 entry->type = 1;
5506 entry->i2c_index = LEGACY_I2C_TV;
5507 entry->heads = twoHeads ? 3 : 1;
5508 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5509}
5510
5511static bool
7f245b20 5512parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5513 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5514{
5515 entry->type = conn & 0xf;
5516 entry->i2c_index = (conn >> 4) & 0xf;
5517 entry->heads = (conn >> 8) & 0xf;
7f245b20 5518 if (dcb->version >= 0x40)
6ee73861
BS		 5519 entry->connector = (conn >> 12) & 0xf;
5520 entry->bus = (conn >> 16) & 0xf;
5521 entry->location = (conn >> 20) & 0x3;
5522 entry->or = (conn >> 24) & 0xf;
5523 /*
5524 * Normal entries consist of a single bit, but dual link has the
5525 * next most significant bit set too
5526 */
5527 entry->duallink_possible =
5528 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5529
5530 switch (entry->type) {
5531 case OUTPUT_ANALOG:
5532 /*
5533 * Although the rest of a CRT conf dword is usually
5534 * zeros, mac biosen have stuff there so we must mask
5535 */
7f245b20 5536 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5537 (conf & 0xffff) * 10 :
5538 (conf & 0xff) * 10000;
5539 break;
5540 case OUTPUT_LVDS:
5541 {
5542 uint32_t mask;
5543 if (conf & 0x1)
5544 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5545 if (dcb->version < 0x22) {
6ee73861
BS		 5546 mask = ~0xd;
5547 /*
5548 * The laptop in bug 14567 lies and claims to not use
5549 * straps when it does, so assume all DCB 2.0 laptops
5550 * use straps, until a broken EDID using one is produced
5551 */
5552 entry->lvdsconf.use_straps_for_mode = true;
5553 /*
5554 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5555 * mean the same thing (probably wrong, but might work)
5556 */
5557 if (conf & 0x4 || conf & 0x8)
5558 entry->lvdsconf.use_power_scripts = true;
5559 } else {
5560 mask = ~0x5;
5561 if (conf & 0x4)
5562 entry->lvdsconf.use_power_scripts = true;
5563 }
5564 if (conf & mask) {
5565 /*
5566 * Until we even try to use these on G8x, it's
5567 * useless reporting unknown bits. They all are.
5568 */
7f245b20 5569 if (dcb->version >= 0x40)
6ee73861
BS		 5570 break;
5571
5572 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5573 "please report\n");
5574 }
5575 break;
5576 }
5577 case OUTPUT_TV:
5578 {
7f245b20 5579 if (dcb->version >= 0x30)
6ee73861
BS		 5580 entry->tvconf.has_component_output = conf & (0x8 << 4);
5581 else
5582 entry->tvconf.has_component_output = false;
5583
5584 break;
5585 }
5586 case OUTPUT_DP:
5587 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5588 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5589 switch ((conf & 0x0f000000) >> 24) {
5590 case 0xf:
5591 entry->dpconf.link_nr = 4;
5592 break;
5593 case 0x3:
5594 entry->dpconf.link_nr = 2;
5595 break;
5596 default:
5597 entry->dpconf.link_nr = 1;
5598 break;
5599 }
5600 break;
5601 case OUTPUT_TMDS:
5602 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5603 break;
5604 case 0xe:
5605 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 5606 dcb->entries--;
6ee73861 5607 return false;
e7cc51c5
BS		 5608 default:
5609 break;
6ee73861
BS		 5610 }
5611
5612 /* unsure what DCB version introduces this, 3.0? */
5613 if (conf & 0x100000)
5614 entry->i2c_upper_default = true;
5615
5616 return true;
5617}
5618
5619static bool
7f245b20 5620parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5621 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5622{
b0d2de86
BS		 5623 switch (conn & 0x0000000f) {
5624 case 0:
5625 entry->type = OUTPUT_ANALOG;
5626 break;
5627 case 1:
5628 entry->type = OUTPUT_TV;
5629 break;
5630 case 2:
5631 case 3:
6ee73861 5632 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 5633 break;
5634 case 4:
5635 switch ((conn & 0x000000f0) >> 4) {
5636 case 0:
6ee73861 5637 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 5638 break;
5639 case 1:
5640 entry->type = OUTPUT_LVDS;
5641 break;
5642 default:
5643 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5644 (conn & 0x000000f0) >> 4);
5645 return false;
5646 }
5647 break;
5648 default:
5649 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5650 return false;
6ee73861 5651 }
b0d2de86
BS		 5652
5653 entry->i2c_index = (conn & 0x0003c000) >> 14;
5654 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5655 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5656 entry->location = (conn & 0x01e00000) >> 21;
5657 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 5658 entry->duallink_possible = false;
5659
5660 switch (entry->type) {
5661 case OUTPUT_ANALOG:
5662 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5663 break;
b0d2de86
BS		 5664 case OUTPUT_TV:
5665 entry->tvconf.has_component_output = false;
6ee73861
BS		 5666 break;
5667 case OUTPUT_TMDS:
5668 /*
5669 * Invent a DVI-A output, by copying the fields of the DVI-D
5670 * output; reported to work by math_b on an NV20(!).
5671 */
5672 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5673 break;
b0d2de86
BS		 5674 case OUTPUT_LVDS:
5675 if ((conn & 0x00003f00) != 0x10)
5676 entry->lvdsconf.use_straps_for_mode = true;
5677 entry->lvdsconf.use_power_scripts = true;
5678 break;
5679 default:
6ee73861
BS		 5680 break;
5681 }
5682
5683 return true;
5684}
5685
7f245b20 5686static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5687 uint32_t conn, uint32_t conf)
5688{
7f245b20 5689 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 5690 bool ret;
5691
7f245b20
BS		 5692 if (dcb->version >= 0x20)
5693 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 5694 else
7f245b20 5695 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 5696 if (!ret)
5697 return ret;
5698
7f245b20
BS		 5699 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
5700 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 5701
5702 return true;
5703}
5704
5705static
7f245b20 5706void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 5707{
5708 /*
5709 * DCB v2.0 lists each output combination separately.
5710 * Here we merge compatible entries to have fewer outputs, with
5711 * more options
5712 */
5713
5714 int i, newentries = 0;
5715
5716 for (i = 0; i < dcb->entries; i++) {
5717 struct dcb_entry *ient = &dcb->entry[i];
5718 int j;
5719
5720 for (j = i + 1; j < dcb->entries; j++) {
5721 struct dcb_entry *jent = &dcb->entry[j];
5722
5723 if (jent->type == 100) /* already merged entry */
5724 continue;
5725
5726 /* merge heads field when all other fields the same */
5727 if (jent->i2c_index == ient->i2c_index &&
5728 jent->type == ient->type &&
5729 jent->location == ient->location &&
5730 jent->or == ient->or) {
5731 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5732 i, j);
5733 ient->heads |= jent->heads;
5734 jent->type = 100; /* dummy value */
5735 }
5736 }
5737 }
5738
5739 /* Compact entries merged into others out of dcb */
5740 for (i = 0; i < dcb->entries; i++) {
5741 if (dcb->entry[i].type == 100)
5742 continue;
5743
5744 if (newentries != i) {
5745 dcb->entry[newentries] = dcb->entry[i];
5746 dcb->entry[newentries].index = newentries;
5747 }
5748 newentries++;
5749 }
5750
5751 dcb->entries = newentries;
5752}
5753
ed42f824
BS		 5754static int
5755parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 5756{
ed42f824 5757 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 5758 struct dcb_table *dcb = &bios->dcb;
ed42f824 5759 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 5760 uint8_t *dcbtable;
5761 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5762 bool configblock = true;
5763 int recordlength = 8, confofs = 4;
5764 int i;
5765
6ee73861 5766 /* get the offset from 0x36 */
ed42f824
BS		 5767 if (dev_priv->card_type > NV_04) {
5768 dcbptr = ROM16(bios->data[0x36]);
5769 if (dcbptr == 0x0000)
5770 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5771 }
6ee73861 5772
ed42f824 5773 /* this situation likely means a really old card, pre DCB */
6ee73861 5774 if (dcbptr == 0x0) {
ed42f824 5775 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 5776 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5777
ed42f824 5778 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 5779 fabricate_tv_output(dcb, twoHeads);
5780
5781 return 0;
5782 }
5783
5784 dcbtable = &bios->data[dcbptr];
5785
5786 /* get DCB version */
7f245b20 5787 dcb->version = dcbtable[0];
6ee73861 5788 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 5789 dcb->version >> 4, dcb->version & 0xf);
6ee73861 5790
7f245b20 5791 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 5792 uint32_t sig;
5793
7f245b20 5794 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 5795 headerlen = dcbtable[1];
5796 entries = dcbtable[2];
5797 recordlength = dcbtable[3];
5798 i2ctabptr = ROM16(dcbtable[4]);
5799 sig = ROM32(dcbtable[6]);
7f245b20
BS		 5800 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
5801 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 5802 } else {
5803 i2ctabptr = ROM16(dcbtable[2]);
5804 sig = ROM32(dcbtable[4]);
5805 headerlen = 8;
5806 }
5807
5808 if (sig != 0x4edcbdcb) {
5809 NV_ERROR(dev, "Bad Display Configuration Block "
5810 "signature (%08X)\n", sig);
5811 return -EINVAL;
5812 }
7f245b20 5813 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 5814 char sig[8] = { 0 };
5815
5816 strncpy(sig, (char *)&dcbtable[-7], 7);
5817 i2ctabptr = ROM16(dcbtable[2]);
5818 recordlength = 10;
5819 confofs = 6;
5820
5821 if (strcmp(sig, "DEV_REC")) {
5822 NV_ERROR(dev, "Bad Display Configuration Block "
5823 "signature (%s)\n", sig);
5824 return -EINVAL;
5825 }
5826 } else {
5827 /*
5828 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5829 * has the same single (crt) entry, even when tv-out present, so
5830 * the conclusion is this version cannot really be used.
5831 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5832 * 5 entries, which are not specific to the card and so no use.
5833 * v1.2 does have an I2C table that read_dcb_i2c_table can
5834 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5835 * pointer, so use the indices parsed in parse_bmp_structure.
5836 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5837 */
5838 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5839 "adding all possible outputs\n");
5840 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5841
5842 /*
5843 * Attempt to detect TV before DVI because the test
5844 * for the former is more accurate and it rules the
5845 * latter out.
5846 */
5847 if (nv04_tv_identify(dev,
5848 bios->legacy.i2c_indices.tv) >= 0)
5849 fabricate_tv_output(dcb, twoHeads);
5850
5851 else if (bios->tmds.output0_script_ptr ||
5852 bios->tmds.output1_script_ptr)
5853 fabricate_dvi_i_output(dcb, twoHeads);
5854
5855 return 0;
5856 }
5857
5858 if (!i2ctabptr)
5859 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5860 else {
7f245b20
BS		 5861 dcb->i2c_table = &bios->data[i2ctabptr];
5862 if (dcb->version >= 0x30)
5863 dcb->i2c_default_indices = dcb->i2c_table[4];
6ee73861
BS		 5864 }
5865
6ee73861
BS		 5866 if (entries > DCB_MAX_NUM_ENTRIES)
5867 entries = DCB_MAX_NUM_ENTRIES;
5868
5869 for (i = 0; i < entries; i++) {
5870 uint32_t connection, config = 0;
5871
5872 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5873 if (configblock)
5874 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5875
5876 /* seen on an NV11 with DCB v1.5 */
5877 if (connection == 0x00000000)
5878 break;
5879
5880 /* seen on an NV17 with DCB v2.0 */
5881 if (connection == 0xffffffff)
5882 break;
5883
5884 if ((connection & 0x0000000f) == 0x0000000f)
5885 continue;
5886
5887 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5888 dcb->entries, connection, config);
5889
7f245b20 5890 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 5891 break;
5892 }
5893
5894 /*
5895 * apart for v2.1+ not being known for requiring merging, this
5896 * guarantees dcbent->index is the index of the entry in the rom image
5897 */
7f245b20 5898 if (dcb->version < 0x21)
6ee73861
BS		 5899 merge_like_dcb_entries(dev, dcb);
5900
54abb5dd
BS		 5901 if (!dcb->entries)
5902 return -ENXIO;
5903
5904 parse_dcb_gpio_table(bios);
5905 parse_dcb_connector_table(bios);
5906 return 0;
6ee73861
BS		 5907}
5908
5909static void
5910fixup_legacy_connector(struct nvbios *bios)
5911{
7f245b20 5912 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 5913 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 5914
5915 /*
5916 * DCB 3.0 also has the table in most cases, but there are some cards
5917 * where the table is filled with stub entries, and the DCB entriy
5918 * indices are all 0. We don't need the connector indices on pre-G80
5919 * chips (yet?) so limit the use to DCB 4.0 and above.
5920 */
7f245b20 5921 if (dcb->version >= 0x40)
6ee73861
BS		 5922 return;
5923
dc5bc4ed
BS		 5924 dcb->connector.entries = 0;
5925
6ee73861
BS		 5926 /*
5927 * No known connector info before v3.0, so make it up. the rule here
5928 * is: anything on the same i2c bus is considered to be on the same
5929 * connector. any output without an associated i2c bus is assigned
5930 * its own unique connector index.
5931 */
5932 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 5933 /*
5934 * Ignore the I2C index for on-chip TV-out, as there
5935 * are cards with bogus values (nv31m in bug 23212),
5936 * and it's otherwise useless.
5937 */
5938 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 5939 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 5940 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 5941 i2c = dcb->entry[i].i2c_index;
5942
5943 if (i2c_conn[i2c]) {
5944 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 5945 continue;
5946 }
5947
dc5bc4ed
BS		 5948 dcb->entry[i].connector = dcb->connector.entries++;
5949 if (i2c != 0xf)
5950 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 5951 }
5952
dc5bc4ed
BS		 5953 /* Fake the connector table as well as just connector indices */
5954 for (i = 0; i < dcb->connector.entries; i++) {
5955 dcb->connector.entry[i].index = i;
5956 dcb->connector.entry[i].type = divine_connector_type(bios, i);
5957 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 5958 }
5959}
5960
5961static void
5962fixup_legacy_i2c(struct nvbios *bios)
5963{
7f245b20 5964 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 5965 int i;
5966
5967 for (i = 0; i < dcb->entries; i++) {
5968 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
5969 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
5970 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
5971 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
5972 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
5973 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
5974 }
5975}
5976
5977static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5978{
5979 /*
5980 * The header following the "HWSQ" signature has the number of entries,
5981 * and the entry size
5982 *
5983 * An entry consists of a dword to write to the sequencer control reg
5984 * (0x00001304), followed by the ucode bytes, written sequentially,
5985 * starting at reg 0x00001400
5986 */
5987
5988 uint8_t bytes_to_write;
5989 uint16_t hwsq_entry_offset;
5990 int i;
5991
5992 if (bios->data[hwsq_offset] <= entry) {
5993 NV_ERROR(dev, "Too few entries in HW sequencer table for "
5994 "requested entry\n");
5995 return -ENOENT;
5996 }
5997
5998 bytes_to_write = bios->data[hwsq_offset + 1];
5999
6000 if (bytes_to_write != 36) {
6001 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6002 return -EINVAL;
6003 }
6004
6005 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6006
6007 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6008
6009 /* set sequencer control */
6010 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6011 bytes_to_write -= 4;
6012
6013 /* write ucode */
6014 for (i = 0; i < bytes_to_write; i += 4)
6015 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6016
6017 /* twiddle NV_PBUS_DEBUG_4 */
6018 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6019
6020 return 0;
6021}
6022
6023static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6024 struct nvbios *bios)
6025{
6026 /*
6027 * BMP based cards, from NV17, need a microcode loading to correctly
6028 * control the GPIO etc for LVDS panels
6029 *
6030 * BIT based cards seem to do this directly in the init scripts
6031 *
6032 * The microcode entries are found by the "HWSQ" signature.
6033 */
6034
6035 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6036 const int sz = sizeof(hwsq_signature);
6037 int hwsq_offset;
6038
6039 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6040 if (!hwsq_offset)
6041 return 0;
6042
6043 /* always use entry 0? */
6044 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6045}
6046
6047uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6048{
6049 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6050 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6051 const uint8_t edid_sig[] = {
6052 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6053 uint16_t offset = 0;
6054 uint16_t newoffset;
6055 int searchlen = NV_PROM_SIZE;
6056
6057 if (bios->fp.edid)
6058 return bios->fp.edid;
6059
6060 while (searchlen) {
6061 newoffset = findstr(&bios->data[offset], searchlen,
6062 edid_sig, 8);
6063 if (!newoffset)
6064 return NULL;
6065 offset += newoffset;
6066 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6067 break;
6068
6069 searchlen -= offset;
6070 offset++;
6071 }
6072
6073 NV_TRACE(dev, "Found EDID in BIOS\n");
6074
6075 return bios->fp.edid = &bios->data[offset];
6076}
6077
6078void
6079nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6080 struct dcb_entry *dcbent)
6081{
6082 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6083 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6084 struct init_exec iexec = { true, false };
6085
d9184fa9 6086 mutex_lock(&bios->lock);
6ee73861
BS		 6087 bios->display.output = dcbent;
6088 parse_init_table(bios, table, &iexec);
6089 bios->display.output = NULL;
d9184fa9 6090 mutex_unlock(&bios->lock);
6ee73861
BS		 6091}
6092
6093static bool NVInitVBIOS(struct drm_device *dev)
6094{
6095 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6096 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6097
6098 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 6099 mutex_init(&bios->lock);
6ee73861
BS		 6100 bios->dev = dev;
6101
6102 if (!NVShadowVBIOS(dev, bios->data))
6103 return false;
6104
6105 bios->length = NV_PROM_SIZE;
6106 return true;
6107}
6108
6109static int nouveau_parse_vbios_struct(struct drm_device *dev)
6110{
6111 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6112 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6113 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6114 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6115 int offset;
6116
6117 offset = findstr(bios->data, bios->length,
6118 bit_signature, sizeof(bit_signature));
6119 if (offset) {
6120 NV_TRACE(dev, "BIT BIOS found\n");
6121 return parse_bit_structure(bios, offset + 6);
6122 }
6123
6124 offset = findstr(bios->data, bios->length,
6125 bmp_signature, sizeof(bmp_signature));
6126 if (offset) {
6127 NV_TRACE(dev, "BMP BIOS found\n");
6128 return parse_bmp_structure(dev, bios, offset);
6129 }
6130
6131 NV_ERROR(dev, "No known BIOS signature found\n");
6132 return -ENODEV;
6133}
6134
6135int
6136nouveau_run_vbios_init(struct drm_device *dev)
6137{
6138 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6139 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6140 int i, ret = 0;
6141
6142 NVLockVgaCrtcs(dev, false);
6143 if (nv_two_heads(dev))
6144 NVSetOwner(dev, bios->state.crtchead);
6145
6146 if (bios->major_version < 5) /* BMP only */
6147 load_nv17_hw_sequencer_ucode(dev, bios);
6148
6149 if (bios->execute) {
6150 bios->fp.last_script_invoc = 0;
6151 bios->fp.lvds_init_run = false;
6152 }
6153
6154 parse_init_tables(bios);
6155
6156 /*
6157 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6158 * parser will run this right after the init tables, the binary
6159 * driver appears to run it at some point later.
6160 */
6161 if (bios->some_script_ptr) {
6162 struct init_exec iexec = {true, false};
6163
6164 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6165 bios->some_script_ptr);
6166 parse_init_table(bios, bios->some_script_ptr, &iexec);
6167 }
6168
6169 if (dev_priv->card_type >= NV_50) {
7f245b20 6170 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6171 nouveau_bios_run_display_table(dev,
7f245b20 6172 &bios->dcb.entry[i],
6ee73861
BS		 6173 0, 0);
6174 }
6175 }
6176
6177 NVLockVgaCrtcs(dev, true);
6178
6179 return ret;
6180}
6181
6182static void
6183nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6184{
6185 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6186 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6187 struct dcb_i2c_entry *entry;
6188 int i;
6189
7f245b20 6190 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6191 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6192 nouveau_i2c_fini(dev, entry);
6193}
6194
6195int
6196nouveau_bios_init(struct drm_device *dev)
6197{
6198 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6199 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6200 uint32_t saved_nv_pextdev_boot_0;
6201 bool was_locked;
6202 int ret;
6203
6ee73861
BS		 6204 if (!NVInitVBIOS(dev))
6205 return -ENODEV;
6206
6207 ret = nouveau_parse_vbios_struct(dev);
6208 if (ret)
6209 return ret;
6210
6211 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6212 if (ret)
6213 return ret;
6214
6215 fixup_legacy_i2c(bios);
6216 fixup_legacy_connector(bios);
6217
6218 if (!bios->major_version) /* we don't run version 0 bios */
6219 return 0;
6220
6221 /* these will need remembering across a suspend */
6222 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6223 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6224
6225 /* init script execution disabled */
6226 bios->execute = false;
6227
6228 /* ... unless card isn't POSTed already */
6229 if (dev_priv->card_type >= NV_10 &&
6230 NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6231 NVReadVgaCrtc(dev, 0, 0x1a) == 0) {
6232 NV_INFO(dev, "Adaptor not initialised\n");
6233 if (dev_priv->card_type < NV_50) {
6234 NV_ERROR(dev, "Unable to POST this chipset\n");
6235 return -ENODEV;
6236 }
6237
6238 NV_INFO(dev, "Running VBIOS init tables\n");
6239 bios->execute = true;
6240 }
6241
6242 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6243
6244 ret = nouveau_run_vbios_init(dev);
04a39c57 6245 if (ret)
6ee73861 6246 return ret;
6ee73861
BS		 6247
6248 /* feature_byte on BMP is poor, but init always sets CR4B */
6249 was_locked = NVLockVgaCrtcs(dev, false);
6250 if (bios->major_version < 5)
6251 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6252
6253 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6254 if (bios->is_mobile || bios->major_version >= 5)
6255 ret = parse_fp_mode_table(dev, bios);
6256 NVLockVgaCrtcs(dev, was_locked);
6257
6258 /* allow subsequent scripts to execute */
6259 bios->execute = true;
6260
6261 return 0;
6262}
6263
6264void
6265nouveau_bios_takedown(struct drm_device *dev)
6266{
6267 nouveau_bios_i2c_devices_takedown(dev);
6268}
Clone of davem's net-next-2.6 tree