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[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
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6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861 30
67eda20e
FJ		 31#include <linux/io-mapping.h>
32
6ee73861
BS		 33/* these defines are made up */
34#define NV_CIO_CRE_44_HEADA 0x0
35#define NV_CIO_CRE_44_HEADB 0x3
36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
37#define LEGACY_I2C_CRT 0x80
38#define LEGACY_I2C_PANEL 0x81
39#define LEGACY_I2C_TV 0x82
40
41#define EDID1_LEN 128
42
43#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
44#define LOG_OLD_VALUE(x)
45
46#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
47#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
48
49struct init_exec {
50 bool execute;
51 bool repeat;
52};
53
54static bool nv_cksum(const uint8_t *data, unsigned int length)
55{
56 /*
57 * There's a few checksums in the BIOS, so here's a generic checking
58 * function.
59 */
60 int i;
61 uint8_t sum = 0;
62
63 for (i = 0; i < length; i++)
64 sum += data[i];
65
66 if (sum)
67 return true;
68
69 return false;
70}
71
72static int
73score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
74{
75 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
76 NV_TRACEWARN(dev, "... BIOS signature not found\n");
77 return 0;
78 }
79
80 if (nv_cksum(data, data[2] * 512)) {
81 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
82 /* if a ro image is somewhat bad, it's probably all rubbish */
83 return writeable ? 2 : 1;
84 } else
85 NV_TRACE(dev, "... appears to be valid\n");
86
87 return 3;
88}
89
90static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
91{
92 struct drm_nouveau_private *dev_priv = dev->dev_private;
93 uint32_t pci_nv_20, save_pci_nv_20;
94 int pcir_ptr;
95 int i;
96
97 if (dev_priv->card_type >= NV_50)
98 pci_nv_20 = 0x88050;
99 else
100 pci_nv_20 = NV_PBUS_PCI_NV_20;
101
102 /* enable ROM access */
103 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
104 nvWriteMC(dev, pci_nv_20,
105 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
106
107 /* bail if no rom signature */
108 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
109 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
110 goto out;
111
112 /* additional check (see note below) - read PCI record header */
113 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
114 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
115 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
117 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
118 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
119 goto out;
120
121 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
122 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
123 * each byte. we'll hope pramin has something usable instead
124 */
125 for (i = 0; i < NV_PROM_SIZE; i++)
126 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
127
128out:
129 /* disable ROM access */
130 nvWriteMC(dev, pci_nv_20,
131 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
132}
133
134static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
135{
136 struct drm_nouveau_private *dev_priv = dev->dev_private;
137 uint32_t old_bar0_pramin = 0;
138 int i;
139
140 if (dev_priv->card_type >= NV_50) {
141 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
142
143 if (!vbios_vram)
144 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
145
146 old_bar0_pramin = nv_rd32(dev, 0x1700);
147 nv_wr32(dev, 0x1700, vbios_vram >> 16);
148 }
149
150 /* bail if no rom signature */
151 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
152 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
153 goto out;
154
155 for (i = 0; i < NV_PROM_SIZE; i++)
156 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
157
158out:
159 if (dev_priv->card_type >= NV_50)
160 nv_wr32(dev, 0x1700, old_bar0_pramin);
161}
162
163static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
164{
165 void __iomem *rom = NULL;
166 size_t rom_len;
167 int ret;
168
169 ret = pci_enable_rom(dev->pdev);
170 if (ret)
171 return;
172
173 rom = pci_map_rom(dev->pdev, &rom_len);
174 if (!rom)
175 goto out;
176 memcpy_fromio(data, rom, rom_len);
177 pci_unmap_rom(dev->pdev, rom);
178
179out:
180 pci_disable_rom(dev->pdev);
181}
182
afeb3e11
DA		 183static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
184{
185 int i;
186 int ret;
187 int size = 64 * 1024;
188
189 if (!nouveau_acpi_rom_supported(dev->pdev))
190 return;
191
192 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
193 ret = nouveau_acpi_get_bios_chunk(data,
194 (i * ROM_BIOS_PAGE),
195 ROM_BIOS_PAGE);
196 if (ret <= 0)
197 break;
198 }
199 return;
200}
201
6ee73861
BS		 202struct methods {
203 const char desc[8];
204 void (*loadbios)(struct drm_device *, uint8_t *);
205 const bool rw;
6ee73861
BS		 206};
207
41090eb4 208static struct methods shadow_methods[] = {
6ee73861
BS		 209 { "PRAMIN", load_vbios_pramin, true },
210 { "PROM", load_vbios_prom, false },
211 { "PCIROM", load_vbios_pci, true },
41090eb4 212 { "ACPI", load_vbios_acpi, true },
6ee73861 213};
eae6192a 214#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
6ee73861
BS		 215
216static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
217{
41090eb4 218 struct methods *methods = shadow_methods;
6ee73861 219 int testscore = 3;
eae6192a 220 int scores[NUM_SHADOW_METHODS], i;
6ee73861
BS		 221
222 if (nouveau_vbios) {
eae6192a 223 for (i = 0; i < NUM_SHADOW_METHODS; i++)
657b6245 224 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 225 break;
6ee73861 226
eae6192a 227 if (i < NUM_SHADOW_METHODS) {
6ee73861 228 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 229 methods[i].desc);
6ee73861 230
657b6245
MK		 231 methods[i].loadbios(dev, data);
232 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 233 return true;
234 }
235
236 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
237 }
238
eae6192a 239 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
6ee73861 240 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 241 methods[i].desc);
6ee73861 242 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 243 methods[i].loadbios(dev, data);
244 scores[i] = score_vbios(dev, data, methods[i].rw);
245 if (scores[i] == testscore)
6ee73861 246 return true;
6ee73861
BS		 247 }
248
249 while (--testscore > 0) {
eae6192a 250 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
657b6245 251 if (scores[i] == testscore) {
6ee73861 252 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 253 methods[i].desc);
254 methods[i].loadbios(dev, data);
6ee73861
BS		 255 return true;
256 }
6ee73861
BS		 257 }
258 }
259
260 NV_ERROR(dev, "No valid BIOS image found\n");
261 return false;
262}
263
264struct init_tbl_entry {
265 char *name;
266 uint8_t id;
9170a824
BS		 267 /* Return:
268 * > 0: success, length of opcode
269 * 0: success, but abort further parsing of table (INIT_DONE etc)
270 * < 0: failure, table parsing will be aborted
271 */
37383650 272 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 273};
274
275struct bit_entry {
276 uint8_t id[2];
277 uint16_t length;
278 uint16_t offset;
279};
280
281static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
282
283#define MACRO_INDEX_SIZE 2
284#define MACRO_SIZE 8
285#define CONDITION_SIZE 12
286#define IO_FLAG_CONDITION_SIZE 9
287#define IO_CONDITION_SIZE 5
288#define MEM_INIT_SIZE 66
289
290static void still_alive(void)
291{
292#if 0
293 sync();
294 msleep(2);
295#endif
296}
297
298static uint32_t
299munge_reg(struct nvbios *bios, uint32_t reg)
300{
301 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
302 struct dcb_entry *dcbent = bios->display.output;
303
304 if (dev_priv->card_type < NV_50)
305 return reg;
306
307 if (reg & 0x40000000) {
308 BUG_ON(!dcbent);
309
310 reg += (ffs(dcbent->or) - 1) * 0x800;
311 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
312 reg += 0x00000080;
313 }
314
315 reg &= ~0x60000000;
316 return reg;
317}
318
319static int
320valid_reg(struct nvbios *bios, uint32_t reg)
321{
322 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
323 struct drm_device *dev = bios->dev;
324
325 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 326 if (reg & 0x2 ||
04a39c57 327 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 328 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
329
330 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 331 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 332 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
333 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
334 reg);
335
9855e584
BS		 336 if (reg >= (8*1024*1024)) {
337 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
338 return 0;
6ee73861 339 }
9855e584
BS		 340
341 return 1;
6ee73861
BS		 342}
343
344static bool
345valid_idx_port(struct nvbios *bios, uint16_t port)
346{
347 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
348 struct drm_device *dev = bios->dev;
349
350 /*
351 * If adding more ports here, the read/write functions below will need
352 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
353 * used for the port in question
354 */
355 if (dev_priv->card_type < NV_50) {
356 if (port == NV_CIO_CRX__COLOR)
357 return true;
358 if (port == NV_VIO_SRX)
359 return true;
360 } else {
361 if (port == NV_CIO_CRX__COLOR)
362 return true;
363 }
364
365 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
366 port);
367
368 return false;
369}
370
371static bool
372valid_port(struct nvbios *bios, uint16_t port)
373{
374 struct drm_device *dev = bios->dev;
375
376 /*
377 * If adding more ports here, the read/write functions below will need
378 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
379 * used for the port in question
380 */
381 if (port == NV_VIO_VSE2)
382 return true;
383
384 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
385
386 return false;
387}
388
389static uint32_t
390bios_rd32(struct nvbios *bios, uint32_t reg)
391{
392 uint32_t data;
393
394 reg = munge_reg(bios, reg);
395 if (!valid_reg(bios, reg))
396 return 0;
397
398 /*
399 * C51 sometimes uses regs with bit0 set in the address. For these
400 * cases there should exist a translation in a BIOS table to an IO
401 * port address which the BIOS uses for accessing the reg
402 *
403 * These only seem to appear for the power control regs to a flat panel,
404 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
405 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
406 * suspend-resume mmio trace from a C51 will be required to see if this
407 * is true for the power microcode in 0x14.., or whether the direct IO
408 * port access method is needed
409 */
410 if (reg & 0x1)
411 reg &= ~0x1;
412
413 data = nv_rd32(bios->dev, reg);
414
415 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
416
417 return data;
418}
419
420static void
421bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
422{
423 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
424
425 reg = munge_reg(bios, reg);
426 if (!valid_reg(bios, reg))
427 return;
428
429 /* see note in bios_rd32 */
430 if (reg & 0x1)
431 reg &= 0xfffffffe;
432
433 LOG_OLD_VALUE(bios_rd32(bios, reg));
434 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
435
04a39c57 436 if (dev_priv->vbios.execute) {
6ee73861
BS		 437 still_alive();
438 nv_wr32(bios->dev, reg, data);
439 }
440}
441
442static uint8_t
443bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
444{
445 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
446 struct drm_device *dev = bios->dev;
447 uint8_t data;
448
449 if (!valid_idx_port(bios, port))
450 return 0;
451
452 if (dev_priv->card_type < NV_50) {
453 if (port == NV_VIO_SRX)
454 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
455 else /* assume NV_CIO_CRX__COLOR */
456 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
457 } else {
458 uint32_t data32;
459
460 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
461 data = (data32 >> ((index & 3) << 3)) & 0xff;
462 }
463
464 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
465 "Head: 0x%02X, Data: 0x%02X\n",
466 port, index, bios->state.crtchead, data);
467 return data;
468}
469
470static void
471bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
472{
473 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
474 struct drm_device *dev = bios->dev;
475
476 if (!valid_idx_port(bios, port))
477 return;
478
479 /*
480 * The current head is maintained in the nvbios member state.crtchead.
481 * We trap changes to CR44 and update the head variable and hence the
482 * register set written.
483 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
484 * of the write, and to head1 after the write
485 */
486 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
487 data != NV_CIO_CRE_44_HEADB)
488 bios->state.crtchead = 0;
489
490 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
491 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
492 "Head: 0x%02X, Data: 0x%02X\n",
493 port, index, bios->state.crtchead, data);
494
495 if (bios->execute && dev_priv->card_type < NV_50) {
496 still_alive();
497 if (port == NV_VIO_SRX)
498 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
499 else /* assume NV_CIO_CRX__COLOR */
500 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
501 } else
502 if (bios->execute) {
503 uint32_t data32, shift = (index & 3) << 3;
504
505 still_alive();
506
507 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
508 data32 &= ~(0xff << shift);
509 data32 |= (data << shift);
510 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
511 }
512
513 if (port == NV_CIO_CRX__COLOR &&
514 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
515 bios->state.crtchead = 1;
516}
517
518static uint8_t
519bios_port_rd(struct nvbios *bios, uint16_t port)
520{
521 uint8_t data, head = bios->state.crtchead;
522
523 if (!valid_port(bios, port))
524 return 0;
525
526 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
527
528 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
529 port, head, data);
530
531 return data;
532}
533
534static void
535bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
536{
537 int head = bios->state.crtchead;
538
539 if (!valid_port(bios, port))
540 return;
541
542 LOG_OLD_VALUE(bios_port_rd(bios, port));
543 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
544 port, head, data);
545
546 if (!bios->execute)
547 return;
548
549 still_alive();
550 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
551}
552
553static bool
554io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
555{
556 /*
557 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
558 * for the CRTC index; 1 byte for the mask to apply to the value
559 * retrieved from the CRTC; 1 byte for the shift right to apply to the
560 * masked CRTC value; 2 bytes for the offset to the flag array, to
561 * which the shifted value is added; 1 byte for the mask applied to the
562 * value read from the flag array; and 1 byte for the value to compare
563 * against the masked byte from the flag table.
564 */
565
566 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
567 uint16_t crtcport = ROM16(bios->data[condptr]);
568 uint8_t crtcindex = bios->data[condptr + 2];
569 uint8_t mask = bios->data[condptr + 3];
570 uint8_t shift = bios->data[condptr + 4];
571 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
572 uint8_t flagarraymask = bios->data[condptr + 7];
573 uint8_t cmpval = bios->data[condptr + 8];
574 uint8_t data;
575
576 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
577 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
578 "Cmpval: 0x%02X\n",
579 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
580
581 data = bios_idxprt_rd(bios, crtcport, crtcindex);
582
583 data = bios->data[flagarray + ((data & mask) >> shift)];
584 data &= flagarraymask;
585
586 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
587 offset, data, cmpval);
588
589 return (data == cmpval);
590}
591
592static bool
593bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
594{
595 /*
596 * The condition table entry has 4 bytes for the address of the
597 * register to check, 4 bytes for a mask to apply to the register and
598 * 4 for a test comparison value
599 */
600
601 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
602 uint32_t reg = ROM32(bios->data[condptr]);
603 uint32_t mask = ROM32(bios->data[condptr + 4]);
604 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
605 uint32_t data;
606
607 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
608 offset, cond, reg, mask);
609
610 data = bios_rd32(bios, reg) & mask;
611
612 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
613 offset, data, cmpval);
614
615 return (data == cmpval);
616}
617
618static bool
619io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
620{
621 /*
622 * The IO condition entry has 2 bytes for the IO port address; 1 byte
623 * for the index to write to io_port; 1 byte for the mask to apply to
624 * the byte read from io_port+1; and 1 byte for the value to compare
625 * against the masked byte.
626 */
627
628 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
629 uint16_t io_port = ROM16(bios->data[condptr]);
630 uint8_t port_index = bios->data[condptr + 2];
631 uint8_t mask = bios->data[condptr + 3];
632 uint8_t cmpval = bios->data[condptr + 4];
633
634 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
635
636 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
637 offset, data, cmpval);
638
639 return (data == cmpval);
640}
641
642static int
643nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
644{
645 struct drm_nouveau_private *dev_priv = dev->dev_private;
646 uint32_t reg0 = nv_rd32(dev, reg + 0);
647 uint32_t reg1 = nv_rd32(dev, reg + 4);
648 struct nouveau_pll_vals pll;
649 struct pll_lims pll_limits;
650 int ret;
651
652 ret = get_pll_limits(dev, reg, &pll_limits);
653 if (ret)
654 return ret;
655
656 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
657 if (!clk)
658 return -ERANGE;
659
660 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
661 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
662
04a39c57 663 if (dev_priv->vbios.execute) {
6ee73861
BS		 664 still_alive();
665 nv_wr32(dev, reg + 4, reg1);
666 nv_wr32(dev, reg + 0, reg0);
667 }
668
669 return 0;
670}
671
672static int
673setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
674{
675 struct drm_device *dev = bios->dev;
676 struct drm_nouveau_private *dev_priv = dev->dev_private;
677 /* clk in kHz */
678 struct pll_lims pll_lim;
679 struct nouveau_pll_vals pllvals;
680 int ret;
681
682 if (dev_priv->card_type >= NV_50)
683 return nv50_pll_set(dev, reg, clk);
684
685 /* high regs (such as in the mac g5 table) are not -= 4 */
686 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
687 if (ret)
688 return ret;
689
690 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
691 if (!clk)
692 return -ERANGE;
693
694 if (bios->execute) {
695 still_alive();
696 nouveau_hw_setpll(dev, reg, &pllvals);
697 }
698
699 return 0;
700}
701
702static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
703{
704 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 705 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 706
707 /*
708 * For the results of this function to be correct, CR44 must have been
709 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
710 * and the DCB table parsed, before the script calling the function is
711 * run. run_digital_op_script is example of how to do such setup
712 */
713
714 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
715
7f245b20 716 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 717 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
718 "(%02X)\n", dcb_entry);
719 dcb_entry = 0x7f; /* unused / invalid marker */
720 }
721
722 return dcb_entry;
723}
724
f8b0be1a
BS		 725static int
726read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
727{
728 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
729 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
730 int recordoffset = 0, rdofs = 1, wrofs = 0;
731 uint8_t port_type = 0;
732
733 if (!i2ctable)
734 return -EINVAL;
735
736 if (dcb_version >= 0x30) {
737 if (i2ctable[0] != dcb_version) /* necessary? */
738 NV_WARN(dev,
739 "DCB I2C table version mismatch (%02X vs %02X)\n",
740 i2ctable[0], dcb_version);
741 dcb_i2c_ver = i2ctable[0];
742 headerlen = i2ctable[1];
743 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
744 i2c_entries = i2ctable[2];
745 else
746 NV_WARN(dev,
747 "DCB I2C table has more entries than indexable "
748 "(%d entries, max %d)\n", i2ctable[2],
749 DCB_MAX_NUM_I2C_ENTRIES);
750 entry_len = i2ctable[3];
751 /* [4] is i2c_default_indices, read in parse_dcb_table() */
752 }
753 /*
754 * It's your own fault if you call this function on a DCB 1.1 BIOS --
755 * the test below is for DCB 1.2
756 */
757 if (dcb_version < 0x14) {
758 recordoffset = 2;
759 rdofs = 0;
760 wrofs = 1;
761 }
762
763 if (index == 0xf)
764 return 0;
765 if (index >= i2c_entries) {
766 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
767 index, i2ctable[2]);
768 return -ENOENT;
769 }
770 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
771 NV_ERROR(dev, "DCB I2C entry invalid\n");
772 return -EINVAL;
773 }
774
775 if (dcb_i2c_ver >= 0x30) {
776 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
777
778 /*
779 * Fixup for chips using same address offset for read and
780 * write.
781 */
782 if (port_type == 4) /* seen on C51 */
783 rdofs = wrofs = 1;
784 if (port_type >= 5) /* G80+ */
785 rdofs = wrofs = 0;
786 }
787
788 if (dcb_i2c_ver >= 0x40) {
789 if (port_type != 5 && port_type != 6)
790 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
791
792 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
793 }
794
795 i2c->port_type = port_type;
796 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
797 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
798
799 return 0;
800}
801
6ee73861
BS		 802static struct nouveau_i2c_chan *
803init_i2c_device_find(struct drm_device *dev, int i2c_index)
804{
805 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 806 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 807
808 if (i2c_index == 0xff) {
809 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
810 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 811 int default_indices = dcb->i2c_default_indices;
6ee73861 812
7f245b20 813 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 814 shift = 4;
815
816 i2c_index = (default_indices >> shift) & 0xf;
817 }
818 if (i2c_index == 0x80) /* g80+ */
7f245b20 819 i2c_index = dcb->i2c_default_indices & 0xf;
04f542c0
BS		 820 else
821 if (i2c_index == 0x81)
822 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
6ee73861 823
75047944 824 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
f8b0be1a
BS		 825 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
826 return NULL;
827 }
828
829 /* Make sure i2c table entry has been parsed, it may not
830 * have been if this is a bus not referenced by a DCB encoder
831 */
832 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
833 i2c_index, &dcb->i2c[i2c_index]);
834
6ee73861
BS		 835 return nouveau_i2c_find(dev, i2c_index);
836}
837
7f245b20
BS		 838static uint32_t
839get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 840{
841 /*
842 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
843 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
844 * CR58 for CR57 = 0 to index a table of offsets to the basic
845 * 0x6808b0 address.
846 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
847 * CR58 for CR57 = 0 to index a table of offsets to the basic
848 * 0x6808b0 address, and then flip the offset by 8.
849 */
850
851 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 852 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 853 const int pramdac_offset[13] = {
854 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
855 const uint32_t pramdac_table[4] = {
856 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
857
858 if (mlv >= 0x80) {
859 int dcb_entry, dacoffset;
860
861 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
862 dcb_entry = dcb_entry_idx_from_crtchead(dev);
863 if (dcb_entry == 0x7f)
864 return 0;
7f245b20 865 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 866 if (mlv == 0x81)
867 dacoffset ^= 8;
868 return 0x6808b0 + dacoffset;
869 } else {
df31ef4d 870 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 871 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
872 mlv);
873 return 0;
874 }
875 return pramdac_table[mlv];
876 }
877}
878
37383650 879static int
6ee73861
BS		 880init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
881 struct init_exec *iexec)
882{
883 /*
884 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
885 *
886 * offset (8 bit): opcode
887 * offset + 1 (16 bit): CRTC port
888 * offset + 3 (8 bit): CRTC index
889 * offset + 4 (8 bit): mask
890 * offset + 5 (8 bit): shift
891 * offset + 6 (8 bit): count
892 * offset + 7 (32 bit): register
893 * offset + 11 (32 bit): configuration 1
894 * ...
895 *
896 * Starting at offset + 11 there are "count" 32 bit values.
897 * To find out which value to use read index "CRTC index" on "CRTC
898 * port", AND this value with "mask" and then bit shift right "shift"
899 * bits. Read the appropriate value using this index and write to
900 * "register"
901 */
902
903 uint16_t crtcport = ROM16(bios->data[offset + 1]);
904 uint8_t crtcindex = bios->data[offset + 3];
905 uint8_t mask = bios->data[offset + 4];
906 uint8_t shift = bios->data[offset + 5];
907 uint8_t count = bios->data[offset + 6];
908 uint32_t reg = ROM32(bios->data[offset + 7]);
909 uint8_t config;
910 uint32_t configval;
37383650 911 int len = 11 + count * 4;
6ee73861
BS		 912
913 if (!iexec->execute)
37383650 914 return len;
6ee73861
BS		 915
916 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
917 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
918 offset, crtcport, crtcindex, mask, shift, count, reg);
919
920 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
921 if (config > count) {
922 NV_ERROR(bios->dev,
923 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
924 offset, config, count);
309b8c89 925 return len;
6ee73861
BS		 926 }
927
928 configval = ROM32(bios->data[offset + 11 + config * 4]);
929
930 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
931
932 bios_wr32(bios, reg, configval);
933
37383650 934 return len;
6ee73861
BS		 935}
936
37383650 937static int
6ee73861
BS		 938init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
939{
940 /*
941 * INIT_REPEAT opcode: 0x33 ('3')
942 *
943 * offset (8 bit): opcode
944 * offset + 1 (8 bit): count
945 *
946 * Execute script following this opcode up to INIT_REPEAT_END
947 * "count" times
948 */
949
950 uint8_t count = bios->data[offset + 1];
951 uint8_t i;
952
953 /* no iexec->execute check by design */
954
955 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
956 offset, count);
957
958 iexec->repeat = true;
959
960 /*
961 * count - 1, as the script block will execute once when we leave this
962 * opcode -- this is compatible with bios behaviour as:
963 * a) the block is always executed at least once, even if count == 0
964 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
965 * while we don't
966 */
967 for (i = 0; i < count - 1; i++)
968 parse_init_table(bios, offset + 2, iexec);
969
970 iexec->repeat = false;
971
37383650 972 return 2;
6ee73861
BS		 973}
974
37383650 975static int
6ee73861
BS		 976init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
977 struct init_exec *iexec)
978{
979 /*
980 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
981 *
982 * offset (8 bit): opcode
983 * offset + 1 (16 bit): CRTC port
984 * offset + 3 (8 bit): CRTC index
985 * offset + 4 (8 bit): mask
986 * offset + 5 (8 bit): shift
987 * offset + 6 (8 bit): IO flag condition index
988 * offset + 7 (8 bit): count
989 * offset + 8 (32 bit): register
990 * offset + 12 (16 bit): frequency 1
991 * ...
992 *
993 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
994 * Set PLL register "register" to coefficients for frequency n,
995 * selected by reading index "CRTC index" of "CRTC port" ANDed with
996 * "mask" and shifted right by "shift".
997 *
998 * If "IO flag condition index" > 0, and condition met, double
999 * frequency before setting it.
1000 */
1001
1002 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1003 uint8_t crtcindex = bios->data[offset + 3];
1004 uint8_t mask = bios->data[offset + 4];
1005 uint8_t shift = bios->data[offset + 5];
1006 int8_t io_flag_condition_idx = bios->data[offset + 6];
1007 uint8_t count = bios->data[offset + 7];
1008 uint32_t reg = ROM32(bios->data[offset + 8]);
1009 uint8_t config;
1010 uint16_t freq;
37383650 1011 int len = 12 + count * 2;
6ee73861
BS		 1012
1013 if (!iexec->execute)
37383650 1014 return len;
6ee73861
BS		 1015
1016 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1017 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1018 "Count: 0x%02X, Reg: 0x%08X\n",
1019 offset, crtcport, crtcindex, mask, shift,
1020 io_flag_condition_idx, count, reg);
1021
1022 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1023 if (config > count) {
1024 NV_ERROR(bios->dev,
1025 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1026 offset, config, count);
309b8c89 1027 return len;
6ee73861
BS		 1028 }
1029
1030 freq = ROM16(bios->data[offset + 12 + config * 2]);
1031
1032 if (io_flag_condition_idx > 0) {
1033 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1034 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1035 "frequency doubled\n", offset);
1036 freq *= 2;
1037 } else
1038 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1039 "frequency unchanged\n", offset);
1040 }
1041
1042 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1043 offset, reg, config, freq);
1044
1045 setPLL(bios, reg, freq * 10);
1046
37383650 1047 return len;
6ee73861
BS		 1048}
1049
37383650 1050static int
6ee73861
BS		 1051init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1052{
1053 /*
1054 * INIT_END_REPEAT opcode: 0x36 ('6')
1055 *
1056 * offset (8 bit): opcode
1057 *
1058 * Marks the end of the block for INIT_REPEAT to repeat
1059 */
1060
1061 /* no iexec->execute check by design */
1062
1063 /*
1064 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1065 * we're not in repeat mode
1066 */
1067 if (iexec->repeat)
37383650 1068 return 0;
6ee73861 1069
37383650 1070 return 1;
6ee73861
BS		 1071}
1072
37383650 1073static int
6ee73861
BS		 1074init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1075{
1076 /*
1077 * INIT_COPY opcode: 0x37 ('7')
1078 *
1079 * offset (8 bit): opcode
1080 * offset + 1 (32 bit): register
1081 * offset + 5 (8 bit): shift
1082 * offset + 6 (8 bit): srcmask
1083 * offset + 7 (16 bit): CRTC port
1084 * offset + 9 (8 bit): CRTC index
1085 * offset + 10 (8 bit): mask
1086 *
1087 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1088 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1089 * port
1090 */
1091
1092 uint32_t reg = ROM32(bios->data[offset + 1]);
1093 uint8_t shift = bios->data[offset + 5];
1094 uint8_t srcmask = bios->data[offset + 6];
1095 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1096 uint8_t crtcindex = bios->data[offset + 9];
1097 uint8_t mask = bios->data[offset + 10];
1098 uint32_t data;
1099 uint8_t crtcdata;
1100
1101 if (!iexec->execute)
37383650 1102 return 11;
6ee73861
BS		 1103
1104 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1105 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1106 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1107
1108 data = bios_rd32(bios, reg);
1109
1110 if (shift < 0x80)
1111 data >>= shift;
1112 else
1113 data <<= (0x100 - shift);
1114
1115 data &= srcmask;
1116
1117 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1118 crtcdata |= (uint8_t)data;
1119 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1120
37383650 1121 return 11;
6ee73861
BS		 1122}
1123
37383650 1124static int
6ee73861
BS		 1125init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1126{
1127 /*
1128 * INIT_NOT opcode: 0x38 ('8')
1129 *
1130 * offset (8 bit): opcode
1131 *
1132 * Invert the current execute / no-execute condition (i.e. "else")
1133 */
1134 if (iexec->execute)
1135 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1136 else
1137 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1138
1139 iexec->execute = !iexec->execute;
37383650 1140 return 1;
6ee73861
BS		 1141}
1142
37383650 1143static int
6ee73861
BS		 1144init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1145 struct init_exec *iexec)
1146{
1147 /*
1148 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1149 *
1150 * offset (8 bit): opcode
1151 * offset + 1 (8 bit): condition number
1152 *
1153 * Check condition "condition number" in the IO flag condition table.
1154 * If condition not met skip subsequent opcodes until condition is
1155 * inverted (INIT_NOT), or we hit INIT_RESUME
1156 */
1157
1158 uint8_t cond = bios->data[offset + 1];
1159
1160 if (!iexec->execute)
37383650 1161 return 2;
6ee73861
BS		 1162
1163 if (io_flag_condition_met(bios, offset, cond))
1164 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1165 else {
1166 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1167 iexec->execute = false;
1168 }
1169
37383650 1170 return 2;
6ee73861
BS		 1171}
1172
25908b77
BS		 1173static int
1174init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1175{
1176 /*
1177 * INIT_DP_CONDITION opcode: 0x3A ('')
1178 *
1179 * offset (8 bit): opcode
1180 * offset + 1 (8 bit): "sub" opcode
1181 * offset + 2 (8 bit): unknown
1182 *
1183 */
1184
1185 struct bit_displayport_encoder_table *dpe = NULL;
1186 struct dcb_entry *dcb = bios->display.output;
1187 struct drm_device *dev = bios->dev;
1188 uint8_t cond = bios->data[offset + 1];
1189 int dummy;
1190
1191 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1192
1193 if (!iexec->execute)
1194 return 3;
1195
1196 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1197 if (!dpe) {
1198 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
309b8c89 1199 return 3;
25908b77
BS		 1200 }
1201
1202 switch (cond) {
1203 case 0:
1204 {
1205 struct dcb_connector_table_entry *ent =
1206 &bios->dcb.connector.entry[dcb->connector];
1207
1208 if (ent->type != DCB_CONNECTOR_eDP)
1209 iexec->execute = false;
1210 }
1211 break;
1212 case 1:
1213 case 2:
1214 if (!(dpe->unknown & cond))
1215 iexec->execute = false;
1216 break;
1217 case 5:
1218 {
1219 struct nouveau_i2c_chan *auxch;
1220 int ret;
1221
1222 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
309b8c89
BS		 1223 if (!auxch) {
1224 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1225 return 3;
1226 }
25908b77
BS		 1227
1228 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
309b8c89
BS		 1229 if (ret) {
1230 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1231 return 3;
1232 }
25908b77
BS		 1233
1234 if (cond & 1)
1235 iexec->execute = false;
1236 }
1237 break;
1238 default:
1239 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1240 break;
1241 }
1242
1243 if (iexec->execute)
1244 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1245 else
1246 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1247
1248 return 3;
1249}
1250
1251static int
1252init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1253{
1254 /*
1255 * INIT_3B opcode: 0x3B ('')
1256 *
1257 * offset (8 bit): opcode
1258 * offset + 1 (8 bit): crtc index
1259 *
1260 */
1261
1262 uint8_t or = ffs(bios->display.output->or) - 1;
1263 uint8_t index = bios->data[offset + 1];
1264 uint8_t data;
1265
1266 if (!iexec->execute)
1267 return 2;
1268
1269 data = bios_idxprt_rd(bios, 0x3d4, index);
1270 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1271 return 2;
1272}
1273
1274static int
1275init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1276{
1277 /*
1278 * INIT_3C opcode: 0x3C ('')
1279 *
1280 * offset (8 bit): opcode
1281 * offset + 1 (8 bit): crtc index
1282 *
1283 */
1284
1285 uint8_t or = ffs(bios->display.output->or) - 1;
1286 uint8_t index = bios->data[offset + 1];
1287 uint8_t data;
1288
1289 if (!iexec->execute)
1290 return 2;
1291
1292 data = bios_idxprt_rd(bios, 0x3d4, index);
1293 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1294 return 2;
1295}
1296
37383650 1297static int
6ee73861
BS		 1298init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1299 struct init_exec *iexec)
1300{
1301 /*
1302 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1303 *
1304 * offset (8 bit): opcode
1305 * offset + 1 (32 bit): control register
1306 * offset + 5 (32 bit): data register
1307 * offset + 9 (32 bit): mask
1308 * offset + 13 (32 bit): data
1309 * offset + 17 (8 bit): count
1310 * offset + 18 (8 bit): address 1
1311 * offset + 19 (8 bit): data 1
1312 * ...
1313 *
1314 * For each of "count" address and data pairs, write "data n" to
1315 * "data register", read the current value of "control register",
1316 * and write it back once ANDed with "mask", ORed with "data",
1317 * and ORed with "address n"
1318 */
1319
1320 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1321 uint32_t datareg = ROM32(bios->data[offset + 5]);
1322 uint32_t mask = ROM32(bios->data[offset + 9]);
1323 uint32_t data = ROM32(bios->data[offset + 13]);
1324 uint8_t count = bios->data[offset + 17];
37383650 1325 int len = 18 + count * 2;
6ee73861
BS		 1326 uint32_t value;
1327 int i;
1328
1329 if (!iexec->execute)
37383650 1330 return len;
6ee73861
BS		 1331
1332 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1333 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1334 offset, controlreg, datareg, mask, data, count);
1335
1336 for (i = 0; i < count; i++) {
1337 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1338 uint8_t instdata = bios->data[offset + 19 + i * 2];
1339
1340 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1341 offset, instaddress, instdata);
1342
1343 bios_wr32(bios, datareg, instdata);
1344 value = bios_rd32(bios, controlreg) & mask;
1345 value |= data;
1346 value |= instaddress;
1347 bios_wr32(bios, controlreg, value);
1348 }
1349
37383650 1350 return len;
6ee73861
BS		 1351}
1352
37383650 1353static int
6ee73861
BS		 1354init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1355 struct init_exec *iexec)
1356{
1357 /*
1358 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1359 *
1360 * offset (8 bit): opcode
1361 * offset + 1 (16 bit): CRTC port
1362 * offset + 3 (8 bit): CRTC index
1363 * offset + 4 (8 bit): mask
1364 * offset + 5 (8 bit): shift
1365 * offset + 6 (8 bit): count
1366 * offset + 7 (32 bit): register
1367 * offset + 11 (32 bit): frequency 1
1368 * ...
1369 *
1370 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1371 * Set PLL register "register" to coefficients for frequency n,
1372 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1373 * "mask" and shifted right by "shift".
1374 */
1375
1376 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1377 uint8_t crtcindex = bios->data[offset + 3];
1378 uint8_t mask = bios->data[offset + 4];
1379 uint8_t shift = bios->data[offset + 5];
1380 uint8_t count = bios->data[offset + 6];
1381 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1382 int len = 11 + count * 4;
6ee73861
BS		 1383 uint8_t config;
1384 uint32_t freq;
1385
1386 if (!iexec->execute)
37383650 1387 return len;
6ee73861
BS		 1388
1389 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1390 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1391 offset, crtcport, crtcindex, mask, shift, count, reg);
1392
1393 if (!reg)
37383650 1394 return len;
6ee73861
BS		 1395
1396 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1397 if (config > count) {
1398 NV_ERROR(bios->dev,
1399 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1400 offset, config, count);
309b8c89 1401 return len;
6ee73861
BS		 1402 }
1403
1404 freq = ROM32(bios->data[offset + 11 + config * 4]);
1405
1406 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1407 offset, reg, config, freq);
1408
1409 setPLL(bios, reg, freq);
1410
37383650 1411 return len;
6ee73861
BS		 1412}
1413
37383650 1414static int
6ee73861
BS		 1415init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1416{
1417 /*
1418 * INIT_PLL2 opcode: 0x4B ('K')
1419 *
1420 * offset (8 bit): opcode
1421 * offset + 1 (32 bit): register
1422 * offset + 5 (32 bit): freq
1423 *
1424 * Set PLL register "register" to coefficients for frequency "freq"
1425 */
1426
1427 uint32_t reg = ROM32(bios->data[offset + 1]);
1428 uint32_t freq = ROM32(bios->data[offset + 5]);
1429
1430 if (!iexec->execute)
37383650 1431 return 9;
6ee73861
BS		 1432
1433 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1434 offset, reg, freq);
1435
1436 setPLL(bios, reg, freq);
37383650 1437 return 9;
6ee73861
BS		 1438}
1439
37383650 1440static int
6ee73861
BS		 1441init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1442{
1443 /*
1444 * INIT_I2C_BYTE opcode: 0x4C ('L')
1445 *
1446 * offset (8 bit): opcode
1447 * offset + 1 (8 bit): DCB I2C table entry index
1448 * offset + 2 (8 bit): I2C slave address
1449 * offset + 3 (8 bit): count
1450 * offset + 4 (8 bit): I2C register 1
1451 * offset + 5 (8 bit): mask 1
1452 * offset + 6 (8 bit): data 1
1453 * ...
1454 *
1455 * For each of "count" registers given by "I2C register n" on the device
1456 * addressed by "I2C slave address" on the I2C bus given by
1457 * "DCB I2C table entry index", read the register, AND the result with
1458 * "mask n" and OR it with "data n" before writing it back to the device
1459 */
1460
309b8c89 1461 struct drm_device *dev = bios->dev;
6ee73861 1462 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1463 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1464 uint8_t count = bios->data[offset + 3];
1465 struct nouveau_i2c_chan *chan;
893887ed
BS		 1466 int len = 4 + count * 3;
1467 int ret, i;
6ee73861
BS		 1468
1469 if (!iexec->execute)
37383650 1470 return len;
6ee73861
BS		 1471
1472 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1473 "Count: 0x%02X\n",
1474 offset, i2c_index, i2c_address, count);
1475
309b8c89
BS		 1476 chan = init_i2c_device_find(dev, i2c_index);
1477 if (!chan) {
1478 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1479 return len;
1480 }
6ee73861
BS		 1481
1482 for (i = 0; i < count; i++) {
893887ed 1483 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1484 uint8_t mask = bios->data[offset + 5 + i * 3];
1485 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1486 union i2c_smbus_data val;
6ee73861 1487
893887ed
BS		 1488 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1489 I2C_SMBUS_READ, reg,
1490 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1491 if (ret < 0) {
1492 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1493 return len;
1494 }
6ee73861
BS		 1495
1496 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1497 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1498 offset, reg, val.byte, mask, data);
6ee73861 1499
893887ed
BS		 1500 if (!bios->execute)
1501 continue;
6ee73861 1502
893887ed
BS		 1503 val.byte &= mask;
1504 val.byte |= data;
1505 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1506 I2C_SMBUS_WRITE, reg,
1507 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1508 if (ret < 0) {
1509 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1510 return len;
1511 }
6ee73861
BS		 1512 }
1513
37383650 1514 return len;
6ee73861
BS		 1515}
1516
37383650 1517static int
6ee73861
BS		 1518init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1519{
1520 /*
1521 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1522 *
1523 * offset (8 bit): opcode
1524 * offset + 1 (8 bit): DCB I2C table entry index
1525 * offset + 2 (8 bit): I2C slave address
1526 * offset + 3 (8 bit): count
1527 * offset + 4 (8 bit): I2C register 1
1528 * offset + 5 (8 bit): data 1
1529 * ...
1530 *
1531 * For each of "count" registers given by "I2C register n" on the device
1532 * addressed by "I2C slave address" on the I2C bus given by
1533 * "DCB I2C table entry index", set the register to "data n"
1534 */
1535
309b8c89 1536 struct drm_device *dev = bios->dev;
6ee73861 1537 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1538 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1539 uint8_t count = bios->data[offset + 3];
1540 struct nouveau_i2c_chan *chan;
893887ed
BS		 1541 int len = 4 + count * 2;
1542 int ret, i;
6ee73861
BS		 1543
1544 if (!iexec->execute)
37383650 1545 return len;
6ee73861
BS		 1546
1547 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1548 "Count: 0x%02X\n",
1549 offset, i2c_index, i2c_address, count);
1550
309b8c89
BS		 1551 chan = init_i2c_device_find(dev, i2c_index);
1552 if (!chan) {
1553 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1554 return len;
1555 }
6ee73861
BS		 1556
1557 for (i = 0; i < count; i++) {
893887ed
BS		 1558 uint8_t reg = bios->data[offset + 4 + i * 2];
1559 union i2c_smbus_data val;
1560
1561 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1562
1563 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1564 offset, reg, val.byte);
1565
1566 if (!bios->execute)
1567 continue;
1568
1569 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1570 I2C_SMBUS_WRITE, reg,
1571 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1572 if (ret < 0) {
1573 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1574 return len;
1575 }
6ee73861
BS		 1576 }
1577
37383650 1578 return len;
6ee73861
BS		 1579}
1580
37383650 1581static int
6ee73861
BS		 1582init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1583{
1584 /*
1585 * INIT_ZM_I2C opcode: 0x4E ('N')
1586 *
1587 * offset (8 bit): opcode
1588 * offset + 1 (8 bit): DCB I2C table entry index
1589 * offset + 2 (8 bit): I2C slave address
1590 * offset + 3 (8 bit): count
1591 * offset + 4 (8 bit): data 1
1592 * ...
1593 *
1594 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1595 * address" on the I2C bus given by "DCB I2C table entry index"
1596 */
1597
309b8c89 1598 struct drm_device *dev = bios->dev;
6ee73861 1599 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1600 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1601 uint8_t count = bios->data[offset + 3];
37383650 1602 int len = 4 + count;
6ee73861
BS		 1603 struct nouveau_i2c_chan *chan;
1604 struct i2c_msg msg;
1605 uint8_t data[256];
309b8c89 1606 int ret, i;
6ee73861
BS		 1607
1608 if (!iexec->execute)
37383650 1609 return len;
6ee73861
BS		 1610
1611 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1612 "Count: 0x%02X\n",
1613 offset, i2c_index, i2c_address, count);
1614
309b8c89
BS		 1615 chan = init_i2c_device_find(dev, i2c_index);
1616 if (!chan) {
1617 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1618 return len;
1619 }
6ee73861
BS		 1620
1621 for (i = 0; i < count; i++) {
1622 data[i] = bios->data[offset + 4 + i];
1623
1624 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1625 }
1626
1627 if (bios->execute) {
1628 msg.addr = i2c_address;
1629 msg.flags = 0;
1630 msg.len = count;
1631 msg.buf = data;
309b8c89
BS		 1632 ret = i2c_transfer(&chan->adapter, &msg, 1);
1633 if (ret != 1) {
1634 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1635 return len;
1636 }
6ee73861
BS		 1637 }
1638
37383650 1639 return len;
6ee73861
BS		 1640}
1641
37383650 1642static int
6ee73861
BS		 1643init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1644{
1645 /*
1646 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1647 *
1648 * offset (8 bit): opcode
1649 * offset + 1 (8 bit): magic lookup value
1650 * offset + 2 (8 bit): TMDS address
1651 * offset + 3 (8 bit): mask
1652 * offset + 4 (8 bit): data
1653 *
1654 * Read the data reg for TMDS address "TMDS address", AND it with mask
1655 * and OR it with data, then write it back
1656 * "magic lookup value" determines which TMDS base address register is
1657 * used -- see get_tmds_index_reg()
1658 */
1659
309b8c89 1660 struct drm_device *dev = bios->dev;
6ee73861
BS		 1661 uint8_t mlv = bios->data[offset + 1];
1662 uint32_t tmdsaddr = bios->data[offset + 2];
1663 uint8_t mask = bios->data[offset + 3];
1664 uint8_t data = bios->data[offset + 4];
1665 uint32_t reg, value;
1666
1667 if (!iexec->execute)
37383650 1668 return 5;
6ee73861
BS		 1669
1670 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1671 "Mask: 0x%02X, Data: 0x%02X\n",
1672 offset, mlv, tmdsaddr, mask, data);
1673
1674 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1675 if (!reg) {
1676 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1677 return 5;
1678 }
6ee73861
BS		 1679
1680 bios_wr32(bios, reg,
1681 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1682 value = (bios_rd32(bios, reg + 4) & mask) | data;
1683 bios_wr32(bios, reg + 4, value);
1684 bios_wr32(bios, reg, tmdsaddr);
1685
37383650 1686 return 5;
6ee73861
BS		 1687}
1688
37383650 1689static int
6ee73861
BS		 1690init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1691 struct init_exec *iexec)
1692{
1693 /*
1694 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1695 *
1696 * offset (8 bit): opcode
1697 * offset + 1 (8 bit): magic lookup value
1698 * offset + 2 (8 bit): count
1699 * offset + 3 (8 bit): addr 1
1700 * offset + 4 (8 bit): data 1
1701 * ...
1702 *
1703 * For each of "count" TMDS address and data pairs write "data n" to
1704 * "addr n". "magic lookup value" determines which TMDS base address
1705 * register is used -- see get_tmds_index_reg()
1706 */
1707
309b8c89 1708 struct drm_device *dev = bios->dev;
6ee73861
BS		 1709 uint8_t mlv = bios->data[offset + 1];
1710 uint8_t count = bios->data[offset + 2];
37383650 1711 int len = 3 + count * 2;
6ee73861
BS		 1712 uint32_t reg;
1713 int i;
1714
1715 if (!iexec->execute)
37383650 1716 return len;
6ee73861
BS		 1717
1718 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1719 offset, mlv, count);
1720
1721 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1722 if (!reg) {
1723 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1724 return len;
1725 }
6ee73861
BS		 1726
1727 for (i = 0; i < count; i++) {
1728 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1729 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1730
1731 bios_wr32(bios, reg + 4, tmdsdata);
1732 bios_wr32(bios, reg, tmdsaddr);
1733 }
1734
37383650 1735 return len;
6ee73861
BS		 1736}
1737
37383650 1738static int
6ee73861
BS		 1739init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1740 struct init_exec *iexec)
1741{
1742 /*
1743 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1744 *
1745 * offset (8 bit): opcode
1746 * offset + 1 (8 bit): CRTC index1
1747 * offset + 2 (8 bit): CRTC index2
1748 * offset + 3 (8 bit): baseaddr
1749 * offset + 4 (8 bit): count
1750 * offset + 5 (8 bit): data 1
1751 * ...
1752 *
1753 * For each of "count" address and data pairs, write "baseaddr + n" to
1754 * "CRTC index1" and "data n" to "CRTC index2"
1755 * Once complete, restore initial value read from "CRTC index1"
1756 */
1757 uint8_t crtcindex1 = bios->data[offset + 1];
1758 uint8_t crtcindex2 = bios->data[offset + 2];
1759 uint8_t baseaddr = bios->data[offset + 3];
1760 uint8_t count = bios->data[offset + 4];
37383650 1761 int len = 5 + count;
6ee73861
BS		 1762 uint8_t oldaddr, data;
1763 int i;
1764
1765 if (!iexec->execute)
37383650 1766 return len;
6ee73861
BS		 1767
1768 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1769 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1770 offset, crtcindex1, crtcindex2, baseaddr, count);
1771
1772 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1773
1774 for (i = 0; i < count; i++) {
1775 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1776 baseaddr + i);
1777 data = bios->data[offset + 5 + i];
1778 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1779 }
1780
1781 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1782
37383650 1783 return len;
6ee73861
BS		 1784}
1785
37383650 1786static int
6ee73861
BS		 1787init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1788{
1789 /*
1790 * INIT_CR opcode: 0x52 ('R')
1791 *
1792 * offset (8 bit): opcode
1793 * offset + 1 (8 bit): CRTC index
1794 * offset + 2 (8 bit): mask
1795 * offset + 3 (8 bit): data
1796 *
1797 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1798 * data back to "CRTC index"
1799 */
1800
1801 uint8_t crtcindex = bios->data[offset + 1];
1802 uint8_t mask = bios->data[offset + 2];
1803 uint8_t data = bios->data[offset + 3];
1804 uint8_t value;
1805
1806 if (!iexec->execute)
37383650 1807 return 4;
6ee73861
BS		 1808
1809 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1810 offset, crtcindex, mask, data);
1811
1812 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1813 value |= data;
1814 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1815
37383650 1816 return 4;
6ee73861
BS		 1817}
1818
37383650 1819static int
6ee73861
BS		 1820init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1821{
1822 /*
1823 * INIT_ZM_CR opcode: 0x53 ('S')
1824 *
1825 * offset (8 bit): opcode
1826 * offset + 1 (8 bit): CRTC index
1827 * offset + 2 (8 bit): value
1828 *
1829 * Assign "value" to CRTC register with index "CRTC index".
1830 */
1831
1832 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1833 uint8_t data = bios->data[offset + 2];
1834
1835 if (!iexec->execute)
37383650 1836 return 3;
6ee73861
BS		 1837
1838 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1839
37383650 1840 return 3;
6ee73861
BS		 1841}
1842
37383650 1843static int
6ee73861
BS		 1844init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1845{
1846 /*
1847 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1848 *
1849 * offset (8 bit): opcode
1850 * offset + 1 (8 bit): count
1851 * offset + 2 (8 bit): CRTC index 1
1852 * offset + 3 (8 bit): value 1
1853 * ...
1854 *
1855 * For "count", assign "value n" to CRTC register with index
1856 * "CRTC index n".
1857 */
1858
1859 uint8_t count = bios->data[offset + 1];
37383650 1860 int len = 2 + count * 2;
6ee73861
BS		 1861 int i;
1862
1863 if (!iexec->execute)
37383650 1864 return len;
6ee73861
BS		 1865
1866 for (i = 0; i < count; i++)
1867 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1868
37383650 1869 return len;
6ee73861
BS		 1870}
1871
37383650 1872static int
6ee73861
BS		 1873init_condition_time(struct nvbios *bios, uint16_t offset,
1874 struct init_exec *iexec)
1875{
1876 /*
1877 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1878 *
1879 * offset (8 bit): opcode
1880 * offset + 1 (8 bit): condition number
1881 * offset + 2 (8 bit): retries / 50
1882 *
1883 * Check condition "condition number" in the condition table.
1884 * Bios code then sleeps for 2ms if the condition is not met, and
1885 * repeats up to "retries" times, but on one C51 this has proved
1886 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1887 * this, and bail after "retries" times, or 2s, whichever is less.
1888 * If still not met after retries, clear execution flag for this table.
1889 */
1890
1891 uint8_t cond = bios->data[offset + 1];
1892 uint16_t retries = bios->data[offset + 2] * 50;
1893 unsigned cnt;
1894
1895 if (!iexec->execute)
37383650 1896 return 3;
6ee73861
BS		 1897
1898 if (retries > 100)
1899 retries = 100;
1900
1901 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1902 offset, cond, retries);
1903
1904 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1905 retries = 1;
1906
1907 for (cnt = 0; cnt < retries; cnt++) {
1908 if (bios_condition_met(bios, offset, cond)) {
1909 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1910 offset);
1911 break;
1912 } else {
1913 BIOSLOG(bios, "0x%04X: "
1914 "Condition not met, sleeping for 20ms\n",
1915 offset);
1916 msleep(20);
1917 }
1918 }
1919
1920 if (!bios_condition_met(bios, offset, cond)) {
1921 NV_WARN(bios->dev,
1922 "0x%04X: Condition still not met after %dms, "
1923 "skipping following opcodes\n", offset, 20 * retries);
1924 iexec->execute = false;
1925 }
1926
37383650 1927 return 3;
6ee73861
BS		 1928}
1929
37383650 1930static int
6ee73861
BS		 1931init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1932 struct init_exec *iexec)
1933{
1934 /*
1935 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1936 *
1937 * offset (8 bit): opcode
1938 * offset + 1 (32 bit): base register
1939 * offset + 5 (8 bit): count
1940 * offset + 6 (32 bit): value 1
1941 * ...
1942 *
1943 * Starting at offset + 6 there are "count" 32 bit values.
1944 * For "count" iterations set "base register" + 4 * current_iteration
1945 * to "value current_iteration"
1946 */
1947
1948 uint32_t basereg = ROM32(bios->data[offset + 1]);
1949 uint32_t count = bios->data[offset + 5];
37383650 1950 int len = 6 + count * 4;
6ee73861
BS		 1951 int i;
1952
1953 if (!iexec->execute)
37383650 1954 return len;
6ee73861
BS		 1955
1956 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1957 offset, basereg, count);
1958
1959 for (i = 0; i < count; i++) {
1960 uint32_t reg = basereg + i * 4;
1961 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1962
1963 bios_wr32(bios, reg, data);
1964 }
1965
37383650 1966 return len;
6ee73861
BS		 1967}
1968
37383650 1969static int
6ee73861
BS		 1970init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1971{
1972 /*
1973 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1974 *
1975 * offset (8 bit): opcode
1976 * offset + 1 (16 bit): subroutine offset (in bios)
1977 *
1978 * Calls a subroutine that will execute commands until INIT_DONE
1979 * is found.
1980 */
1981
1982 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1983
1984 if (!iexec->execute)
37383650 1985 return 3;
6ee73861
BS		 1986
1987 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1988 offset, sub_offset);
1989
1990 parse_init_table(bios, sub_offset, iexec);
1991
1992 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1993
37383650 1994 return 3;
6ee73861
BS		 1995}
1996
37383650 1997static int
6ee73861
BS		 1998init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1999{
2000 /*
2001 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2002 *
2003 * offset (8 bit): opcode
2004 * offset + 1 (32 bit): src reg
2005 * offset + 5 (8 bit): shift
2006 * offset + 6 (32 bit): src mask
2007 * offset + 10 (32 bit): xor
2008 * offset + 14 (32 bit): dst reg
2009 * offset + 18 (32 bit): dst mask
2010 *
2011 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2012 * "src mask", then XOR with "xor". Write this OR'd with
2013 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2014 */
2015
2016 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2017 uint8_t shift = bios->data[offset + 5];
2018 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2019 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2020 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2021 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2022 uint32_t srcvalue, dstvalue;
2023
2024 if (!iexec->execute)
37383650 2025 return 22;
6ee73861
BS		 2026
2027 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2028 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2029 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2030
2031 srcvalue = bios_rd32(bios, srcreg);
2032
2033 if (shift < 0x80)
2034 srcvalue >>= shift;
2035 else
2036 srcvalue <<= (0x100 - shift);
2037
2038 srcvalue = (srcvalue & srcmask) ^ xor;
2039
2040 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2041
2042 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2043
37383650 2044 return 22;
6ee73861
BS		 2045}
2046
37383650 2047static int
6ee73861
BS		 2048init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2049{
2050 /*
2051 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2052 *
2053 * offset (8 bit): opcode
2054 * offset + 1 (16 bit): CRTC port
2055 * offset + 3 (8 bit): CRTC index
2056 * offset + 4 (8 bit): data
2057 *
2058 * Write "data" to index "CRTC index" of "CRTC port"
2059 */
2060 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2061 uint8_t crtcindex = bios->data[offset + 3];
2062 uint8_t data = bios->data[offset + 4];
2063
2064 if (!iexec->execute)
37383650 2065 return 5;
6ee73861
BS		 2066
2067 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2068
37383650 2069 return 5;
6ee73861
BS		 2070}
2071
67eda20e
FJ		 2072static inline void
2073bios_md32(struct nvbios *bios, uint32_t reg,
2074 uint32_t mask, uint32_t val)
2075{
2076 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2077}
2078
2079static uint32_t
2080peek_fb(struct drm_device *dev, struct io_mapping *fb,
2081 uint32_t off)
2082{
2083 uint32_t val = 0;
2084
2085 if (off < pci_resource_len(dev->pdev, 1)) {
0bf9b0e0
FJ		 2086 uint32_t __iomem *p =
2087 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0);
67eda20e 2088
0bf9b0e0 2089 val = ioread32(p + (off & ~PAGE_MASK));
67eda20e 2090
fca3ec01 2091 io_mapping_unmap_atomic(p, KM_USER0);
67eda20e
FJ		 2092 }
2093
2094 return val;
2095}
2096
2097static void
2098poke_fb(struct drm_device *dev, struct io_mapping *fb,
2099 uint32_t off, uint32_t val)
2100{
2101 if (off < pci_resource_len(dev->pdev, 1)) {
0bf9b0e0
FJ		 2102 uint32_t __iomem *p =
2103 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0);
67eda20e 2104
0bf9b0e0 2105 iowrite32(val, p + (off & ~PAGE_MASK));
67eda20e
FJ		 2106 wmb();
2107
fca3ec01 2108 io_mapping_unmap_atomic(p, KM_USER0);
67eda20e
FJ		 2109 }
2110}
2111
2112static inline bool
2113read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2114 uint32_t off, uint32_t val)
2115{
2116 poke_fb(dev, fb, off, val);
2117 return val == peek_fb(dev, fb, off);
2118}
2119
2120static int
2121nv04_init_compute_mem(struct nvbios *bios)
2122{
2123 struct drm_device *dev = bios->dev;
2124 uint32_t patt = 0xdeadbeef;
2125 struct io_mapping *fb;
2126 int i;
2127
2128 /* Map the framebuffer aperture */
2129 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2130 pci_resource_len(dev->pdev, 1));
2131 if (!fb)
2132 return -ENOMEM;
2133
2134 /* Sequencer and refresh off */
2135 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2136 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2137
2138 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2139 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2140 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2141 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2142
2143 for (i = 0; i < 4; i++)
2144 poke_fb(dev, fb, 4 * i, patt);
2145
2146 poke_fb(dev, fb, 0x400000, patt + 1);
2147
2148 if (peek_fb(dev, fb, 0) == patt + 1) {
2149 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2150 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2151 bios_md32(bios, NV04_PFB_DEBUG_0,
2152 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2153
2154 for (i = 0; i < 4; i++)
2155 poke_fb(dev, fb, 4 * i, patt);
2156
2157 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2158 bios_md32(bios, NV04_PFB_BOOT_0,
2159 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2160 NV04_PFB_BOOT_0_RAM_AMOUNT,
2161 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2162
2163 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2164 (patt & 0xffff0000)) {
2165 bios_md32(bios, NV04_PFB_BOOT_0,
2166 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2167 NV04_PFB_BOOT_0_RAM_AMOUNT,
2168 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2169
2170 } else if (peek_fb(dev, fb, 0) == patt) {
2171 if (read_back_fb(dev, fb, 0x800000, patt))
2172 bios_md32(bios, NV04_PFB_BOOT_0,
2173 NV04_PFB_BOOT_0_RAM_AMOUNT,
2174 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2175 else
2176 bios_md32(bios, NV04_PFB_BOOT_0,
2177 NV04_PFB_BOOT_0_RAM_AMOUNT,
2178 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2179
2180 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2181 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2182
2183 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2184 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2185 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2186
2187 }
2188
2189 /* Refresh on, sequencer on */
2190 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2191 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2192
2193 io_mapping_free(fb);
2194 return 0;
2195}
2196
2197static const uint8_t *
2198nv05_memory_config(struct nvbios *bios)
2199{
2200 /* Defaults for BIOSes lacking a memory config table */
2201 static const uint8_t default_config_tab[][2] = {
2202 { 0x24, 0x00 },
2203 { 0x28, 0x00 },
2204 { 0x24, 0x01 },
2205 { 0x1f, 0x00 },
2206 { 0x0f, 0x00 },
2207 { 0x17, 0x00 },
2208 { 0x06, 0x00 },
2209 { 0x00, 0x00 }
2210 };
2211 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2212 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2213
2214 if (bios->legacy.mem_init_tbl_ptr)
2215 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2216 else
2217 return default_config_tab[i];
2218}
2219
2220static int
2221nv05_init_compute_mem(struct nvbios *bios)
2222{
2223 struct drm_device *dev = bios->dev;
2224 const uint8_t *ramcfg = nv05_memory_config(bios);
2225 uint32_t patt = 0xdeadbeef;
2226 struct io_mapping *fb;
2227 int i, v;
2228
2229 /* Map the framebuffer aperture */
2230 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2231 pci_resource_len(dev->pdev, 1));
2232 if (!fb)
2233 return -ENOMEM;
2234
2235 /* Sequencer off */
2236 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2237
2238 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2239 goto out;
2240
2241 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2242
2243 /* If present load the hardcoded scrambling table */
2244 if (bios->legacy.mem_init_tbl_ptr) {
2245 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2246 bios->legacy.mem_init_tbl_ptr + 0x10];
2247
2248 for (i = 0; i < 8; i++)
2249 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2250 ROM32(scramble_tab[i]));
2251 }
2252
2253 /* Set memory type/width/length defaults depending on the straps */
2254 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2255
2256 if (ramcfg[1] & 0x80)
2257 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2258
2259 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2260 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2261
2262 /* Probe memory bus width */
2263 for (i = 0; i < 4; i++)
2264 poke_fb(dev, fb, 4 * i, patt);
2265
2266 if (peek_fb(dev, fb, 0xc) != patt)
2267 bios_md32(bios, NV04_PFB_BOOT_0,
2268 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2269
2270 /* Probe memory length */
2271 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2272
2273 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2274 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2275 !read_back_fb(dev, fb, 0, ++patt)))
2276 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2277 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2278
2279 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2280 !read_back_fb(dev, fb, 0x800000, ++patt))
2281 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2282 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2283
2284 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2285 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2286 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2287
2288out:
2289 /* Sequencer on */
2290 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2291
2292 io_mapping_free(fb);
2293 return 0;
2294}
2295
2296static int
2297nv10_init_compute_mem(struct nvbios *bios)
2298{
2299 struct drm_device *dev = bios->dev;
2300 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2301 const int mem_width[] = { 0x10, 0x00, 0x20 };
2302 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2303 uint32_t patt = 0xdeadbeef;
2304 struct io_mapping *fb;
2305 int i, j, k;
2306
2307 /* Map the framebuffer aperture */
2308 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2309 pci_resource_len(dev->pdev, 1));
2310 if (!fb)
2311 return -ENOMEM;
2312
2313 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2314
2315 /* Probe memory bus width */
2316 for (i = 0; i < mem_width_count; i++) {
2317 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2318
2319 for (j = 0; j < 4; j++) {
2320 for (k = 0; k < 4; k++)
2321 poke_fb(dev, fb, 0x1c, 0);
2322
2323 poke_fb(dev, fb, 0x1c, patt);
2324 poke_fb(dev, fb, 0x3c, 0);
2325
2326 if (peek_fb(dev, fb, 0x1c) == patt)
2327 goto mem_width_found;
2328 }
2329 }
2330
2331mem_width_found:
2332 patt <<= 1;
2333
2334 /* Probe amount of installed memory */
2335 for (i = 0; i < 4; i++) {
2336 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2337
2338 poke_fb(dev, fb, off, patt);
2339 poke_fb(dev, fb, 0, 0);
2340
2341 peek_fb(dev, fb, 0);
2342 peek_fb(dev, fb, 0);
2343 peek_fb(dev, fb, 0);
2344 peek_fb(dev, fb, 0);
2345
2346 if (peek_fb(dev, fb, off) == patt)
2347 goto amount_found;
2348 }
2349
2350 /* IC missing - disable the upper half memory space. */
2351 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2352
2353amount_found:
2354 io_mapping_free(fb);
2355 return 0;
2356}
2357
2358static int
2359nv20_init_compute_mem(struct nvbios *bios)
2360{
2361 struct drm_device *dev = bios->dev;
2362 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2363 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2364 uint32_t amount, off;
2365 struct io_mapping *fb;
2366
2367 /* Map the framebuffer aperture */
2368 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2369 pci_resource_len(dev->pdev, 1));
2370 if (!fb)
2371 return -ENOMEM;
2372
2373 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2374
2375 /* Allow full addressing */
2376 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2377
2378 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2379 for (off = amount; off > 0x2000000; off -= 0x2000000)
2380 poke_fb(dev, fb, off - 4, off);
2381
2382 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2383 if (amount != peek_fb(dev, fb, amount - 4))
2384 /* IC missing - disable the upper half memory space. */
2385 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2386
2387 io_mapping_free(fb);
2388 return 0;
2389}
2390
37383650 2391static int
6ee73861
BS		 2392init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2393{
2394 /*
2395 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2396 *
2397 * offset (8 bit): opcode
2398 *
67eda20e
FJ		 2399 * This opcode is meant to set the PFB memory config registers
2400 * appropriately so that we can correctly calculate how much VRAM it
2401 * has (on nv10 and better chipsets the amount of installed VRAM is
2402 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
6ee73861 2403 *
67eda20e
FJ		 2404 * The implementation of this opcode in general consists of several
2405 * parts:
6ee73861 2406 *
67eda20e
FJ		 2407 * 1) Determination of memory type and density. Only necessary for
2408 * really old chipsets, the memory type reported by the strap bits
2409 * (0x101000) is assumed to be accurate on nv05 and newer.
6ee73861 2410 *
67eda20e
FJ		 2411 * 2) Determination of the memory bus width. Usually done by a cunning
2412 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2413 * seeing whether the written values are read back correctly.
6ee73861 2414 *
67eda20e
FJ		 2415 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2416 * trust the straps.
6ee73861 2417 *
67eda20e
FJ		 2418 * 3) Determination of how many of the card's RAM pads have ICs
2419 * attached, usually done by a cunning combination of writes to an
2420 * offset slightly less than the maximum memory reported by
2421 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
6ee73861 2422 *
67eda20e
FJ		 2423 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2424 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2425 * card show nothing being done for this opcode. Why is it still listed
2426 * in the table?!
6ee73861
BS		 2427 */
2428
2429 /* no iexec->execute check by design */
2430
6ee73861 2431 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
67eda20e 2432 int ret;
6ee73861 2433
67eda20e
FJ		 2434 if (dev_priv->chipset >= 0x40 ||
2435 dev_priv->chipset == 0x1a ||
2436 dev_priv->chipset == 0x1f)
2437 ret = 0;
2438 else if (dev_priv->chipset >= 0x20 &&
2439 dev_priv->chipset != 0x34)
2440 ret = nv20_init_compute_mem(bios);
2441 else if (dev_priv->chipset >= 0x10)
2442 ret = nv10_init_compute_mem(bios);
2443 else if (dev_priv->chipset >= 0x5)
2444 ret = nv05_init_compute_mem(bios);
2445 else
2446 ret = nv04_init_compute_mem(bios);
6ee73861 2447
67eda20e
FJ		 2448 if (ret)
2449 return ret;
6ee73861 2450
37383650 2451 return 1;
6ee73861
BS		 2452}
2453
37383650 2454static int
6ee73861
BS		 2455init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2456{
2457 /*
2458 * INIT_RESET opcode: 0x65 ('e')
2459 *
2460 * offset (8 bit): opcode
2461 * offset + 1 (32 bit): register
2462 * offset + 5 (32 bit): value1
2463 * offset + 9 (32 bit): value2
2464 *
2465 * Assign "value1" to "register", then assign "value2" to "register"
2466 */
2467
2468 uint32_t reg = ROM32(bios->data[offset + 1]);
2469 uint32_t value1 = ROM32(bios->data[offset + 5]);
2470 uint32_t value2 = ROM32(bios->data[offset + 9]);
2471 uint32_t pci_nv_19, pci_nv_20;
2472
2473 /* no iexec->execute check by design */
2474
2475 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
190a4378
FJ		 2476 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2477
6ee73861
BS		 2478 bios_wr32(bios, reg, value1);
2479
2480 udelay(10);
2481
2482 bios_wr32(bios, reg, value2);
2483 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2484
2485 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2486 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2487 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2488
37383650 2489 return 13;
6ee73861
BS		 2490}
2491
37383650 2492static int
6ee73861
BS		 2493init_configure_mem(struct nvbios *bios, uint16_t offset,
2494 struct init_exec *iexec)
2495{
2496 /*
2497 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2498 *
2499 * offset (8 bit): opcode
2500 *
2501 * Equivalent to INIT_DONE on bios version 3 or greater.
2502 * For early bios versions, sets up the memory registers, using values
2503 * taken from the memory init table
2504 */
2505
2506 /* no iexec->execute check by design */
2507
2508 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2509 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2510 uint32_t reg, data;
2511
2512 if (bios->major_version > 2)
ae55321c 2513 return 0;
6ee73861
BS		 2514
2515 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2516 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2517
2518 if (bios->data[meminitoffs] & 1)
2519 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2520
2521 for (reg = ROM32(bios->data[seqtbloffs]);
2522 reg != 0xffffffff;
2523 reg = ROM32(bios->data[seqtbloffs += 4])) {
2524
2525 switch (reg) {
3c7066bc
FJ		 2526 case NV04_PFB_PRE:
2527 data = NV04_PFB_PRE_CMD_PRECHARGE;
6ee73861 2528 break;
3c7066bc
FJ		 2529 case NV04_PFB_PAD:
2530 data = NV04_PFB_PAD_CKE_NORMAL;
6ee73861 2531 break;
3c7066bc
FJ		 2532 case NV04_PFB_REF:
2533 data = NV04_PFB_REF_CMD_REFRESH;
6ee73861
BS		 2534 break;
2535 default:
2536 data = ROM32(bios->data[meminitdata]);
2537 meminitdata += 4;
2538 if (data == 0xffffffff)
2539 continue;
2540 }
2541
2542 bios_wr32(bios, reg, data);
2543 }
2544
37383650 2545 return 1;
6ee73861
BS		 2546}
2547
37383650 2548static int
6ee73861
BS		 2549init_configure_clk(struct nvbios *bios, uint16_t offset,
2550 struct init_exec *iexec)
2551{
2552 /*
2553 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2554 *
2555 * offset (8 bit): opcode
2556 *
2557 * Equivalent to INIT_DONE on bios version 3 or greater.
2558 * For early bios versions, sets up the NVClk and MClk PLLs, using
2559 * values taken from the memory init table
2560 */
2561
2562 /* no iexec->execute check by design */
2563
2564 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2565 int clock;
2566
2567 if (bios->major_version > 2)
ae55321c 2568 return 0;
6ee73861
BS		 2569
2570 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2571 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2572
2573 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2574 if (bios->data[meminitoffs] & 1) /* DDR */
2575 clock *= 2;
2576 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2577
37383650 2578 return 1;
6ee73861
BS		 2579}
2580
37383650 2581static int
6ee73861
BS		 2582init_configure_preinit(struct nvbios *bios, uint16_t offset,
2583 struct init_exec *iexec)
2584{
2585 /*
2586 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2587 *
2588 * offset (8 bit): opcode
2589 *
2590 * Equivalent to INIT_DONE on bios version 3 or greater.
2591 * For early bios versions, does early init, loading ram and crystal
2592 * configuration from straps into CR3C
2593 */
2594
2595 /* no iexec->execute check by design */
2596
2597 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
3c9b2534 2598 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
6ee73861
BS		 2599
2600 if (bios->major_version > 2)
ae55321c 2601 return 0;
6ee73861
BS		 2602
2603 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2604 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2605
37383650 2606 return 1;
6ee73861
BS		 2607}
2608
37383650 2609static int
6ee73861
BS		 2610init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2611{
2612 /*
2613 * INIT_IO opcode: 0x69 ('i')
2614 *
2615 * offset (8 bit): opcode
2616 * offset + 1 (16 bit): CRTC port
2617 * offset + 3 (8 bit): mask
2618 * offset + 4 (8 bit): data
2619 *
2620 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2621 */
2622
2623 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2624 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2625 uint8_t mask = bios->data[offset + 3];
2626 uint8_t data = bios->data[offset + 4];
2627
2628 if (!iexec->execute)
37383650 2629 return 5;
6ee73861
BS		 2630
2631 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2632 offset, crtcport, mask, data);
2633
2634 /*
2635 * I have no idea what this does, but NVIDIA do this magic sequence
2636 * in the places where this INIT_IO happens..
2637 */
2638 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2639 int i;
2640
2641 bios_wr32(bios, 0x614100, (bios_rd32(
2642 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2643
2644 bios_wr32(bios, 0x00e18c, bios_rd32(
2645 bios, 0x00e18c) | 0x00020000);
2646
2647 bios_wr32(bios, 0x614900, (bios_rd32(
2648 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2649
2650 bios_wr32(bios, 0x000200, bios_rd32(
2651 bios, 0x000200) & ~0x40000000);
2652
2653 mdelay(10);
2654
2655 bios_wr32(bios, 0x00e18c, bios_rd32(
2656 bios, 0x00e18c) & ~0x00020000);
2657
2658 bios_wr32(bios, 0x000200, bios_rd32(
2659 bios, 0x000200) | 0x40000000);
2660
2661 bios_wr32(bios, 0x614100, 0x00800018);
2662 bios_wr32(bios, 0x614900, 0x00800018);
2663
2664 mdelay(10);
2665
2666 bios_wr32(bios, 0x614100, 0x10000018);
2667 bios_wr32(bios, 0x614900, 0x10000018);
2668
2669 for (i = 0; i < 3; i++)
2670 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2671 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2672
2673 for (i = 0; i < 2; i++)
2674 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2675 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2676
2677 for (i = 0; i < 3; i++)
2678 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2679 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2680
2681 for (i = 0; i < 2; i++)
2682 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2683 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2684
2685 for (i = 0; i < 2; i++)
2686 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2687 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2688 return 5;
6ee73861
BS		 2689 }
2690
2691 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2692 data);
37383650 2693 return 5;
6ee73861
BS		 2694}
2695
37383650 2696static int
6ee73861
BS		 2697init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2698{
2699 /*
2700 * INIT_SUB opcode: 0x6B ('k')
2701 *
2702 * offset (8 bit): opcode
2703 * offset + 1 (8 bit): script number
2704 *
2705 * Execute script number "script number", as a subroutine
2706 */
2707
2708 uint8_t sub = bios->data[offset + 1];
2709
2710 if (!iexec->execute)
37383650 2711 return 2;
6ee73861
BS		 2712
2713 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2714
2715 parse_init_table(bios,
2716 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2717 iexec);
2718
2719 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2720
37383650 2721 return 2;
6ee73861
BS		 2722}
2723
37383650 2724static int
6ee73861
BS		 2725init_ram_condition(struct nvbios *bios, uint16_t offset,
2726 struct init_exec *iexec)
2727{
2728 /*
2729 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2730 *
2731 * offset (8 bit): opcode
2732 * offset + 1 (8 bit): mask
2733 * offset + 2 (8 bit): cmpval
2734 *
3c7066bc 2735 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
6ee73861
BS		 2736 * If condition not met skip subsequent opcodes until condition is
2737 * inverted (INIT_NOT), or we hit INIT_RESUME
2738 */
2739
2740 uint8_t mask = bios->data[offset + 1];
2741 uint8_t cmpval = bios->data[offset + 2];
2742 uint8_t data;
2743
2744 if (!iexec->execute)
37383650 2745 return 3;
6ee73861 2746
3c7066bc 2747 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
6ee73861
BS		 2748
2749 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2750 offset, data, cmpval);
2751
2752 if (data == cmpval)
2753 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2754 else {
2755 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2756 iexec->execute = false;
2757 }
2758
37383650 2759 return 3;
6ee73861
BS		 2760}
2761
37383650 2762static int
6ee73861
BS		 2763init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2764{
2765 /*
2766 * INIT_NV_REG opcode: 0x6E ('n')
2767 *
2768 * offset (8 bit): opcode
2769 * offset + 1 (32 bit): register
2770 * offset + 5 (32 bit): mask
2771 * offset + 9 (32 bit): data
2772 *
2773 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2774 */
2775
2776 uint32_t reg = ROM32(bios->data[offset + 1]);
2777 uint32_t mask = ROM32(bios->data[offset + 5]);
2778 uint32_t data = ROM32(bios->data[offset + 9]);
2779
2780 if (!iexec->execute)
37383650 2781 return 13;
6ee73861
BS		 2782
2783 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2784 offset, reg, mask, data);
2785
2786 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2787
37383650 2788 return 13;
6ee73861
BS		 2789}
2790
37383650 2791static int
6ee73861
BS		 2792init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2793{
2794 /*
2795 * INIT_MACRO opcode: 0x6F ('o')
2796 *
2797 * offset (8 bit): opcode
2798 * offset + 1 (8 bit): macro number
2799 *
2800 * Look up macro index "macro number" in the macro index table.
2801 * The macro index table entry has 1 byte for the index in the macro
2802 * table, and 1 byte for the number of times to repeat the macro.
2803 * The macro table entry has 4 bytes for the register address and
2804 * 4 bytes for the value to write to that register
2805 */
2806
2807 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2808 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2809 uint8_t macro_tbl_idx = bios->data[tmp];
2810 uint8_t count = bios->data[tmp + 1];
2811 uint32_t reg, data;
2812 int i;
2813
2814 if (!iexec->execute)
37383650 2815 return 2;
6ee73861
BS		 2816
2817 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2818 "Count: 0x%02X\n",
2819 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2820
2821 for (i = 0; i < count; i++) {
2822 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2823
2824 reg = ROM32(bios->data[macroentryptr]);
2825 data = ROM32(bios->data[macroentryptr + 4]);
2826
2827 bios_wr32(bios, reg, data);
2828 }
2829
37383650 2830 return 2;
6ee73861
BS		 2831}
2832
37383650 2833static int
6ee73861
BS		 2834init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2835{
2836 /*
2837 * INIT_DONE opcode: 0x71 ('q')
2838 *
2839 * offset (8 bit): opcode
2840 *
2841 * End the current script
2842 */
2843
2844 /* mild retval abuse to stop parsing this table */
37383650 2845 return 0;
6ee73861
BS		 2846}
2847
37383650 2848static int
6ee73861
BS		 2849init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2850{
2851 /*
2852 * INIT_RESUME opcode: 0x72 ('r')
2853 *
2854 * offset (8 bit): opcode
2855 *
2856 * End the current execute / no-execute condition
2857 */
2858
2859 if (iexec->execute)
37383650 2860 return 1;
6ee73861
BS		 2861
2862 iexec->execute = true;
2863 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2864
37383650 2865 return 1;
6ee73861
BS		 2866}
2867
37383650 2868static int
6ee73861
BS		 2869init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2870{
2871 /*
2872 * INIT_TIME opcode: 0x74 ('t')
2873 *
2874 * offset (8 bit): opcode
2875 * offset + 1 (16 bit): time
2876 *
2877 * Sleep for "time" microseconds.
2878 */
2879
2880 unsigned time = ROM16(bios->data[offset + 1]);
2881
2882 if (!iexec->execute)
37383650 2883 return 3;
6ee73861
BS		 2884
2885 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2886 offset, time);
2887
2888 if (time < 1000)
2889 udelay(time);
2890 else
2891 msleep((time + 900) / 1000);
2892
37383650 2893 return 3;
6ee73861
BS		 2894}
2895
37383650 2896static int
6ee73861
BS		 2897init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2898{
2899 /*
2900 * INIT_CONDITION opcode: 0x75 ('u')
2901 *
2902 * offset (8 bit): opcode
2903 * offset + 1 (8 bit): condition number
2904 *
2905 * Check condition "condition number" in the condition table.
2906 * If condition not met skip subsequent opcodes until condition is
2907 * inverted (INIT_NOT), or we hit INIT_RESUME
2908 */
2909
2910 uint8_t cond = bios->data[offset + 1];
2911
2912 if (!iexec->execute)
37383650 2913 return 2;
6ee73861
BS		 2914
2915 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2916
2917 if (bios_condition_met(bios, offset, cond))
2918 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2919 else {
2920 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2921 iexec->execute = false;
2922 }
2923
37383650 2924 return 2;
6ee73861
BS		 2925}
2926
37383650 2927static int
6ee73861
BS		 2928init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2929{
2930 /*
2931 * INIT_IO_CONDITION opcode: 0x76
2932 *
2933 * offset (8 bit): opcode
2934 * offset + 1 (8 bit): condition number
2935 *
2936 * Check condition "condition number" in the io condition table.
2937 * If condition not met skip subsequent opcodes until condition is
2938 * inverted (INIT_NOT), or we hit INIT_RESUME
2939 */
2940
2941 uint8_t cond = bios->data[offset + 1];
2942
2943 if (!iexec->execute)
37383650 2944 return 2;
6ee73861
BS		 2945
2946 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2947
2948 if (io_condition_met(bios, offset, cond))
2949 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2950 else {
2951 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2952 iexec->execute = false;
2953 }
2954
37383650 2955 return 2;
6ee73861
BS		 2956}
2957
37383650 2958static int
6ee73861
BS		 2959init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2960{
2961 /*
2962 * INIT_INDEX_IO opcode: 0x78 ('x')
2963 *
2964 * offset (8 bit): opcode
2965 * offset + 1 (16 bit): CRTC port
2966 * offset + 3 (8 bit): CRTC index
2967 * offset + 4 (8 bit): mask
2968 * offset + 5 (8 bit): data
2969 *
2970 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2971 * OR with "data", write-back
2972 */
2973
2974 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2975 uint8_t crtcindex = bios->data[offset + 3];
2976 uint8_t mask = bios->data[offset + 4];
2977 uint8_t data = bios->data[offset + 5];
2978 uint8_t value;
2979
2980 if (!iexec->execute)
37383650 2981 return 6;
6ee73861
BS		 2982
2983 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2984 "Data: 0x%02X\n",
2985 offset, crtcport, crtcindex, mask, data);
2986
2987 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2988 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2989
37383650 2990 return 6;
6ee73861
BS		 2991}
2992
37383650 2993static int
6ee73861
BS		 2994init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2995{
2996 /*
2997 * INIT_PLL opcode: 0x79 ('y')
2998 *
2999 * offset (8 bit): opcode
3000 * offset + 1 (32 bit): register
3001 * offset + 5 (16 bit): freq
3002 *
3003 * Set PLL register "register" to coefficients for frequency (10kHz)
3004 * "freq"
3005 */
3006
3007 uint32_t reg = ROM32(bios->data[offset + 1]);
3008 uint16_t freq = ROM16(bios->data[offset + 5]);
3009
3010 if (!iexec->execute)
37383650 3011 return 7;
6ee73861
BS		 3012
3013 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3014
3015 setPLL(bios, reg, freq * 10);
3016
37383650 3017 return 7;
6ee73861
BS		 3018}
3019
37383650 3020static int
6ee73861
BS		 3021init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3022{
3023 /*
3024 * INIT_ZM_REG opcode: 0x7A ('z')
3025 *
3026 * offset (8 bit): opcode
3027 * offset + 1 (32 bit): register
3028 * offset + 5 (32 bit): value
3029 *
3030 * Assign "value" to "register"
3031 */
3032
3033 uint32_t reg = ROM32(bios->data[offset + 1]);
3034 uint32_t value = ROM32(bios->data[offset + 5]);
3035
3036 if (!iexec->execute)
37383650 3037 return 9;
6ee73861
BS		 3038
3039 if (reg == 0x000200)
3040 value |= 1;
3041
3042 bios_wr32(bios, reg, value);
3043
37383650 3044 return 9;
6ee73861
BS		 3045}
3046
37383650 3047static int
6ee73861
BS		 3048init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3049 struct init_exec *iexec)
3050{
3051 /*
3052 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3053 *
3054 * offset (8 bit): opcode
3055 * offset + 1 (8 bit): PLL type
3056 * offset + 2 (32 bit): frequency 0
3057 *
3058 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3059 * ram_restrict_table_ptr. The value read from there is used to select
3060 * a frequency from the table starting at 'frequency 0' to be
3061 * programmed into the PLL corresponding to 'type'.
3062 *
3063 * The PLL limits table on cards using this opcode has a mapping of
3064 * 'type' to the relevant registers.
3065 */
3066
3067 struct drm_device *dev = bios->dev;
3068 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3069 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3070 uint8_t type = bios->data[offset + 1];
3071 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3072 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 3073 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 3074 int i;
3075
3076 if (!iexec->execute)
37383650 3077 return len;
6ee73861
BS		 3078
3079 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3080 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 3081 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 3082 }
3083
3084 entry = pll_limits + pll_limits[1];
3085 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3086 if (entry[0] == type) {
3087 uint32_t reg = ROM32(entry[3]);
3088
3089 BIOSLOG(bios, "0x%04X: "
3090 "Type %02x Reg 0x%08x Freq %dKHz\n",
3091 offset, type, reg, freq);
3092
3093 setPLL(bios, reg, freq);
37383650 3094 return len;
6ee73861
BS		 3095 }
3096 }
3097
3098 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 3099 return len;
6ee73861
BS		 3100}
3101
37383650 3102static int
6ee73861
BS		 3103init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3104{
3105 /*
3106 * INIT_8C opcode: 0x8C ('')
3107 *
3108 * NOP so far....
3109 *
3110 */
3111
37383650 3112 return 1;
6ee73861
BS		 3113}
3114
37383650 3115static int
6ee73861
BS		 3116init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3117{
3118 /*
3119 * INIT_8D opcode: 0x8D ('')
3120 *
3121 * NOP so far....
3122 *
3123 */
3124
37383650 3125 return 1;
6ee73861
BS		 3126}
3127
37383650 3128static int
6ee73861
BS		 3129init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3130{
3131 /*
3132 * INIT_GPIO opcode: 0x8E ('')
3133 *
3134 * offset (8 bit): opcode
3135 *
3136 * Loop over all entries in the DCB GPIO table, and initialise
3137 * each GPIO according to various values listed in each entry
3138 */
3139
2535d71c 3140 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
ee2e0131 3141 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861 3142 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
6ee73861
BS		 3143 int i;
3144
080feda5 3145 if (dev_priv->card_type < NV_50) {
2535d71c 3146 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
309b8c89 3147 return 1;
6ee73861
BS		 3148 }
3149
2535d71c
BS		 3150 if (!iexec->execute)
3151 return 1;
6ee73861 3152
2535d71c
BS		 3153 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3154 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
3155 uint32_t r, s, v;
6ee73861 3156
2535d71c 3157 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 3158
73db4bed
BS		 3159 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3160 offset, gpio->tag, gpio->state_default);
3161 if (bios->execute)
ee2e0131 3162 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
6ee73861 3163
45284162
BS		 3164 /* The NVIDIA binary driver doesn't appear to actually do
3165 * any of this, my VBIOS does however.
3166 */
3167 /* Not a clue, needs de-magicing */
2535d71c
BS		 3168 r = nv50_gpio_ctl[gpio->line >> 4];
3169 s = (gpio->line & 0x0f);
6ee73861 3170 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2535d71c 3171 switch ((gpio->entry & 0x06000000) >> 25) {
6ee73861
BS		 3172 case 1:
3173 v |= (0x00000001 << s);
3174 break;
3175 case 2:
3176 v |= (0x00010000 << s);
3177 break;
3178 default:
3179 break;
3180 }
3181 bios_wr32(bios, r, v);
3182 }
3183
37383650 3184 return 1;
6ee73861
BS		 3185}
3186
37383650 3187static int
6ee73861
BS		 3188init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3189 struct init_exec *iexec)
3190{
3191 /*
3192 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3193 *
3194 * offset (8 bit): opcode
3195 * offset + 1 (32 bit): reg
3196 * offset + 5 (8 bit): regincrement
3197 * offset + 6 (8 bit): count
3198 * offset + 7 (32 bit): value 1,1
3199 * ...
3200 *
3201 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3202 * ram_restrict_table_ptr. The value read from here is 'n', and
3203 * "value 1,n" gets written to "reg". This repeats "count" times and on
3204 * each iteration 'm', "reg" increases by "regincrement" and
3205 * "value m,n" is used. The extent of n is limited by a number read
3206 * from the 'M' BIT table, herein called "blocklen"
3207 */
3208
3209 uint32_t reg = ROM32(bios->data[offset + 1]);
3210 uint8_t regincrement = bios->data[offset + 5];
3211 uint8_t count = bios->data[offset + 6];
3212 uint32_t strap_ramcfg, data;
37383650
MK		 3213 /* previously set by 'M' BIT table */
3214 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3215 int len = 7 + count * blocklen;
6ee73861
BS		 3216 uint8_t index;
3217 int i;
3218
309b8c89 3219 /* critical! to know the length of the opcode */;
6ee73861
BS		 3220 if (!blocklen) {
3221 NV_ERROR(bios->dev,
3222 "0x%04X: Zero block length - has the M table "
3223 "been parsed?\n", offset);
9170a824 3224 return -EINVAL;
6ee73861
BS		 3225 }
3226
309b8c89
BS		 3227 if (!iexec->execute)
3228 return len;
3229
6ee73861
BS		 3230 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3231 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3232
3233 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3234 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3235 offset, reg, regincrement, count, strap_ramcfg, index);
3236
3237 for (i = 0; i < count; i++) {
3238 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3239
3240 bios_wr32(bios, reg, data);
3241
3242 reg += regincrement;
3243 }
3244
37383650 3245 return len;
6ee73861
BS		 3246}
3247
37383650 3248static int
6ee73861
BS		 3249init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3250{
3251 /*
3252 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3253 *
3254 * offset (8 bit): opcode
3255 * offset + 1 (32 bit): src reg
3256 * offset + 5 (32 bit): dst reg
3257 *
3258 * Put contents of "src reg" into "dst reg"
3259 */
3260
3261 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3262 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3263
3264 if (!iexec->execute)
37383650 3265 return 9;
6ee73861
BS		 3266
3267 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3268
37383650 3269 return 9;
6ee73861
BS		 3270}
3271
37383650 3272static int
6ee73861
BS		 3273init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3274 struct init_exec *iexec)
3275{
3276 /*
3277 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3278 *
3279 * offset (8 bit): opcode
3280 * offset + 1 (32 bit): dst reg
3281 * offset + 5 (8 bit): count
3282 * offset + 6 (32 bit): data 1
3283 * ...
3284 *
3285 * For each of "count" values write "data n" to "dst reg"
3286 */
3287
3288 uint32_t reg = ROM32(bios->data[offset + 1]);
3289 uint8_t count = bios->data[offset + 5];
37383650 3290 int len = 6 + count * 4;
6ee73861
BS		 3291 int i;
3292
3293 if (!iexec->execute)
37383650 3294 return len;
6ee73861
BS		 3295
3296 for (i = 0; i < count; i++) {
3297 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3298 bios_wr32(bios, reg, data);
3299 }
3300
37383650 3301 return len;
6ee73861
BS		 3302}
3303
37383650 3304static int
6ee73861
BS		 3305init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3306{
3307 /*
3308 * INIT_RESERVED opcode: 0x92 ('')
3309 *
3310 * offset (8 bit): opcode
3311 *
3312 * Seemingly does nothing
3313 */
3314
37383650 3315 return 1;
6ee73861
BS		 3316}
3317
37383650 3318static int
6ee73861
BS		 3319init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3320{
3321 /*
3322 * INIT_96 opcode: 0x96 ('')
3323 *
3324 * offset (8 bit): opcode
3325 * offset + 1 (32 bit): sreg
3326 * offset + 5 (8 bit): sshift
3327 * offset + 6 (8 bit): smask
3328 * offset + 7 (8 bit): index
3329 * offset + 8 (32 bit): reg
3330 * offset + 12 (32 bit): mask
3331 * offset + 16 (8 bit): shift
3332 *
3333 */
3334
3335 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3336 uint32_t reg = ROM32(bios->data[offset + 8]);
3337 uint32_t mask = ROM32(bios->data[offset + 12]);
3338 uint32_t val;
3339
3340 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3341 if (bios->data[offset + 5] < 0x80)
3342 val >>= bios->data[offset + 5];
3343 else
3344 val <<= (0x100 - bios->data[offset + 5]);
3345 val &= bios->data[offset + 6];
3346
3347 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3348 val <<= bios->data[offset + 16];
3349
3350 if (!iexec->execute)
37383650 3351 return 17;
6ee73861
BS		 3352
3353 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3354 return 17;
6ee73861
BS		 3355}
3356
37383650 3357static int
6ee73861
BS		 3358init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3359{
3360 /*
3361 * INIT_97 opcode: 0x97 ('')
3362 *
3363 * offset (8 bit): opcode
3364 * offset + 1 (32 bit): register
3365 * offset + 5 (32 bit): mask
3366 * offset + 9 (32 bit): value
3367 *
3368 * Adds "value" to "register" preserving the fields specified
3369 * by "mask"
3370 */
3371
3372 uint32_t reg = ROM32(bios->data[offset + 1]);
3373 uint32_t mask = ROM32(bios->data[offset + 5]);
3374 uint32_t add = ROM32(bios->data[offset + 9]);
3375 uint32_t val;
3376
3377 val = bios_rd32(bios, reg);
3378 val = (val & mask) | ((val + add) & ~mask);
3379
3380 if (!iexec->execute)
37383650 3381 return 13;
6ee73861
BS		 3382
3383 bios_wr32(bios, reg, val);
37383650 3384 return 13;
6ee73861
BS		 3385}
3386
37383650 3387static int
6ee73861
BS		 3388init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3389{
3390 /*
3391 * INIT_AUXCH opcode: 0x98 ('')
3392 *
3393 * offset (8 bit): opcode
3394 * offset + 1 (32 bit): address
3395 * offset + 5 (8 bit): count
3396 * offset + 6 (8 bit): mask 0
3397 * offset + 7 (8 bit): data 0
3398 * ...
3399 *
3400 */
3401
3402 struct drm_device *dev = bios->dev;
3403 struct nouveau_i2c_chan *auxch;
3404 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3405 uint8_t count = bios->data[offset + 5];
3406 int len = 6 + count * 2;
6ee73861
BS		 3407 int ret, i;
3408
3409 if (!bios->display.output) {
3410 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
309b8c89 3411 return len;
6ee73861
BS		 3412 }
3413
3414 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3415 if (!auxch) {
3416 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3417 bios->display.output->i2c_index);
309b8c89 3418 return len;
6ee73861
BS		 3419 }
3420
3421 if (!iexec->execute)
37383650 3422 return len;
6ee73861
BS		 3423
3424 offset += 6;
37383650 3425 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3426 uint8_t data;
3427
3428 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3429 if (ret) {
3430 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
309b8c89 3431 return len;
6ee73861
BS		 3432 }
3433
3434 data &= bios->data[offset + 0];
3435 data |= bios->data[offset + 1];
3436
3437 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3438 if (ret) {
3439 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3440 return len;
6ee73861
BS		 3441 }
3442 }
3443
37383650 3444 return len;
6ee73861
BS		 3445}
3446
37383650 3447static int
6ee73861
BS		 3448init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3449{
3450 /*
3451 * INIT_ZM_AUXCH opcode: 0x99 ('')
3452 *
3453 * offset (8 bit): opcode
3454 * offset + 1 (32 bit): address
3455 * offset + 5 (8 bit): count
3456 * offset + 6 (8 bit): data 0
3457 * ...
3458 *
3459 */
3460
3461 struct drm_device *dev = bios->dev;
3462 struct nouveau_i2c_chan *auxch;
3463 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3464 uint8_t count = bios->data[offset + 5];
3465 int len = 6 + count;
6ee73861
BS		 3466 int ret, i;
3467
3468 if (!bios->display.output) {
3469 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
309b8c89 3470 return len;
6ee73861
BS		 3471 }
3472
3473 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3474 if (!auxch) {
3475 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3476 bios->display.output->i2c_index);
309b8c89 3477 return len;
6ee73861
BS		 3478 }
3479
3480 if (!iexec->execute)
37383650 3481 return len;
6ee73861
BS		 3482
3483 offset += 6;
37383650 3484 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3485 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3486 if (ret) {
3487 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3488 return len;
6ee73861
BS		 3489 }
3490 }
3491
37383650 3492 return len;
6ee73861
BS		 3493}
3494
3495static struct init_tbl_entry itbl_entry[] = {
3496 /* command name , id , length , offset , mult , command handler */
3497 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3498 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3499 { "INIT_REPEAT" , 0x33, init_repeat },
3500 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3501 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3502 { "INIT_COPY" , 0x37, init_copy },
3503 { "INIT_NOT" , 0x38, init_not },
3504 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3505 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3506 { "INIT_OP_3B" , 0x3B, init_op_3b },
3507 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3508 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3509 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3510 { "INIT_PLL2" , 0x4B, init_pll2 },
3511 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3512 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3513 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3514 { "INIT_TMDS" , 0x4F, init_tmds },
3515 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3516 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3517 { "INIT_CR" , 0x52, init_cr },
3518 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3519 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3520 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3521 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3522 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 3523 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3524 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3525 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3526 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3527 { "INIT_RESET" , 0x65, init_reset },
3528 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3529 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3530 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3531 { "INIT_IO" , 0x69, init_io },
3532 { "INIT_SUB" , 0x6B, init_sub },
3533 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3534 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3535 { "INIT_MACRO" , 0x6F, init_macro },
3536 { "INIT_DONE" , 0x71, init_done },
3537 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3538 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3539 { "INIT_TIME" , 0x74, init_time },
3540 { "INIT_CONDITION" , 0x75, init_condition },
3541 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3542 { "INIT_INDEX_IO" , 0x78, init_index_io },
3543 { "INIT_PLL" , 0x79, init_pll },
3544 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3545 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3546 { "INIT_8C" , 0x8C, init_8c },
3547 { "INIT_8D" , 0x8D, init_8d },
3548 { "INIT_GPIO" , 0x8E, init_gpio },
3549 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3550 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3551 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3552 { "INIT_RESERVED" , 0x92, init_reserved },
3553 { "INIT_96" , 0x96, init_96 },
3554 { "INIT_97" , 0x97, init_97 },
3555 { "INIT_AUXCH" , 0x98, init_auxch },
3556 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3557 { NULL , 0 , NULL }
6ee73861
BS		 3558};
3559
6ee73861
BS		 3560#define MAX_TABLE_OPS 1000
3561
3562static int
3563parse_init_table(struct nvbios *bios, unsigned int offset,
3564 struct init_exec *iexec)
3565{
3566 /*
3567 * Parses all commands in an init table.
3568 *
3569 * We start out executing all commands found in the init table. Some
3570 * opcodes may change the status of iexec->execute to SKIP, which will
3571 * cause the following opcodes to perform no operation until the value
3572 * is changed back to EXECUTE.
3573 */
3574
92b96187 3575 int count = 0, i, ret;
6ee73861
BS		 3576 uint8_t id;
3577
3578 /*
3579 * Loop until INIT_DONE causes us to break out of the loop
3580 * (or until offset > bios length just in case... )
3581 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3582 */
3583 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3584 id = bios->data[offset];
3585
3586 /* Find matching id in itbl_entry */
3587 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3588 ;
3589
92b96187 3590 if (!itbl_entry[i].name) {
6ee73861
BS		 3591 NV_ERROR(bios->dev,
3592 "0x%04X: Init table command not found: "
3593 "0x%02X\n", offset, id);
3594 return -ENOENT;
3595 }
92b96187
BS		 3596
3597 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3598 itbl_entry[i].id, itbl_entry[i].name);
3599
3600 /* execute eventual command handler */
3601 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3602 if (ret < 0) {
3603 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3604 "table opcode: %s %d\n", offset,
3605 itbl_entry[i].name, ret);
3606 }
3607
3608 if (ret <= 0)
3609 break;
3610
3611 /*
3612 * Add the offset of the current command including all data
3613 * of that command. The offset will then be pointing on the
3614 * next op code.
3615 */
3616 offset += ret;
6ee73861
BS		 3617 }
3618
3619 if (offset >= bios->length)
3620 NV_WARN(bios->dev,
3621 "Offset 0x%04X greater than known bios image length. "
3622 "Corrupt image?\n", offset);
3623 if (count >= MAX_TABLE_OPS)
3624 NV_WARN(bios->dev,
3625 "More than %d opcodes to a table is unlikely, "
3626 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3627
3628 return 0;
3629}
3630
3631static void
3632parse_init_tables(struct nvbios *bios)
3633{
3634 /* Loops and calls parse_init_table() for each present table. */
3635
3636 int i = 0;
3637 uint16_t table;
3638 struct init_exec iexec = {true, false};
3639
3640 if (bios->old_style_init) {
3641 if (bios->init_script_tbls_ptr)
3642 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3643 if (bios->extra_init_script_tbl_ptr)
3644 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3645
3646 return;
3647 }
3648
3649 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3650 NV_INFO(bios->dev,
3651 "Parsing VBIOS init table %d at offset 0x%04X\n",
3652 i / 2, table);
3653 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3654
3655 parse_init_table(bios, table, &iexec);
3656 i += 2;
3657 }
3658}
3659
3660static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3661{
3662 int compare_record_len, i = 0;
3663 uint16_t compareclk, scriptptr = 0;
3664
3665 if (bios->major_version < 5) /* pre BIT */
3666 compare_record_len = 3;
3667 else
3668 compare_record_len = 4;
3669
3670 do {
3671 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3672 if (pxclk >= compareclk * 10) {
3673 if (bios->major_version < 5) {
3674 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3675 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3676 } else
3677 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3678 break;
3679 }
3680 i++;
3681 } while (compareclk);
3682
3683 return scriptptr;
3684}
3685
3686static void
3687run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3688 struct dcb_entry *dcbent, int head, bool dl)
3689{
3690 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3691 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3692 struct init_exec iexec = {true, false};
3693
3694 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3695 scriptptr);
3696 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3697 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3698 /* note: if dcb entries have been merged, index may be misleading */
3699 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3700 parse_init_table(bios, scriptptr, &iexec);
3701
3702 nv04_dfp_bind_head(dev, dcbent, head, dl);
3703}
3704
3705static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3706{
3707 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3708 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3709 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3710 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3711
3712 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3713 return -EINVAL;
3714
3715 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3716
3717 if (script == LVDS_PANEL_OFF) {
3718 /* off-on delay in ms */
3719 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3720 }
3721#ifdef __powerpc__
3722 /* Powerbook specific quirks */
3d9aefb8
FJ		 3723 if ((dev->pci_device & 0xffff) == 0x0179 ||
3724 (dev->pci_device & 0xffff) == 0x0189 ||
3725 (dev->pci_device & 0xffff) == 0x0329) {
3726 if (script == LVDS_RESET) {
3727 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3728
3729 } else if (script == LVDS_PANEL_ON) {
3730 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3731 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3732 | (1 << 31));
3733 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3734 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3735
3736 } else if (script == LVDS_PANEL_OFF) {
3737 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3738 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3739 & ~(1 << 31));
3740 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3741 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3742 }
3743 }
3744#endif
3745
3746 return 0;
3747}
3748
3749static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3750{
3751 /*
3752 * The BIT LVDS table's header has the information to setup the
3753 * necessary registers. Following the standard 4 byte header are:
3754 * A bitmask byte and a dual-link transition pxclk value for use in
3755 * selecting the init script when not using straps; 4 script pointers
3756 * for panel power, selected by output and on/off; and 8 table pointers
3757 * for panel init, the needed one determined by output, and bits in the
3758 * conf byte. These tables are similar to the TMDS tables, consisting
3759 * of a list of pxclks and script pointers.
3760 */
3761 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3762 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3763 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3764 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3765
3766 /*
3767 * For now we assume version 3.0 table - g80 support will need some
3768 * changes
3769 */
3770
3771 switch (script) {
3772 case LVDS_INIT:
3773 return -ENOSYS;
3774 case LVDS_BACKLIGHT_ON:
3775 case LVDS_PANEL_ON:
3776 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3777 break;
3778 case LVDS_BACKLIGHT_OFF:
3779 case LVDS_PANEL_OFF:
3780 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3781 break;
3782 case LVDS_RESET:
f3bbb9cc
BS		 3783 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3784 if (dcbent->or == 4)
3785 clktable += 8;
3786
6ee73861
BS		 3787 if (dcbent->lvdsconf.use_straps_for_mode) {
3788 if (bios->fp.dual_link)
f3bbb9cc
BS		 3789 clktable += 4;
3790 if (bios->fp.if_is_24bit)
3791 clktable += 2;
6ee73861
BS		 3792 } else {
3793 /* using EDID */
f3bbb9cc 3794 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3795
3796 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3797 clktable += 4;
3798 cmpval_24bit <<= 1;
6ee73861 3799 }
f3bbb9cc
BS		 3800
3801 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3802 clktable += 2;
6ee73861
BS		 3803 }
3804
f3bbb9cc 3805 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3806 if (!clktable) {
3807 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3808 return -ENOENT;
3809 }
3810 scriptptr = clkcmptable(bios, clktable, pxclk);
3811 }
3812
3813 if (!scriptptr) {
3814 NV_ERROR(dev, "LVDS output init script not found\n");
3815 return -ENOENT;
3816 }
3817 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3818
3819 return 0;
3820}
3821
3822int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3823{
3824 /*
3825 * LVDS operations are multiplexed in an effort to present a single API
3826 * which works with two vastly differing underlying structures.
3827 * This acts as the demux
3828 */
3829
3830 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3831 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3832 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3833 uint32_t sel_clk_binding, sel_clk;
3834 int ret;
3835
3836 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3837 (lvds_ver >= 0x30 && script == LVDS_INIT))
3838 return 0;
3839
3840 if (!bios->fp.lvds_init_run) {
3841 bios->fp.lvds_init_run = true;
3842 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3843 }
3844
3845 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3846 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3847 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3848 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3849
3850 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3851
3852 /* don't let script change pll->head binding */
3853 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3854
3855 if (lvds_ver < 0x30)
3856 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3857 else
3858 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3859
3860 bios->fp.last_script_invoc = (script << 1 | head);
3861
3862 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3863 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3864 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3865 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3866
3867 return ret;
3868}
3869
3870struct lvdstableheader {
3871 uint8_t lvds_ver, headerlen, recordlen;
3872};
3873
3874static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3875{
3876 /*
3877 * BMP version (0xa) LVDS table has a simple header of version and
3878 * record length. The BIT LVDS table has the typical BIT table header:
3879 * version byte, header length byte, record length byte, and a byte for
3880 * the maximum number of records that can be held in the table.
3881 */
3882
3883 uint8_t lvds_ver, headerlen, recordlen;
3884
3885 memset(lth, 0, sizeof(struct lvdstableheader));
3886
3887 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3888 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3889 return -EINVAL;
3890 }
3891
3892 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3893
3894 switch (lvds_ver) {
3895 case 0x0a: /* pre NV40 */
3896 headerlen = 2;
3897 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3898 break;
3899 case 0x30: /* NV4x */
3900 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3901 if (headerlen < 0x1f) {
3902 NV_ERROR(dev, "LVDS table header not understood\n");
3903 return -EINVAL;
3904 }
3905 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3906 break;
3907 case 0x40: /* G80/G90 */
3908 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3909 if (headerlen < 0x7) {
3910 NV_ERROR(dev, "LVDS table header not understood\n");
3911 return -EINVAL;
3912 }
3913 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3914 break;
3915 default:
3916 NV_ERROR(dev,
3917 "LVDS table revision %d.%d not currently supported\n",
3918 lvds_ver >> 4, lvds_ver & 0xf);
3919 return -ENOSYS;
3920 }
3921
3922 lth->lvds_ver = lvds_ver;
3923 lth->headerlen = headerlen;
3924 lth->recordlen = recordlen;
3925
3926 return 0;
3927}
3928
3929static int
3930get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3931{
3932 struct drm_nouveau_private *dev_priv = dev->dev_private;
3933
3934 /*
3935 * The fp strap is normally dictated by the "User Strap" in
3936 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3937 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3938 * by the PCI subsystem ID during POST, but not before the previous user
3939 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3940 * read and used instead
3941 */
3942
3943 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3944 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3945
3946 if (dev_priv->card_type >= NV_50)
3947 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3948 else
3949 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3950}
3951
3952static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3953{
3954 uint8_t *fptable;
3955 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3956 int ret, ofs, fpstrapping;
3957 struct lvdstableheader lth;
3958
3959 if (bios->fp.fptablepointer == 0x0) {
3960 /* Apple cards don't have the fp table; the laptops use DDC */
3961 /* The table is also missing on some x86 IGPs */
3962#ifndef __powerpc__
3963 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3964#endif
04a39c57 3965 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3966 return 0;
3967 }
3968
3969 fptable = &bios->data[bios->fp.fptablepointer];
3970 fptable_ver = fptable[0];
3971
3972 switch (fptable_ver) {
3973 /*
3974 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3975 * version field, and miss one of the spread spectrum/PWM bytes.
3976 * This could affect early GF2Go parts (not seen any appropriate ROMs
3977 * though). Here we assume that a version of 0x05 matches this case
3978 * (combining with a BMP version check would be better), as the
3979 * common case for the panel type field is 0x0005, and that is in
3980 * fact what we are reading the first byte of.
3981 */
3982 case 0x05: /* some NV10, 11, 15, 16 */
3983 recordlen = 42;
3984 ofs = -1;
3985 break;
3986 case 0x10: /* some NV15/16, and NV11+ */
3987 recordlen = 44;
3988 ofs = 0;
3989 break;
3990 case 0x20: /* NV40+ */
3991 headerlen = fptable[1];
3992 recordlen = fptable[2];
3993 fpentries = fptable[3];
3994 /*
3995 * fptable[4] is the minimum
3996 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3997 */
04a39c57 3998 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 3999 ofs = -7;
4000 break;
4001 default:
4002 NV_ERROR(dev,
4003 "FP table revision %d.%d not currently supported\n",
4004 fptable_ver >> 4, fptable_ver & 0xf);
4005 return -ENOSYS;
4006 }
4007
4008 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4009 return 0;
4010
4011 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4012 if (ret)
4013 return ret;
4014
4015 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4016 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4017 lth.headerlen + 1;
4018 bios->fp.xlatwidth = lth.recordlen;
4019 }
4020 if (bios->fp.fpxlatetableptr == 0x0) {
4021 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4022 return -EINVAL;
4023 }
4024
4025 fpstrapping = get_fp_strap(dev, bios);
4026
4027 fpindex = bios->data[bios->fp.fpxlatetableptr +
4028 fpstrapping * bios->fp.xlatwidth];
4029
4030 if (fpindex > fpentries) {
4031 NV_ERROR(dev, "Bad flat panel table index\n");
4032 return -ENOENT;
4033 }
4034
4035 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4036 if (lth.lvds_ver > 0x10)
04a39c57 4037 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 4038
4039 /*
4040 * If either the strap or xlated fpindex value are 0xf there is no
4041 * panel using a strap-derived bios mode present. this condition
4042 * includes, but is different from, the DDC panel indicator above
4043 */
4044 if (fpstrapping == 0xf || fpindex == 0xf)
4045 return 0;
4046
4047 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4048 recordlen * fpindex + ofs;
4049
4050 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4051 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4052 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4053 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4054
4055 return 0;
4056}
4057
4058bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4059{
4060 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4061 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4062 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4063
4064 if (!mode) /* just checking whether we can produce a mode */
4065 return bios->fp.mode_ptr;
4066
4067 memset(mode, 0, sizeof(struct drm_display_mode));
4068 /*
4069 * For version 1.0 (version in byte 0):
4070 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4071 * single/dual link, and type (TFT etc.)
4072 * bytes 3-6 are bits per colour in RGBX
4073 */
4074 mode->clock = ROM16(mode_entry[7]) * 10;
4075 /* bytes 9-10 is HActive */
4076 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4077 /*
4078 * bytes 13-14 is HValid Start
4079 * bytes 15-16 is HValid End
4080 */
4081 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4082 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4083 mode->htotal = ROM16(mode_entry[21]) + 1;
4084 /* bytes 23-24, 27-30 similarly, but vertical */
4085 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4086 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4087 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4088 mode->vtotal = ROM16(mode_entry[35]) + 1;
4089 mode->flags |= (mode_entry[37] & 0x10) ?
4090 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4091 mode->flags |= (mode_entry[37] & 0x1) ?
4092 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4093 /*
4094 * bytes 38-39 relate to spread spectrum settings
4095 * bytes 40-43 are something to do with PWM
4096 */
4097
4098 mode->status = MODE_OK;
4099 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4100 drm_mode_set_name(mode);
4101 return bios->fp.mode_ptr;
4102}
4103
4104int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4105{
4106 /*
4107 * The LVDS table header is (mostly) described in
4108 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4109 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4110 * straps are not being used for the panel, this specifies the frequency
4111 * at which modes should be set up in the dual link style.
4112 *
4113 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 4114 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 4115 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4116 * numbers for use by INIT_SUB which controlled panel init and power,
4117 * and finally a dword of ms to sleep between power off and on
4118 * operations.
4119 *
4120 * In the BIT versions, the table following the header serves as an
4121 * integrated config and xlat table: the records in the table are
4122 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4123 * two bytes - the first as a config byte, the second for indexing the
4124 * fp mode table pointed to by the BIT 'D' table
4125 *
4126 * DDC is not used until after card init, so selecting the correct table
4127 * entry and setting the dual link flag for EDID equipped panels,
4128 * requiring tests against the native-mode pixel clock, cannot be done
4129 * until later, when this function should be called with non-zero pxclk
4130 */
4131 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4132 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4133 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4134 struct lvdstableheader lth;
4135 uint16_t lvdsofs;
04a39c57 4136 int ret, chip_version = bios->chip_version;
6ee73861
BS		 4137
4138 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4139 if (ret)
4140 return ret;
4141
4142 switch (lth.lvds_ver) {
4143 case 0x0a: /* pre NV40 */
4144 lvdsmanufacturerindex = bios->data[
4145 bios->fp.fpxlatemanufacturertableptr +
4146 fpstrapping];
4147
4148 /* we're done if this isn't the EDID panel case */
4149 if (!pxclk)
4150 break;
4151
4152 if (chip_version < 0x25) {
4153 /* nv17 behaviour
4154 *
4155 * It seems the old style lvds script pointer is reused
4156 * to select 18/24 bit colour depth for EDID panels.
4157 */
4158 lvdsmanufacturerindex =
4159 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4160 2 : 0;
4161 if (pxclk >= bios->fp.duallink_transition_clk)
4162 lvdsmanufacturerindex++;
4163 } else if (chip_version < 0x30) {
4164 /* nv28 behaviour (off-chip encoder)
4165 *
4166 * nv28 does a complex dance of first using byte 121 of
4167 * the EDID to choose the lvdsmanufacturerindex, then
4168 * later attempting to match the EDID manufacturer and
4169 * product IDs in a table (signature 'pidt' (panel id
4170 * table?)), setting an lvdsmanufacturerindex of 0 and
4171 * an fp strap of the match index (or 0xf if none)
4172 */
4173 lvdsmanufacturerindex = 0;
4174 } else {
4175 /* nv31, nv34 behaviour */
4176 lvdsmanufacturerindex = 0;
4177 if (pxclk >= bios->fp.duallink_transition_clk)
4178 lvdsmanufacturerindex = 2;
4179 if (pxclk >= 140000)
4180 lvdsmanufacturerindex = 3;
4181 }
4182
4183 /*
4184 * nvidia set the high nibble of (cr57=f, cr58) to
4185 * lvdsmanufacturerindex in this case; we don't
4186 */
4187 break;
4188 case 0x30: /* NV4x */
4189 case 0x40: /* G80/G90 */
4190 lvdsmanufacturerindex = fpstrapping;
4191 break;
4192 default:
4193 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4194 return -ENOSYS;
4195 }
4196
4197 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4198 switch (lth.lvds_ver) {
4199 case 0x0a:
4200 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4201 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4202 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4203 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4204 *if_is_24bit = bios->data[lvdsofs] & 16;
4205 break;
4206 case 0x30:
f3bbb9cc 4207 case 0x40:
6ee73861
BS		 4208 /*
4209 * No sign of the "power off for reset" or "reset for panel
4210 * on" bits, but it's safer to assume we should
4211 */
4212 bios->fp.power_off_for_reset = true;
4213 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 4214
6ee73861
BS		 4215 /*
4216 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 4217 * over-written, and if_is_24bit isn't used
6ee73861
BS		 4218 */
4219 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 4220 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4221 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4222 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4223 break;
4224 }
4225
2eb92c80
BS		 4226 /* Dell Latitude D620 reports a too-high value for the dual-link
4227 * transition freq, causing us to program the panel incorrectly.
4228 *
4229 * It doesn't appear the VBIOS actually uses its transition freq
4230 * (90000kHz), instead it uses the "Number of LVDS channels" field
4231 * out of the panel ID structure (http://www.spwg.org/).
4232 *
4233 * For the moment, a quirk will do :)
4234 */
4235 if ((dev->pdev->device == 0x01d7) &&
4236 (dev->pdev->subsystem_vendor == 0x1028) &&
4237 (dev->pdev->subsystem_device == 0x01c2)) {
4238 bios->fp.duallink_transition_clk = 80000;
4239 }
4240
6ee73861
BS		 4241 /* set dual_link flag for EDID case */
4242 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4243 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4244
4245 *dl = bios->fp.dual_link;
4246
4247 return 0;
4248}
4249
4250static uint8_t *
4251bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
1eb38100
BS		 4252 uint16_t record, int record_len, int record_nr,
4253 bool match_link)
6ee73861
BS		 4254{
4255 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4256 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4257 uint32_t entry;
4258 uint16_t table;
4259 int i, v;
4260
1eb38100
BS		 4261 switch (dcbent->type) {
4262 case OUTPUT_TMDS:
4263 case OUTPUT_LVDS:
4264 case OUTPUT_DP:
4265 break;
4266 default:
4267 match_link = false;
4268 break;
4269 }
4270
6ee73861
BS		 4271 for (i = 0; i < record_nr; i++, record += record_len) {
4272 table = ROM16(bios->data[record]);
4273 if (!table)
4274 continue;
4275 entry = ROM32(bios->data[table]);
4276
1eb38100
BS		 4277 if (match_link) {
4278 v = (entry & 0x00c00000) >> 22;
4279 if (!(v & dcbent->sorconf.link))
4280 continue;
4281 }
4282
6ee73861
BS		 4283 v = (entry & 0x000f0000) >> 16;
4284 if (!(v & dcbent->or))
4285 continue;
4286
4287 v = (entry & 0x000000f0) >> 4;
4288 if (v != dcbent->location)
4289 continue;
4290
4291 v = (entry & 0x0000000f);
4292 if (v != dcbent->type)
4293 continue;
4294
4295 return &bios->data[table];
4296 }
4297
4298 return NULL;
4299}
4300
4301void *
4302nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
4303 int *length)
4304{
4305 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4306 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4307 uint8_t *table;
4308
4309 if (!bios->display.dp_table_ptr) {
4310 NV_ERROR(dev, "No pointer to DisplayPort table\n");
4311 return NULL;
4312 }
4313 table = &bios->data[bios->display.dp_table_ptr];
4314
c52e53fd 4315 if (table[0] != 0x20 && table[0] != 0x21) {
6ee73861
BS		 4316 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
4317 table[0]);
4318 return NULL;
4319 }
4320
4321 *length = table[4];
4322 return bios_output_config_match(dev, dcbent,
4323 bios->display.dp_table_ptr + table[1],
1eb38100 4324 table[2], table[3], table[0] >= 0x21);
6ee73861
BS		 4325}
4326
4327int
4328nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4329 uint32_t sub, int pxclk)
4330{
4331 /*
4332 * The display script table is located by the BIT 'U' table.
4333 *
4334 * It contains an array of pointers to various tables describing
4335 * a particular output type. The first 32-bits of the output
4336 * tables contains similar information to a DCB entry, and is
4337 * used to decide whether that particular table is suitable for
4338 * the output you want to access.
4339 *
4340 * The "record header length" field here seems to indicate the
4341 * offset of the first configuration entry in the output tables.
4342 * This is 10 on most cards I've seen, but 12 has been witnessed
4343 * on DP cards, and there's another script pointer within the
4344 * header.
4345 *
4346 * offset + 0 ( 8 bits): version
4347 * offset + 1 ( 8 bits): header length
4348 * offset + 2 ( 8 bits): record length
4349 * offset + 3 ( 8 bits): number of records
4350 * offset + 4 ( 8 bits): record header length
4351 * offset + 5 (16 bits): pointer to first output script table
4352 */
4353
4354 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4355 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4356 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4357 uint8_t *otable = NULL;
4358 uint16_t script;
4359 int i = 0;
4360
4361 if (!bios->display.script_table_ptr) {
4362 NV_ERROR(dev, "No pointer to output script table\n");
4363 return 1;
4364 }
4365
4366 /*
4367 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4368 * so until they are, we really don't need to care.
4369 */
4370 if (table[0] < 0x20)
4371 return 1;
4372
4373 if (table[0] != 0x20 && table[0] != 0x21) {
4374 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4375 table[0]);
4376 return 1;
4377 }
4378
4379 /*
4380 * The output script tables describing a particular output type
4381 * look as follows:
4382 *
4383 * offset + 0 (32 bits): output this table matches (hash of DCB)
4384 * offset + 4 ( 8 bits): unknown
4385 * offset + 5 ( 8 bits): number of configurations
4386 * offset + 6 (16 bits): pointer to some script
4387 * offset + 8 (16 bits): pointer to some script
4388 *
4389 * headerlen == 10
4390 * offset + 10 : configuration 0
4391 *
4392 * headerlen == 12
4393 * offset + 10 : pointer to some script
4394 * offset + 12 : configuration 0
4395 *
4396 * Each config entry is as follows:
4397 *
4398 * offset + 0 (16 bits): unknown, assumed to be a match value
4399 * offset + 2 (16 bits): pointer to script table (clock set?)
4400 * offset + 4 (16 bits): pointer to script table (reset?)
4401 *
4402 * There doesn't appear to be a count value to say how many
4403 * entries exist in each script table, instead, a 0 value in
4404 * the first 16-bit word seems to indicate both the end of the
4405 * list and the default entry. The second 16-bit word in the
4406 * script tables is a pointer to the script to execute.
4407 */
4408
ef2bb506 4409 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 4410 dcbent->type, dcbent->location, dcbent->or);
4411 otable = bios_output_config_match(dev, dcbent, table[1] +
4412 bios->display.script_table_ptr,
1eb38100 4413 table[2], table[3], table[0] >= 0x21);
6ee73861
BS		 4414 if (!otable) {
4415 NV_ERROR(dev, "Couldn't find matching output script table\n");
4416 return 1;
4417 }
4418
4419 if (pxclk < -2 || pxclk > 0) {
4420 /* Try to find matching script table entry */
4421 for (i = 0; i < otable[5]; i++) {
4422 if (ROM16(otable[table[4] + i*6]) == sub)
4423 break;
4424 }
4425
4426 if (i == otable[5]) {
4427 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4428 "using first\n",
4429 sub, dcbent->type, dcbent->or);
4430 i = 0;
4431 }
4432 }
4433
6ee73861
BS		 4434 if (pxclk == 0) {
4435 script = ROM16(otable[6]);
4436 if (!script) {
ef2bb506 4437 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4438 return 1;
4439 }
4440
4441 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 4442 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4443 } else
4444 if (pxclk == -1) {
4445 script = ROM16(otable[8]);
4446 if (!script) {
ef2bb506 4447 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4448 return 1;
4449 }
4450
4451 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 4452 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4453 } else
4454 if (pxclk == -2) {
4455 if (table[4] >= 12)
4456 script = ROM16(otable[10]);
4457 else
4458 script = 0;
4459 if (!script) {
ef2bb506 4460 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4461 return 1;
4462 }
4463
4464 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 4465 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4466 } else
4467 if (pxclk > 0) {
4468 script = ROM16(otable[table[4] + i*6 + 2]);
4469 if (script)
4470 script = clkcmptable(bios, script, pxclk);
4471 if (!script) {
4472 NV_ERROR(dev, "clock script 0 not found\n");
4473 return 1;
4474 }
4475
4476 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 4477 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4478 } else
4479 if (pxclk < 0) {
4480 script = ROM16(otable[table[4] + i*6 + 4]);
4481 if (script)
4482 script = clkcmptable(bios, script, -pxclk);
4483 if (!script) {
ef2bb506 4484 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4485 return 1;
4486 }
4487
4488 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 4489 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4490 }
4491
4492 return 0;
4493}
4494
4495
4496int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4497{
4498 /*
4499 * the pxclk parameter is in kHz
4500 *
4501 * This runs the TMDS regs setting code found on BIT bios cards
4502 *
4503 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4504 * ffs(or) == 3, use the second.
4505 */
4506
4507 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4508 struct nvbios *bios = &dev_priv->vbios;
4509 int cv = bios->chip_version;
6ee73861
BS		 4510 uint16_t clktable = 0, scriptptr;
4511 uint32_t sel_clk_binding, sel_clk;
4512
4513 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4514 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4515 dcbent->location != DCB_LOC_ON_CHIP)
4516 return 0;
4517
4518 switch (ffs(dcbent->or)) {
4519 case 1:
4520 clktable = bios->tmds.output0_script_ptr;
4521 break;
4522 case 2:
4523 case 3:
4524 clktable = bios->tmds.output1_script_ptr;
4525 break;
4526 }
4527
4528 if (!clktable) {
4529 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4530 return -EINVAL;
4531 }
4532
4533 scriptptr = clkcmptable(bios, clktable, pxclk);
4534
4535 if (!scriptptr) {
4536 NV_ERROR(dev, "TMDS output init script not found\n");
4537 return -ENOENT;
4538 }
4539
4540 /* don't let script change pll->head binding */
4541 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4542 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4543 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4544 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4545
4546 return 0;
4547}
4548
4549int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4550{
4551 /*
4552 * PLL limits table
4553 *
4554 * Version 0x10: NV30, NV31
4555 * One byte header (version), one record of 24 bytes
4556 * Version 0x11: NV36 - Not implemented
4557 * Seems to have same record style as 0x10, but 3 records rather than 1
4558 * Version 0x20: Found on Geforce 6 cards
4559 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4560 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4561 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4562 * length in general, some (integrated) have an extra configuration byte
4563 * Version 0x30: Found on Geforce 8, separates the register mapping
4564 * from the limits tables.
4565 */
4566
4567 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4568 struct nvbios *bios = &dev_priv->vbios;
4569 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4570 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4571 uint32_t crystal_strap_mask, crystal_straps;
4572
4573 if (!bios->pll_limit_tbl_ptr) {
4574 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4575 cv >= 0x40) {
4576 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4577 return -EINVAL;
4578 }
4579 } else
4580 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4581
4582 crystal_strap_mask = 1 << 6;
4583 /* open coded dev->twoHeads test */
4584 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4585 crystal_strap_mask |= 1 << 22;
4586 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4587 crystal_strap_mask;
4588
4589 switch (pll_lim_ver) {
4590 /*
4591 * We use version 0 to indicate a pre limit table bios (single stage
4592 * pll) and load the hard coded limits instead.
4593 */
4594 case 0:
4595 break;
4596 case 0x10:
4597 case 0x11:
4598 /*
4599 * Strictly v0x11 has 3 entries, but the last two don't seem
4600 * to get used.
4601 */
4602 headerlen = 1;
4603 recordlen = 0x18;
4604 entries = 1;
4605 pllindex = 0;
4606 break;
4607 case 0x20:
4608 case 0x21:
4609 case 0x30:
4610 case 0x40:
4611 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4612 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4613 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4614 break;
4615 default:
4616 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4617 "supported\n", pll_lim_ver);
4618 return -ENOSYS;
4619 }
4620
4621 /* initialize all members to zero */
4622 memset(pll_lim, 0, sizeof(struct pll_lims));
4623
4624 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4625 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4626
4627 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4628 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4629 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4630 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4631 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4632 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4633 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4634
4635 /* these values taken from nv30/31/36 */
4636 pll_lim->vco1.min_n = 0x1;
4637 if (cv == 0x36)
4638 pll_lim->vco1.min_n = 0x5;
4639 pll_lim->vco1.max_n = 0xff;
4640 pll_lim->vco1.min_m = 0x1;
4641 pll_lim->vco1.max_m = 0xd;
4642 pll_lim->vco2.min_n = 0x4;
4643 /*
4644 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4645 * table version (apart from nv35)), N2 is compared to
4646 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4647 * save a comparison
4648 */
4649 pll_lim->vco2.max_n = 0x28;
4650 if (cv == 0x30 || cv == 0x35)
4651 /* only 5 bits available for N2 on nv30/35 */
4652 pll_lim->vco2.max_n = 0x1f;
4653 pll_lim->vco2.min_m = 0x1;
4654 pll_lim->vco2.max_m = 0x4;
4655 pll_lim->max_log2p = 0x7;
4656 pll_lim->max_usable_log2p = 0x6;
4657 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4658 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4659 uint32_t reg = 0; /* default match */
4660 uint8_t *pll_rec;
4661 int i;
4662
4663 /*
4664 * First entry is default match, if nothing better. warn if
4665 * reg field nonzero
4666 */
4667 if (ROM32(bios->data[plloffs]))
4668 NV_WARN(dev, "Default PLL limit entry has non-zero "
4669 "register field\n");
4670
4671 if (limit_match > MAX_PLL_TYPES)
4672 /* we've been passed a reg as the match */
4673 reg = limit_match;
4674 else /* limit match is a pll type */
4675 for (i = 1; i < entries && !reg; i++) {
4676 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4677
4678 if (limit_match == NVPLL &&
4679 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4680 reg = cmpreg;
4681 if (limit_match == MPLL &&
4682 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4683 reg = cmpreg;
4684 if (limit_match == VPLL1 &&
4685 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4686 reg = cmpreg;
4687 if (limit_match == VPLL2 &&
4688 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4689 reg = cmpreg;
4690 }
4691
4692 for (i = 1; i < entries; i++)
4693 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4694 pllindex = i;
4695 break;
4696 }
4697
4698 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4699
4700 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4701 pllindex ? reg : 0);
4702
4703 /*
4704 * Frequencies are stored in tables in MHz, kHz are more
4705 * useful, so we convert.
4706 */
4707
4708 /* What output frequencies can each VCO generate? */
4709 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4710 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4711 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4712 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4713
4714 /* What input frequencies they accept (past the m-divider)? */
4715 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4716 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4717 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4718 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4719
4720 /* What values are accepted as multiplier and divider? */
4721 pll_lim->vco1.min_n = pll_rec[20];
4722 pll_lim->vco1.max_n = pll_rec[21];
4723 pll_lim->vco1.min_m = pll_rec[22];
4724 pll_lim->vco1.max_m = pll_rec[23];
4725 pll_lim->vco2.min_n = pll_rec[24];
4726 pll_lim->vco2.max_n = pll_rec[25];
4727 pll_lim->vco2.min_m = pll_rec[26];
4728 pll_lim->vco2.max_m = pll_rec[27];
4729
4730 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4731 if (pll_lim->max_log2p > 0x7)
4732 /* pll decoding in nv_hw.c assumes never > 7 */
4733 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4734 pll_lim->max_log2p);
4735 if (cv < 0x60)
4736 pll_lim->max_usable_log2p = 0x6;
4737 pll_lim->log2p_bias = pll_rec[30];
4738
4739 if (recordlen > 0x22)
4740 pll_lim->refclk = ROM32(pll_rec[31]);
4741
4742 if (recordlen > 0x23 && pll_rec[35])
4743 NV_WARN(dev,
4744 "Bits set in PLL configuration byte (%x)\n",
4745 pll_rec[35]);
4746
4747 /* C51 special not seen elsewhere */
4748 if (cv == 0x51 && !pll_lim->refclk) {
4749 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4750
4751 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4752 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4753 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4754 pll_lim->refclk = 200000;
4755 else
4756 pll_lim->refclk = 25000;
4757 }
4758 }
4759 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4760 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4761 uint8_t *record = NULL;
4762 int i;
4763
4764 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4765 limit_match);
4766
4767 for (i = 0; i < entries; i++, entry += recordlen) {
4768 if (ROM32(entry[3]) == limit_match) {
4769 record = &bios->data[ROM16(entry[1])];
4770 break;
4771 }
4772 }
4773
4774 if (!record) {
4775 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4776 "limits table", limit_match);
4777 return -ENOENT;
4778 }
4779
4780 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4781 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4782 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4783 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4784 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4785 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4786 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4787 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4788 pll_lim->vco1.min_n = record[16];
4789 pll_lim->vco1.max_n = record[17];
4790 pll_lim->vco1.min_m = record[18];
4791 pll_lim->vco1.max_m = record[19];
4792 pll_lim->vco2.min_n = record[20];
4793 pll_lim->vco2.max_n = record[21];
4794 pll_lim->vco2.min_m = record[22];
4795 pll_lim->vco2.max_m = record[23];
4796 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4797 pll_lim->log2p_bias = record[27];
4798 pll_lim->refclk = ROM32(record[28]);
4799 } else if (pll_lim_ver) { /* ver 0x40 */
4800 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4801 uint8_t *record = NULL;
4802 int i;
4803
4804 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4805 limit_match);
4806
4807 for (i = 0; i < entries; i++, entry += recordlen) {
4808 if (ROM32(entry[3]) == limit_match) {
4809 record = &bios->data[ROM16(entry[1])];
4810 break;
4811 }
4812 }
4813
4814 if (!record) {
4815 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4816 "limits table", limit_match);
4817 return -ENOENT;
4818 }
4819
4820 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4821 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4822 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4823 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4824 pll_lim->vco1.min_m = record[8];
4825 pll_lim->vco1.max_m = record[9];
4826 pll_lim->vco1.min_n = record[10];
4827 pll_lim->vco1.max_n = record[11];
4828 pll_lim->min_p = record[12];
4829 pll_lim->max_p = record[13];
4830 /* where did this go to?? */
4831 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4832 pll_lim->refclk = 27000;
4833 else
4834 pll_lim->refclk = 100000;
4835 }
4836
4837 /*
4838 * By now any valid limit table ought to have set a max frequency for
4839 * vco1, so if it's zero it's either a pre limit table bios, or one
4840 * with an empty limit table (seen on nv18)
4841 */
4842 if (!pll_lim->vco1.maxfreq) {
4843 pll_lim->vco1.minfreq = bios->fminvco;
4844 pll_lim->vco1.maxfreq = bios->fmaxvco;
4845 pll_lim->vco1.min_inputfreq = 0;
4846 pll_lim->vco1.max_inputfreq = INT_MAX;
4847 pll_lim->vco1.min_n = 0x1;
4848 pll_lim->vco1.max_n = 0xff;
4849 pll_lim->vco1.min_m = 0x1;
4850 if (crystal_straps == 0) {
4851 /* nv05 does this, nv11 doesn't, nv10 unknown */
4852 if (cv < 0x11)
4853 pll_lim->vco1.min_m = 0x7;
4854 pll_lim->vco1.max_m = 0xd;
4855 } else {
4856 if (cv < 0x11)
4857 pll_lim->vco1.min_m = 0x8;
4858 pll_lim->vco1.max_m = 0xe;
4859 }
4860 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4861 pll_lim->max_log2p = 4;
4862 else
4863 pll_lim->max_log2p = 5;
4864 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4865 }
4866
4867 if (!pll_lim->refclk)
4868 switch (crystal_straps) {
4869 case 0:
4870 pll_lim->refclk = 13500;
4871 break;
4872 case (1 << 6):
4873 pll_lim->refclk = 14318;
4874 break;
4875 case (1 << 22):
4876 pll_lim->refclk = 27000;
4877 break;
4878 case (1 << 22 | 1 << 6):
4879 pll_lim->refclk = 25000;
4880 break;
4881 }
4882
4c389f00
BS		 4883 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4884 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4885 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4886 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4887 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4888 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4889 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4890 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4891 if (pll_lim->vco2.maxfreq) {
4892 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4893 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4894 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4895 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4896 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4897 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4898 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4899 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4900 }
4901 if (!pll_lim->max_p) {
4902 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4903 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4904 } else {
4905 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4906 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4907 }
4908 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 4909
4910 return 0;
4911}
4912
4913static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4914{
4915 /*
4916 * offset + 0 (8 bits): Micro version
4917 * offset + 1 (8 bits): Minor version
4918 * offset + 2 (8 bits): Chip version
4919 * offset + 3 (8 bits): Major version
4920 */
4921
4922 bios->major_version = bios->data[offset + 3];
04a39c57 4923 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4924 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4925 bios->data[offset + 3], bios->data[offset + 2],
4926 bios->data[offset + 1], bios->data[offset]);
4927}
4928
4929static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4930{
4931 /*
4932 * Parses the init table segment for pointers used in script execution.
4933 *
4934 * offset + 0 (16 bits): init script tables pointer
4935 * offset + 2 (16 bits): macro index table pointer
4936 * offset + 4 (16 bits): macro table pointer
4937 * offset + 6 (16 bits): condition table pointer
4938 * offset + 8 (16 bits): io condition table pointer
4939 * offset + 10 (16 bits): io flag condition table pointer
4940 * offset + 12 (16 bits): init function table pointer
4941 */
4942
4943 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4944 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4945 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4946 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4947 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4948 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4949 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4950}
4951
4952static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4953{
4954 /*
4955 * Parses the load detect values for g80 cards.
4956 *
4957 * offset + 0 (16 bits): loadval table pointer
4958 */
4959
4960 uint16_t load_table_ptr;
4961 uint8_t version, headerlen, entrylen, num_entries;
4962
4963 if (bitentry->length != 3) {
4964 NV_ERROR(dev, "Do not understand BIT A table\n");
4965 return -EINVAL;
4966 }
4967
4968 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4969
4970 if (load_table_ptr == 0x0) {
4971 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4972 return -EINVAL;
4973 }
4974
4975 version = bios->data[load_table_ptr];
4976
4977 if (version != 0x10) {
4978 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4979 version >> 4, version & 0xF);
4980 return -ENOSYS;
4981 }
4982
4983 headerlen = bios->data[load_table_ptr + 1];
4984 entrylen = bios->data[load_table_ptr + 2];
4985 num_entries = bios->data[load_table_ptr + 3];
4986
4987 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4988 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4989 return -EINVAL;
4990 }
4991
4992 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 4993 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 4994
4995 return 0;
4996}
4997
4998static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4999{
5000 /*
5001 * offset + 8 (16 bits): PLL limits table pointer
5002 *
5003 * There's more in here, but that's unknown.
5004 */
5005
5006 if (bitentry->length < 10) {
5007 NV_ERROR(dev, "Do not understand BIT C table\n");
5008 return -EINVAL;
5009 }
5010
5011 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5012
5013 return 0;
5014}
5015
5016static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5017{
5018 /*
5019 * Parses the flat panel table segment that the bit entry points to.
5020 * Starting at bitentry->offset:
5021 *
5022 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5023 * records beginning with a freq.
5024 * offset + 2 (16 bits): mode table pointer
5025 */
5026
5027 if (bitentry->length != 4) {
5028 NV_ERROR(dev, "Do not understand BIT display table\n");
5029 return -EINVAL;
5030 }
5031
5032 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5033
5034 return 0;
5035}
5036
5037static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5038{
5039 /*
5040 * Parses the init table segment that the bit entry points to.
5041 *
5042 * See parse_script_table_pointers for layout
5043 */
5044
5045 if (bitentry->length < 14) {
5046 NV_ERROR(dev, "Do not understand init table\n");
5047 return -EINVAL;
5048 }
5049
5050 parse_script_table_pointers(bios, bitentry->offset);
5051
5052 if (bitentry->length >= 16)
5053 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5054 if (bitentry->length >= 18)
5055 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5056
5057 return 0;
5058}
5059
5060static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5061{
5062 /*
5063 * BIT 'i' (info?) table
5064 *
5065 * offset + 0 (32 bits): BIOS version dword (as in B table)
5066 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5067 * offset + 13 (16 bits): pointer to table containing DAC load
5068 * detection comparison values
5069 *
5070 * There's other things in the table, purpose unknown
5071 */
5072
5073 uint16_t daccmpoffset;
5074 uint8_t dacver, dacheaderlen;
5075
5076 if (bitentry->length < 6) {
5077 NV_ERROR(dev, "BIT i table too short for needed information\n");
5078 return -EINVAL;
5079 }
5080
5081 parse_bios_version(dev, bios, bitentry->offset);
5082
5083 /*
5084 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5085 * Quadro identity crisis), other bits possibly as for BMP feature byte
5086 */
5087 bios->feature_byte = bios->data[bitentry->offset + 5];
5088 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5089
5090 if (bitentry->length < 15) {
5091 NV_WARN(dev, "BIT i table not long enough for DAC load "
5092 "detection comparison table\n");
5093 return -EINVAL;
5094 }
5095
5096 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5097
5098 /* doesn't exist on g80 */
5099 if (!daccmpoffset)
5100 return 0;
5101
5102 /*
5103 * The first value in the table, following the header, is the
5104 * comparison value, the second entry is a comparison value for
5105 * TV load detection.
5106 */
5107
5108 dacver = bios->data[daccmpoffset];
5109 dacheaderlen = bios->data[daccmpoffset + 1];
5110
5111 if (dacver != 0x00 && dacver != 0x10) {
5112 NV_WARN(dev, "DAC load detection comparison table version "
5113 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5114 return -ENOSYS;
5115 }
5116
04a39c57
BS		 5117 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5118 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 5119
5120 return 0;
5121}
5122
5123static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5124{
5125 /*
5126 * Parses the LVDS table segment that the bit entry points to.
5127 * Starting at bitentry->offset:
5128 *
5129 * offset + 0 (16 bits): LVDS strap xlate table pointer
5130 */
5131
5132 if (bitentry->length != 2) {
5133 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5134 return -EINVAL;
5135 }
5136
5137 /*
5138 * No idea if it's still called the LVDS manufacturer table, but
5139 * the concept's close enough.
5140 */
5141 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5142
5143 return 0;
5144}
5145
5146static int
5147parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5148 struct bit_entry *bitentry)
5149{
5150 /*
5151 * offset + 2 (8 bits): number of options in an
5152 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5153 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5154 * restrict option selection
5155 *
5156 * There's a bunch of bits in this table other than the RAM restrict
5157 * stuff that we don't use - their use currently unknown
5158 */
5159
6ee73861
BS		 5160 /*
5161 * Older bios versions don't have a sufficiently long table for
5162 * what we want
5163 */
5164 if (bitentry->length < 0x5)
5165 return 0;
5166
5167 if (bitentry->id[1] < 2) {
37383650
MK		 5168 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5169 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 5170 } else {
37383650
MK		 5171 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5172 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 5173 }
5174
6ee73861
BS		 5175 return 0;
5176}
5177
5178static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5179{
5180 /*
5181 * Parses the pointer to the TMDS table
5182 *
5183 * Starting at bitentry->offset:
5184 *
5185 * offset + 0 (16 bits): TMDS table pointer
5186 *
5187 * The TMDS table is typically found just before the DCB table, with a
5188 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5189 * length?)
5190 *
5191 * At offset +7 is a pointer to a script, which I don't know how to
5192 * run yet.
5193 * At offset +9 is a pointer to another script, likewise
5194 * Offset +11 has a pointer to a table where the first word is a pxclk
5195 * frequency and the second word a pointer to a script, which should be
5196 * run if the comparison pxclk frequency is less than the pxclk desired.
5197 * This repeats for decreasing comparison frequencies
5198 * Offset +13 has a pointer to a similar table
5199 * The selection of table (and possibly +7/+9 script) is dictated by
5200 * "or" from the DCB.
5201 */
5202
5203 uint16_t tmdstableptr, script1, script2;
5204
5205 if (bitentry->length != 2) {
5206 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5207 return -EINVAL;
5208 }
5209
5210 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5211
5212 if (tmdstableptr == 0x0) {
5213 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5214 return -EINVAL;
5215 }
5216
5217 /* nv50+ has v2.0, but we don't parse it atm */
5218 if (bios->data[tmdstableptr] != 0x11) {
5219 NV_WARN(dev,
5220 "TMDS table revision %d.%d not currently supported\n",
5221 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5222 return -ENOSYS;
5223 }
5224
5225 /*
5226 * These two scripts are odd: they don't seem to get run even when
5227 * they are not stubbed.
5228 */
5229 script1 = ROM16(bios->data[tmdstableptr + 7]);
5230 script2 = ROM16(bios->data[tmdstableptr + 9]);
5231 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5232 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5233
5234 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5235 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5236
5237 return 0;
5238}
5239
5240static int
5241parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5242 struct bit_entry *bitentry)
5243{
5244 /*
5245 * Parses the pointer to the G80 output script tables
5246 *
5247 * Starting at bitentry->offset:
5248 *
5249 * offset + 0 (16 bits): output script table pointer
5250 */
5251
5252 uint16_t outputscripttableptr;
5253
5254 if (bitentry->length != 3) {
5255 NV_ERROR(dev, "Do not understand BIT U table\n");
5256 return -EINVAL;
5257 }
5258
5259 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5260 bios->display.script_table_ptr = outputscripttableptr;
5261 return 0;
5262}
5263
5264static int
5265parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5266 struct bit_entry *bitentry)
5267{
5268 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
5269 return 0;
5270}
5271
5272struct bit_table {
5273 const char id;
5274 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5275};
5276
5277#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5278
5279static int
5280parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5281 struct bit_table *table)
5282{
5283 struct drm_device *dev = bios->dev;
5284 uint8_t maxentries = bios->data[bitoffset + 4];
5285 int i, offset;
5286 struct bit_entry bitentry;
5287
5288 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
5289 bitentry.id[0] = bios->data[offset];
5290
5291 if (bitentry.id[0] != table->id)
5292 continue;
5293
5294 bitentry.id[1] = bios->data[offset + 1];
5295 bitentry.length = ROM16(bios->data[offset + 2]);
5296 bitentry.offset = ROM16(bios->data[offset + 4]);
5297
5298 return table->parse_fn(dev, bios, &bitentry);
5299 }
5300
5301 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5302 return -ENOSYS;
5303}
5304
5305static int
5306parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5307{
5308 int ret;
5309
5310 /*
5311 * The only restriction on parsing order currently is having 'i' first
5312 * for use of bios->*_version or bios->feature_byte while parsing;
5313 * functions shouldn't be actually *doing* anything apart from pulling
5314 * data from the image into the bios struct, thus no interdependencies
5315 */
5316 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5317 if (ret) /* info? */
5318 return ret;
5319 if (bios->major_version >= 0x60) /* g80+ */
5320 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5321 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5322 if (ret)
5323 return ret;
5324 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5325 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5326 if (ret)
5327 return ret;
5328 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5329 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5330 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5331 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5332 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
5333
5334 return 0;
5335}
5336
5337static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5338{
5339 /*
5340 * Parses the BMP structure for useful things, but does not act on them
5341 *
5342 * offset + 5: BMP major version
5343 * offset + 6: BMP minor version
5344 * offset + 9: BMP feature byte
5345 * offset + 10: BCD encoded BIOS version
5346 *
5347 * offset + 18: init script table pointer (for bios versions < 5.10h)
5348 * offset + 20: extra init script table pointer (for bios
5349 * versions < 5.10h)
5350 *
5351 * offset + 24: memory init table pointer (used on early bios versions)
5352 * offset + 26: SDR memory sequencing setup data table
5353 * offset + 28: DDR memory sequencing setup data table
5354 *
5355 * offset + 54: index of I2C CRTC pair to use for CRT output
5356 * offset + 55: index of I2C CRTC pair to use for TV output
5357 * offset + 56: index of I2C CRTC pair to use for flat panel output
5358 * offset + 58: write CRTC index for I2C pair 0
5359 * offset + 59: read CRTC index for I2C pair 0
5360 * offset + 60: write CRTC index for I2C pair 1
5361 * offset + 61: read CRTC index for I2C pair 1
5362 *
5363 * offset + 67: maximum internal PLL frequency (single stage PLL)
5364 * offset + 71: minimum internal PLL frequency (single stage PLL)
5365 *
5366 * offset + 75: script table pointers, as described in
5367 * parse_script_table_pointers
5368 *
5369 * offset + 89: TMDS single link output A table pointer
5370 * offset + 91: TMDS single link output B table pointer
5371 * offset + 95: LVDS single link output A table pointer
5372 * offset + 105: flat panel timings table pointer
5373 * offset + 107: flat panel strapping translation table pointer
5374 * offset + 117: LVDS manufacturer panel config table pointer
5375 * offset + 119: LVDS manufacturer strapping translation table pointer
5376 *
5377 * offset + 142: PLL limits table pointer
5378 *
5379 * offset + 156: minimum pixel clock for LVDS dual link
5380 */
5381
5382 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5383 uint16_t bmplength;
5384 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5385
5386 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 5387 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5388 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5389 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5390 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 5391 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5392 bios->fmaxvco = 256000;
5393 bios->fminvco = 128000;
5394 bios->fp.duallink_transition_clk = 90000;
5395
5396 bmp_version_major = bmp[5];
5397 bmp_version_minor = bmp[6];
5398
5399 NV_TRACE(dev, "BMP version %d.%d\n",
5400 bmp_version_major, bmp_version_minor);
5401
5402 /*
5403 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5404 * pointer on early versions
5405 */
5406 if (bmp_version_major < 5)
5407 *(uint16_t *)&bios->data[0x36] = 0;
5408
5409 /*
5410 * Seems that the minor version was 1 for all major versions prior
5411 * to 5. Version 6 could theoretically exist, but I suspect BIT
5412 * happened instead.
5413 */
5414 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5415 NV_ERROR(dev, "You have an unsupported BMP version. "
5416 "Please send in your bios\n");
5417 return -ENOSYS;
5418 }
5419
5420 if (bmp_version_major == 0)
5421 /* nothing that's currently useful in this version */
5422 return 0;
5423 else if (bmp_version_major == 1)
5424 bmplength = 44; /* exact for 1.01 */
5425 else if (bmp_version_major == 2)
5426 bmplength = 48; /* exact for 2.01 */
5427 else if (bmp_version_major == 3)
5428 bmplength = 54;
5429 /* guessed - mem init tables added in this version */
5430 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5431 /* don't know if 5.0 exists... */
5432 bmplength = 62;
5433 /* guessed - BMP I2C indices added in version 4*/
5434 else if (bmp_version_minor < 0x6)
5435 bmplength = 67; /* exact for 5.01 */
5436 else if (bmp_version_minor < 0x10)
5437 bmplength = 75; /* exact for 5.06 */
5438 else if (bmp_version_minor == 0x10)
5439 bmplength = 89; /* exact for 5.10h */
5440 else if (bmp_version_minor < 0x14)
5441 bmplength = 118; /* exact for 5.11h */
5442 else if (bmp_version_minor < 0x24)
5443 /*
5444 * Not sure of version where pll limits came in;
5445 * certainly exist by 0x24 though.
5446 */
5447 /* length not exact: this is long enough to get lvds members */
5448 bmplength = 123;
5449 else if (bmp_version_minor < 0x27)
5450 /*
5451 * Length not exact: this is long enough to get pll limit
5452 * member
5453 */
5454 bmplength = 144;
5455 else
5456 /*
5457 * Length not exact: this is long enough to get dual link
5458 * transition clock.
5459 */
5460 bmplength = 158;
5461
5462 /* checksum */
5463 if (nv_cksum(bmp, 8)) {
5464 NV_ERROR(dev, "Bad BMP checksum\n");
5465 return -EINVAL;
5466 }
5467
5468 /*
5469 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5470 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5471 * (not nv10gl), bit 5 that the flat panel tables are present, and
5472 * bit 6 a tv bios.
5473 */
5474 bios->feature_byte = bmp[9];
5475
5476 parse_bios_version(dev, bios, offset + 10);
5477
5478 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5479 bios->old_style_init = true;
5480 legacy_scripts_offset = 18;
5481 if (bmp_version_major < 2)
5482 legacy_scripts_offset -= 4;
5483 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5484 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5485
5486 if (bmp_version_major > 2) { /* appears in BMP 3 */
5487 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5488 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5489 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5490 }
5491
5492 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5493 if (bmplength > 61)
5494 legacy_i2c_offset = offset + 54;
5495 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5496 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5497 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3af76454
FJ		 5498 if (bios->data[legacy_i2c_offset + 4])
5499 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5500 if (bios->data[legacy_i2c_offset + 5])
5501 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5502 if (bios->data[legacy_i2c_offset + 6])
5503 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5504 if (bios->data[legacy_i2c_offset + 7])
5505 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5506
5507 if (bmplength > 74) {
5508 bios->fmaxvco = ROM32(bmp[67]);
5509 bios->fminvco = ROM32(bmp[71]);
5510 }
5511 if (bmplength > 88)
5512 parse_script_table_pointers(bios, offset + 75);
5513 if (bmplength > 94) {
5514 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5515 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5516 /*
5517 * Never observed in use with lvds scripts, but is reused for
5518 * 18/24 bit panel interface default for EDID equipped panels
5519 * (if_is_24bit not set directly to avoid any oscillation).
5520 */
5521 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5522 }
5523 if (bmplength > 108) {
5524 bios->fp.fptablepointer = ROM16(bmp[105]);
5525 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5526 bios->fp.xlatwidth = 1;
5527 }
5528 if (bmplength > 120) {
5529 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5530 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5531 }
5532 if (bmplength > 143)
5533 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5534
5535 if (bmplength > 157)
5536 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5537
5538 return 0;
5539}
5540
5541static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5542{
5543 int i, j;
5544
5545 for (i = 0; i <= (n - len); i++) {
5546 for (j = 0; j < len; j++)
5547 if (data[i + j] != str[j])
5548 break;
5549 if (j == len)
5550 return i;
5551 }
5552
5553 return 0;
5554}
5555
6ee73861
BS		 5556static struct dcb_gpio_entry *
5557new_gpio_entry(struct nvbios *bios)
5558{
7f245b20 5559 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861
BS		 5560
5561 return &gpio->entry[gpio->entries++];
5562}
5563
5564struct dcb_gpio_entry *
5565nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5566{
5567 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5568 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5569 int i;
5570
7f245b20
BS		 5571 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5572 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5573 continue;
5574
7f245b20 5575 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5576 }
5577
5578 return NULL;
5579}
5580
5581static void
5582parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5583{
5584 struct dcb_gpio_entry *gpio;
5585 uint16_t ent = ROM16(bios->data[offset]);
5586 uint8_t line = ent & 0x1f,
5587 tag = ent >> 5 & 0x3f,
5588 flags = ent >> 11 & 0x1f;
5589
5590 if (tag == 0x3f)
5591 return;
5592
5593 gpio = new_gpio_entry(bios);
5594
5595 gpio->tag = tag;
5596 gpio->line = line;
5597 gpio->invert = flags != 4;
2535d71c 5598 gpio->entry = ent;
6ee73861
BS		 5599}
5600
5601static void
5602parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5603{
02faec09 5604 uint32_t entry = ROM32(bios->data[offset]);
6ee73861 5605 struct dcb_gpio_entry *gpio;
6ee73861 5606
02faec09 5607 if ((entry & 0x0000ff00) == 0x0000ff00)
6ee73861
BS		 5608 return;
5609
5610 gpio = new_gpio_entry(bios);
02faec09
BS		 5611 gpio->tag = (entry & 0x0000ff00) >> 8;
5612 gpio->line = (entry & 0x0000001f) >> 0;
5613 gpio->state_default = (entry & 0x01000000) >> 24;
5614 gpio->state[0] = (entry & 0x18000000) >> 27;
5615 gpio->state[1] = (entry & 0x60000000) >> 29;
5616 gpio->entry = entry;
6ee73861
BS		 5617}
5618
5619static void
5620parse_dcb_gpio_table(struct nvbios *bios)
5621{
5622 struct drm_device *dev = bios->dev;
7f245b20 5623 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr;
6ee73861
BS		 5624 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5625 int header_len = gpio_table[1],
5626 entries = gpio_table[2],
5627 entry_len = gpio_table[3];
5628 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5629 int i;
5630
7f245b20 5631 if (bios->dcb.version >= 0x40) {
6ee73861
BS		 5632 if (gpio_table_ptr && entry_len != 4) {
5633 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5634 return;
5635 }
5636
5637 parse_entry = parse_dcb40_gpio_entry;
5638
7f245b20 5639 } else if (bios->dcb.version >= 0x30) {
6ee73861
BS		 5640 if (gpio_table_ptr && entry_len != 2) {
5641 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5642 return;
5643 }
5644
5645 parse_entry = parse_dcb30_gpio_entry;
5646
7f245b20 5647 } else if (bios->dcb.version >= 0x22) {
6ee73861
BS		 5648 /*
5649 * DCBs older than v3.0 don't really have a GPIO
5650 * table, instead they keep some GPIO info at fixed
5651 * locations.
5652 */
5653 uint16_t dcbptr = ROM16(bios->data[0x36]);
5654 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5655
5656 if (tvdac_gpio[0] & 1) {
5657 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5658
5659 gpio->tag = DCB_GPIO_TVDAC0;
5660 gpio->line = tvdac_gpio[1] >> 4;
5661 gpio->invert = tvdac_gpio[0] & 2;
5662 }
5663 }
5664
5665 if (!gpio_table_ptr)
5666 return;
5667
5668 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5669 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5670 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5671 }
5672
5673 for (i = 0; i < entries; i++)
5674 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5675}
5676
5677struct dcb_connector_table_entry *
5678nouveau_bios_connector_entry(struct drm_device *dev, int index)
5679{
5680 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5681 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5682 struct dcb_connector_table_entry *cte;
5683
7f245b20 5684 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5685 return NULL;
5686
7f245b20 5687 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5688 if (cte->type == 0xff)
5689 return NULL;
5690
5691 return cte;
5692}
5693
f66fa771
BS		 5694static enum dcb_connector_type
5695divine_connector_type(struct nvbios *bios, int index)
5696{
5697 struct dcb_table *dcb = &bios->dcb;
5698 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5699 int i;
5700
5701 for (i = 0; i < dcb->entries; i++) {
5702 if (dcb->entry[i].connector == index)
5703 encoders |= (1 << dcb->entry[i].type);
5704 }
5705
5706 if (encoders & (1 << OUTPUT_DP)) {
5707 if (encoders & (1 << OUTPUT_TMDS))
5708 type = DCB_CONNECTOR_DP;
5709 else
5710 type = DCB_CONNECTOR_eDP;
5711 } else
5712 if (encoders & (1 << OUTPUT_TMDS)) {
5713 if (encoders & (1 << OUTPUT_ANALOG))
5714 type = DCB_CONNECTOR_DVI_I;
5715 else
5716 type = DCB_CONNECTOR_DVI_D;
5717 } else
5718 if (encoders & (1 << OUTPUT_ANALOG)) {
5719 type = DCB_CONNECTOR_VGA;
5720 } else
5721 if (encoders & (1 << OUTPUT_LVDS)) {
5722 type = DCB_CONNECTOR_LVDS;
5723 } else
5724 if (encoders & (1 << OUTPUT_TV)) {
5725 type = DCB_CONNECTOR_TV_0;
5726 }
5727
5728 return type;
5729}
5730
53c44c3a
BS		 5731static void
5732apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5733{
5734 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5735 struct drm_device *dev = bios->dev;
5736
5737 /* Gigabyte NX85T */
5738 if ((dev->pdev->device == 0x0421) &&
5739 (dev->pdev->subsystem_vendor == 0x1458) &&
5740 (dev->pdev->subsystem_device == 0x344c)) {
5741 if (cte->type == DCB_CONNECTOR_HDMI_1)
5742 cte->type = DCB_CONNECTOR_DVI_I;
5743 }
5744}
5745
6ee73861
BS		 5746static void
5747parse_dcb_connector_table(struct nvbios *bios)
5748{
5749 struct drm_device *dev = bios->dev;
7f245b20 5750 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5751 struct dcb_connector_table_entry *cte;
7f245b20 5752 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5753 uint8_t *entry;
5754 int i;
5755
7f245b20 5756 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5757 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5758 return;
5759 }
5760
5761 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5762 conntab[0], conntab[1], conntab[2], conntab[3]);
5763 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5764 (conntab[3] != 2 && conntab[3] != 4)) {
5765 NV_ERROR(dev, " Unknown! Please report.\n");
5766 return;
5767 }
5768
5769 ct->entries = conntab[2];
5770
5771 entry = conntab + conntab[1];
5772 cte = &ct->entry[0];
5773 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5774 cte->index = i;
6ee73861
BS		 5775 if (conntab[3] == 2)
5776 cte->entry = ROM16(entry[0]);
5777 else
5778 cte->entry = ROM32(entry[0]);
f66fa771 5779
6ee73861 5780 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 5781 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6ee73861
BS		 5782 switch (cte->entry & 0x00033000) {
5783 case 0x00001000:
5784 cte->gpio_tag = 0x07;
5785 break;
5786 case 0x00002000:
5787 cte->gpio_tag = 0x08;
5788 break;
5789 case 0x00010000:
5790 cte->gpio_tag = 0x51;
5791 break;
5792 case 0x00020000:
5793 cte->gpio_tag = 0x52;
5794 break;
5795 default:
5796 cte->gpio_tag = 0xff;
5797 break;
5798 }
5799
5800 if (cte->type == 0xff)
5801 continue;
5802
53c44c3a
BS		 5803 apply_dcb_connector_quirks(bios, i);
5804
6ee73861
BS		 5805 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5806 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5807
5808 /* check for known types, fallback to guessing the type
5809 * from attached encoders if we hit an unknown.
5810 */
5811 switch (cte->type) {
5812 case DCB_CONNECTOR_VGA:
5813 case DCB_CONNECTOR_TV_0:
5814 case DCB_CONNECTOR_TV_1:
5815 case DCB_CONNECTOR_TV_3:
5816 case DCB_CONNECTOR_DVI_I:
5817 case DCB_CONNECTOR_DVI_D:
5818 case DCB_CONNECTOR_LVDS:
5819 case DCB_CONNECTOR_DP:
5820 case DCB_CONNECTOR_eDP:
5821 case DCB_CONNECTOR_HDMI_0:
5822 case DCB_CONNECTOR_HDMI_1:
5823 break;
5824 default:
5825 cte->type = divine_connector_type(bios, cte->index);
da647d5b 5826 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 5827 break;
5828 }
5829
da647d5b
BS		 5830 if (nouveau_override_conntype) {
5831 int type = divine_connector_type(bios, cte->index);
5832 if (type != cte->type)
5833 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5834 }
5835
6ee73861
BS		 5836 }
5837}
5838
7f245b20 5839static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5840{
5841 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5842
5843 memset(entry, 0, sizeof(struct dcb_entry));
5844 entry->index = dcb->entries++;
5845
5846 return entry;
5847}
5848
7f245b20 5849static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
6ee73861
BS		 5850{
5851 struct dcb_entry *entry = new_dcb_entry(dcb);
5852
5853 entry->type = 0;
5854 entry->i2c_index = i2c;
5855 entry->heads = heads;
5856 entry->location = DCB_LOC_ON_CHIP;
5857 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5858}
5859
7f245b20 5860static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5861{
5862 struct dcb_entry *entry = new_dcb_entry(dcb);
5863
5864 entry->type = 2;
5865 entry->i2c_index = LEGACY_I2C_PANEL;
5866 entry->heads = twoHeads ? 3 : 1;
5867 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5868 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5869 entry->duallink_possible = false; /* SiI164 and co. are single link */
5870
5871#if 0
5872 /*
5873 * For dvi-a either crtc probably works, but my card appears to only
5874 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5875 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5876 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5877 * the monitor picks up the mode res ok and lights up, but no pixel
5878 * data appears, so the board manufacturer probably connected up the
5879 * sync lines, but missed the video traces / components
5880 *
5881 * with this introduction, dvi-a left as an exercise for the reader.
5882 */
5883 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5884#endif
5885}
5886
7f245b20 5887static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5888{
5889 struct dcb_entry *entry = new_dcb_entry(dcb);
5890
5891 entry->type = 1;
5892 entry->i2c_index = LEGACY_I2C_TV;
5893 entry->heads = twoHeads ? 3 : 1;
5894 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5895}
5896
5897static bool
7f245b20 5898parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5899 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5900{
5901 entry->type = conn & 0xf;
5902 entry->i2c_index = (conn >> 4) & 0xf;
5903 entry->heads = (conn >> 8) & 0xf;
7f245b20 5904 if (dcb->version >= 0x40)
6ee73861
BS		 5905 entry->connector = (conn >> 12) & 0xf;
5906 entry->bus = (conn >> 16) & 0xf;
5907 entry->location = (conn >> 20) & 0x3;
5908 entry->or = (conn >> 24) & 0xf;
6ee73861
BS		 5909
5910 switch (entry->type) {
5911 case OUTPUT_ANALOG:
5912 /*
5913 * Although the rest of a CRT conf dword is usually
5914 * zeros, mac biosen have stuff there so we must mask
5915 */
7f245b20 5916 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5917 (conf & 0xffff) * 10 :
5918 (conf & 0xff) * 10000;
5919 break;
5920 case OUTPUT_LVDS:
5921 {
5922 uint32_t mask;
5923 if (conf & 0x1)
5924 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5925 if (dcb->version < 0x22) {
6ee73861
BS		 5926 mask = ~0xd;
5927 /*
5928 * The laptop in bug 14567 lies and claims to not use
5929 * straps when it does, so assume all DCB 2.0 laptops
5930 * use straps, until a broken EDID using one is produced
5931 */
5932 entry->lvdsconf.use_straps_for_mode = true;
5933 /*
5934 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5935 * mean the same thing (probably wrong, but might work)
5936 */
5937 if (conf & 0x4 || conf & 0x8)
5938 entry->lvdsconf.use_power_scripts = true;
5939 } else {
a6ed76d7
BS		 5940 mask = ~0x7;
5941 if (conf & 0x2)
5942 entry->lvdsconf.use_acpi_for_edid = true;
6ee73861
BS		 5943 if (conf & 0x4)
5944 entry->lvdsconf.use_power_scripts = true;
c5875470 5945 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6ee73861
BS		 5946 }
5947 if (conf & mask) {
5948 /*
5949 * Until we even try to use these on G8x, it's
5950 * useless reporting unknown bits. They all are.
5951 */
7f245b20 5952 if (dcb->version >= 0x40)
6ee73861
BS		 5953 break;
5954
5955 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5956 "please report\n");
5957 }
5958 break;
5959 }
5960 case OUTPUT_TV:
5961 {
7f245b20 5962 if (dcb->version >= 0x30)
6ee73861
BS		 5963 entry->tvconf.has_component_output = conf & (0x8 << 4);
5964 else
5965 entry->tvconf.has_component_output = false;
5966
5967 break;
5968 }
5969 case OUTPUT_DP:
5970 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5971 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5972 switch ((conf & 0x0f000000) >> 24) {
5973 case 0xf:
5974 entry->dpconf.link_nr = 4;
5975 break;
5976 case 0x3:
5977 entry->dpconf.link_nr = 2;
5978 break;
5979 default:
5980 entry->dpconf.link_nr = 1;
5981 break;
5982 }
5983 break;
5984 case OUTPUT_TMDS:
4a9f822f
FJ		 5985 if (dcb->version >= 0x22)
5986 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
5987 else if (dcb->version >= 0x30)
5988 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
5989 else if (dcb->version >= 0x40)
5990 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5991
6ee73861
BS		 5992 break;
5993 case 0xe:
5994 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 5995 dcb->entries--;
6ee73861 5996 return false;
e7cc51c5
BS		 5997 default:
5998 break;
6ee73861
BS		 5999 }
6000
23484874
BS		 6001 if (dcb->version < 0x40) {
6002 /* Normal entries consist of a single bit, but dual link has
6003 * the next most significant bit set too
6004 */
6005 entry->duallink_possible =
6006 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6007 } else {
6008 entry->duallink_possible = (entry->sorconf.link == 3);
6009 }
6010
6ee73861
BS		 6011 /* unsure what DCB version introduces this, 3.0? */
6012 if (conf & 0x100000)
6013 entry->i2c_upper_default = true;
6014
6015 return true;
6016}
6017
6018static bool
7f245b20 6019parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6020 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6021{
b0d2de86
BS		 6022 switch (conn & 0x0000000f) {
6023 case 0:
6024 entry->type = OUTPUT_ANALOG;
6025 break;
6026 case 1:
6027 entry->type = OUTPUT_TV;
6028 break;
6029 case 2:
6030 case 3:
6ee73861 6031 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 6032 break;
6033 case 4:
6034 switch ((conn & 0x000000f0) >> 4) {
6035 case 0:
6ee73861 6036 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 6037 break;
6038 case 1:
6039 entry->type = OUTPUT_LVDS;
6040 break;
6041 default:
6042 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
6043 (conn & 0x000000f0) >> 4);
6044 return false;
6045 }
6046 break;
6047 default:
6048 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6049 return false;
6ee73861 6050 }
b0d2de86
BS		 6051
6052 entry->i2c_index = (conn & 0x0003c000) >> 14;
6053 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6054 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6055 entry->location = (conn & 0x01e00000) >> 21;
6056 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 6057 entry->duallink_possible = false;
6058
6059 switch (entry->type) {
6060 case OUTPUT_ANALOG:
6061 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6062 break;
b0d2de86
BS		 6063 case OUTPUT_TV:
6064 entry->tvconf.has_component_output = false;
6ee73861 6065 break;
b0d2de86
BS		 6066 case OUTPUT_LVDS:
6067 if ((conn & 0x00003f00) != 0x10)
6068 entry->lvdsconf.use_straps_for_mode = true;
6069 entry->lvdsconf.use_power_scripts = true;
6070 break;
6071 default:
6ee73861
BS		 6072 break;
6073 }
6074
6075 return true;
6076}
6077
7f245b20 6078static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6079 uint32_t conn, uint32_t conf)
6080{
7f245b20 6081 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 6082 bool ret;
6083
7f245b20
BS		 6084 if (dcb->version >= 0x20)
6085 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 6086 else
7f245b20 6087 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 6088 if (!ret)
6089 return ret;
6090
7f245b20
BS		 6091 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6092 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 6093
6094 return true;
6095}
6096
6097static
7f245b20 6098void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 6099{
6100 /*
6101 * DCB v2.0 lists each output combination separately.
6102 * Here we merge compatible entries to have fewer outputs, with
6103 * more options
6104 */
6105
6106 int i, newentries = 0;
6107
6108 for (i = 0; i < dcb->entries; i++) {
6109 struct dcb_entry *ient = &dcb->entry[i];
6110 int j;
6111
6112 for (j = i + 1; j < dcb->entries; j++) {
6113 struct dcb_entry *jent = &dcb->entry[j];
6114
6115 if (jent->type == 100) /* already merged entry */
6116 continue;
6117
6118 /* merge heads field when all other fields the same */
6119 if (jent->i2c_index == ient->i2c_index &&
6120 jent->type == ient->type &&
6121 jent->location == ient->location &&
6122 jent->or == ient->or) {
6123 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6124 i, j);
6125 ient->heads |= jent->heads;
6126 jent->type = 100; /* dummy value */
6127 }
6128 }
6129 }
6130
6131 /* Compact entries merged into others out of dcb */
6132 for (i = 0; i < dcb->entries; i++) {
6133 if (dcb->entry[i].type == 100)
6134 continue;
6135
6136 if (newentries != i) {
6137 dcb->entry[newentries] = dcb->entry[i];
6138 dcb->entry[newentries].index = newentries;
6139 }
6140 newentries++;
6141 }
6142
6143 dcb->entries = newentries;
6144}
6145
df4cf1b7
BS		 6146static bool
6147apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6148{
6149 /* Dell Precision M6300
6150 * DCB entry 2: 02025312 00000010
6151 * DCB entry 3: 02026312 00000020
6152 *
6153 * Identical, except apparently a different connector on a
6154 * different SOR link. Not a clue how we're supposed to know
6155 * which one is in use if it even shares an i2c line...
6156 *
6157 * Ignore the connector on the second SOR link to prevent
6158 * nasty problems until this is sorted (assuming it's not a
6159 * VBIOS bug).
6160 */
6161 if ((dev->pdev->device == 0x040d) &&
6162 (dev->pdev->subsystem_vendor == 0x1028) &&
6163 (dev->pdev->subsystem_device == 0x019b)) {
6164 if (*conn == 0x02026312 && *conf == 0x00000020)
6165 return false;
6166 }
6167
6168 return true;
6169}
6170
ed42f824
BS		 6171static int
6172parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 6173{
ed42f824 6174 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 6175 struct dcb_table *dcb = &bios->dcb;
ed42f824 6176 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 6177 uint8_t *dcbtable;
6178 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
6179 bool configblock = true;
6180 int recordlength = 8, confofs = 4;
6181 int i;
6182
6ee73861 6183 /* get the offset from 0x36 */
ed42f824
BS		 6184 if (dev_priv->card_type > NV_04) {
6185 dcbptr = ROM16(bios->data[0x36]);
6186 if (dcbptr == 0x0000)
6187 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
6188 }
6ee73861 6189
ed42f824 6190 /* this situation likely means a really old card, pre DCB */
6ee73861 6191 if (dcbptr == 0x0) {
ed42f824 6192 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 6193 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
6194
ed42f824 6195 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 6196 fabricate_tv_output(dcb, twoHeads);
6197
6198 return 0;
6199 }
6200
6201 dcbtable = &bios->data[dcbptr];
6202
6203 /* get DCB version */
7f245b20 6204 dcb->version = dcbtable[0];
6ee73861 6205 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 6206 dcb->version >> 4, dcb->version & 0xf);
6ee73861 6207
7f245b20 6208 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 6209 uint32_t sig;
6210
7f245b20 6211 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 6212 headerlen = dcbtable[1];
6213 entries = dcbtable[2];
6214 recordlength = dcbtable[3];
6215 i2ctabptr = ROM16(dcbtable[4]);
6216 sig = ROM32(dcbtable[6]);
7f245b20
BS		 6217 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
6218 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 6219 } else {
6220 i2ctabptr = ROM16(dcbtable[2]);
6221 sig = ROM32(dcbtable[4]);
6222 headerlen = 8;
6223 }
6224
6225 if (sig != 0x4edcbdcb) {
6226 NV_ERROR(dev, "Bad Display Configuration Block "
6227 "signature (%08X)\n", sig);
6228 return -EINVAL;
6229 }
7f245b20 6230 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 6231 char sig[8] = { 0 };
6232
6233 strncpy(sig, (char *)&dcbtable[-7], 7);
6234 i2ctabptr = ROM16(dcbtable[2]);
6235 recordlength = 10;
6236 confofs = 6;
6237
6238 if (strcmp(sig, "DEV_REC")) {
6239 NV_ERROR(dev, "Bad Display Configuration Block "
6240 "signature (%s)\n", sig);
6241 return -EINVAL;
6242 }
6243 } else {
6244 /*
6245 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6246 * has the same single (crt) entry, even when tv-out present, so
6247 * the conclusion is this version cannot really be used.
6248 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6249 * 5 entries, which are not specific to the card and so no use.
6250 * v1.2 does have an I2C table that read_dcb_i2c_table can
6251 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6252 * pointer, so use the indices parsed in parse_bmp_structure.
6253 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6254 */
6255 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
6256 "adding all possible outputs\n");
6257 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
6258
6259 /*
6260 * Attempt to detect TV before DVI because the test
6261 * for the former is more accurate and it rules the
6262 * latter out.
6263 */
6264 if (nv04_tv_identify(dev,
6265 bios->legacy.i2c_indices.tv) >= 0)
6266 fabricate_tv_output(dcb, twoHeads);
6267
6268 else if (bios->tmds.output0_script_ptr ||
6269 bios->tmds.output1_script_ptr)
6270 fabricate_dvi_i_output(dcb, twoHeads);
6271
6272 return 0;
6273 }
6274
6275 if (!i2ctabptr)
6276 NV_WARN(dev, "No pointer to DCB I2C port table\n");
6277 else {
7f245b20
BS		 6278 dcb->i2c_table = &bios->data[i2ctabptr];
6279 if (dcb->version >= 0x30)
6280 dcb->i2c_default_indices = dcb->i2c_table[4];
4a9f822f
FJ		 6281
6282 /*
6283 * Parse the "management" I2C bus, used for hardware
6284 * monitoring and some external TMDS transmitters.
6285 */
6286 if (dcb->version >= 0x22) {
6287 int idx = (dcb->version >= 0x40 ?
6288 dcb->i2c_default_indices & 0xf :
6289 2);
6290
6291 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6292 idx, &dcb->i2c[idx]);
6293 }
6ee73861
BS		 6294 }
6295
6ee73861
BS		 6296 if (entries > DCB_MAX_NUM_ENTRIES)
6297 entries = DCB_MAX_NUM_ENTRIES;
6298
6299 for (i = 0; i < entries; i++) {
6300 uint32_t connection, config = 0;
6301
6302 connection = ROM32(dcbtable[headerlen + recordlength * i]);
6303 if (configblock)
6304 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
6305
6306 /* seen on an NV11 with DCB v1.5 */
6307 if (connection == 0x00000000)
6308 break;
6309
6310 /* seen on an NV17 with DCB v2.0 */
6311 if (connection == 0xffffffff)
6312 break;
6313
6314 if ((connection & 0x0000000f) == 0x0000000f)
6315 continue;
6316
df4cf1b7
BS		 6317 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config))
6318 continue;
6319
6ee73861
BS		 6320 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
6321 dcb->entries, connection, config);
6322
7f245b20 6323 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 6324 break;
6325 }
6326
6327 /*
6328 * apart for v2.1+ not being known for requiring merging, this
6329 * guarantees dcbent->index is the index of the entry in the rom image
6330 */
7f245b20 6331 if (dcb->version < 0x21)
6ee73861
BS		 6332 merge_like_dcb_entries(dev, dcb);
6333
54abb5dd
BS		 6334 if (!dcb->entries)
6335 return -ENXIO;
6336
6337 parse_dcb_gpio_table(bios);
6338 parse_dcb_connector_table(bios);
6339 return 0;
6ee73861
BS		 6340}
6341
6342static void
6343fixup_legacy_connector(struct nvbios *bios)
6344{
7f245b20 6345 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 6346 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 6347
6348 /*
6349 * DCB 3.0 also has the table in most cases, but there are some cards
6350 * where the table is filled with stub entries, and the DCB entriy
6351 * indices are all 0. We don't need the connector indices on pre-G80
6352 * chips (yet?) so limit the use to DCB 4.0 and above.
6353 */
7f245b20 6354 if (dcb->version >= 0x40)
6ee73861
BS		 6355 return;
6356
dc5bc4ed
BS		 6357 dcb->connector.entries = 0;
6358
6ee73861
BS		 6359 /*
6360 * No known connector info before v3.0, so make it up. the rule here
6361 * is: anything on the same i2c bus is considered to be on the same
6362 * connector. any output without an associated i2c bus is assigned
6363 * its own unique connector index.
6364 */
6365 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 6366 /*
6367 * Ignore the I2C index for on-chip TV-out, as there
6368 * are cards with bogus values (nv31m in bug 23212),
6369 * and it's otherwise useless.
6370 */
6371 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 6372 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 6373 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 6374 i2c = dcb->entry[i].i2c_index;
6375
6376 if (i2c_conn[i2c]) {
6377 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 6378 continue;
6379 }
6380
dc5bc4ed
BS		 6381 dcb->entry[i].connector = dcb->connector.entries++;
6382 if (i2c != 0xf)
6383 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 6384 }
6385
dc5bc4ed
BS		 6386 /* Fake the connector table as well as just connector indices */
6387 for (i = 0; i < dcb->connector.entries; i++) {
6388 dcb->connector.entry[i].index = i;
6389 dcb->connector.entry[i].type = divine_connector_type(bios, i);
6390 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 6391 }
6392}
6393
6394static void
6395fixup_legacy_i2c(struct nvbios *bios)
6396{
7f245b20 6397 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 6398 int i;
6399
6400 for (i = 0; i < dcb->entries; i++) {
6401 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
6402 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
6403 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
6404 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
6405 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
6406 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
6407 }
6408}
6409
6410static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6411{
6412 /*
6413 * The header following the "HWSQ" signature has the number of entries,
6414 * and the entry size
6415 *
6416 * An entry consists of a dword to write to the sequencer control reg
6417 * (0x00001304), followed by the ucode bytes, written sequentially,
6418 * starting at reg 0x00001400
6419 */
6420
6421 uint8_t bytes_to_write;
6422 uint16_t hwsq_entry_offset;
6423 int i;
6424
6425 if (bios->data[hwsq_offset] <= entry) {
6426 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6427 "requested entry\n");
6428 return -ENOENT;
6429 }
6430
6431 bytes_to_write = bios->data[hwsq_offset + 1];
6432
6433 if (bytes_to_write != 36) {
6434 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6435 return -EINVAL;
6436 }
6437
6438 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6439
6440 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6441
6442 /* set sequencer control */
6443 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6444 bytes_to_write -= 4;
6445
6446 /* write ucode */
6447 for (i = 0; i < bytes_to_write; i += 4)
6448 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6449
6450 /* twiddle NV_PBUS_DEBUG_4 */
6451 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6452
6453 return 0;
6454}
6455
6456static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6457 struct nvbios *bios)
6458{
6459 /*
6460 * BMP based cards, from NV17, need a microcode loading to correctly
6461 * control the GPIO etc for LVDS panels
6462 *
6463 * BIT based cards seem to do this directly in the init scripts
6464 *
6465 * The microcode entries are found by the "HWSQ" signature.
6466 */
6467
6468 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6469 const int sz = sizeof(hwsq_signature);
6470 int hwsq_offset;
6471
6472 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6473 if (!hwsq_offset)
6474 return 0;
6475
6476 /* always use entry 0? */
6477 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6478}
6479
6480uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6481{
6482 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6483 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6484 const uint8_t edid_sig[] = {
6485 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6486 uint16_t offset = 0;
6487 uint16_t newoffset;
6488 int searchlen = NV_PROM_SIZE;
6489
6490 if (bios->fp.edid)
6491 return bios->fp.edid;
6492
6493 while (searchlen) {
6494 newoffset = findstr(&bios->data[offset], searchlen,
6495 edid_sig, 8);
6496 if (!newoffset)
6497 return NULL;
6498 offset += newoffset;
6499 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6500 break;
6501
6502 searchlen -= offset;
6503 offset++;
6504 }
6505
6506 NV_TRACE(dev, "Found EDID in BIOS\n");
6507
6508 return bios->fp.edid = &bios->data[offset];
6509}
6510
6511void
6512nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6513 struct dcb_entry *dcbent)
6514{
6515 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6516 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6517 struct init_exec iexec = { true, false };
6518
d9184fa9 6519 mutex_lock(&bios->lock);
6ee73861
BS		 6520 bios->display.output = dcbent;
6521 parse_init_table(bios, table, &iexec);
6522 bios->display.output = NULL;
d9184fa9 6523 mutex_unlock(&bios->lock);
6ee73861
BS		 6524}
6525
6526static bool NVInitVBIOS(struct drm_device *dev)
6527{
6528 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6529 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6530
6531 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 6532 mutex_init(&bios->lock);
6ee73861
BS		 6533 bios->dev = dev;
6534
6535 if (!NVShadowVBIOS(dev, bios->data))
6536 return false;
6537
6538 bios->length = NV_PROM_SIZE;
6539 return true;
6540}
6541
6542static int nouveau_parse_vbios_struct(struct drm_device *dev)
6543{
6544 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6545 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6546 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6547 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6548 int offset;
6549
6550 offset = findstr(bios->data, bios->length,
6551 bit_signature, sizeof(bit_signature));
6552 if (offset) {
6553 NV_TRACE(dev, "BIT BIOS found\n");
6554 return parse_bit_structure(bios, offset + 6);
6555 }
6556
6557 offset = findstr(bios->data, bios->length,
6558 bmp_signature, sizeof(bmp_signature));
6559 if (offset) {
6560 NV_TRACE(dev, "BMP BIOS found\n");
6561 return parse_bmp_structure(dev, bios, offset);
6562 }
6563
6564 NV_ERROR(dev, "No known BIOS signature found\n");
6565 return -ENODEV;
6566}
6567
6568int
6569nouveau_run_vbios_init(struct drm_device *dev)
6570{
6571 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6572 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6573 int i, ret = 0;
6574
946fd35f
FJ		 6575 /* Reset the BIOS head to 0. */
6576 bios->state.crtchead = 0;
6ee73861
BS		 6577
6578 if (bios->major_version < 5) /* BMP only */
6579 load_nv17_hw_sequencer_ucode(dev, bios);
6580
6581 if (bios->execute) {
6582 bios->fp.last_script_invoc = 0;
6583 bios->fp.lvds_init_run = false;
6584 }
6585
6586 parse_init_tables(bios);
6587
6588 /*
6589 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6590 * parser will run this right after the init tables, the binary
6591 * driver appears to run it at some point later.
6592 */
6593 if (bios->some_script_ptr) {
6594 struct init_exec iexec = {true, false};
6595
6596 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6597 bios->some_script_ptr);
6598 parse_init_table(bios, bios->some_script_ptr, &iexec);
6599 }
6600
6601 if (dev_priv->card_type >= NV_50) {
7f245b20 6602 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6603 nouveau_bios_run_display_table(dev,
7f245b20 6604 &bios->dcb.entry[i],
6ee73861
BS		 6605 0, 0);
6606 }
6607 }
6608
6ee73861
BS		 6609 return ret;
6610}
6611
6612static void
6613nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6614{
6615 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6616 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6617 struct dcb_i2c_entry *entry;
6618 int i;
6619
7f245b20 6620 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6621 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6622 nouveau_i2c_fini(dev, entry);
6623}
6624
d13102c6
BS		 6625static bool
6626nouveau_bios_posted(struct drm_device *dev)
6627{
6628 struct drm_nouveau_private *dev_priv = dev->dev_private;
d13102c6
BS		 6629 unsigned htotal;
6630
6631 if (dev_priv->chipset >= NV_50) {
6632 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6633 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6634 return false;
6635 return true;
6636 }
6637
d13102c6
BS		 6638 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6639 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6640 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6641 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6642 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
03cd06ca 6643
d13102c6
BS		 6644 return (htotal != 0);
6645}
6646
6ee73861
BS		 6647int
6648nouveau_bios_init(struct drm_device *dev)
6649{
6650 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6651 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6652 int ret;
6653
6ee73861
BS		 6654 if (!NVInitVBIOS(dev))
6655 return -ENODEV;
6656
6657 ret = nouveau_parse_vbios_struct(dev);
6658 if (ret)
6659 return ret;
6660
6661 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6662 if (ret)
6663 return ret;
6664
6665 fixup_legacy_i2c(bios);
6666 fixup_legacy_connector(bios);
6667
6668 if (!bios->major_version) /* we don't run version 0 bios */
6669 return 0;
6670
6ee73861
BS		 6671 /* init script execution disabled */
6672 bios->execute = false;
6673
6674 /* ... unless card isn't POSTed already */
d13102c6 6675 if (!nouveau_bios_posted(dev)) {
67eda20e
FJ		 6676 NV_INFO(dev, "Adaptor not initialised, "
6677 "running VBIOS init tables.\n");
6ee73861
BS		 6678 bios->execute = true;
6679 }
6680
6ee73861 6681 ret = nouveau_run_vbios_init(dev);
04a39c57 6682 if (ret)
6ee73861 6683 return ret;
6ee73861
BS		 6684
6685 /* feature_byte on BMP is poor, but init always sets CR4B */
6ee73861
BS		 6686 if (bios->major_version < 5)
6687 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6688
6689 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6690 if (bios->is_mobile || bios->major_version >= 5)
6691 ret = parse_fp_mode_table(dev, bios);
6ee73861
BS		 6692
6693 /* allow subsequent scripts to execute */
6694 bios->execute = true;
6695
6696 return 0;
6697}
6698
6699void
6700nouveau_bios_takedown(struct drm_device *dev)
6701{
6702 nouveau_bios_i2c_devices_takedown(dev);
6703}
Clone of davem's net-next-2.6 tree