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drm/nv50: store full dcb i2c entry from vbios
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861
BS		 30
31/* these defines are made up */
32#define NV_CIO_CRE_44_HEADA 0x0
33#define NV_CIO_CRE_44_HEADB 0x3
34#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
35#define LEGACY_I2C_CRT 0x80
36#define LEGACY_I2C_PANEL 0x81
37#define LEGACY_I2C_TV 0x82
38
39#define EDID1_LEN 128
40
41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42#define LOG_OLD_VALUE(x)
43
44#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
45#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
46
47struct init_exec {
48 bool execute;
49 bool repeat;
50};
51
52static bool nv_cksum(const uint8_t *data, unsigned int length)
53{
54 /*
55 * There's a few checksums in the BIOS, so here's a generic checking
56 * function.
57 */
58 int i;
59 uint8_t sum = 0;
60
61 for (i = 0; i < length; i++)
62 sum += data[i];
63
64 if (sum)
65 return true;
66
67 return false;
68}
69
70static int
71score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
72{
73 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
74 NV_TRACEWARN(dev, "... BIOS signature not found\n");
75 return 0;
76 }
77
78 if (nv_cksum(data, data[2] * 512)) {
79 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
80 /* if a ro image is somewhat bad, it's probably all rubbish */
81 return writeable ? 2 : 1;
82 } else
83 NV_TRACE(dev, "... appears to be valid\n");
84
85 return 3;
86}
87
88static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
89{
90 struct drm_nouveau_private *dev_priv = dev->dev_private;
91 uint32_t pci_nv_20, save_pci_nv_20;
92 int pcir_ptr;
93 int i;
94
95 if (dev_priv->card_type >= NV_50)
96 pci_nv_20 = 0x88050;
97 else
98 pci_nv_20 = NV_PBUS_PCI_NV_20;
99
100 /* enable ROM access */
101 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
102 nvWriteMC(dev, pci_nv_20,
103 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
104
105 /* bail if no rom signature */
106 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
107 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
108 goto out;
109
110 /* additional check (see note below) - read PCI record header */
111 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
112 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
113 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
117 goto out;
118
119 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
120 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
121 * each byte. we'll hope pramin has something usable instead
122 */
123 for (i = 0; i < NV_PROM_SIZE; i++)
124 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
125
126out:
127 /* disable ROM access */
128 nvWriteMC(dev, pci_nv_20,
129 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
130}
131
132static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
133{
134 struct drm_nouveau_private *dev_priv = dev->dev_private;
135 uint32_t old_bar0_pramin = 0;
136 int i;
137
138 if (dev_priv->card_type >= NV_50) {
139 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
140
141 if (!vbios_vram)
142 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
143
144 old_bar0_pramin = nv_rd32(dev, 0x1700);
145 nv_wr32(dev, 0x1700, vbios_vram >> 16);
146 }
147
148 /* bail if no rom signature */
149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
151 goto out;
152
153 for (i = 0; i < NV_PROM_SIZE; i++)
154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
155
156out:
157 if (dev_priv->card_type >= NV_50)
158 nv_wr32(dev, 0x1700, old_bar0_pramin);
159}
160
161static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
162{
163 void __iomem *rom = NULL;
164 size_t rom_len;
165 int ret;
166
167 ret = pci_enable_rom(dev->pdev);
168 if (ret)
169 return;
170
171 rom = pci_map_rom(dev->pdev, &rom_len);
172 if (!rom)
173 goto out;
174 memcpy_fromio(data, rom, rom_len);
175 pci_unmap_rom(dev->pdev, rom);
176
177out:
178 pci_disable_rom(dev->pdev);
179}
180
181struct methods {
182 const char desc[8];
183 void (*loadbios)(struct drm_device *, uint8_t *);
184 const bool rw;
6ee73861
BS		 185};
186
187static struct methods nv04_methods[] = {
188 { "PROM", load_vbios_prom, false },
189 { "PRAMIN", load_vbios_pramin, true },
190 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 191};
192
193static struct methods nv50_methods[] = {
194 { "PRAMIN", load_vbios_pramin, true },
195 { "PROM", load_vbios_prom, false },
196 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 197};
198
657b6245
MK		 199#define METHODCNT 3
200
6ee73861
BS		 201static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
202{
203 struct drm_nouveau_private *dev_priv = dev->dev_private;
657b6245
MK		 204 struct methods *methods;
205 int i;
6ee73861 206 int testscore = 3;
657b6245 207 int scores[METHODCNT];
6ee73861
BS		 208
209 if (nouveau_vbios) {
657b6245
MK		 210 methods = nv04_methods;
211 for (i = 0; i < METHODCNT; i++)
212 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 213 break;
6ee73861 214
657b6245 215 if (i < METHODCNT) {
6ee73861 216 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 217 methods[i].desc);
6ee73861 218
657b6245
MK		 219 methods[i].loadbios(dev, data);
220 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 221 return true;
222 }
223
224 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
225 }
226
227 if (dev_priv->card_type < NV_50)
228 methods = nv04_methods;
229 else
230 methods = nv50_methods;
231
657b6245 232 for (i = 0; i < METHODCNT; i++) {
6ee73861 233 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 234 methods[i].desc);
6ee73861 235 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 236 methods[i].loadbios(dev, data);
237 scores[i] = score_vbios(dev, data, methods[i].rw);
238 if (scores[i] == testscore)
6ee73861 239 return true;
6ee73861
BS		 240 }
241
242 while (--testscore > 0) {
657b6245
MK		 243 for (i = 0; i < METHODCNT; i++) {
244 if (scores[i] == testscore) {
6ee73861 245 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 246 methods[i].desc);
247 methods[i].loadbios(dev, data);
6ee73861
BS		 248 return true;
249 }
6ee73861
BS		 250 }
251 }
252
253 NV_ERROR(dev, "No valid BIOS image found\n");
254 return false;
255}
256
257struct init_tbl_entry {
258 char *name;
259 uint8_t id;
37383650 260 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 261};
262
263struct bit_entry {
264 uint8_t id[2];
265 uint16_t length;
266 uint16_t offset;
267};
268
269static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
270
271#define MACRO_INDEX_SIZE 2
272#define MACRO_SIZE 8
273#define CONDITION_SIZE 12
274#define IO_FLAG_CONDITION_SIZE 9
275#define IO_CONDITION_SIZE 5
276#define MEM_INIT_SIZE 66
277
278static void still_alive(void)
279{
280#if 0
281 sync();
282 msleep(2);
283#endif
284}
285
286static uint32_t
287munge_reg(struct nvbios *bios, uint32_t reg)
288{
289 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
290 struct dcb_entry *dcbent = bios->display.output;
291
292 if (dev_priv->card_type < NV_50)
293 return reg;
294
295 if (reg & 0x40000000) {
296 BUG_ON(!dcbent);
297
298 reg += (ffs(dcbent->or) - 1) * 0x800;
299 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
300 reg += 0x00000080;
301 }
302
303 reg &= ~0x60000000;
304 return reg;
305}
306
307static int
308valid_reg(struct nvbios *bios, uint32_t reg)
309{
310 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
311 struct drm_device *dev = bios->dev;
312
313 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 314 if (reg & 0x2 ||
04a39c57 315 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 316 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
317
318 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 319 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 320 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
321 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
322 reg);
323
9855e584
BS		 324 if (reg >= (8*1024*1024)) {
325 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
326 return 0;
6ee73861 327 }
9855e584
BS		 328
329 return 1;
6ee73861
BS		 330}
331
332static bool
333valid_idx_port(struct nvbios *bios, uint16_t port)
334{
335 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
336 struct drm_device *dev = bios->dev;
337
338 /*
339 * If adding more ports here, the read/write functions below will need
340 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
341 * used for the port in question
342 */
343 if (dev_priv->card_type < NV_50) {
344 if (port == NV_CIO_CRX__COLOR)
345 return true;
346 if (port == NV_VIO_SRX)
347 return true;
348 } else {
349 if (port == NV_CIO_CRX__COLOR)
350 return true;
351 }
352
353 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
354 port);
355
356 return false;
357}
358
359static bool
360valid_port(struct nvbios *bios, uint16_t port)
361{
362 struct drm_device *dev = bios->dev;
363
364 /*
365 * If adding more ports here, the read/write functions below will need
366 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
367 * used for the port in question
368 */
369 if (port == NV_VIO_VSE2)
370 return true;
371
372 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
373
374 return false;
375}
376
377static uint32_t
378bios_rd32(struct nvbios *bios, uint32_t reg)
379{
380 uint32_t data;
381
382 reg = munge_reg(bios, reg);
383 if (!valid_reg(bios, reg))
384 return 0;
385
386 /*
387 * C51 sometimes uses regs with bit0 set in the address. For these
388 * cases there should exist a translation in a BIOS table to an IO
389 * port address which the BIOS uses for accessing the reg
390 *
391 * These only seem to appear for the power control regs to a flat panel,
392 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
393 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
394 * suspend-resume mmio trace from a C51 will be required to see if this
395 * is true for the power microcode in 0x14.., or whether the direct IO
396 * port access method is needed
397 */
398 if (reg & 0x1)
399 reg &= ~0x1;
400
401 data = nv_rd32(bios->dev, reg);
402
403 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
404
405 return data;
406}
407
408static void
409bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
410{
411 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
412
413 reg = munge_reg(bios, reg);
414 if (!valid_reg(bios, reg))
415 return;
416
417 /* see note in bios_rd32 */
418 if (reg & 0x1)
419 reg &= 0xfffffffe;
420
421 LOG_OLD_VALUE(bios_rd32(bios, reg));
422 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
423
04a39c57 424 if (dev_priv->vbios.execute) {
6ee73861
BS		 425 still_alive();
426 nv_wr32(bios->dev, reg, data);
427 }
428}
429
430static uint8_t
431bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
432{
433 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
434 struct drm_device *dev = bios->dev;
435 uint8_t data;
436
437 if (!valid_idx_port(bios, port))
438 return 0;
439
440 if (dev_priv->card_type < NV_50) {
441 if (port == NV_VIO_SRX)
442 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
443 else /* assume NV_CIO_CRX__COLOR */
444 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
445 } else {
446 uint32_t data32;
447
448 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
449 data = (data32 >> ((index & 3) << 3)) & 0xff;
450 }
451
452 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
453 "Head: 0x%02X, Data: 0x%02X\n",
454 port, index, bios->state.crtchead, data);
455 return data;
456}
457
458static void
459bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
460{
461 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
462 struct drm_device *dev = bios->dev;
463
464 if (!valid_idx_port(bios, port))
465 return;
466
467 /*
468 * The current head is maintained in the nvbios member state.crtchead.
469 * We trap changes to CR44 and update the head variable and hence the
470 * register set written.
471 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
472 * of the write, and to head1 after the write
473 */
474 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
475 data != NV_CIO_CRE_44_HEADB)
476 bios->state.crtchead = 0;
477
478 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
479 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
480 "Head: 0x%02X, Data: 0x%02X\n",
481 port, index, bios->state.crtchead, data);
482
483 if (bios->execute && dev_priv->card_type < NV_50) {
484 still_alive();
485 if (port == NV_VIO_SRX)
486 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
487 else /* assume NV_CIO_CRX__COLOR */
488 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
489 } else
490 if (bios->execute) {
491 uint32_t data32, shift = (index & 3) << 3;
492
493 still_alive();
494
495 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
496 data32 &= ~(0xff << shift);
497 data32 |= (data << shift);
498 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
499 }
500
501 if (port == NV_CIO_CRX__COLOR &&
502 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
503 bios->state.crtchead = 1;
504}
505
506static uint8_t
507bios_port_rd(struct nvbios *bios, uint16_t port)
508{
509 uint8_t data, head = bios->state.crtchead;
510
511 if (!valid_port(bios, port))
512 return 0;
513
514 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
515
516 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
517 port, head, data);
518
519 return data;
520}
521
522static void
523bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
524{
525 int head = bios->state.crtchead;
526
527 if (!valid_port(bios, port))
528 return;
529
530 LOG_OLD_VALUE(bios_port_rd(bios, port));
531 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
532 port, head, data);
533
534 if (!bios->execute)
535 return;
536
537 still_alive();
538 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
539}
540
541static bool
542io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
543{
544 /*
545 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
546 * for the CRTC index; 1 byte for the mask to apply to the value
547 * retrieved from the CRTC; 1 byte for the shift right to apply to the
548 * masked CRTC value; 2 bytes for the offset to the flag array, to
549 * which the shifted value is added; 1 byte for the mask applied to the
550 * value read from the flag array; and 1 byte for the value to compare
551 * against the masked byte from the flag table.
552 */
553
554 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
555 uint16_t crtcport = ROM16(bios->data[condptr]);
556 uint8_t crtcindex = bios->data[condptr + 2];
557 uint8_t mask = bios->data[condptr + 3];
558 uint8_t shift = bios->data[condptr + 4];
559 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
560 uint8_t flagarraymask = bios->data[condptr + 7];
561 uint8_t cmpval = bios->data[condptr + 8];
562 uint8_t data;
563
564 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
565 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
566 "Cmpval: 0x%02X\n",
567 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
568
569 data = bios_idxprt_rd(bios, crtcport, crtcindex);
570
571 data = bios->data[flagarray + ((data & mask) >> shift)];
572 data &= flagarraymask;
573
574 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
575 offset, data, cmpval);
576
577 return (data == cmpval);
578}
579
580static bool
581bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
582{
583 /*
584 * The condition table entry has 4 bytes for the address of the
585 * register to check, 4 bytes for a mask to apply to the register and
586 * 4 for a test comparison value
587 */
588
589 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
590 uint32_t reg = ROM32(bios->data[condptr]);
591 uint32_t mask = ROM32(bios->data[condptr + 4]);
592 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
593 uint32_t data;
594
595 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
596 offset, cond, reg, mask);
597
598 data = bios_rd32(bios, reg) & mask;
599
600 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
601 offset, data, cmpval);
602
603 return (data == cmpval);
604}
605
606static bool
607io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
608{
609 /*
610 * The IO condition entry has 2 bytes for the IO port address; 1 byte
611 * for the index to write to io_port; 1 byte for the mask to apply to
612 * the byte read from io_port+1; and 1 byte for the value to compare
613 * against the masked byte.
614 */
615
616 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
617 uint16_t io_port = ROM16(bios->data[condptr]);
618 uint8_t port_index = bios->data[condptr + 2];
619 uint8_t mask = bios->data[condptr + 3];
620 uint8_t cmpval = bios->data[condptr + 4];
621
622 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
623
624 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
625 offset, data, cmpval);
626
627 return (data == cmpval);
628}
629
630static int
631nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
632{
633 struct drm_nouveau_private *dev_priv = dev->dev_private;
634 uint32_t reg0 = nv_rd32(dev, reg + 0);
635 uint32_t reg1 = nv_rd32(dev, reg + 4);
636 struct nouveau_pll_vals pll;
637 struct pll_lims pll_limits;
638 int ret;
639
640 ret = get_pll_limits(dev, reg, &pll_limits);
641 if (ret)
642 return ret;
643
644 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
645 if (!clk)
646 return -ERANGE;
647
648 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
649 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
650
04a39c57 651 if (dev_priv->vbios.execute) {
6ee73861
BS		 652 still_alive();
653 nv_wr32(dev, reg + 4, reg1);
654 nv_wr32(dev, reg + 0, reg0);
655 }
656
657 return 0;
658}
659
660static int
661setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
662{
663 struct drm_device *dev = bios->dev;
664 struct drm_nouveau_private *dev_priv = dev->dev_private;
665 /* clk in kHz */
666 struct pll_lims pll_lim;
667 struct nouveau_pll_vals pllvals;
668 int ret;
669
670 if (dev_priv->card_type >= NV_50)
671 return nv50_pll_set(dev, reg, clk);
672
673 /* high regs (such as in the mac g5 table) are not -= 4 */
674 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
675 if (ret)
676 return ret;
677
678 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
679 if (!clk)
680 return -ERANGE;
681
682 if (bios->execute) {
683 still_alive();
684 nouveau_hw_setpll(dev, reg, &pllvals);
685 }
686
687 return 0;
688}
689
690static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
691{
692 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 693 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 694
695 /*
696 * For the results of this function to be correct, CR44 must have been
697 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
698 * and the DCB table parsed, before the script calling the function is
699 * run. run_digital_op_script is example of how to do such setup
700 */
701
702 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
703
7f245b20 704 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 705 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
706 "(%02X)\n", dcb_entry);
707 dcb_entry = 0x7f; /* unused / invalid marker */
708 }
709
710 return dcb_entry;
711}
712
713static struct nouveau_i2c_chan *
714init_i2c_device_find(struct drm_device *dev, int i2c_index)
715{
716 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 717 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 718
719 if (i2c_index == 0xff) {
720 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
721 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 722 int default_indices = dcb->i2c_default_indices;
6ee73861 723
7f245b20 724 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 725 shift = 4;
726
727 i2c_index = (default_indices >> shift) & 0xf;
728 }
729 if (i2c_index == 0x80) /* g80+ */
7f245b20 730 i2c_index = dcb->i2c_default_indices & 0xf;
6ee73861
BS		 731
732 return nouveau_i2c_find(dev, i2c_index);
733}
734
7f245b20
BS		 735static uint32_t
736get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 737{
738 /*
739 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
740 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
741 * CR58 for CR57 = 0 to index a table of offsets to the basic
742 * 0x6808b0 address.
743 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
744 * CR58 for CR57 = 0 to index a table of offsets to the basic
745 * 0x6808b0 address, and then flip the offset by 8.
746 */
747
748 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 749 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 750 const int pramdac_offset[13] = {
751 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
752 const uint32_t pramdac_table[4] = {
753 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
754
755 if (mlv >= 0x80) {
756 int dcb_entry, dacoffset;
757
758 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
759 dcb_entry = dcb_entry_idx_from_crtchead(dev);
760 if (dcb_entry == 0x7f)
761 return 0;
7f245b20 762 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 763 if (mlv == 0x81)
764 dacoffset ^= 8;
765 return 0x6808b0 + dacoffset;
766 } else {
df31ef4d 767 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 768 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
769 mlv);
770 return 0;
771 }
772 return pramdac_table[mlv];
773 }
774}
775
37383650 776static int
6ee73861
BS		 777init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
778 struct init_exec *iexec)
779{
780 /*
781 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
782 *
783 * offset (8 bit): opcode
784 * offset + 1 (16 bit): CRTC port
785 * offset + 3 (8 bit): CRTC index
786 * offset + 4 (8 bit): mask
787 * offset + 5 (8 bit): shift
788 * offset + 6 (8 bit): count
789 * offset + 7 (32 bit): register
790 * offset + 11 (32 bit): configuration 1
791 * ...
792 *
793 * Starting at offset + 11 there are "count" 32 bit values.
794 * To find out which value to use read index "CRTC index" on "CRTC
795 * port", AND this value with "mask" and then bit shift right "shift"
796 * bits. Read the appropriate value using this index and write to
797 * "register"
798 */
799
800 uint16_t crtcport = ROM16(bios->data[offset + 1]);
801 uint8_t crtcindex = bios->data[offset + 3];
802 uint8_t mask = bios->data[offset + 4];
803 uint8_t shift = bios->data[offset + 5];
804 uint8_t count = bios->data[offset + 6];
805 uint32_t reg = ROM32(bios->data[offset + 7]);
806 uint8_t config;
807 uint32_t configval;
37383650 808 int len = 11 + count * 4;
6ee73861
BS		 809
810 if (!iexec->execute)
37383650 811 return len;
6ee73861
BS		 812
813 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
814 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
815 offset, crtcport, crtcindex, mask, shift, count, reg);
816
817 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
818 if (config > count) {
819 NV_ERROR(bios->dev,
820 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
821 offset, config, count);
37383650 822 return 0;
6ee73861
BS		 823 }
824
825 configval = ROM32(bios->data[offset + 11 + config * 4]);
826
827 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
828
829 bios_wr32(bios, reg, configval);
830
37383650 831 return len;
6ee73861
BS		 832}
833
37383650 834static int
6ee73861
BS		 835init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
836{
837 /*
838 * INIT_REPEAT opcode: 0x33 ('3')
839 *
840 * offset (8 bit): opcode
841 * offset + 1 (8 bit): count
842 *
843 * Execute script following this opcode up to INIT_REPEAT_END
844 * "count" times
845 */
846
847 uint8_t count = bios->data[offset + 1];
848 uint8_t i;
849
850 /* no iexec->execute check by design */
851
852 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
853 offset, count);
854
855 iexec->repeat = true;
856
857 /*
858 * count - 1, as the script block will execute once when we leave this
859 * opcode -- this is compatible with bios behaviour as:
860 * a) the block is always executed at least once, even if count == 0
861 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
862 * while we don't
863 */
864 for (i = 0; i < count - 1; i++)
865 parse_init_table(bios, offset + 2, iexec);
866
867 iexec->repeat = false;
868
37383650 869 return 2;
6ee73861
BS		 870}
871
37383650 872static int
6ee73861
BS		 873init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
874 struct init_exec *iexec)
875{
876 /*
877 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
878 *
879 * offset (8 bit): opcode
880 * offset + 1 (16 bit): CRTC port
881 * offset + 3 (8 bit): CRTC index
882 * offset + 4 (8 bit): mask
883 * offset + 5 (8 bit): shift
884 * offset + 6 (8 bit): IO flag condition index
885 * offset + 7 (8 bit): count
886 * offset + 8 (32 bit): register
887 * offset + 12 (16 bit): frequency 1
888 * ...
889 *
890 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
891 * Set PLL register "register" to coefficients for frequency n,
892 * selected by reading index "CRTC index" of "CRTC port" ANDed with
893 * "mask" and shifted right by "shift".
894 *
895 * If "IO flag condition index" > 0, and condition met, double
896 * frequency before setting it.
897 */
898
899 uint16_t crtcport = ROM16(bios->data[offset + 1]);
900 uint8_t crtcindex = bios->data[offset + 3];
901 uint8_t mask = bios->data[offset + 4];
902 uint8_t shift = bios->data[offset + 5];
903 int8_t io_flag_condition_idx = bios->data[offset + 6];
904 uint8_t count = bios->data[offset + 7];
905 uint32_t reg = ROM32(bios->data[offset + 8]);
906 uint8_t config;
907 uint16_t freq;
37383650 908 int len = 12 + count * 2;
6ee73861
BS		 909
910 if (!iexec->execute)
37383650 911 return len;
6ee73861
BS		 912
913 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
914 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
915 "Count: 0x%02X, Reg: 0x%08X\n",
916 offset, crtcport, crtcindex, mask, shift,
917 io_flag_condition_idx, count, reg);
918
919 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
920 if (config > count) {
921 NV_ERROR(bios->dev,
922 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
923 offset, config, count);
37383650 924 return 0;
6ee73861
BS		 925 }
926
927 freq = ROM16(bios->data[offset + 12 + config * 2]);
928
929 if (io_flag_condition_idx > 0) {
930 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
931 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
932 "frequency doubled\n", offset);
933 freq *= 2;
934 } else
935 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
936 "frequency unchanged\n", offset);
937 }
938
939 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
940 offset, reg, config, freq);
941
942 setPLL(bios, reg, freq * 10);
943
37383650 944 return len;
6ee73861
BS		 945}
946
37383650 947static int
6ee73861
BS		 948init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
949{
950 /*
951 * INIT_END_REPEAT opcode: 0x36 ('6')
952 *
953 * offset (8 bit): opcode
954 *
955 * Marks the end of the block for INIT_REPEAT to repeat
956 */
957
958 /* no iexec->execute check by design */
959
960 /*
961 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
962 * we're not in repeat mode
963 */
964 if (iexec->repeat)
37383650 965 return 0;
6ee73861 966
37383650 967 return 1;
6ee73861
BS		 968}
969
37383650 970static int
6ee73861
BS		 971init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
972{
973 /*
974 * INIT_COPY opcode: 0x37 ('7')
975 *
976 * offset (8 bit): opcode
977 * offset + 1 (32 bit): register
978 * offset + 5 (8 bit): shift
979 * offset + 6 (8 bit): srcmask
980 * offset + 7 (16 bit): CRTC port
981 * offset + 9 (8 bit): CRTC index
982 * offset + 10 (8 bit): mask
983 *
984 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
985 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
986 * port
987 */
988
989 uint32_t reg = ROM32(bios->data[offset + 1]);
990 uint8_t shift = bios->data[offset + 5];
991 uint8_t srcmask = bios->data[offset + 6];
992 uint16_t crtcport = ROM16(bios->data[offset + 7]);
993 uint8_t crtcindex = bios->data[offset + 9];
994 uint8_t mask = bios->data[offset + 10];
995 uint32_t data;
996 uint8_t crtcdata;
997
998 if (!iexec->execute)
37383650 999 return 11;
6ee73861
BS		 1000
1001 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1002 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1003 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1004
1005 data = bios_rd32(bios, reg);
1006
1007 if (shift < 0x80)
1008 data >>= shift;
1009 else
1010 data <<= (0x100 - shift);
1011
1012 data &= srcmask;
1013
1014 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1015 crtcdata |= (uint8_t)data;
1016 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1017
37383650 1018 return 11;
6ee73861
BS		 1019}
1020
37383650 1021static int
6ee73861
BS		 1022init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1023{
1024 /*
1025 * INIT_NOT opcode: 0x38 ('8')
1026 *
1027 * offset (8 bit): opcode
1028 *
1029 * Invert the current execute / no-execute condition (i.e. "else")
1030 */
1031 if (iexec->execute)
1032 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1033 else
1034 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1035
1036 iexec->execute = !iexec->execute;
37383650 1037 return 1;
6ee73861
BS		 1038}
1039
37383650 1040static int
6ee73861
BS		 1041init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1042 struct init_exec *iexec)
1043{
1044 /*
1045 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1046 *
1047 * offset (8 bit): opcode
1048 * offset + 1 (8 bit): condition number
1049 *
1050 * Check condition "condition number" in the IO flag condition table.
1051 * If condition not met skip subsequent opcodes until condition is
1052 * inverted (INIT_NOT), or we hit INIT_RESUME
1053 */
1054
1055 uint8_t cond = bios->data[offset + 1];
1056
1057 if (!iexec->execute)
37383650 1058 return 2;
6ee73861
BS		 1059
1060 if (io_flag_condition_met(bios, offset, cond))
1061 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1062 else {
1063 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1064 iexec->execute = false;
1065 }
1066
37383650 1067 return 2;
6ee73861
BS		 1068}
1069
25908b77
BS		 1070static int
1071init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1072{
1073 /*
1074 * INIT_DP_CONDITION opcode: 0x3A ('')
1075 *
1076 * offset (8 bit): opcode
1077 * offset + 1 (8 bit): "sub" opcode
1078 * offset + 2 (8 bit): unknown
1079 *
1080 */
1081
1082 struct bit_displayport_encoder_table *dpe = NULL;
1083 struct dcb_entry *dcb = bios->display.output;
1084 struct drm_device *dev = bios->dev;
1085 uint8_t cond = bios->data[offset + 1];
1086 int dummy;
1087
1088 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1089
1090 if (!iexec->execute)
1091 return 3;
1092
1093 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1094 if (!dpe) {
1095 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
1096 return -EINVAL;
1097 }
1098
1099 switch (cond) {
1100 case 0:
1101 {
1102 struct dcb_connector_table_entry *ent =
1103 &bios->dcb.connector.entry[dcb->connector];
1104
1105 if (ent->type != DCB_CONNECTOR_eDP)
1106 iexec->execute = false;
1107 }
1108 break;
1109 case 1:
1110 case 2:
1111 if (!(dpe->unknown & cond))
1112 iexec->execute = false;
1113 break;
1114 case 5:
1115 {
1116 struct nouveau_i2c_chan *auxch;
1117 int ret;
1118
1119 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1120 if (!auxch)
1121 return -ENODEV;
1122
1123 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1124 if (ret)
1125 return ret;
1126
1127 if (cond & 1)
1128 iexec->execute = false;
1129 }
1130 break;
1131 default:
1132 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1133 break;
1134 }
1135
1136 if (iexec->execute)
1137 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1138 else
1139 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1140
1141 return 3;
1142}
1143
1144static int
1145init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1146{
1147 /*
1148 * INIT_3B opcode: 0x3B ('')
1149 *
1150 * offset (8 bit): opcode
1151 * offset + 1 (8 bit): crtc index
1152 *
1153 */
1154
1155 uint8_t or = ffs(bios->display.output->or) - 1;
1156 uint8_t index = bios->data[offset + 1];
1157 uint8_t data;
1158
1159 if (!iexec->execute)
1160 return 2;
1161
1162 data = bios_idxprt_rd(bios, 0x3d4, index);
1163 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1164 return 2;
1165}
1166
1167static int
1168init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1169{
1170 /*
1171 * INIT_3C opcode: 0x3C ('')
1172 *
1173 * offset (8 bit): opcode
1174 * offset + 1 (8 bit): crtc index
1175 *
1176 */
1177
1178 uint8_t or = ffs(bios->display.output->or) - 1;
1179 uint8_t index = bios->data[offset + 1];
1180 uint8_t data;
1181
1182 if (!iexec->execute)
1183 return 2;
1184
1185 data = bios_idxprt_rd(bios, 0x3d4, index);
1186 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1187 return 2;
1188}
1189
37383650 1190static int
6ee73861
BS		 1191init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1192 struct init_exec *iexec)
1193{
1194 /*
1195 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1196 *
1197 * offset (8 bit): opcode
1198 * offset + 1 (32 bit): control register
1199 * offset + 5 (32 bit): data register
1200 * offset + 9 (32 bit): mask
1201 * offset + 13 (32 bit): data
1202 * offset + 17 (8 bit): count
1203 * offset + 18 (8 bit): address 1
1204 * offset + 19 (8 bit): data 1
1205 * ...
1206 *
1207 * For each of "count" address and data pairs, write "data n" to
1208 * "data register", read the current value of "control register",
1209 * and write it back once ANDed with "mask", ORed with "data",
1210 * and ORed with "address n"
1211 */
1212
1213 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1214 uint32_t datareg = ROM32(bios->data[offset + 5]);
1215 uint32_t mask = ROM32(bios->data[offset + 9]);
1216 uint32_t data = ROM32(bios->data[offset + 13]);
1217 uint8_t count = bios->data[offset + 17];
37383650 1218 int len = 18 + count * 2;
6ee73861
BS		 1219 uint32_t value;
1220 int i;
1221
1222 if (!iexec->execute)
37383650 1223 return len;
6ee73861
BS		 1224
1225 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1226 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1227 offset, controlreg, datareg, mask, data, count);
1228
1229 for (i = 0; i < count; i++) {
1230 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1231 uint8_t instdata = bios->data[offset + 19 + i * 2];
1232
1233 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1234 offset, instaddress, instdata);
1235
1236 bios_wr32(bios, datareg, instdata);
1237 value = bios_rd32(bios, controlreg) & mask;
1238 value |= data;
1239 value |= instaddress;
1240 bios_wr32(bios, controlreg, value);
1241 }
1242
37383650 1243 return len;
6ee73861
BS		 1244}
1245
37383650 1246static int
6ee73861
BS		 1247init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1248 struct init_exec *iexec)
1249{
1250 /*
1251 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1252 *
1253 * offset (8 bit): opcode
1254 * offset + 1 (16 bit): CRTC port
1255 * offset + 3 (8 bit): CRTC index
1256 * offset + 4 (8 bit): mask
1257 * offset + 5 (8 bit): shift
1258 * offset + 6 (8 bit): count
1259 * offset + 7 (32 bit): register
1260 * offset + 11 (32 bit): frequency 1
1261 * ...
1262 *
1263 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1264 * Set PLL register "register" to coefficients for frequency n,
1265 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1266 * "mask" and shifted right by "shift".
1267 */
1268
1269 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1270 uint8_t crtcindex = bios->data[offset + 3];
1271 uint8_t mask = bios->data[offset + 4];
1272 uint8_t shift = bios->data[offset + 5];
1273 uint8_t count = bios->data[offset + 6];
1274 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1275 int len = 11 + count * 4;
6ee73861
BS		 1276 uint8_t config;
1277 uint32_t freq;
1278
1279 if (!iexec->execute)
37383650 1280 return len;
6ee73861
BS		 1281
1282 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1283 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1284 offset, crtcport, crtcindex, mask, shift, count, reg);
1285
1286 if (!reg)
37383650 1287 return len;
6ee73861
BS		 1288
1289 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1290 if (config > count) {
1291 NV_ERROR(bios->dev,
1292 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1293 offset, config, count);
37383650 1294 return 0;
6ee73861
BS		 1295 }
1296
1297 freq = ROM32(bios->data[offset + 11 + config * 4]);
1298
1299 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1300 offset, reg, config, freq);
1301
1302 setPLL(bios, reg, freq);
1303
37383650 1304 return len;
6ee73861
BS		 1305}
1306
37383650 1307static int
6ee73861
BS		 1308init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1309{
1310 /*
1311 * INIT_PLL2 opcode: 0x4B ('K')
1312 *
1313 * offset (8 bit): opcode
1314 * offset + 1 (32 bit): register
1315 * offset + 5 (32 bit): freq
1316 *
1317 * Set PLL register "register" to coefficients for frequency "freq"
1318 */
1319
1320 uint32_t reg = ROM32(bios->data[offset + 1]);
1321 uint32_t freq = ROM32(bios->data[offset + 5]);
1322
1323 if (!iexec->execute)
37383650 1324 return 9;
6ee73861
BS		 1325
1326 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1327 offset, reg, freq);
1328
1329 setPLL(bios, reg, freq);
37383650 1330 return 9;
6ee73861
BS		 1331}
1332
37383650 1333static int
6ee73861
BS		 1334init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1335{
1336 /*
1337 * INIT_I2C_BYTE opcode: 0x4C ('L')
1338 *
1339 * offset (8 bit): opcode
1340 * offset + 1 (8 bit): DCB I2C table entry index
1341 * offset + 2 (8 bit): I2C slave address
1342 * offset + 3 (8 bit): count
1343 * offset + 4 (8 bit): I2C register 1
1344 * offset + 5 (8 bit): mask 1
1345 * offset + 6 (8 bit): data 1
1346 * ...
1347 *
1348 * For each of "count" registers given by "I2C register n" on the device
1349 * addressed by "I2C slave address" on the I2C bus given by
1350 * "DCB I2C table entry index", read the register, AND the result with
1351 * "mask n" and OR it with "data n" before writing it back to the device
1352 */
1353
1354 uint8_t i2c_index = bios->data[offset + 1];
1355 uint8_t i2c_address = bios->data[offset + 2];
1356 uint8_t count = bios->data[offset + 3];
37383650 1357 int len = 4 + count * 3;
6ee73861
BS		 1358 struct nouveau_i2c_chan *chan;
1359 struct i2c_msg msg;
1360 int i;
1361
1362 if (!iexec->execute)
37383650 1363 return len;
6ee73861
BS		 1364
1365 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1366 "Count: 0x%02X\n",
1367 offset, i2c_index, i2c_address, count);
1368
1369 chan = init_i2c_device_find(bios->dev, i2c_index);
1370 if (!chan)
37383650 1371 return 0;
6ee73861
BS		 1372
1373 for (i = 0; i < count; i++) {
1374 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
1375 uint8_t mask = bios->data[offset + 5 + i * 3];
1376 uint8_t data = bios->data[offset + 6 + i * 3];
1377 uint8_t value;
1378
1379 msg.addr = i2c_address;
1380 msg.flags = I2C_M_RD;
1381 msg.len = 1;
1382 msg.buf = &value;
1383 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1384 return 0;
6ee73861
BS		 1385
1386 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1387 "Mask: 0x%02X, Data: 0x%02X\n",
1388 offset, i2c_reg, value, mask, data);
1389
1390 value = (value & mask) | data;
1391
1392 if (bios->execute) {
1393 msg.addr = i2c_address;
1394 msg.flags = 0;
1395 msg.len = 1;
1396 msg.buf = &value;
1397 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1398 return 0;
6ee73861
BS		 1399 }
1400 }
1401
37383650 1402 return len;
6ee73861
BS		 1403}
1404
37383650 1405static int
6ee73861
BS		 1406init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1407{
1408 /*
1409 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1410 *
1411 * offset (8 bit): opcode
1412 * offset + 1 (8 bit): DCB I2C table entry index
1413 * offset + 2 (8 bit): I2C slave address
1414 * offset + 3 (8 bit): count
1415 * offset + 4 (8 bit): I2C register 1
1416 * offset + 5 (8 bit): data 1
1417 * ...
1418 *
1419 * For each of "count" registers given by "I2C register n" on the device
1420 * addressed by "I2C slave address" on the I2C bus given by
1421 * "DCB I2C table entry index", set the register to "data n"
1422 */
1423
1424 uint8_t i2c_index = bios->data[offset + 1];
1425 uint8_t i2c_address = bios->data[offset + 2];
1426 uint8_t count = bios->data[offset + 3];
37383650 1427 int len = 4 + count * 2;
6ee73861
BS		 1428 struct nouveau_i2c_chan *chan;
1429 struct i2c_msg msg;
1430 int i;
1431
1432 if (!iexec->execute)
37383650 1433 return len;
6ee73861
BS		 1434
1435 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1436 "Count: 0x%02X\n",
1437 offset, i2c_index, i2c_address, count);
1438
1439 chan = init_i2c_device_find(bios->dev, i2c_index);
1440 if (!chan)
37383650 1441 return 0;
6ee73861
BS		 1442
1443 for (i = 0; i < count; i++) {
1444 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
1445 uint8_t data = bios->data[offset + 5 + i * 2];
1446
1447 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1448 offset, i2c_reg, data);
1449
1450 if (bios->execute) {
1451 msg.addr = i2c_address;
1452 msg.flags = 0;
1453 msg.len = 1;
1454 msg.buf = &data;
1455 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1456 return 0;
6ee73861
BS		 1457 }
1458 }
1459
37383650 1460 return len;
6ee73861
BS		 1461}
1462
37383650 1463static int
6ee73861
BS		 1464init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1465{
1466 /*
1467 * INIT_ZM_I2C opcode: 0x4E ('N')
1468 *
1469 * offset (8 bit): opcode
1470 * offset + 1 (8 bit): DCB I2C table entry index
1471 * offset + 2 (8 bit): I2C slave address
1472 * offset + 3 (8 bit): count
1473 * offset + 4 (8 bit): data 1
1474 * ...
1475 *
1476 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1477 * address" on the I2C bus given by "DCB I2C table entry index"
1478 */
1479
1480 uint8_t i2c_index = bios->data[offset + 1];
1481 uint8_t i2c_address = bios->data[offset + 2];
1482 uint8_t count = bios->data[offset + 3];
37383650 1483 int len = 4 + count;
6ee73861
BS		 1484 struct nouveau_i2c_chan *chan;
1485 struct i2c_msg msg;
1486 uint8_t data[256];
1487 int i;
1488
1489 if (!iexec->execute)
37383650 1490 return len;
6ee73861
BS		 1491
1492 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1493 "Count: 0x%02X\n",
1494 offset, i2c_index, i2c_address, count);
1495
1496 chan = init_i2c_device_find(bios->dev, i2c_index);
1497 if (!chan)
37383650 1498 return 0;
6ee73861
BS		 1499
1500 for (i = 0; i < count; i++) {
1501 data[i] = bios->data[offset + 4 + i];
1502
1503 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1504 }
1505
1506 if (bios->execute) {
1507 msg.addr = i2c_address;
1508 msg.flags = 0;
1509 msg.len = count;
1510 msg.buf = data;
1511 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1512 return 0;
6ee73861
BS		 1513 }
1514
37383650 1515 return len;
6ee73861
BS		 1516}
1517
37383650 1518static int
6ee73861
BS		 1519init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1520{
1521 /*
1522 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1523 *
1524 * offset (8 bit): opcode
1525 * offset + 1 (8 bit): magic lookup value
1526 * offset + 2 (8 bit): TMDS address
1527 * offset + 3 (8 bit): mask
1528 * offset + 4 (8 bit): data
1529 *
1530 * Read the data reg for TMDS address "TMDS address", AND it with mask
1531 * and OR it with data, then write it back
1532 * "magic lookup value" determines which TMDS base address register is
1533 * used -- see get_tmds_index_reg()
1534 */
1535
1536 uint8_t mlv = bios->data[offset + 1];
1537 uint32_t tmdsaddr = bios->data[offset + 2];
1538 uint8_t mask = bios->data[offset + 3];
1539 uint8_t data = bios->data[offset + 4];
1540 uint32_t reg, value;
1541
1542 if (!iexec->execute)
37383650 1543 return 5;
6ee73861
BS		 1544
1545 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1546 "Mask: 0x%02X, Data: 0x%02X\n",
1547 offset, mlv, tmdsaddr, mask, data);
1548
1549 reg = get_tmds_index_reg(bios->dev, mlv);
1550 if (!reg)
37383650 1551 return 0;
6ee73861
BS		 1552
1553 bios_wr32(bios, reg,
1554 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1555 value = (bios_rd32(bios, reg + 4) & mask) | data;
1556 bios_wr32(bios, reg + 4, value);
1557 bios_wr32(bios, reg, tmdsaddr);
1558
37383650 1559 return 5;
6ee73861
BS		 1560}
1561
37383650 1562static int
6ee73861
BS		 1563init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1564 struct init_exec *iexec)
1565{
1566 /*
1567 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1568 *
1569 * offset (8 bit): opcode
1570 * offset + 1 (8 bit): magic lookup value
1571 * offset + 2 (8 bit): count
1572 * offset + 3 (8 bit): addr 1
1573 * offset + 4 (8 bit): data 1
1574 * ...
1575 *
1576 * For each of "count" TMDS address and data pairs write "data n" to
1577 * "addr n". "magic lookup value" determines which TMDS base address
1578 * register is used -- see get_tmds_index_reg()
1579 */
1580
1581 uint8_t mlv = bios->data[offset + 1];
1582 uint8_t count = bios->data[offset + 2];
37383650 1583 int len = 3 + count * 2;
6ee73861
BS		 1584 uint32_t reg;
1585 int i;
1586
1587 if (!iexec->execute)
37383650 1588 return len;
6ee73861
BS		 1589
1590 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1591 offset, mlv, count);
1592
1593 reg = get_tmds_index_reg(bios->dev, mlv);
1594 if (!reg)
37383650 1595 return 0;
6ee73861
BS		 1596
1597 for (i = 0; i < count; i++) {
1598 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1599 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1600
1601 bios_wr32(bios, reg + 4, tmdsdata);
1602 bios_wr32(bios, reg, tmdsaddr);
1603 }
1604
37383650 1605 return len;
6ee73861
BS		 1606}
1607
37383650 1608static int
6ee73861
BS		 1609init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1610 struct init_exec *iexec)
1611{
1612 /*
1613 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1614 *
1615 * offset (8 bit): opcode
1616 * offset + 1 (8 bit): CRTC index1
1617 * offset + 2 (8 bit): CRTC index2
1618 * offset + 3 (8 bit): baseaddr
1619 * offset + 4 (8 bit): count
1620 * offset + 5 (8 bit): data 1
1621 * ...
1622 *
1623 * For each of "count" address and data pairs, write "baseaddr + n" to
1624 * "CRTC index1" and "data n" to "CRTC index2"
1625 * Once complete, restore initial value read from "CRTC index1"
1626 */
1627 uint8_t crtcindex1 = bios->data[offset + 1];
1628 uint8_t crtcindex2 = bios->data[offset + 2];
1629 uint8_t baseaddr = bios->data[offset + 3];
1630 uint8_t count = bios->data[offset + 4];
37383650 1631 int len = 5 + count;
6ee73861
BS		 1632 uint8_t oldaddr, data;
1633 int i;
1634
1635 if (!iexec->execute)
37383650 1636 return len;
6ee73861
BS		 1637
1638 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1639 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1640 offset, crtcindex1, crtcindex2, baseaddr, count);
1641
1642 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1643
1644 for (i = 0; i < count; i++) {
1645 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1646 baseaddr + i);
1647 data = bios->data[offset + 5 + i];
1648 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1649 }
1650
1651 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1652
37383650 1653 return len;
6ee73861
BS		 1654}
1655
37383650 1656static int
6ee73861
BS		 1657init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1658{
1659 /*
1660 * INIT_CR opcode: 0x52 ('R')
1661 *
1662 * offset (8 bit): opcode
1663 * offset + 1 (8 bit): CRTC index
1664 * offset + 2 (8 bit): mask
1665 * offset + 3 (8 bit): data
1666 *
1667 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1668 * data back to "CRTC index"
1669 */
1670
1671 uint8_t crtcindex = bios->data[offset + 1];
1672 uint8_t mask = bios->data[offset + 2];
1673 uint8_t data = bios->data[offset + 3];
1674 uint8_t value;
1675
1676 if (!iexec->execute)
37383650 1677 return 4;
6ee73861
BS		 1678
1679 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1680 offset, crtcindex, mask, data);
1681
1682 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1683 value |= data;
1684 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1685
37383650 1686 return 4;
6ee73861
BS		 1687}
1688
37383650 1689static int
6ee73861
BS		 1690init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1691{
1692 /*
1693 * INIT_ZM_CR opcode: 0x53 ('S')
1694 *
1695 * offset (8 bit): opcode
1696 * offset + 1 (8 bit): CRTC index
1697 * offset + 2 (8 bit): value
1698 *
1699 * Assign "value" to CRTC register with index "CRTC index".
1700 */
1701
1702 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1703 uint8_t data = bios->data[offset + 2];
1704
1705 if (!iexec->execute)
37383650 1706 return 3;
6ee73861
BS		 1707
1708 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1709
37383650 1710 return 3;
6ee73861
BS		 1711}
1712
37383650 1713static int
6ee73861
BS		 1714init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1715{
1716 /*
1717 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1718 *
1719 * offset (8 bit): opcode
1720 * offset + 1 (8 bit): count
1721 * offset + 2 (8 bit): CRTC index 1
1722 * offset + 3 (8 bit): value 1
1723 * ...
1724 *
1725 * For "count", assign "value n" to CRTC register with index
1726 * "CRTC index n".
1727 */
1728
1729 uint8_t count = bios->data[offset + 1];
37383650 1730 int len = 2 + count * 2;
6ee73861
BS		 1731 int i;
1732
1733 if (!iexec->execute)
37383650 1734 return len;
6ee73861
BS		 1735
1736 for (i = 0; i < count; i++)
1737 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1738
37383650 1739 return len;
6ee73861
BS		 1740}
1741
37383650 1742static int
6ee73861
BS		 1743init_condition_time(struct nvbios *bios, uint16_t offset,
1744 struct init_exec *iexec)
1745{
1746 /*
1747 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1748 *
1749 * offset (8 bit): opcode
1750 * offset + 1 (8 bit): condition number
1751 * offset + 2 (8 bit): retries / 50
1752 *
1753 * Check condition "condition number" in the condition table.
1754 * Bios code then sleeps for 2ms if the condition is not met, and
1755 * repeats up to "retries" times, but on one C51 this has proved
1756 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1757 * this, and bail after "retries" times, or 2s, whichever is less.
1758 * If still not met after retries, clear execution flag for this table.
1759 */
1760
1761 uint8_t cond = bios->data[offset + 1];
1762 uint16_t retries = bios->data[offset + 2] * 50;
1763 unsigned cnt;
1764
1765 if (!iexec->execute)
37383650 1766 return 3;
6ee73861
BS		 1767
1768 if (retries > 100)
1769 retries = 100;
1770
1771 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1772 offset, cond, retries);
1773
1774 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1775 retries = 1;
1776
1777 for (cnt = 0; cnt < retries; cnt++) {
1778 if (bios_condition_met(bios, offset, cond)) {
1779 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1780 offset);
1781 break;
1782 } else {
1783 BIOSLOG(bios, "0x%04X: "
1784 "Condition not met, sleeping for 20ms\n",
1785 offset);
1786 msleep(20);
1787 }
1788 }
1789
1790 if (!bios_condition_met(bios, offset, cond)) {
1791 NV_WARN(bios->dev,
1792 "0x%04X: Condition still not met after %dms, "
1793 "skipping following opcodes\n", offset, 20 * retries);
1794 iexec->execute = false;
1795 }
1796
37383650 1797 return 3;
6ee73861
BS		 1798}
1799
37383650 1800static int
6ee73861
BS		 1801init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1802 struct init_exec *iexec)
1803{
1804 /*
1805 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1806 *
1807 * offset (8 bit): opcode
1808 * offset + 1 (32 bit): base register
1809 * offset + 5 (8 bit): count
1810 * offset + 6 (32 bit): value 1
1811 * ...
1812 *
1813 * Starting at offset + 6 there are "count" 32 bit values.
1814 * For "count" iterations set "base register" + 4 * current_iteration
1815 * to "value current_iteration"
1816 */
1817
1818 uint32_t basereg = ROM32(bios->data[offset + 1]);
1819 uint32_t count = bios->data[offset + 5];
37383650 1820 int len = 6 + count * 4;
6ee73861
BS		 1821 int i;
1822
1823 if (!iexec->execute)
37383650 1824 return len;
6ee73861
BS		 1825
1826 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1827 offset, basereg, count);
1828
1829 for (i = 0; i < count; i++) {
1830 uint32_t reg = basereg + i * 4;
1831 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1832
1833 bios_wr32(bios, reg, data);
1834 }
1835
37383650 1836 return len;
6ee73861
BS		 1837}
1838
37383650 1839static int
6ee73861
BS		 1840init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1841{
1842 /*
1843 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1844 *
1845 * offset (8 bit): opcode
1846 * offset + 1 (16 bit): subroutine offset (in bios)
1847 *
1848 * Calls a subroutine that will execute commands until INIT_DONE
1849 * is found.
1850 */
1851
1852 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1853
1854 if (!iexec->execute)
37383650 1855 return 3;
6ee73861
BS		 1856
1857 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1858 offset, sub_offset);
1859
1860 parse_init_table(bios, sub_offset, iexec);
1861
1862 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1863
37383650 1864 return 3;
6ee73861
BS		 1865}
1866
37383650 1867static int
6ee73861
BS		 1868init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1869{
1870 /*
1871 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1872 *
1873 * offset (8 bit): opcode
1874 * offset + 1 (32 bit): src reg
1875 * offset + 5 (8 bit): shift
1876 * offset + 6 (32 bit): src mask
1877 * offset + 10 (32 bit): xor
1878 * offset + 14 (32 bit): dst reg
1879 * offset + 18 (32 bit): dst mask
1880 *
1881 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1882 * "src mask", then XOR with "xor". Write this OR'd with
1883 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1884 */
1885
1886 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1887 uint8_t shift = bios->data[offset + 5];
1888 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1889 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1890 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1891 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1892 uint32_t srcvalue, dstvalue;
1893
1894 if (!iexec->execute)
37383650 1895 return 22;
6ee73861
BS		 1896
1897 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1898 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1899 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1900
1901 srcvalue = bios_rd32(bios, srcreg);
1902
1903 if (shift < 0x80)
1904 srcvalue >>= shift;
1905 else
1906 srcvalue <<= (0x100 - shift);
1907
1908 srcvalue = (srcvalue & srcmask) ^ xor;
1909
1910 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1911
1912 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1913
37383650 1914 return 22;
6ee73861
BS		 1915}
1916
37383650 1917static int
6ee73861
BS		 1918init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1919{
1920 /*
1921 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1922 *
1923 * offset (8 bit): opcode
1924 * offset + 1 (16 bit): CRTC port
1925 * offset + 3 (8 bit): CRTC index
1926 * offset + 4 (8 bit): data
1927 *
1928 * Write "data" to index "CRTC index" of "CRTC port"
1929 */
1930 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1931 uint8_t crtcindex = bios->data[offset + 3];
1932 uint8_t data = bios->data[offset + 4];
1933
1934 if (!iexec->execute)
37383650 1935 return 5;
6ee73861
BS		 1936
1937 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1938
37383650 1939 return 5;
6ee73861
BS		 1940}
1941
37383650 1942static int
6ee73861
BS		 1943init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1944{
1945 /*
1946 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
1947 *
1948 * offset (8 bit): opcode
1949 *
1950 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1951 * that the hardware can correctly calculate how much VRAM it has
1952 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
1953 *
1954 * The implementation of this opcode in general consists of two parts:
1955 * 1) determination of the memory bus width
1956 * 2) determination of how many of the card's RAM pads have ICs attached
1957 *
1958 * 1) is done by a cunning combination of writes to offsets 0x1c and
1959 * 0x3c in the framebuffer, and seeing whether the written values are
1960 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1961 *
1962 * 2) is done by a cunning combination of writes to an offset slightly
1963 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
1964 * if the test pattern can be read back. This then affects bits 12-15 of
1965 * NV_PFB_CFG0
1966 *
1967 * In this context a "cunning combination" may include multiple reads
1968 * and writes to varying locations, often alternating the test pattern
1969 * and 0, doubtless to make sure buffers are filled, residual charges
1970 * on tracks are removed etc.
1971 *
1972 * Unfortunately, the "cunning combination"s mentioned above, and the
1973 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1974 * trace I have.
1975 *
1976 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1977 * we started was correct, and use that instead
1978 */
1979
1980 /* no iexec->execute check by design */
1981
1982 /*
1983 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
1984 * and kmmio traces of the binary driver POSTing the card show nothing
1985 * being done for this opcode. why is it still listed in the table?!
1986 */
1987
1988 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1989
e235c1f3 1990 if (dev_priv->card_type >= NV_40)
37383650 1991 return 1;
6ee73861
BS		 1992
1993 /*
1994 * On every card I've seen, this step gets done for us earlier in
1995 * the init scripts
1996 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
1997 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
1998 */
1999
2000 /*
2001 * This also has probably been done in the scripts, but an mmio trace of
2002 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
2003 */
2004 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
2005
2006 /* write back the saved configuration value */
2007 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
2008
37383650 2009 return 1;
6ee73861
BS		 2010}
2011
37383650 2012static int
6ee73861
BS		 2013init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2014{
2015 /*
2016 * INIT_RESET opcode: 0x65 ('e')
2017 *
2018 * offset (8 bit): opcode
2019 * offset + 1 (32 bit): register
2020 * offset + 5 (32 bit): value1
2021 * offset + 9 (32 bit): value2
2022 *
2023 * Assign "value1" to "register", then assign "value2" to "register"
2024 */
2025
2026 uint32_t reg = ROM32(bios->data[offset + 1]);
2027 uint32_t value1 = ROM32(bios->data[offset + 5]);
2028 uint32_t value2 = ROM32(bios->data[offset + 9]);
2029 uint32_t pci_nv_19, pci_nv_20;
2030
2031 /* no iexec->execute check by design */
2032
2033 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2034 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
2035 bios_wr32(bios, reg, value1);
2036
2037 udelay(10);
2038
2039 bios_wr32(bios, reg, value2);
2040 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2041
2042 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2043 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2044 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2045
37383650 2046 return 13;
6ee73861
BS		 2047}
2048
37383650 2049static int
6ee73861
BS		 2050init_configure_mem(struct nvbios *bios, uint16_t offset,
2051 struct init_exec *iexec)
2052{
2053 /*
2054 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2055 *
2056 * offset (8 bit): opcode
2057 *
2058 * Equivalent to INIT_DONE on bios version 3 or greater.
2059 * For early bios versions, sets up the memory registers, using values
2060 * taken from the memory init table
2061 */
2062
2063 /* no iexec->execute check by design */
2064
2065 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2066 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2067 uint32_t reg, data;
2068
2069 if (bios->major_version > 2)
37383650 2070 return 0;
6ee73861
BS		 2071
2072 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2073 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2074
2075 if (bios->data[meminitoffs] & 1)
2076 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2077
2078 for (reg = ROM32(bios->data[seqtbloffs]);
2079 reg != 0xffffffff;
2080 reg = ROM32(bios->data[seqtbloffs += 4])) {
2081
2082 switch (reg) {
2083 case NV_PFB_PRE:
2084 data = NV_PFB_PRE_CMD_PRECHARGE;
2085 break;
2086 case NV_PFB_PAD:
2087 data = NV_PFB_PAD_CKE_NORMAL;
2088 break;
2089 case NV_PFB_REF:
2090 data = NV_PFB_REF_CMD_REFRESH;
2091 break;
2092 default:
2093 data = ROM32(bios->data[meminitdata]);
2094 meminitdata += 4;
2095 if (data == 0xffffffff)
2096 continue;
2097 }
2098
2099 bios_wr32(bios, reg, data);
2100 }
2101
37383650 2102 return 1;
6ee73861
BS		 2103}
2104
37383650 2105static int
6ee73861
BS		 2106init_configure_clk(struct nvbios *bios, uint16_t offset,
2107 struct init_exec *iexec)
2108{
2109 /*
2110 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2111 *
2112 * offset (8 bit): opcode
2113 *
2114 * Equivalent to INIT_DONE on bios version 3 or greater.
2115 * For early bios versions, sets up the NVClk and MClk PLLs, using
2116 * values taken from the memory init table
2117 */
2118
2119 /* no iexec->execute check by design */
2120
2121 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2122 int clock;
2123
2124 if (bios->major_version > 2)
37383650 2125 return 0;
6ee73861
BS		 2126
2127 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2128 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2129
2130 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2131 if (bios->data[meminitoffs] & 1) /* DDR */
2132 clock *= 2;
2133 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2134
37383650 2135 return 1;
6ee73861
BS		 2136}
2137
37383650 2138static int
6ee73861
BS		 2139init_configure_preinit(struct nvbios *bios, uint16_t offset,
2140 struct init_exec *iexec)
2141{
2142 /*
2143 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2144 *
2145 * offset (8 bit): opcode
2146 *
2147 * Equivalent to INIT_DONE on bios version 3 or greater.
2148 * For early bios versions, does early init, loading ram and crystal
2149 * configuration from straps into CR3C
2150 */
2151
2152 /* no iexec->execute check by design */
2153
2154 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2155 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2156
2157 if (bios->major_version > 2)
37383650 2158 return 0;
6ee73861
BS		 2159
2160 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2161 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2162
37383650 2163 return 1;
6ee73861
BS		 2164}
2165
37383650 2166static int
6ee73861
BS		 2167init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2168{
2169 /*
2170 * INIT_IO opcode: 0x69 ('i')
2171 *
2172 * offset (8 bit): opcode
2173 * offset + 1 (16 bit): CRTC port
2174 * offset + 3 (8 bit): mask
2175 * offset + 4 (8 bit): data
2176 *
2177 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2178 */
2179
2180 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2181 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2182 uint8_t mask = bios->data[offset + 3];
2183 uint8_t data = bios->data[offset + 4];
2184
2185 if (!iexec->execute)
37383650 2186 return 5;
6ee73861
BS		 2187
2188 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2189 offset, crtcport, mask, data);
2190
2191 /*
2192 * I have no idea what this does, but NVIDIA do this magic sequence
2193 * in the places where this INIT_IO happens..
2194 */
2195 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2196 int i;
2197
2198 bios_wr32(bios, 0x614100, (bios_rd32(
2199 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2200
2201 bios_wr32(bios, 0x00e18c, bios_rd32(
2202 bios, 0x00e18c) | 0x00020000);
2203
2204 bios_wr32(bios, 0x614900, (bios_rd32(
2205 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2206
2207 bios_wr32(bios, 0x000200, bios_rd32(
2208 bios, 0x000200) & ~0x40000000);
2209
2210 mdelay(10);
2211
2212 bios_wr32(bios, 0x00e18c, bios_rd32(
2213 bios, 0x00e18c) & ~0x00020000);
2214
2215 bios_wr32(bios, 0x000200, bios_rd32(
2216 bios, 0x000200) | 0x40000000);
2217
2218 bios_wr32(bios, 0x614100, 0x00800018);
2219 bios_wr32(bios, 0x614900, 0x00800018);
2220
2221 mdelay(10);
2222
2223 bios_wr32(bios, 0x614100, 0x10000018);
2224 bios_wr32(bios, 0x614900, 0x10000018);
2225
2226 for (i = 0; i < 3; i++)
2227 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2228 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2229
2230 for (i = 0; i < 2; i++)
2231 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2232 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2233
2234 for (i = 0; i < 3; i++)
2235 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2236 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2237
2238 for (i = 0; i < 2; i++)
2239 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2240 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2241
2242 for (i = 0; i < 2; i++)
2243 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2244 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2245 return 5;
6ee73861
BS		 2246 }
2247
2248 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2249 data);
37383650 2250 return 5;
6ee73861
BS		 2251}
2252
37383650 2253static int
6ee73861
BS		 2254init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2255{
2256 /*
2257 * INIT_SUB opcode: 0x6B ('k')
2258 *
2259 * offset (8 bit): opcode
2260 * offset + 1 (8 bit): script number
2261 *
2262 * Execute script number "script number", as a subroutine
2263 */
2264
2265 uint8_t sub = bios->data[offset + 1];
2266
2267 if (!iexec->execute)
37383650 2268 return 2;
6ee73861
BS		 2269
2270 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2271
2272 parse_init_table(bios,
2273 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2274 iexec);
2275
2276 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2277
37383650 2278 return 2;
6ee73861
BS		 2279}
2280
37383650 2281static int
6ee73861
BS		 2282init_ram_condition(struct nvbios *bios, uint16_t offset,
2283 struct init_exec *iexec)
2284{
2285 /*
2286 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2287 *
2288 * offset (8 bit): opcode
2289 * offset + 1 (8 bit): mask
2290 * offset + 2 (8 bit): cmpval
2291 *
2292 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2293 * If condition not met skip subsequent opcodes until condition is
2294 * inverted (INIT_NOT), or we hit INIT_RESUME
2295 */
2296
2297 uint8_t mask = bios->data[offset + 1];
2298 uint8_t cmpval = bios->data[offset + 2];
2299 uint8_t data;
2300
2301 if (!iexec->execute)
37383650 2302 return 3;
6ee73861
BS		 2303
2304 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2305
2306 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2307 offset, data, cmpval);
2308
2309 if (data == cmpval)
2310 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2311 else {
2312 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2313 iexec->execute = false;
2314 }
2315
37383650 2316 return 3;
6ee73861
BS		 2317}
2318
37383650 2319static int
6ee73861
BS		 2320init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2321{
2322 /*
2323 * INIT_NV_REG opcode: 0x6E ('n')
2324 *
2325 * offset (8 bit): opcode
2326 * offset + 1 (32 bit): register
2327 * offset + 5 (32 bit): mask
2328 * offset + 9 (32 bit): data
2329 *
2330 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2331 */
2332
2333 uint32_t reg = ROM32(bios->data[offset + 1]);
2334 uint32_t mask = ROM32(bios->data[offset + 5]);
2335 uint32_t data = ROM32(bios->data[offset + 9]);
2336
2337 if (!iexec->execute)
37383650 2338 return 13;
6ee73861
BS		 2339
2340 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2341 offset, reg, mask, data);
2342
2343 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2344
37383650 2345 return 13;
6ee73861
BS		 2346}
2347
37383650 2348static int
6ee73861
BS		 2349init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2350{
2351 /*
2352 * INIT_MACRO opcode: 0x6F ('o')
2353 *
2354 * offset (8 bit): opcode
2355 * offset + 1 (8 bit): macro number
2356 *
2357 * Look up macro index "macro number" in the macro index table.
2358 * The macro index table entry has 1 byte for the index in the macro
2359 * table, and 1 byte for the number of times to repeat the macro.
2360 * The macro table entry has 4 bytes for the register address and
2361 * 4 bytes for the value to write to that register
2362 */
2363
2364 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2365 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2366 uint8_t macro_tbl_idx = bios->data[tmp];
2367 uint8_t count = bios->data[tmp + 1];
2368 uint32_t reg, data;
2369 int i;
2370
2371 if (!iexec->execute)
37383650 2372 return 2;
6ee73861
BS		 2373
2374 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2375 "Count: 0x%02X\n",
2376 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2377
2378 for (i = 0; i < count; i++) {
2379 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2380
2381 reg = ROM32(bios->data[macroentryptr]);
2382 data = ROM32(bios->data[macroentryptr + 4]);
2383
2384 bios_wr32(bios, reg, data);
2385 }
2386
37383650 2387 return 2;
6ee73861
BS		 2388}
2389
37383650 2390static int
6ee73861
BS		 2391init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2392{
2393 /*
2394 * INIT_DONE opcode: 0x71 ('q')
2395 *
2396 * offset (8 bit): opcode
2397 *
2398 * End the current script
2399 */
2400
2401 /* mild retval abuse to stop parsing this table */
37383650 2402 return 0;
6ee73861
BS		 2403}
2404
37383650 2405static int
6ee73861
BS		 2406init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2407{
2408 /*
2409 * INIT_RESUME opcode: 0x72 ('r')
2410 *
2411 * offset (8 bit): opcode
2412 *
2413 * End the current execute / no-execute condition
2414 */
2415
2416 if (iexec->execute)
37383650 2417 return 1;
6ee73861
BS		 2418
2419 iexec->execute = true;
2420 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2421
37383650 2422 return 1;
6ee73861
BS		 2423}
2424
37383650 2425static int
6ee73861
BS		 2426init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2427{
2428 /*
2429 * INIT_TIME opcode: 0x74 ('t')
2430 *
2431 * offset (8 bit): opcode
2432 * offset + 1 (16 bit): time
2433 *
2434 * Sleep for "time" microseconds.
2435 */
2436
2437 unsigned time = ROM16(bios->data[offset + 1]);
2438
2439 if (!iexec->execute)
37383650 2440 return 3;
6ee73861
BS		 2441
2442 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2443 offset, time);
2444
2445 if (time < 1000)
2446 udelay(time);
2447 else
2448 msleep((time + 900) / 1000);
2449
37383650 2450 return 3;
6ee73861
BS		 2451}
2452
37383650 2453static int
6ee73861
BS		 2454init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2455{
2456 /*
2457 * INIT_CONDITION opcode: 0x75 ('u')
2458 *
2459 * offset (8 bit): opcode
2460 * offset + 1 (8 bit): condition number
2461 *
2462 * Check condition "condition number" in the condition table.
2463 * If condition not met skip subsequent opcodes until condition is
2464 * inverted (INIT_NOT), or we hit INIT_RESUME
2465 */
2466
2467 uint8_t cond = bios->data[offset + 1];
2468
2469 if (!iexec->execute)
37383650 2470 return 2;
6ee73861
BS		 2471
2472 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2473
2474 if (bios_condition_met(bios, offset, cond))
2475 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2476 else {
2477 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2478 iexec->execute = false;
2479 }
2480
37383650 2481 return 2;
6ee73861
BS		 2482}
2483
37383650 2484static int
6ee73861
BS		 2485init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2486{
2487 /*
2488 * INIT_IO_CONDITION opcode: 0x76
2489 *
2490 * offset (8 bit): opcode
2491 * offset + 1 (8 bit): condition number
2492 *
2493 * Check condition "condition number" in the io condition table.
2494 * If condition not met skip subsequent opcodes until condition is
2495 * inverted (INIT_NOT), or we hit INIT_RESUME
2496 */
2497
2498 uint8_t cond = bios->data[offset + 1];
2499
2500 if (!iexec->execute)
37383650 2501 return 2;
6ee73861
BS		 2502
2503 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2504
2505 if (io_condition_met(bios, offset, cond))
2506 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2507 else {
2508 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2509 iexec->execute = false;
2510 }
2511
37383650 2512 return 2;
6ee73861
BS		 2513}
2514
37383650 2515static int
6ee73861
BS		 2516init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2517{
2518 /*
2519 * INIT_INDEX_IO opcode: 0x78 ('x')
2520 *
2521 * offset (8 bit): opcode
2522 * offset + 1 (16 bit): CRTC port
2523 * offset + 3 (8 bit): CRTC index
2524 * offset + 4 (8 bit): mask
2525 * offset + 5 (8 bit): data
2526 *
2527 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2528 * OR with "data", write-back
2529 */
2530
2531 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2532 uint8_t crtcindex = bios->data[offset + 3];
2533 uint8_t mask = bios->data[offset + 4];
2534 uint8_t data = bios->data[offset + 5];
2535 uint8_t value;
2536
2537 if (!iexec->execute)
37383650 2538 return 6;
6ee73861
BS		 2539
2540 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2541 "Data: 0x%02X\n",
2542 offset, crtcport, crtcindex, mask, data);
2543
2544 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2545 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2546
37383650 2547 return 6;
6ee73861
BS		 2548}
2549
37383650 2550static int
6ee73861
BS		 2551init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2552{
2553 /*
2554 * INIT_PLL opcode: 0x79 ('y')
2555 *
2556 * offset (8 bit): opcode
2557 * offset + 1 (32 bit): register
2558 * offset + 5 (16 bit): freq
2559 *
2560 * Set PLL register "register" to coefficients for frequency (10kHz)
2561 * "freq"
2562 */
2563
2564 uint32_t reg = ROM32(bios->data[offset + 1]);
2565 uint16_t freq = ROM16(bios->data[offset + 5]);
2566
2567 if (!iexec->execute)
37383650 2568 return 7;
6ee73861
BS		 2569
2570 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2571
2572 setPLL(bios, reg, freq * 10);
2573
37383650 2574 return 7;
6ee73861
BS		 2575}
2576
37383650 2577static int
6ee73861
BS		 2578init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2579{
2580 /*
2581 * INIT_ZM_REG opcode: 0x7A ('z')
2582 *
2583 * offset (8 bit): opcode
2584 * offset + 1 (32 bit): register
2585 * offset + 5 (32 bit): value
2586 *
2587 * Assign "value" to "register"
2588 */
2589
2590 uint32_t reg = ROM32(bios->data[offset + 1]);
2591 uint32_t value = ROM32(bios->data[offset + 5]);
2592
2593 if (!iexec->execute)
37383650 2594 return 9;
6ee73861
BS		 2595
2596 if (reg == 0x000200)
2597 value |= 1;
2598
2599 bios_wr32(bios, reg, value);
2600
37383650 2601 return 9;
6ee73861
BS		 2602}
2603
37383650 2604static int
6ee73861
BS		 2605init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2606 struct init_exec *iexec)
2607{
2608 /*
2609 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2610 *
2611 * offset (8 bit): opcode
2612 * offset + 1 (8 bit): PLL type
2613 * offset + 2 (32 bit): frequency 0
2614 *
2615 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2616 * ram_restrict_table_ptr. The value read from there is used to select
2617 * a frequency from the table starting at 'frequency 0' to be
2618 * programmed into the PLL corresponding to 'type'.
2619 *
2620 * The PLL limits table on cards using this opcode has a mapping of
2621 * 'type' to the relevant registers.
2622 */
2623
2624 struct drm_device *dev = bios->dev;
2625 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2626 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2627 uint8_t type = bios->data[offset + 1];
2628 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2629 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 2630 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 2631 int i;
2632
2633 if (!iexec->execute)
37383650 2634 return len;
6ee73861
BS		 2635
2636 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2637 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 2638 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 2639 }
2640
2641 entry = pll_limits + pll_limits[1];
2642 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2643 if (entry[0] == type) {
2644 uint32_t reg = ROM32(entry[3]);
2645
2646 BIOSLOG(bios, "0x%04X: "
2647 "Type %02x Reg 0x%08x Freq %dKHz\n",
2648 offset, type, reg, freq);
2649
2650 setPLL(bios, reg, freq);
37383650 2651 return len;
6ee73861
BS		 2652 }
2653 }
2654
2655 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 2656 return len;
6ee73861
BS		 2657}
2658
37383650 2659static int
6ee73861
BS		 2660init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2661{
2662 /*
2663 * INIT_8C opcode: 0x8C ('')
2664 *
2665 * NOP so far....
2666 *
2667 */
2668
37383650 2669 return 1;
6ee73861
BS		 2670}
2671
37383650 2672static int
6ee73861
BS		 2673init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2674{
2675 /*
2676 * INIT_8D opcode: 0x8D ('')
2677 *
2678 * NOP so far....
2679 *
2680 */
2681
37383650 2682 return 1;
6ee73861
BS		 2683}
2684
37383650 2685static int
6ee73861
BS		 2686init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2687{
2688 /*
2689 * INIT_GPIO opcode: 0x8E ('')
2690 *
2691 * offset (8 bit): opcode
2692 *
2693 * Loop over all entries in the DCB GPIO table, and initialise
2694 * each GPIO according to various values listed in each entry
2695 */
2696
2535d71c 2697 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
6ee73861 2698 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
6ee73861
BS		 2699 int i;
2700
2535d71c
BS		 2701 if (dev_priv->card_type != NV_50) {
2702 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
2703 return -ENODEV;
6ee73861
BS		 2704 }
2705
2535d71c
BS		 2706 if (!iexec->execute)
2707 return 1;
6ee73861 2708
2535d71c
BS		 2709 for (i = 0; i < bios->dcb.gpio.entries; i++) {
2710 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
2711 uint32_t r, s, v;
6ee73861 2712
2535d71c 2713 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 2714
45284162 2715 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default);
6ee73861 2716
45284162
BS		 2717 /* The NVIDIA binary driver doesn't appear to actually do
2718 * any of this, my VBIOS does however.
2719 */
2720 /* Not a clue, needs de-magicing */
2535d71c
BS		 2721 r = nv50_gpio_ctl[gpio->line >> 4];
2722 s = (gpio->line & 0x0f);
6ee73861 2723 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2535d71c 2724 switch ((gpio->entry & 0x06000000) >> 25) {
6ee73861
BS		 2725 case 1:
2726 v |= (0x00000001 << s);
2727 break;
2728 case 2:
2729 v |= (0x00010000 << s);
2730 break;
2731 default:
2732 break;
2733 }
2734 bios_wr32(bios, r, v);
2735 }
2736
37383650 2737 return 1;
6ee73861
BS		 2738}
2739
37383650 2740static int
6ee73861
BS		 2741init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2742 struct init_exec *iexec)
2743{
2744 /*
2745 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2746 *
2747 * offset (8 bit): opcode
2748 * offset + 1 (32 bit): reg
2749 * offset + 5 (8 bit): regincrement
2750 * offset + 6 (8 bit): count
2751 * offset + 7 (32 bit): value 1,1
2752 * ...
2753 *
2754 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2755 * ram_restrict_table_ptr. The value read from here is 'n', and
2756 * "value 1,n" gets written to "reg". This repeats "count" times and on
2757 * each iteration 'm', "reg" increases by "regincrement" and
2758 * "value m,n" is used. The extent of n is limited by a number read
2759 * from the 'M' BIT table, herein called "blocklen"
2760 */
2761
2762 uint32_t reg = ROM32(bios->data[offset + 1]);
2763 uint8_t regincrement = bios->data[offset + 5];
2764 uint8_t count = bios->data[offset + 6];
2765 uint32_t strap_ramcfg, data;
37383650
MK		 2766 /* previously set by 'M' BIT table */
2767 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2768 int len = 7 + count * blocklen;
6ee73861
BS		 2769 uint8_t index;
2770 int i;
2771
6ee73861
BS		 2772
2773 if (!iexec->execute)
37383650 2774 return len;
6ee73861
BS		 2775
2776 if (!blocklen) {
2777 NV_ERROR(bios->dev,
2778 "0x%04X: Zero block length - has the M table "
2779 "been parsed?\n", offset);
37383650 2780 return 0;
6ee73861
BS		 2781 }
2782
2783 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2784 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2785
2786 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2787 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2788 offset, reg, regincrement, count, strap_ramcfg, index);
2789
2790 for (i = 0; i < count; i++) {
2791 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2792
2793 bios_wr32(bios, reg, data);
2794
2795 reg += regincrement;
2796 }
2797
37383650 2798 return len;
6ee73861
BS		 2799}
2800
37383650 2801static int
6ee73861
BS		 2802init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2803{
2804 /*
2805 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2806 *
2807 * offset (8 bit): opcode
2808 * offset + 1 (32 bit): src reg
2809 * offset + 5 (32 bit): dst reg
2810 *
2811 * Put contents of "src reg" into "dst reg"
2812 */
2813
2814 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2815 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2816
2817 if (!iexec->execute)
37383650 2818 return 9;
6ee73861
BS		 2819
2820 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2821
37383650 2822 return 9;
6ee73861
BS		 2823}
2824
37383650 2825static int
6ee73861
BS		 2826init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2827 struct init_exec *iexec)
2828{
2829 /*
2830 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2831 *
2832 * offset (8 bit): opcode
2833 * offset + 1 (32 bit): dst reg
2834 * offset + 5 (8 bit): count
2835 * offset + 6 (32 bit): data 1
2836 * ...
2837 *
2838 * For each of "count" values write "data n" to "dst reg"
2839 */
2840
2841 uint32_t reg = ROM32(bios->data[offset + 1]);
2842 uint8_t count = bios->data[offset + 5];
37383650 2843 int len = 6 + count * 4;
6ee73861
BS		 2844 int i;
2845
2846 if (!iexec->execute)
37383650 2847 return len;
6ee73861
BS		 2848
2849 for (i = 0; i < count; i++) {
2850 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2851 bios_wr32(bios, reg, data);
2852 }
2853
37383650 2854 return len;
6ee73861
BS		 2855}
2856
37383650 2857static int
6ee73861
BS		 2858init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2859{
2860 /*
2861 * INIT_RESERVED opcode: 0x92 ('')
2862 *
2863 * offset (8 bit): opcode
2864 *
2865 * Seemingly does nothing
2866 */
2867
37383650 2868 return 1;
6ee73861
BS		 2869}
2870
37383650 2871static int
6ee73861
BS		 2872init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2873{
2874 /*
2875 * INIT_96 opcode: 0x96 ('')
2876 *
2877 * offset (8 bit): opcode
2878 * offset + 1 (32 bit): sreg
2879 * offset + 5 (8 bit): sshift
2880 * offset + 6 (8 bit): smask
2881 * offset + 7 (8 bit): index
2882 * offset + 8 (32 bit): reg
2883 * offset + 12 (32 bit): mask
2884 * offset + 16 (8 bit): shift
2885 *
2886 */
2887
2888 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2889 uint32_t reg = ROM32(bios->data[offset + 8]);
2890 uint32_t mask = ROM32(bios->data[offset + 12]);
2891 uint32_t val;
2892
2893 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2894 if (bios->data[offset + 5] < 0x80)
2895 val >>= bios->data[offset + 5];
2896 else
2897 val <<= (0x100 - bios->data[offset + 5]);
2898 val &= bios->data[offset + 6];
2899
2900 val = bios->data[ROM16(bios->data[xlatptr]) + val];
2901 val <<= bios->data[offset + 16];
2902
2903 if (!iexec->execute)
37383650 2904 return 17;
6ee73861
BS		 2905
2906 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 2907 return 17;
6ee73861
BS		 2908}
2909
37383650 2910static int
6ee73861
BS		 2911init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2912{
2913 /*
2914 * INIT_97 opcode: 0x97 ('')
2915 *
2916 * offset (8 bit): opcode
2917 * offset + 1 (32 bit): register
2918 * offset + 5 (32 bit): mask
2919 * offset + 9 (32 bit): value
2920 *
2921 * Adds "value" to "register" preserving the fields specified
2922 * by "mask"
2923 */
2924
2925 uint32_t reg = ROM32(bios->data[offset + 1]);
2926 uint32_t mask = ROM32(bios->data[offset + 5]);
2927 uint32_t add = ROM32(bios->data[offset + 9]);
2928 uint32_t val;
2929
2930 val = bios_rd32(bios, reg);
2931 val = (val & mask) | ((val + add) & ~mask);
2932
2933 if (!iexec->execute)
37383650 2934 return 13;
6ee73861
BS		 2935
2936 bios_wr32(bios, reg, val);
37383650 2937 return 13;
6ee73861
BS		 2938}
2939
37383650 2940static int
6ee73861
BS		 2941init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2942{
2943 /*
2944 * INIT_AUXCH opcode: 0x98 ('')
2945 *
2946 * offset (8 bit): opcode
2947 * offset + 1 (32 bit): address
2948 * offset + 5 (8 bit): count
2949 * offset + 6 (8 bit): mask 0
2950 * offset + 7 (8 bit): data 0
2951 * ...
2952 *
2953 */
2954
2955 struct drm_device *dev = bios->dev;
2956 struct nouveau_i2c_chan *auxch;
2957 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 2958 uint8_t count = bios->data[offset + 5];
2959 int len = 6 + count * 2;
6ee73861
BS		 2960 int ret, i;
2961
2962 if (!bios->display.output) {
2963 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
37383650 2964 return 0;
6ee73861
BS		 2965 }
2966
2967 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2968 if (!auxch) {
2969 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
2970 bios->display.output->i2c_index);
37383650 2971 return 0;
6ee73861
BS		 2972 }
2973
2974 if (!iexec->execute)
37383650 2975 return len;
6ee73861
BS		 2976
2977 offset += 6;
37383650 2978 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 2979 uint8_t data;
2980
2981 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
2982 if (ret) {
2983 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
37383650 2984 return 0;
6ee73861
BS		 2985 }
2986
2987 data &= bios->data[offset + 0];
2988 data |= bios->data[offset + 1];
2989
2990 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
2991 if (ret) {
2992 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
37383650 2993 return 0;
6ee73861
BS		 2994 }
2995 }
2996
37383650 2997 return len;
6ee73861
BS		 2998}
2999
37383650 3000static int
6ee73861
BS		 3001init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3002{
3003 /*
3004 * INIT_ZM_AUXCH opcode: 0x99 ('')
3005 *
3006 * offset (8 bit): opcode
3007 * offset + 1 (32 bit): address
3008 * offset + 5 (8 bit): count
3009 * offset + 6 (8 bit): data 0
3010 * ...
3011 *
3012 */
3013
3014 struct drm_device *dev = bios->dev;
3015 struct nouveau_i2c_chan *auxch;
3016 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3017 uint8_t count = bios->data[offset + 5];
3018 int len = 6 + count;
6ee73861
BS		 3019 int ret, i;
3020
3021 if (!bios->display.output) {
3022 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
37383650 3023 return 0;
6ee73861
BS		 3024 }
3025
3026 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3027 if (!auxch) {
3028 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3029 bios->display.output->i2c_index);
37383650 3030 return 0;
6ee73861
BS		 3031 }
3032
3033 if (!iexec->execute)
37383650 3034 return len;
6ee73861
BS		 3035
3036 offset += 6;
37383650 3037 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3038 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3039 if (ret) {
3040 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
37383650 3041 return 0;
6ee73861
BS		 3042 }
3043 }
3044
37383650 3045 return len;
6ee73861
BS		 3046}
3047
3048static struct init_tbl_entry itbl_entry[] = {
3049 /* command name , id , length , offset , mult , command handler */
3050 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3051 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3052 { "INIT_REPEAT" , 0x33, init_repeat },
3053 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3054 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3055 { "INIT_COPY" , 0x37, init_copy },
3056 { "INIT_NOT" , 0x38, init_not },
3057 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3058 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3059 { "INIT_OP_3B" , 0x3B, init_op_3b },
3060 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3061 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3062 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3063 { "INIT_PLL2" , 0x4B, init_pll2 },
3064 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3065 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3066 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3067 { "INIT_TMDS" , 0x4F, init_tmds },
3068 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3069 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3070 { "INIT_CR" , 0x52, init_cr },
3071 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3072 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3073 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3074 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3075 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 3076 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3077 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3078 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3079 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3080 { "INIT_RESET" , 0x65, init_reset },
3081 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3082 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3083 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3084 { "INIT_IO" , 0x69, init_io },
3085 { "INIT_SUB" , 0x6B, init_sub },
3086 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3087 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3088 { "INIT_MACRO" , 0x6F, init_macro },
3089 { "INIT_DONE" , 0x71, init_done },
3090 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3091 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3092 { "INIT_TIME" , 0x74, init_time },
3093 { "INIT_CONDITION" , 0x75, init_condition },
3094 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3095 { "INIT_INDEX_IO" , 0x78, init_index_io },
3096 { "INIT_PLL" , 0x79, init_pll },
3097 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3098 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3099 { "INIT_8C" , 0x8C, init_8c },
3100 { "INIT_8D" , 0x8D, init_8d },
3101 { "INIT_GPIO" , 0x8E, init_gpio },
3102 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3103 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3104 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3105 { "INIT_RESERVED" , 0x92, init_reserved },
3106 { "INIT_96" , 0x96, init_96 },
3107 { "INIT_97" , 0x97, init_97 },
3108 { "INIT_AUXCH" , 0x98, init_auxch },
3109 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3110 { NULL , 0 , NULL }
6ee73861
BS		 3111};
3112
6ee73861
BS		 3113#define MAX_TABLE_OPS 1000
3114
3115static int
3116parse_init_table(struct nvbios *bios, unsigned int offset,
3117 struct init_exec *iexec)
3118{
3119 /*
3120 * Parses all commands in an init table.
3121 *
3122 * We start out executing all commands found in the init table. Some
3123 * opcodes may change the status of iexec->execute to SKIP, which will
3124 * cause the following opcodes to perform no operation until the value
3125 * is changed back to EXECUTE.
3126 */
3127
37383650 3128 int count = 0, i, res;
6ee73861
BS		 3129 uint8_t id;
3130
3131 /*
3132 * Loop until INIT_DONE causes us to break out of the loop
3133 * (or until offset > bios length just in case... )
3134 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3135 */
3136 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3137 id = bios->data[offset];
3138
3139 /* Find matching id in itbl_entry */
3140 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3141 ;
3142
3143 if (itbl_entry[i].name) {
3144 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n",
3145 offset, itbl_entry[i].id, itbl_entry[i].name);
3146
3147 /* execute eventual command handler */
37383650
MK		 3148 res = (*itbl_entry[i].handler)(bios, offset, iexec);
3149 if (!res)
3150 break;
3151 /*
3152 * Add the offset of the current command including all data
3153 * of that command. The offset will then be pointing on the
3154 * next op code.
3155 */
3156 offset += res;
6ee73861
BS		 3157 } else {
3158 NV_ERROR(bios->dev,
3159 "0x%04X: Init table command not found: "
3160 "0x%02X\n", offset, id);
3161 return -ENOENT;
3162 }
6ee73861
BS		 3163 }
3164
3165 if (offset >= bios->length)
3166 NV_WARN(bios->dev,
3167 "Offset 0x%04X greater than known bios image length. "
3168 "Corrupt image?\n", offset);
3169 if (count >= MAX_TABLE_OPS)
3170 NV_WARN(bios->dev,
3171 "More than %d opcodes to a table is unlikely, "
3172 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3173
3174 return 0;
3175}
3176
3177static void
3178parse_init_tables(struct nvbios *bios)
3179{
3180 /* Loops and calls parse_init_table() for each present table. */
3181
3182 int i = 0;
3183 uint16_t table;
3184 struct init_exec iexec = {true, false};
3185
3186 if (bios->old_style_init) {
3187 if (bios->init_script_tbls_ptr)
3188 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3189 if (bios->extra_init_script_tbl_ptr)
3190 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3191
3192 return;
3193 }
3194
3195 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3196 NV_INFO(bios->dev,
3197 "Parsing VBIOS init table %d at offset 0x%04X\n",
3198 i / 2, table);
3199 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3200
3201 parse_init_table(bios, table, &iexec);
3202 i += 2;
3203 }
3204}
3205
3206static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3207{
3208 int compare_record_len, i = 0;
3209 uint16_t compareclk, scriptptr = 0;
3210
3211 if (bios->major_version < 5) /* pre BIT */
3212 compare_record_len = 3;
3213 else
3214 compare_record_len = 4;
3215
3216 do {
3217 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3218 if (pxclk >= compareclk * 10) {
3219 if (bios->major_version < 5) {
3220 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3221 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3222 } else
3223 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3224 break;
3225 }
3226 i++;
3227 } while (compareclk);
3228
3229 return scriptptr;
3230}
3231
3232static void
3233run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3234 struct dcb_entry *dcbent, int head, bool dl)
3235{
3236 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3237 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3238 struct init_exec iexec = {true, false};
3239
3240 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3241 scriptptr);
3242 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3243 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3244 /* note: if dcb entries have been merged, index may be misleading */
3245 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3246 parse_init_table(bios, scriptptr, &iexec);
3247
3248 nv04_dfp_bind_head(dev, dcbent, head, dl);
3249}
3250
3251static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3252{
3253 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3254 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3255 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3256 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3257
3258 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3259 return -EINVAL;
3260
3261 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3262
3263 if (script == LVDS_PANEL_OFF) {
3264 /* off-on delay in ms */
3265 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3266 }
3267#ifdef __powerpc__
3268 /* Powerbook specific quirks */
3d9aefb8
FJ		 3269 if ((dev->pci_device & 0xffff) == 0x0179 ||
3270 (dev->pci_device & 0xffff) == 0x0189 ||
3271 (dev->pci_device & 0xffff) == 0x0329) {
3272 if (script == LVDS_RESET) {
3273 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3274
3275 } else if (script == LVDS_PANEL_ON) {
3276 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3277 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3278 | (1 << 31));
3279 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3280 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3281
3282 } else if (script == LVDS_PANEL_OFF) {
3283 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3284 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3285 & ~(1 << 31));
3286 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3287 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3288 }
3289 }
3290#endif
3291
3292 return 0;
3293}
3294
3295static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3296{
3297 /*
3298 * The BIT LVDS table's header has the information to setup the
3299 * necessary registers. Following the standard 4 byte header are:
3300 * A bitmask byte and a dual-link transition pxclk value for use in
3301 * selecting the init script when not using straps; 4 script pointers
3302 * for panel power, selected by output and on/off; and 8 table pointers
3303 * for panel init, the needed one determined by output, and bits in the
3304 * conf byte. These tables are similar to the TMDS tables, consisting
3305 * of a list of pxclks and script pointers.
3306 */
3307 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3308 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3309 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3310 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3311
3312 /*
3313 * For now we assume version 3.0 table - g80 support will need some
3314 * changes
3315 */
3316
3317 switch (script) {
3318 case LVDS_INIT:
3319 return -ENOSYS;
3320 case LVDS_BACKLIGHT_ON:
3321 case LVDS_PANEL_ON:
3322 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3323 break;
3324 case LVDS_BACKLIGHT_OFF:
3325 case LVDS_PANEL_OFF:
3326 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3327 break;
3328 case LVDS_RESET:
f3bbb9cc
BS		 3329 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3330 if (dcbent->or == 4)
3331 clktable += 8;
3332
6ee73861
BS		 3333 if (dcbent->lvdsconf.use_straps_for_mode) {
3334 if (bios->fp.dual_link)
f3bbb9cc
BS		 3335 clktable += 4;
3336 if (bios->fp.if_is_24bit)
3337 clktable += 2;
6ee73861
BS		 3338 } else {
3339 /* using EDID */
f3bbb9cc 3340 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3341
3342 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3343 clktable += 4;
3344 cmpval_24bit <<= 1;
6ee73861 3345 }
f3bbb9cc
BS		 3346
3347 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3348 clktable += 2;
6ee73861
BS		 3349 }
3350
f3bbb9cc 3351 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3352 if (!clktable) {
3353 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3354 return -ENOENT;
3355 }
3356 scriptptr = clkcmptable(bios, clktable, pxclk);
3357 }
3358
3359 if (!scriptptr) {
3360 NV_ERROR(dev, "LVDS output init script not found\n");
3361 return -ENOENT;
3362 }
3363 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3364
3365 return 0;
3366}
3367
3368int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3369{
3370 /*
3371 * LVDS operations are multiplexed in an effort to present a single API
3372 * which works with two vastly differing underlying structures.
3373 * This acts as the demux
3374 */
3375
3376 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3377 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3378 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3379 uint32_t sel_clk_binding, sel_clk;
3380 int ret;
3381
3382 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3383 (lvds_ver >= 0x30 && script == LVDS_INIT))
3384 return 0;
3385
3386 if (!bios->fp.lvds_init_run) {
3387 bios->fp.lvds_init_run = true;
3388 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3389 }
3390
3391 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3392 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3393 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3394 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3395
3396 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3397
3398 /* don't let script change pll->head binding */
3399 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3400
3401 if (lvds_ver < 0x30)
3402 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3403 else
3404 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3405
3406 bios->fp.last_script_invoc = (script << 1 | head);
3407
3408 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3409 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3410 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3411 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3412
3413 return ret;
3414}
3415
3416struct lvdstableheader {
3417 uint8_t lvds_ver, headerlen, recordlen;
3418};
3419
3420static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3421{
3422 /*
3423 * BMP version (0xa) LVDS table has a simple header of version and
3424 * record length. The BIT LVDS table has the typical BIT table header:
3425 * version byte, header length byte, record length byte, and a byte for
3426 * the maximum number of records that can be held in the table.
3427 */
3428
3429 uint8_t lvds_ver, headerlen, recordlen;
3430
3431 memset(lth, 0, sizeof(struct lvdstableheader));
3432
3433 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3434 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3435 return -EINVAL;
3436 }
3437
3438 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3439
3440 switch (lvds_ver) {
3441 case 0x0a: /* pre NV40 */
3442 headerlen = 2;
3443 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3444 break;
3445 case 0x30: /* NV4x */
3446 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3447 if (headerlen < 0x1f) {
3448 NV_ERROR(dev, "LVDS table header not understood\n");
3449 return -EINVAL;
3450 }
3451 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3452 break;
3453 case 0x40: /* G80/G90 */
3454 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3455 if (headerlen < 0x7) {
3456 NV_ERROR(dev, "LVDS table header not understood\n");
3457 return -EINVAL;
3458 }
3459 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3460 break;
3461 default:
3462 NV_ERROR(dev,
3463 "LVDS table revision %d.%d not currently supported\n",
3464 lvds_ver >> 4, lvds_ver & 0xf);
3465 return -ENOSYS;
3466 }
3467
3468 lth->lvds_ver = lvds_ver;
3469 lth->headerlen = headerlen;
3470 lth->recordlen = recordlen;
3471
3472 return 0;
3473}
3474
3475static int
3476get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3477{
3478 struct drm_nouveau_private *dev_priv = dev->dev_private;
3479
3480 /*
3481 * The fp strap is normally dictated by the "User Strap" in
3482 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3483 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3484 * by the PCI subsystem ID during POST, but not before the previous user
3485 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3486 * read and used instead
3487 */
3488
3489 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3490 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3491
3492 if (dev_priv->card_type >= NV_50)
3493 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3494 else
3495 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3496}
3497
3498static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3499{
3500 uint8_t *fptable;
3501 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3502 int ret, ofs, fpstrapping;
3503 struct lvdstableheader lth;
3504
3505 if (bios->fp.fptablepointer == 0x0) {
3506 /* Apple cards don't have the fp table; the laptops use DDC */
3507 /* The table is also missing on some x86 IGPs */
3508#ifndef __powerpc__
3509 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3510#endif
04a39c57 3511 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3512 return 0;
3513 }
3514
3515 fptable = &bios->data[bios->fp.fptablepointer];
3516 fptable_ver = fptable[0];
3517
3518 switch (fptable_ver) {
3519 /*
3520 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3521 * version field, and miss one of the spread spectrum/PWM bytes.
3522 * This could affect early GF2Go parts (not seen any appropriate ROMs
3523 * though). Here we assume that a version of 0x05 matches this case
3524 * (combining with a BMP version check would be better), as the
3525 * common case for the panel type field is 0x0005, and that is in
3526 * fact what we are reading the first byte of.
3527 */
3528 case 0x05: /* some NV10, 11, 15, 16 */
3529 recordlen = 42;
3530 ofs = -1;
3531 break;
3532 case 0x10: /* some NV15/16, and NV11+ */
3533 recordlen = 44;
3534 ofs = 0;
3535 break;
3536 case 0x20: /* NV40+ */
3537 headerlen = fptable[1];
3538 recordlen = fptable[2];
3539 fpentries = fptable[3];
3540 /*
3541 * fptable[4] is the minimum
3542 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3543 */
04a39c57 3544 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 3545 ofs = -7;
3546 break;
3547 default:
3548 NV_ERROR(dev,
3549 "FP table revision %d.%d not currently supported\n",
3550 fptable_ver >> 4, fptable_ver & 0xf);
3551 return -ENOSYS;
3552 }
3553
3554 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3555 return 0;
3556
3557 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3558 if (ret)
3559 return ret;
3560
3561 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3562 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3563 lth.headerlen + 1;
3564 bios->fp.xlatwidth = lth.recordlen;
3565 }
3566 if (bios->fp.fpxlatetableptr == 0x0) {
3567 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3568 return -EINVAL;
3569 }
3570
3571 fpstrapping = get_fp_strap(dev, bios);
3572
3573 fpindex = bios->data[bios->fp.fpxlatetableptr +
3574 fpstrapping * bios->fp.xlatwidth];
3575
3576 if (fpindex > fpentries) {
3577 NV_ERROR(dev, "Bad flat panel table index\n");
3578 return -ENOENT;
3579 }
3580
3581 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3582 if (lth.lvds_ver > 0x10)
04a39c57 3583 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 3584
3585 /*
3586 * If either the strap or xlated fpindex value are 0xf there is no
3587 * panel using a strap-derived bios mode present. this condition
3588 * includes, but is different from, the DDC panel indicator above
3589 */
3590 if (fpstrapping == 0xf || fpindex == 0xf)
3591 return 0;
3592
3593 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3594 recordlen * fpindex + ofs;
3595
3596 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3597 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3598 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3599 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3600
3601 return 0;
3602}
3603
3604bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3605{
3606 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3607 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3608 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3609
3610 if (!mode) /* just checking whether we can produce a mode */
3611 return bios->fp.mode_ptr;
3612
3613 memset(mode, 0, sizeof(struct drm_display_mode));
3614 /*
3615 * For version 1.0 (version in byte 0):
3616 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3617 * single/dual link, and type (TFT etc.)
3618 * bytes 3-6 are bits per colour in RGBX
3619 */
3620 mode->clock = ROM16(mode_entry[7]) * 10;
3621 /* bytes 9-10 is HActive */
3622 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3623 /*
3624 * bytes 13-14 is HValid Start
3625 * bytes 15-16 is HValid End
3626 */
3627 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3628 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3629 mode->htotal = ROM16(mode_entry[21]) + 1;
3630 /* bytes 23-24, 27-30 similarly, but vertical */
3631 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3632 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3633 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3634 mode->vtotal = ROM16(mode_entry[35]) + 1;
3635 mode->flags |= (mode_entry[37] & 0x10) ?
3636 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3637 mode->flags |= (mode_entry[37] & 0x1) ?
3638 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3639 /*
3640 * bytes 38-39 relate to spread spectrum settings
3641 * bytes 40-43 are something to do with PWM
3642 */
3643
3644 mode->status = MODE_OK;
3645 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3646 drm_mode_set_name(mode);
3647 return bios->fp.mode_ptr;
3648}
3649
3650int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3651{
3652 /*
3653 * The LVDS table header is (mostly) described in
3654 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3655 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3656 * straps are not being used for the panel, this specifies the frequency
3657 * at which modes should be set up in the dual link style.
3658 *
3659 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 3660 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 3661 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3662 * numbers for use by INIT_SUB which controlled panel init and power,
3663 * and finally a dword of ms to sleep between power off and on
3664 * operations.
3665 *
3666 * In the BIT versions, the table following the header serves as an
3667 * integrated config and xlat table: the records in the table are
3668 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3669 * two bytes - the first as a config byte, the second for indexing the
3670 * fp mode table pointed to by the BIT 'D' table
3671 *
3672 * DDC is not used until after card init, so selecting the correct table
3673 * entry and setting the dual link flag for EDID equipped panels,
3674 * requiring tests against the native-mode pixel clock, cannot be done
3675 * until later, when this function should be called with non-zero pxclk
3676 */
3677 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3678 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3679 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3680 struct lvdstableheader lth;
3681 uint16_t lvdsofs;
04a39c57 3682 int ret, chip_version = bios->chip_version;
6ee73861
BS		 3683
3684 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3685 if (ret)
3686 return ret;
3687
3688 switch (lth.lvds_ver) {
3689 case 0x0a: /* pre NV40 */
3690 lvdsmanufacturerindex = bios->data[
3691 bios->fp.fpxlatemanufacturertableptr +
3692 fpstrapping];
3693
3694 /* we're done if this isn't the EDID panel case */
3695 if (!pxclk)
3696 break;
3697
3698 if (chip_version < 0x25) {
3699 /* nv17 behaviour
3700 *
3701 * It seems the old style lvds script pointer is reused
3702 * to select 18/24 bit colour depth for EDID panels.
3703 */
3704 lvdsmanufacturerindex =
3705 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3706 2 : 0;
3707 if (pxclk >= bios->fp.duallink_transition_clk)
3708 lvdsmanufacturerindex++;
3709 } else if (chip_version < 0x30) {
3710 /* nv28 behaviour (off-chip encoder)
3711 *
3712 * nv28 does a complex dance of first using byte 121 of
3713 * the EDID to choose the lvdsmanufacturerindex, then
3714 * later attempting to match the EDID manufacturer and
3715 * product IDs in a table (signature 'pidt' (panel id
3716 * table?)), setting an lvdsmanufacturerindex of 0 and
3717 * an fp strap of the match index (or 0xf if none)
3718 */
3719 lvdsmanufacturerindex = 0;
3720 } else {
3721 /* nv31, nv34 behaviour */
3722 lvdsmanufacturerindex = 0;
3723 if (pxclk >= bios->fp.duallink_transition_clk)
3724 lvdsmanufacturerindex = 2;
3725 if (pxclk >= 140000)
3726 lvdsmanufacturerindex = 3;
3727 }
3728
3729 /*
3730 * nvidia set the high nibble of (cr57=f, cr58) to
3731 * lvdsmanufacturerindex in this case; we don't
3732 */
3733 break;
3734 case 0x30: /* NV4x */
3735 case 0x40: /* G80/G90 */
3736 lvdsmanufacturerindex = fpstrapping;
3737 break;
3738 default:
3739 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3740 return -ENOSYS;
3741 }
3742
3743 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3744 switch (lth.lvds_ver) {
3745 case 0x0a:
3746 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3747 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3748 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3749 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3750 *if_is_24bit = bios->data[lvdsofs] & 16;
3751 break;
3752 case 0x30:
f3bbb9cc 3753 case 0x40:
6ee73861
BS		 3754 /*
3755 * No sign of the "power off for reset" or "reset for panel
3756 * on" bits, but it's safer to assume we should
3757 */
3758 bios->fp.power_off_for_reset = true;
3759 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 3760
6ee73861
BS		 3761 /*
3762 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 3763 * over-written, and if_is_24bit isn't used
6ee73861
BS		 3764 */
3765 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 3766 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3767 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3768 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3769 break;
3770 }
3771
2eb92c80
BS		 3772 /* Dell Latitude D620 reports a too-high value for the dual-link
3773 * transition freq, causing us to program the panel incorrectly.
3774 *
3775 * It doesn't appear the VBIOS actually uses its transition freq
3776 * (90000kHz), instead it uses the "Number of LVDS channels" field
3777 * out of the panel ID structure (http://www.spwg.org/).
3778 *
3779 * For the moment, a quirk will do :)
3780 */
3781 if ((dev->pdev->device == 0x01d7) &&
3782 (dev->pdev->subsystem_vendor == 0x1028) &&
3783 (dev->pdev->subsystem_device == 0x01c2)) {
3784 bios->fp.duallink_transition_clk = 80000;
3785 }
3786
6ee73861
BS		 3787 /* set dual_link flag for EDID case */
3788 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3789 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3790
3791 *dl = bios->fp.dual_link;
3792
3793 return 0;
3794}
3795
3796static uint8_t *
3797bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3798 uint16_t record, int record_len, int record_nr)
3799{
3800 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3801 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3802 uint32_t entry;
3803 uint16_t table;
3804 int i, v;
3805
3806 for (i = 0; i < record_nr; i++, record += record_len) {
3807 table = ROM16(bios->data[record]);
3808 if (!table)
3809 continue;
3810 entry = ROM32(bios->data[table]);
3811
3812 v = (entry & 0x000f0000) >> 16;
3813 if (!(v & dcbent->or))
3814 continue;
3815
3816 v = (entry & 0x000000f0) >> 4;
3817 if (v != dcbent->location)
3818 continue;
3819
3820 v = (entry & 0x0000000f);
3821 if (v != dcbent->type)
3822 continue;
3823
3824 return &bios->data[table];
3825 }
3826
3827 return NULL;
3828}
3829
3830void *
3831nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3832 int *length)
3833{
3834 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3835 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3836 uint8_t *table;
3837
3838 if (!bios->display.dp_table_ptr) {
3839 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3840 return NULL;
3841 }
3842 table = &bios->data[bios->display.dp_table_ptr];
3843
c52e53fd 3844 if (table[0] != 0x20 && table[0] != 0x21) {
6ee73861
BS		 3845 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3846 table[0]);
3847 return NULL;
3848 }
3849
3850 *length = table[4];
3851 return bios_output_config_match(dev, dcbent,
3852 bios->display.dp_table_ptr + table[1],
3853 table[2], table[3]);
3854}
3855
3856int
3857nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3858 uint32_t sub, int pxclk)
3859{
3860 /*
3861 * The display script table is located by the BIT 'U' table.
3862 *
3863 * It contains an array of pointers to various tables describing
3864 * a particular output type. The first 32-bits of the output
3865 * tables contains similar information to a DCB entry, and is
3866 * used to decide whether that particular table is suitable for
3867 * the output you want to access.
3868 *
3869 * The "record header length" field here seems to indicate the
3870 * offset of the first configuration entry in the output tables.
3871 * This is 10 on most cards I've seen, but 12 has been witnessed
3872 * on DP cards, and there's another script pointer within the
3873 * header.
3874 *
3875 * offset + 0 ( 8 bits): version
3876 * offset + 1 ( 8 bits): header length
3877 * offset + 2 ( 8 bits): record length
3878 * offset + 3 ( 8 bits): number of records
3879 * offset + 4 ( 8 bits): record header length
3880 * offset + 5 (16 bits): pointer to first output script table
3881 */
3882
3883 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3884 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3885 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3886 uint8_t *otable = NULL;
3887 uint16_t script;
3888 int i = 0;
3889
3890 if (!bios->display.script_table_ptr) {
3891 NV_ERROR(dev, "No pointer to output script table\n");
3892 return 1;
3893 }
3894
3895 /*
3896 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3897 * so until they are, we really don't need to care.
3898 */
3899 if (table[0] < 0x20)
3900 return 1;
3901
3902 if (table[0] != 0x20 && table[0] != 0x21) {
3903 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
3904 table[0]);
3905 return 1;
3906 }
3907
3908 /*
3909 * The output script tables describing a particular output type
3910 * look as follows:
3911 *
3912 * offset + 0 (32 bits): output this table matches (hash of DCB)
3913 * offset + 4 ( 8 bits): unknown
3914 * offset + 5 ( 8 bits): number of configurations
3915 * offset + 6 (16 bits): pointer to some script
3916 * offset + 8 (16 bits): pointer to some script
3917 *
3918 * headerlen == 10
3919 * offset + 10 : configuration 0
3920 *
3921 * headerlen == 12
3922 * offset + 10 : pointer to some script
3923 * offset + 12 : configuration 0
3924 *
3925 * Each config entry is as follows:
3926 *
3927 * offset + 0 (16 bits): unknown, assumed to be a match value
3928 * offset + 2 (16 bits): pointer to script table (clock set?)
3929 * offset + 4 (16 bits): pointer to script table (reset?)
3930 *
3931 * There doesn't appear to be a count value to say how many
3932 * entries exist in each script table, instead, a 0 value in
3933 * the first 16-bit word seems to indicate both the end of the
3934 * list and the default entry. The second 16-bit word in the
3935 * script tables is a pointer to the script to execute.
3936 */
3937
ef2bb506 3938 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 3939 dcbent->type, dcbent->location, dcbent->or);
3940 otable = bios_output_config_match(dev, dcbent, table[1] +
3941 bios->display.script_table_ptr,
3942 table[2], table[3]);
3943 if (!otable) {
3944 NV_ERROR(dev, "Couldn't find matching output script table\n");
3945 return 1;
3946 }
3947
3948 if (pxclk < -2 || pxclk > 0) {
3949 /* Try to find matching script table entry */
3950 for (i = 0; i < otable[5]; i++) {
3951 if (ROM16(otable[table[4] + i*6]) == sub)
3952 break;
3953 }
3954
3955 if (i == otable[5]) {
3956 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
3957 "using first\n",
3958 sub, dcbent->type, dcbent->or);
3959 i = 0;
3960 }
3961 }
3962
6ee73861
BS		 3963 if (pxclk == 0) {
3964 script = ROM16(otable[6]);
3965 if (!script) {
ef2bb506 3966 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 3967 return 1;
3968 }
3969
3970 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 3971 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3972 } else
3973 if (pxclk == -1) {
3974 script = ROM16(otable[8]);
3975 if (!script) {
ef2bb506 3976 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 3977 return 1;
3978 }
3979
3980 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 3981 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3982 } else
3983 if (pxclk == -2) {
3984 if (table[4] >= 12)
3985 script = ROM16(otable[10]);
3986 else
3987 script = 0;
3988 if (!script) {
ef2bb506 3989 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 3990 return 1;
3991 }
3992
3993 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 3994 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3995 } else
3996 if (pxclk > 0) {
3997 script = ROM16(otable[table[4] + i*6 + 2]);
3998 if (script)
3999 script = clkcmptable(bios, script, pxclk);
4000 if (!script) {
4001 NV_ERROR(dev, "clock script 0 not found\n");
4002 return 1;
4003 }
4004
4005 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 4006 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4007 } else
4008 if (pxclk < 0) {
4009 script = ROM16(otable[table[4] + i*6 + 4]);
4010 if (script)
4011 script = clkcmptable(bios, script, -pxclk);
4012 if (!script) {
ef2bb506 4013 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4014 return 1;
4015 }
4016
4017 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 4018 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4019 }
4020
4021 return 0;
4022}
4023
4024
4025int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4026{
4027 /*
4028 * the pxclk parameter is in kHz
4029 *
4030 * This runs the TMDS regs setting code found on BIT bios cards
4031 *
4032 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4033 * ffs(or) == 3, use the second.
4034 */
4035
4036 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4037 struct nvbios *bios = &dev_priv->vbios;
4038 int cv = bios->chip_version;
6ee73861
BS		 4039 uint16_t clktable = 0, scriptptr;
4040 uint32_t sel_clk_binding, sel_clk;
4041
4042 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4043 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4044 dcbent->location != DCB_LOC_ON_CHIP)
4045 return 0;
4046
4047 switch (ffs(dcbent->or)) {
4048 case 1:
4049 clktable = bios->tmds.output0_script_ptr;
4050 break;
4051 case 2:
4052 case 3:
4053 clktable = bios->tmds.output1_script_ptr;
4054 break;
4055 }
4056
4057 if (!clktable) {
4058 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4059 return -EINVAL;
4060 }
4061
4062 scriptptr = clkcmptable(bios, clktable, pxclk);
4063
4064 if (!scriptptr) {
4065 NV_ERROR(dev, "TMDS output init script not found\n");
4066 return -ENOENT;
4067 }
4068
4069 /* don't let script change pll->head binding */
4070 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4071 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4072 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4073 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4074
4075 return 0;
4076}
4077
4078int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4079{
4080 /*
4081 * PLL limits table
4082 *
4083 * Version 0x10: NV30, NV31
4084 * One byte header (version), one record of 24 bytes
4085 * Version 0x11: NV36 - Not implemented
4086 * Seems to have same record style as 0x10, but 3 records rather than 1
4087 * Version 0x20: Found on Geforce 6 cards
4088 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4089 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4090 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4091 * length in general, some (integrated) have an extra configuration byte
4092 * Version 0x30: Found on Geforce 8, separates the register mapping
4093 * from the limits tables.
4094 */
4095
4096 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4097 struct nvbios *bios = &dev_priv->vbios;
4098 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4099 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4100 uint32_t crystal_strap_mask, crystal_straps;
4101
4102 if (!bios->pll_limit_tbl_ptr) {
4103 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4104 cv >= 0x40) {
4105 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4106 return -EINVAL;
4107 }
4108 } else
4109 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4110
4111 crystal_strap_mask = 1 << 6;
4112 /* open coded dev->twoHeads test */
4113 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4114 crystal_strap_mask |= 1 << 22;
4115 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4116 crystal_strap_mask;
4117
4118 switch (pll_lim_ver) {
4119 /*
4120 * We use version 0 to indicate a pre limit table bios (single stage
4121 * pll) and load the hard coded limits instead.
4122 */
4123 case 0:
4124 break;
4125 case 0x10:
4126 case 0x11:
4127 /*
4128 * Strictly v0x11 has 3 entries, but the last two don't seem
4129 * to get used.
4130 */
4131 headerlen = 1;
4132 recordlen = 0x18;
4133 entries = 1;
4134 pllindex = 0;
4135 break;
4136 case 0x20:
4137 case 0x21:
4138 case 0x30:
4139 case 0x40:
4140 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4141 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4142 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4143 break;
4144 default:
4145 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4146 "supported\n", pll_lim_ver);
4147 return -ENOSYS;
4148 }
4149
4150 /* initialize all members to zero */
4151 memset(pll_lim, 0, sizeof(struct pll_lims));
4152
4153 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4154 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4155
4156 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4157 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4158 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4159 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4160 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4161 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4162 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4163
4164 /* these values taken from nv30/31/36 */
4165 pll_lim->vco1.min_n = 0x1;
4166 if (cv == 0x36)
4167 pll_lim->vco1.min_n = 0x5;
4168 pll_lim->vco1.max_n = 0xff;
4169 pll_lim->vco1.min_m = 0x1;
4170 pll_lim->vco1.max_m = 0xd;
4171 pll_lim->vco2.min_n = 0x4;
4172 /*
4173 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4174 * table version (apart from nv35)), N2 is compared to
4175 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4176 * save a comparison
4177 */
4178 pll_lim->vco2.max_n = 0x28;
4179 if (cv == 0x30 || cv == 0x35)
4180 /* only 5 bits available for N2 on nv30/35 */
4181 pll_lim->vco2.max_n = 0x1f;
4182 pll_lim->vco2.min_m = 0x1;
4183 pll_lim->vco2.max_m = 0x4;
4184 pll_lim->max_log2p = 0x7;
4185 pll_lim->max_usable_log2p = 0x6;
4186 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4187 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4188 uint32_t reg = 0; /* default match */
4189 uint8_t *pll_rec;
4190 int i;
4191
4192 /*
4193 * First entry is default match, if nothing better. warn if
4194 * reg field nonzero
4195 */
4196 if (ROM32(bios->data[plloffs]))
4197 NV_WARN(dev, "Default PLL limit entry has non-zero "
4198 "register field\n");
4199
4200 if (limit_match > MAX_PLL_TYPES)
4201 /* we've been passed a reg as the match */
4202 reg = limit_match;
4203 else /* limit match is a pll type */
4204 for (i = 1; i < entries && !reg; i++) {
4205 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4206
4207 if (limit_match == NVPLL &&
4208 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4209 reg = cmpreg;
4210 if (limit_match == MPLL &&
4211 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4212 reg = cmpreg;
4213 if (limit_match == VPLL1 &&
4214 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4215 reg = cmpreg;
4216 if (limit_match == VPLL2 &&
4217 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4218 reg = cmpreg;
4219 }
4220
4221 for (i = 1; i < entries; i++)
4222 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4223 pllindex = i;
4224 break;
4225 }
4226
4227 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4228
4229 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4230 pllindex ? reg : 0);
4231
4232 /*
4233 * Frequencies are stored in tables in MHz, kHz are more
4234 * useful, so we convert.
4235 */
4236
4237 /* What output frequencies can each VCO generate? */
4238 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4239 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4240 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4241 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4242
4243 /* What input frequencies they accept (past the m-divider)? */
4244 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4245 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4246 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4247 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4248
4249 /* What values are accepted as multiplier and divider? */
4250 pll_lim->vco1.min_n = pll_rec[20];
4251 pll_lim->vco1.max_n = pll_rec[21];
4252 pll_lim->vco1.min_m = pll_rec[22];
4253 pll_lim->vco1.max_m = pll_rec[23];
4254 pll_lim->vco2.min_n = pll_rec[24];
4255 pll_lim->vco2.max_n = pll_rec[25];
4256 pll_lim->vco2.min_m = pll_rec[26];
4257 pll_lim->vco2.max_m = pll_rec[27];
4258
4259 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4260 if (pll_lim->max_log2p > 0x7)
4261 /* pll decoding in nv_hw.c assumes never > 7 */
4262 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4263 pll_lim->max_log2p);
4264 if (cv < 0x60)
4265 pll_lim->max_usable_log2p = 0x6;
4266 pll_lim->log2p_bias = pll_rec[30];
4267
4268 if (recordlen > 0x22)
4269 pll_lim->refclk = ROM32(pll_rec[31]);
4270
4271 if (recordlen > 0x23 && pll_rec[35])
4272 NV_WARN(dev,
4273 "Bits set in PLL configuration byte (%x)\n",
4274 pll_rec[35]);
4275
4276 /* C51 special not seen elsewhere */
4277 if (cv == 0x51 && !pll_lim->refclk) {
4278 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4279
4280 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4281 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4282 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4283 pll_lim->refclk = 200000;
4284 else
4285 pll_lim->refclk = 25000;
4286 }
4287 }
4288 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4289 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4290 uint8_t *record = NULL;
4291 int i;
4292
4293 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4294 limit_match);
4295
4296 for (i = 0; i < entries; i++, entry += recordlen) {
4297 if (ROM32(entry[3]) == limit_match) {
4298 record = &bios->data[ROM16(entry[1])];
4299 break;
4300 }
4301 }
4302
4303 if (!record) {
4304 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4305 "limits table", limit_match);
4306 return -ENOENT;
4307 }
4308
4309 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4310 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4311 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4312 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4313 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4314 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4315 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4316 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4317 pll_lim->vco1.min_n = record[16];
4318 pll_lim->vco1.max_n = record[17];
4319 pll_lim->vco1.min_m = record[18];
4320 pll_lim->vco1.max_m = record[19];
4321 pll_lim->vco2.min_n = record[20];
4322 pll_lim->vco2.max_n = record[21];
4323 pll_lim->vco2.min_m = record[22];
4324 pll_lim->vco2.max_m = record[23];
4325 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4326 pll_lim->log2p_bias = record[27];
4327 pll_lim->refclk = ROM32(record[28]);
4328 } else if (pll_lim_ver) { /* ver 0x40 */
4329 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4330 uint8_t *record = NULL;
4331 int i;
4332
4333 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4334 limit_match);
4335
4336 for (i = 0; i < entries; i++, entry += recordlen) {
4337 if (ROM32(entry[3]) == limit_match) {
4338 record = &bios->data[ROM16(entry[1])];
4339 break;
4340 }
4341 }
4342
4343 if (!record) {
4344 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4345 "limits table", limit_match);
4346 return -ENOENT;
4347 }
4348
4349 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4350 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4351 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4352 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4353 pll_lim->vco1.min_m = record[8];
4354 pll_lim->vco1.max_m = record[9];
4355 pll_lim->vco1.min_n = record[10];
4356 pll_lim->vco1.max_n = record[11];
4357 pll_lim->min_p = record[12];
4358 pll_lim->max_p = record[13];
4359 /* where did this go to?? */
4360 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4361 pll_lim->refclk = 27000;
4362 else
4363 pll_lim->refclk = 100000;
4364 }
4365
4366 /*
4367 * By now any valid limit table ought to have set a max frequency for
4368 * vco1, so if it's zero it's either a pre limit table bios, or one
4369 * with an empty limit table (seen on nv18)
4370 */
4371 if (!pll_lim->vco1.maxfreq) {
4372 pll_lim->vco1.minfreq = bios->fminvco;
4373 pll_lim->vco1.maxfreq = bios->fmaxvco;
4374 pll_lim->vco1.min_inputfreq = 0;
4375 pll_lim->vco1.max_inputfreq = INT_MAX;
4376 pll_lim->vco1.min_n = 0x1;
4377 pll_lim->vco1.max_n = 0xff;
4378 pll_lim->vco1.min_m = 0x1;
4379 if (crystal_straps == 0) {
4380 /* nv05 does this, nv11 doesn't, nv10 unknown */
4381 if (cv < 0x11)
4382 pll_lim->vco1.min_m = 0x7;
4383 pll_lim->vco1.max_m = 0xd;
4384 } else {
4385 if (cv < 0x11)
4386 pll_lim->vco1.min_m = 0x8;
4387 pll_lim->vco1.max_m = 0xe;
4388 }
4389 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4390 pll_lim->max_log2p = 4;
4391 else
4392 pll_lim->max_log2p = 5;
4393 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4394 }
4395
4396 if (!pll_lim->refclk)
4397 switch (crystal_straps) {
4398 case 0:
4399 pll_lim->refclk = 13500;
4400 break;
4401 case (1 << 6):
4402 pll_lim->refclk = 14318;
4403 break;
4404 case (1 << 22):
4405 pll_lim->refclk = 27000;
4406 break;
4407 case (1 << 22 | 1 << 6):
4408 pll_lim->refclk = 25000;
4409 break;
4410 }
4411
4c389f00
BS		 4412 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4413 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4414 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4415 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4416 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4417 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4418 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4419 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4420 if (pll_lim->vco2.maxfreq) {
4421 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4422 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4423 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4424 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4425 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4426 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4427 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4428 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4429 }
4430 if (!pll_lim->max_p) {
4431 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4432 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4433 } else {
4434 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4435 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4436 }
4437 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 4438
4439 return 0;
4440}
4441
4442static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4443{
4444 /*
4445 * offset + 0 (8 bits): Micro version
4446 * offset + 1 (8 bits): Minor version
4447 * offset + 2 (8 bits): Chip version
4448 * offset + 3 (8 bits): Major version
4449 */
4450
4451 bios->major_version = bios->data[offset + 3];
04a39c57 4452 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4453 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4454 bios->data[offset + 3], bios->data[offset + 2],
4455 bios->data[offset + 1], bios->data[offset]);
4456}
4457
4458static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4459{
4460 /*
4461 * Parses the init table segment for pointers used in script execution.
4462 *
4463 * offset + 0 (16 bits): init script tables pointer
4464 * offset + 2 (16 bits): macro index table pointer
4465 * offset + 4 (16 bits): macro table pointer
4466 * offset + 6 (16 bits): condition table pointer
4467 * offset + 8 (16 bits): io condition table pointer
4468 * offset + 10 (16 bits): io flag condition table pointer
4469 * offset + 12 (16 bits): init function table pointer
4470 */
4471
4472 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4473 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4474 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4475 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4476 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4477 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4478 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4479}
4480
4481static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4482{
4483 /*
4484 * Parses the load detect values for g80 cards.
4485 *
4486 * offset + 0 (16 bits): loadval table pointer
4487 */
4488
4489 uint16_t load_table_ptr;
4490 uint8_t version, headerlen, entrylen, num_entries;
4491
4492 if (bitentry->length != 3) {
4493 NV_ERROR(dev, "Do not understand BIT A table\n");
4494 return -EINVAL;
4495 }
4496
4497 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4498
4499 if (load_table_ptr == 0x0) {
4500 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4501 return -EINVAL;
4502 }
4503
4504 version = bios->data[load_table_ptr];
4505
4506 if (version != 0x10) {
4507 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4508 version >> 4, version & 0xF);
4509 return -ENOSYS;
4510 }
4511
4512 headerlen = bios->data[load_table_ptr + 1];
4513 entrylen = bios->data[load_table_ptr + 2];
4514 num_entries = bios->data[load_table_ptr + 3];
4515
4516 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4517 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4518 return -EINVAL;
4519 }
4520
4521 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 4522 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 4523
4524 return 0;
4525}
4526
4527static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4528{
4529 /*
4530 * offset + 8 (16 bits): PLL limits table pointer
4531 *
4532 * There's more in here, but that's unknown.
4533 */
4534
4535 if (bitentry->length < 10) {
4536 NV_ERROR(dev, "Do not understand BIT C table\n");
4537 return -EINVAL;
4538 }
4539
4540 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4541
4542 return 0;
4543}
4544
4545static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4546{
4547 /*
4548 * Parses the flat panel table segment that the bit entry points to.
4549 * Starting at bitentry->offset:
4550 *
4551 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4552 * records beginning with a freq.
4553 * offset + 2 (16 bits): mode table pointer
4554 */
4555
4556 if (bitentry->length != 4) {
4557 NV_ERROR(dev, "Do not understand BIT display table\n");
4558 return -EINVAL;
4559 }
4560
4561 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4562
4563 return 0;
4564}
4565
4566static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4567{
4568 /*
4569 * Parses the init table segment that the bit entry points to.
4570 *
4571 * See parse_script_table_pointers for layout
4572 */
4573
4574 if (bitentry->length < 14) {
4575 NV_ERROR(dev, "Do not understand init table\n");
4576 return -EINVAL;
4577 }
4578
4579 parse_script_table_pointers(bios, bitentry->offset);
4580
4581 if (bitentry->length >= 16)
4582 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4583 if (bitentry->length >= 18)
4584 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4585
4586 return 0;
4587}
4588
4589static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4590{
4591 /*
4592 * BIT 'i' (info?) table
4593 *
4594 * offset + 0 (32 bits): BIOS version dword (as in B table)
4595 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4596 * offset + 13 (16 bits): pointer to table containing DAC load
4597 * detection comparison values
4598 *
4599 * There's other things in the table, purpose unknown
4600 */
4601
4602 uint16_t daccmpoffset;
4603 uint8_t dacver, dacheaderlen;
4604
4605 if (bitentry->length < 6) {
4606 NV_ERROR(dev, "BIT i table too short for needed information\n");
4607 return -EINVAL;
4608 }
4609
4610 parse_bios_version(dev, bios, bitentry->offset);
4611
4612 /*
4613 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4614 * Quadro identity crisis), other bits possibly as for BMP feature byte
4615 */
4616 bios->feature_byte = bios->data[bitentry->offset + 5];
4617 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4618
4619 if (bitentry->length < 15) {
4620 NV_WARN(dev, "BIT i table not long enough for DAC load "
4621 "detection comparison table\n");
4622 return -EINVAL;
4623 }
4624
4625 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4626
4627 /* doesn't exist on g80 */
4628 if (!daccmpoffset)
4629 return 0;
4630
4631 /*
4632 * The first value in the table, following the header, is the
4633 * comparison value, the second entry is a comparison value for
4634 * TV load detection.
4635 */
4636
4637 dacver = bios->data[daccmpoffset];
4638 dacheaderlen = bios->data[daccmpoffset + 1];
4639
4640 if (dacver != 0x00 && dacver != 0x10) {
4641 NV_WARN(dev, "DAC load detection comparison table version "
4642 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4643 return -ENOSYS;
4644 }
4645
04a39c57
BS		 4646 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4647 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 4648
4649 return 0;
4650}
4651
4652static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4653{
4654 /*
4655 * Parses the LVDS table segment that the bit entry points to.
4656 * Starting at bitentry->offset:
4657 *
4658 * offset + 0 (16 bits): LVDS strap xlate table pointer
4659 */
4660
4661 if (bitentry->length != 2) {
4662 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4663 return -EINVAL;
4664 }
4665
4666 /*
4667 * No idea if it's still called the LVDS manufacturer table, but
4668 * the concept's close enough.
4669 */
4670 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4671
4672 return 0;
4673}
4674
4675static int
4676parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4677 struct bit_entry *bitentry)
4678{
4679 /*
4680 * offset + 2 (8 bits): number of options in an
4681 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4682 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4683 * restrict option selection
4684 *
4685 * There's a bunch of bits in this table other than the RAM restrict
4686 * stuff that we don't use - their use currently unknown
4687 */
4688
6ee73861
BS		 4689 /*
4690 * Older bios versions don't have a sufficiently long table for
4691 * what we want
4692 */
4693 if (bitentry->length < 0x5)
4694 return 0;
4695
4696 if (bitentry->id[1] < 2) {
37383650
MK		 4697 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4698 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 4699 } else {
37383650
MK		 4700 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4701 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 4702 }
4703
6ee73861
BS		 4704 return 0;
4705}
4706
4707static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4708{
4709 /*
4710 * Parses the pointer to the TMDS table
4711 *
4712 * Starting at bitentry->offset:
4713 *
4714 * offset + 0 (16 bits): TMDS table pointer
4715 *
4716 * The TMDS table is typically found just before the DCB table, with a
4717 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4718 * length?)
4719 *
4720 * At offset +7 is a pointer to a script, which I don't know how to
4721 * run yet.
4722 * At offset +9 is a pointer to another script, likewise
4723 * Offset +11 has a pointer to a table where the first word is a pxclk
4724 * frequency and the second word a pointer to a script, which should be
4725 * run if the comparison pxclk frequency is less than the pxclk desired.
4726 * This repeats for decreasing comparison frequencies
4727 * Offset +13 has a pointer to a similar table
4728 * The selection of table (and possibly +7/+9 script) is dictated by
4729 * "or" from the DCB.
4730 */
4731
4732 uint16_t tmdstableptr, script1, script2;
4733
4734 if (bitentry->length != 2) {
4735 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4736 return -EINVAL;
4737 }
4738
4739 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4740
4741 if (tmdstableptr == 0x0) {
4742 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4743 return -EINVAL;
4744 }
4745
4746 /* nv50+ has v2.0, but we don't parse it atm */
4747 if (bios->data[tmdstableptr] != 0x11) {
4748 NV_WARN(dev,
4749 "TMDS table revision %d.%d not currently supported\n",
4750 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4751 return -ENOSYS;
4752 }
4753
4754 /*
4755 * These two scripts are odd: they don't seem to get run even when
4756 * they are not stubbed.
4757 */
4758 script1 = ROM16(bios->data[tmdstableptr + 7]);
4759 script2 = ROM16(bios->data[tmdstableptr + 9]);
4760 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4761 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4762
4763 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4764 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4765
4766 return 0;
4767}
4768
4769static int
4770parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4771 struct bit_entry *bitentry)
4772{
4773 /*
4774 * Parses the pointer to the G80 output script tables
4775 *
4776 * Starting at bitentry->offset:
4777 *
4778 * offset + 0 (16 bits): output script table pointer
4779 */
4780
4781 uint16_t outputscripttableptr;
4782
4783 if (bitentry->length != 3) {
4784 NV_ERROR(dev, "Do not understand BIT U table\n");
4785 return -EINVAL;
4786 }
4787
4788 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4789 bios->display.script_table_ptr = outputscripttableptr;
4790 return 0;
4791}
4792
4793static int
4794parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4795 struct bit_entry *bitentry)
4796{
4797 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4798 return 0;
4799}
4800
4801struct bit_table {
4802 const char id;
4803 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4804};
4805
4806#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4807
4808static int
4809parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4810 struct bit_table *table)
4811{
4812 struct drm_device *dev = bios->dev;
4813 uint8_t maxentries = bios->data[bitoffset + 4];
4814 int i, offset;
4815 struct bit_entry bitentry;
4816
4817 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4818 bitentry.id[0] = bios->data[offset];
4819
4820 if (bitentry.id[0] != table->id)
4821 continue;
4822
4823 bitentry.id[1] = bios->data[offset + 1];
4824 bitentry.length = ROM16(bios->data[offset + 2]);
4825 bitentry.offset = ROM16(bios->data[offset + 4]);
4826
4827 return table->parse_fn(dev, bios, &bitentry);
4828 }
4829
4830 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4831 return -ENOSYS;
4832}
4833
4834static int
4835parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4836{
4837 int ret;
4838
4839 /*
4840 * The only restriction on parsing order currently is having 'i' first
4841 * for use of bios->*_version or bios->feature_byte while parsing;
4842 * functions shouldn't be actually *doing* anything apart from pulling
4843 * data from the image into the bios struct, thus no interdependencies
4844 */
4845 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4846 if (ret) /* info? */
4847 return ret;
4848 if (bios->major_version >= 0x60) /* g80+ */
4849 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4850 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4851 if (ret)
4852 return ret;
4853 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4854 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4855 if (ret)
4856 return ret;
4857 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4858 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4859 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4860 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4861 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4862
4863 return 0;
4864}
4865
4866static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4867{
4868 /*
4869 * Parses the BMP structure for useful things, but does not act on them
4870 *
4871 * offset + 5: BMP major version
4872 * offset + 6: BMP minor version
4873 * offset + 9: BMP feature byte
4874 * offset + 10: BCD encoded BIOS version
4875 *
4876 * offset + 18: init script table pointer (for bios versions < 5.10h)
4877 * offset + 20: extra init script table pointer (for bios
4878 * versions < 5.10h)
4879 *
4880 * offset + 24: memory init table pointer (used on early bios versions)
4881 * offset + 26: SDR memory sequencing setup data table
4882 * offset + 28: DDR memory sequencing setup data table
4883 *
4884 * offset + 54: index of I2C CRTC pair to use for CRT output
4885 * offset + 55: index of I2C CRTC pair to use for TV output
4886 * offset + 56: index of I2C CRTC pair to use for flat panel output
4887 * offset + 58: write CRTC index for I2C pair 0
4888 * offset + 59: read CRTC index for I2C pair 0
4889 * offset + 60: write CRTC index for I2C pair 1
4890 * offset + 61: read CRTC index for I2C pair 1
4891 *
4892 * offset + 67: maximum internal PLL frequency (single stage PLL)
4893 * offset + 71: minimum internal PLL frequency (single stage PLL)
4894 *
4895 * offset + 75: script table pointers, as described in
4896 * parse_script_table_pointers
4897 *
4898 * offset + 89: TMDS single link output A table pointer
4899 * offset + 91: TMDS single link output B table pointer
4900 * offset + 95: LVDS single link output A table pointer
4901 * offset + 105: flat panel timings table pointer
4902 * offset + 107: flat panel strapping translation table pointer
4903 * offset + 117: LVDS manufacturer panel config table pointer
4904 * offset + 119: LVDS manufacturer strapping translation table pointer
4905 *
4906 * offset + 142: PLL limits table pointer
4907 *
4908 * offset + 156: minimum pixel clock for LVDS dual link
4909 */
4910
4911 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
4912 uint16_t bmplength;
4913 uint16_t legacy_scripts_offset, legacy_i2c_offset;
4914
4915 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 4916 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
4917 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
4918 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
4919 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 4920 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 4921 bios->fmaxvco = 256000;
4922 bios->fminvco = 128000;
4923 bios->fp.duallink_transition_clk = 90000;
4924
4925 bmp_version_major = bmp[5];
4926 bmp_version_minor = bmp[6];
4927
4928 NV_TRACE(dev, "BMP version %d.%d\n",
4929 bmp_version_major, bmp_version_minor);
4930
4931 /*
4932 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4933 * pointer on early versions
4934 */
4935 if (bmp_version_major < 5)
4936 *(uint16_t *)&bios->data[0x36] = 0;
4937
4938 /*
4939 * Seems that the minor version was 1 for all major versions prior
4940 * to 5. Version 6 could theoretically exist, but I suspect BIT
4941 * happened instead.
4942 */
4943 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
4944 NV_ERROR(dev, "You have an unsupported BMP version. "
4945 "Please send in your bios\n");
4946 return -ENOSYS;
4947 }
4948
4949 if (bmp_version_major == 0)
4950 /* nothing that's currently useful in this version */
4951 return 0;
4952 else if (bmp_version_major == 1)
4953 bmplength = 44; /* exact for 1.01 */
4954 else if (bmp_version_major == 2)
4955 bmplength = 48; /* exact for 2.01 */
4956 else if (bmp_version_major == 3)
4957 bmplength = 54;
4958 /* guessed - mem init tables added in this version */
4959 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
4960 /* don't know if 5.0 exists... */
4961 bmplength = 62;
4962 /* guessed - BMP I2C indices added in version 4*/
4963 else if (bmp_version_minor < 0x6)
4964 bmplength = 67; /* exact for 5.01 */
4965 else if (bmp_version_minor < 0x10)
4966 bmplength = 75; /* exact for 5.06 */
4967 else if (bmp_version_minor == 0x10)
4968 bmplength = 89; /* exact for 5.10h */
4969 else if (bmp_version_minor < 0x14)
4970 bmplength = 118; /* exact for 5.11h */
4971 else if (bmp_version_minor < 0x24)
4972 /*
4973 * Not sure of version where pll limits came in;
4974 * certainly exist by 0x24 though.
4975 */
4976 /* length not exact: this is long enough to get lvds members */
4977 bmplength = 123;
4978 else if (bmp_version_minor < 0x27)
4979 /*
4980 * Length not exact: this is long enough to get pll limit
4981 * member
4982 */
4983 bmplength = 144;
4984 else
4985 /*
4986 * Length not exact: this is long enough to get dual link
4987 * transition clock.
4988 */
4989 bmplength = 158;
4990
4991 /* checksum */
4992 if (nv_cksum(bmp, 8)) {
4993 NV_ERROR(dev, "Bad BMP checksum\n");
4994 return -EINVAL;
4995 }
4996
4997 /*
4998 * Bit 4 seems to indicate either a mobile bios or a quadro card --
4999 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5000 * (not nv10gl), bit 5 that the flat panel tables are present, and
5001 * bit 6 a tv bios.
5002 */
5003 bios->feature_byte = bmp[9];
5004
5005 parse_bios_version(dev, bios, offset + 10);
5006
5007 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5008 bios->old_style_init = true;
5009 legacy_scripts_offset = 18;
5010 if (bmp_version_major < 2)
5011 legacy_scripts_offset -= 4;
5012 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5013 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5014
5015 if (bmp_version_major > 2) { /* appears in BMP 3 */
5016 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5017 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5018 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5019 }
5020
5021 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5022 if (bmplength > 61)
5023 legacy_i2c_offset = offset + 54;
5024 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5025 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5026 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
7f245b20
BS		 5027 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5028 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5029 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5030 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5031
5032 if (bmplength > 74) {
5033 bios->fmaxvco = ROM32(bmp[67]);
5034 bios->fminvco = ROM32(bmp[71]);
5035 }
5036 if (bmplength > 88)
5037 parse_script_table_pointers(bios, offset + 75);
5038 if (bmplength > 94) {
5039 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5040 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5041 /*
5042 * Never observed in use with lvds scripts, but is reused for
5043 * 18/24 bit panel interface default for EDID equipped panels
5044 * (if_is_24bit not set directly to avoid any oscillation).
5045 */
5046 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5047 }
5048 if (bmplength > 108) {
5049 bios->fp.fptablepointer = ROM16(bmp[105]);
5050 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5051 bios->fp.xlatwidth = 1;
5052 }
5053 if (bmplength > 120) {
5054 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5055 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5056 }
5057 if (bmplength > 143)
5058 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5059
5060 if (bmplength > 157)
5061 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5062
5063 return 0;
5064}
5065
5066static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5067{
5068 int i, j;
5069
5070 for (i = 0; i <= (n - len); i++) {
5071 for (j = 0; j < len; j++)
5072 if (data[i + j] != str[j])
5073 break;
5074 if (j == len)
5075 return i;
5076 }
5077
5078 return 0;
5079}
5080
5081static int
5082read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
5083{
5084 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
5085 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
5086 int recordoffset = 0, rdofs = 1, wrofs = 0;
5087 uint8_t port_type = 0;
5088
5089 if (!i2ctable)
5090 return -EINVAL;
5091
5092 if (dcb_version >= 0x30) {
5093 if (i2ctable[0] != dcb_version) /* necessary? */
5094 NV_WARN(dev,
5095 "DCB I2C table version mismatch (%02X vs %02X)\n",
5096 i2ctable[0], dcb_version);
5097 dcb_i2c_ver = i2ctable[0];
5098 headerlen = i2ctable[1];
5099 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
5100 i2c_entries = i2ctable[2];
5101 else
5102 NV_WARN(dev,
5103 "DCB I2C table has more entries than indexable "
761c5a69
MS		 5104 "(%d entries, max %d)\n", i2ctable[2],
5105 DCB_MAX_NUM_I2C_ENTRIES);
6ee73861
BS		 5106 entry_len = i2ctable[3];
5107 /* [4] is i2c_default_indices, read in parse_dcb_table() */
5108 }
5109 /*
5110 * It's your own fault if you call this function on a DCB 1.1 BIOS --
5111 * the test below is for DCB 1.2
5112 */
5113 if (dcb_version < 0x14) {
5114 recordoffset = 2;
5115 rdofs = 0;
5116 wrofs = 1;
5117 }
5118
5119 if (index == 0xf)
5120 return 0;
761c5a69
MS		 5121 if (index >= i2c_entries) {
5122 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
6ee73861
BS		 5123 index, i2ctable[2]);
5124 return -ENOENT;
5125 }
5126 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
5127 NV_ERROR(dev, "DCB I2C entry invalid\n");
5128 return -EINVAL;
5129 }
5130
5131 if (dcb_i2c_ver >= 0x30) {
5132 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
5133
5134 /*
5135 * Fixup for chips using same address offset for read and
5136 * write.
5137 */
5138 if (port_type == 4) /* seen on C51 */
5139 rdofs = wrofs = 1;
5140 if (port_type >= 5) /* G80+ */
5141 rdofs = wrofs = 0;
5142 }
5143
07fee3d5
BS		 5144 if (dcb_i2c_ver >= 0x40) {
5145 if (port_type != 5 && port_type != 6)
5146 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
5147
5148 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
5149 }
6ee73861
BS		 5150
5151 i2c->port_type = port_type;
5152 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
5153 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
5154
5155 return 0;
5156}
5157
5158static struct dcb_gpio_entry *
5159new_gpio_entry(struct nvbios *bios)
5160{
7f245b20 5161 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861
BS		 5162
5163 return &gpio->entry[gpio->entries++];
5164}
5165
5166struct dcb_gpio_entry *
5167nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5168{
5169 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5170 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5171 int i;
5172
7f245b20
BS		 5173 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5174 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5175 continue;
5176
7f245b20 5177 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5178 }
5179
5180 return NULL;
5181}
5182
5183static void
5184parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5185{
5186 struct dcb_gpio_entry *gpio;
5187 uint16_t ent = ROM16(bios->data[offset]);
5188 uint8_t line = ent & 0x1f,
5189 tag = ent >> 5 & 0x3f,
5190 flags = ent >> 11 & 0x1f;
5191
5192 if (tag == 0x3f)
5193 return;
5194
5195 gpio = new_gpio_entry(bios);
5196
5197 gpio->tag = tag;
5198 gpio->line = line;
5199 gpio->invert = flags != 4;
2535d71c 5200 gpio->entry = ent;
6ee73861
BS		 5201}
5202
5203static void
5204parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5205{
02faec09 5206 uint32_t entry = ROM32(bios->data[offset]);
6ee73861 5207 struct dcb_gpio_entry *gpio;
6ee73861 5208
02faec09 5209 if ((entry & 0x0000ff00) == 0x0000ff00)
6ee73861
BS		 5210 return;
5211
5212 gpio = new_gpio_entry(bios);
02faec09
BS		 5213 gpio->tag = (entry & 0x0000ff00) >> 8;
5214 gpio->line = (entry & 0x0000001f) >> 0;
5215 gpio->state_default = (entry & 0x01000000) >> 24;
5216 gpio->state[0] = (entry & 0x18000000) >> 27;
5217 gpio->state[1] = (entry & 0x60000000) >> 29;
5218 gpio->entry = entry;
6ee73861
BS		 5219}
5220
5221static void
5222parse_dcb_gpio_table(struct nvbios *bios)
5223{
5224 struct drm_device *dev = bios->dev;
7f245b20 5225 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr;
6ee73861
BS		 5226 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5227 int header_len = gpio_table[1],
5228 entries = gpio_table[2],
5229 entry_len = gpio_table[3];
5230 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5231 int i;
5232
7f245b20 5233 if (bios->dcb.version >= 0x40) {
6ee73861
BS		 5234 if (gpio_table_ptr && entry_len != 4) {
5235 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5236 return;
5237 }
5238
5239 parse_entry = parse_dcb40_gpio_entry;
5240
7f245b20 5241 } else if (bios->dcb.version >= 0x30) {
6ee73861
BS		 5242 if (gpio_table_ptr && entry_len != 2) {
5243 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5244 return;
5245 }
5246
5247 parse_entry = parse_dcb30_gpio_entry;
5248
7f245b20 5249 } else if (bios->dcb.version >= 0x22) {
6ee73861
BS		 5250 /*
5251 * DCBs older than v3.0 don't really have a GPIO
5252 * table, instead they keep some GPIO info at fixed
5253 * locations.
5254 */
5255 uint16_t dcbptr = ROM16(bios->data[0x36]);
5256 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5257
5258 if (tvdac_gpio[0] & 1) {
5259 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5260
5261 gpio->tag = DCB_GPIO_TVDAC0;
5262 gpio->line = tvdac_gpio[1] >> 4;
5263 gpio->invert = tvdac_gpio[0] & 2;
5264 }
5265 }
5266
5267 if (!gpio_table_ptr)
5268 return;
5269
5270 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5271 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5272 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5273 }
5274
5275 for (i = 0; i < entries; i++)
5276 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5277}
5278
5279struct dcb_connector_table_entry *
5280nouveau_bios_connector_entry(struct drm_device *dev, int index)
5281{
5282 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5283 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5284 struct dcb_connector_table_entry *cte;
5285
7f245b20 5286 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5287 return NULL;
5288
7f245b20 5289 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5290 if (cte->type == 0xff)
5291 return NULL;
5292
5293 return cte;
5294}
5295
f66fa771
BS		 5296static enum dcb_connector_type
5297divine_connector_type(struct nvbios *bios, int index)
5298{
5299 struct dcb_table *dcb = &bios->dcb;
5300 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5301 int i;
5302
5303 for (i = 0; i < dcb->entries; i++) {
5304 if (dcb->entry[i].connector == index)
5305 encoders |= (1 << dcb->entry[i].type);
5306 }
5307
5308 if (encoders & (1 << OUTPUT_DP)) {
5309 if (encoders & (1 << OUTPUT_TMDS))
5310 type = DCB_CONNECTOR_DP;
5311 else
5312 type = DCB_CONNECTOR_eDP;
5313 } else
5314 if (encoders & (1 << OUTPUT_TMDS)) {
5315 if (encoders & (1 << OUTPUT_ANALOG))
5316 type = DCB_CONNECTOR_DVI_I;
5317 else
5318 type = DCB_CONNECTOR_DVI_D;
5319 } else
5320 if (encoders & (1 << OUTPUT_ANALOG)) {
5321 type = DCB_CONNECTOR_VGA;
5322 } else
5323 if (encoders & (1 << OUTPUT_LVDS)) {
5324 type = DCB_CONNECTOR_LVDS;
5325 } else
5326 if (encoders & (1 << OUTPUT_TV)) {
5327 type = DCB_CONNECTOR_TV_0;
5328 }
5329
5330 return type;
5331}
5332
53c44c3a
BS		 5333static void
5334apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5335{
5336 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5337 struct drm_device *dev = bios->dev;
5338
5339 /* Gigabyte NX85T */
5340 if ((dev->pdev->device == 0x0421) &&
5341 (dev->pdev->subsystem_vendor == 0x1458) &&
5342 (dev->pdev->subsystem_device == 0x344c)) {
5343 if (cte->type == DCB_CONNECTOR_HDMI_1)
5344 cte->type = DCB_CONNECTOR_DVI_I;
5345 }
5346}
5347
6ee73861
BS		 5348static void
5349parse_dcb_connector_table(struct nvbios *bios)
5350{
5351 struct drm_device *dev = bios->dev;
7f245b20 5352 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5353 struct dcb_connector_table_entry *cte;
7f245b20 5354 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5355 uint8_t *entry;
5356 int i;
5357
7f245b20 5358 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5359 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5360 return;
5361 }
5362
5363 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5364 conntab[0], conntab[1], conntab[2], conntab[3]);
5365 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5366 (conntab[3] != 2 && conntab[3] != 4)) {
5367 NV_ERROR(dev, " Unknown! Please report.\n");
5368 return;
5369 }
5370
5371 ct->entries = conntab[2];
5372
5373 entry = conntab + conntab[1];
5374 cte = &ct->entry[0];
5375 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5376 cte->index = i;
6ee73861
BS		 5377 if (conntab[3] == 2)
5378 cte->entry = ROM16(entry[0]);
5379 else
5380 cte->entry = ROM32(entry[0]);
f66fa771 5381
6ee73861 5382 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 5383 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6ee73861
BS		 5384 switch (cte->entry & 0x00033000) {
5385 case 0x00001000:
5386 cte->gpio_tag = 0x07;
5387 break;
5388 case 0x00002000:
5389 cte->gpio_tag = 0x08;
5390 break;
5391 case 0x00010000:
5392 cte->gpio_tag = 0x51;
5393 break;
5394 case 0x00020000:
5395 cte->gpio_tag = 0x52;
5396 break;
5397 default:
5398 cte->gpio_tag = 0xff;
5399 break;
5400 }
5401
5402 if (cte->type == 0xff)
5403 continue;
5404
53c44c3a
BS		 5405 apply_dcb_connector_quirks(bios, i);
5406
6ee73861
BS		 5407 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5408 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5409
5410 /* check for known types, fallback to guessing the type
5411 * from attached encoders if we hit an unknown.
5412 */
5413 switch (cte->type) {
5414 case DCB_CONNECTOR_VGA:
5415 case DCB_CONNECTOR_TV_0:
5416 case DCB_CONNECTOR_TV_1:
5417 case DCB_CONNECTOR_TV_3:
5418 case DCB_CONNECTOR_DVI_I:
5419 case DCB_CONNECTOR_DVI_D:
5420 case DCB_CONNECTOR_LVDS:
5421 case DCB_CONNECTOR_DP:
5422 case DCB_CONNECTOR_eDP:
5423 case DCB_CONNECTOR_HDMI_0:
5424 case DCB_CONNECTOR_HDMI_1:
5425 break;
5426 default:
5427 cte->type = divine_connector_type(bios, cte->index);
da647d5b 5428 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 5429 break;
5430 }
5431
da647d5b
BS		 5432 if (nouveau_override_conntype) {
5433 int type = divine_connector_type(bios, cte->index);
5434 if (type != cte->type)
5435 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5436 }
5437
6ee73861
BS		 5438 }
5439}
5440
7f245b20 5441static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5442{
5443 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5444
5445 memset(entry, 0, sizeof(struct dcb_entry));
5446 entry->index = dcb->entries++;
5447
5448 return entry;
5449}
5450
7f245b20 5451static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
6ee73861
BS		 5452{
5453 struct dcb_entry *entry = new_dcb_entry(dcb);
5454
5455 entry->type = 0;
5456 entry->i2c_index = i2c;
5457 entry->heads = heads;
5458 entry->location = DCB_LOC_ON_CHIP;
5459 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5460}
5461
7f245b20 5462static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5463{
5464 struct dcb_entry *entry = new_dcb_entry(dcb);
5465
5466 entry->type = 2;
5467 entry->i2c_index = LEGACY_I2C_PANEL;
5468 entry->heads = twoHeads ? 3 : 1;
5469 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5470 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5471 entry->duallink_possible = false; /* SiI164 and co. are single link */
5472
5473#if 0
5474 /*
5475 * For dvi-a either crtc probably works, but my card appears to only
5476 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5477 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5478 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5479 * the monitor picks up the mode res ok and lights up, but no pixel
5480 * data appears, so the board manufacturer probably connected up the
5481 * sync lines, but missed the video traces / components
5482 *
5483 * with this introduction, dvi-a left as an exercise for the reader.
5484 */
5485 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5486#endif
5487}
5488
7f245b20 5489static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5490{
5491 struct dcb_entry *entry = new_dcb_entry(dcb);
5492
5493 entry->type = 1;
5494 entry->i2c_index = LEGACY_I2C_TV;
5495 entry->heads = twoHeads ? 3 : 1;
5496 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5497}
5498
5499static bool
7f245b20 5500parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5501 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5502{
5503 entry->type = conn & 0xf;
5504 entry->i2c_index = (conn >> 4) & 0xf;
5505 entry->heads = (conn >> 8) & 0xf;
7f245b20 5506 if (dcb->version >= 0x40)
6ee73861
BS		 5507 entry->connector = (conn >> 12) & 0xf;
5508 entry->bus = (conn >> 16) & 0xf;
5509 entry->location = (conn >> 20) & 0x3;
5510 entry->or = (conn >> 24) & 0xf;
5511 /*
5512 * Normal entries consist of a single bit, but dual link has the
5513 * next most significant bit set too
5514 */
5515 entry->duallink_possible =
5516 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5517
5518 switch (entry->type) {
5519 case OUTPUT_ANALOG:
5520 /*
5521 * Although the rest of a CRT conf dword is usually
5522 * zeros, mac biosen have stuff there so we must mask
5523 */
7f245b20 5524 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5525 (conf & 0xffff) * 10 :
5526 (conf & 0xff) * 10000;
5527 break;
5528 case OUTPUT_LVDS:
5529 {
5530 uint32_t mask;
5531 if (conf & 0x1)
5532 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5533 if (dcb->version < 0x22) {
6ee73861
BS		 5534 mask = ~0xd;
5535 /*
5536 * The laptop in bug 14567 lies and claims to not use
5537 * straps when it does, so assume all DCB 2.0 laptops
5538 * use straps, until a broken EDID using one is produced
5539 */
5540 entry->lvdsconf.use_straps_for_mode = true;
5541 /*
5542 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5543 * mean the same thing (probably wrong, but might work)
5544 */
5545 if (conf & 0x4 || conf & 0x8)
5546 entry->lvdsconf.use_power_scripts = true;
5547 } else {
5548 mask = ~0x5;
5549 if (conf & 0x4)
5550 entry->lvdsconf.use_power_scripts = true;
5551 }
5552 if (conf & mask) {
5553 /*
5554 * Until we even try to use these on G8x, it's
5555 * useless reporting unknown bits. They all are.
5556 */
7f245b20 5557 if (dcb->version >= 0x40)
6ee73861
BS		 5558 break;
5559
5560 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5561 "please report\n");
5562 }
5563 break;
5564 }
5565 case OUTPUT_TV:
5566 {
7f245b20 5567 if (dcb->version >= 0x30)
6ee73861
BS		 5568 entry->tvconf.has_component_output = conf & (0x8 << 4);
5569 else
5570 entry->tvconf.has_component_output = false;
5571
5572 break;
5573 }
5574 case OUTPUT_DP:
5575 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5576 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5577 switch ((conf & 0x0f000000) >> 24) {
5578 case 0xf:
5579 entry->dpconf.link_nr = 4;
5580 break;
5581 case 0x3:
5582 entry->dpconf.link_nr = 2;
5583 break;
5584 default:
5585 entry->dpconf.link_nr = 1;
5586 break;
5587 }
5588 break;
5589 case OUTPUT_TMDS:
5590 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5591 break;
5592 case 0xe:
5593 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 5594 dcb->entries--;
6ee73861 5595 return false;
e7cc51c5
BS		 5596 default:
5597 break;
6ee73861
BS		 5598 }
5599
5600 /* unsure what DCB version introduces this, 3.0? */
5601 if (conf & 0x100000)
5602 entry->i2c_upper_default = true;
5603
5604 return true;
5605}
5606
5607static bool
7f245b20 5608parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5609 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5610{
b0d2de86
BS		 5611 switch (conn & 0x0000000f) {
5612 case 0:
5613 entry->type = OUTPUT_ANALOG;
5614 break;
5615 case 1:
5616 entry->type = OUTPUT_TV;
5617 break;
5618 case 2:
5619 case 3:
6ee73861 5620 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 5621 break;
5622 case 4:
5623 switch ((conn & 0x000000f0) >> 4) {
5624 case 0:
6ee73861 5625 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 5626 break;
5627 case 1:
5628 entry->type = OUTPUT_LVDS;
5629 break;
5630 default:
5631 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5632 (conn & 0x000000f0) >> 4);
5633 return false;
5634 }
5635 break;
5636 default:
5637 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5638 return false;
6ee73861 5639 }
b0d2de86
BS		 5640
5641 entry->i2c_index = (conn & 0x0003c000) >> 14;
5642 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5643 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5644 entry->location = (conn & 0x01e00000) >> 21;
5645 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 5646 entry->duallink_possible = false;
5647
5648 switch (entry->type) {
5649 case OUTPUT_ANALOG:
5650 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5651 break;
b0d2de86
BS		 5652 case OUTPUT_TV:
5653 entry->tvconf.has_component_output = false;
6ee73861
BS		 5654 break;
5655 case OUTPUT_TMDS:
5656 /*
5657 * Invent a DVI-A output, by copying the fields of the DVI-D
5658 * output; reported to work by math_b on an NV20(!).
5659 */
5660 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5661 break;
b0d2de86
BS		 5662 case OUTPUT_LVDS:
5663 if ((conn & 0x00003f00) != 0x10)
5664 entry->lvdsconf.use_straps_for_mode = true;
5665 entry->lvdsconf.use_power_scripts = true;
5666 break;
5667 default:
6ee73861
BS		 5668 break;
5669 }
5670
5671 return true;
5672}
5673
7f245b20 5674static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5675 uint32_t conn, uint32_t conf)
5676{
7f245b20 5677 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 5678 bool ret;
5679
7f245b20
BS		 5680 if (dcb->version >= 0x20)
5681 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 5682 else
7f245b20 5683 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 5684 if (!ret)
5685 return ret;
5686
7f245b20
BS		 5687 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
5688 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 5689
5690 return true;
5691}
5692
5693static
7f245b20 5694void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 5695{
5696 /*
5697 * DCB v2.0 lists each output combination separately.
5698 * Here we merge compatible entries to have fewer outputs, with
5699 * more options
5700 */
5701
5702 int i, newentries = 0;
5703
5704 for (i = 0; i < dcb->entries; i++) {
5705 struct dcb_entry *ient = &dcb->entry[i];
5706 int j;
5707
5708 for (j = i + 1; j < dcb->entries; j++) {
5709 struct dcb_entry *jent = &dcb->entry[j];
5710
5711 if (jent->type == 100) /* already merged entry */
5712 continue;
5713
5714 /* merge heads field when all other fields the same */
5715 if (jent->i2c_index == ient->i2c_index &&
5716 jent->type == ient->type &&
5717 jent->location == ient->location &&
5718 jent->or == ient->or) {
5719 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5720 i, j);
5721 ient->heads |= jent->heads;
5722 jent->type = 100; /* dummy value */
5723 }
5724 }
5725 }
5726
5727 /* Compact entries merged into others out of dcb */
5728 for (i = 0; i < dcb->entries; i++) {
5729 if (dcb->entry[i].type == 100)
5730 continue;
5731
5732 if (newentries != i) {
5733 dcb->entry[newentries] = dcb->entry[i];
5734 dcb->entry[newentries].index = newentries;
5735 }
5736 newentries++;
5737 }
5738
5739 dcb->entries = newentries;
5740}
5741
ed42f824
BS		 5742static int
5743parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 5744{
ed42f824 5745 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 5746 struct dcb_table *dcb = &bios->dcb;
ed42f824 5747 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 5748 uint8_t *dcbtable;
5749 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5750 bool configblock = true;
5751 int recordlength = 8, confofs = 4;
5752 int i;
5753
6ee73861 5754 /* get the offset from 0x36 */
ed42f824
BS		 5755 if (dev_priv->card_type > NV_04) {
5756 dcbptr = ROM16(bios->data[0x36]);
5757 if (dcbptr == 0x0000)
5758 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5759 }
6ee73861 5760
ed42f824 5761 /* this situation likely means a really old card, pre DCB */
6ee73861 5762 if (dcbptr == 0x0) {
ed42f824 5763 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 5764 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5765
ed42f824 5766 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 5767 fabricate_tv_output(dcb, twoHeads);
5768
5769 return 0;
5770 }
5771
5772 dcbtable = &bios->data[dcbptr];
5773
5774 /* get DCB version */
7f245b20 5775 dcb->version = dcbtable[0];
6ee73861 5776 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 5777 dcb->version >> 4, dcb->version & 0xf);
6ee73861 5778
7f245b20 5779 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 5780 uint32_t sig;
5781
7f245b20 5782 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 5783 headerlen = dcbtable[1];
5784 entries = dcbtable[2];
5785 recordlength = dcbtable[3];
5786 i2ctabptr = ROM16(dcbtable[4]);
5787 sig = ROM32(dcbtable[6]);
7f245b20
BS		 5788 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
5789 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 5790 } else {
5791 i2ctabptr = ROM16(dcbtable[2]);
5792 sig = ROM32(dcbtable[4]);
5793 headerlen = 8;
5794 }
5795
5796 if (sig != 0x4edcbdcb) {
5797 NV_ERROR(dev, "Bad Display Configuration Block "
5798 "signature (%08X)\n", sig);
5799 return -EINVAL;
5800 }
7f245b20 5801 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 5802 char sig[8] = { 0 };
5803
5804 strncpy(sig, (char *)&dcbtable[-7], 7);
5805 i2ctabptr = ROM16(dcbtable[2]);
5806 recordlength = 10;
5807 confofs = 6;
5808
5809 if (strcmp(sig, "DEV_REC")) {
5810 NV_ERROR(dev, "Bad Display Configuration Block "
5811 "signature (%s)\n", sig);
5812 return -EINVAL;
5813 }
5814 } else {
5815 /*
5816 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5817 * has the same single (crt) entry, even when tv-out present, so
5818 * the conclusion is this version cannot really be used.
5819 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5820 * 5 entries, which are not specific to the card and so no use.
5821 * v1.2 does have an I2C table that read_dcb_i2c_table can
5822 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5823 * pointer, so use the indices parsed in parse_bmp_structure.
5824 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5825 */
5826 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5827 "adding all possible outputs\n");
5828 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5829
5830 /*
5831 * Attempt to detect TV before DVI because the test
5832 * for the former is more accurate and it rules the
5833 * latter out.
5834 */
5835 if (nv04_tv_identify(dev,
5836 bios->legacy.i2c_indices.tv) >= 0)
5837 fabricate_tv_output(dcb, twoHeads);
5838
5839 else if (bios->tmds.output0_script_ptr ||
5840 bios->tmds.output1_script_ptr)
5841 fabricate_dvi_i_output(dcb, twoHeads);
5842
5843 return 0;
5844 }
5845
5846 if (!i2ctabptr)
5847 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5848 else {
7f245b20
BS		 5849 dcb->i2c_table = &bios->data[i2ctabptr];
5850 if (dcb->version >= 0x30)
5851 dcb->i2c_default_indices = dcb->i2c_table[4];
6ee73861
BS		 5852 }
5853
6ee73861
BS		 5854 if (entries > DCB_MAX_NUM_ENTRIES)
5855 entries = DCB_MAX_NUM_ENTRIES;
5856
5857 for (i = 0; i < entries; i++) {
5858 uint32_t connection, config = 0;
5859
5860 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5861 if (configblock)
5862 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5863
5864 /* seen on an NV11 with DCB v1.5 */
5865 if (connection == 0x00000000)
5866 break;
5867
5868 /* seen on an NV17 with DCB v2.0 */
5869 if (connection == 0xffffffff)
5870 break;
5871
5872 if ((connection & 0x0000000f) == 0x0000000f)
5873 continue;
5874
5875 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5876 dcb->entries, connection, config);
5877
7f245b20 5878 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 5879 break;
5880 }
5881
5882 /*
5883 * apart for v2.1+ not being known for requiring merging, this
5884 * guarantees dcbent->index is the index of the entry in the rom image
5885 */
7f245b20 5886 if (dcb->version < 0x21)
6ee73861
BS		 5887 merge_like_dcb_entries(dev, dcb);
5888
54abb5dd
BS		 5889 if (!dcb->entries)
5890 return -ENXIO;
5891
5892 parse_dcb_gpio_table(bios);
5893 parse_dcb_connector_table(bios);
5894 return 0;
6ee73861
BS		 5895}
5896
5897static void
5898fixup_legacy_connector(struct nvbios *bios)
5899{
7f245b20 5900 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 5901 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 5902
5903 /*
5904 * DCB 3.0 also has the table in most cases, but there are some cards
5905 * where the table is filled with stub entries, and the DCB entriy
5906 * indices are all 0. We don't need the connector indices on pre-G80
5907 * chips (yet?) so limit the use to DCB 4.0 and above.
5908 */
7f245b20 5909 if (dcb->version >= 0x40)
6ee73861
BS		 5910 return;
5911
dc5bc4ed
BS		 5912 dcb->connector.entries = 0;
5913
6ee73861
BS		 5914 /*
5915 * No known connector info before v3.0, so make it up. the rule here
5916 * is: anything on the same i2c bus is considered to be on the same
5917 * connector. any output without an associated i2c bus is assigned
5918 * its own unique connector index.
5919 */
5920 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 5921 /*
5922 * Ignore the I2C index for on-chip TV-out, as there
5923 * are cards with bogus values (nv31m in bug 23212),
5924 * and it's otherwise useless.
5925 */
5926 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 5927 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 5928 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 5929 i2c = dcb->entry[i].i2c_index;
5930
5931 if (i2c_conn[i2c]) {
5932 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 5933 continue;
5934 }
5935
dc5bc4ed
BS		 5936 dcb->entry[i].connector = dcb->connector.entries++;
5937 if (i2c != 0xf)
5938 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 5939 }
5940
dc5bc4ed
BS		 5941 /* Fake the connector table as well as just connector indices */
5942 for (i = 0; i < dcb->connector.entries; i++) {
5943 dcb->connector.entry[i].index = i;
5944 dcb->connector.entry[i].type = divine_connector_type(bios, i);
5945 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 5946 }
5947}
5948
5949static void
5950fixup_legacy_i2c(struct nvbios *bios)
5951{
7f245b20 5952 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 5953 int i;
5954
5955 for (i = 0; i < dcb->entries; i++) {
5956 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
5957 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
5958 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
5959 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
5960 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
5961 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
5962 }
5963}
5964
5965static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5966{
5967 /*
5968 * The header following the "HWSQ" signature has the number of entries,
5969 * and the entry size
5970 *
5971 * An entry consists of a dword to write to the sequencer control reg
5972 * (0x00001304), followed by the ucode bytes, written sequentially,
5973 * starting at reg 0x00001400
5974 */
5975
5976 uint8_t bytes_to_write;
5977 uint16_t hwsq_entry_offset;
5978 int i;
5979
5980 if (bios->data[hwsq_offset] <= entry) {
5981 NV_ERROR(dev, "Too few entries in HW sequencer table for "
5982 "requested entry\n");
5983 return -ENOENT;
5984 }
5985
5986 bytes_to_write = bios->data[hwsq_offset + 1];
5987
5988 if (bytes_to_write != 36) {
5989 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
5990 return -EINVAL;
5991 }
5992
5993 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
5994
5995 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
5996
5997 /* set sequencer control */
5998 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
5999 bytes_to_write -= 4;
6000
6001 /* write ucode */
6002 for (i = 0; i < bytes_to_write; i += 4)
6003 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6004
6005 /* twiddle NV_PBUS_DEBUG_4 */
6006 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6007
6008 return 0;
6009}
6010
6011static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6012 struct nvbios *bios)
6013{
6014 /*
6015 * BMP based cards, from NV17, need a microcode loading to correctly
6016 * control the GPIO etc for LVDS panels
6017 *
6018 * BIT based cards seem to do this directly in the init scripts
6019 *
6020 * The microcode entries are found by the "HWSQ" signature.
6021 */
6022
6023 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6024 const int sz = sizeof(hwsq_signature);
6025 int hwsq_offset;
6026
6027 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6028 if (!hwsq_offset)
6029 return 0;
6030
6031 /* always use entry 0? */
6032 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6033}
6034
6035uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6036{
6037 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6038 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6039 const uint8_t edid_sig[] = {
6040 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6041 uint16_t offset = 0;
6042 uint16_t newoffset;
6043 int searchlen = NV_PROM_SIZE;
6044
6045 if (bios->fp.edid)
6046 return bios->fp.edid;
6047
6048 while (searchlen) {
6049 newoffset = findstr(&bios->data[offset], searchlen,
6050 edid_sig, 8);
6051 if (!newoffset)
6052 return NULL;
6053 offset += newoffset;
6054 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6055 break;
6056
6057 searchlen -= offset;
6058 offset++;
6059 }
6060
6061 NV_TRACE(dev, "Found EDID in BIOS\n");
6062
6063 return bios->fp.edid = &bios->data[offset];
6064}
6065
6066void
6067nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6068 struct dcb_entry *dcbent)
6069{
6070 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6071 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6072 struct init_exec iexec = { true, false };
6073
d9184fa9 6074 mutex_lock(&bios->lock);
6ee73861
BS		 6075 bios->display.output = dcbent;
6076 parse_init_table(bios, table, &iexec);
6077 bios->display.output = NULL;
d9184fa9 6078 mutex_unlock(&bios->lock);
6ee73861
BS		 6079}
6080
6081static bool NVInitVBIOS(struct drm_device *dev)
6082{
6083 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6084 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6085
6086 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 6087 mutex_init(&bios->lock);
6ee73861
BS		 6088 bios->dev = dev;
6089
6090 if (!NVShadowVBIOS(dev, bios->data))
6091 return false;
6092
6093 bios->length = NV_PROM_SIZE;
6094 return true;
6095}
6096
6097static int nouveau_parse_vbios_struct(struct drm_device *dev)
6098{
6099 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6100 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6101 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6102 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6103 int offset;
6104
6105 offset = findstr(bios->data, bios->length,
6106 bit_signature, sizeof(bit_signature));
6107 if (offset) {
6108 NV_TRACE(dev, "BIT BIOS found\n");
6109 return parse_bit_structure(bios, offset + 6);
6110 }
6111
6112 offset = findstr(bios->data, bios->length,
6113 bmp_signature, sizeof(bmp_signature));
6114 if (offset) {
6115 NV_TRACE(dev, "BMP BIOS found\n");
6116 return parse_bmp_structure(dev, bios, offset);
6117 }
6118
6119 NV_ERROR(dev, "No known BIOS signature found\n");
6120 return -ENODEV;
6121}
6122
6123int
6124nouveau_run_vbios_init(struct drm_device *dev)
6125{
6126 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6127 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6128 int i, ret = 0;
6129
6130 NVLockVgaCrtcs(dev, false);
6131 if (nv_two_heads(dev))
6132 NVSetOwner(dev, bios->state.crtchead);
6133
6134 if (bios->major_version < 5) /* BMP only */
6135 load_nv17_hw_sequencer_ucode(dev, bios);
6136
6137 if (bios->execute) {
6138 bios->fp.last_script_invoc = 0;
6139 bios->fp.lvds_init_run = false;
6140 }
6141
6142 parse_init_tables(bios);
6143
6144 /*
6145 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6146 * parser will run this right after the init tables, the binary
6147 * driver appears to run it at some point later.
6148 */
6149 if (bios->some_script_ptr) {
6150 struct init_exec iexec = {true, false};
6151
6152 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6153 bios->some_script_ptr);
6154 parse_init_table(bios, bios->some_script_ptr, &iexec);
6155 }
6156
6157 if (dev_priv->card_type >= NV_50) {
7f245b20 6158 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6159 nouveau_bios_run_display_table(dev,
7f245b20 6160 &bios->dcb.entry[i],
6ee73861
BS		 6161 0, 0);
6162 }
6163 }
6164
6165 NVLockVgaCrtcs(dev, true);
6166
6167 return ret;
6168}
6169
6170static void
6171nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6172{
6173 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6174 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6175 struct dcb_i2c_entry *entry;
6176 int i;
6177
7f245b20 6178 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6179 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6180 nouveau_i2c_fini(dev, entry);
6181}
6182
6183int
6184nouveau_bios_init(struct drm_device *dev)
6185{
6186 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6187 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6188 uint32_t saved_nv_pextdev_boot_0;
6189 bool was_locked;
6190 int ret;
6191
6ee73861
BS		 6192 if (!NVInitVBIOS(dev))
6193 return -ENODEV;
6194
6195 ret = nouveau_parse_vbios_struct(dev);
6196 if (ret)
6197 return ret;
6198
6199 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6200 if (ret)
6201 return ret;
6202
6203 fixup_legacy_i2c(bios);
6204 fixup_legacy_connector(bios);
6205
6206 if (!bios->major_version) /* we don't run version 0 bios */
6207 return 0;
6208
6209 /* these will need remembering across a suspend */
6210 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6211 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6212
6213 /* init script execution disabled */
6214 bios->execute = false;
6215
6216 /* ... unless card isn't POSTed already */
6217 if (dev_priv->card_type >= NV_10 &&
6218 NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6219 NVReadVgaCrtc(dev, 0, 0x1a) == 0) {
6220 NV_INFO(dev, "Adaptor not initialised\n");
6221 if (dev_priv->card_type < NV_50) {
6222 NV_ERROR(dev, "Unable to POST this chipset\n");
6223 return -ENODEV;
6224 }
6225
6226 NV_INFO(dev, "Running VBIOS init tables\n");
6227 bios->execute = true;
6228 }
6229
6230 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6231
6232 ret = nouveau_run_vbios_init(dev);
04a39c57 6233 if (ret)
6ee73861 6234 return ret;
6ee73861
BS		 6235
6236 /* feature_byte on BMP is poor, but init always sets CR4B */
6237 was_locked = NVLockVgaCrtcs(dev, false);
6238 if (bios->major_version < 5)
6239 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6240
6241 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6242 if (bios->is_mobile || bios->major_version >= 5)
6243 ret = parse_fp_mode_table(dev, bios);
6244 NVLockVgaCrtcs(dev, was_locked);
6245
6246 /* allow subsequent scripts to execute */
6247 bios->execute = true;
6248
6249 return 0;
6250}
6251
6252void
6253nouveau_bios_takedown(struct drm_device *dev)
6254{
6255 nouveau_bios_i2c_devices_takedown(dev);
6256}
Clone of davem's net-next-2.6 tree