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drm/i915: Fix SDVO command debug function
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
29#include <linux/delay.h>
30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
36#include "intel_sdvo_regs.h"
37
38#undef SDVO_DEBUG
39
40struct intel_sdvo_priv {
41 struct intel_i2c_chan *i2c_bus;
42 int slaveaddr;
e2f0ba97
JB		 43
44 /* Register for the SDVO device: SDVOB or SDVOC */
79e53945
JB		 45 int output_device;
46
e2f0ba97
JB		 47 /* Active outputs controlled by this SDVO output */
48 uint16_t controlled_output;
79e53945 49
e2f0ba97
JB		 50 /*
51 * Capabilities of the SDVO device returned by
52 * i830_sdvo_get_capabilities()
53 */
79e53945 54 struct intel_sdvo_caps caps;
e2f0ba97
JB		 55
56 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 57 int pixel_clock_min, pixel_clock_max;
58
e2f0ba97
JB		 59 /**
60 * This is set if we're going to treat the device as TV-out.
61 *
62 * While we have these nice friendly flags for output types that ought
63 * to decide this for us, the S-Video output on our HDMI+S-Video card
64 * shows up as RGB1 (VGA).
65 */
66 bool is_tv;
67
68 /**
69 * This is set if we treat the device as HDMI, instead of DVI.
70 */
71 bool is_hdmi;
72
73 /**
74 * Returned SDTV resolutions allowed for the current format, if the
75 * device reported it.
76 */
77 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
78
79 /**
80 * Current selected TV format.
81 *
82 * This is stored in the same structure that's passed to the device, for
83 * convenience.
84 */
85 struct intel_sdvo_tv_format tv_format;
86
87 /*
88 * supported encoding mode, used to determine whether HDMI is
89 * supported
90 */
91 struct intel_sdvo_encode encode;
92
93 /* DDC bus used by this SDVO output */
94 uint8_t ddc_bus;
95
79e53945
JB		 96 int save_sdvo_mult;
97 u16 save_active_outputs;
98 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
99 struct intel_sdvo_dtd save_output_dtd[16];
100 u32 save_SDVOX;
101};
102
103/**
104 * Writes the SDVOB or SDVOC with the given value, but always writes both
105 * SDVOB and SDVOC to work around apparent hardware issues (according to
106 * comments in the BIOS).
107 */
b358d0a6 108static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
79e53945
JB		 109{
110 struct drm_device *dev = intel_output->base.dev;
111 struct drm_i915_private *dev_priv = dev->dev_private;
112 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
113 u32 bval = val, cval = val;
114 int i;
115
116 if (sdvo_priv->output_device == SDVOB) {
117 cval = I915_READ(SDVOC);
118 } else {
119 bval = I915_READ(SDVOB);
120 }
121 /*
122 * Write the registers twice for luck. Sometimes,
123 * writing them only once doesn't appear to 'stick'.
124 * The BIOS does this too. Yay, magic
125 */
126 for (i = 0; i < 2; i++)
127 {
128 I915_WRITE(SDVOB, bval);
129 I915_READ(SDVOB);
130 I915_WRITE(SDVOC, cval);
131 I915_READ(SDVOC);
132 }
133}
134
135static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
136 u8 *ch)
137{
138 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
139 u8 out_buf[2];
140 u8 buf[2];
141 int ret;
142
143 struct i2c_msg msgs[] = {
144 {
145 .addr = sdvo_priv->i2c_bus->slave_addr,
146 .flags = 0,
147 .len = 1,
148 .buf = out_buf,
149 },
150 {
151 .addr = sdvo_priv->i2c_bus->slave_addr,
152 .flags = I2C_M_RD,
153 .len = 1,
154 .buf = buf,
155 }
156 };
157
158 out_buf[0] = addr;
159 out_buf[1] = 0;
160
161 if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
162 {
163 *ch = buf[0];
164 return true;
165 }
166
167 DRM_DEBUG("i2c transfer returned %d\n", ret);
168 return false;
169}
170
171static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
172 u8 ch)
173{
174 u8 out_buf[2];
175 struct i2c_msg msgs[] = {
176 {
177 .addr = intel_output->i2c_bus->slave_addr,
178 .flags = 0,
179 .len = 2,
180 .buf = out_buf,
181 }
182 };
183
184 out_buf[0] = addr;
185 out_buf[1] = ch;
186
187 if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
188 {
189 return true;
190 }
191 return false;
192}
193
194#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
195/** Mapping of command numbers to names, for debug output */
005568be 196static const struct _sdvo_cmd_name {
e2f0ba97
JB		 197 u8 cmd;
198 char *name;
79e53945
JB		 199} sdvo_cmd_names[] = {
200 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
201 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
202 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
203 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
204 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
205 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
206 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
207 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
208 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
209 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
210 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
211 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
212 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
213 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
214 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
215 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
216 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
217 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
218 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
219 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
220 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
221 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
222 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
223 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
224 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
225 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
226 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
227 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
228 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
229 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
230 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
231 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
232 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
233 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
234 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 235 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
236 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
237 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
238 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 239 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 240 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
241 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
242 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
243 /* HDMI op code */
244 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
245 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
246 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
247 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
248 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
249 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
250 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
251 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
252 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
253 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
254 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
255 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
256 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
257 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
258 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
259 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
260 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
261 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
262 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 264};
265
266#define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
267#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
268
269#ifdef SDVO_DEBUG
270static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
271 void *args, int args_len)
272{
273 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
274 int i;
275
33b52961 276 printk(KERN_DEBUG "%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
79e53945 277 for (i = 0; i < args_len; i++)
33b52961 278 printk(KERN_DEBUG "%02X ", ((u8 *)args)[i]);
79e53945 279 for (; i < 8; i++)
33b52961 280 printk(KERN_DEBUG " ");
79e53945
JB		 281 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
282 if (cmd == sdvo_cmd_names[i].cmd) {
33b52961 283 printk(KERN_DEBUG "(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 284 break;
285 }
286 }
287 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
33b52961
ZW		 288 printk(KERN_DEBUG "(%02X)", cmd);
289 printk(KERN_DEBUG "\n");
79e53945
JB		 290}
291#else
292#define intel_sdvo_debug_write(o, c, a, l)
293#endif
294
295static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
296 void *args, int args_len)
297{
298 int i;
299
300 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
301
302 for (i = 0; i < args_len; i++) {
303 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
304 ((u8*)args)[i]);
305 }
306
307 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
308}
309
310#ifdef SDVO_DEBUG
311static const char *cmd_status_names[] = {
312 "Power on",
313 "Success",
314 "Not supported",
315 "Invalid arg",
316 "Pending",
317 "Target not specified",
318 "Scaling not supported"
319};
320
321static void intel_sdvo_debug_response(struct intel_output *intel_output,
322 void *response, int response_len,
323 u8 status)
324{
325 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
33b52961 326 int i;
79e53945 327
33b52961 328 printk(KERN_DEBUG "%s: R: ", SDVO_NAME(sdvo_priv));
79e53945 329 for (i = 0; i < response_len; i++)
33b52961 330 printk(KERN_DEBUG "%02X ", ((u8 *)response)[i]);
79e53945 331 for (; i < 8; i++)
33b52961 332 printk(KERN_DEBUG " ");
79e53945 333 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
33b52961 334 printk(KERN_DEBUG "(%s)", cmd_status_names[status]);
79e53945 335 else
33b52961
ZW		 336 printk(KERN_DEBUG "(??? %d)", status);
337 printk(KERN_DEBUG "\n");
79e53945
JB		 338}
339#else
340#define intel_sdvo_debug_response(o, r, l, s)
341#endif
342
343static u8 intel_sdvo_read_response(struct intel_output *intel_output,
344 void *response, int response_len)
345{
346 int i;
347 u8 status;
348 u8 retry = 50;
349
350 while (retry--) {
351 /* Read the command response */
352 for (i = 0; i < response_len; i++) {
353 intel_sdvo_read_byte(intel_output,
354 SDVO_I2C_RETURN_0 + i,
355 &((u8 *)response)[i]);
356 }
357
358 /* read the return status */
359 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
360 &status);
361
362 intel_sdvo_debug_response(intel_output, response, response_len,
363 status);
364 if (status != SDVO_CMD_STATUS_PENDING)
365 return status;
366
367 mdelay(50);
368 }
369
370 return status;
371}
372
b358d0a6 373static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 374{
375 if (mode->clock >= 100000)
376 return 1;
377 else if (mode->clock >= 50000)
378 return 2;
379 else
380 return 4;
381}
382
383/**
384 * Don't check status code from this as it switches the bus back to the
385 * SDVO chips which defeats the purpose of doing a bus switch in the first
386 * place.
387 */
b358d0a6
HE		 388static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
389 u8 target)
79e53945
JB		 390{
391 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
392}
393
394static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
395{
396 struct intel_sdvo_set_target_input_args targets = {0};
397 u8 status;
398
399 if (target_0 && target_1)
400 return SDVO_CMD_STATUS_NOTSUPP;
401
402 if (target_1)
403 targets.target_1 = 1;
404
405 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
406 sizeof(targets));
407
408 status = intel_sdvo_read_response(intel_output, NULL, 0);
409
410 return (status == SDVO_CMD_STATUS_SUCCESS);
411}
412
413/**
414 * Return whether each input is trained.
415 *
416 * This function is making an assumption about the layout of the response,
417 * which should be checked against the docs.
418 */
419static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
420{
421 struct intel_sdvo_get_trained_inputs_response response;
422 u8 status;
423
424 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
425 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
426 if (status != SDVO_CMD_STATUS_SUCCESS)
427 return false;
428
429 *input_1 = response.input0_trained;
430 *input_2 = response.input1_trained;
431 return true;
432}
433
434static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
435 u16 *outputs)
436{
437 u8 status;
438
439 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
440 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
441
442 return (status == SDVO_CMD_STATUS_SUCCESS);
443}
444
445static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
446 u16 outputs)
447{
448 u8 status;
449
450 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
451 sizeof(outputs));
452 status = intel_sdvo_read_response(intel_output, NULL, 0);
453 return (status == SDVO_CMD_STATUS_SUCCESS);
454}
455
456static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
457 int mode)
458{
459 u8 status, state = SDVO_ENCODER_STATE_ON;
460
461 switch (mode) {
462 case DRM_MODE_DPMS_ON:
463 state = SDVO_ENCODER_STATE_ON;
464 break;
465 case DRM_MODE_DPMS_STANDBY:
466 state = SDVO_ENCODER_STATE_STANDBY;
467 break;
468 case DRM_MODE_DPMS_SUSPEND:
469 state = SDVO_ENCODER_STATE_SUSPEND;
470 break;
471 case DRM_MODE_DPMS_OFF:
472 state = SDVO_ENCODER_STATE_OFF;
473 break;
474 }
475
476 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
477 sizeof(state));
478 status = intel_sdvo_read_response(intel_output, NULL, 0);
479
480 return (status == SDVO_CMD_STATUS_SUCCESS);
481}
482
483static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
484 int *clock_min,
485 int *clock_max)
486{
487 struct intel_sdvo_pixel_clock_range clocks;
488 u8 status;
489
490 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
491 NULL, 0);
492
493 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
494
495 if (status != SDVO_CMD_STATUS_SUCCESS)
496 return false;
497
498 /* Convert the values from units of 10 kHz to kHz. */
499 *clock_min = clocks.min * 10;
500 *clock_max = clocks.max * 10;
501
502 return true;
503}
504
505static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
506 u16 outputs)
507{
508 u8 status;
509
510 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
511 sizeof(outputs));
512
513 status = intel_sdvo_read_response(intel_output, NULL, 0);
514 return (status == SDVO_CMD_STATUS_SUCCESS);
515}
516
517static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
518 struct intel_sdvo_dtd *dtd)
519{
520 u8 status;
521
522 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
523 status = intel_sdvo_read_response(intel_output, &dtd->part1,
524 sizeof(dtd->part1));
525 if (status != SDVO_CMD_STATUS_SUCCESS)
526 return false;
527
528 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
529 status = intel_sdvo_read_response(intel_output, &dtd->part2,
530 sizeof(dtd->part2));
531 if (status != SDVO_CMD_STATUS_SUCCESS)
532 return false;
533
534 return true;
535}
536
537static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
538 struct intel_sdvo_dtd *dtd)
539{
540 return intel_sdvo_get_timing(intel_output,
541 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
542}
543
544static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
545 struct intel_sdvo_dtd *dtd)
546{
547 return intel_sdvo_get_timing(intel_output,
548 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
549}
550
551static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
552 struct intel_sdvo_dtd *dtd)
553{
554 u8 status;
555
556 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
557 status = intel_sdvo_read_response(intel_output, NULL, 0);
558 if (status != SDVO_CMD_STATUS_SUCCESS)
559 return false;
560
561 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
562 status = intel_sdvo_read_response(intel_output, NULL, 0);
563 if (status != SDVO_CMD_STATUS_SUCCESS)
564 return false;
565
566 return true;
567}
568
569static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
570 struct intel_sdvo_dtd *dtd)
571{
572 return intel_sdvo_set_timing(intel_output,
573 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
574}
575
576static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
577 struct intel_sdvo_dtd *dtd)
578{
579 return intel_sdvo_set_timing(intel_output,
580 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
581}
582
e2f0ba97
JB		 583static bool
584intel_sdvo_create_preferred_input_timing(struct intel_output *output,
585 uint16_t clock,
586 uint16_t width,
587 uint16_t height)
588{
589 struct intel_sdvo_preferred_input_timing_args args;
590 uint8_t status;
591
592 args.clock = clock;
593 args.width = width;
594 args.height = height;
595 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
596 &args, sizeof(args));
597 status = intel_sdvo_read_response(output, NULL, 0);
598 if (status != SDVO_CMD_STATUS_SUCCESS)
599 return false;
600
601 return true;
602}
603
604static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
605 struct intel_sdvo_dtd *dtd)
606{
607 bool status;
608
609 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
610 NULL, 0);
611
612 status = intel_sdvo_read_response(output, &dtd->part1,
613 sizeof(dtd->part1));
614 if (status != SDVO_CMD_STATUS_SUCCESS)
615 return false;
616
617 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
618 NULL, 0);
619
620 status = intel_sdvo_read_response(output, &dtd->part2,
621 sizeof(dtd->part2));
622 if (status != SDVO_CMD_STATUS_SUCCESS)
623 return false;
624
625 return false;
626}
79e53945
JB		 627
628static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
629{
630 u8 response, status;
631
632 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
633 status = intel_sdvo_read_response(intel_output, &response, 1);
634
635 if (status != SDVO_CMD_STATUS_SUCCESS) {
636 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
637 return SDVO_CLOCK_RATE_MULT_1X;
638 } else {
639 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
640 }
641
642 return response;
643}
644
645static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
646{
647 u8 status;
648
649 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
650 status = intel_sdvo_read_response(intel_output, NULL, 0);
651 if (status != SDVO_CMD_STATUS_SUCCESS)
652 return false;
653
654 return true;
655}
656
e2f0ba97
JB		 657static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
658 struct drm_display_mode *mode)
79e53945 659{
e2f0ba97
JB		 660 uint16_t width, height;
661 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
662 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 663
664 width = mode->crtc_hdisplay;
665 height = mode->crtc_vdisplay;
666
667 /* do some mode translations */
668 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
669 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
670
671 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
672 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
673
674 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
675 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
676
e2f0ba97
JB		 677 dtd->part1.clock = mode->clock / 10;
678 dtd->part1.h_active = width & 0xff;
679 dtd->part1.h_blank = h_blank_len & 0xff;
680 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 681 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 682 dtd->part1.v_active = height & 0xff;
683 dtd->part1.v_blank = v_blank_len & 0xff;
684 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 685 ((v_blank_len >> 8) & 0xf);
686
e2f0ba97
JB		 687 dtd->part2.h_sync_off = h_sync_offset;
688 dtd->part2.h_sync_width = h_sync_len & 0xff;
689 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 690 (v_sync_len & 0xf);
e2f0ba97 691 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 692 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
693 ((v_sync_len & 0x30) >> 4);
694
e2f0ba97 695 dtd->part2.dtd_flags = 0x18;
79e53945 696 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 697 dtd->part2.dtd_flags |= 0x2;
79e53945 698 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 699 dtd->part2.dtd_flags |= 0x4;
700
701 dtd->part2.sdvo_flags = 0;
702 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
703 dtd->part2.reserved = 0;
704}
705
706static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
707 struct intel_sdvo_dtd *dtd)
708{
709 uint16_t width, height;
710 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
711 uint16_t h_sync_offset, v_sync_offset;
712
713 width = mode->crtc_hdisplay;
714 height = mode->crtc_vdisplay;
715
716 /* do some mode translations */
717 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
718 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
719
720 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
721 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
722
723 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
724 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
725
726 mode->hdisplay = dtd->part1.h_active;
727 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
728 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
729 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xa0) << 2;
730 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
731 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
732 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
733 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
734
735 mode->vdisplay = dtd->part1.v_active;
736 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
737 mode->vsync_start = mode->vdisplay;
738 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
739 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0a) << 2;
740 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
741 mode->vsync_end = mode->vsync_start +
742 (dtd->part2.v_sync_off_width & 0xf);
743 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
744 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
745 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
746
747 mode->clock = dtd->part1.clock * 10;
748
749 mode->flags &= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
750 if (dtd->part2.dtd_flags & 0x2)
751 mode->flags |= DRM_MODE_FLAG_PHSYNC;
752 if (dtd->part2.dtd_flags & 0x4)
753 mode->flags |= DRM_MODE_FLAG_PVSYNC;
754}
755
756static bool intel_sdvo_get_supp_encode(struct intel_output *output,
757 struct intel_sdvo_encode *encode)
758{
759 uint8_t status;
760
761 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
762 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
763 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
764 memset(encode, 0, sizeof(*encode));
765 return false;
766 }
767
768 return true;
769}
770
771static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
772{
773 uint8_t status;
774
775 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
776 status = intel_sdvo_read_response(output, NULL, 0);
777
778 return (status == SDVO_CMD_STATUS_SUCCESS);
779}
780
781static bool intel_sdvo_set_colorimetry(struct intel_output *output,
782 uint8_t mode)
783{
784 uint8_t status;
785
786 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
787 status = intel_sdvo_read_response(output, NULL, 0);
788
789 return (status == SDVO_CMD_STATUS_SUCCESS);
790}
791
792#if 0
793static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
794{
795 int i, j;
796 uint8_t set_buf_index[2];
797 uint8_t av_split;
798 uint8_t buf_size;
799 uint8_t buf[48];
800 uint8_t *pos;
801
802 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
803 intel_sdvo_read_response(output, &av_split, 1);
804
805 for (i = 0; i <= av_split; i++) {
806 set_buf_index[0] = i; set_buf_index[1] = 0;
807 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
808 set_buf_index, 2);
809 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
810 intel_sdvo_read_response(output, &buf_size, 1);
811
812 pos = buf;
813 for (j = 0; j <= buf_size; j += 8) {
814 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
815 NULL, 0);
816 intel_sdvo_read_response(output, pos, 8);
817 pos += 8;
818 }
819 }
820}
821#endif
822
823static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
824 uint8_t *data, int8_t size, uint8_t tx_rate)
825{
826 uint8_t set_buf_index[2];
827
828 set_buf_index[0] = index;
829 set_buf_index[1] = 0;
830
831 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
832
833 for (; size > 0; size -= 8) {
834 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
835 data += 8;
836 }
837
838 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
839}
840
841static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
842{
843 uint8_t csum = 0;
844 int i;
845
846 for (i = 0; i < size; i++)
847 csum += data[i];
848
849 return 0x100 - csum;
850}
851
852#define DIP_TYPE_AVI 0x82
853#define DIP_VERSION_AVI 0x2
854#define DIP_LEN_AVI 13
855
856struct dip_infoframe {
857 uint8_t type;
858 uint8_t version;
859 uint8_t len;
860 uint8_t checksum;
861 union {
862 struct {
863 /* Packet Byte #1 */
864 uint8_t S:2;
865 uint8_t B:2;
866 uint8_t A:1;
867 uint8_t Y:2;
868 uint8_t rsvd1:1;
869 /* Packet Byte #2 */
870 uint8_t R:4;
871 uint8_t M:2;
872 uint8_t C:2;
873 /* Packet Byte #3 */
874 uint8_t SC:2;
875 uint8_t Q:2;
876 uint8_t EC:3;
877 uint8_t ITC:1;
878 /* Packet Byte #4 */
879 uint8_t VIC:7;
880 uint8_t rsvd2:1;
881 /* Packet Byte #5 */
882 uint8_t PR:4;
883 uint8_t rsvd3:4;
884 /* Packet Byte #6~13 */
885 uint16_t top_bar_end;
886 uint16_t bottom_bar_start;
887 uint16_t left_bar_end;
888 uint16_t right_bar_start;
889 } avi;
890 struct {
891 /* Packet Byte #1 */
892 uint8_t channel_count:3;
893 uint8_t rsvd1:1;
894 uint8_t coding_type:4;
895 /* Packet Byte #2 */
896 uint8_t sample_size:2; /* SS0, SS1 */
897 uint8_t sample_frequency:3;
898 uint8_t rsvd2:3;
899 /* Packet Byte #3 */
900 uint8_t coding_type_private:5;
901 uint8_t rsvd3:3;
902 /* Packet Byte #4 */
903 uint8_t channel_allocation;
904 /* Packet Byte #5 */
905 uint8_t rsvd4:3;
906 uint8_t level_shift:4;
907 uint8_t downmix_inhibit:1;
908 } audio;
909 uint8_t payload[28];
910 } __attribute__ ((packed)) u;
911} __attribute__((packed));
912
913static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
914 struct drm_display_mode * mode)
915{
916 struct dip_infoframe avi_if = {
917 .type = DIP_TYPE_AVI,
918 .version = DIP_VERSION_AVI,
919 .len = DIP_LEN_AVI,
920 };
921
922 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
923 4 + avi_if.len);
924 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
925 SDVO_HBUF_TX_VSYNC);
926}
927
928static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
929 struct drm_display_mode *mode,
930 struct drm_display_mode *adjusted_mode)
931{
932 struct intel_output *output = enc_to_intel_output(encoder);
933 struct intel_sdvo_priv *dev_priv = output->dev_priv;
79e53945 934
e2f0ba97
JB		 935 if (!dev_priv->is_tv) {
936 /* Make the CRTC code factor in the SDVO pixel multiplier. The
937 * SDVO device will be told of the multiplier during mode_set.
938 */
939 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
940 } else {
941 struct intel_sdvo_dtd output_dtd;
942 bool success;
943
944 /* We need to construct preferred input timings based on our
945 * output timings. To do that, we have to set the output
946 * timings, even though this isn't really the right place in
947 * the sequence to do it. Oh well.
948 */
949
950
951 /* Set output timings */
952 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
953 intel_sdvo_set_target_output(output,
954 dev_priv->controlled_output);
955 intel_sdvo_set_output_timing(output, &output_dtd);
956
957 /* Set the input timing to the screen. Assume always input 0. */
958 intel_sdvo_set_target_input(output, true, false);
959
960
961 success = intel_sdvo_create_preferred_input_timing(output,
962 mode->clock / 10,
963 mode->hdisplay,
964 mode->vdisplay);
965 if (success) {
966 struct intel_sdvo_dtd input_dtd;
79e53945 967
e2f0ba97
JB		 968 intel_sdvo_get_preferred_input_timing(output,
969 &input_dtd);
970 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
971
972 } else {
973 return false;
974 }
975 }
976 return true;
977}
978
979static void intel_sdvo_mode_set(struct drm_encoder *encoder,
980 struct drm_display_mode *mode,
981 struct drm_display_mode *adjusted_mode)
982{
983 struct drm_device *dev = encoder->dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 struct drm_crtc *crtc = encoder->crtc;
986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
987 struct intel_output *output = enc_to_intel_output(encoder);
988 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
989 u32 sdvox = 0;
990 int sdvo_pixel_multiply;
991 struct intel_sdvo_in_out_map in_out;
992 struct intel_sdvo_dtd input_dtd;
993 u8 status;
994
995 if (!mode)
996 return;
997
998 /* First, set the input mapping for the first input to our controlled
999 * output. This is only correct if we're a single-input device, in
1000 * which case the first input is the output from the appropriate SDVO
1001 * channel on the motherboard. In a two-input device, the first input
1002 * will be SDVOB and the second SDVOC.
1003 */
1004 in_out.in0 = sdvo_priv->controlled_output;
1005 in_out.in1 = 0;
1006
1007 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1008 &in_out, sizeof(in_out));
1009 status = intel_sdvo_read_response(output, NULL, 0);
1010
1011 if (sdvo_priv->is_hdmi) {
1012 intel_sdvo_set_avi_infoframe(output, mode);
1013 sdvox |= SDVO_AUDIO_ENABLE;
1014 }
1015
1016 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1017
1018 /* If it's a TV, we already set the output timing in mode_fixup.
1019 * Otherwise, the output timing is equal to the input timing.
1020 */
1021 if (!sdvo_priv->is_tv) {
1022 /* Set the output timing to the screen */
1023 intel_sdvo_set_target_output(output,
1024 sdvo_priv->controlled_output);
1025 intel_sdvo_set_output_timing(output, &input_dtd);
1026 }
79e53945
JB		 1027
1028 /* Set the input timing to the screen. Assume always input 0. */
e2f0ba97 1029 intel_sdvo_set_target_input(output, true, false);
79e53945 1030
e2f0ba97 1031 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1032 * provide the device with a timing it can support, if it supports that
1033 * feature. However, presumably we would need to adjust the CRTC to
1034 * output the preferred timing, and we don't support that currently.
1035 */
e2f0ba97
JB		 1036#if 0
1037 success = intel_sdvo_create_preferred_input_timing(output, clock,
1038 width, height);
1039 if (success) {
1040 struct intel_sdvo_dtd *input_dtd;
1041
1042 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1043 intel_sdvo_set_input_timing(output, &input_dtd);
1044 }
1045#else
1046 intel_sdvo_set_input_timing(output, &input_dtd);
1047#endif
79e53945
JB		 1048
1049 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1050 case 1:
e2f0ba97 1051 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1052 SDVO_CLOCK_RATE_MULT_1X);
1053 break;
1054 case 2:
e2f0ba97 1055 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1056 SDVO_CLOCK_RATE_MULT_2X);
1057 break;
1058 case 4:
e2f0ba97 1059 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1060 SDVO_CLOCK_RATE_MULT_4X);
1061 break;
1062 }
1063
1064 /* Set the SDVO control regs. */
e2f0ba97
JB		 1065 if (IS_I965G(dev)) {
1066 sdvox |= SDVO_BORDER_ENABLE |
1067 SDVO_VSYNC_ACTIVE_HIGH |
1068 SDVO_HSYNC_ACTIVE_HIGH;
1069 } else {
1070 sdvox |= I915_READ(sdvo_priv->output_device);
1071 switch (sdvo_priv->output_device) {
1072 case SDVOB:
1073 sdvox &= SDVOB_PRESERVE_MASK;
1074 break;
1075 case SDVOC:
1076 sdvox &= SDVOC_PRESERVE_MASK;
1077 break;
1078 }
1079 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1080 }
79e53945
JB		 1081 if (intel_crtc->pipe == 1)
1082 sdvox |= SDVO_PIPE_B_SELECT;
1083
1084 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1085 if (IS_I965G(dev)) {
e2f0ba97
JB		 1086 /* done in crtc_mode_set as the dpll_md reg must be written early */
1087 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1088 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1089 } else {
1090 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1091 }
1092
e2f0ba97 1093 intel_sdvo_write_sdvox(output, sdvox);
79e53945
JB		 1094}
1095
1096static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1097{
1098 struct drm_device *dev = encoder->dev;
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 struct intel_output *intel_output = enc_to_intel_output(encoder);
1101 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1102 u32 temp;
1103
1104 if (mode != DRM_MODE_DPMS_ON) {
1105 intel_sdvo_set_active_outputs(intel_output, 0);
1106 if (0)
1107 intel_sdvo_set_encoder_power_state(intel_output, mode);
1108
1109 if (mode == DRM_MODE_DPMS_OFF) {
1110 temp = I915_READ(sdvo_priv->output_device);
1111 if ((temp & SDVO_ENABLE) != 0) {
1112 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1113 }
1114 }
1115 } else {
1116 bool input1, input2;
1117 int i;
1118 u8 status;
1119
1120 temp = I915_READ(sdvo_priv->output_device);
1121 if ((temp & SDVO_ENABLE) == 0)
1122 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1123 for (i = 0; i < 2; i++)
1124 intel_wait_for_vblank(dev);
1125
1126 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1127 &input2);
1128
1129
1130 /* Warn if the device reported failure to sync.
1131 * A lot of SDVO devices fail to notify of sync, but it's
1132 * a given it the status is a success, we succeeded.
1133 */
1134 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1135 DRM_DEBUG("First %s output reported failure to sync\n",
1136 SDVO_NAME(sdvo_priv));
1137 }
1138
1139 if (0)
1140 intel_sdvo_set_encoder_power_state(intel_output, mode);
e2f0ba97 1141 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
79e53945
JB		 1142 }
1143 return;
1144}
1145
1146static void intel_sdvo_save(struct drm_connector *connector)
1147{
1148 struct drm_device *dev = connector->dev;
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150 struct intel_output *intel_output = to_intel_output(connector);
1151 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1152 int o;
1153
1154 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1155 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1156
1157 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1158 intel_sdvo_set_target_input(intel_output, true, false);
1159 intel_sdvo_get_input_timing(intel_output,
1160 &sdvo_priv->save_input_dtd_1);
1161 }
1162
1163 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1164 intel_sdvo_set_target_input(intel_output, false, true);
1165 intel_sdvo_get_input_timing(intel_output,
1166 &sdvo_priv->save_input_dtd_2);
1167 }
1168
1169 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1170 {
1171 u16 this_output = (1 << o);
1172 if (sdvo_priv->caps.output_flags & this_output)
1173 {
1174 intel_sdvo_set_target_output(intel_output, this_output);
1175 intel_sdvo_get_output_timing(intel_output,
1176 &sdvo_priv->save_output_dtd[o]);
1177 }
1178 }
e2f0ba97
JB		 1179 if (sdvo_priv->is_tv) {
1180 /* XXX: Save TV format/enhancements. */
1181 }
79e53945
JB		 1182
1183 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1184}
1185
1186static void intel_sdvo_restore(struct drm_connector *connector)
1187{
1188 struct drm_device *dev = connector->dev;
79e53945
JB		 1189 struct intel_output *intel_output = to_intel_output(connector);
1190 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1191 int o;
1192 int i;
1193 bool input1, input2;
1194 u8 status;
1195
1196 intel_sdvo_set_active_outputs(intel_output, 0);
1197
1198 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1199 {
1200 u16 this_output = (1 << o);
1201 if (sdvo_priv->caps.output_flags & this_output) {
1202 intel_sdvo_set_target_output(intel_output, this_output);
1203 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1204 }
1205 }
1206
1207 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1208 intel_sdvo_set_target_input(intel_output, true, false);
1209 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1210 }
1211
1212 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1213 intel_sdvo_set_target_input(intel_output, false, true);
1214 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1215 }
1216
1217 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1218
e2f0ba97
JB		 1219 if (sdvo_priv->is_tv) {
1220 /* XXX: Restore TV format/enhancements. */
1221 }
1222
1223 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
79e53945
JB		 1224
1225 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1226 {
1227 for (i = 0; i < 2; i++)
1228 intel_wait_for_vblank(dev);
1229 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1230 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1231 DRM_DEBUG("First %s output reported failure to sync\n",
1232 SDVO_NAME(sdvo_priv));
1233 }
1234
1235 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1236}
1237
1238static int intel_sdvo_mode_valid(struct drm_connector *connector,
1239 struct drm_display_mode *mode)
1240{
1241 struct intel_output *intel_output = to_intel_output(connector);
1242 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1243
1244 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1245 return MODE_NO_DBLESCAN;
1246
1247 if (sdvo_priv->pixel_clock_min > mode->clock)
1248 return MODE_CLOCK_LOW;
1249
1250 if (sdvo_priv->pixel_clock_max < mode->clock)
1251 return MODE_CLOCK_HIGH;
1252
1253 return MODE_OK;
1254}
1255
1256static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1257{
1258 u8 status;
1259
1260 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1261 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1262 if (status != SDVO_CMD_STATUS_SUCCESS)
1263 return false;
1264
1265 return true;
1266}
1267
1268struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1269{
1270 struct drm_connector *connector = NULL;
1271 struct intel_output *iout = NULL;
1272 struct intel_sdvo_priv *sdvo;
1273
1274 /* find the sdvo connector */
1275 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1276 iout = to_intel_output(connector);
1277
1278 if (iout->type != INTEL_OUTPUT_SDVO)
1279 continue;
1280
1281 sdvo = iout->dev_priv;
1282
1283 if (sdvo->output_device == SDVOB && sdvoB)
1284 return connector;
1285
1286 if (sdvo->output_device == SDVOC && !sdvoB)
1287 return connector;
1288
1289 }
1290
1291 return NULL;
1292}
1293
1294int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1295{
1296 u8 response[2];
1297 u8 status;
1298 struct intel_output *intel_output;
1299 DRM_DEBUG("\n");
1300
1301 if (!connector)
1302 return 0;
1303
1304 intel_output = to_intel_output(connector);
1305
1306 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1307 status = intel_sdvo_read_response(intel_output, &response, 2);
1308
1309 if (response[0] !=0)
1310 return 1;
1311
1312 return 0;
1313}
1314
1315void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1316{
1317 u8 response[2];
1318 u8 status;
1319 struct intel_output *intel_output = to_intel_output(connector);
1320
1321 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1322 intel_sdvo_read_response(intel_output, &response, 2);
1323
1324 if (on) {
1325 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1326 status = intel_sdvo_read_response(intel_output, &response, 2);
1327
1328 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1329 } else {
1330 response[0] = 0;
1331 response[1] = 0;
1332 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1333 }
1334
1335 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1336 intel_sdvo_read_response(intel_output, &response, 2);
1337}
1338
1339static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1340{
1341 u8 response[2];
1342 u8 status;
1343 struct intel_output *intel_output = to_intel_output(connector);
1344
1345 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1346 status = intel_sdvo_read_response(intel_output, &response, 2);
1347
1348 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
e2f0ba97
JB		 1349
1350 if (status != SDVO_CMD_STATUS_SUCCESS)
1351 return connector_status_unknown;
1352
79e53945
JB		 1353 if ((response[0] != 0) || (response[1] != 0))
1354 return connector_status_connected;
1355 else
1356 return connector_status_disconnected;
1357}
1358
e2f0ba97 1359static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945
JB		 1360{
1361 struct intel_output *intel_output = to_intel_output(connector);
e2f0ba97 1362 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
79e53945
JB		 1363
1364 /* set the bus switch and get the modes */
e2f0ba97 1365 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
79e53945
JB		 1366 intel_ddc_get_modes(intel_output);
1367
e2f0ba97
JB		 1368#if 0
1369 struct drm_device *dev = encoder->dev;
1370 struct drm_i915_private *dev_priv = dev->dev_private;
1371 /* Mac mini hack. On this device, I get DDC through the analog, which
1372 * load-detects as disconnected. I fail to DDC through the SDVO DDC,
1373 * but it does load-detect as connected. So, just steal the DDC bits
1374 * from analog when we fail at finding it the right way.
1375 */
1376 crt = xf86_config->output[0];
1377 intel_output = crt->driver_private;
1378 if (intel_output->type == I830_OUTPUT_ANALOG &&
1379 crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1380 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1381 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1382 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1383 }
1384 if (edid_mon) {
1385 xf86OutputSetEDID(output, edid_mon);
1386 modes = xf86OutputGetEDIDModes(output);
1387 }
1388#endif
1389}
1390
1391/**
1392 * This function checks the current TV format, and chooses a default if
1393 * it hasn't been set.
1394 */
1395static void
1396intel_sdvo_check_tv_format(struct intel_output *output)
1397{
1398 struct intel_sdvo_priv *dev_priv = output->dev_priv;
1399 struct intel_sdvo_tv_format format, unset;
1400 uint8_t status;
1401
1402 intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1403 status = intel_sdvo_read_response(output, &format, sizeof(format));
1404 if (status != SDVO_CMD_STATUS_SUCCESS)
1405 return;
1406
1407 memset(&unset, 0, sizeof(unset));
1408 if (memcmp(&format, &unset, sizeof(format))) {
1409 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
1410 SDVO_NAME(dev_priv));
1411
1412 format.ntsc_m = true;
1413 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, NULL, 0);
1414 status = intel_sdvo_read_response(output, NULL, 0);
1415 }
1416}
1417
1418/*
1419 * Set of SDVO TV modes.
1420 * Note! This is in reply order (see loop in get_tv_modes).
1421 * XXX: all 60Hz refresh?
1422 */
1423struct drm_display_mode sdvo_tv_modes[] = {
1424 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815680, 321, 384, 416,
1425 200, 0, 232, 201, 233, 4196112, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1427 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814080, 321, 384, 416,
1428 240, 0, 272, 241, 273, 4196112, 0,
1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1430 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910080, 401, 464, 496,
1431 300, 0, 332, 301, 333, 4196112, 0,
1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1433 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913280, 641, 704, 736,
1434 350, 0, 382, 351, 383, 4196112, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1436 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121280, 641, 704, 736,
1437 400, 0, 432, 401, 433, 4196112, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1439 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121280, 641, 704, 736,
1440 400, 0, 432, 401, 433, 4196112, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1442 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624000, 705, 768, 800,
1443 480, 0, 512, 481, 513, 4196112, 0,
1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1445 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232000, 705, 768, 800,
1446 576, 0, 608, 577, 609, 4196112, 0,
1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1448 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751680, 721, 784, 816,
1449 350, 0, 382, 351, 383, 4196112, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1451 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199680, 721, 784, 816,
1452 400, 0, 432, 401, 433, 4196112, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1454 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116480, 721, 784, 816,
1455 480, 0, 512, 481, 513, 4196112, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1457 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054080, 721, 784, 816,
1458 540, 0, 572, 541, 573, 4196112, 0,
1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1460 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816640, 721, 784, 816,
1461 576, 0, 608, 577, 609, 4196112, 0,
1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1463 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570560, 769, 832, 864,
1464 576, 0, 608, 577, 609, 4196112, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1466 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030080, 801, 864, 896,
1467 600, 0, 632, 601, 633, 4196112, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1469 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581760, 833, 896, 928,
1470 624, 0, 656, 625, 657, 4196112, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1472 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707040, 921, 984, 1016,
1473 766, 0, 798, 767, 799, 4196112, 0,
1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1475 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827200, 1025, 1088, 1120,
1476 768, 0, 800, 769, 801, 4196112, 0,
1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1478 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265920, 1281, 1344, 1376,
1479 1024, 0, 1056, 1025, 1057, 4196112, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1481};
1482
1483static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1484{
1485 struct intel_output *output = to_intel_output(connector);
1486 uint32_t reply = 0;
1487 uint8_t status;
1488 int i = 0;
1489
1490 intel_sdvo_check_tv_format(output);
1491
1492 /* Read the list of supported input resolutions for the selected TV
1493 * format.
1494 */
1495 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1496 NULL, 0);
1497 status = intel_sdvo_read_response(output, &reply, 3);
1498 if (status != SDVO_CMD_STATUS_SUCCESS)
1499 return;
1500
1501 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1502 if (reply & (1 << i))
1503 drm_mode_probed_add(connector, &sdvo_tv_modes[i]);
1504}
1505
1506static int intel_sdvo_get_modes(struct drm_connector *connector)
1507{
1508 struct intel_output *output = to_intel_output(connector);
1509 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1510
1511 if (sdvo_priv->is_tv)
1512 intel_sdvo_get_tv_modes(connector);
1513 else
1514 intel_sdvo_get_ddc_modes(connector);
1515
79e53945
JB		 1516 if (list_empty(&connector->probed_modes))
1517 return 0;
1518 return 1;
1519}
1520
1521static void intel_sdvo_destroy(struct drm_connector *connector)
1522{
1523 struct intel_output *intel_output = to_intel_output(connector);
1524
1525 if (intel_output->i2c_bus)
1526 intel_i2c_destroy(intel_output->i2c_bus);
1527 drm_sysfs_connector_remove(connector);
1528 drm_connector_cleanup(connector);
1529 kfree(intel_output);
1530}
1531
1532static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1533 .dpms = intel_sdvo_dpms,
1534 .mode_fixup = intel_sdvo_mode_fixup,
1535 .prepare = intel_encoder_prepare,
1536 .mode_set = intel_sdvo_mode_set,
1537 .commit = intel_encoder_commit,
1538};
1539
1540static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1541 .save = intel_sdvo_save,
1542 .restore = intel_sdvo_restore,
1543 .detect = intel_sdvo_detect,
1544 .fill_modes = drm_helper_probe_single_connector_modes,
1545 .destroy = intel_sdvo_destroy,
1546};
1547
1548static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1549 .get_modes = intel_sdvo_get_modes,
1550 .mode_valid = intel_sdvo_mode_valid,
1551 .best_encoder = intel_best_encoder,
1552};
1553
b358d0a6 1554static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945
JB		 1555{
1556 drm_encoder_cleanup(encoder);
1557}
1558
1559static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1560 .destroy = intel_sdvo_enc_destroy,
1561};
1562
1563
e2f0ba97
JB		 1564/**
1565 * Choose the appropriate DDC bus for control bus switch command for this
1566 * SDVO output based on the controlled output.
1567 *
1568 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1569 * outputs, then LVDS outputs.
1570 */
1571static void
1572intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1573{
1574 uint16_t mask = 0;
1575 unsigned int num_bits;
1576
1577 /* Make a mask of outputs less than or equal to our own priority in the
1578 * list.
1579 */
1580 switch (dev_priv->controlled_output) {
1581 case SDVO_OUTPUT_LVDS1:
1582 mask |= SDVO_OUTPUT_LVDS1;
1583 case SDVO_OUTPUT_LVDS0:
1584 mask |= SDVO_OUTPUT_LVDS0;
1585 case SDVO_OUTPUT_TMDS1:
1586 mask |= SDVO_OUTPUT_TMDS1;
1587 case SDVO_OUTPUT_TMDS0:
1588 mask |= SDVO_OUTPUT_TMDS0;
1589 case SDVO_OUTPUT_RGB1:
1590 mask |= SDVO_OUTPUT_RGB1;
1591 case SDVO_OUTPUT_RGB0:
1592 mask |= SDVO_OUTPUT_RGB0;
1593 break;
1594 }
1595
1596 /* Count bits to find what number we are in the priority list. */
1597 mask &= dev_priv->caps.output_flags;
1598 num_bits = hweight16(mask);
1599 if (num_bits > 3) {
1600 /* if more than 3 outputs, default to DDC bus 3 for now */
1601 num_bits = 3;
1602 }
1603
1604 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1605 dev_priv->ddc_bus = 1 << num_bits;
1606}
1607
1608static bool
1609intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1610{
1611 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1612 uint8_t status;
1613
1614 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1615
1616 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1617 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1618 if (status != SDVO_CMD_STATUS_SUCCESS)
1619 return false;
1620 return true;
1621}
1622
7d57382e 1623bool intel_sdvo_init(struct drm_device *dev, int output_device)
79e53945
JB		 1624{
1625 struct drm_connector *connector;
1626 struct intel_output *intel_output;
1627 struct intel_sdvo_priv *sdvo_priv;
1628 struct intel_i2c_chan *i2cbus = NULL;
1629 int connector_type;
1630 u8 ch[0x40];
1631 int i;
1632 int encoder_type, output_id;
1633
1634 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1635 if (!intel_output) {
7d57382e 1636 return false;
79e53945
JB		 1637 }
1638
1639 connector = &intel_output->base;
1640
1641 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
1642 DRM_MODE_CONNECTOR_Unknown);
1643 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
1644 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1645 intel_output->type = INTEL_OUTPUT_SDVO;
1646
1647 connector->interlace_allowed = 0;
1648 connector->doublescan_allowed = 0;
1649
1650 /* setup the DDC bus. */
1651 if (output_device == SDVOB)
1652 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1653 else
1654 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1655
1656 if (!i2cbus)
1657 goto err_connector;
1658
1659 sdvo_priv->i2c_bus = i2cbus;
1660
1661 if (output_device == SDVOB) {
1662 output_id = 1;
1663 sdvo_priv->i2c_bus->slave_addr = 0x38;
1664 } else {
1665 output_id = 2;
1666 sdvo_priv->i2c_bus->slave_addr = 0x39;
1667 }
1668
1669 sdvo_priv->output_device = output_device;
1670 intel_output->i2c_bus = i2cbus;
1671 intel_output->dev_priv = sdvo_priv;
1672
1673
1674 /* Read the regs to test if we can talk to the device */
1675 for (i = 0; i < 0x40; i++) {
1676 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1677 DRM_DEBUG("No SDVO device found on SDVO%c\n",
1678 output_device == SDVOB ? 'B' : 'C');
1679 goto err_i2c;
1680 }
1681 }
1682
1683 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1684
e2f0ba97
JB		 1685 if (sdvo_priv->caps.output_flags &
1686 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1687 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1688 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1689 else
1690 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1691
1692 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1693 encoder_type = DRM_MODE_ENCODER_TMDS;
1694 connector_type = DRM_MODE_CONNECTOR_DVID;
79e53945 1695
e2f0ba97
JB		 1696 if (intel_sdvo_get_supp_encode(intel_output,
1697 &sdvo_priv->encode) &&
1698 intel_sdvo_get_digital_encoding_mode(intel_output) &&
1699 sdvo_priv->is_hdmi) {
1700 /* enable hdmi encoding mode if supported */
1701 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1702 intel_sdvo_set_colorimetry(intel_output,
1703 SDVO_COLORIMETRY_RGB256);
1704 connector_type = DRM_MODE_CONNECTOR_HDMIA;
1705 }
1706 }
1707 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
79e53945 1708 {
e2f0ba97
JB		 1709 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1710 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1711 encoder_type = DRM_MODE_ENCODER_TVDAC;
1712 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1713 sdvo_priv->is_tv = true;
1714 intel_output->needs_tv_clock = true;
1715 }
1716 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1717 {
1718 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
79e53945
JB		 1719 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1720 encoder_type = DRM_MODE_ENCODER_DAC;
1721 connector_type = DRM_MODE_CONNECTOR_VGA;
1722 }
1723 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1724 {
e2f0ba97 1725 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
79e53945
JB		 1726 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1727 encoder_type = DRM_MODE_ENCODER_DAC;
1728 connector_type = DRM_MODE_CONNECTOR_VGA;
1729 }
e2f0ba97 1730 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
79e53945 1731 {
e2f0ba97 1732 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
79e53945 1733 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
e2f0ba97
JB		 1734 encoder_type = DRM_MODE_ENCODER_LVDS;
1735 connector_type = DRM_MODE_CONNECTOR_LVDS;
79e53945 1736 }
e2f0ba97 1737 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
79e53945 1738 {
e2f0ba97 1739 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
79e53945 1740 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
e2f0ba97
JB		 1741 encoder_type = DRM_MODE_ENCODER_LVDS;
1742 connector_type = DRM_MODE_CONNECTOR_LVDS;
79e53945
JB		 1743 }
1744 else
1745 {
1746 unsigned char bytes[2];
1747
e2f0ba97 1748 sdvo_priv->controlled_output = 0;
79e53945 1749 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
e2f0ba97 1750 DRM_DEBUG("%s: Unknown SDVO output type (0x%02x%02x)\n",
79e53945
JB		 1751 SDVO_NAME(sdvo_priv),
1752 bytes[0], bytes[1]);
e2f0ba97
JB		 1753 encoder_type = DRM_MODE_ENCODER_NONE;
1754 connector_type = DRM_MODE_CONNECTOR_Unknown;
79e53945
JB		 1755 goto err_i2c;
1756 }
1757
1758 drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
1759 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
1760 connector->connector_type = connector_type;
1761
1762 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1763 drm_sysfs_connector_add(connector);
1764
e2f0ba97
JB		 1765 intel_sdvo_select_ddc_bus(sdvo_priv);
1766
79e53945
JB		 1767 /* Set the input timing to the screen. Assume always input 0. */
1768 intel_sdvo_set_target_input(intel_output, true, false);
1769
1770 intel_sdvo_get_input_pixel_clock_range(intel_output,
1771 &sdvo_priv->pixel_clock_min,
1772 &sdvo_priv->pixel_clock_max);
1773
1774
1775 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1776 "clock range %dMHz - %dMHz, "
1777 "input 1: %c, input 2: %c, "
1778 "output 1: %c, output 2: %c\n",
1779 SDVO_NAME(sdvo_priv),
1780 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1781 sdvo_priv->caps.device_rev_id,
1782 sdvo_priv->pixel_clock_min / 1000,
1783 sdvo_priv->pixel_clock_max / 1000,
1784 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1785 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1786 /* check currently supported outputs */
1787 sdvo_priv->caps.output_flags &
1788 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1789 sdvo_priv->caps.output_flags &
1790 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1791
1792 intel_output->ddc_bus = i2cbus;
1793
7d57382e 1794 return true;
79e53945
JB		 1795
1796err_i2c:
1797 intel_i2c_destroy(intel_output->i2c_bus);
1798err_connector:
1799 drm_connector_cleanup(connector);
1800 kfree(intel_output);
1801
7d57382e 1802 return false;
79e53945 1803}
Clone of davem's net-next-2.6 tree