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drm/i915: change intel_ddc_get_modes() function parameters
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
29#include <linux/delay.h>
30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "intel_drv.h"
2b8d33f7 34#include "drm_edid.h"
79e53945
JB		 35#include "i915_drm.h"
36#include "i915_drv.h"
37#include "intel_sdvo_regs.h"
6070a4a9 38#include <linux/dmi.h>
79e53945 39
ce6feabd
ZY		 40static char *tv_format_names[] = {
41 "NTSC_M" , "NTSC_J" , "NTSC_443",
42 "PAL_B" , "PAL_D" , "PAL_G" ,
43 "PAL_H" , "PAL_I" , "PAL_M" ,
44 "PAL_N" , "PAL_NC" , "PAL_60" ,
45 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
46 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
47 "SECAM_60"
48};
49
50#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
51
79e53945 52struct intel_sdvo_priv {
f9c10a9b 53 u8 slave_addr;
e2f0ba97
JB		 54
55 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 56 int sdvo_reg;
79e53945 57
e2f0ba97
JB		 58 /* Active outputs controlled by this SDVO output */
59 uint16_t controlled_output;
79e53945 60
e2f0ba97
JB		 61 /*
62 * Capabilities of the SDVO device returned by
63 * i830_sdvo_get_capabilities()
64 */
79e53945 65 struct intel_sdvo_caps caps;
e2f0ba97
JB		 66
67 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 68 int pixel_clock_min, pixel_clock_max;
69
fb7a46f3 70 /*
71 * For multiple function SDVO device,
72 * this is for current attached outputs.
73 */
74 uint16_t attached_output;
75
e2f0ba97
JB		 76 /**
77 * This is set if we're going to treat the device as TV-out.
78 *
79 * While we have these nice friendly flags for output types that ought
80 * to decide this for us, the S-Video output on our HDMI+S-Video card
81 * shows up as RGB1 (VGA).
82 */
83 bool is_tv;
84
ce6feabd
ZY		 85 /* This is for current tv format name */
86 char *tv_format_name;
87
88 /* This contains all current supported TV format */
89 char *tv_format_supported[TV_FORMAT_NUM];
90 int format_supported_num;
91 struct drm_property *tv_format_property;
92 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
93
e2f0ba97
JB		 94 /**
95 * This is set if we treat the device as HDMI, instead of DVI.
96 */
97 bool is_hdmi;
12682a97 98
7086c87f
ML		 99 /**
100 * This is set if we detect output of sdvo device as LVDS.
101 */
102 bool is_lvds;
e2f0ba97 103
12682a97 104 /**
105 * This is sdvo flags for input timing.
106 */
107 uint8_t sdvo_flags;
108
109 /**
110 * This is sdvo fixed pannel mode pointer
111 */
112 struct drm_display_mode *sdvo_lvds_fixed_mode;
113
e2f0ba97
JB		 114 /**
115 * Returned SDTV resolutions allowed for the current format, if the
116 * device reported it.
117 */
118 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
119
e2f0ba97
JB		 120 /*
121 * supported encoding mode, used to determine whether HDMI is
122 * supported
123 */
124 struct intel_sdvo_encode encode;
125
c751ce4f 126 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 127 uint8_t ddc_bus;
128
57cdaf90
KP		 129 /* Mac mini hack -- use the same DDC as the analog connector */
130 struct i2c_adapter *analog_ddc_bus;
131
79e53945
JB		 132 int save_sdvo_mult;
133 u16 save_active_outputs;
134 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
135 struct intel_sdvo_dtd save_output_dtd[16];
136 u32 save_SDVOX;
b9219c5e
ZY		 137 /* add the property for the SDVO-TV */
138 struct drm_property *left_property;
139 struct drm_property *right_property;
140 struct drm_property *top_property;
141 struct drm_property *bottom_property;
142 struct drm_property *hpos_property;
143 struct drm_property *vpos_property;
144
145 /* add the property for the SDVO-TV/LVDS */
146 struct drm_property *brightness_property;
147 struct drm_property *contrast_property;
148 struct drm_property *saturation_property;
149 struct drm_property *hue_property;
150
151 /* Add variable to record current setting for the above property */
152 u32 left_margin, right_margin, top_margin, bottom_margin;
153 /* this is to get the range of margin.*/
154 u32 max_hscan, max_vscan;
155 u32 max_hpos, cur_hpos;
156 u32 max_vpos, cur_vpos;
157 u32 cur_brightness, max_brightness;
158 u32 cur_contrast, max_contrast;
159 u32 cur_saturation, max_saturation;
160 u32 cur_hue, max_hue;
79e53945
JB		 161};
162
fb7a46f3 163static bool
21d40d37 164intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags);
fb7a46f3 165
79e53945
JB		 166/**
167 * Writes the SDVOB or SDVOC with the given value, but always writes both
168 * SDVOB and SDVOC to work around apparent hardware issues (according to
169 * comments in the BIOS).
170 */
21d40d37 171static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
79e53945 172{
21d40d37 173 struct drm_device *dev = intel_encoder->base.dev;
79e53945 174 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 175 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 176 u32 bval = val, cval = val;
177 int i;
178
c751ce4f 179 if (sdvo_priv->sdvo_reg == SDVOB) {
79e53945
JB		 180 cval = I915_READ(SDVOC);
181 } else {
182 bval = I915_READ(SDVOB);
183 }
184 /*
185 * Write the registers twice for luck. Sometimes,
186 * writing them only once doesn't appear to 'stick'.
187 * The BIOS does this too. Yay, magic
188 */
189 for (i = 0; i < 2; i++)
190 {
191 I915_WRITE(SDVOB, bval);
192 I915_READ(SDVOB);
193 I915_WRITE(SDVOC, cval);
194 I915_READ(SDVOC);
195 }
196}
197
21d40d37 198static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
79e53945
JB		 199 u8 *ch)
200{
21d40d37 201 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 202 u8 out_buf[2];
203 u8 buf[2];
204 int ret;
205
206 struct i2c_msg msgs[] = {
207 {
f9c10a9b 208 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 209 .flags = 0,
210 .len = 1,
211 .buf = out_buf,
212 },
213 {
f9c10a9b 214 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 215 .flags = I2C_M_RD,
216 .len = 1,
217 .buf = buf,
218 }
219 };
220
221 out_buf[0] = addr;
222 out_buf[1] = 0;
223
21d40d37 224 if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
79e53945
JB		 225 {
226 *ch = buf[0];
227 return true;
228 }
229
8a4c47f3 230 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 231 return false;
232}
233
21d40d37 234static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr,
79e53945
JB		 235 u8 ch)
236{
21d40d37 237 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 238 u8 out_buf[2];
239 struct i2c_msg msgs[] = {
240 {
f9c10a9b 241 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 242 .flags = 0,
243 .len = 2,
244 .buf = out_buf,
245 }
246 };
247
248 out_buf[0] = addr;
249 out_buf[1] = ch;
250
21d40d37 251 if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
79e53945
JB		 252 {
253 return true;
254 }
255 return false;
256}
257
258#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
259/** Mapping of command numbers to names, for debug output */
005568be 260static const struct _sdvo_cmd_name {
e2f0ba97
JB		 261 u8 cmd;
262 char *name;
79e53945
JB		 263} sdvo_cmd_names[] = {
264 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
268 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
269 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
270 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
271 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
272 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
273 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
274 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
275 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
b9219c5e
ZY		 307 /* Add the op code for SDVO enhancements */
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
e2f0ba97
JB		 332 /* HDMI op code */
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 353};
354
c751ce4f
EA		 355#define SDVO_NAME(dev_priv) ((dev_priv)->sdvo_reg == SDVOB ? "SDVOB" : "SDVOC")
356#define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv)
79e53945 357
21d40d37 358static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 359 void *args, int args_len)
360{
21d40d37 361 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 362 int i;
363
8a4c47f3 364 DRM_DEBUG_KMS("%s: W: %02X ",
342dc382 365 SDVO_NAME(sdvo_priv), cmd);
79e53945 366 for (i = 0; i < args_len; i++)
342dc382 367 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 368 for (; i < 8; i++)
342dc382 369 DRM_LOG_KMS(" ");
79e53945
JB		 370 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
371 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 372 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 373 break;
374 }
375 }
376 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
342dc382 377 DRM_LOG_KMS("(%02X)", cmd);
378 DRM_LOG_KMS("\n");
79e53945 379}
79e53945 380
21d40d37 381static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 382 void *args, int args_len)
383{
384 int i;
385
21d40d37 386 intel_sdvo_debug_write(intel_encoder, cmd, args, args_len);
79e53945
JB		 387
388 for (i = 0; i < args_len; i++) {
21d40d37 389 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i,
79e53945
JB		 390 ((u8*)args)[i]);
391 }
392
21d40d37 393 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 394}
395
79e53945
JB		 396static const char *cmd_status_names[] = {
397 "Power on",
398 "Success",
399 "Not supported",
400 "Invalid arg",
401 "Pending",
402 "Target not specified",
403 "Scaling not supported"
404};
405
21d40d37 406static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
79e53945
JB		 407 void *response, int response_len,
408 u8 status)
409{
21d40d37 410 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
33b52961 411 int i;
79e53945 412
8a4c47f3 413 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
79e53945 414 for (i = 0; i < response_len; i++)
342dc382 415 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 416 for (; i < 8; i++)
342dc382 417 DRM_LOG_KMS(" ");
79e53945 418 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 419 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 420 else
342dc382 421 DRM_LOG_KMS("(??? %d)", status);
422 DRM_LOG_KMS("\n");
79e53945 423}
79e53945 424
21d40d37 425static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
79e53945
JB		 426 void *response, int response_len)
427{
428 int i;
429 u8 status;
430 u8 retry = 50;
431
432 while (retry--) {
433 /* Read the command response */
434 for (i = 0; i < response_len; i++) {
21d40d37 435 intel_sdvo_read_byte(intel_encoder,
79e53945
JB		 436 SDVO_I2C_RETURN_0 + i,
437 &((u8 *)response)[i]);
438 }
439
440 /* read the return status */
21d40d37 441 intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS,
79e53945
JB		 442 &status);
443
21d40d37 444 intel_sdvo_debug_response(intel_encoder, response, response_len,
79e53945
JB		 445 status);
446 if (status != SDVO_CMD_STATUS_PENDING)
447 return status;
448
449 mdelay(50);
450 }
451
452 return status;
453}
454
b358d0a6 455static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 456{
457 if (mode->clock >= 100000)
458 return 1;
459 else if (mode->clock >= 50000)
460 return 2;
461 else
462 return 4;
463}
464
465/**
6a304caf
ZY		 466 * Try to read the response after issuie the DDC switch command. But it
467 * is noted that we must do the action of reading response and issuing DDC
468 * switch command in one I2C transaction. Otherwise when we try to start
469 * another I2C transaction after issuing the DDC bus switch, it will be
470 * switched to the internal SDVO register.
79e53945 471 */
21d40d37 472static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder,
b358d0a6 473 u8 target)
79e53945 474{
21d40d37 475 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
6a304caf
ZY		 476 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
477 struct i2c_msg msgs[] = {
478 {
479 .addr = sdvo_priv->slave_addr >> 1,
480 .flags = 0,
481 .len = 2,
482 .buf = out_buf,
483 },
484 /* the following two are to read the response */
485 {
486 .addr = sdvo_priv->slave_addr >> 1,
487 .flags = 0,
488 .len = 1,
489 .buf = cmd_buf,
490 },
491 {
492 .addr = sdvo_priv->slave_addr >> 1,
493 .flags = I2C_M_RD,
494 .len = 1,
495 .buf = ret_value,
496 },
497 };
498
21d40d37 499 intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 500 &target, 1);
501 /* write the DDC switch command argument */
21d40d37 502 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 503
504 out_buf[0] = SDVO_I2C_OPCODE;
505 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
506 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
507 cmd_buf[1] = 0;
508 ret_value[0] = 0;
509 ret_value[1] = 0;
510
21d40d37 511 ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3);
6a304caf
ZY		 512 if (ret != 3) {
513 /* failure in I2C transfer */
514 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
515 return;
516 }
517 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
518 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
519 ret_value[0]);
520 return;
521 }
522 return;
79e53945
JB		 523}
524
21d40d37 525static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1)
79e53945
JB		 526{
527 struct intel_sdvo_set_target_input_args targets = {0};
528 u8 status;
529
530 if (target_0 && target_1)
531 return SDVO_CMD_STATUS_NOTSUPP;
532
533 if (target_1)
534 targets.target_1 = 1;
535
21d40d37 536 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets,
79e53945
JB		 537 sizeof(targets));
538
21d40d37 539 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 540
541 return (status == SDVO_CMD_STATUS_SUCCESS);
542}
543
544/**
545 * Return whether each input is trained.
546 *
547 * This function is making an assumption about the layout of the response,
548 * which should be checked against the docs.
549 */
21d40d37 550static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2)
79e53945
JB		 551{
552 struct intel_sdvo_get_trained_inputs_response response;
553 u8 status;
554
21d40d37
EA		 555 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
556 status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response));
79e53945
JB		 557 if (status != SDVO_CMD_STATUS_SUCCESS)
558 return false;
559
560 *input_1 = response.input0_trained;
561 *input_2 = response.input1_trained;
562 return true;
563}
564
21d40d37 565static bool intel_sdvo_get_active_outputs(struct intel_encoder *intel_encoder,
79e53945
JB		 566 u16 *outputs)
567{
568 u8 status;
569
21d40d37
EA		 570 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
571 status = intel_sdvo_read_response(intel_encoder, outputs, sizeof(*outputs));
79e53945
JB		 572
573 return (status == SDVO_CMD_STATUS_SUCCESS);
574}
575
21d40d37 576static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder,
79e53945
JB		 577 u16 outputs)
578{
579 u8 status;
580
21d40d37 581 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
79e53945 582 sizeof(outputs));
21d40d37 583 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 584 return (status == SDVO_CMD_STATUS_SUCCESS);
585}
586
21d40d37 587static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder,
79e53945
JB		 588 int mode)
589{
590 u8 status, state = SDVO_ENCODER_STATE_ON;
591
592 switch (mode) {
593 case DRM_MODE_DPMS_ON:
594 state = SDVO_ENCODER_STATE_ON;
595 break;
596 case DRM_MODE_DPMS_STANDBY:
597 state = SDVO_ENCODER_STATE_STANDBY;
598 break;
599 case DRM_MODE_DPMS_SUSPEND:
600 state = SDVO_ENCODER_STATE_SUSPEND;
601 break;
602 case DRM_MODE_DPMS_OFF:
603 state = SDVO_ENCODER_STATE_OFF;
604 break;
605 }
606
21d40d37 607 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
79e53945 608 sizeof(state));
21d40d37 609 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 610
611 return (status == SDVO_CMD_STATUS_SUCCESS);
612}
613
21d40d37 614static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder,
79e53945
JB		 615 int *clock_min,
616 int *clock_max)
617{
618 struct intel_sdvo_pixel_clock_range clocks;
619 u8 status;
620
21d40d37 621 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
79e53945
JB		 622 NULL, 0);
623
21d40d37 624 status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
79e53945
JB		 625
626 if (status != SDVO_CMD_STATUS_SUCCESS)
627 return false;
628
629 /* Convert the values from units of 10 kHz to kHz. */
630 *clock_min = clocks.min * 10;
631 *clock_max = clocks.max * 10;
632
633 return true;
634}
635
21d40d37 636static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder,
79e53945
JB		 637 u16 outputs)
638{
639 u8 status;
640
21d40d37 641 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
79e53945
JB		 642 sizeof(outputs));
643
21d40d37 644 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 645 return (status == SDVO_CMD_STATUS_SUCCESS);
646}
647
21d40d37 648static bool intel_sdvo_get_timing(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 649 struct intel_sdvo_dtd *dtd)
650{
651 u8 status;
652
21d40d37
EA		 653 intel_sdvo_write_cmd(intel_encoder, cmd, NULL, 0);
654 status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
79e53945
JB		 655 sizeof(dtd->part1));
656 if (status != SDVO_CMD_STATUS_SUCCESS)
657 return false;
658
21d40d37
EA		 659 intel_sdvo_write_cmd(intel_encoder, cmd + 1, NULL, 0);
660 status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
79e53945
JB		 661 sizeof(dtd->part2));
662 if (status != SDVO_CMD_STATUS_SUCCESS)
663 return false;
664
665 return true;
666}
667
21d40d37 668static bool intel_sdvo_get_input_timing(struct intel_encoder *intel_encoder,
79e53945
JB		 669 struct intel_sdvo_dtd *dtd)
670{
21d40d37 671 return intel_sdvo_get_timing(intel_encoder,
79e53945
JB		 672 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
673}
674
21d40d37 675static bool intel_sdvo_get_output_timing(struct intel_encoder *intel_encoder,
79e53945
JB		 676 struct intel_sdvo_dtd *dtd)
677{
21d40d37 678 return intel_sdvo_get_timing(intel_encoder,
79e53945
JB		 679 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
680}
681
21d40d37 682static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 683 struct intel_sdvo_dtd *dtd)
684{
685 u8 status;
686
21d40d37
EA		 687 intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
688 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 689 if (status != SDVO_CMD_STATUS_SUCCESS)
690 return false;
691
21d40d37
EA		 692 intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
693 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 694 if (status != SDVO_CMD_STATUS_SUCCESS)
695 return false;
696
697 return true;
698}
699
21d40d37 700static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder,
79e53945
JB		 701 struct intel_sdvo_dtd *dtd)
702{
21d40d37 703 return intel_sdvo_set_timing(intel_encoder,
79e53945
JB		 704 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
705}
706
21d40d37 707static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder,
79e53945
JB		 708 struct intel_sdvo_dtd *dtd)
709{
21d40d37 710 return intel_sdvo_set_timing(intel_encoder,
79e53945
JB		 711 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
712}
713
e2f0ba97 714static bool
c751ce4f 715intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 716 uint16_t clock,
717 uint16_t width,
718 uint16_t height)
719{
720 struct intel_sdvo_preferred_input_timing_args args;
c751ce4f 721 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
e2f0ba97
JB		 722 uint8_t status;
723
e642c6f1 724 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 725 args.clock = clock;
726 args.width = width;
727 args.height = height;
e642c6f1 728 args.interlace = 0;
12682a97 729
730 if (sdvo_priv->is_lvds &&
731 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
732 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
733 args.scaled = 1;
734
c751ce4f
EA		 735 intel_sdvo_write_cmd(intel_encoder,
736 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
e2f0ba97 737 &args, sizeof(args));
c751ce4f 738 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 739 if (status != SDVO_CMD_STATUS_SUCCESS)
740 return false;
741
742 return true;
743}
744
c751ce4f 745static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 746 struct intel_sdvo_dtd *dtd)
747{
748 bool status;
749
c751ce4f 750 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
e2f0ba97
JB		 751 NULL, 0);
752
c751ce4f 753 status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
e2f0ba97
JB		 754 sizeof(dtd->part1));
755 if (status != SDVO_CMD_STATUS_SUCCESS)
756 return false;
757
c751ce4f 758 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
e2f0ba97
JB		 759 NULL, 0);
760
c751ce4f 761 status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
e2f0ba97
JB		 762 sizeof(dtd->part2));
763 if (status != SDVO_CMD_STATUS_SUCCESS)
764 return false;
765
766 return false;
767}
79e53945 768
21d40d37 769static int intel_sdvo_get_clock_rate_mult(struct intel_encoder *intel_encoder)
79e53945
JB		 770{
771 u8 response, status;
772
21d40d37
EA		 773 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
774 status = intel_sdvo_read_response(intel_encoder, &response, 1);
79e53945
JB		 775
776 if (status != SDVO_CMD_STATUS_SUCCESS) {
8a4c47f3 777 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
79e53945
JB		 778 return SDVO_CLOCK_RATE_MULT_1X;
779 } else {
8a4c47f3 780 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
79e53945
JB		 781 }
782
783 return response;
784}
785
21d40d37 786static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val)
79e53945
JB		 787{
788 u8 status;
789
21d40d37
EA		 790 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
791 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 792 if (status != SDVO_CMD_STATUS_SUCCESS)
793 return false;
794
795 return true;
796}
797
e2f0ba97
JB		 798static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
799 struct drm_display_mode *mode)
79e53945 800{
e2f0ba97
JB		 801 uint16_t width, height;
802 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
803 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 804
805 width = mode->crtc_hdisplay;
806 height = mode->crtc_vdisplay;
807
808 /* do some mode translations */
809 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
810 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
811
812 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
813 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
814
815 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
816 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
817
e2f0ba97
JB		 818 dtd->part1.clock = mode->clock / 10;
819 dtd->part1.h_active = width & 0xff;
820 dtd->part1.h_blank = h_blank_len & 0xff;
821 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 822 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 823 dtd->part1.v_active = height & 0xff;
824 dtd->part1.v_blank = v_blank_len & 0xff;
825 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 826 ((v_blank_len >> 8) & 0xf);
827
171a9e96 828 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 829 dtd->part2.h_sync_width = h_sync_len & 0xff;
830 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 831 (v_sync_len & 0xf);
e2f0ba97 832 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 833 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
834 ((v_sync_len & 0x30) >> 4);
835
e2f0ba97 836 dtd->part2.dtd_flags = 0x18;
79e53945 837 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 838 dtd->part2.dtd_flags |= 0x2;
79e53945 839 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 840 dtd->part2.dtd_flags |= 0x4;
841
842 dtd->part2.sdvo_flags = 0;
843 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
844 dtd->part2.reserved = 0;
845}
846
847static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
848 struct intel_sdvo_dtd *dtd)
849{
e2f0ba97
JB		 850 mode->hdisplay = dtd->part1.h_active;
851 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
852 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 853 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 854 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
855 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
856 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
857 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
858
859 mode->vdisplay = dtd->part1.v_active;
860 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
861 mode->vsync_start = mode->vdisplay;
862 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 863 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 864 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
865 mode->vsync_end = mode->vsync_start +
866 (dtd->part2.v_sync_off_width & 0xf);
867 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
868 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
869 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
870
871 mode->clock = dtd->part1.clock * 10;
872
171a9e96 873 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 874 if (dtd->part2.dtd_flags & 0x2)
875 mode->flags |= DRM_MODE_FLAG_PHSYNC;
876 if (dtd->part2.dtd_flags & 0x4)
877 mode->flags |= DRM_MODE_FLAG_PVSYNC;
878}
879
c751ce4f 880static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 881 struct intel_sdvo_encode *encode)
882{
883 uint8_t status;
884
c751ce4f
EA		 885 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
886 status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));
e2f0ba97
JB		 887 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
888 memset(encode, 0, sizeof(*encode));
889 return false;
890 }
891
892 return true;
893}
894
c751ce4f
EA		 895static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,
896 uint8_t mode)
e2f0ba97
JB		 897{
898 uint8_t status;
899
c751ce4f
EA		 900 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
901 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 902
903 return (status == SDVO_CMD_STATUS_SUCCESS);
904}
905
c751ce4f 906static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 907 uint8_t mode)
908{
909 uint8_t status;
910
c751ce4f
EA		 911 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
912 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 913
914 return (status == SDVO_CMD_STATUS_SUCCESS);
915}
916
917#if 0
c751ce4f 918static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
e2f0ba97
JB		 919{
920 int i, j;
921 uint8_t set_buf_index[2];
922 uint8_t av_split;
923 uint8_t buf_size;
924 uint8_t buf[48];
925 uint8_t *pos;
926
c751ce4f
EA		 927 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
928 intel_sdvo_read_response(encoder, &av_split, 1);
e2f0ba97
JB		 929
930 for (i = 0; i <= av_split; i++) {
931 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 932 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 933 set_buf_index, 2);
c751ce4f
EA		 934 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
935 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 936
937 pos = buf;
938 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 939 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 940 NULL, 0);
c751ce4f 941 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 942 pos += 8;
943 }
944 }
945}
946#endif
947
c751ce4f
EA		 948static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
949 int index,
950 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 951{
952 uint8_t set_buf_index[2];
953
954 set_buf_index[0] = index;
955 set_buf_index[1] = 0;
956
c751ce4f
EA		 957 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,
958 set_buf_index, 2);
e2f0ba97
JB		 959
960 for (; size > 0; size -= 8) {
c751ce4f 961 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);
e2f0ba97
JB		 962 data += 8;
963 }
964
c751ce4f 965 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 966}
967
968static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
969{
970 uint8_t csum = 0;
971 int i;
972
973 for (i = 0; i < size; i++)
974 csum += data[i];
975
976 return 0x100 - csum;
977}
978
979#define DIP_TYPE_AVI 0x82
980#define DIP_VERSION_AVI 0x2
981#define DIP_LEN_AVI 13
982
983struct dip_infoframe {
984 uint8_t type;
985 uint8_t version;
986 uint8_t len;
987 uint8_t checksum;
988 union {
989 struct {
990 /* Packet Byte #1 */
991 uint8_t S:2;
992 uint8_t B:2;
993 uint8_t A:1;
994 uint8_t Y:2;
995 uint8_t rsvd1:1;
996 /* Packet Byte #2 */
997 uint8_t R:4;
998 uint8_t M:2;
999 uint8_t C:2;
1000 /* Packet Byte #3 */
1001 uint8_t SC:2;
1002 uint8_t Q:2;
1003 uint8_t EC:3;
1004 uint8_t ITC:1;
1005 /* Packet Byte #4 */
1006 uint8_t VIC:7;
1007 uint8_t rsvd2:1;
1008 /* Packet Byte #5 */
1009 uint8_t PR:4;
1010 uint8_t rsvd3:4;
1011 /* Packet Byte #6~13 */
1012 uint16_t top_bar_end;
1013 uint16_t bottom_bar_start;
1014 uint16_t left_bar_end;
1015 uint16_t right_bar_start;
1016 } avi;
1017 struct {
1018 /* Packet Byte #1 */
1019 uint8_t channel_count:3;
1020 uint8_t rsvd1:1;
1021 uint8_t coding_type:4;
1022 /* Packet Byte #2 */
1023 uint8_t sample_size:2; /* SS0, SS1 */
1024 uint8_t sample_frequency:3;
1025 uint8_t rsvd2:3;
1026 /* Packet Byte #3 */
1027 uint8_t coding_type_private:5;
1028 uint8_t rsvd3:3;
1029 /* Packet Byte #4 */
1030 uint8_t channel_allocation;
1031 /* Packet Byte #5 */
1032 uint8_t rsvd4:3;
1033 uint8_t level_shift:4;
1034 uint8_t downmix_inhibit:1;
1035 } audio;
1036 uint8_t payload[28];
1037 } __attribute__ ((packed)) u;
1038} __attribute__((packed));
1039
c751ce4f 1040static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 1041 struct drm_display_mode * mode)
1042{
1043 struct dip_infoframe avi_if = {
1044 .type = DIP_TYPE_AVI,
1045 .version = DIP_VERSION_AVI,
1046 .len = DIP_LEN_AVI,
1047 };
1048
1049 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1050 4 + avi_if.len);
c751ce4f
EA		 1051 intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,
1052 4 + avi_if.len,
e2f0ba97
JB		 1053 SDVO_HBUF_TX_VSYNC);
1054}
1055
c751ce4f 1056static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)
7026d4ac 1057{
ce6feabd
ZY		 1058
1059 struct intel_sdvo_tv_format format;
c751ce4f 1060 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
ce6feabd
ZY		 1061 uint32_t format_map, i;
1062 uint8_t status;
7026d4ac 1063
ce6feabd
ZY		 1064 for (i = 0; i < TV_FORMAT_NUM; i++)
1065 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1066 break;
1067
1068 format_map = 1 << i;
1069 memset(&format, 0, sizeof(format));
1070 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1071 sizeof(format) : sizeof(format_map));
1072
c751ce4f 1073 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format_map,
ce6feabd
ZY		 1074 sizeof(format));
1075
c751ce4f 1076 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
ce6feabd 1077 if (status != SDVO_CMD_STATUS_SUCCESS)
b9219c5e 1078 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
ce6feabd 1079 SDVO_NAME(sdvo_priv));
7026d4ac
ZW		 1080}
1081
e2f0ba97
JB		 1082static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1083 struct drm_display_mode *mode,
1084 struct drm_display_mode *adjusted_mode)
1085{
c751ce4f
EA		 1086 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1087 struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
79e53945 1088
12682a97 1089 if (dev_priv->is_tv) {
e2f0ba97
JB		 1090 struct intel_sdvo_dtd output_dtd;
1091 bool success;
1092
1093 /* We need to construct preferred input timings based on our
1094 * output timings. To do that, we have to set the output
1095 * timings, even though this isn't really the right place in
1096 * the sequence to do it. Oh well.
1097 */
1098
1099
1100 /* Set output timings */
1101 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c751ce4f 1102 intel_sdvo_set_target_output(intel_encoder,
e2f0ba97 1103 dev_priv->controlled_output);
c751ce4f 1104 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
e2f0ba97
JB		 1105
1106 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1107 intel_sdvo_set_target_input(intel_encoder, true, false);
e2f0ba97
JB		 1108
1109
c751ce4f 1110 success = intel_sdvo_create_preferred_input_timing(intel_encoder,
e2f0ba97
JB		 1111 mode->clock / 10,
1112 mode->hdisplay,
1113 mode->vdisplay);
1114 if (success) {
1115 struct intel_sdvo_dtd input_dtd;
79e53945 1116
c751ce4f 1117 intel_sdvo_get_preferred_input_timing(intel_encoder,
e2f0ba97
JB		 1118 &input_dtd);
1119 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
12682a97 1120 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1121
1122 drm_mode_set_crtcinfo(adjusted_mode, 0);
1123
1124 mode->clock = adjusted_mode->clock;
1125
1126 adjusted_mode->clock *=
1127 intel_sdvo_get_pixel_multiplier(mode);
1128 } else {
1129 return false;
1130 }
1131 } else if (dev_priv->is_lvds) {
1132 struct intel_sdvo_dtd output_dtd;
1133 bool success;
1134
1135 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1136 /* Set output timings */
1137 intel_sdvo_get_dtd_from_mode(&output_dtd,
1138 dev_priv->sdvo_lvds_fixed_mode);
1139
c751ce4f 1140 intel_sdvo_set_target_output(intel_encoder,
12682a97 1141 dev_priv->controlled_output);
c751ce4f 1142 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
12682a97 1143
1144 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1145 intel_sdvo_set_target_input(intel_encoder, true, false);
12682a97 1146
1147
1148 success = intel_sdvo_create_preferred_input_timing(
c751ce4f 1149 intel_encoder,
12682a97 1150 mode->clock / 10,
1151 mode->hdisplay,
1152 mode->vdisplay);
1153
1154 if (success) {
1155 struct intel_sdvo_dtd input_dtd;
1156
c751ce4f 1157 intel_sdvo_get_preferred_input_timing(intel_encoder,
12682a97 1158 &input_dtd);
1159 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1160 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
e2f0ba97 1161
7026d4ac
ZW		 1162 drm_mode_set_crtcinfo(adjusted_mode, 0);
1163
1164 mode->clock = adjusted_mode->clock;
1165
1166 adjusted_mode->clock *=
1167 intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1168 } else {
1169 return false;
1170 }
12682a97 1171
1172 } else {
1173 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1174 * SDVO device will be told of the multiplier during mode_set.
1175 */
1176 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1177 }
1178 return true;
1179}
1180
1181static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1182 struct drm_display_mode *mode,
1183 struct drm_display_mode *adjusted_mode)
1184{
1185 struct drm_device *dev = encoder->dev;
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 struct drm_crtc *crtc = encoder->crtc;
1188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c751ce4f
EA		 1189 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1190 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
e2f0ba97
JB		 1191 u32 sdvox = 0;
1192 int sdvo_pixel_multiply;
1193 struct intel_sdvo_in_out_map in_out;
1194 struct intel_sdvo_dtd input_dtd;
1195 u8 status;
1196
1197 if (!mode)
1198 return;
1199
1200 /* First, set the input mapping for the first input to our controlled
1201 * output. This is only correct if we're a single-input device, in
1202 * which case the first input is the output from the appropriate SDVO
1203 * channel on the motherboard. In a two-input device, the first input
1204 * will be SDVOB and the second SDVOC.
1205 */
1206 in_out.in0 = sdvo_priv->controlled_output;
1207 in_out.in1 = 0;
1208
c751ce4f 1209 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,
e2f0ba97 1210 &in_out, sizeof(in_out));
c751ce4f 1211 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 1212
1213 if (sdvo_priv->is_hdmi) {
c751ce4f 1214 intel_sdvo_set_avi_infoframe(intel_encoder, mode);
e2f0ba97
JB		 1215 sdvox |= SDVO_AUDIO_ENABLE;
1216 }
1217
7026d4ac
ZW		 1218 /* We have tried to get input timing in mode_fixup, and filled into
1219 adjusted_mode */
12682a97 1220 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
7026d4ac 1221 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
12682a97 1222 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1223 } else
7026d4ac 1224 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
e2f0ba97
JB		 1225
1226 /* If it's a TV, we already set the output timing in mode_fixup.
1227 * Otherwise, the output timing is equal to the input timing.
1228 */
12682a97 1229 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
e2f0ba97 1230 /* Set the output timing to the screen */
c751ce4f 1231 intel_sdvo_set_target_output(intel_encoder,
e2f0ba97 1232 sdvo_priv->controlled_output);
c751ce4f 1233 intel_sdvo_set_output_timing(intel_encoder, &input_dtd);
e2f0ba97 1234 }
79e53945
JB		 1235
1236 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1237 intel_sdvo_set_target_input(intel_encoder, true, false);
79e53945 1238
7026d4ac 1239 if (sdvo_priv->is_tv)
c751ce4f 1240 intel_sdvo_set_tv_format(intel_encoder);
7026d4ac 1241
e2f0ba97 1242 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1243 * provide the device with a timing it can support, if it supports that
1244 * feature. However, presumably we would need to adjust the CRTC to
1245 * output the preferred timing, and we don't support that currently.
1246 */
e2f0ba97 1247#if 0
c751ce4f 1248 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
e2f0ba97
JB		 1249 width, height);
1250 if (success) {
1251 struct intel_sdvo_dtd *input_dtd;
1252
c751ce4f
EA		 1253 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1254 intel_sdvo_set_input_timing(encoder, &input_dtd);
e2f0ba97
JB		 1255 }
1256#else
c751ce4f 1257 intel_sdvo_set_input_timing(intel_encoder, &input_dtd);
e2f0ba97 1258#endif
79e53945
JB		 1259
1260 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1261 case 1:
c751ce4f 1262 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1263 SDVO_CLOCK_RATE_MULT_1X);
1264 break;
1265 case 2:
c751ce4f 1266 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1267 SDVO_CLOCK_RATE_MULT_2X);
1268 break;
1269 case 4:
c751ce4f 1270 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1271 SDVO_CLOCK_RATE_MULT_4X);
1272 break;
1273 }
1274
1275 /* Set the SDVO control regs. */
e2f0ba97
JB		 1276 if (IS_I965G(dev)) {
1277 sdvox |= SDVO_BORDER_ENABLE |
1278 SDVO_VSYNC_ACTIVE_HIGH |
1279 SDVO_HSYNC_ACTIVE_HIGH;
1280 } else {
c751ce4f
EA		 1281 sdvox |= I915_READ(sdvo_priv->sdvo_reg);
1282 switch (sdvo_priv->sdvo_reg) {
e2f0ba97
JB		 1283 case SDVOB:
1284 sdvox &= SDVOB_PRESERVE_MASK;
1285 break;
1286 case SDVOC:
1287 sdvox &= SDVOC_PRESERVE_MASK;
1288 break;
1289 }
1290 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1291 }
79e53945
JB		 1292 if (intel_crtc->pipe == 1)
1293 sdvox |= SDVO_PIPE_B_SELECT;
1294
1295 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1296 if (IS_I965G(dev)) {
e2f0ba97
JB		 1297 /* done in crtc_mode_set as the dpll_md reg must be written early */
1298 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1299 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1300 } else {
1301 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1302 }
1303
12682a97 1304 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1305 sdvox |= SDVO_STALL_SELECT;
c751ce4f 1306 intel_sdvo_write_sdvox(intel_encoder, sdvox);
79e53945
JB		 1307}
1308
1309static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1310{
1311 struct drm_device *dev = encoder->dev;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37
EA		 1313 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1314 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 1315 u32 temp;
1316
1317 if (mode != DRM_MODE_DPMS_ON) {
21d40d37 1318 intel_sdvo_set_active_outputs(intel_encoder, 0);
79e53945 1319 if (0)
21d40d37 1320 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
79e53945
JB		 1321
1322 if (mode == DRM_MODE_DPMS_OFF) {
c751ce4f 1323 temp = I915_READ(sdvo_priv->sdvo_reg);
79e53945 1324 if ((temp & SDVO_ENABLE) != 0) {
21d40d37 1325 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);
79e53945
JB		 1326 }
1327 }
1328 } else {
1329 bool input1, input2;
1330 int i;
1331 u8 status;
1332
c751ce4f 1333 temp = I915_READ(sdvo_priv->sdvo_reg);
79e53945 1334 if ((temp & SDVO_ENABLE) == 0)
21d40d37 1335 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);
79e53945
JB		 1336 for (i = 0; i < 2; i++)
1337 intel_wait_for_vblank(dev);
1338
21d40d37 1339 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
79e53945
JB		 1340 &input2);
1341
1342
1343 /* Warn if the device reported failure to sync.
1344 * A lot of SDVO devices fail to notify of sync, but it's
1345 * a given it the status is a success, we succeeded.
1346 */
1347 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3
ZY		 1348 DRM_DEBUG_KMS("First %s output reported failure to "
1349 "sync\n", SDVO_NAME(sdvo_priv));
79e53945
JB		 1350 }
1351
1352 if (0)
21d40d37
EA		 1353 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1354 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->controlled_output);
79e53945
JB		 1355 }
1356 return;
1357}
1358
1359static void intel_sdvo_save(struct drm_connector *connector)
1360{
1361 struct drm_device *dev = connector->dev;
1362 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37
EA		 1363 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1364 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 1365 int o;
1366
21d40d37
EA		 1367 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_encoder);
1368 intel_sdvo_get_active_outputs(intel_encoder, &sdvo_priv->save_active_outputs);
79e53945
JB		 1369
1370 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
21d40d37
EA		 1371 intel_sdvo_set_target_input(intel_encoder, true, false);
1372 intel_sdvo_get_input_timing(intel_encoder,
79e53945
JB		 1373 &sdvo_priv->save_input_dtd_1);
1374 }
1375
1376 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
21d40d37
EA		 1377 intel_sdvo_set_target_input(intel_encoder, false, true);
1378 intel_sdvo_get_input_timing(intel_encoder,
79e53945
JB		 1379 &sdvo_priv->save_input_dtd_2);
1380 }
1381
1382 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1383 {
1384 u16 this_output = (1 << o);
1385 if (sdvo_priv->caps.output_flags & this_output)
1386 {
21d40d37
EA		 1387 intel_sdvo_set_target_output(intel_encoder, this_output);
1388 intel_sdvo_get_output_timing(intel_encoder,
79e53945
JB		 1389 &sdvo_priv->save_output_dtd[o]);
1390 }
1391 }
e2f0ba97
JB		 1392 if (sdvo_priv->is_tv) {
1393 /* XXX: Save TV format/enhancements. */
1394 }
79e53945 1395
c751ce4f 1396 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->sdvo_reg);
79e53945
JB		 1397}
1398
1399static void intel_sdvo_restore(struct drm_connector *connector)
1400{
1401 struct drm_device *dev = connector->dev;
21d40d37
EA		 1402 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1403 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 1404 int o;
1405 int i;
1406 bool input1, input2;
1407 u8 status;
1408
21d40d37 1409 intel_sdvo_set_active_outputs(intel_encoder, 0);
79e53945
JB		 1410
1411 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1412 {
1413 u16 this_output = (1 << o);
1414 if (sdvo_priv->caps.output_flags & this_output) {
21d40d37
EA		 1415 intel_sdvo_set_target_output(intel_encoder, this_output);
1416 intel_sdvo_set_output_timing(intel_encoder, &sdvo_priv->save_output_dtd[o]);
79e53945
JB		 1417 }
1418 }
1419
1420 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
21d40d37
EA		 1421 intel_sdvo_set_target_input(intel_encoder, true, false);
1422 intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_1);
79e53945
JB		 1423 }
1424
1425 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
21d40d37
EA		 1426 intel_sdvo_set_target_input(intel_encoder, false, true);
1427 intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_2);
79e53945
JB		 1428 }
1429
21d40d37 1430 intel_sdvo_set_clock_rate_mult(intel_encoder, sdvo_priv->save_sdvo_mult);
79e53945 1431
e2f0ba97
JB		 1432 if (sdvo_priv->is_tv) {
1433 /* XXX: Restore TV format/enhancements. */
1434 }
1435
21d40d37 1436 intel_sdvo_write_sdvox(intel_encoder, sdvo_priv->save_SDVOX);
79e53945
JB		 1437
1438 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1439 {
1440 for (i = 0; i < 2; i++)
1441 intel_wait_for_vblank(dev);
21d40d37 1442 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1, &input2);
79e53945 1443 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
8a4c47f3
ZY		 1444 DRM_DEBUG_KMS("First %s output reported failure to "
1445 "sync\n", SDVO_NAME(sdvo_priv));
79e53945
JB		 1446 }
1447
21d40d37 1448 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->save_active_outputs);
79e53945
JB		 1449}
1450
1451static int intel_sdvo_mode_valid(struct drm_connector *connector,
1452 struct drm_display_mode *mode)
1453{
21d40d37
EA		 1454 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1455 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 1456
1457 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1458 return MODE_NO_DBLESCAN;
1459
1460 if (sdvo_priv->pixel_clock_min > mode->clock)
1461 return MODE_CLOCK_LOW;
1462
1463 if (sdvo_priv->pixel_clock_max < mode->clock)
1464 return MODE_CLOCK_HIGH;
1465
12682a97 1466 if (sdvo_priv->is_lvds == true) {
1467 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1468 return MODE_PANEL;
1469
1470 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1471 return MODE_PANEL;
1472
1473 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1474 return MODE_PANEL;
1475 }
1476
79e53945
JB		 1477 return MODE_OK;
1478}
1479
21d40d37 1480static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps)
79e53945
JB		 1481{
1482 u8 status;
1483
21d40d37
EA		 1484 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1485 status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
79e53945
JB		 1486 if (status != SDVO_CMD_STATUS_SUCCESS)
1487 return false;
1488
1489 return true;
1490}
1491
1492struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1493{
1494 struct drm_connector *connector = NULL;
21d40d37 1495 struct intel_encoder *iout = NULL;
79e53945
JB		 1496 struct intel_sdvo_priv *sdvo;
1497
1498 /* find the sdvo connector */
1499 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
21d40d37 1500 iout = to_intel_encoder(connector);
79e53945
JB		 1501
1502 if (iout->type != INTEL_OUTPUT_SDVO)
1503 continue;
1504
1505 sdvo = iout->dev_priv;
1506
c751ce4f 1507 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1508 return connector;
1509
c751ce4f 1510 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1511 return connector;
1512
1513 }
1514
1515 return NULL;
1516}
1517
1518int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1519{
1520 u8 response[2];
1521 u8 status;
21d40d37 1522 struct intel_encoder *intel_encoder;
8a4c47f3 1523 DRM_DEBUG_KMS("\n");
79e53945
JB		 1524
1525 if (!connector)
1526 return 0;
1527
21d40d37 1528 intel_encoder = to_intel_encoder(connector);
79e53945 1529
21d40d37
EA		 1530 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1531 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945
JB		 1532
1533 if (response[0] !=0)
1534 return 1;
1535
1536 return 0;
1537}
1538
1539void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1540{
1541 u8 response[2];
1542 u8 status;
21d40d37 1543 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
79e53945 1544
21d40d37
EA		 1545 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1546 intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945
JB		 1547
1548 if (on) {
21d40d37
EA		 1549 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1550 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945 1551
21d40d37 1552 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1553 } else {
1554 response[0] = 0;
1555 response[1] = 0;
21d40d37 1556 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1557 }
1558
21d40d37
EA		 1559 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1560 intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945
JB		 1561}
1562
fb7a46f3 1563static bool
21d40d37 1564intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder)
fb7a46f3 1565{
21d40d37 1566 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
fb7a46f3 1567 int caps = 0;
1568
1569 if (sdvo_priv->caps.output_flags &
1570 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1571 caps++;
1572 if (sdvo_priv->caps.output_flags &
1573 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1574 caps++;
1575 if (sdvo_priv->caps.output_flags &
19e1f888 1576 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1577 caps++;
1578 if (sdvo_priv->caps.output_flags &
1579 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1580 caps++;
1581 if (sdvo_priv->caps.output_flags &
1582 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1583 caps++;
1584
1585 if (sdvo_priv->caps.output_flags &
1586 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1587 caps++;
1588
1589 if (sdvo_priv->caps.output_flags &
1590 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1591 caps++;
1592
1593 return (caps > 1);
1594}
1595
57cdaf90
KP		 1596static struct drm_connector *
1597intel_find_analog_connector(struct drm_device *dev)
1598{
1599 struct drm_connector *connector;
21d40d37 1600 struct intel_encoder *intel_encoder;
57cdaf90
KP		 1601
1602 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
21d40d37
EA		 1603 intel_encoder = to_intel_encoder(connector);
1604 if (intel_encoder->type == INTEL_OUTPUT_ANALOG)
57cdaf90
KP		 1605 return connector;
1606 }
1607 return NULL;
1608}
1609
1610static int
1611intel_analog_is_connected(struct drm_device *dev)
1612{
1613 struct drm_connector *analog_connector;
1614 analog_connector = intel_find_analog_connector(dev);
1615
1616 if (!analog_connector)
1617 return false;
1618
1619 if (analog_connector->funcs->detect(analog_connector) ==
1620 connector_status_disconnected)
1621 return false;
1622
1623 return true;
1624}
1625
2b8d33f7 1626enum drm_connector_status
1627intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
9dff6af8 1628{
21d40d37
EA		 1629 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1630 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2b8d33f7 1631 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1632 struct edid *edid = NULL;
1633
21d40d37
EA		 1634 edid = drm_get_edid(&intel_encoder->base,
1635 intel_encoder->ddc_bus);
57cdaf90 1636
7c3f0a27 1637 /* This is only applied to SDVO cards with multiple outputs */
21d40d37 1638 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) {
7c3f0a27
ZY		 1639 uint8_t saved_ddc, temp_ddc;
1640 saved_ddc = sdvo_priv->ddc_bus;
1641 temp_ddc = sdvo_priv->ddc_bus >> 1;
1642 /*
1643 * Don't use the 1 as the argument of DDC bus switch to get
1644 * the EDID. It is used for SDVO SPD ROM.
1645 */
1646 while(temp_ddc > 1) {
1647 sdvo_priv->ddc_bus = temp_ddc;
21d40d37
EA		 1648 edid = drm_get_edid(&intel_encoder->base,
1649 intel_encoder->ddc_bus);
7c3f0a27
ZY		 1650 if (edid) {
1651 /*
1652 * When we can get the EDID, maybe it is the
1653 * correct DDC bus. Update it.
1654 */
1655 sdvo_priv->ddc_bus = temp_ddc;
1656 break;
1657 }
1658 temp_ddc >>= 1;
1659 }
1660 if (edid == NULL)
1661 sdvo_priv->ddc_bus = saved_ddc;
1662 }
57cdaf90
KP		 1663 /* when there is no edid and no monitor is connected with VGA
1664 * port, try to use the CRT ddc to read the EDID for DVI-connector
1665 */
1666 if (edid == NULL &&
1667 sdvo_priv->analog_ddc_bus &&
21d40d37
EA		 1668 !intel_analog_is_connected(intel_encoder->base.dev))
1669 edid = drm_get_edid(&intel_encoder->base,
57cdaf90 1670 sdvo_priv->analog_ddc_bus);
9dff6af8 1671 if (edid != NULL) {
2b8d33f7 1672 /* Don't report the output as connected if it's a DVI-I
1673 * connector with a non-digital EDID coming out.
1674 */
1675 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1676 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1677 sdvo_priv->is_hdmi =
1678 drm_detect_hdmi_monitor(edid);
1679 else
1680 status = connector_status_disconnected;
1681 }
1682
9dff6af8 1683 kfree(edid);
21d40d37 1684 intel_encoder->base.display_info.raw_edid = NULL;
2b8d33f7 1685
1686 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1687 status = connector_status_disconnected;
1688
1689 return status;
9dff6af8
ML		 1690}
1691
79e53945
JB		 1692static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1693{
fb7a46f3 1694 uint16_t response;
79e53945 1695 u8 status;
21d40d37
EA		 1696 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1697 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945 1698
21d40d37 1699 intel_sdvo_write_cmd(intel_encoder,
ce6feabd 1700 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
d09c23de
ZY		 1701 if (sdvo_priv->is_tv) {
1702 /* add 30ms delay when the output type is SDVO-TV */
1703 mdelay(30);
1704 }
21d40d37 1705 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945 1706
51c8b407 1707 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97
JB		 1708
1709 if (status != SDVO_CMD_STATUS_SUCCESS)
1710 return connector_status_unknown;
1711
fb7a46f3 1712 if (response == 0)
79e53945 1713 return connector_status_disconnected;
fb7a46f3 1714
21d40d37 1715 if (intel_sdvo_multifunc_encoder(intel_encoder) &&
fb7a46f3 1716 sdvo_priv->attached_output != response) {
1717 if (sdvo_priv->controlled_output != response &&
21d40d37 1718 intel_sdvo_output_setup(intel_encoder, response) != true)
fb7a46f3 1719 return connector_status_unknown;
1720 sdvo_priv->attached_output = response;
1721 }
2b8d33f7 1722 return intel_sdvo_hdmi_sink_detect(connector, response);
79e53945
JB		 1723}
1724
e2f0ba97 1725static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1726{
21d40d37
EA		 1727 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1728 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
57cdaf90 1729 int num_modes;
79e53945
JB		 1730
1731 /* set the bus switch and get the modes */
335af9a2 1732 num_modes = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
79e53945 1733
57cdaf90
KP		 1734 /*
1735 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1736 * link between analog and digital outputs. So, if the regular SDVO
1737 * DDC fails, check to see if the analog output is disconnected, in
1738 * which case we'll look there for the digital DDC data.
e2f0ba97 1739 */
57cdaf90
KP		 1740 if (num_modes == 0 &&
1741 sdvo_priv->analog_ddc_bus &&
21d40d37 1742 !intel_analog_is_connected(intel_encoder->base.dev)) {
57cdaf90
KP		 1743 /* Switch to the analog ddc bus and try that
1744 */
335af9a2 1745 (void) intel_ddc_get_modes(connector, sdvo_priv->analog_ddc_bus);
e2f0ba97 1746 }
e2f0ba97
JB		 1747}
1748
1749/*
1750 * Set of SDVO TV modes.
1751 * Note! This is in reply order (see loop in get_tv_modes).
1752 * XXX: all 60Hz refresh?
1753 */
1754struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1755 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1756 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1758 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1759 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1761 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1762 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1763 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1764 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1765 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1766 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1767 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1768 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1770 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1771 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1772 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1773 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1774 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1775 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1776 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1777 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1778 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1779 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1780 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1782 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1783 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1785 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1786 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1788 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1789 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1791 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1792 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1794 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1795 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1797 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1798 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1800 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1801 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1802 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1803 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1804 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1806 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1807 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1808 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1809 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1810 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1812};
1813
1814static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1815{
21d40d37 1816 struct intel_encoder *output = to_intel_encoder(connector);
7026d4ac
ZW		 1817 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1818 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1819 uint32_t reply = 0, format_map = 0;
1820 int i;
e2f0ba97 1821 uint8_t status;
e2f0ba97 1822
e2f0ba97
JB		 1823
1824 /* Read the list of supported input resolutions for the selected TV
1825 * format.
1826 */
ce6feabd
ZY		 1827 for (i = 0; i < TV_FORMAT_NUM; i++)
1828 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1829 break;
1830
1831 format_map = (1 << i);
1832 memcpy(&tv_res, &format_map,
1833 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1834 sizeof(format_map) ? sizeof(format_map) :
1835 sizeof(struct intel_sdvo_sdtv_resolution_request));
1836
1837 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1838
e2f0ba97 1839 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
7026d4ac 1840 &tv_res, sizeof(tv_res));
e2f0ba97
JB		 1841 status = intel_sdvo_read_response(output, &reply, 3);
1842 if (status != SDVO_CMD_STATUS_SUCCESS)
1843 return;
1844
1845 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1846 if (reply & (1 << i)) {
1847 struct drm_display_mode *nmode;
1848 nmode = drm_mode_duplicate(connector->dev,
1849 &sdvo_tv_modes[i]);
1850 if (nmode)
1851 drm_mode_probed_add(connector, nmode);
1852 }
ce6feabd 1853
e2f0ba97
JB		 1854}
1855
7086c87f
ML		 1856static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1857{
21d40d37 1858 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
7086c87f 1859 struct drm_i915_private *dev_priv = connector->dev->dev_private;
21d40d37 1860 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
12682a97 1861 struct drm_display_mode *newmode;
7086c87f
ML		 1862
1863 /*
1864 * Attempt to get the mode list from DDC.
1865 * Assume that the preferred modes are
1866 * arranged in priority order.
1867 */
335af9a2 1868 intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
7086c87f 1869 if (list_empty(&connector->probed_modes) == false)
12682a97 1870 goto end;
7086c87f
ML		 1871
1872 /* Fetch modes from VBT */
1873 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1874 newmode = drm_mode_duplicate(connector->dev,
1875 dev_priv->sdvo_lvds_vbt_mode);
1876 if (newmode != NULL) {
1877 /* Guarantee the mode is preferred */
1878 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1879 DRM_MODE_TYPE_DRIVER);
1880 drm_mode_probed_add(connector, newmode);
1881 }
1882 }
12682a97 1883
1884end:
1885 list_for_each_entry(newmode, &connector->probed_modes, head) {
1886 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1887 sdvo_priv->sdvo_lvds_fixed_mode =
1888 drm_mode_duplicate(connector->dev, newmode);
1889 break;
1890 }
1891 }
1892
7086c87f
ML		 1893}
1894
e2f0ba97
JB		 1895static int intel_sdvo_get_modes(struct drm_connector *connector)
1896{
21d40d37 1897 struct intel_encoder *output = to_intel_encoder(connector);
e2f0ba97
JB		 1898 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1899
1900 if (sdvo_priv->is_tv)
1901 intel_sdvo_get_tv_modes(connector);
7086c87f
ML		 1902 else if (sdvo_priv->is_lvds == true)
1903 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1904 else
1905 intel_sdvo_get_ddc_modes(connector);
1906
79e53945
JB		 1907 if (list_empty(&connector->probed_modes))
1908 return 0;
1909 return 1;
1910}
1911
b9219c5e
ZY		 1912static
1913void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1914{
21d40d37
EA		 1915 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1916 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
b9219c5e
ZY		 1917 struct drm_device *dev = connector->dev;
1918
1919 if (sdvo_priv->is_tv) {
1920 if (sdvo_priv->left_property)
1921 drm_property_destroy(dev, sdvo_priv->left_property);
1922 if (sdvo_priv->right_property)
1923 drm_property_destroy(dev, sdvo_priv->right_property);
1924 if (sdvo_priv->top_property)
1925 drm_property_destroy(dev, sdvo_priv->top_property);
1926 if (sdvo_priv->bottom_property)
1927 drm_property_destroy(dev, sdvo_priv->bottom_property);
1928 if (sdvo_priv->hpos_property)
1929 drm_property_destroy(dev, sdvo_priv->hpos_property);
1930 if (sdvo_priv->vpos_property)
1931 drm_property_destroy(dev, sdvo_priv->vpos_property);
1932 }
1933 if (sdvo_priv->is_tv) {
1934 if (sdvo_priv->saturation_property)
1935 drm_property_destroy(dev,
1936 sdvo_priv->saturation_property);
1937 if (sdvo_priv->contrast_property)
1938 drm_property_destroy(dev,
1939 sdvo_priv->contrast_property);
1940 if (sdvo_priv->hue_property)
1941 drm_property_destroy(dev, sdvo_priv->hue_property);
1942 }
d0cbde93 1943 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e
ZY		 1944 if (sdvo_priv->brightness_property)
1945 drm_property_destroy(dev,
1946 sdvo_priv->brightness_property);
1947 }
1948 return;
1949}
1950
79e53945
JB		 1951static void intel_sdvo_destroy(struct drm_connector *connector)
1952{
21d40d37
EA		 1953 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1954 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945 1955
21d40d37
EA		 1956 if (intel_encoder->i2c_bus)
1957 intel_i2c_destroy(intel_encoder->i2c_bus);
1958 if (intel_encoder->ddc_bus)
1959 intel_i2c_destroy(intel_encoder->ddc_bus);
57cdaf90
KP		 1960 if (sdvo_priv->analog_ddc_bus)
1961 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
619ac3b7 1962
12682a97 1963 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1964 drm_mode_destroy(connector->dev,
1965 sdvo_priv->sdvo_lvds_fixed_mode);
1966
ce6feabd
ZY		 1967 if (sdvo_priv->tv_format_property)
1968 drm_property_destroy(connector->dev,
1969 sdvo_priv->tv_format_property);
1970
d0cbde93 1971 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
b9219c5e
ZY		 1972 intel_sdvo_destroy_enhance_property(connector);
1973
79e53945
JB		 1974 drm_sysfs_connector_remove(connector);
1975 drm_connector_cleanup(connector);
12682a97 1976
21d40d37 1977 kfree(intel_encoder);
79e53945
JB		 1978}
1979
ce6feabd
ZY		 1980static int
1981intel_sdvo_set_property(struct drm_connector *connector,
1982 struct drm_property *property,
1983 uint64_t val)
1984{
21d40d37
EA		 1985 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1986 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1987 struct drm_encoder *encoder = &intel_encoder->enc;
ce6feabd
ZY		 1988 struct drm_crtc *crtc = encoder->crtc;
1989 int ret = 0;
1990 bool changed = false;
b9219c5e
ZY		 1991 uint8_t cmd, status;
1992 uint16_t temp_value;
ce6feabd
ZY		 1993
1994 ret = drm_connector_property_set_value(connector, property, val);
1995 if (ret < 0)
1996 goto out;
1997
1998 if (property == sdvo_priv->tv_format_property) {
1999 if (val >= TV_FORMAT_NUM) {
2000 ret = -EINVAL;
2001 goto out;
2002 }
2003 if (sdvo_priv->tv_format_name ==
2004 sdvo_priv->tv_format_supported[val])
2005 goto out;
2006
2007 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
2008 changed = true;
ce6feabd
ZY		 2009 }
2010
d0cbde93 2011 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e
ZY		 2012 cmd = 0;
2013 temp_value = val;
2014 if (sdvo_priv->left_property == property) {
2015 drm_connector_property_set_value(connector,
2016 sdvo_priv->right_property, val);
2017 if (sdvo_priv->left_margin == temp_value)
2018 goto out;
2019
2020 sdvo_priv->left_margin = temp_value;
2021 sdvo_priv->right_margin = temp_value;
2022 temp_value = sdvo_priv->max_hscan -
2023 sdvo_priv->left_margin;
2024 cmd = SDVO_CMD_SET_OVERSCAN_H;
2025 } else if (sdvo_priv->right_property == property) {
2026 drm_connector_property_set_value(connector,
2027 sdvo_priv->left_property, val);
2028 if (sdvo_priv->right_margin == temp_value)
2029 goto out;
2030
2031 sdvo_priv->left_margin = temp_value;
2032 sdvo_priv->right_margin = temp_value;
2033 temp_value = sdvo_priv->max_hscan -
2034 sdvo_priv->left_margin;
2035 cmd = SDVO_CMD_SET_OVERSCAN_H;
2036 } else if (sdvo_priv->top_property == property) {
2037 drm_connector_property_set_value(connector,
2038 sdvo_priv->bottom_property, val);
2039 if (sdvo_priv->top_margin == temp_value)
2040 goto out;
2041
2042 sdvo_priv->top_margin = temp_value;
2043 sdvo_priv->bottom_margin = temp_value;
2044 temp_value = sdvo_priv->max_vscan -
2045 sdvo_priv->top_margin;
2046 cmd = SDVO_CMD_SET_OVERSCAN_V;
2047 } else if (sdvo_priv->bottom_property == property) {
2048 drm_connector_property_set_value(connector,
2049 sdvo_priv->top_property, val);
2050 if (sdvo_priv->bottom_margin == temp_value)
2051 goto out;
2052 sdvo_priv->top_margin = temp_value;
2053 sdvo_priv->bottom_margin = temp_value;
2054 temp_value = sdvo_priv->max_vscan -
2055 sdvo_priv->top_margin;
2056 cmd = SDVO_CMD_SET_OVERSCAN_V;
2057 } else if (sdvo_priv->hpos_property == property) {
2058 if (sdvo_priv->cur_hpos == temp_value)
2059 goto out;
2060
2061 cmd = SDVO_CMD_SET_POSITION_H;
2062 sdvo_priv->cur_hpos = temp_value;
2063 } else if (sdvo_priv->vpos_property == property) {
2064 if (sdvo_priv->cur_vpos == temp_value)
2065 goto out;
2066
2067 cmd = SDVO_CMD_SET_POSITION_V;
2068 sdvo_priv->cur_vpos = temp_value;
2069 } else if (sdvo_priv->saturation_property == property) {
2070 if (sdvo_priv->cur_saturation == temp_value)
2071 goto out;
2072
2073 cmd = SDVO_CMD_SET_SATURATION;
2074 sdvo_priv->cur_saturation = temp_value;
2075 } else if (sdvo_priv->contrast_property == property) {
2076 if (sdvo_priv->cur_contrast == temp_value)
2077 goto out;
2078
2079 cmd = SDVO_CMD_SET_CONTRAST;
2080 sdvo_priv->cur_contrast = temp_value;
2081 } else if (sdvo_priv->hue_property == property) {
2082 if (sdvo_priv->cur_hue == temp_value)
2083 goto out;
2084
2085 cmd = SDVO_CMD_SET_HUE;
2086 sdvo_priv->cur_hue = temp_value;
2087 } else if (sdvo_priv->brightness_property == property) {
2088 if (sdvo_priv->cur_brightness == temp_value)
2089 goto out;
2090
2091 cmd = SDVO_CMD_SET_BRIGHTNESS;
2092 sdvo_priv->cur_brightness = temp_value;
2093 }
2094 if (cmd) {
21d40d37
EA		 2095 intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
2096 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2097 NULL, 0);
2098 if (status != SDVO_CMD_STATUS_SUCCESS) {
2099 DRM_DEBUG_KMS("Incorrect SDVO command \n");
2100 return -EINVAL;
2101 }
2102 changed = true;
2103 }
2104 }
ce6feabd
ZY		 2105 if (changed && crtc)
2106 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
2107 crtc->y, crtc->fb);
2108out:
2109 return ret;
2110}
2111
79e53945
JB		 2112static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2113 .dpms = intel_sdvo_dpms,
2114 .mode_fixup = intel_sdvo_mode_fixup,
2115 .prepare = intel_encoder_prepare,
2116 .mode_set = intel_sdvo_mode_set,
2117 .commit = intel_encoder_commit,
2118};
2119
2120static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 2121 .dpms = drm_helper_connector_dpms,
79e53945
JB		 2122 .save = intel_sdvo_save,
2123 .restore = intel_sdvo_restore,
2124 .detect = intel_sdvo_detect,
2125 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2126 .set_property = intel_sdvo_set_property,
79e53945
JB		 2127 .destroy = intel_sdvo_destroy,
2128};
2129
2130static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2131 .get_modes = intel_sdvo_get_modes,
2132 .mode_valid = intel_sdvo_mode_valid,
2133 .best_encoder = intel_best_encoder,
2134};
2135
b358d0a6 2136static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945
JB		 2137{
2138 drm_encoder_cleanup(encoder);
2139}
2140
2141static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2142 .destroy = intel_sdvo_enc_destroy,
2143};
2144
2145
e2f0ba97
JB		 2146/**
2147 * Choose the appropriate DDC bus for control bus switch command for this
2148 * SDVO output based on the controlled output.
2149 *
2150 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2151 * outputs, then LVDS outputs.
2152 */
2153static void
2154intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
2155{
2156 uint16_t mask = 0;
2157 unsigned int num_bits;
2158
2159 /* Make a mask of outputs less than or equal to our own priority in the
2160 * list.
2161 */
2162 switch (dev_priv->controlled_output) {
2163 case SDVO_OUTPUT_LVDS1:
2164 mask |= SDVO_OUTPUT_LVDS1;
2165 case SDVO_OUTPUT_LVDS0:
2166 mask |= SDVO_OUTPUT_LVDS0;
2167 case SDVO_OUTPUT_TMDS1:
2168 mask |= SDVO_OUTPUT_TMDS1;
2169 case SDVO_OUTPUT_TMDS0:
2170 mask |= SDVO_OUTPUT_TMDS0;
2171 case SDVO_OUTPUT_RGB1:
2172 mask |= SDVO_OUTPUT_RGB1;
2173 case SDVO_OUTPUT_RGB0:
2174 mask |= SDVO_OUTPUT_RGB0;
2175 break;
2176 }
2177
2178 /* Count bits to find what number we are in the priority list. */
2179 mask &= dev_priv->caps.output_flags;
2180 num_bits = hweight16(mask);
2181 if (num_bits > 3) {
2182 /* if more than 3 outputs, default to DDC bus 3 for now */
2183 num_bits = 3;
2184 }
2185
2186 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2187 dev_priv->ddc_bus = 1 << num_bits;
2188}
2189
2190static bool
21d40d37 2191intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output)
e2f0ba97
JB		 2192{
2193 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2194 uint8_t status;
2195
2196 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
2197
2198 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2199 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2200 if (status != SDVO_CMD_STATUS_SUCCESS)
2201 return false;
2202 return true;
2203}
2204
21d40d37
EA		 2205static struct intel_encoder *
2206intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan)
619ac3b7
ML		 2207{
2208 struct drm_device *dev = chan->drm_dev;
2209 struct drm_connector *connector;
21d40d37 2210 struct intel_encoder *intel_encoder = NULL;
619ac3b7
ML		 2211
2212 list_for_each_entry(connector,
2213 &dev->mode_config.connector_list, head) {
21d40d37
EA		 2214 if (to_intel_encoder(connector)->ddc_bus == &chan->adapter) {
2215 intel_encoder = to_intel_encoder(connector);
619ac3b7
ML		 2216 break;
2217 }
2218 }
21d40d37 2219 return intel_encoder;
619ac3b7
ML		 2220}
2221
2222static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2223 struct i2c_msg msgs[], int num)
2224{
21d40d37 2225 struct intel_encoder *intel_encoder;
619ac3b7
ML		 2226 struct intel_sdvo_priv *sdvo_priv;
2227 struct i2c_algo_bit_data *algo_data;
f9c10a9b 2228 const struct i2c_algorithm *algo;
619ac3b7
ML		 2229
2230 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
21d40d37
EA		 2231 intel_encoder =
2232 intel_sdvo_chan_to_intel_encoder(
619ac3b7 2233 (struct intel_i2c_chan *)(algo_data->data));
21d40d37 2234 if (intel_encoder == NULL)
619ac3b7
ML		 2235 return -EINVAL;
2236
21d40d37
EA		 2237 sdvo_priv = intel_encoder->dev_priv;
2238 algo = intel_encoder->i2c_bus->algo;
619ac3b7 2239
21d40d37 2240 intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus);
619ac3b7
ML		 2241 return algo->master_xfer(i2c_adap, msgs, num);
2242}
2243
2244static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2245 .master_xfer = intel_sdvo_master_xfer,
2246};
2247
714605e4 2248static u8
c751ce4f 2249intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2250{
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2252 struct sdvo_device_mapping *my_mapping, *other_mapping;
2253
c751ce4f 2254 if (sdvo_reg == SDVOB) {
714605e4 2255 my_mapping = &dev_priv->sdvo_mappings[0];
2256 other_mapping = &dev_priv->sdvo_mappings[1];
2257 } else {
2258 my_mapping = &dev_priv->sdvo_mappings[1];
2259 other_mapping = &dev_priv->sdvo_mappings[0];
2260 }
2261
2262 /* If the BIOS described our SDVO device, take advantage of it. */
2263 if (my_mapping->slave_addr)
2264 return my_mapping->slave_addr;
2265
2266 /* If the BIOS only described a different SDVO device, use the
2267 * address that it isn't using.
2268 */
2269 if (other_mapping->slave_addr) {
2270 if (other_mapping->slave_addr == 0x70)
2271 return 0x72;
2272 else
2273 return 0x70;
2274 }
2275
2276 /* No SDVO device info is found for another DVO port,
2277 * so use mapping assumption we had before BIOS parsing.
2278 */
c751ce4f 2279 if (sdvo_reg == SDVOB)
714605e4 2280 return 0x70;
2281 else
2282 return 0x72;
2283}
2284
6070a4a9
ZY		 2285static int intel_sdvo_bad_tv_callback(const struct dmi_system_id *id)
2286{
2287 DRM_DEBUG_KMS("Ignoring bad SDVO TV connector for %s\n", id->ident);
2288 return 1;
2289}
2290
2291static struct dmi_system_id intel_sdvo_bad_tv[] = {
2292 {
2293 .callback = intel_sdvo_bad_tv_callback,
2294 .ident = "IntelG45/ICH10R/DME1737",
2295 .matches = {
2296 DMI_MATCH(DMI_SYS_VENDOR, "IBM CORPORATION"),
2297 DMI_MATCH(DMI_PRODUCT_NAME, "4800784"),
2298 },
2299 },
2300
2301 { } /* terminating entry */
2302};
2303
fb7a46f3 2304static bool
21d40d37 2305intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags)
fb7a46f3 2306{
21d40d37
EA		 2307 struct drm_connector *connector = &intel_encoder->base;
2308 struct drm_encoder *encoder = &intel_encoder->enc;
2309 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
fb7a46f3 2310 bool ret = true, registered = false;
2311
2312 sdvo_priv->is_tv = false;
21d40d37 2313 intel_encoder->needs_tv_clock = false;
fb7a46f3 2314 sdvo_priv->is_lvds = false;
2315
2316 if (device_is_registered(&connector->kdev)) {
2317 drm_sysfs_connector_remove(connector);
2318 registered = true;
2319 }
2320
2321 if (flags &
2322 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
2323 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
2324 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2325 else
2326 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2327
2328 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2329 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2330
21d40d37 2331 if (intel_sdvo_get_supp_encode(intel_encoder,
fb7a46f3 2332 &sdvo_priv->encode) &&
21d40d37 2333 intel_sdvo_get_digital_encoding_mode(intel_encoder) &&
fb7a46f3 2334 sdvo_priv->is_hdmi) {
2335 /* enable hdmi encoding mode if supported */
21d40d37
EA		 2336 intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI);
2337 intel_sdvo_set_colorimetry(intel_encoder,
fb7a46f3 2338 SDVO_COLORIMETRY_RGB256);
2339 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
21d40d37 2340 intel_encoder->clone_mask =
f8aed700
ML		 2341 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2342 (1 << INTEL_ANALOG_CLONE_BIT);
fb7a46f3 2343 }
6070a4a9
ZY		 2344 } else if ((flags & SDVO_OUTPUT_SVID0) &&
2345 !dmi_check_system(intel_sdvo_bad_tv)) {
fb7a46f3 2346
2347 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2348 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2349 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2350 sdvo_priv->is_tv = true;
21d40d37
EA		 2351 intel_encoder->needs_tv_clock = true;
2352 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
fb7a46f3 2353 } else if (flags & SDVO_OUTPUT_RGB0) {
2354
2355 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2356 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2357 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
21d40d37 2358 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
f8aed700 2359 (1 << INTEL_ANALOG_CLONE_BIT);
fb7a46f3 2360 } else if (flags & SDVO_OUTPUT_RGB1) {
2361
2362 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2363 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2364 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
21d40d37 2365 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
e270846f 2366 (1 << INTEL_ANALOG_CLONE_BIT);
2dd87383
ZY		 2367 } else if (flags & SDVO_OUTPUT_CVBS0) {
2368
2369 sdvo_priv->controlled_output = SDVO_OUTPUT_CVBS0;
2370 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2371 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2372 sdvo_priv->is_tv = true;
21d40d37
EA		 2373 intel_encoder->needs_tv_clock = true;
2374 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
fb7a46f3 2375 } else if (flags & SDVO_OUTPUT_LVDS0) {
2376
2377 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2378 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2379 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2380 sdvo_priv->is_lvds = true;
21d40d37 2381 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
f8aed700 2382 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
fb7a46f3 2383 } else if (flags & SDVO_OUTPUT_LVDS1) {
2384
2385 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2386 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2387 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2388 sdvo_priv->is_lvds = true;
21d40d37 2389 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
f8aed700 2390 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
fb7a46f3 2391 } else {
2392
2393 unsigned char bytes[2];
2394
2395 sdvo_priv->controlled_output = 0;
2396 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
51c8b407
DA		 2397 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2398 SDVO_NAME(sdvo_priv),
2399 bytes[0], bytes[1]);
fb7a46f3 2400 ret = false;
2401 }
21d40d37 2402 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2403
2404 if (ret && registered)
2405 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2406
2407
2408 return ret;
2409
2410}
2411
ce6feabd
ZY		 2412static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2413{
21d40d37
EA		 2414 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2415 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
ce6feabd
ZY		 2416 struct intel_sdvo_tv_format format;
2417 uint32_t format_map, i;
2418 uint8_t status;
2419
21d40d37 2420 intel_sdvo_set_target_output(intel_encoder,
ce6feabd
ZY		 2421 sdvo_priv->controlled_output);
2422
21d40d37 2423 intel_sdvo_write_cmd(intel_encoder,
ce6feabd 2424 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
21d40d37 2425 status = intel_sdvo_read_response(intel_encoder,
ce6feabd
ZY		 2426 &format, sizeof(format));
2427 if (status != SDVO_CMD_STATUS_SUCCESS)
2428 return;
2429
2430 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2431 sizeof(format_map) : sizeof(format));
2432
2433 if (format_map == 0)
2434 return;
2435
2436 sdvo_priv->format_supported_num = 0;
2437 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2438 if (format_map & (1 << i)) {
2439 sdvo_priv->tv_format_supported
2440 [sdvo_priv->format_supported_num++] =
2441 tv_format_names[i];
2442 }
2443
2444
2445 sdvo_priv->tv_format_property =
2446 drm_property_create(
2447 connector->dev, DRM_MODE_PROP_ENUM,
2448 "mode", sdvo_priv->format_supported_num);
2449
2450 for (i = 0; i < sdvo_priv->format_supported_num; i++)
2451 drm_property_add_enum(
2452 sdvo_priv->tv_format_property, i,
2453 i, sdvo_priv->tv_format_supported[i]);
2454
2455 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2456 drm_connector_attach_property(
2457 connector, sdvo_priv->tv_format_property, 0);
2458
2459}
2460
b9219c5e
ZY		 2461static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2462{
21d40d37
EA		 2463 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2464 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
b9219c5e
ZY		 2465 struct intel_sdvo_enhancements_reply sdvo_data;
2466 struct drm_device *dev = connector->dev;
2467 uint8_t status;
2468 uint16_t response, data_value[2];
2469
21d40d37 2470 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
b9219c5e 2471 NULL, 0);
21d40d37 2472 status = intel_sdvo_read_response(intel_encoder, &sdvo_data,
b9219c5e
ZY		 2473 sizeof(sdvo_data));
2474 if (status != SDVO_CMD_STATUS_SUCCESS) {
2475 DRM_DEBUG_KMS(" incorrect response is returned\n");
2476 return;
2477 }
2478 response = *((uint16_t *)&sdvo_data);
2479 if (!response) {
2480 DRM_DEBUG_KMS("No enhancement is supported\n");
2481 return;
2482 }
2483 if (sdvo_priv->is_tv) {
2484 /* when horizontal overscan is supported, Add the left/right
2485 * property
2486 */
2487 if (sdvo_data.overscan_h) {
21d40d37 2488 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2489 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
21d40d37 2490 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2491 &data_value, 4);
2492 if (status != SDVO_CMD_STATUS_SUCCESS) {
2493 DRM_DEBUG_KMS("Incorrect SDVO max "
2494 "h_overscan\n");
2495 return;
2496 }
21d40d37 2497 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2498 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
21d40d37 2499 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2500 &response, 2);
2501 if (status != SDVO_CMD_STATUS_SUCCESS) {
2502 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2503 return;
2504 }
2505 sdvo_priv->max_hscan = data_value[0];
2506 sdvo_priv->left_margin = data_value[0] - response;
2507 sdvo_priv->right_margin = sdvo_priv->left_margin;
2508 sdvo_priv->left_property =
2509 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2510 "left_margin", 2);
2511 sdvo_priv->left_property->values[0] = 0;
2512 sdvo_priv->left_property->values[1] = data_value[0];
2513 drm_connector_attach_property(connector,
2514 sdvo_priv->left_property,
2515 sdvo_priv->left_margin);
2516 sdvo_priv->right_property =
2517 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2518 "right_margin", 2);
2519 sdvo_priv->right_property->values[0] = 0;
2520 sdvo_priv->right_property->values[1] = data_value[0];
2521 drm_connector_attach_property(connector,
2522 sdvo_priv->right_property,
2523 sdvo_priv->right_margin);
2524 DRM_DEBUG_KMS("h_overscan: max %d, "
2525 "default %d, current %d\n",
2526 data_value[0], data_value[1], response);
2527 }
2528 if (sdvo_data.overscan_v) {
21d40d37 2529 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2530 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
21d40d37 2531 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2532 &data_value, 4);
2533 if (status != SDVO_CMD_STATUS_SUCCESS) {
2534 DRM_DEBUG_KMS("Incorrect SDVO max "
2535 "v_overscan\n");
2536 return;
2537 }
21d40d37 2538 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2539 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
21d40d37 2540 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2541 &response, 2);
2542 if (status != SDVO_CMD_STATUS_SUCCESS) {
2543 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2544 return;
2545 }
2546 sdvo_priv->max_vscan = data_value[0];
2547 sdvo_priv->top_margin = data_value[0] - response;
2548 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2549 sdvo_priv->top_property =
2550 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2551 "top_margin", 2);
2552 sdvo_priv->top_property->values[0] = 0;
2553 sdvo_priv->top_property->values[1] = data_value[0];
2554 drm_connector_attach_property(connector,
2555 sdvo_priv->top_property,
2556 sdvo_priv->top_margin);
2557 sdvo_priv->bottom_property =
2558 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2559 "bottom_margin", 2);
2560 sdvo_priv->bottom_property->values[0] = 0;
2561 sdvo_priv->bottom_property->values[1] = data_value[0];
2562 drm_connector_attach_property(connector,
2563 sdvo_priv->bottom_property,
2564 sdvo_priv->bottom_margin);
2565 DRM_DEBUG_KMS("v_overscan: max %d, "
2566 "default %d, current %d\n",
2567 data_value[0], data_value[1], response);
2568 }
2569 if (sdvo_data.position_h) {
21d40d37 2570 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2571 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
21d40d37 2572 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2573 &data_value, 4);
2574 if (status != SDVO_CMD_STATUS_SUCCESS) {
2575 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2576 return;
2577 }
21d40d37 2578 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2579 SDVO_CMD_GET_POSITION_H, NULL, 0);
21d40d37 2580 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2581 &response, 2);
2582 if (status != SDVO_CMD_STATUS_SUCCESS) {
2583 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2584 return;
2585 }
2586 sdvo_priv->max_hpos = data_value[0];
2587 sdvo_priv->cur_hpos = response;
2588 sdvo_priv->hpos_property =
2589 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2590 "hpos", 2);
2591 sdvo_priv->hpos_property->values[0] = 0;
2592 sdvo_priv->hpos_property->values[1] = data_value[0];
2593 drm_connector_attach_property(connector,
2594 sdvo_priv->hpos_property,
2595 sdvo_priv->cur_hpos);
2596 DRM_DEBUG_KMS("h_position: max %d, "
2597 "default %d, current %d\n",
2598 data_value[0], data_value[1], response);
2599 }
2600 if (sdvo_data.position_v) {
21d40d37 2601 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2602 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
21d40d37 2603 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2604 &data_value, 4);
2605 if (status != SDVO_CMD_STATUS_SUCCESS) {
2606 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2607 return;
2608 }
21d40d37 2609 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2610 SDVO_CMD_GET_POSITION_V, NULL, 0);
21d40d37 2611 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2612 &response, 2);
2613 if (status != SDVO_CMD_STATUS_SUCCESS) {
2614 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2615 return;
2616 }
2617 sdvo_priv->max_vpos = data_value[0];
2618 sdvo_priv->cur_vpos = response;
2619 sdvo_priv->vpos_property =
2620 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2621 "vpos", 2);
2622 sdvo_priv->vpos_property->values[0] = 0;
2623 sdvo_priv->vpos_property->values[1] = data_value[0];
2624 drm_connector_attach_property(connector,
2625 sdvo_priv->vpos_property,
2626 sdvo_priv->cur_vpos);
2627 DRM_DEBUG_KMS("v_position: max %d, "
2628 "default %d, current %d\n",
2629 data_value[0], data_value[1], response);
2630 }
2631 }
2632 if (sdvo_priv->is_tv) {
2633 if (sdvo_data.saturation) {
21d40d37 2634 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2635 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
21d40d37 2636 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2637 &data_value, 4);
2638 if (status != SDVO_CMD_STATUS_SUCCESS) {
2639 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2640 return;
2641 }
21d40d37 2642 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2643 SDVO_CMD_GET_SATURATION, NULL, 0);
21d40d37 2644 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2645 &response, 2);
2646 if (status != SDVO_CMD_STATUS_SUCCESS) {
2647 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2648 return;
2649 }
2650 sdvo_priv->max_saturation = data_value[0];
2651 sdvo_priv->cur_saturation = response;
2652 sdvo_priv->saturation_property =
2653 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2654 "saturation", 2);
2655 sdvo_priv->saturation_property->values[0] = 0;
2656 sdvo_priv->saturation_property->values[1] =
2657 data_value[0];
2658 drm_connector_attach_property(connector,
2659 sdvo_priv->saturation_property,
2660 sdvo_priv->cur_saturation);
2661 DRM_DEBUG_KMS("saturation: max %d, "
2662 "default %d, current %d\n",
2663 data_value[0], data_value[1], response);
2664 }
2665 if (sdvo_data.contrast) {
21d40d37 2666 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2667 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
21d40d37 2668 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2669 &data_value, 4);
2670 if (status != SDVO_CMD_STATUS_SUCCESS) {
2671 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2672 return;
2673 }
21d40d37 2674 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2675 SDVO_CMD_GET_CONTRAST, NULL, 0);
21d40d37 2676 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2677 &response, 2);
2678 if (status != SDVO_CMD_STATUS_SUCCESS) {
2679 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2680 return;
2681 }
2682 sdvo_priv->max_contrast = data_value[0];
2683 sdvo_priv->cur_contrast = response;
2684 sdvo_priv->contrast_property =
2685 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2686 "contrast", 2);
2687 sdvo_priv->contrast_property->values[0] = 0;
2688 sdvo_priv->contrast_property->values[1] = data_value[0];
2689 drm_connector_attach_property(connector,
2690 sdvo_priv->contrast_property,
2691 sdvo_priv->cur_contrast);
2692 DRM_DEBUG_KMS("contrast: max %d, "
2693 "default %d, current %d\n",
2694 data_value[0], data_value[1], response);
2695 }
2696 if (sdvo_data.hue) {
21d40d37 2697 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2698 SDVO_CMD_GET_MAX_HUE, NULL, 0);
21d40d37 2699 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2700 &data_value, 4);
2701 if (status != SDVO_CMD_STATUS_SUCCESS) {
2702 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2703 return;
2704 }
21d40d37 2705 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2706 SDVO_CMD_GET_HUE, NULL, 0);
21d40d37 2707 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2708 &response, 2);
2709 if (status != SDVO_CMD_STATUS_SUCCESS) {
2710 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2711 return;
2712 }
2713 sdvo_priv->max_hue = data_value[0];
2714 sdvo_priv->cur_hue = response;
2715 sdvo_priv->hue_property =
2716 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2717 "hue", 2);
2718 sdvo_priv->hue_property->values[0] = 0;
2719 sdvo_priv->hue_property->values[1] =
2720 data_value[0];
2721 drm_connector_attach_property(connector,
2722 sdvo_priv->hue_property,
2723 sdvo_priv->cur_hue);
2724 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2725 data_value[0], data_value[1], response);
2726 }
2727 }
d0cbde93 2728 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e 2729 if (sdvo_data.brightness) {
21d40d37 2730 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2731 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
21d40d37 2732 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2733 &data_value, 4);
2734 if (status != SDVO_CMD_STATUS_SUCCESS) {
2735 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2736 return;
2737 }
21d40d37 2738 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2739 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
21d40d37 2740 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2741 &response, 2);
2742 if (status != SDVO_CMD_STATUS_SUCCESS) {
2743 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2744 return;
2745 }
2746 sdvo_priv->max_brightness = data_value[0];
2747 sdvo_priv->cur_brightness = response;
2748 sdvo_priv->brightness_property =
2749 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2750 "brightness", 2);
2751 sdvo_priv->brightness_property->values[0] = 0;
2752 sdvo_priv->brightness_property->values[1] =
2753 data_value[0];
2754 drm_connector_attach_property(connector,
2755 sdvo_priv->brightness_property,
2756 sdvo_priv->cur_brightness);
2757 DRM_DEBUG_KMS("brightness: max %d, "
2758 "default %d, current %d\n",
2759 data_value[0], data_value[1], response);
2760 }
2761 }
2762 return;
2763}
2764
c751ce4f 2765bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2766{
b01f2c3a 2767 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2768 struct drm_connector *connector;
21d40d37 2769 struct intel_encoder *intel_encoder;
79e53945 2770 struct intel_sdvo_priv *sdvo_priv;
f9c10a9b 2771
79e53945
JB		 2772 u8 ch[0x40];
2773 int i;
79e53945 2774
21d40d37
EA		 2775 intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2776 if (!intel_encoder) {
7d57382e 2777 return false;
79e53945
JB		 2778 }
2779
21d40d37 2780 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);
c751ce4f 2781 sdvo_priv->sdvo_reg = sdvo_reg;
308cd3a2 2782
21d40d37
EA		 2783 intel_encoder->dev_priv = sdvo_priv;
2784 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2785
79e53945 2786 /* setup the DDC bus. */
c751ce4f 2787 if (sdvo_reg == SDVOB)
21d40d37 2788 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
308cd3a2 2789 else
21d40d37 2790 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
308cd3a2 2791
21d40d37 2792 if (!intel_encoder->i2c_bus)
ad5b2a6d 2793 goto err_inteloutput;
79e53945 2794
c751ce4f 2795 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2796
308cd3a2 2797 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2798 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2799
79e53945
JB		 2800 /* Read the regs to test if we can talk to the device */
2801 for (i = 0; i < 0x40; i++) {
21d40d37 2802 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {
8a4c47f3 2803 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
c751ce4f 2804 sdvo_reg == SDVOB ? 'B' : 'C');
79e53945
JB		 2805 goto err_i2c;
2806 }
2807 }
2808
619ac3b7 2809 /* setup the DDC bus. */
c751ce4f 2810 if (sdvo_reg == SDVOB) {
21d40d37 2811 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
57cdaf90
KP		 2812 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2813 "SDVOB/VGA DDC BUS");
b01f2c3a 2814 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2815 } else {
21d40d37 2816 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
57cdaf90
KP		 2817 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2818 "SDVOC/VGA DDC BUS");
b01f2c3a 2819 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2820 }
619ac3b7 2821
21d40d37 2822 if (intel_encoder->ddc_bus == NULL)
619ac3b7
ML		 2823 goto err_i2c;
2824
308cd3a2 2825 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2826 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2827
af901ca1 2828 /* In default case sdvo lvds is false */
21d40d37 2829 intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps);
79e53945 2830
21d40d37 2831 if (intel_sdvo_output_setup(intel_encoder,
fb7a46f3 2832 sdvo_priv->caps.output_flags) != true) {
51c8b407 2833 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
c751ce4f 2834 sdvo_reg == SDVOB ? 'B' : 'C');
79e53945
JB		 2835 goto err_i2c;
2836 }
2837
fb7a46f3 2838
21d40d37 2839 connector = &intel_encoder->base;
ad5b2a6d 2840 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
fb7a46f3 2841 connector->connector_type);
2842
ad5b2a6d
JB		 2843 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2844 connector->interlace_allowed = 0;
2845 connector->doublescan_allowed = 0;
2846 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2847
21d40d37
EA		 2848 drm_encoder_init(dev, &intel_encoder->enc,
2849 &intel_sdvo_enc_funcs, intel_encoder->enc.encoder_type);
fb7a46f3 2850
21d40d37 2851 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
79e53945 2852
21d40d37 2853 drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc);
d0cbde93 2854 if (sdvo_priv->is_tv)
ce6feabd 2855 intel_sdvo_tv_create_property(connector);
d0cbde93
ZY		 2856
2857 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
b9219c5e 2858 intel_sdvo_create_enhance_property(connector);
d0cbde93 2859
79e53945
JB		 2860 drm_sysfs_connector_add(connector);
2861
e2f0ba97
JB		 2862 intel_sdvo_select_ddc_bus(sdvo_priv);
2863
79e53945 2864 /* Set the input timing to the screen. Assume always input 0. */
21d40d37 2865 intel_sdvo_set_target_input(intel_encoder, true, false);
79e53945 2866
21d40d37 2867 intel_sdvo_get_input_pixel_clock_range(intel_encoder,
79e53945
JB		 2868 &sdvo_priv->pixel_clock_min,
2869 &sdvo_priv->pixel_clock_max);
2870
2871
8a4c47f3 2872 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2873 "clock range %dMHz - %dMHz, "
2874 "input 1: %c, input 2: %c, "
2875 "output 1: %c, output 2: %c\n",
2876 SDVO_NAME(sdvo_priv),
2877 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2878 sdvo_priv->caps.device_rev_id,
2879 sdvo_priv->pixel_clock_min / 1000,
2880 sdvo_priv->pixel_clock_max / 1000,
2881 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2882 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2883 /* check currently supported outputs */
2884 sdvo_priv->caps.output_flags &
79e53945 2885 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
342dc382 2886 sdvo_priv->caps.output_flags &
79e53945
JB		 2887 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2888
7d57382e 2889 return true;
79e53945
JB		 2890
2891err_i2c:
57cdaf90
KP		 2892 if (sdvo_priv->analog_ddc_bus != NULL)
2893 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
21d40d37
EA		 2894 if (intel_encoder->ddc_bus != NULL)
2895 intel_i2c_destroy(intel_encoder->ddc_bus);
2896 if (intel_encoder->i2c_bus != NULL)
2897 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2898err_inteloutput:
21d40d37 2899 kfree(intel_encoder);
79e53945 2900
7d57382e 2901 return false;
79e53945 2902}
Clone of davem's net-next-2.6 tree