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Merge branch 'x86/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux...
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
2e88e40b 53static const char *tv_format_names[] = {
ce6feabd
ZY		 54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f9c10a9b 68 u8 slave_addr;
e2f0ba97
JB		 69
70 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 71 int sdvo_reg;
79e53945 72
e2f0ba97
JB		 73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
79e53945 75
e2f0ba97
JB		 76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
79e53945 80 struct intel_sdvo_caps caps;
e2f0ba97
JB		 81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 83 int pixel_clock_min, pixel_clock_max;
84
fb7a46f3 85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
e2f0ba97
JB		 91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
ce6feabd 100 /* This is for current tv format name */
40039750 101 int tv_format_index;
ce6feabd 102
e2f0ba97
JB		 103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
12682a97 107
7086c87f
ML		 108 /**
109 * This is set if we detect output of sdvo device as LVDS.
110 */
111 bool is_lvds;
e2f0ba97 112
12682a97 113 /**
114 * This is sdvo flags for input timing.
115 */
116 uint8_t sdvo_flags;
117
118 /**
119 * This is sdvo fixed pannel mode pointer
120 */
121 struct drm_display_mode *sdvo_lvds_fixed_mode;
122
e2f0ba97
JB		 123 /*
124 * supported encoding mode, used to determine whether HDMI is
125 * supported
126 */
127 struct intel_sdvo_encode encode;
128
c751ce4f 129 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 130 uint8_t ddc_bus;
131
57cdaf90
KP		 132 /* Mac mini hack -- use the same DDC as the analog connector */
133 struct i2c_adapter *analog_ddc_bus;
134
14571b4c
ZW		 135};
136
137struct intel_sdvo_connector {
615fb93f
CW		 138 struct intel_connector base;
139
14571b4c
ZW		 140 /* Mark the type of connector */
141 uint16_t output_flag;
142
143 /* This contains all current supported TV format */
40039750 144 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 145 int format_supported_num;
c5521706 146 struct drm_property *tv_format;
14571b4c 147
b9219c5e 148 /* add the property for the SDVO-TV */
c5521706
CW		 149 struct drm_property *left;
150 struct drm_property *right;
151 struct drm_property *top;
152 struct drm_property *bottom;
153 struct drm_property *hpos;
154 struct drm_property *vpos;
155 struct drm_property *contrast;
156 struct drm_property *saturation;
157 struct drm_property *hue;
158 struct drm_property *sharpness;
159 struct drm_property *flicker_filter;
160 struct drm_property *flicker_filter_adaptive;
161 struct drm_property *flicker_filter_2d;
162 struct drm_property *tv_chroma_filter;
163 struct drm_property *tv_luma_filter;
e044218a 164 struct drm_property *dot_crawl;
b9219c5e
ZY		 165
166 /* add the property for the SDVO-TV/LVDS */
c5521706 167 struct drm_property *brightness;
b9219c5e
ZY		 168
169 /* Add variable to record current setting for the above property */
170 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 171
b9219c5e
ZY		 172 /* this is to get the range of margin.*/
173 u32 max_hscan, max_vscan;
174 u32 max_hpos, cur_hpos;
175 u32 max_vpos, cur_vpos;
176 u32 cur_brightness, max_brightness;
177 u32 cur_contrast, max_contrast;
178 u32 cur_saturation, max_saturation;
179 u32 cur_hue, max_hue;
c5521706
CW		 180 u32 cur_sharpness, max_sharpness;
181 u32 cur_flicker_filter, max_flicker_filter;
182 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
183 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
184 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
185 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 186 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 187};
188
ea5b213a
CW		 189static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
190{
191 return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base);
192}
193
615fb93f
CW		 194static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
195{
196 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
197}
198
fb7a46f3 199static bool
ea5b213a 200intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 201static bool
202intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
203 struct intel_sdvo_connector *intel_sdvo_connector,
204 int type);
205static bool
206intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
207 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 208
79e53945
JB		 209/**
210 * Writes the SDVOB or SDVOC with the given value, but always writes both
211 * SDVOB and SDVOC to work around apparent hardware issues (according to
212 * comments in the BIOS).
213 */
ea5b213a 214static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 215{
ea5b213a 216 struct drm_device *dev = intel_sdvo->base.enc.dev;
79e53945 217 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 218 u32 bval = val, cval = val;
219 int i;
220
ea5b213a
CW		 221 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
222 I915_WRITE(intel_sdvo->sdvo_reg, val);
223 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 224 return;
225 }
226
ea5b213a 227 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 228 cval = I915_READ(SDVOC);
229 } else {
230 bval = I915_READ(SDVOB);
231 }
232 /*
233 * Write the registers twice for luck. Sometimes,
234 * writing them only once doesn't appear to 'stick'.
235 * The BIOS does this too. Yay, magic
236 */
237 for (i = 0; i < 2; i++)
238 {
239 I915_WRITE(SDVOB, bval);
240 I915_READ(SDVOB);
241 I915_WRITE(SDVOC, cval);
242 I915_READ(SDVOC);
243 }
244}
245
32aad86f 246static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 247{
32aad86f 248 u8 out_buf[2] = { addr, 0 };
79e53945 249 u8 buf[2];
79e53945
JB		 250 struct i2c_msg msgs[] = {
251 {
ea5b213a 252 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 253 .flags = 0,
254 .len = 1,
255 .buf = out_buf,
256 },
257 {
ea5b213a 258 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 259 .flags = I2C_M_RD,
260 .len = 1,
261 .buf = buf,
262 }
263 };
32aad86f 264 int ret;
79e53945 265
ea5b213a 266 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
79e53945
JB		 267 {
268 *ch = buf[0];
269 return true;
270 }
271
8a4c47f3 272 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 273 return false;
274}
275
32aad86f 276static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
79e53945 277{
32aad86f 278 u8 out_buf[2] = { addr, ch };
79e53945
JB		 279 struct i2c_msg msgs[] = {
280 {
ea5b213a 281 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 282 .flags = 0,
283 .len = 2,
284 .buf = out_buf,
285 }
286 };
287
32aad86f 288 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
79e53945
JB		 289}
290
291#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
292/** Mapping of command numbers to names, for debug output */
005568be 293static const struct _sdvo_cmd_name {
e2f0ba97 294 u8 cmd;
2e88e40b 295 const char *name;
79e53945
JB		 296} sdvo_cmd_names[] = {
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
c5521706 340
b9219c5e 341 /* Add the op code for SDVO enhancements */
c5521706
CW		 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
b9219c5e
ZY		 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
c5521706
CW		 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
386
e2f0ba97
JB		 387 /* HDMI op code */
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 408};
409
461ed3ca 410#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 411#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 412
ea5b213a 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 414 const void *args, int args_len)
79e53945 415{
79e53945
JB		 416 int i;
417
8a4c47f3 418 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 419 SDVO_NAME(intel_sdvo), cmd);
79e53945 420 for (i = 0; i < args_len; i++)
342dc382 421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 422 for (; i < 8; i++)
342dc382 423 DRM_LOG_KMS(" ");
04ad327f 424 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 425 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 426 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 427 break;
428 }
429 }
04ad327f 430 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 431 DRM_LOG_KMS("(%02X)", cmd);
432 DRM_LOG_KMS("\n");
79e53945 433}
79e53945 434
32aad86f
CW		 435static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
436 const void *args, int args_len)
79e53945
JB		 437{
438 int i;
439
ea5b213a 440 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 441
442 for (i = 0; i < args_len; i++) {
32aad86f
CW		 443 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
444 ((u8*)args)[i]))
445 return false;
79e53945
JB		 446 }
447
32aad86f 448 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 449}
450
79e53945
JB		 451static const char *cmd_status_names[] = {
452 "Power on",
453 "Success",
454 "Not supported",
455 "Invalid arg",
456 "Pending",
457 "Target not specified",
458 "Scaling not supported"
459};
460
ea5b213a 461static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
79e53945
JB		 462 void *response, int response_len,
463 u8 status)
464{
33b52961 465 int i;
79e53945 466
ea5b213a 467 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 468 for (i = 0; i < response_len; i++)
342dc382 469 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 470 for (; i < 8; i++)
342dc382 471 DRM_LOG_KMS(" ");
79e53945 472 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 473 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 474 else
342dc382 475 DRM_LOG_KMS("(??? %d)", status);
476 DRM_LOG_KMS("\n");
79e53945 477}
79e53945 478
32aad86f
CW		 479static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
480 void *response, int response_len)
79e53945
JB		 481{
482 int i;
483 u8 status;
484 u8 retry = 50;
485
486 while (retry--) {
487 /* Read the command response */
488 for (i = 0; i < response_len; i++) {
32aad86f
CW		 489 if (!intel_sdvo_read_byte(intel_sdvo,
490 SDVO_I2C_RETURN_0 + i,
491 &((u8 *)response)[i]))
492 return false;
79e53945
JB		 493 }
494
495 /* read the return status */
32aad86f
CW		 496 if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
497 &status))
498 return false;
79e53945 499
ea5b213a 500 intel_sdvo_debug_response(intel_sdvo, response, response_len,
79e53945
JB		 501 status);
502 if (status != SDVO_CMD_STATUS_PENDING)
32aad86f 503 break;
79e53945
JB		 504
505 mdelay(50);
506 }
507
32aad86f 508 return status == SDVO_CMD_STATUS_SUCCESS;
79e53945
JB		 509}
510
b358d0a6 511static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 512{
513 if (mode->clock >= 100000)
514 return 1;
515 else if (mode->clock >= 50000)
516 return 2;
517 else
518 return 4;
519}
520
521/**
6a304caf
ZY		 522 * Try to read the response after issuie the DDC switch command. But it
523 * is noted that we must do the action of reading response and issuing DDC
524 * switch command in one I2C transaction. Otherwise when we try to start
525 * another I2C transaction after issuing the DDC bus switch, it will be
526 * switched to the internal SDVO register.
79e53945 527 */
ea5b213a 528static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
b358d0a6 529 u8 target)
79e53945 530{
6a304caf
ZY		 531 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
532 struct i2c_msg msgs[] = {
533 {
ea5b213a 534 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 535 .flags = 0,
536 .len = 2,
537 .buf = out_buf,
538 },
539 /* the following two are to read the response */
540 {
ea5b213a 541 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 542 .flags = 0,
543 .len = 1,
544 .buf = cmd_buf,
545 },
546 {
ea5b213a 547 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 548 .flags = I2C_M_RD,
549 .len = 1,
550 .buf = ret_value,
551 },
552 };
553
ea5b213a 554 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 555 &target, 1);
556 /* write the DDC switch command argument */
ea5b213a 557 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 558
559 out_buf[0] = SDVO_I2C_OPCODE;
560 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
561 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
562 cmd_buf[1] = 0;
563 ret_value[0] = 0;
564 ret_value[1] = 0;
565
ea5b213a 566 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
6a304caf
ZY		 567 if (ret != 3) {
568 /* failure in I2C transfer */
569 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
570 return;
571 }
572 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
573 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
574 ret_value[0]);
575 return;
576 }
577 return;
79e53945
JB		 578}
579
32aad86f 580static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 581{
32aad86f
CW		 582 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
583 return false;
79e53945 584
32aad86f
CW		 585 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
586}
79e53945 587
32aad86f
CW		 588static bool
589intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
590{
591 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
592 return false;
79e53945 593
32aad86f
CW		 594 return intel_sdvo_read_response(intel_sdvo, value, len);
595}
79e53945 596
32aad86f
CW		 597static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
598{
599 struct intel_sdvo_set_target_input_args targets = {0};
600 return intel_sdvo_set_value(intel_sdvo,
601 SDVO_CMD_SET_TARGET_INPUT,
602 &targets, sizeof(targets));
79e53945
JB		 603}
604
605/**
606 * Return whether each input is trained.
607 *
608 * This function is making an assumption about the layout of the response,
609 * which should be checked against the docs.
610 */
ea5b213a 611static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 612{
613 struct intel_sdvo_get_trained_inputs_response response;
79e53945 614
32aad86f
CW		 615 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
616 &response, sizeof(response)))
79e53945
JB		 617 return false;
618
619 *input_1 = response.input0_trained;
620 *input_2 = response.input1_trained;
621 return true;
622}
623
ea5b213a 624static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 625 u16 outputs)
626{
32aad86f
CW		 627 return intel_sdvo_set_value(intel_sdvo,
628 SDVO_CMD_SET_ACTIVE_OUTPUTS,
629 &outputs, sizeof(outputs));
79e53945
JB		 630}
631
ea5b213a 632static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 633 int mode)
634{
32aad86f 635 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 636
637 switch (mode) {
638 case DRM_MODE_DPMS_ON:
639 state = SDVO_ENCODER_STATE_ON;
640 break;
641 case DRM_MODE_DPMS_STANDBY:
642 state = SDVO_ENCODER_STATE_STANDBY;
643 break;
644 case DRM_MODE_DPMS_SUSPEND:
645 state = SDVO_ENCODER_STATE_SUSPEND;
646 break;
647 case DRM_MODE_DPMS_OFF:
648 state = SDVO_ENCODER_STATE_OFF;
649 break;
650 }
651
32aad86f
CW		 652 return intel_sdvo_set_value(intel_sdvo,
653 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 654}
655
ea5b213a 656static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 657 int *clock_min,
658 int *clock_max)
659{
660 struct intel_sdvo_pixel_clock_range clocks;
79e53945 661
32aad86f
CW		 662 if (!intel_sdvo_get_value(intel_sdvo,
663 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
664 &clocks, sizeof(clocks)))
79e53945
JB		 665 return false;
666
667 /* Convert the values from units of 10 kHz to kHz. */
668 *clock_min = clocks.min * 10;
669 *clock_max = clocks.max * 10;
79e53945
JB		 670 return true;
671}
672
ea5b213a 673static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 674 u16 outputs)
675{
32aad86f
CW		 676 return intel_sdvo_set_value(intel_sdvo,
677 SDVO_CMD_SET_TARGET_OUTPUT,
678 &outputs, sizeof(outputs));
79e53945
JB		 679}
680
ea5b213a 681static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 682 struct intel_sdvo_dtd *dtd)
683{
32aad86f
CW		 684 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
685 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 686}
687
ea5b213a 688static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 689 struct intel_sdvo_dtd *dtd)
690{
ea5b213a 691 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 692 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
693}
694
ea5b213a 695static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 696 struct intel_sdvo_dtd *dtd)
697{
ea5b213a 698 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 699 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
700}
701
e2f0ba97 702static bool
ea5b213a 703intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 704 uint16_t clock,
705 uint16_t width,
706 uint16_t height)
707{
708 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 709
e642c6f1 710 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 711 args.clock = clock;
712 args.width = width;
713 args.height = height;
e642c6f1 714 args.interlace = 0;
12682a97 715
ea5b213a
CW		 716 if (intel_sdvo->is_lvds &&
717 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
718 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 719 args.scaled = 1;
720
32aad86f
CW		 721 return intel_sdvo_set_value(intel_sdvo,
722 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
723 &args, sizeof(args));
e2f0ba97
JB		 724}
725
ea5b213a 726static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 727 struct intel_sdvo_dtd *dtd)
728{
32aad86f
CW		 729 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
730 &dtd->part1, sizeof(dtd->part1)) &&
731 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
732 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 733}
79e53945 734
ea5b213a 735static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 736{
32aad86f 737 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 738}
739
e2f0ba97 740static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 741 const struct drm_display_mode *mode)
79e53945 742{
e2f0ba97
JB		 743 uint16_t width, height;
744 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
745 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 746
747 width = mode->crtc_hdisplay;
748 height = mode->crtc_vdisplay;
749
750 /* do some mode translations */
751 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
752 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
753
754 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
755 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
756
757 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
758 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
759
e2f0ba97
JB		 760 dtd->part1.clock = mode->clock / 10;
761 dtd->part1.h_active = width & 0xff;
762 dtd->part1.h_blank = h_blank_len & 0xff;
763 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 764 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 765 dtd->part1.v_active = height & 0xff;
766 dtd->part1.v_blank = v_blank_len & 0xff;
767 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 768 ((v_blank_len >> 8) & 0xf);
769
171a9e96 770 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 771 dtd->part2.h_sync_width = h_sync_len & 0xff;
772 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 773 (v_sync_len & 0xf);
e2f0ba97 774 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 775 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
776 ((v_sync_len & 0x30) >> 4);
777
e2f0ba97 778 dtd->part2.dtd_flags = 0x18;
79e53945 779 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 780 dtd->part2.dtd_flags |= 0x2;
79e53945 781 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 782 dtd->part2.dtd_flags |= 0x4;
783
784 dtd->part2.sdvo_flags = 0;
785 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
786 dtd->part2.reserved = 0;
787}
788
789static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 790 const struct intel_sdvo_dtd *dtd)
e2f0ba97 791{
e2f0ba97
JB		 792 mode->hdisplay = dtd->part1.h_active;
793 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
794 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 795 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 796 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
797 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
798 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
799 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
800
801 mode->vdisplay = dtd->part1.v_active;
802 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
803 mode->vsync_start = mode->vdisplay;
804 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 805 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 806 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
807 mode->vsync_end = mode->vsync_start +
808 (dtd->part2.v_sync_off_width & 0xf);
809 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
810 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
811 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
812
813 mode->clock = dtd->part1.clock * 10;
814
171a9e96 815 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 816 if (dtd->part2.dtd_flags & 0x2)
817 mode->flags |= DRM_MODE_FLAG_PHSYNC;
818 if (dtd->part2.dtd_flags & 0x4)
819 mode->flags |= DRM_MODE_FLAG_PVSYNC;
820}
821
ea5b213a 822static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 823 struct intel_sdvo_encode *encode)
824{
32aad86f
CW		 825 if (intel_sdvo_get_value(intel_sdvo,
826 SDVO_CMD_GET_SUPP_ENCODE,
827 encode, sizeof(*encode)))
828 return true;
e2f0ba97 829
32aad86f
CW		 830 /* non-support means DVI */
831 memset(encode, 0, sizeof(*encode));
832 return false;
e2f0ba97
JB		 833}
834
ea5b213a 835static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 836 uint8_t mode)
e2f0ba97 837{
32aad86f 838 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 839}
840
ea5b213a 841static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 842 uint8_t mode)
843{
32aad86f 844 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 845}
846
847#if 0
ea5b213a 848static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 849{
850 int i, j;
851 uint8_t set_buf_index[2];
852 uint8_t av_split;
853 uint8_t buf_size;
854 uint8_t buf[48];
855 uint8_t *pos;
856
32aad86f 857 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 858
859 for (i = 0; i <= av_split; i++) {
860 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 861 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 862 set_buf_index, 2);
c751ce4f
EA		 863 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
864 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 865
866 pos = buf;
867 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 868 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 869 NULL, 0);
c751ce4f 870 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 871 pos += 8;
872 }
873 }
874}
875#endif
876
32aad86f 877static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 878 int index,
879 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 880{
881 uint8_t set_buf_index[2];
882
883 set_buf_index[0] = index;
884 set_buf_index[1] = 0;
885
32aad86f
CW		 886 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
887 set_buf_index, 2))
888 return false;
e2f0ba97
JB		 889
890 for (; size > 0; size -= 8) {
32aad86f
CW		 891 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
892 return false;
893
e2f0ba97
JB		 894 data += 8;
895 }
896
32aad86f 897 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 898}
899
900static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
901{
902 uint8_t csum = 0;
903 int i;
904
905 for (i = 0; i < size; i++)
906 csum += data[i];
907
908 return 0x100 - csum;
909}
910
911#define DIP_TYPE_AVI 0x82
912#define DIP_VERSION_AVI 0x2
913#define DIP_LEN_AVI 13
914
915struct dip_infoframe {
916 uint8_t type;
917 uint8_t version;
918 uint8_t len;
919 uint8_t checksum;
920 union {
921 struct {
922 /* Packet Byte #1 */
923 uint8_t S:2;
924 uint8_t B:2;
925 uint8_t A:1;
926 uint8_t Y:2;
927 uint8_t rsvd1:1;
928 /* Packet Byte #2 */
929 uint8_t R:4;
930 uint8_t M:2;
931 uint8_t C:2;
932 /* Packet Byte #3 */
933 uint8_t SC:2;
934 uint8_t Q:2;
935 uint8_t EC:3;
936 uint8_t ITC:1;
937 /* Packet Byte #4 */
938 uint8_t VIC:7;
939 uint8_t rsvd2:1;
940 /* Packet Byte #5 */
941 uint8_t PR:4;
942 uint8_t rsvd3:4;
943 /* Packet Byte #6~13 */
944 uint16_t top_bar_end;
945 uint16_t bottom_bar_start;
946 uint16_t left_bar_end;
947 uint16_t right_bar_start;
948 } avi;
949 struct {
950 /* Packet Byte #1 */
951 uint8_t channel_count:3;
952 uint8_t rsvd1:1;
953 uint8_t coding_type:4;
954 /* Packet Byte #2 */
955 uint8_t sample_size:2; /* SS0, SS1 */
956 uint8_t sample_frequency:3;
957 uint8_t rsvd2:3;
958 /* Packet Byte #3 */
959 uint8_t coding_type_private:5;
960 uint8_t rsvd3:3;
961 /* Packet Byte #4 */
962 uint8_t channel_allocation;
963 /* Packet Byte #5 */
964 uint8_t rsvd4:3;
965 uint8_t level_shift:4;
966 uint8_t downmix_inhibit:1;
967 } audio;
968 uint8_t payload[28];
969 } __attribute__ ((packed)) u;
970} __attribute__((packed));
971
32aad86f 972static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 973 struct drm_display_mode * mode)
974{
975 struct dip_infoframe avi_if = {
976 .type = DIP_TYPE_AVI,
977 .version = DIP_VERSION_AVI,
978 .len = DIP_LEN_AVI,
979 };
980
981 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
982 4 + avi_if.len);
32aad86f
CW		 983 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
984 4 + avi_if.len,
985 SDVO_HBUF_TX_VSYNC);
e2f0ba97
JB		 986}
987
32aad86f 988static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 989{
ce6feabd 990 struct intel_sdvo_tv_format format;
40039750 991 uint32_t format_map;
ce6feabd 992
40039750 993 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 994 memset(&format, 0, sizeof(format));
32aad86f 995 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 996
32aad86f
CW		 997 BUILD_BUG_ON(sizeof(format) != 6);
998 return intel_sdvo_set_value(intel_sdvo,
999 SDVO_CMD_SET_TV_FORMAT,
1000 &format, sizeof(format));
7026d4ac
ZW		 1001}
1002
32aad86f
CW		 1003static bool
1004intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1005 struct drm_display_mode *mode)
e2f0ba97 1006{
32aad86f 1007 struct intel_sdvo_dtd output_dtd;
79e53945 1008
32aad86f
CW		 1009 if (!intel_sdvo_set_target_output(intel_sdvo,
1010 intel_sdvo->attached_output))
1011 return false;
e2f0ba97 1012
32aad86f
CW		 1013 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1014 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1015 return false;
e2f0ba97 1016
32aad86f
CW		 1017 return true;
1018}
1019
1020static bool
1021intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1022 struct drm_display_mode *mode,
1023 struct drm_display_mode *adjusted_mode)
1024{
1025 struct intel_sdvo_dtd input_dtd;
e2f0ba97 1026
32aad86f
CW		 1027 /* Reset the input timing to the screen. Assume always input 0. */
1028 if (!intel_sdvo_set_target_input(intel_sdvo))
1029 return false;
e2f0ba97 1030
32aad86f
CW		 1031 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1032 mode->clock / 10,
1033 mode->hdisplay,
1034 mode->vdisplay))
1035 return false;
e2f0ba97 1036
32aad86f
CW		 1037 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1038 &input_dtd))
1039 return false;
e2f0ba97 1040
32aad86f
CW		 1041 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1042 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1043
32aad86f
CW		 1044 drm_mode_set_crtcinfo(adjusted_mode, 0);
1045 mode->clock = adjusted_mode->clock;
1046 return true;
1047}
12682a97 1048
32aad86f
CW		 1049static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1050 struct drm_display_mode *mode,
1051 struct drm_display_mode *adjusted_mode)
1052{
1053 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
12682a97 1054
32aad86f
CW		 1055 /* We need to construct preferred input timings based on our
1056 * output timings. To do that, we have to set the output
1057 * timings, even though this isn't really the right place in
1058 * the sequence to do it. Oh well.
1059 */
1060 if (intel_sdvo->is_tv) {
1061 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1062 return false;
12682a97 1063
c74696b9
PR		 1064 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1065 mode,
1066 adjusted_mode);
ea5b213a 1067 } else if (intel_sdvo->is_lvds) {
ea5b213a 1068 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
e2f0ba97 1069
32aad86f
CW		 1070 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1071 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1072 return false;
12682a97 1073
c74696b9
PR		 1074 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1075 mode,
1076 adjusted_mode);
e2f0ba97 1077 }
32aad86f
CW		 1078
1079 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1080 * SDVO device will be told of the multiplier during mode_set.
1081 */
1082 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1083
e2f0ba97
JB		 1084 return true;
1085}
1086
1087static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1088 struct drm_display_mode *mode,
1089 struct drm_display_mode *adjusted_mode)
1090{
1091 struct drm_device *dev = encoder->dev;
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 struct drm_crtc *crtc = encoder->crtc;
1094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a 1095 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
e2f0ba97 1096 u32 sdvox = 0;
32aad86f 1097 int sdvo_pixel_multiply, rate;
e2f0ba97
JB		 1098 struct intel_sdvo_in_out_map in_out;
1099 struct intel_sdvo_dtd input_dtd;
e2f0ba97
JB		 1100
1101 if (!mode)
1102 return;
1103
1104 /* First, set the input mapping for the first input to our controlled
1105 * output. This is only correct if we're a single-input device, in
1106 * which case the first input is the output from the appropriate SDVO
1107 * channel on the motherboard. In a two-input device, the first input
1108 * will be SDVOB and the second SDVOC.
1109 */
ea5b213a 1110 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1111 in_out.in1 = 0;
1112
c74696b9
PR		 1113 intel_sdvo_set_value(intel_sdvo,
1114 SDVO_CMD_SET_IN_OUT_MAP,
1115 &in_out, sizeof(in_out));
e2f0ba97 1116
ea5b213a 1117 if (intel_sdvo->is_hdmi) {
32aad86f
CW		 1118 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1119 return;
1120
e2f0ba97
JB		 1121 sdvox |= SDVO_AUDIO_ENABLE;
1122 }
1123
7026d4ac
ZW		 1124 /* We have tried to get input timing in mode_fixup, and filled into
1125 adjusted_mode */
c74696b9
PR		 1126 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1127 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
ea5b213a 1128 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
e2f0ba97
JB		 1129
1130 /* If it's a TV, we already set the output timing in mode_fixup.
1131 * Otherwise, the output timing is equal to the input timing.
1132 */
ea5b213a 1133 if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) {
e2f0ba97 1134 /* Set the output timing to the screen */
32aad86f
CW		 1135 if (!intel_sdvo_set_target_output(intel_sdvo,
1136 intel_sdvo->attached_output))
1137 return;
1138
c74696b9 1139 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1140 }
79e53945
JB		 1141
1142 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1143 if (!intel_sdvo_set_target_input(intel_sdvo))
1144 return;
79e53945 1145
32aad86f
CW		 1146 if (intel_sdvo->is_tv) {
1147 if (!intel_sdvo_set_tv_format(intel_sdvo))
1148 return;
1149 }
7026d4ac 1150
e2f0ba97 1151 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1152 * provide the device with a timing it can support, if it supports that
1153 * feature. However, presumably we would need to adjust the CRTC to
1154 * output the preferred timing, and we don't support that currently.
1155 */
e2f0ba97 1156#if 0
c751ce4f 1157 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
e2f0ba97
JB		 1158 width, height);
1159 if (success) {
1160 struct intel_sdvo_dtd *input_dtd;
1161
c751ce4f
EA		 1162 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1163 intel_sdvo_set_input_timing(encoder, &input_dtd);
e2f0ba97
JB		 1164 }
1165#else
c74696b9 1166 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
e2f0ba97 1167#endif
79e53945 1168
32aad86f
CW		 1169 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1170 switch (sdvo_pixel_multiply) {
1171 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1172 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1173 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1174 }
32aad86f
CW		 1175 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1176 return;
79e53945
JB		 1177
1178 /* Set the SDVO control regs. */
e2f0ba97 1179 if (IS_I965G(dev)) {
81a14b46
AJ		 1180 sdvox |= SDVO_BORDER_ENABLE;
1181 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1182 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1183 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1184 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1185 } else {
ea5b213a
CW		 1186 sdvox |= I915_READ(intel_sdvo->sdvo_reg);
1187 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1188 case SDVOB:
1189 sdvox &= SDVOB_PRESERVE_MASK;
1190 break;
1191 case SDVOC:
1192 sdvox &= SDVOC_PRESERVE_MASK;
1193 break;
1194 }
1195 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1196 }
79e53945
JB		 1197 if (intel_crtc->pipe == 1)
1198 sdvox |= SDVO_PIPE_B_SELECT;
1199
79e53945 1200 if (IS_I965G(dev)) {
e2f0ba97
JB		 1201 /* done in crtc_mode_set as the dpll_md reg must be written early */
1202 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1203 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1204 } else {
1205 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1206 }
1207
ea5b213a 1208 if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1209 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1210 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1211}
1212
1213static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1214{
1215 struct drm_device *dev = encoder->dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1217 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
9d0498a2 1218 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1219 u32 temp;
1220
1221 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1222 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1223 if (0)
ea5b213a 1224 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1225
1226 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1227 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1228 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1229 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1230 }
1231 }
1232 } else {
1233 bool input1, input2;
1234 int i;
1235 u8 status;
1236
ea5b213a 1237 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1238 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1239 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1240 for (i = 0; i < 2; i++)
9d0498a2 1241 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1242
32aad86f 1243 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1244 /* Warn if the device reported failure to sync.
1245 * A lot of SDVO devices fail to notify of sync, but it's
1246 * a given it the status is a success, we succeeded.
1247 */
1248 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1249 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1250 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1251 }
1252
1253 if (0)
ea5b213a
CW		 1254 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1255 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1256 }
1257 return;
1258}
1259
79e53945
JB		 1260static int intel_sdvo_mode_valid(struct drm_connector *connector,
1261 struct drm_display_mode *mode)
1262{
d2a82a6f 1263 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1264 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
79e53945
JB		 1265
1266 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1267 return MODE_NO_DBLESCAN;
1268
ea5b213a 1269 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1270 return MODE_CLOCK_LOW;
1271
ea5b213a 1272 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1273 return MODE_CLOCK_HIGH;
1274
8545423a 1275 if (intel_sdvo->is_lvds) {
ea5b213a 1276 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1277 return MODE_PANEL;
1278
ea5b213a 1279 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1280 return MODE_PANEL;
1281 }
1282
79e53945
JB		 1283 return MODE_OK;
1284}
1285
ea5b213a 1286static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1287{
32aad86f 1288 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
79e53945
JB		 1289}
1290
d2a82a6f
ZW		 1291/* No use! */
1292#if 0
79e53945
JB		 1293struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1294{
1295 struct drm_connector *connector = NULL;
ea5b213a
CW		 1296 struct intel_sdvo *iout = NULL;
1297 struct intel_sdvo *sdvo;
79e53945
JB		 1298
1299 /* find the sdvo connector */
1300 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1301 iout = to_intel_sdvo(connector);
79e53945
JB		 1302
1303 if (iout->type != INTEL_OUTPUT_SDVO)
1304 continue;
1305
1306 sdvo = iout->dev_priv;
1307
c751ce4f 1308 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1309 return connector;
1310
c751ce4f 1311 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1312 return connector;
1313
1314 }
1315
1316 return NULL;
1317}
1318
1319int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1320{
1321 u8 response[2];
1322 u8 status;
ea5b213a 1323 struct intel_sdvo *intel_sdvo;
8a4c47f3 1324 DRM_DEBUG_KMS("\n");
79e53945
JB		 1325
1326 if (!connector)
1327 return 0;
1328
ea5b213a 1329 intel_sdvo = to_intel_sdvo(connector);
79e53945 1330
32aad86f
CW		 1331 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1332 &response, 2) && response[0];
79e53945
JB		 1333}
1334
1335void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1336{
1337 u8 response[2];
1338 u8 status;
ea5b213a 1339 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1340
ea5b213a
CW		 1341 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1342 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1343
1344 if (on) {
ea5b213a
CW		 1345 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1346 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1347
ea5b213a 1348 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1349 } else {
1350 response[0] = 0;
1351 response[1] = 0;
ea5b213a 1352 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1353 }
1354
ea5b213a
CW		 1355 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1356 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1357}
d2a82a6f 1358#endif
79e53945 1359
fb7a46f3 1360static bool
ea5b213a 1361intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1362{
fb7a46f3 1363 int caps = 0;
1364
ea5b213a 1365 if (intel_sdvo->caps.output_flags &
fb7a46f3 1366 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1367 caps++;
ea5b213a 1368 if (intel_sdvo->caps.output_flags &
fb7a46f3 1369 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1370 caps++;
ea5b213a 1371 if (intel_sdvo->caps.output_flags &
19e1f888 1372 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1373 caps++;
ea5b213a 1374 if (intel_sdvo->caps.output_flags &
fb7a46f3 1375 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1376 caps++;
ea5b213a 1377 if (intel_sdvo->caps.output_flags &
fb7a46f3 1378 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1379 caps++;
1380
ea5b213a 1381 if (intel_sdvo->caps.output_flags &
fb7a46f3 1382 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1383 caps++;
1384
ea5b213a 1385 if (intel_sdvo->caps.output_flags &
fb7a46f3 1386 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1387 caps++;
1388
1389 return (caps > 1);
1390}
1391
57cdaf90
KP		 1392static struct drm_connector *
1393intel_find_analog_connector(struct drm_device *dev)
1394{
1395 struct drm_connector *connector;
d2a82a6f 1396 struct drm_encoder *encoder;
ea5b213a 1397 struct intel_sdvo *intel_sdvo;
57cdaf90 1398
d2a82a6f 1399 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 1400 intel_sdvo = enc_to_intel_sdvo(encoder);
1401 if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) {
d2a82a6f 1402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
90a78e8f 1403 if (encoder == intel_attached_encoder(connector))
d2a82a6f
ZW		 1404 return connector;
1405 }
1406 }
57cdaf90
KP		 1407 }
1408 return NULL;
1409}
1410
1411static int
1412intel_analog_is_connected(struct drm_device *dev)
1413{
1414 struct drm_connector *analog_connector;
57cdaf90 1415
32aad86f 1416 analog_connector = intel_find_analog_connector(dev);
57cdaf90
KP		 1417 if (!analog_connector)
1418 return false;
1419
930a9e28 1420 if (analog_connector->funcs->detect(analog_connector, false) ==
57cdaf90
KP		 1421 connector_status_disconnected)
1422 return false;
1423
1424 return true;
1425}
1426
2b8d33f7 1427enum drm_connector_status
149c36a3 1428intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1429{
d2a82a6f 1430 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1431 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1432 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2b8d33f7 1433 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1434 struct edid *edid = NULL;
1435
ea5b213a 1436 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
57cdaf90 1437
7c3f0a27 1438 /* This is only applied to SDVO cards with multiple outputs */
ea5b213a 1439 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
7c3f0a27 1440 uint8_t saved_ddc, temp_ddc;
ea5b213a
CW		 1441 saved_ddc = intel_sdvo->ddc_bus;
1442 temp_ddc = intel_sdvo->ddc_bus >> 1;
7c3f0a27
ZY		 1443 /*
1444 * Don't use the 1 as the argument of DDC bus switch to get
1445 * the EDID. It is used for SDVO SPD ROM.
1446 */
1447 while(temp_ddc > 1) {
ea5b213a
CW		 1448 intel_sdvo->ddc_bus = temp_ddc;
1449 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
7c3f0a27
ZY		 1450 if (edid) {
1451 /*
1452 * When we can get the EDID, maybe it is the
1453 * correct DDC bus. Update it.
1454 */
ea5b213a 1455 intel_sdvo->ddc_bus = temp_ddc;
7c3f0a27
ZY		 1456 break;
1457 }
1458 temp_ddc >>= 1;
1459 }
1460 if (edid == NULL)
ea5b213a 1461 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1462 }
57cdaf90
KP		 1463 /* when there is no edid and no monitor is connected with VGA
1464 * port, try to use the CRT ddc to read the EDID for DVI-connector
1465 */
ea5b213a 1466 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
d2a82a6f 1467 !intel_analog_is_connected(connector->dev))
ea5b213a 1468 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
149c36a3 1469
9dff6af8 1470 if (edid != NULL) {
149c36a3 1471 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
615fb93f 1472 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
2b8d33f7 1473
149c36a3
AJ		 1474 /* DDC bus is shared, match EDID to connector type */
1475 if (is_digital && need_digital)
ea5b213a 1476 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
149c36a3
AJ		 1477 else if (is_digital != need_digital)
1478 status = connector_status_disconnected;
2b8d33f7 1479
149c36a3
AJ		 1480 connector->display_info.raw_edid = NULL;
1481 } else
2b8d33f7 1482 status = connector_status_disconnected;
149c36a3
AJ		 1483
1484 kfree(edid);
2b8d33f7 1485
1486 return status;
9dff6af8
ML		 1487}
1488
7b334fcb 1489static enum drm_connector_status
930a9e28 1490intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1491{
fb7a46f3 1492 uint16_t response;
d2a82a6f 1493 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1494 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1495 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1496 enum drm_connector_status ret;
79e53945 1497
32aad86f
CW		 1498 if (!intel_sdvo_write_cmd(intel_sdvo,
1499 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1500 return connector_status_unknown;
ea5b213a 1501 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1502 /* add 30ms delay when the output type is SDVO-TV */
1503 mdelay(30);
1504 }
32aad86f
CW		 1505 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1506 return connector_status_unknown;
79e53945 1507
51c8b407 1508 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97 1509
fb7a46f3 1510 if (response == 0)
79e53945 1511 return connector_status_disconnected;
fb7a46f3 1512
ea5b213a 1513 intel_sdvo->attached_output = response;
14571b4c 1514
615fb93f 1515 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1516 ret = connector_status_disconnected;
149c36a3
AJ		 1517 else if (response & SDVO_TMDS_MASK)
1518 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1519 else
1520 ret = connector_status_connected;
1521
1522 /* May update encoder flag for like clock for SDVO TV, etc.*/
1523 if (ret == connector_status_connected) {
ea5b213a
CW		 1524 intel_sdvo->is_tv = false;
1525 intel_sdvo->is_lvds = false;
1526 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1527
1528 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1529 intel_sdvo->is_tv = true;
1530 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1531 }
1532 if (response & SDVO_LVDS_MASK)
8545423a 1533 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1534 }
14571b4c
ZW		 1535
1536 return ret;
79e53945
JB		 1537}
1538
e2f0ba97 1539static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1540{
d2a82a6f 1541 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1542 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
57cdaf90 1543 int num_modes;
79e53945
JB		 1544
1545 /* set the bus switch and get the modes */
ea5b213a 1546 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
79e53945 1547
57cdaf90
KP		 1548 /*
1549 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1550 * link between analog and digital outputs. So, if the regular SDVO
1551 * DDC fails, check to see if the analog output is disconnected, in
1552 * which case we'll look there for the digital DDC data.
e2f0ba97 1553 */
57cdaf90 1554 if (num_modes == 0 &&
ea5b213a 1555 intel_sdvo->analog_ddc_bus &&
d2a82a6f 1556 !intel_analog_is_connected(connector->dev)) {
57cdaf90
KP		 1557 /* Switch to the analog ddc bus and try that
1558 */
ea5b213a 1559 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
e2f0ba97 1560 }
e2f0ba97
JB		 1561}
1562
1563/*
1564 * Set of SDVO TV modes.
1565 * Note! This is in reply order (see loop in get_tv_modes).
1566 * XXX: all 60Hz refresh?
1567 */
1568struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1569 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1570 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1572 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1573 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1575 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1576 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1578 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1579 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1581 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1582 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1584 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1585 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1587 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1588 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1590 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1591 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1593 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1594 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1596 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1597 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1599 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1600 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1602 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1603 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1605 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1606 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1608 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1609 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1611 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1612 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1613 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1614 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1615 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1617 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1618 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1621 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1623 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1624 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1625 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1626};
1627
1628static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1629{
d2a82a6f 1630 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1631 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
7026d4ac 1632 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1633 uint32_t reply = 0, format_map = 0;
1634 int i;
e2f0ba97
JB		 1635
1636 /* Read the list of supported input resolutions for the selected TV
1637 * format.
1638 */
40039750 1639 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1640 memcpy(&tv_res, &format_map,
32aad86f 1641 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1642
32aad86f
CW		 1643 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1644 return;
ce6feabd 1645
32aad86f
CW		 1646 BUILD_BUG_ON(sizeof(tv_res) != 3);
1647 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1648 &tv_res, sizeof(tv_res)))
1649 return;
1650 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1651 return;
1652
1653 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1654 if (reply & (1 << i)) {
1655 struct drm_display_mode *nmode;
1656 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1657 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1658 if (nmode)
1659 drm_mode_probed_add(connector, nmode);
1660 }
e2f0ba97
JB		 1661}
1662
7086c87f
ML		 1663static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1664{
d2a82a6f 1665 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1666 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
7086c87f 1667 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1668 struct drm_display_mode *newmode;
7086c87f
ML		 1669
1670 /*
1671 * Attempt to get the mode list from DDC.
1672 * Assume that the preferred modes are
1673 * arranged in priority order.
1674 */
ea5b213a 1675 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
7086c87f 1676 if (list_empty(&connector->probed_modes) == false)
12682a97 1677 goto end;
7086c87f
ML		 1678
1679 /* Fetch modes from VBT */
1680 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1681 newmode = drm_mode_duplicate(connector->dev,
1682 dev_priv->sdvo_lvds_vbt_mode);
1683 if (newmode != NULL) {
1684 /* Guarantee the mode is preferred */
1685 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1686 DRM_MODE_TYPE_DRIVER);
1687 drm_mode_probed_add(connector, newmode);
1688 }
1689 }
12682a97 1690
1691end:
1692 list_for_each_entry(newmode, &connector->probed_modes, head) {
1693 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1694 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1695 drm_mode_duplicate(connector->dev, newmode);
8545423a 1696 intel_sdvo->is_lvds = true;
12682a97 1697 break;
1698 }
1699 }
1700
7086c87f
ML		 1701}
1702
e2f0ba97
JB		 1703static int intel_sdvo_get_modes(struct drm_connector *connector)
1704{
615fb93f 1705 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1706
615fb93f 1707 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1708 intel_sdvo_get_tv_modes(connector);
615fb93f 1709 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1710 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1711 else
1712 intel_sdvo_get_ddc_modes(connector);
1713
32aad86f 1714 return !list_empty(&connector->probed_modes);
79e53945
JB		 1715}
1716
fcc8d672
CW		 1717static void
1718intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1719{
615fb93f 1720 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1721 struct drm_device *dev = connector->dev;
1722
c5521706
CW		 1723 if (intel_sdvo_connector->left)
1724 drm_property_destroy(dev, intel_sdvo_connector->left);
1725 if (intel_sdvo_connector->right)
1726 drm_property_destroy(dev, intel_sdvo_connector->right);
1727 if (intel_sdvo_connector->top)
1728 drm_property_destroy(dev, intel_sdvo_connector->top);
1729 if (intel_sdvo_connector->bottom)
1730 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1731 if (intel_sdvo_connector->hpos)
1732 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1733 if (intel_sdvo_connector->vpos)
1734 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1735 if (intel_sdvo_connector->saturation)
1736 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1737 if (intel_sdvo_connector->contrast)
1738 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1739 if (intel_sdvo_connector->hue)
1740 drm_property_destroy(dev, intel_sdvo_connector->hue);
1741 if (intel_sdvo_connector->sharpness)
1742 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1743 if (intel_sdvo_connector->flicker_filter)
1744 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1745 if (intel_sdvo_connector->flicker_filter_2d)
1746 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1747 if (intel_sdvo_connector->flicker_filter_adaptive)
1748 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1749 if (intel_sdvo_connector->tv_luma_filter)
1750 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1751 if (intel_sdvo_connector->tv_chroma_filter)
1752 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1753 if (intel_sdvo_connector->dot_crawl)
1754 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1755 if (intel_sdvo_connector->brightness)
1756 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1757}
1758
79e53945
JB		 1759static void intel_sdvo_destroy(struct drm_connector *connector)
1760{
615fb93f 1761 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1762
c5521706 1763 if (intel_sdvo_connector->tv_format)
ce6feabd 1764 drm_property_destroy(connector->dev,
c5521706 1765 intel_sdvo_connector->tv_format);
b9219c5e 1766
d2a82a6f 1767 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1768 drm_sysfs_connector_remove(connector);
1769 drm_connector_cleanup(connector);
d2a82a6f 1770 kfree(connector);
79e53945
JB		 1771}
1772
ce6feabd
ZY		 1773static int
1774intel_sdvo_set_property(struct drm_connector *connector,
1775 struct drm_property *property,
1776 uint64_t val)
1777{
d2a82a6f 1778 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1779 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
615fb93f 1780 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e 1781 uint16_t temp_value;
32aad86f
CW		 1782 uint8_t cmd;
1783 int ret;
ce6feabd
ZY		 1784
1785 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1786 if (ret)
1787 return ret;
ce6feabd 1788
c5521706
CW		 1789#define CHECK_PROPERTY(name, NAME) \
1790 if (intel_sdvo_connector->name == property) { \
1791 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1792 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1793 cmd = SDVO_CMD_SET_##NAME; \
1794 intel_sdvo_connector->cur_##name = temp_value; \
1795 goto set_value; \
1796 }
1797
1798 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1799 if (val >= TV_FORMAT_NUM)
1800 return -EINVAL;
1801
40039750 1802 if (intel_sdvo->tv_format_index ==
615fb93f 1803 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1804 return 0;
ce6feabd 1805
40039750 1806 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1807 goto done;
32aad86f 1808 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1809 temp_value = val;
c5521706 1810 if (intel_sdvo_connector->left == property) {
b9219c5e 1811 drm_connector_property_set_value(connector,
c5521706 1812 intel_sdvo_connector->right, val);
615fb93f 1813 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1814 return 0;
b9219c5e 1815
615fb93f
CW		 1816 intel_sdvo_connector->left_margin = temp_value;
1817 intel_sdvo_connector->right_margin = temp_value;
1818 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1819 intel_sdvo_connector->left_margin;
b9219c5e 1820 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1821 goto set_value;
1822 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1823 drm_connector_property_set_value(connector,
c5521706 1824 intel_sdvo_connector->left, val);
615fb93f 1825 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1826 return 0;
b9219c5e 1827
615fb93f
CW		 1828 intel_sdvo_connector->left_margin = temp_value;
1829 intel_sdvo_connector->right_margin = temp_value;
1830 temp_value = intel_sdvo_connector->max_hscan -
1831 intel_sdvo_connector->left_margin;
b9219c5e 1832 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1833 goto set_value;
1834 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1835 drm_connector_property_set_value(connector,
c5521706 1836 intel_sdvo_connector->bottom, val);
615fb93f 1837 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1838 return 0;
b9219c5e 1839
615fb93f
CW		 1840 intel_sdvo_connector->top_margin = temp_value;
1841 intel_sdvo_connector->bottom_margin = temp_value;
1842 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1843 intel_sdvo_connector->top_margin;
b9219c5e 1844 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1845 goto set_value;
1846 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1847 drm_connector_property_set_value(connector,
c5521706 1848 intel_sdvo_connector->top, val);
615fb93f 1849 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1850 return 0;
1851
615fb93f
CW		 1852 intel_sdvo_connector->top_margin = temp_value;
1853 intel_sdvo_connector->bottom_margin = temp_value;
1854 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1855 intel_sdvo_connector->top_margin;
b9219c5e 1856 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1857 goto set_value;
1858 }
1859 CHECK_PROPERTY(hpos, HPOS)
1860 CHECK_PROPERTY(vpos, VPOS)
1861 CHECK_PROPERTY(saturation, SATURATION)
1862 CHECK_PROPERTY(contrast, CONTRAST)
1863 CHECK_PROPERTY(hue, HUE)
1864 CHECK_PROPERTY(brightness, BRIGHTNESS)
1865 CHECK_PROPERTY(sharpness, SHARPNESS)
1866 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1867 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1868 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1869 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1870 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1871 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1872 }
b9219c5e 1873
c5521706 1874 return -EINVAL; /* unknown property */
b9219c5e 1875
c5521706
CW		 1876set_value:
1877 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1878 return -EIO;
b9219c5e 1879
b9219c5e 1880
c5521706
CW		 1881done:
1882 if (encoder->crtc) {
1883 struct drm_crtc *crtc = encoder->crtc;
32aad86f 1884
ce6feabd 1885 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1886 crtc->y, crtc->fb);
1887 }
1888
32aad86f 1889 return 0;
c5521706 1890#undef CHECK_PROPERTY
ce6feabd
ZY		 1891}
1892
79e53945
JB		 1893static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1894 .dpms = intel_sdvo_dpms,
1895 .mode_fixup = intel_sdvo_mode_fixup,
1896 .prepare = intel_encoder_prepare,
1897 .mode_set = intel_sdvo_mode_set,
1898 .commit = intel_encoder_commit,
1899};
1900
1901static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1902 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1903 .detect = intel_sdvo_detect,
1904 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1905 .set_property = intel_sdvo_set_property,
79e53945
JB		 1906 .destroy = intel_sdvo_destroy,
1907};
1908
1909static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1910 .get_modes = intel_sdvo_get_modes,
1911 .mode_valid = intel_sdvo_mode_valid,
d2a82a6f 1912 .best_encoder = intel_attached_encoder,
79e53945
JB		 1913};
1914
b358d0a6 1915static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1916{
ea5b213a 1917 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
d2a82a6f 1918
ea5b213a
CW		 1919 if (intel_sdvo->analog_ddc_bus)
1920 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
d2a82a6f 1921
ea5b213a 1922 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1923 drm_mode_destroy(encoder->dev,
ea5b213a 1924 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1925
ea5b213a 1926 intel_encoder_destroy(encoder);
79e53945
JB		 1927}
1928
1929static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1930 .destroy = intel_sdvo_enc_destroy,
1931};
1932
b66d8424
CW		 1933static void
1934intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1935{
1936 uint16_t mask = 0;
1937 unsigned int num_bits;
1938
1939 /* Make a mask of outputs less than or equal to our own priority in the
1940 * list.
1941 */
1942 switch (sdvo->controlled_output) {
1943 case SDVO_OUTPUT_LVDS1:
1944 mask |= SDVO_OUTPUT_LVDS1;
1945 case SDVO_OUTPUT_LVDS0:
1946 mask |= SDVO_OUTPUT_LVDS0;
1947 case SDVO_OUTPUT_TMDS1:
1948 mask |= SDVO_OUTPUT_TMDS1;
1949 case SDVO_OUTPUT_TMDS0:
1950 mask |= SDVO_OUTPUT_TMDS0;
1951 case SDVO_OUTPUT_RGB1:
1952 mask |= SDVO_OUTPUT_RGB1;
1953 case SDVO_OUTPUT_RGB0:
1954 mask |= SDVO_OUTPUT_RGB0;
1955 break;
1956 }
1957
1958 /* Count bits to find what number we are in the priority list. */
1959 mask &= sdvo->caps.output_flags;
1960 num_bits = hweight16(mask);
1961 /* If more than 3 outputs, default to DDC bus 3 for now. */
1962 if (num_bits > 3)
1963 num_bits = 3;
1964
1965 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1966 sdvo->ddc_bus = 1 << num_bits;
1967}
79e53945 1968
e2f0ba97
JB		 1969/**
1970 * Choose the appropriate DDC bus for control bus switch command for this
1971 * SDVO output based on the controlled output.
1972 *
1973 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1974 * outputs, then LVDS outputs.
1975 */
1976static void
b1083333 1977intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1978 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1979{
b1083333 1980 struct sdvo_device_mapping *mapping;
e2f0ba97 1981
b1083333
AJ		 1982 if (IS_SDVOB(reg))
1983 mapping = &(dev_priv->sdvo_mappings[0]);
1984 else
1985 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1986
b66d8424
CW		 1987 if (mapping->initialized)
1988 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1989 else
1990 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1991}
1992
1993static bool
ea5b213a 1994intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1995{
32aad86f
CW		 1996 return intel_sdvo_set_target_output(intel_sdvo,
1997 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1998 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1999 &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 2000}
2001
ea5b213a
CW		 2002static struct intel_sdvo *
2003intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
619ac3b7
ML		 2004{
2005 struct drm_device *dev = chan->drm_dev;
d2a82a6f 2006 struct drm_encoder *encoder;
619ac3b7 2007
d2a82a6f 2008 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 2009 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
2010 if (intel_sdvo->base.ddc_bus == &chan->adapter)
2011 return intel_sdvo;
619ac3b7 2012 }
ea5b213a 2013
32aad86f 2014 return NULL;
619ac3b7
ML		 2015}
2016
2017static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2018 struct i2c_msg msgs[], int num)
2019{
ea5b213a 2020 struct intel_sdvo *intel_sdvo;
619ac3b7 2021 struct i2c_algo_bit_data *algo_data;
f9c10a9b 2022 const struct i2c_algorithm *algo;
619ac3b7
ML		 2023
2024 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
ea5b213a
CW		 2025 intel_sdvo =
2026 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
2027 (algo_data->data));
2028 if (intel_sdvo == NULL)
619ac3b7
ML		 2029 return -EINVAL;
2030
ea5b213a 2031 algo = intel_sdvo->base.i2c_bus->algo;
619ac3b7 2032
ea5b213a 2033 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
619ac3b7
ML		 2034 return algo->master_xfer(i2c_adap, msgs, num);
2035}
2036
2037static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2038 .master_xfer = intel_sdvo_master_xfer,
2039};
2040
714605e4 2041static u8
c751ce4f 2042intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2043{
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 struct sdvo_device_mapping *my_mapping, *other_mapping;
2046
461ed3ca 2047 if (IS_SDVOB(sdvo_reg)) {
714605e4 2048 my_mapping = &dev_priv->sdvo_mappings[0];
2049 other_mapping = &dev_priv->sdvo_mappings[1];
2050 } else {
2051 my_mapping = &dev_priv->sdvo_mappings[1];
2052 other_mapping = &dev_priv->sdvo_mappings[0];
2053 }
2054
2055 /* If the BIOS described our SDVO device, take advantage of it. */
2056 if (my_mapping->slave_addr)
2057 return my_mapping->slave_addr;
2058
2059 /* If the BIOS only described a different SDVO device, use the
2060 * address that it isn't using.
2061 */
2062 if (other_mapping->slave_addr) {
2063 if (other_mapping->slave_addr == 0x70)
2064 return 0x72;
2065 else
2066 return 0x70;
2067 }
2068
2069 /* No SDVO device info is found for another DVO port,
2070 * so use mapping assumption we had before BIOS parsing.
2071 */
461ed3ca 2072 if (IS_SDVOB(sdvo_reg))
714605e4 2073 return 0x70;
2074 else
2075 return 0x72;
2076}
2077
14571b4c 2078static void
32aad86f
CW		 2079intel_sdvo_connector_init(struct drm_encoder *encoder,
2080 struct drm_connector *connector)
14571b4c
ZW		 2081{
2082 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2083 connector->connector_type);
6070a4a9 2084
14571b4c
ZW		 2085 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2086
2087 connector->interlace_allowed = 0;
2088 connector->doublescan_allowed = 0;
2089 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2090
2091 drm_mode_connector_attach_encoder(connector, encoder);
2092 drm_sysfs_connector_add(connector);
2093}
6070a4a9 2094
fb7a46f3 2095static bool
ea5b213a 2096intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2097{
ea5b213a 2098 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2099 struct drm_connector *connector;
2100 struct intel_connector *intel_connector;
615fb93f 2101 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2102
615fb93f
CW		 2103 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2104 if (!intel_sdvo_connector)
14571b4c
ZW		 2105 return false;
2106
14571b4c 2107 if (device == 0) {
ea5b213a 2108 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2109 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2110 } else if (device == 1) {
ea5b213a 2111 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2112 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2113 }
2114
615fb93f 2115 intel_connector = &intel_sdvo_connector->base;
14571b4c 2116 connector = &intel_connector->base;
eb1f8e4f 2117 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2118 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2119 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2120
ea5b213a
CW		 2121 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2122 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2123 && intel_sdvo->is_hdmi) {
14571b4c 2124 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2125 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2126 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2127 SDVO_COLORIMETRY_RGB256);
2128 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2129 }
ea5b213a
CW		 2130 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2131 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2132
32aad86f 2133 intel_sdvo_connector_init(encoder, connector);
14571b4c
ZW		 2134
2135 return true;
2136}
2137
2138static bool
ea5b213a 2139intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2140{
ea5b213a 2141 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2142 struct drm_connector *connector;
2143 struct intel_connector *intel_connector;
615fb93f 2144 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2145
615fb93f
CW		 2146 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2147 if (!intel_sdvo_connector)
2148 return false;
14571b4c 2149
615fb93f 2150 intel_connector = &intel_sdvo_connector->base;
14571b4c
ZW		 2151 connector = &intel_connector->base;
2152 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2153 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2154
ea5b213a 2155 intel_sdvo->controlled_output |= type;
615fb93f 2156 intel_sdvo_connector->output_flag = type;
14571b4c 2157
ea5b213a
CW		 2158 intel_sdvo->is_tv = true;
2159 intel_sdvo->base.needs_tv_clock = true;
2160 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2161
32aad86f 2162 intel_sdvo_connector_init(encoder, connector);
14571b4c 2163
32aad86f
CW		 2164 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2165 goto err;
14571b4c 2166
32aad86f
CW		 2167 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2168 goto err;
14571b4c
ZW		 2169
2170 return true;
32aad86f
CW		 2171
2172err:
123d5c01 2173 intel_sdvo_destroy(connector);
32aad86f 2174 return false;
14571b4c
ZW		 2175}
2176
2177static bool
ea5b213a 2178intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2179{
ea5b213a 2180 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2181 struct drm_connector *connector;
2182 struct intel_connector *intel_connector;
615fb93f 2183 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2184
615fb93f
CW		 2185 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2186 if (!intel_sdvo_connector)
2187 return false;
14571b4c 2188
615fb93f 2189 intel_connector = &intel_sdvo_connector->base;
14571b4c 2190 connector = &intel_connector->base;
eb1f8e4f 2191 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
14571b4c
ZW		 2192 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2193 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
14571b4c
ZW		 2194
2195 if (device == 0) {
ea5b213a 2196 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
615fb93f 2197 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
14571b4c 2198 } else if (device == 1) {
ea5b213a 2199 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
615fb93f 2200 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
14571b4c
ZW		 2201 }
2202
ea5b213a
CW		 2203 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2204 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2205
32aad86f 2206 intel_sdvo_connector_init(encoder, connector);
14571b4c
ZW		 2207 return true;
2208}
2209
2210static bool
ea5b213a 2211intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2212{
ea5b213a 2213 struct drm_encoder *encoder = &intel_sdvo->base.enc;
14571b4c
ZW		 2214 struct drm_connector *connector;
2215 struct intel_connector *intel_connector;
615fb93f 2216 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2217
615fb93f
CW		 2218 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2219 if (!intel_sdvo_connector)
2220 return false;
14571b4c 2221
615fb93f
CW		 2222 intel_connector = &intel_sdvo_connector->base;
2223 connector = &intel_connector->base;
14571b4c
ZW		 2224 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2225 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
14571b4c 2226
14571b4c 2227 if (device == 0) {
ea5b213a 2228 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
615fb93f 2229 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
14571b4c 2230 } else if (device == 1) {
ea5b213a 2231 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
615fb93f 2232 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
14571b4c
ZW		 2233 }
2234
ea5b213a
CW		 2235 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2236 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2237
32aad86f
CW		 2238 intel_sdvo_connector_init(encoder, connector);
2239 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2240 goto err;
2241
2242 return true;
2243
2244err:
123d5c01 2245 intel_sdvo_destroy(connector);
32aad86f 2246 return false;
14571b4c
ZW		 2247}
2248
2249static bool
ea5b213a 2250intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2251{
ea5b213a
CW		 2252 intel_sdvo->is_tv = false;
2253 intel_sdvo->base.needs_tv_clock = false;
2254 intel_sdvo->is_lvds = false;
fb7a46f3 2255
14571b4c 2256 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2257
14571b4c 2258 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2259 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2260 return false;
2261
2262 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2263 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2264 return false;
2265
2266 /* TV has no XXX1 function block */
a1f4b7ff 2267 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2268 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2269 return false;
2270
2271 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2272 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2273 return false;
fb7a46f3 2274
14571b4c 2275 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2276 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2277 return false;
2278
2279 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2280 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2281 return false;
2282
2283 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2284 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2285 return false;
2286
2287 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2288 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2289 return false;
fb7a46f3 2290
14571b4c 2291 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2292 unsigned char bytes[2];
2293
ea5b213a
CW		 2294 intel_sdvo->controlled_output = 0;
2295 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2296 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2297 SDVO_NAME(intel_sdvo),
51c8b407 2298 bytes[0], bytes[1]);
14571b4c 2299 return false;
fb7a46f3 2300 }
ea5b213a 2301 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2302
14571b4c 2303 return true;
fb7a46f3 2304}
2305
32aad86f
CW		 2306static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2307 struct intel_sdvo_connector *intel_sdvo_connector,
2308 int type)
ce6feabd 2309{
32aad86f 2310 struct drm_device *dev = intel_sdvo->base.enc.dev;
ce6feabd
ZY		 2311 struct intel_sdvo_tv_format format;
2312 uint32_t format_map, i;
ce6feabd 2313
32aad86f
CW		 2314 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2315 return false;
ce6feabd 2316
32aad86f
CW		 2317 if (!intel_sdvo_get_value(intel_sdvo,
2318 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2319 &format, sizeof(format)))
2320 return false;
ce6feabd 2321
32aad86f 2322 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2323
2324 if (format_map == 0)
32aad86f 2325 return false;
ce6feabd 2326
615fb93f 2327 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2328 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2329 if (format_map & (1 << i))
2330 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2331
2332
c5521706 2333 intel_sdvo_connector->tv_format =
32aad86f
CW		 2334 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2335 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2336 if (!intel_sdvo_connector->tv_format)
fcc8d672 2337 return false;
ce6feabd 2338
615fb93f 2339 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2340 drm_property_add_enum(
c5521706 2341 intel_sdvo_connector->tv_format, i,
40039750 2342 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2343
40039750 2344 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2345 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2346 intel_sdvo_connector->tv_format, 0);
32aad86f 2347 return true;
ce6feabd
ZY		 2348
2349}
2350
c5521706
CW		 2351#define ENHANCEMENT(name, NAME) do { \
2352 if (enhancements.name) { \
2353 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2354 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2355 return false; \
2356 intel_sdvo_connector->max_##name = data_value[0]; \
2357 intel_sdvo_connector->cur_##name = response; \
2358 intel_sdvo_connector->name = \
2359 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2360 if (!intel_sdvo_connector->name) return false; \
2361 intel_sdvo_connector->name->values[0] = 0; \
2362 intel_sdvo_connector->name->values[1] = data_value[0]; \
2363 drm_connector_attach_property(connector, \
2364 intel_sdvo_connector->name, \
2365 intel_sdvo_connector->cur_##name); \
2366 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2367 data_value[0], data_value[1], response); \
2368 } \
2369} while(0)
2370
2371static bool
2372intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2373 struct intel_sdvo_connector *intel_sdvo_connector,
2374 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2375{
32aad86f
CW		 2376 struct drm_device *dev = intel_sdvo->base.enc.dev;
2377 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2378 uint16_t response, data_value[2];
2379
c5521706
CW		 2380 /* when horizontal overscan is supported, Add the left/right property */
2381 if (enhancements.overscan_h) {
2382 if (!intel_sdvo_get_value(intel_sdvo,
2383 SDVO_CMD_GET_MAX_OVERSCAN_H,
2384 &data_value, 4))
2385 return false;
32aad86f 2386
c5521706
CW		 2387 if (!intel_sdvo_get_value(intel_sdvo,
2388 SDVO_CMD_GET_OVERSCAN_H,
2389 &response, 2))
2390 return false;
fcc8d672 2391
c5521706
CW		 2392 intel_sdvo_connector->max_hscan = data_value[0];
2393 intel_sdvo_connector->left_margin = data_value[0] - response;
2394 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2395 intel_sdvo_connector->left =
2396 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2397 "left_margin", 2);
2398 if (!intel_sdvo_connector->left)
2399 return false;
fcc8d672 2400
c5521706
CW		 2401 intel_sdvo_connector->left->values[0] = 0;
2402 intel_sdvo_connector->left->values[1] = data_value[0];
2403 drm_connector_attach_property(connector,
2404 intel_sdvo_connector->left,
2405 intel_sdvo_connector->left_margin);
fcc8d672 2406
c5521706
CW		 2407 intel_sdvo_connector->right =
2408 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2409 "right_margin", 2);
2410 if (!intel_sdvo_connector->right)
2411 return false;
32aad86f 2412
c5521706
CW		 2413 intel_sdvo_connector->right->values[0] = 0;
2414 intel_sdvo_connector->right->values[1] = data_value[0];
2415 drm_connector_attach_property(connector,
2416 intel_sdvo_connector->right,
2417 intel_sdvo_connector->right_margin);
2418 DRM_DEBUG_KMS("h_overscan: max %d, "
2419 "default %d, current %d\n",
2420 data_value[0], data_value[1], response);
2421 }
32aad86f 2422
c5521706
CW		 2423 if (enhancements.overscan_v) {
2424 if (!intel_sdvo_get_value(intel_sdvo,
2425 SDVO_CMD_GET_MAX_OVERSCAN_V,
2426 &data_value, 4))
2427 return false;
fcc8d672 2428
c5521706
CW		 2429 if (!intel_sdvo_get_value(intel_sdvo,
2430 SDVO_CMD_GET_OVERSCAN_V,
2431 &response, 2))
2432 return false;
32aad86f 2433
c5521706
CW		 2434 intel_sdvo_connector->max_vscan = data_value[0];
2435 intel_sdvo_connector->top_margin = data_value[0] - response;
2436 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2437 intel_sdvo_connector->top =
2438 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2439 "top_margin", 2);
2440 if (!intel_sdvo_connector->top)
2441 return false;
32aad86f 2442
c5521706
CW		 2443 intel_sdvo_connector->top->values[0] = 0;
2444 intel_sdvo_connector->top->values[1] = data_value[0];
2445 drm_connector_attach_property(connector,
2446 intel_sdvo_connector->top,
2447 intel_sdvo_connector->top_margin);
fcc8d672 2448
c5521706
CW		 2449 intel_sdvo_connector->bottom =
2450 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2451 "bottom_margin", 2);
2452 if (!intel_sdvo_connector->bottom)
2453 return false;
32aad86f 2454
c5521706
CW		 2455 intel_sdvo_connector->bottom->values[0] = 0;
2456 intel_sdvo_connector->bottom->values[1] = data_value[0];
2457 drm_connector_attach_property(connector,
2458 intel_sdvo_connector->bottom,
2459 intel_sdvo_connector->bottom_margin);
2460 DRM_DEBUG_KMS("v_overscan: max %d, "
2461 "default %d, current %d\n",
2462 data_value[0], data_value[1], response);
2463 }
32aad86f 2464
c5521706
CW		 2465 ENHANCEMENT(hpos, HPOS);
2466 ENHANCEMENT(vpos, VPOS);
2467 ENHANCEMENT(saturation, SATURATION);
2468 ENHANCEMENT(contrast, CONTRAST);
2469 ENHANCEMENT(hue, HUE);
2470 ENHANCEMENT(sharpness, SHARPNESS);
2471 ENHANCEMENT(brightness, BRIGHTNESS);
2472 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2473 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2474 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2475 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2476 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2477
e044218a
CW		 2478 if (enhancements.dot_crawl) {
2479 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2480 return false;
2481
2482 intel_sdvo_connector->max_dot_crawl = 1;
2483 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2484 intel_sdvo_connector->dot_crawl =
2485 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2486 if (!intel_sdvo_connector->dot_crawl)
2487 return false;
2488
2489 intel_sdvo_connector->dot_crawl->values[0] = 0;
2490 intel_sdvo_connector->dot_crawl->values[1] = 1;
2491 drm_connector_attach_property(connector,
2492 intel_sdvo_connector->dot_crawl,
2493 intel_sdvo_connector->cur_dot_crawl);
2494 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2495 }
2496
c5521706
CW		 2497 return true;
2498}
32aad86f 2499
c5521706
CW		 2500static bool
2501intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2502 struct intel_sdvo_connector *intel_sdvo_connector,
2503 struct intel_sdvo_enhancements_reply enhancements)
2504{
2505 struct drm_device *dev = intel_sdvo->base.enc.dev;
2506 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2507 uint16_t response, data_value[2];
32aad86f 2508
c5521706 2509 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2510
c5521706
CW		 2511 return true;
2512}
2513#undef ENHANCEMENT
32aad86f 2514
c5521706
CW		 2515static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2516 struct intel_sdvo_connector *intel_sdvo_connector)
2517{
2518 union {
2519 struct intel_sdvo_enhancements_reply reply;
2520 uint16_t response;
2521 } enhancements;
32aad86f 2522
cf9a2f3a
CW		 2523 enhancements.response = 0;
2524 intel_sdvo_get_value(intel_sdvo,
2525 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2526 &enhancements, sizeof(enhancements));
c5521706
CW		 2527 if (enhancements.response == 0) {
2528 DRM_DEBUG_KMS("No enhancement is supported\n");
2529 return true;
b9219c5e 2530 }
32aad86f 2531
c5521706
CW		 2532 if (IS_TV(intel_sdvo_connector))
2533 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2534 else if(IS_LVDS(intel_sdvo_connector))
2535 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2536 else
2537 return true;
fcc8d672 2538
b9219c5e
ZY		 2539}
2540
c751ce4f 2541bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2542{
b01f2c3a 2543 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2544 struct intel_encoder *intel_encoder;
ea5b213a 2545 struct intel_sdvo *intel_sdvo;
79e53945
JB		 2546 u8 ch[0x40];
2547 int i;
461ed3ca 2548 u32 i2c_reg, ddc_reg, analog_ddc_reg;
79e53945 2549
ea5b213a
CW		 2550 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2551 if (!intel_sdvo)
7d57382e 2552 return false;
79e53945 2553
ea5b213a 2554 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2555
ea5b213a 2556 intel_encoder = &intel_sdvo->base;
21d40d37 2557 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2558
461ed3ca
ZY		 2559 if (HAS_PCH_SPLIT(dev)) {
2560 i2c_reg = PCH_GPIOE;
2561 ddc_reg = PCH_GPIOE;
2562 analog_ddc_reg = PCH_GPIOA;
2563 } else {
2564 i2c_reg = GPIOE;
2565 ddc_reg = GPIOE;
2566 analog_ddc_reg = GPIOA;
2567 }
2568
79e53945 2569 /* setup the DDC bus. */
461ed3ca
ZY		 2570 if (IS_SDVOB(sdvo_reg))
2571 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2572 else
461ed3ca 2573 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2574
21d40d37 2575 if (!intel_encoder->i2c_bus)
ad5b2a6d 2576 goto err_inteloutput;
79e53945 2577
ea5b213a 2578 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2579
308cd3a2 2580 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2581 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2582
79e53945
JB		 2583 /* Read the regs to test if we can talk to the device */
2584 for (i = 0; i < 0x40; i++) {
ea5b213a 2585 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
8a4c47f3 2586 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2587 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2588 goto err_i2c;
2589 }
2590 }
2591
619ac3b7 2592 /* setup the DDC bus. */
461ed3ca
ZY		 2593 if (IS_SDVOB(sdvo_reg)) {
2594 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
ea5b213a 2595 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2596 "SDVOB/VGA DDC BUS");
b01f2c3a 2597 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2598 } else {
461ed3ca 2599 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
ea5b213a 2600 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2601 "SDVOC/VGA DDC BUS");
b01f2c3a 2602 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2603 }
32aad86f 2604 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
619ac3b7
ML		 2605 goto err_i2c;
2606
308cd3a2 2607 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2608 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2609
14571b4c
ZW		 2610 /* encoder type will be decided later */
2611 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
2612 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2613
af901ca1 2614 /* In default case sdvo lvds is false */
32aad86f
CW		 2615 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2616 goto err_enc;
79e53945 2617
ea5b213a
CW		 2618 if (intel_sdvo_output_setup(intel_sdvo,
2619 intel_sdvo->caps.output_flags) != true) {
51c8b407 2620 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2621 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
32aad86f 2622 goto err_enc;
79e53945
JB		 2623 }
2624
ea5b213a 2625 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2626
79e53945 2627 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 2628 if (!intel_sdvo_set_target_input(intel_sdvo))
2629 goto err_enc;
79e53945 2630
32aad86f
CW		 2631 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2632 &intel_sdvo->pixel_clock_min,
2633 &intel_sdvo->pixel_clock_max))
2634 goto err_enc;
79e53945 2635
8a4c47f3 2636 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2637 "clock range %dMHz - %dMHz, "
2638 "input 1: %c, input 2: %c, "
2639 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2640 SDVO_NAME(intel_sdvo),
2641 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2642 intel_sdvo->caps.device_rev_id,
2643 intel_sdvo->pixel_clock_min / 1000,
2644 intel_sdvo->pixel_clock_max / 1000,
2645 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2646 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2647 /* check currently supported outputs */
ea5b213a 2648 intel_sdvo->caps.output_flags &
79e53945 2649 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2650 intel_sdvo->caps.output_flags &
79e53945 2651 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2652 return true;
79e53945 2653
32aad86f
CW		 2654err_enc:
2655 drm_encoder_cleanup(&intel_encoder->enc);
79e53945 2656err_i2c:
ea5b213a
CW		 2657 if (intel_sdvo->analog_ddc_bus != NULL)
2658 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
21d40d37
EA		 2659 if (intel_encoder->ddc_bus != NULL)
2660 intel_i2c_destroy(intel_encoder->ddc_bus);
2661 if (intel_encoder->i2c_bus != NULL)
2662 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2663err_inteloutput:
ea5b213a 2664 kfree(intel_sdvo);
79e53945 2665
7d57382e 2666 return false;
79e53945 2667}
Clone of davem's net-next-2.6 tree