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drm/i915: Fix product names and #defines
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include "drmP.h"
30#include "drm.h"
31#include "drm_crtc.h"
32#include "drm_crtc_helper.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
36#include "intel_dp.h"
37
ae266c98 38
a4fc5ed6
KP		 39#define DP_LINK_STATUS_SIZE 6
40#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
41
42#define DP_LINK_CONFIGURATION_SIZE 9
43
32f9d658
ZW		 44#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
45
a4fc5ed6
KP		 46struct intel_dp_priv {
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 uint32_t save_DP;
51 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
52 bool has_audio;
c8110e52 53 int dpms_mode;
a4fc5ed6
KP		 54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[4];
57 struct intel_output *intel_output;
58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
60};
61
62static void
63intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
64 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
65
66static void
67intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
68
32f9d658
ZW		 69void
70intel_edp_link_config (struct intel_output *intel_output,
71 int *lane_num, int *link_bw)
72{
73 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
74
75 *lane_num = dp_priv->lane_count;
76 if (dp_priv->link_bw == DP_LINK_BW_1_62)
77 *link_bw = 162000;
78 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
79 *link_bw = 270000;
80}
81
a4fc5ed6
KP		 82static int
83intel_dp_max_lane_count(struct intel_output *intel_output)
84{
85 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
86 int max_lane_count = 4;
87
88 if (dp_priv->dpcd[0] >= 0x11) {
89 max_lane_count = dp_priv->dpcd[2] & 0x1f;
90 switch (max_lane_count) {
91 case 1: case 2: case 4:
92 break;
93 default:
94 max_lane_count = 4;
95 }
96 }
97 return max_lane_count;
98}
99
100static int
101intel_dp_max_link_bw(struct intel_output *intel_output)
102{
103 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
104 int max_link_bw = dp_priv->dpcd[1];
105
106 switch (max_link_bw) {
107 case DP_LINK_BW_1_62:
108 case DP_LINK_BW_2_7:
109 break;
110 default:
111 max_link_bw = DP_LINK_BW_1_62;
112 break;
113 }
114 return max_link_bw;
115}
116
117static int
118intel_dp_link_clock(uint8_t link_bw)
119{
120 if (link_bw == DP_LINK_BW_2_7)
121 return 270000;
122 else
123 return 162000;
124}
125
126/* I think this is a fiction */
127static int
128intel_dp_link_required(int pixel_clock)
129{
130 return pixel_clock * 3;
131}
132
133static int
134intel_dp_mode_valid(struct drm_connector *connector,
135 struct drm_display_mode *mode)
136{
137 struct intel_output *intel_output = to_intel_output(connector);
138 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
139 int max_lanes = intel_dp_max_lane_count(intel_output);
140
141 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
142 return MODE_CLOCK_HIGH;
143
144 if (mode->clock < 10000)
145 return MODE_CLOCK_LOW;
146
147 return MODE_OK;
148}
149
150static uint32_t
151pack_aux(uint8_t *src, int src_bytes)
152{
153 int i;
154 uint32_t v = 0;
155
156 if (src_bytes > 4)
157 src_bytes = 4;
158 for (i = 0; i < src_bytes; i++)
159 v |= ((uint32_t) src[i]) << ((3-i) * 8);
160 return v;
161}
162
163static void
164unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
165{
166 int i;
167 if (dst_bytes > 4)
168 dst_bytes = 4;
169 for (i = 0; i < dst_bytes; i++)
170 dst[i] = src >> ((3-i) * 8);
171}
172
fb0f8fbf
KP		 173/* hrawclock is 1/4 the FSB frequency */
174static int
175intel_hrawclk(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 uint32_t clkcfg;
179
180 clkcfg = I915_READ(CLKCFG);
181 switch (clkcfg & CLKCFG_FSB_MASK) {
182 case CLKCFG_FSB_400:
183 return 100;
184 case CLKCFG_FSB_533:
185 return 133;
186 case CLKCFG_FSB_667:
187 return 166;
188 case CLKCFG_FSB_800:
189 return 200;
190 case CLKCFG_FSB_1067:
191 return 266;
192 case CLKCFG_FSB_1333:
193 return 333;
194 /* these two are just a guess; one of them might be right */
195 case CLKCFG_FSB_1600:
196 case CLKCFG_FSB_1600_ALT:
197 return 400;
198 default:
199 return 133;
200 }
201}
202
a4fc5ed6
KP		 203static int
204intel_dp_aux_ch(struct intel_output *intel_output,
205 uint8_t *send, int send_bytes,
206 uint8_t *recv, int recv_size)
207{
208 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
209 uint32_t output_reg = dp_priv->output_reg;
210 struct drm_device *dev = intel_output->base.dev;
211 struct drm_i915_private *dev_priv = dev->dev_private;
212 uint32_t ch_ctl = output_reg + 0x10;
213 uint32_t ch_data = ch_ctl + 4;
214 int i;
215 int recv_bytes;
216 uint32_t ctl;
217 uint32_t status;
fb0f8fbf
KP		 218 uint32_t aux_clock_divider;
219 int try;
a4fc5ed6
KP		 220
221 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 222 * and would like to run at 2MHz. So, take the
223 * hrawclk value and divide by 2 and use that
a4fc5ed6 224 */
32f9d658
ZW		 225 if (IS_eDP(intel_output))
226 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
f2b115e6
AJ		 227 else if (IS_IRONLAKE(dev))
228 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 229 else
230 aux_clock_divider = intel_hrawclk(dev) / 2;
231
fb0f8fbf
KP		 232 /* Must try at least 3 times according to DP spec */
233 for (try = 0; try < 5; try++) {
234 /* Load the send data into the aux channel data registers */
235 for (i = 0; i < send_bytes; i += 4) {
a419aef8 236 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 237
238 I915_WRITE(ch_data + i, d);
239 }
240
241 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
242 DP_AUX_CH_CTL_TIME_OUT_400us |
243 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
244 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
245 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
246 DP_AUX_CH_CTL_DONE |
247 DP_AUX_CH_CTL_TIME_OUT_ERROR |
248 DP_AUX_CH_CTL_RECEIVE_ERROR);
249
250 /* Send the command and wait for it to complete */
251 I915_WRITE(ch_ctl, ctl);
252 (void) I915_READ(ch_ctl);
253 for (;;) {
254 udelay(100);
255 status = I915_READ(ch_ctl);
256 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
257 break;
258 }
259
260 /* Clear done status and any errors */
eebc863e 261 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 262 DP_AUX_CH_CTL_DONE |
263 DP_AUX_CH_CTL_TIME_OUT_ERROR |
264 DP_AUX_CH_CTL_RECEIVE_ERROR));
265 (void) I915_READ(ch_ctl);
266 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 267 break;
268 }
269
a4fc5ed6 270 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 271 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 272 return -EBUSY;
a4fc5ed6
KP		 273 }
274
275 /* Check for timeout or receive error.
276 * Timeouts occur when the sink is not connected
277 */
a5b3da54 278 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 279 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 280 return -EIO;
281 }
1ae8c0a5
KP		 282
283 /* Timeouts occur when the device isn't connected, so they're
284 * "normal" -- don't fill the kernel log with these */
a5b3da54 285 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 286 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 287 return -ETIMEDOUT;
a4fc5ed6
KP		 288 }
289
290 /* Unload any bytes sent back from the other side */
291 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
292 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
293
294 if (recv_bytes > recv_size)
295 recv_bytes = recv_size;
296
297 for (i = 0; i < recv_bytes; i += 4) {
298 uint32_t d = I915_READ(ch_data + i);
299
300 unpack_aux(d, recv + i, recv_bytes - i);
301 }
302
303 return recv_bytes;
304}
305
306/* Write data to the aux channel in native mode */
307static int
308intel_dp_aux_native_write(struct intel_output *intel_output,
309 uint16_t address, uint8_t *send, int send_bytes)
310{
311 int ret;
312 uint8_t msg[20];
313 int msg_bytes;
314 uint8_t ack;
315
316 if (send_bytes > 16)
317 return -1;
318 msg[0] = AUX_NATIVE_WRITE << 4;
319 msg[1] = address >> 8;
eebc863e 320 msg[2] = address & 0xff;
a4fc5ed6
KP		 321 msg[3] = send_bytes - 1;
322 memcpy(&msg[4], send, send_bytes);
323 msg_bytes = send_bytes + 4;
324 for (;;) {
325 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
326 if (ret < 0)
327 return ret;
328 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
329 break;
330 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
331 udelay(100);
332 else
a5b3da54 333 return -EIO;
a4fc5ed6
KP		 334 }
335 return send_bytes;
336}
337
338/* Write a single byte to the aux channel in native mode */
339static int
340intel_dp_aux_native_write_1(struct intel_output *intel_output,
341 uint16_t address, uint8_t byte)
342{
343 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
344}
345
346/* read bytes from a native aux channel */
347static int
348intel_dp_aux_native_read(struct intel_output *intel_output,
349 uint16_t address, uint8_t *recv, int recv_bytes)
350{
351 uint8_t msg[4];
352 int msg_bytes;
353 uint8_t reply[20];
354 int reply_bytes;
355 uint8_t ack;
356 int ret;
357
358 msg[0] = AUX_NATIVE_READ << 4;
359 msg[1] = address >> 8;
360 msg[2] = address & 0xff;
361 msg[3] = recv_bytes - 1;
362
363 msg_bytes = 4;
364 reply_bytes = recv_bytes + 1;
365
366 for (;;) {
367 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
368 reply, reply_bytes);
a5b3da54
KP		 369 if (ret == 0)
370 return -EPROTO;
371 if (ret < 0)
a4fc5ed6
KP		 372 return ret;
373 ack = reply[0];
374 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
375 memcpy(recv, reply + 1, ret - 1);
376 return ret - 1;
377 }
378 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
379 udelay(100);
380 else
a5b3da54 381 return -EIO;
a4fc5ed6
KP		 382 }
383}
384
385static int
386intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
387 uint8_t *send, int send_bytes,
388 uint8_t *recv, int recv_bytes)
389{
390 struct intel_dp_priv *dp_priv = container_of(adapter,
391 struct intel_dp_priv,
392 adapter);
393 struct intel_output *intel_output = dp_priv->intel_output;
394
395 return intel_dp_aux_ch(intel_output,
396 send, send_bytes, recv, recv_bytes);
397}
398
399static int
400intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
401{
402 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
403
d54e9d28 404 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 405 dp_priv->algo.running = false;
406 dp_priv->algo.address = 0;
407 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
408
409 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
410 dp_priv->adapter.owner = THIS_MODULE;
411 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 412 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
413 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6
KP		 414 dp_priv->adapter.algo_data = &dp_priv->algo;
415 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
416
417 return i2c_dp_aux_add_bus(&dp_priv->adapter);
418}
419
420static bool
421intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
422 struct drm_display_mode *adjusted_mode)
423{
424 struct intel_output *intel_output = enc_to_intel_output(encoder);
425 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
426 int lane_count, clock;
427 int max_lane_count = intel_dp_max_lane_count(intel_output);
428 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
429 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
430
431 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
432 for (clock = 0; clock <= max_clock; clock++) {
433 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
434
435 if (intel_dp_link_required(mode->clock) <= link_avail) {
436 dp_priv->link_bw = bws[clock];
437 dp_priv->lane_count = lane_count;
438 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
28c97730
ZY		 439 DRM_DEBUG_KMS("Display port link bw %02x lane "
440 "count %d clock %d\n",
a4fc5ed6
KP		 441 dp_priv->link_bw, dp_priv->lane_count,
442 adjusted_mode->clock);
443 return true;
444 }
445 }
446 }
447 return false;
448}
449
450struct intel_dp_m_n {
451 uint32_t tu;
452 uint32_t gmch_m;
453 uint32_t gmch_n;
454 uint32_t link_m;
455 uint32_t link_n;
456};
457
458static void
459intel_reduce_ratio(uint32_t *num, uint32_t *den)
460{
461 while (*num > 0xffffff || *den > 0xffffff) {
462 *num >>= 1;
463 *den >>= 1;
464 }
465}
466
467static void
468intel_dp_compute_m_n(int bytes_per_pixel,
469 int nlanes,
470 int pixel_clock,
471 int link_clock,
472 struct intel_dp_m_n *m_n)
473{
474 m_n->tu = 64;
475 m_n->gmch_m = pixel_clock * bytes_per_pixel;
476 m_n->gmch_n = link_clock * nlanes;
477 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
478 m_n->link_m = pixel_clock;
479 m_n->link_n = link_clock;
480 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
481}
482
483void
484intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
485 struct drm_display_mode *adjusted_mode)
486{
487 struct drm_device *dev = crtc->dev;
488 struct drm_mode_config *mode_config = &dev->mode_config;
489 struct drm_connector *connector;
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
492 int lane_count = 4;
493 struct intel_dp_m_n m_n;
494
495 /*
496 * Find the lane count in the intel_output private
497 */
498 list_for_each_entry(connector, &mode_config->connector_list, head) {
499 struct intel_output *intel_output = to_intel_output(connector);
500 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
501
502 if (!connector->encoder || connector->encoder->crtc != crtc)
503 continue;
504
505 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
506 lane_count = dp_priv->lane_count;
507 break;
508 }
509 }
510
511 /*
512 * Compute the GMCH and Link ratios. The '3' here is
513 * the number of bytes_per_pixel post-LUT, which we always
514 * set up for 8-bits of R/G/B, or 3 bytes total.
515 */
516 intel_dp_compute_m_n(3, lane_count,
517 mode->clock, adjusted_mode->clock, &m_n);
518
f2b115e6 519 if (IS_IRONLAKE(dev)) {
5eb08b69
ZW		 520 if (intel_crtc->pipe == 0) {
521 I915_WRITE(TRANSA_DATA_M1,
522 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
523 m_n.gmch_m);
524 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
525 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
526 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
527 } else {
528 I915_WRITE(TRANSB_DATA_M1,
529 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
530 m_n.gmch_m);
531 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
532 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
533 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
534 }
a4fc5ed6 535 } else {
5eb08b69
ZW		 536 if (intel_crtc->pipe == 0) {
537 I915_WRITE(PIPEA_GMCH_DATA_M,
538 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
539 m_n.gmch_m);
540 I915_WRITE(PIPEA_GMCH_DATA_N,
541 m_n.gmch_n);
542 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
543 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
544 } else {
545 I915_WRITE(PIPEB_GMCH_DATA_M,
546 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
547 m_n.gmch_m);
548 I915_WRITE(PIPEB_GMCH_DATA_N,
549 m_n.gmch_n);
550 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
551 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
552 }
a4fc5ed6
KP		 553 }
554}
555
556static void
557intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
558 struct drm_display_mode *adjusted_mode)
559{
560 struct intel_output *intel_output = enc_to_intel_output(encoder);
561 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
562 struct drm_crtc *crtc = intel_output->enc.crtc;
563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
564
565 dp_priv->DP = (DP_LINK_TRAIN_OFF |
566 DP_VOLTAGE_0_4 |
567 DP_PRE_EMPHASIS_0 |
568 DP_SYNC_VS_HIGH |
569 DP_SYNC_HS_HIGH);
570
571 switch (dp_priv->lane_count) {
572 case 1:
573 dp_priv->DP |= DP_PORT_WIDTH_1;
574 break;
575 case 2:
576 dp_priv->DP |= DP_PORT_WIDTH_2;
577 break;
578 case 4:
579 dp_priv->DP |= DP_PORT_WIDTH_4;
580 break;
581 }
582 if (dp_priv->has_audio)
583 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
584
585 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
586 dp_priv->link_configuration[0] = dp_priv->link_bw;
587 dp_priv->link_configuration[1] = dp_priv->lane_count;
588
589 /*
590 * Check for DPCD version > 1.1,
591 * enable enahanced frame stuff in that case
592 */
593 if (dp_priv->dpcd[0] >= 0x11) {
594 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
595 dp_priv->DP |= DP_ENHANCED_FRAMING;
596 }
597
598 if (intel_crtc->pipe == 1)
599 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658
ZW		 600
601 if (IS_eDP(intel_output)) {
602 /* don't miss out required setting for eDP */
603 dp_priv->DP |= DP_PLL_ENABLE;
604 if (adjusted_mode->clock < 200000)
605 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
606 else
607 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
608 }
a4fc5ed6
KP		 609}
610
f2b115e6 611static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 612{
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 u32 pp;
615
28c97730 616 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 617 pp = I915_READ(PCH_PP_CONTROL);
618 pp |= EDP_BLC_ENABLE;
619 I915_WRITE(PCH_PP_CONTROL, pp);
620}
621
f2b115e6 622static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 623{
624 struct drm_i915_private *dev_priv = dev->dev_private;
625 u32 pp;
626
28c97730 627 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 628 pp = I915_READ(PCH_PP_CONTROL);
629 pp &= ~EDP_BLC_ENABLE;
630 I915_WRITE(PCH_PP_CONTROL, pp);
631}
a4fc5ed6
KP		 632
633static void
634intel_dp_dpms(struct drm_encoder *encoder, int mode)
635{
636 struct intel_output *intel_output = enc_to_intel_output(encoder);
637 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
638 struct drm_device *dev = intel_output->base.dev;
639 struct drm_i915_private *dev_priv = dev->dev_private;
640 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
641
642 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 643 if (dp_reg & DP_PORT_EN) {
a4fc5ed6 644 intel_dp_link_down(intel_output, dp_priv->DP);
32f9d658 645 if (IS_eDP(intel_output))
f2b115e6 646 ironlake_edp_backlight_off(dev);
32f9d658 647 }
a4fc5ed6 648 } else {
32f9d658 649 if (!(dp_reg & DP_PORT_EN)) {
a4fc5ed6 650 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
32f9d658 651 if (IS_eDP(intel_output))
f2b115e6 652 ironlake_edp_backlight_on(dev);
32f9d658 653 }
a4fc5ed6 654 }
c8110e52 655 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 656}
657
658/*
659 * Fetch AUX CH registers 0x202 - 0x207 which contain
660 * link status information
661 */
662static bool
663intel_dp_get_link_status(struct intel_output *intel_output,
664 uint8_t link_status[DP_LINK_STATUS_SIZE])
665{
666 int ret;
667
668 ret = intel_dp_aux_native_read(intel_output,
669 DP_LANE0_1_STATUS,
670 link_status, DP_LINK_STATUS_SIZE);
671 if (ret != DP_LINK_STATUS_SIZE)
672 return false;
673 return true;
674}
675
676static uint8_t
677intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
678 int r)
679{
680 return link_status[r - DP_LANE0_1_STATUS];
681}
682
683static void
684intel_dp_save(struct drm_connector *connector)
685{
686 struct intel_output *intel_output = to_intel_output(connector);
687 struct drm_device *dev = intel_output->base.dev;
688 struct drm_i915_private *dev_priv = dev->dev_private;
689 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
690
691 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
692 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
693 dp_priv->save_link_configuration,
694 sizeof (dp_priv->save_link_configuration));
695}
696
697static uint8_t
698intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
699 int lane)
700{
701 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
702 int s = ((lane & 1) ?
703 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
704 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
705 uint8_t l = intel_dp_link_status(link_status, i);
706
707 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
708}
709
710static uint8_t
711intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
712 int lane)
713{
714 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
715 int s = ((lane & 1) ?
716 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
717 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
718 uint8_t l = intel_dp_link_status(link_status, i);
719
720 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
721}
722
723
724#if 0
725static char *voltage_names[] = {
726 "0.4V", "0.6V", "0.8V", "1.2V"
727};
728static char *pre_emph_names[] = {
729 "0dB", "3.5dB", "6dB", "9.5dB"
730};
731static char *link_train_names[] = {
732 "pattern 1", "pattern 2", "idle", "off"
733};
734#endif
735
736/*
737 * These are source-specific values; current Intel hardware supports
738 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
739 */
740#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
741
742static uint8_t
743intel_dp_pre_emphasis_max(uint8_t voltage_swing)
744{
745 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
746 case DP_TRAIN_VOLTAGE_SWING_400:
747 return DP_TRAIN_PRE_EMPHASIS_6;
748 case DP_TRAIN_VOLTAGE_SWING_600:
749 return DP_TRAIN_PRE_EMPHASIS_6;
750 case DP_TRAIN_VOLTAGE_SWING_800:
751 return DP_TRAIN_PRE_EMPHASIS_3_5;
752 case DP_TRAIN_VOLTAGE_SWING_1200:
753 default:
754 return DP_TRAIN_PRE_EMPHASIS_0;
755 }
756}
757
758static void
759intel_get_adjust_train(struct intel_output *intel_output,
760 uint8_t link_status[DP_LINK_STATUS_SIZE],
761 int lane_count,
762 uint8_t train_set[4])
763{
764 uint8_t v = 0;
765 uint8_t p = 0;
766 int lane;
767
768 for (lane = 0; lane < lane_count; lane++) {
769 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
770 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
771
772 if (this_v > v)
773 v = this_v;
774 if (this_p > p)
775 p = this_p;
776 }
777
778 if (v >= I830_DP_VOLTAGE_MAX)
779 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
780
781 if (p >= intel_dp_pre_emphasis_max(v))
782 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
783
784 for (lane = 0; lane < 4; lane++)
785 train_set[lane] = v | p;
786}
787
788static uint32_t
789intel_dp_signal_levels(uint8_t train_set, int lane_count)
790{
791 uint32_t signal_levels = 0;
792
793 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
794 case DP_TRAIN_VOLTAGE_SWING_400:
795 default:
796 signal_levels |= DP_VOLTAGE_0_4;
797 break;
798 case DP_TRAIN_VOLTAGE_SWING_600:
799 signal_levels |= DP_VOLTAGE_0_6;
800 break;
801 case DP_TRAIN_VOLTAGE_SWING_800:
802 signal_levels |= DP_VOLTAGE_0_8;
803 break;
804 case DP_TRAIN_VOLTAGE_SWING_1200:
805 signal_levels |= DP_VOLTAGE_1_2;
806 break;
807 }
808 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
809 case DP_TRAIN_PRE_EMPHASIS_0:
810 default:
811 signal_levels |= DP_PRE_EMPHASIS_0;
812 break;
813 case DP_TRAIN_PRE_EMPHASIS_3_5:
814 signal_levels |= DP_PRE_EMPHASIS_3_5;
815 break;
816 case DP_TRAIN_PRE_EMPHASIS_6:
817 signal_levels |= DP_PRE_EMPHASIS_6;
818 break;
819 case DP_TRAIN_PRE_EMPHASIS_9_5:
820 signal_levels |= DP_PRE_EMPHASIS_9_5;
821 break;
822 }
823 return signal_levels;
824}
825
826static uint8_t
827intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
828 int lane)
829{
830 int i = DP_LANE0_1_STATUS + (lane >> 1);
831 int s = (lane & 1) * 4;
832 uint8_t l = intel_dp_link_status(link_status, i);
833
834 return (l >> s) & 0xf;
835}
836
837/* Check for clock recovery is done on all channels */
838static bool
839intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
840{
841 int lane;
842 uint8_t lane_status;
843
844 for (lane = 0; lane < lane_count; lane++) {
845 lane_status = intel_get_lane_status(link_status, lane);
846 if ((lane_status & DP_LANE_CR_DONE) == 0)
847 return false;
848 }
849 return true;
850}
851
852/* Check to see if channel eq is done on all channels */
853#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
854 DP_LANE_CHANNEL_EQ_DONE|\
855 DP_LANE_SYMBOL_LOCKED)
856static bool
857intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
858{
859 uint8_t lane_align;
860 uint8_t lane_status;
861 int lane;
862
863 lane_align = intel_dp_link_status(link_status,
864 DP_LANE_ALIGN_STATUS_UPDATED);
865 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
866 return false;
867 for (lane = 0; lane < lane_count; lane++) {
868 lane_status = intel_get_lane_status(link_status, lane);
869 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
870 return false;
871 }
872 return true;
873}
874
875static bool
876intel_dp_set_link_train(struct intel_output *intel_output,
877 uint32_t dp_reg_value,
878 uint8_t dp_train_pat,
879 uint8_t train_set[4],
880 bool first)
881{
882 struct drm_device *dev = intel_output->base.dev;
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
885 int ret;
886
887 I915_WRITE(dp_priv->output_reg, dp_reg_value);
888 POSTING_READ(dp_priv->output_reg);
889 if (first)
890 intel_wait_for_vblank(dev);
891
892 intel_dp_aux_native_write_1(intel_output,
893 DP_TRAINING_PATTERN_SET,
894 dp_train_pat);
895
896 ret = intel_dp_aux_native_write(intel_output,
897 DP_TRAINING_LANE0_SET, train_set, 4);
898 if (ret != 4)
899 return false;
900
901 return true;
902}
903
904static void
905intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
906 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
907{
908 struct drm_device *dev = intel_output->base.dev;
909 struct drm_i915_private *dev_priv = dev->dev_private;
910 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
911 uint8_t train_set[4];
912 uint8_t link_status[DP_LINK_STATUS_SIZE];
913 int i;
914 uint8_t voltage;
915 bool clock_recovery = false;
916 bool channel_eq = false;
917 bool first = true;
918 int tries;
919
920 /* Write the link configuration data */
921 intel_dp_aux_native_write(intel_output, 0x100,
922 link_configuration, DP_LINK_CONFIGURATION_SIZE);
923
924 DP |= DP_PORT_EN;
925 DP &= ~DP_LINK_TRAIN_MASK;
926 memset(train_set, 0, 4);
927 voltage = 0xff;
928 tries = 0;
929 clock_recovery = false;
930 for (;;) {
931 /* Use train_set[0] to set the voltage and pre emphasis values */
932 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
933 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
934
935 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
936 DP_TRAINING_PATTERN_1, train_set, first))
937 break;
938 first = false;
939 /* Set training pattern 1 */
940
941 udelay(100);
942 if (!intel_dp_get_link_status(intel_output, link_status))
943 break;
944
945 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
946 clock_recovery = true;
947 break;
948 }
949
950 /* Check to see if we've tried the max voltage */
951 for (i = 0; i < dp_priv->lane_count; i++)
952 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
953 break;
954 if (i == dp_priv->lane_count)
955 break;
956
957 /* Check to see if we've tried the same voltage 5 times */
958 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
959 ++tries;
960 if (tries == 5)
961 break;
962 } else
963 tries = 0;
964 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
965
966 /* Compute new train_set as requested by target */
967 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
968 }
969
970 /* channel equalization */
971 tries = 0;
972 channel_eq = false;
973 for (;;) {
974 /* Use train_set[0] to set the voltage and pre emphasis values */
975 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
976 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
977
978 /* channel eq pattern */
979 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
980 DP_TRAINING_PATTERN_2, train_set,
981 false))
982 break;
983
984 udelay(400);
985 if (!intel_dp_get_link_status(intel_output, link_status))
986 break;
987
988 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
989 channel_eq = true;
990 break;
991 }
992
993 /* Try 5 times */
994 if (tries > 5)
995 break;
996
997 /* Compute new train_set as requested by target */
998 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
999 ++tries;
1000 }
1001
1002 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1003 POSTING_READ(dp_priv->output_reg);
1004 intel_dp_aux_native_write_1(intel_output,
1005 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1006}
1007
1008static void
1009intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1010{
1011 struct drm_device *dev = intel_output->base.dev;
1012 struct drm_i915_private *dev_priv = dev->dev_private;
1013 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1014
28c97730 1015 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 1016
1017 if (IS_eDP(intel_output)) {
1018 DP &= ~DP_PLL_ENABLE;
1019 I915_WRITE(dp_priv->output_reg, DP);
1020 POSTING_READ(dp_priv->output_reg);
1021 udelay(100);
1022 }
1023
5eb08b69
ZW		 1024 DP &= ~DP_LINK_TRAIN_MASK;
1025 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1026 POSTING_READ(dp_priv->output_reg);
1027
1028 udelay(17000);
1029
32f9d658
ZW		 1030 if (IS_eDP(intel_output))
1031 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1032 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1033 POSTING_READ(dp_priv->output_reg);
1034}
1035
1036static void
1037intel_dp_restore(struct drm_connector *connector)
1038{
1039 struct intel_output *intel_output = to_intel_output(connector);
1040 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1041
1042 if (dp_priv->save_DP & DP_PORT_EN)
1043 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
1044 else
1045 intel_dp_link_down(intel_output, dp_priv->save_DP);
1046}
1047
a4fc5ed6
KP		 1048/*
1049 * According to DP spec
1050 * 5.1.2:
1051 * 1. Read DPCD
1052 * 2. Configure link according to Receiver Capabilities
1053 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1054 * 4. Check link status on receipt of hot-plug interrupt
1055 */
1056
1057static void
1058intel_dp_check_link_status(struct intel_output *intel_output)
1059{
1060 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1061 uint8_t link_status[DP_LINK_STATUS_SIZE];
1062
1063 if (!intel_output->enc.crtc)
1064 return;
1065
1066 if (!intel_dp_get_link_status(intel_output, link_status)) {
1067 intel_dp_link_down(intel_output, dp_priv->DP);
1068 return;
1069 }
1070
1071 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1072 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
1073}
a4fc5ed6 1074
5eb08b69 1075static enum drm_connector_status
f2b115e6 1076ironlake_dp_detect(struct drm_connector *connector)
5eb08b69
ZW		 1077{
1078 struct intel_output *intel_output = to_intel_output(connector);
1079 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1080 enum drm_connector_status status;
1081
1082 status = connector_status_disconnected;
1083 if (intel_dp_aux_native_read(intel_output,
1084 0x000, dp_priv->dpcd,
1085 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1086 {
1087 if (dp_priv->dpcd[0] != 0)
1088 status = connector_status_connected;
1089 }
1090 return status;
1091}
1092
a4fc5ed6
KP		 1093/**
1094 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1095 *
1096 * \return true if DP port is connected.
1097 * \return false if DP port is disconnected.
1098 */
1099static enum drm_connector_status
1100intel_dp_detect(struct drm_connector *connector)
1101{
1102 struct intel_output *intel_output = to_intel_output(connector);
1103 struct drm_device *dev = intel_output->base.dev;
1104 struct drm_i915_private *dev_priv = dev->dev_private;
1105 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1106 uint32_t temp, bit;
1107 enum drm_connector_status status;
1108
1109 dp_priv->has_audio = false;
1110
f2b115e6
AJ		 1111 if (IS_IRONLAKE(dev))
1112 return ironlake_dp_detect(connector);
5eb08b69 1113
a4fc5ed6
KP		 1114 temp = I915_READ(PORT_HOTPLUG_EN);
1115
1116 I915_WRITE(PORT_HOTPLUG_EN,
1117 temp |
1118 DPB_HOTPLUG_INT_EN |
1119 DPC_HOTPLUG_INT_EN |
1120 DPD_HOTPLUG_INT_EN);
1121
1122 POSTING_READ(PORT_HOTPLUG_EN);
1123
1124 switch (dp_priv->output_reg) {
1125 case DP_B:
1126 bit = DPB_HOTPLUG_INT_STATUS;
1127 break;
1128 case DP_C:
1129 bit = DPC_HOTPLUG_INT_STATUS;
1130 break;
1131 case DP_D:
1132 bit = DPD_HOTPLUG_INT_STATUS;
1133 break;
1134 default:
1135 return connector_status_unknown;
1136 }
1137
1138 temp = I915_READ(PORT_HOTPLUG_STAT);
1139
1140 if ((temp & bit) == 0)
1141 return connector_status_disconnected;
1142
1143 status = connector_status_disconnected;
1144 if (intel_dp_aux_native_read(intel_output,
1145 0x000, dp_priv->dpcd,
1146 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1147 {
1148 if (dp_priv->dpcd[0] != 0)
1149 status = connector_status_connected;
1150 }
1151 return status;
1152}
1153
1154static int intel_dp_get_modes(struct drm_connector *connector)
1155{
1156 struct intel_output *intel_output = to_intel_output(connector);
32f9d658
ZW		 1157 struct drm_device *dev = intel_output->base.dev;
1158 struct drm_i915_private *dev_priv = dev->dev_private;
1159 int ret;
a4fc5ed6
KP		 1160
1161 /* We should parse the EDID data and find out if it has an audio sink
1162 */
1163
32f9d658
ZW		 1164 ret = intel_ddc_get_modes(intel_output);
1165 if (ret)
1166 return ret;
1167
1168 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1169 if (IS_eDP(intel_output)) {
1170 if (dev_priv->panel_fixed_mode != NULL) {
1171 struct drm_display_mode *mode;
1172 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1173 drm_mode_probed_add(connector, mode);
1174 return 1;
1175 }
1176 }
1177 return 0;
a4fc5ed6
KP		 1178}
1179
1180static void
1181intel_dp_destroy (struct drm_connector *connector)
1182{
1183 struct intel_output *intel_output = to_intel_output(connector);
1184
1185 if (intel_output->i2c_bus)
1186 intel_i2c_destroy(intel_output->i2c_bus);
1187 drm_sysfs_connector_remove(connector);
1188 drm_connector_cleanup(connector);
1189 kfree(intel_output);
1190}
1191
1192static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1193 .dpms = intel_dp_dpms,
1194 .mode_fixup = intel_dp_mode_fixup,
1195 .prepare = intel_encoder_prepare,
1196 .mode_set = intel_dp_mode_set,
1197 .commit = intel_encoder_commit,
1198};
1199
1200static const struct drm_connector_funcs intel_dp_connector_funcs = {
1201 .dpms = drm_helper_connector_dpms,
1202 .save = intel_dp_save,
1203 .restore = intel_dp_restore,
1204 .detect = intel_dp_detect,
1205 .fill_modes = drm_helper_probe_single_connector_modes,
1206 .destroy = intel_dp_destroy,
1207};
1208
1209static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1210 .get_modes = intel_dp_get_modes,
1211 .mode_valid = intel_dp_mode_valid,
1212 .best_encoder = intel_best_encoder,
1213};
1214
1215static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1216{
1217 drm_encoder_cleanup(encoder);
1218}
1219
1220static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1221 .destroy = intel_dp_enc_destroy,
1222};
1223
c8110e52
KP		 1224void
1225intel_dp_hot_plug(struct intel_output *intel_output)
1226{
1227 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1228
1229 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1230 intel_dp_check_link_status(intel_output);
1231}
ae266c98
ZY		 1232/*
1233 * Enumerate the child dev array parsed from VBT to check whether
1234 * the given DP is present.
1235 * If it is present, return 1.
1236 * If it is not present, return false.
1237 * If no child dev is parsed from VBT, it is assumed that the given
1238 * DP is present.
1239 */
6e36595a 1240static int dp_is_present_in_vbt(struct drm_device *dev, int dp_reg)
ae266c98
ZY		 1241{
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 struct child_device_config *p_child;
1244 int i, dp_port, ret;
1245
1246 if (!dev_priv->child_dev_num)
1247 return 1;
1248
1249 dp_port = 0;
f24bc39f 1250 if (dp_reg == DP_B || dp_reg == PCH_DP_B)
ae266c98 1251 dp_port = PORT_IDPB;
f24bc39f 1252 else if (dp_reg == DP_C || dp_reg == PCH_DP_C)
ae266c98 1253 dp_port = PORT_IDPC;
f24bc39f 1254 else if (dp_reg == DP_D || dp_reg == PCH_DP_D)
ae266c98
ZY		 1255 dp_port = PORT_IDPD;
1256
1257 ret = 0;
1258 for (i = 0; i < dev_priv->child_dev_num; i++) {
1259 p_child = dev_priv->child_dev + i;
1260 /*
1261 * If the device type is not DP, continue.
1262 */
1263 if (p_child->device_type != DEVICE_TYPE_DP &&
1264 p_child->device_type != DEVICE_TYPE_eDP)
1265 continue;
1266 /* Find the eDP port */
1267 if (dp_reg == DP_A && p_child->device_type == DEVICE_TYPE_eDP) {
1268 ret = 1;
1269 break;
1270 }
1271 /* Find the DP port */
1272 if (p_child->dvo_port == dp_port) {
1273 ret = 1;
1274 break;
1275 }
1276 }
1277 return ret;
1278}
a4fc5ed6
KP		 1279void
1280intel_dp_init(struct drm_device *dev, int output_reg)
1281{
1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 struct drm_connector *connector;
1284 struct intel_output *intel_output;
1285 struct intel_dp_priv *dp_priv;
5eb08b69 1286 const char *name = NULL;
a4fc5ed6 1287
ae266c98
ZY		 1288 if (!dp_is_present_in_vbt(dev, output_reg)) {
1289 DRM_DEBUG_KMS("DP is not present. Ignore it\n");
1290 return;
1291 }
a4fc5ed6
KP		 1292 intel_output = kcalloc(sizeof(struct intel_output) +
1293 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1294 if (!intel_output)
1295 return;
1296
1297 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1298
1299 connector = &intel_output->base;
1300 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1301 DRM_MODE_CONNECTOR_DisplayPort);
1302 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1303
32f9d658
ZW		 1304 if (output_reg == DP_A)
1305 intel_output->type = INTEL_OUTPUT_EDP;
1306 else
1307 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
a4fc5ed6 1308
652af9d7 1309 if (output_reg == DP_B || output_reg == PCH_DP_B)
f8aed700 1310 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1311 else if (output_reg == DP_C || output_reg == PCH_DP_C)
f8aed700 1312 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1313 else if (output_reg == DP_D || output_reg == PCH_DP_D)
f8aed700
ML		 1314 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1315
1316 if (IS_eDP(intel_output)) {
1317 intel_output->crtc_mask = (1 << 1);
7c8460db 1318 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
f8aed700
ML		 1319 } else
1320 intel_output->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1321 connector->interlace_allowed = true;
1322 connector->doublescan_allowed = 0;
1323
1324 dp_priv->intel_output = intel_output;
1325 dp_priv->output_reg = output_reg;
1326 dp_priv->has_audio = false;
c8110e52 1327 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6
KP		 1328 intel_output->dev_priv = dp_priv;
1329
1330 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1331 DRM_MODE_ENCODER_TMDS);
1332 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1333
1334 drm_mode_connector_attach_encoder(&intel_output->base,
1335 &intel_output->enc);
1336 drm_sysfs_connector_add(connector);
1337
1338 /* Set up the DDC bus. */
5eb08b69 1339 switch (output_reg) {
32f9d658
ZW		 1340 case DP_A:
1341 name = "DPDDC-A";
1342 break;
5eb08b69
ZW		 1343 case DP_B:
1344 case PCH_DP_B:
1345 name = "DPDDC-B";
1346 break;
1347 case DP_C:
1348 case PCH_DP_C:
1349 name = "DPDDC-C";
1350 break;
1351 case DP_D:
1352 case PCH_DP_D:
1353 name = "DPDDC-D";
1354 break;
1355 }
1356
1357 intel_dp_i2c_init(intel_output, name);
32f9d658 1358
a4fc5ed6 1359 intel_output->ddc_bus = &dp_priv->adapter;
c8110e52 1360 intel_output->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1361
32f9d658
ZW		 1362 if (output_reg == DP_A) {
1363 /* initialize panel mode from VBT if available for eDP */
1364 if (dev_priv->lfp_lvds_vbt_mode) {
1365 dev_priv->panel_fixed_mode =
1366 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1367 if (dev_priv->panel_fixed_mode) {
1368 dev_priv->panel_fixed_mode->type |=
1369 DRM_MODE_TYPE_PREFERRED;
1370 }
1371 }
1372 }
1373
a4fc5ed6
KP		 1374 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1375 * 0xd. Failure to do so will result in spurious interrupts being
1376 * generated on the port when a cable is not attached.
1377 */
1378 if (IS_G4X(dev) && !IS_GM45(dev)) {
1379 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1380 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1381 }
1382}
Clone of davem's net-next-2.6 tree