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Merge branch 'v4l_for_2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/mcheha...
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
a4fc5ed6
KP		 30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
ab2c0672 37#include "drm_dp_helper.h"
a4fc5ed6 38
ae266c98 39
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
32f9d658
ZW		 45#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
46
a4fc5ed6
KP		 47struct intel_dp_priv {
48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 51 bool has_audio;
c8110e52 52 int dpms_mode;
a4fc5ed6
KP		 53 uint8_t link_bw;
54 uint8_t lane_count;
55 uint8_t dpcd[4];
21d40d37 56 struct intel_encoder *intel_encoder;
a4fc5ed6
KP		 57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59};
60
61static void
21d40d37 62intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
a4fc5ed6
KP		 63 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
64
65static void
21d40d37 66intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
a4fc5ed6 67
32f9d658 68void
21d40d37 69intel_edp_link_config (struct intel_encoder *intel_encoder,
32f9d658
ZW		 70 int *lane_num, int *link_bw)
71{
21d40d37 72 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
32f9d658
ZW		 73
74 *lane_num = dp_priv->lane_count;
75 if (dp_priv->link_bw == DP_LINK_BW_1_62)
76 *link_bw = 162000;
77 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
78 *link_bw = 270000;
79}
80
a4fc5ed6 81static int
21d40d37 82intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
a4fc5ed6 83{
21d40d37 84 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 85 int max_lane_count = 4;
86
87 if (dp_priv->dpcd[0] >= 0x11) {
88 max_lane_count = dp_priv->dpcd[2] & 0x1f;
89 switch (max_lane_count) {
90 case 1: case 2: case 4:
91 break;
92 default:
93 max_lane_count = 4;
94 }
95 }
96 return max_lane_count;
97}
98
99static int
21d40d37 100intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
a4fc5ed6 101{
21d40d37 102 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 103 int max_link_bw = dp_priv->dpcd[1];
104
105 switch (max_link_bw) {
106 case DP_LINK_BW_1_62:
107 case DP_LINK_BW_2_7:
108 break;
109 default:
110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
116static int
117intel_dp_link_clock(uint8_t link_bw)
118{
119 if (link_bw == DP_LINK_BW_2_7)
120 return 270000;
121 else
122 return 162000;
123}
124
125/* I think this is a fiction */
126static int
885a5fb5 127intel_dp_link_required(struct drm_device *dev,
21d40d37 128 struct intel_encoder *intel_encoder, int pixel_clock)
a4fc5ed6 129{
885a5fb5
ZW		 130 struct drm_i915_private *dev_priv = dev->dev_private;
131
21d40d37 132 if (IS_eDP(intel_encoder))
885a5fb5
ZW		 133 return (pixel_clock * dev_priv->edp_bpp) / 8;
134 else
135 return pixel_clock * 3;
a4fc5ed6
KP		 136}
137
138static int
139intel_dp_mode_valid(struct drm_connector *connector,
140 struct drm_display_mode *mode)
141{
55f78c43
ZW		 142 struct drm_encoder *encoder = intel_attached_encoder(connector);
143 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37
EA		 144 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
145 int max_lanes = intel_dp_max_lane_count(intel_encoder);
a4fc5ed6 146
21d40d37 147 if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
885a5fb5 148 > max_link_clock * max_lanes)
a4fc5ed6
KP		 149 return MODE_CLOCK_HIGH;
150
151 if (mode->clock < 10000)
152 return MODE_CLOCK_LOW;
153
154 return MODE_OK;
155}
156
157static uint32_t
158pack_aux(uint8_t *src, int src_bytes)
159{
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168}
169
170static void
171unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172{
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178}
179
fb0f8fbf
KP		 180/* hrawclock is 1/4 the FSB frequency */
181static int
182intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 clkcfg = I915_READ(CLKCFG);
188 switch (clkcfg & CLKCFG_FSB_MASK) {
189 case CLKCFG_FSB_400:
190 return 100;
191 case CLKCFG_FSB_533:
192 return 133;
193 case CLKCFG_FSB_667:
194 return 166;
195 case CLKCFG_FSB_800:
196 return 200;
197 case CLKCFG_FSB_1067:
198 return 266;
199 case CLKCFG_FSB_1333:
200 return 333;
201 /* these two are just a guess; one of them might be right */
202 case CLKCFG_FSB_1600:
203 case CLKCFG_FSB_1600_ALT:
204 return 400;
205 default:
206 return 133;
207 }
208}
209
a4fc5ed6 210static int
21d40d37 211intel_dp_aux_ch(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 212 uint8_t *send, int send_bytes,
213 uint8_t *recv, int recv_size)
214{
21d40d37 215 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 216 uint32_t output_reg = dp_priv->output_reg;
55f78c43 217 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6
KP		 218 struct drm_i915_private *dev_priv = dev->dev_private;
219 uint32_t ch_ctl = output_reg + 0x10;
220 uint32_t ch_data = ch_ctl + 4;
221 int i;
222 int recv_bytes;
223 uint32_t ctl;
224 uint32_t status;
fb0f8fbf 225 uint32_t aux_clock_divider;
e3421a18 226 int try, precharge;
a4fc5ed6
KP		 227
228 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 229 * and would like to run at 2MHz. So, take the
230 * hrawclk value and divide by 2 and use that
a4fc5ed6 231 */
e3421a18
ZW		 232 if (IS_eDP(intel_encoder)) {
233 if (IS_GEN6(dev))
234 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
235 else
236 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
237 } else if (HAS_PCH_SPLIT(dev))
f2b115e6 238 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 239 else
240 aux_clock_divider = intel_hrawclk(dev) / 2;
241
e3421a18
ZW		 242 if (IS_GEN6(dev))
243 precharge = 3;
244 else
245 precharge = 5;
246
fb0f8fbf
KP		 247 /* Must try at least 3 times according to DP spec */
248 for (try = 0; try < 5; try++) {
249 /* Load the send data into the aux channel data registers */
250 for (i = 0; i < send_bytes; i += 4) {
a419aef8 251 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 252
253 I915_WRITE(ch_data + i, d);
254 }
255
256 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
257 DP_AUX_CH_CTL_TIME_OUT_400us |
258 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
e3421a18 259 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
fb0f8fbf
KP		 260 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
261 DP_AUX_CH_CTL_DONE |
262 DP_AUX_CH_CTL_TIME_OUT_ERROR |
263 DP_AUX_CH_CTL_RECEIVE_ERROR);
264
265 /* Send the command and wait for it to complete */
266 I915_WRITE(ch_ctl, ctl);
267 (void) I915_READ(ch_ctl);
268 for (;;) {
269 udelay(100);
270 status = I915_READ(ch_ctl);
271 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
272 break;
273 }
274
275 /* Clear done status and any errors */
eebc863e 276 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 277 DP_AUX_CH_CTL_DONE |
278 DP_AUX_CH_CTL_TIME_OUT_ERROR |
279 DP_AUX_CH_CTL_RECEIVE_ERROR));
280 (void) I915_READ(ch_ctl);
281 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 282 break;
283 }
284
a4fc5ed6 285 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 286 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 287 return -EBUSY;
a4fc5ed6
KP		 288 }
289
290 /* Check for timeout or receive error.
291 * Timeouts occur when the sink is not connected
292 */
a5b3da54 293 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 294 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 295 return -EIO;
296 }
1ae8c0a5
KP		 297
298 /* Timeouts occur when the device isn't connected, so they're
299 * "normal" -- don't fill the kernel log with these */
a5b3da54 300 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 301 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 302 return -ETIMEDOUT;
a4fc5ed6
KP		 303 }
304
305 /* Unload any bytes sent back from the other side */
306 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
307 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
308
309 if (recv_bytes > recv_size)
310 recv_bytes = recv_size;
311
312 for (i = 0; i < recv_bytes; i += 4) {
313 uint32_t d = I915_READ(ch_data + i);
314
315 unpack_aux(d, recv + i, recv_bytes - i);
316 }
317
318 return recv_bytes;
319}
320
321/* Write data to the aux channel in native mode */
322static int
21d40d37 323intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 324 uint16_t address, uint8_t *send, int send_bytes)
325{
326 int ret;
327 uint8_t msg[20];
328 int msg_bytes;
329 uint8_t ack;
330
331 if (send_bytes > 16)
332 return -1;
333 msg[0] = AUX_NATIVE_WRITE << 4;
334 msg[1] = address >> 8;
eebc863e 335 msg[2] = address & 0xff;
a4fc5ed6
KP		 336 msg[3] = send_bytes - 1;
337 memcpy(&msg[4], send, send_bytes);
338 msg_bytes = send_bytes + 4;
339 for (;;) {
21d40d37 340 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 341 if (ret < 0)
342 return ret;
343 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
344 break;
345 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
346 udelay(100);
347 else
a5b3da54 348 return -EIO;
a4fc5ed6
KP		 349 }
350 return send_bytes;
351}
352
353/* Write a single byte to the aux channel in native mode */
354static int
21d40d37 355intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 356 uint16_t address, uint8_t byte)
357{
21d40d37 358 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
a4fc5ed6
KP		 359}
360
361/* read bytes from a native aux channel */
362static int
21d40d37 363intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 364 uint16_t address, uint8_t *recv, int recv_bytes)
365{
366 uint8_t msg[4];
367 int msg_bytes;
368 uint8_t reply[20];
369 int reply_bytes;
370 uint8_t ack;
371 int ret;
372
373 msg[0] = AUX_NATIVE_READ << 4;
374 msg[1] = address >> 8;
375 msg[2] = address & 0xff;
376 msg[3] = recv_bytes - 1;
377
378 msg_bytes = 4;
379 reply_bytes = recv_bytes + 1;
380
381 for (;;) {
21d40d37 382 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
a4fc5ed6 383 reply, reply_bytes);
a5b3da54
KP		 384 if (ret == 0)
385 return -EPROTO;
386 if (ret < 0)
a4fc5ed6
KP		 387 return ret;
388 ack = reply[0];
389 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
390 memcpy(recv, reply + 1, ret - 1);
391 return ret - 1;
392 }
393 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
394 udelay(100);
395 else
a5b3da54 396 return -EIO;
a4fc5ed6
KP		 397 }
398}
399
400static int
ab2c0672
DA		 401intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
402 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 403{
ab2c0672 404 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6
KP		 405 struct intel_dp_priv *dp_priv = container_of(adapter,
406 struct intel_dp_priv,
407 adapter);
21d40d37 408 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
ab2c0672
DA		 409 uint16_t address = algo_data->address;
410 uint8_t msg[5];
411 uint8_t reply[2];
412 int msg_bytes;
413 int reply_bytes;
414 int ret;
415
416 /* Set up the command byte */
417 if (mode & MODE_I2C_READ)
418 msg[0] = AUX_I2C_READ << 4;
419 else
420 msg[0] = AUX_I2C_WRITE << 4;
421
422 if (!(mode & MODE_I2C_STOP))
423 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 424
ab2c0672
DA		 425 msg[1] = address >> 8;
426 msg[2] = address;
427
428 switch (mode) {
429 case MODE_I2C_WRITE:
430 msg[3] = 0;
431 msg[4] = write_byte;
432 msg_bytes = 5;
433 reply_bytes = 1;
434 break;
435 case MODE_I2C_READ:
436 msg[3] = 0;
437 msg_bytes = 4;
438 reply_bytes = 2;
439 break;
440 default:
441 msg_bytes = 3;
442 reply_bytes = 1;
443 break;
444 }
445
446 for (;;) {
21d40d37 447 ret = intel_dp_aux_ch(intel_encoder,
ab2c0672
DA		 448 msg, msg_bytes,
449 reply, reply_bytes);
450 if (ret < 0) {
3ff99164 451 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 452 return ret;
453 }
454 switch (reply[0] & AUX_I2C_REPLY_MASK) {
455 case AUX_I2C_REPLY_ACK:
456 if (mode == MODE_I2C_READ) {
457 *read_byte = reply[1];
458 }
459 return reply_bytes - 1;
460 case AUX_I2C_REPLY_NACK:
3ff99164 461 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 462 return -EREMOTEIO;
463 case AUX_I2C_REPLY_DEFER:
3ff99164 464 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 465 udelay(100);
466 break;
467 default:
468 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
469 return -EREMOTEIO;
470 }
471 }
a4fc5ed6
KP		 472}
473
474static int
55f78c43
ZW		 475intel_dp_i2c_init(struct intel_encoder *intel_encoder,
476 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 477{
21d40d37 478 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 479
d54e9d28 480 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 481 dp_priv->algo.running = false;
482 dp_priv->algo.address = 0;
483 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
484
485 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
486 dp_priv->adapter.owner = THIS_MODULE;
487 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 488 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
489 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6 490 dp_priv->adapter.algo_data = &dp_priv->algo;
55f78c43 491 dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
a4fc5ed6
KP		 492
493 return i2c_dp_aux_add_bus(&dp_priv->adapter);
494}
495
496static bool
497intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
498 struct drm_display_mode *adjusted_mode)
499{
21d40d37
EA		 500 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
501 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 502 int lane_count, clock;
21d40d37
EA		 503 int max_lane_count = intel_dp_max_lane_count(intel_encoder);
504 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
a4fc5ed6
KP		 505 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
506
507 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
508 for (clock = 0; clock <= max_clock; clock++) {
509 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
510
21d40d37 511 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
885a5fb5 512 <= link_avail) {
a4fc5ed6
KP		 513 dp_priv->link_bw = bws[clock];
514 dp_priv->lane_count = lane_count;
515 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
28c97730
ZY		 516 DRM_DEBUG_KMS("Display port link bw %02x lane "
517 "count %d clock %d\n",
a4fc5ed6
KP		 518 dp_priv->link_bw, dp_priv->lane_count,
519 adjusted_mode->clock);
520 return true;
521 }
522 }
523 }
524 return false;
525}
526
527struct intel_dp_m_n {
528 uint32_t tu;
529 uint32_t gmch_m;
530 uint32_t gmch_n;
531 uint32_t link_m;
532 uint32_t link_n;
533};
534
535static void
536intel_reduce_ratio(uint32_t *num, uint32_t *den)
537{
538 while (*num > 0xffffff || *den > 0xffffff) {
539 *num >>= 1;
540 *den >>= 1;
541 }
542}
543
544static void
545intel_dp_compute_m_n(int bytes_per_pixel,
546 int nlanes,
547 int pixel_clock,
548 int link_clock,
549 struct intel_dp_m_n *m_n)
550{
551 m_n->tu = 64;
552 m_n->gmch_m = pixel_clock * bytes_per_pixel;
553 m_n->gmch_n = link_clock * nlanes;
554 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
555 m_n->link_m = pixel_clock;
556 m_n->link_n = link_clock;
557 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
558}
559
560void
561intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
562 struct drm_display_mode *adjusted_mode)
563{
564 struct drm_device *dev = crtc->dev;
565 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 566 struct drm_encoder *encoder;
a4fc5ed6
KP		 567 struct drm_i915_private *dev_priv = dev->dev_private;
568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
569 int lane_count = 4;
570 struct intel_dp_m_n m_n;
571
572 /*
21d40d37 573 * Find the lane count in the intel_encoder private
a4fc5ed6 574 */
55f78c43
ZW		 575 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
576 struct intel_encoder *intel_encoder;
577 struct intel_dp_priv *dp_priv;
a4fc5ed6 578
d8201ab6 579 if (encoder->crtc != crtc)
a4fc5ed6
KP		 580 continue;
581
55f78c43
ZW		 582 intel_encoder = enc_to_intel_encoder(encoder);
583 dp_priv = intel_encoder->dev_priv;
584
21d40d37 585 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
a4fc5ed6
KP		 586 lane_count = dp_priv->lane_count;
587 break;
588 }
589 }
590
591 /*
592 * Compute the GMCH and Link ratios. The '3' here is
593 * the number of bytes_per_pixel post-LUT, which we always
594 * set up for 8-bits of R/G/B, or 3 bytes total.
595 */
596 intel_dp_compute_m_n(3, lane_count,
597 mode->clock, adjusted_mode->clock, &m_n);
598
c619eed4 599 if (HAS_PCH_SPLIT(dev)) {
5eb08b69
ZW		 600 if (intel_crtc->pipe == 0) {
601 I915_WRITE(TRANSA_DATA_M1,
602 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
603 m_n.gmch_m);
604 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
605 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
606 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
607 } else {
608 I915_WRITE(TRANSB_DATA_M1,
609 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
610 m_n.gmch_m);
611 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
612 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
613 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
614 }
a4fc5ed6 615 } else {
5eb08b69
ZW		 616 if (intel_crtc->pipe == 0) {
617 I915_WRITE(PIPEA_GMCH_DATA_M,
618 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
619 m_n.gmch_m);
620 I915_WRITE(PIPEA_GMCH_DATA_N,
621 m_n.gmch_n);
622 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
623 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
624 } else {
625 I915_WRITE(PIPEB_GMCH_DATA_M,
626 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
627 m_n.gmch_m);
628 I915_WRITE(PIPEB_GMCH_DATA_N,
629 m_n.gmch_n);
630 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
631 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
632 }
a4fc5ed6
KP		 633 }
634}
635
636static void
637intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
638 struct drm_display_mode *adjusted_mode)
639{
e3421a18 640 struct drm_device *dev = encoder->dev;
21d40d37
EA		 641 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
642 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
643 struct drm_crtc *crtc = intel_encoder->enc.crtc;
a4fc5ed6
KP		 644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
645
e3421a18 646 dp_priv->DP = (DP_VOLTAGE_0_4 |
9c9e7927
AJ		 647 DP_PRE_EMPHASIS_0);
648
649 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
650 dp_priv->DP |= DP_SYNC_HS_HIGH;
651 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
652 dp_priv->DP |= DP_SYNC_VS_HIGH;
a4fc5ed6 653
e3421a18
ZW		 654 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
655 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
656 else
657 dp_priv->DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 658
659 switch (dp_priv->lane_count) {
660 case 1:
661 dp_priv->DP |= DP_PORT_WIDTH_1;
662 break;
663 case 2:
664 dp_priv->DP |= DP_PORT_WIDTH_2;
665 break;
666 case 4:
667 dp_priv->DP |= DP_PORT_WIDTH_4;
668 break;
669 }
670 if (dp_priv->has_audio)
671 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
672
673 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
674 dp_priv->link_configuration[0] = dp_priv->link_bw;
675 dp_priv->link_configuration[1] = dp_priv->lane_count;
676
677 /*
9962c925 678 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 679 */
9962c925 680 if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
a4fc5ed6
KP		 681 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
682 dp_priv->DP |= DP_ENHANCED_FRAMING;
683 }
684
e3421a18
ZW		 685 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
686 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
a4fc5ed6 687 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658 688
21d40d37 689 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 690 /* don't miss out required setting for eDP */
691 dp_priv->DP |= DP_PLL_ENABLE;
692 if (adjusted_mode->clock < 200000)
693 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
694 else
695 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
696 }
a4fc5ed6
KP		 697}
698
f2b115e6 699static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 700{
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 u32 pp;
703
28c97730 704 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 705 pp = I915_READ(PCH_PP_CONTROL);
706 pp |= EDP_BLC_ENABLE;
707 I915_WRITE(PCH_PP_CONTROL, pp);
708}
709
f2b115e6 710static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 711{
712 struct drm_i915_private *dev_priv = dev->dev_private;
713 u32 pp;
714
28c97730 715 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 716 pp = I915_READ(PCH_PP_CONTROL);
717 pp &= ~EDP_BLC_ENABLE;
718 I915_WRITE(PCH_PP_CONTROL, pp);
719}
a4fc5ed6
KP		 720
721static void
722intel_dp_dpms(struct drm_encoder *encoder, int mode)
723{
21d40d37
EA		 724 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
725 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
55f78c43 726 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 727 struct drm_i915_private *dev_priv = dev->dev_private;
728 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
729
730 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 731 if (dp_reg & DP_PORT_EN) {
21d40d37
EA		 732 intel_dp_link_down(intel_encoder, dp_priv->DP);
733 if (IS_eDP(intel_encoder))
f2b115e6 734 ironlake_edp_backlight_off(dev);
32f9d658 735 }
a4fc5ed6 736 } else {
32f9d658 737 if (!(dp_reg & DP_PORT_EN)) {
21d40d37
EA		 738 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
739 if (IS_eDP(intel_encoder))
f2b115e6 740 ironlake_edp_backlight_on(dev);
32f9d658 741 }
a4fc5ed6 742 }
c8110e52 743 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 744}
745
746/*
747 * Fetch AUX CH registers 0x202 - 0x207 which contain
748 * link status information
749 */
750static bool
21d40d37 751intel_dp_get_link_status(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 752 uint8_t link_status[DP_LINK_STATUS_SIZE])
753{
754 int ret;
755
21d40d37 756 ret = intel_dp_aux_native_read(intel_encoder,
a4fc5ed6
KP		 757 DP_LANE0_1_STATUS,
758 link_status, DP_LINK_STATUS_SIZE);
759 if (ret != DP_LINK_STATUS_SIZE)
760 return false;
761 return true;
762}
763
764static uint8_t
765intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
766 int r)
767{
768 return link_status[r - DP_LANE0_1_STATUS];
769}
770
a4fc5ed6
KP		 771static uint8_t
772intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
773 int lane)
774{
775 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
776 int s = ((lane & 1) ?
777 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
778 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
779 uint8_t l = intel_dp_link_status(link_status, i);
780
781 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
782}
783
784static uint8_t
785intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
786 int lane)
787{
788 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
789 int s = ((lane & 1) ?
790 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
791 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
792 uint8_t l = intel_dp_link_status(link_status, i);
793
794 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
795}
796
797
798#if 0
799static char *voltage_names[] = {
800 "0.4V", "0.6V", "0.8V", "1.2V"
801};
802static char *pre_emph_names[] = {
803 "0dB", "3.5dB", "6dB", "9.5dB"
804};
805static char *link_train_names[] = {
806 "pattern 1", "pattern 2", "idle", "off"
807};
808#endif
809
810/*
811 * These are source-specific values; current Intel hardware supports
812 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
813 */
814#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
815
816static uint8_t
817intel_dp_pre_emphasis_max(uint8_t voltage_swing)
818{
819 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
820 case DP_TRAIN_VOLTAGE_SWING_400:
821 return DP_TRAIN_PRE_EMPHASIS_6;
822 case DP_TRAIN_VOLTAGE_SWING_600:
823 return DP_TRAIN_PRE_EMPHASIS_6;
824 case DP_TRAIN_VOLTAGE_SWING_800:
825 return DP_TRAIN_PRE_EMPHASIS_3_5;
826 case DP_TRAIN_VOLTAGE_SWING_1200:
827 default:
828 return DP_TRAIN_PRE_EMPHASIS_0;
829 }
830}
831
832static void
21d40d37 833intel_get_adjust_train(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 834 uint8_t link_status[DP_LINK_STATUS_SIZE],
835 int lane_count,
836 uint8_t train_set[4])
837{
838 uint8_t v = 0;
839 uint8_t p = 0;
840 int lane;
841
842 for (lane = 0; lane < lane_count; lane++) {
843 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
844 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
845
846 if (this_v > v)
847 v = this_v;
848 if (this_p > p)
849 p = this_p;
850 }
851
852 if (v >= I830_DP_VOLTAGE_MAX)
853 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
854
855 if (p >= intel_dp_pre_emphasis_max(v))
856 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
857
858 for (lane = 0; lane < 4; lane++)
859 train_set[lane] = v | p;
860}
861
862static uint32_t
863intel_dp_signal_levels(uint8_t train_set, int lane_count)
864{
865 uint32_t signal_levels = 0;
866
867 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
868 case DP_TRAIN_VOLTAGE_SWING_400:
869 default:
870 signal_levels |= DP_VOLTAGE_0_4;
871 break;
872 case DP_TRAIN_VOLTAGE_SWING_600:
873 signal_levels |= DP_VOLTAGE_0_6;
874 break;
875 case DP_TRAIN_VOLTAGE_SWING_800:
876 signal_levels |= DP_VOLTAGE_0_8;
877 break;
878 case DP_TRAIN_VOLTAGE_SWING_1200:
879 signal_levels |= DP_VOLTAGE_1_2;
880 break;
881 }
882 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
883 case DP_TRAIN_PRE_EMPHASIS_0:
884 default:
885 signal_levels |= DP_PRE_EMPHASIS_0;
886 break;
887 case DP_TRAIN_PRE_EMPHASIS_3_5:
888 signal_levels |= DP_PRE_EMPHASIS_3_5;
889 break;
890 case DP_TRAIN_PRE_EMPHASIS_6:
891 signal_levels |= DP_PRE_EMPHASIS_6;
892 break;
893 case DP_TRAIN_PRE_EMPHASIS_9_5:
894 signal_levels |= DP_PRE_EMPHASIS_9_5;
895 break;
896 }
897 return signal_levels;
898}
899
e3421a18
ZW		 900/* Gen6's DP voltage swing and pre-emphasis control */
901static uint32_t
902intel_gen6_edp_signal_levels(uint8_t train_set)
903{
904 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
905 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
906 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
907 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
908 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
909 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
910 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
911 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
912 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
913 default:
914 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
915 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
916 }
917}
918
a4fc5ed6
KP		 919static uint8_t
920intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
921 int lane)
922{
923 int i = DP_LANE0_1_STATUS + (lane >> 1);
924 int s = (lane & 1) * 4;
925 uint8_t l = intel_dp_link_status(link_status, i);
926
927 return (l >> s) & 0xf;
928}
929
930/* Check for clock recovery is done on all channels */
931static bool
932intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
933{
934 int lane;
935 uint8_t lane_status;
936
937 for (lane = 0; lane < lane_count; lane++) {
938 lane_status = intel_get_lane_status(link_status, lane);
939 if ((lane_status & DP_LANE_CR_DONE) == 0)
940 return false;
941 }
942 return true;
943}
944
945/* Check to see if channel eq is done on all channels */
946#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
947 DP_LANE_CHANNEL_EQ_DONE|\
948 DP_LANE_SYMBOL_LOCKED)
949static bool
950intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
951{
952 uint8_t lane_align;
953 uint8_t lane_status;
954 int lane;
955
956 lane_align = intel_dp_link_status(link_status,
957 DP_LANE_ALIGN_STATUS_UPDATED);
958 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
959 return false;
960 for (lane = 0; lane < lane_count; lane++) {
961 lane_status = intel_get_lane_status(link_status, lane);
962 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
963 return false;
964 }
965 return true;
966}
967
968static bool
21d40d37 969intel_dp_set_link_train(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 970 uint32_t dp_reg_value,
971 uint8_t dp_train_pat,
972 uint8_t train_set[4],
973 bool first)
974{
55f78c43 975 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 976 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 977 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 978 int ret;
979
980 I915_WRITE(dp_priv->output_reg, dp_reg_value);
981 POSTING_READ(dp_priv->output_reg);
982 if (first)
983 intel_wait_for_vblank(dev);
984
21d40d37 985 intel_dp_aux_native_write_1(intel_encoder,
a4fc5ed6
KP		 986 DP_TRAINING_PATTERN_SET,
987 dp_train_pat);
988
21d40d37 989 ret = intel_dp_aux_native_write(intel_encoder,
a4fc5ed6
KP		 990 DP_TRAINING_LANE0_SET, train_set, 4);
991 if (ret != 4)
992 return false;
993
994 return true;
995}
996
997static void
21d40d37 998intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
a4fc5ed6
KP		 999 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1000{
55f78c43 1001 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1002 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1003 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1004 uint8_t train_set[4];
1005 uint8_t link_status[DP_LINK_STATUS_SIZE];
1006 int i;
1007 uint8_t voltage;
1008 bool clock_recovery = false;
1009 bool channel_eq = false;
1010 bool first = true;
1011 int tries;
e3421a18 1012 u32 reg;
a4fc5ed6
KP		 1013
1014 /* Write the link configuration data */
ab00a9ef 1015 intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
a4fc5ed6
KP		 1016 link_configuration, DP_LINK_CONFIGURATION_SIZE);
1017
1018 DP |= DP_PORT_EN;
e3421a18
ZW		 1019 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1020 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1021 else
1022 DP &= ~DP_LINK_TRAIN_MASK;
a4fc5ed6
KP		 1023 memset(train_set, 0, 4);
1024 voltage = 0xff;
1025 tries = 0;
1026 clock_recovery = false;
1027 for (;;) {
1028 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1029 uint32_t signal_levels;
1030 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1031 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1032 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1033 } else {
1034 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1035 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1036 }
a4fc5ed6 1037
e3421a18
ZW		 1038 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1039 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1040 else
1041 reg = DP | DP_LINK_TRAIN_PAT_1;
1042
1043 if (!intel_dp_set_link_train(intel_encoder, reg,
a4fc5ed6
KP		 1044 DP_TRAINING_PATTERN_1, train_set, first))
1045 break;
1046 first = false;
1047 /* Set training pattern 1 */
1048
1049 udelay(100);
21d40d37 1050 if (!intel_dp_get_link_status(intel_encoder, link_status))
a4fc5ed6
KP		 1051 break;
1052
1053 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1054 clock_recovery = true;
1055 break;
1056 }
1057
1058 /* Check to see if we've tried the max voltage */
1059 for (i = 0; i < dp_priv->lane_count; i++)
1060 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1061 break;
1062 if (i == dp_priv->lane_count)
1063 break;
1064
1065 /* Check to see if we've tried the same voltage 5 times */
1066 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1067 ++tries;
1068 if (tries == 5)
1069 break;
1070 } else
1071 tries = 0;
1072 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1073
1074 /* Compute new train_set as requested by target */
21d40d37 1075 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
a4fc5ed6
KP		 1076 }
1077
1078 /* channel equalization */
1079 tries = 0;
1080 channel_eq = false;
1081 for (;;) {
1082 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1083 uint32_t signal_levels;
1084
1085 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1086 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1087 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1088 } else {
1089 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1090 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1091 }
1092
1093 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1094 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1095 else
1096 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1097
1098 /* channel eq pattern */
e3421a18 1099 if (!intel_dp_set_link_train(intel_encoder, reg,
a4fc5ed6
KP		 1100 DP_TRAINING_PATTERN_2, train_set,
1101 false))
1102 break;
1103
1104 udelay(400);
21d40d37 1105 if (!intel_dp_get_link_status(intel_encoder, link_status))
a4fc5ed6
KP		 1106 break;
1107
1108 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1109 channel_eq = true;
1110 break;
1111 }
1112
1113 /* Try 5 times */
1114 if (tries > 5)
1115 break;
1116
1117 /* Compute new train_set as requested by target */
21d40d37 1118 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
a4fc5ed6
KP		 1119 ++tries;
1120 }
1121
e3421a18
ZW		 1122 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1123 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1124 else
1125 reg = DP | DP_LINK_TRAIN_OFF;
1126
1127 I915_WRITE(dp_priv->output_reg, reg);
a4fc5ed6 1128 POSTING_READ(dp_priv->output_reg);
21d40d37 1129 intel_dp_aux_native_write_1(intel_encoder,
a4fc5ed6
KP		 1130 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1131}
1132
1133static void
21d40d37 1134intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
a4fc5ed6 1135{
55f78c43 1136 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1137 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1138 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 1139
28c97730 1140 DRM_DEBUG_KMS("\n");
32f9d658 1141
21d40d37 1142 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 1143 DP &= ~DP_PLL_ENABLE;
1144 I915_WRITE(dp_priv->output_reg, DP);
1145 POSTING_READ(dp_priv->output_reg);
1146 udelay(100);
1147 }
1148
e3421a18
ZW		 1149 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1150 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1151 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1152 POSTING_READ(dp_priv->output_reg);
1153 } else {
1154 DP &= ~DP_LINK_TRAIN_MASK;
1155 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1156 POSTING_READ(dp_priv->output_reg);
1157 }
5eb08b69
ZW		 1158
1159 udelay(17000);
1160
21d40d37 1161 if (IS_eDP(intel_encoder))
32f9d658 1162 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1163 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1164 POSTING_READ(dp_priv->output_reg);
1165}
1166
a4fc5ed6
KP		 1167/*
1168 * According to DP spec
1169 * 5.1.2:
1170 * 1. Read DPCD
1171 * 2. Configure link according to Receiver Capabilities
1172 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1173 * 4. Check link status on receipt of hot-plug interrupt
1174 */
1175
1176static void
21d40d37 1177intel_dp_check_link_status(struct intel_encoder *intel_encoder)
a4fc5ed6 1178{
21d40d37 1179 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1180 uint8_t link_status[DP_LINK_STATUS_SIZE];
1181
21d40d37 1182 if (!intel_encoder->enc.crtc)
a4fc5ed6
KP		 1183 return;
1184
21d40d37
EA		 1185 if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1186 intel_dp_link_down(intel_encoder, dp_priv->DP);
a4fc5ed6
KP		 1187 return;
1188 }
1189
1190 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
21d40d37 1191 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
a4fc5ed6 1192}
a4fc5ed6 1193
5eb08b69 1194static enum drm_connector_status
f2b115e6 1195ironlake_dp_detect(struct drm_connector *connector)
5eb08b69 1196{
55f78c43
ZW		 1197 struct drm_encoder *encoder = intel_attached_encoder(connector);
1198 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37 1199 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
5eb08b69
ZW		 1200 enum drm_connector_status status;
1201
1202 status = connector_status_disconnected;
21d40d37 1203 if (intel_dp_aux_native_read(intel_encoder,
5eb08b69
ZW		 1204 0x000, dp_priv->dpcd,
1205 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1206 {
1207 if (dp_priv->dpcd[0] != 0)
1208 status = connector_status_connected;
1209 }
a7de64e5
AJ		 1210 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0],
1211 dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]);
5eb08b69
ZW		 1212 return status;
1213}
1214
a4fc5ed6
KP		 1215/**
1216 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1217 *
1218 * \return true if DP port is connected.
1219 * \return false if DP port is disconnected.
1220 */
1221static enum drm_connector_status
1222intel_dp_detect(struct drm_connector *connector)
1223{
55f78c43
ZW		 1224 struct drm_encoder *encoder = intel_attached_encoder(connector);
1225 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1226 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1227 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1228 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1229 uint32_t temp, bit;
1230 enum drm_connector_status status;
1231
1232 dp_priv->has_audio = false;
1233
c619eed4 1234 if (HAS_PCH_SPLIT(dev))
f2b115e6 1235 return ironlake_dp_detect(connector);
5eb08b69 1236
a4fc5ed6
KP		 1237 switch (dp_priv->output_reg) {
1238 case DP_B:
1239 bit = DPB_HOTPLUG_INT_STATUS;
1240 break;
1241 case DP_C:
1242 bit = DPC_HOTPLUG_INT_STATUS;
1243 break;
1244 case DP_D:
1245 bit = DPD_HOTPLUG_INT_STATUS;
1246 break;
1247 default:
1248 return connector_status_unknown;
1249 }
1250
1251 temp = I915_READ(PORT_HOTPLUG_STAT);
1252
1253 if ((temp & bit) == 0)
1254 return connector_status_disconnected;
1255
1256 status = connector_status_disconnected;
21d40d37 1257 if (intel_dp_aux_native_read(intel_encoder,
a4fc5ed6
KP		 1258 0x000, dp_priv->dpcd,
1259 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1260 {
1261 if (dp_priv->dpcd[0] != 0)
1262 status = connector_status_connected;
1263 }
1264 return status;
1265}
1266
1267static int intel_dp_get_modes(struct drm_connector *connector)
1268{
55f78c43
ZW		 1269 struct drm_encoder *encoder = intel_attached_encoder(connector);
1270 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1271 struct drm_device *dev = intel_encoder->enc.dev;
32f9d658
ZW		 1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 int ret;
a4fc5ed6
KP		 1274
1275 /* We should parse the EDID data and find out if it has an audio sink
1276 */
1277
335af9a2 1278 ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
32f9d658
ZW		 1279 if (ret)
1280 return ret;
1281
1282 /* if eDP has no EDID, try to use fixed panel mode from VBT */
21d40d37 1283 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 1284 if (dev_priv->panel_fixed_mode != NULL) {
1285 struct drm_display_mode *mode;
1286 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1287 drm_mode_probed_add(connector, mode);
1288 return 1;
1289 }
1290 }
1291 return 0;
a4fc5ed6
KP		 1292}
1293
1294static void
1295intel_dp_destroy (struct drm_connector *connector)
1296{
a4fc5ed6
KP		 1297 drm_sysfs_connector_remove(connector);
1298 drm_connector_cleanup(connector);
55f78c43 1299 kfree(connector);
a4fc5ed6
KP		 1300}
1301
1302static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1303 .dpms = intel_dp_dpms,
1304 .mode_fixup = intel_dp_mode_fixup,
1305 .prepare = intel_encoder_prepare,
1306 .mode_set = intel_dp_mode_set,
1307 .commit = intel_encoder_commit,
1308};
1309
1310static const struct drm_connector_funcs intel_dp_connector_funcs = {
1311 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 1312 .detect = intel_dp_detect,
1313 .fill_modes = drm_helper_probe_single_connector_modes,
1314 .destroy = intel_dp_destroy,
1315};
1316
1317static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1318 .get_modes = intel_dp_get_modes,
1319 .mode_valid = intel_dp_mode_valid,
55f78c43 1320 .best_encoder = intel_attached_encoder,
a4fc5ed6
KP		 1321};
1322
1323static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1324{
55f78c43
ZW		 1325 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1326
1327 if (intel_encoder->i2c_bus)
1328 intel_i2c_destroy(intel_encoder->i2c_bus);
a4fc5ed6 1329 drm_encoder_cleanup(encoder);
55f78c43 1330 kfree(intel_encoder);
a4fc5ed6
KP		 1331}
1332
1333static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1334 .destroy = intel_dp_enc_destroy,
1335};
1336
c8110e52 1337void
21d40d37 1338intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 1339{
21d40d37 1340 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
c8110e52
KP		 1341
1342 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
21d40d37 1343 intel_dp_check_link_status(intel_encoder);
c8110e52 1344}
6207937d 1345
e3421a18
ZW		 1346/* Return which DP Port should be selected for Transcoder DP control */
1347int
1348intel_trans_dp_port_sel (struct drm_crtc *crtc)
1349{
1350 struct drm_device *dev = crtc->dev;
1351 struct drm_mode_config *mode_config = &dev->mode_config;
1352 struct drm_encoder *encoder;
1353 struct intel_encoder *intel_encoder = NULL;
1354
1355 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
d8201ab6 1356 if (encoder->crtc != crtc)
e3421a18
ZW		 1357 continue;
1358
1359 intel_encoder = enc_to_intel_encoder(encoder);
1360 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1361 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1362 return dp_priv->output_reg;
1363 }
1364 }
1365 return -1;
1366}
1367
a4fc5ed6
KP		 1368void
1369intel_dp_init(struct drm_device *dev, int output_reg)
1370{
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 struct drm_connector *connector;
21d40d37 1373 struct intel_encoder *intel_encoder;
55f78c43 1374 struct intel_connector *intel_connector;
a4fc5ed6 1375 struct intel_dp_priv *dp_priv;
5eb08b69 1376 const char *name = NULL;
a4fc5ed6 1377
21d40d37 1378 intel_encoder = kcalloc(sizeof(struct intel_encoder) +
a4fc5ed6 1379 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
21d40d37 1380 if (!intel_encoder)
a4fc5ed6
KP		 1381 return;
1382
55f78c43
ZW		 1383 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1384 if (!intel_connector) {
1385 kfree(intel_encoder);
1386 return;
1387 }
1388
21d40d37 1389 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
a4fc5ed6 1390
55f78c43 1391 connector = &intel_connector->base;
a4fc5ed6
KP		 1392 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1393 DRM_MODE_CONNECTOR_DisplayPort);
1394 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1395
eb1f8e4f
DA		 1396 connector->polled = DRM_CONNECTOR_POLL_HPD;
1397
32f9d658 1398 if (output_reg == DP_A)
21d40d37 1399 intel_encoder->type = INTEL_OUTPUT_EDP;
32f9d658 1400 else
21d40d37 1401 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a4fc5ed6 1402
652af9d7 1403 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 1404 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1405 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 1406 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1407 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 1408 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 1409
21d40d37
EA		 1410 if (IS_eDP(intel_encoder))
1411 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a 1412
21d40d37 1413 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1414 connector->interlace_allowed = true;
1415 connector->doublescan_allowed = 0;
1416
21d40d37 1417 dp_priv->intel_encoder = intel_encoder;
a4fc5ed6
KP		 1418 dp_priv->output_reg = output_reg;
1419 dp_priv->has_audio = false;
c8110e52 1420 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
21d40d37 1421 intel_encoder->dev_priv = dp_priv;
a4fc5ed6 1422
21d40d37 1423 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
a4fc5ed6 1424 DRM_MODE_ENCODER_TMDS);
21d40d37 1425 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
a4fc5ed6 1426
55f78c43 1427 drm_mode_connector_attach_encoder(&intel_connector->base,
21d40d37 1428 &intel_encoder->enc);
a4fc5ed6
KP		 1429 drm_sysfs_connector_add(connector);
1430
1431 /* Set up the DDC bus. */
5eb08b69 1432 switch (output_reg) {
32f9d658
ZW		 1433 case DP_A:
1434 name = "DPDDC-A";
1435 break;
5eb08b69
ZW		 1436 case DP_B:
1437 case PCH_DP_B:
b01f2c3a
JB		 1438 dev_priv->hotplug_supported_mask |=
1439 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1440 name = "DPDDC-B";
1441 break;
1442 case DP_C:
1443 case PCH_DP_C:
b01f2c3a
JB		 1444 dev_priv->hotplug_supported_mask |=
1445 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1446 name = "DPDDC-C";
1447 break;
1448 case DP_D:
1449 case PCH_DP_D:
b01f2c3a
JB		 1450 dev_priv->hotplug_supported_mask |=
1451 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1452 name = "DPDDC-D";
1453 break;
1454 }
1455
55f78c43 1456 intel_dp_i2c_init(intel_encoder, intel_connector, name);
32f9d658 1457
21d40d37
EA		 1458 intel_encoder->ddc_bus = &dp_priv->adapter;
1459 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1460
32f9d658
ZW		 1461 if (output_reg == DP_A) {
1462 /* initialize panel mode from VBT if available for eDP */
1463 if (dev_priv->lfp_lvds_vbt_mode) {
1464 dev_priv->panel_fixed_mode =
1465 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1466 if (dev_priv->panel_fixed_mode) {
1467 dev_priv->panel_fixed_mode->type |=
1468 DRM_MODE_TYPE_PREFERRED;
1469 }
1470 }
1471 }
1472
a4fc5ed6
KP		 1473 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1474 * 0xd. Failure to do so will result in spurious interrupts being
1475 * generated on the port when a cable is not attached.
1476 */
1477 if (IS_G4X(dev) && !IS_GM45(dev)) {
1478 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1479 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1480 }
1481}
Clone of davem's net-next-2.6 tree