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Merge branch 'drm-core-next' into drm-linus
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include "drmP.h"
30#include "drm.h"
31#include "drm_crtc.h"
32#include "drm_crtc_helper.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
ab2c0672 36#include "drm_dp_helper.h"
a4fc5ed6
KP		 37
38#define DP_LINK_STATUS_SIZE 6
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41#define DP_LINK_CONFIGURATION_SIZE 9
42
32f9d658
ZW		 43#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
44
a4fc5ed6
KP		 45struct intel_dp_priv {
46 uint32_t output_reg;
47 uint32_t DP;
48 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
49 uint32_t save_DP;
50 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
51 bool has_audio;
c8110e52 52 int dpms_mode;
a4fc5ed6
KP		 53 uint8_t link_bw;
54 uint8_t lane_count;
55 uint8_t dpcd[4];
56 struct intel_output *intel_output;
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59};
60
61static void
62intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
63 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
64
65static void
66intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
67
32f9d658
ZW		 68void
69intel_edp_link_config (struct intel_output *intel_output,
70 int *lane_num, int *link_bw)
71{
72 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
73
74 *lane_num = dp_priv->lane_count;
75 if (dp_priv->link_bw == DP_LINK_BW_1_62)
76 *link_bw = 162000;
77 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
78 *link_bw = 270000;
79}
80
a4fc5ed6
KP		 81static int
82intel_dp_max_lane_count(struct intel_output *intel_output)
83{
84 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
85 int max_lane_count = 4;
86
87 if (dp_priv->dpcd[0] >= 0x11) {
88 max_lane_count = dp_priv->dpcd[2] & 0x1f;
89 switch (max_lane_count) {
90 case 1: case 2: case 4:
91 break;
92 default:
93 max_lane_count = 4;
94 }
95 }
96 return max_lane_count;
97}
98
99static int
100intel_dp_max_link_bw(struct intel_output *intel_output)
101{
102 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
103 int max_link_bw = dp_priv->dpcd[1];
104
105 switch (max_link_bw) {
106 case DP_LINK_BW_1_62:
107 case DP_LINK_BW_2_7:
108 break;
109 default:
110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
116static int
117intel_dp_link_clock(uint8_t link_bw)
118{
119 if (link_bw == DP_LINK_BW_2_7)
120 return 270000;
121 else
122 return 162000;
123}
124
125/* I think this is a fiction */
126static int
127intel_dp_link_required(int pixel_clock)
128{
129 return pixel_clock * 3;
130}
131
132static int
133intel_dp_mode_valid(struct drm_connector *connector,
134 struct drm_display_mode *mode)
135{
136 struct intel_output *intel_output = to_intel_output(connector);
137 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
138 int max_lanes = intel_dp_max_lane_count(intel_output);
139
140 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
141 return MODE_CLOCK_HIGH;
142
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
145
146 return MODE_OK;
147}
148
149static uint32_t
150pack_aux(uint8_t *src, int src_bytes)
151{
152 int i;
153 uint32_t v = 0;
154
155 if (src_bytes > 4)
156 src_bytes = 4;
157 for (i = 0; i < src_bytes; i++)
158 v |= ((uint32_t) src[i]) << ((3-i) * 8);
159 return v;
160}
161
162static void
163unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
164{
165 int i;
166 if (dst_bytes > 4)
167 dst_bytes = 4;
168 for (i = 0; i < dst_bytes; i++)
169 dst[i] = src >> ((3-i) * 8);
170}
171
fb0f8fbf
KP		 172/* hrawclock is 1/4 the FSB frequency */
173static int
174intel_hrawclk(struct drm_device *dev)
175{
176 struct drm_i915_private *dev_priv = dev->dev_private;
177 uint32_t clkcfg;
178
179 clkcfg = I915_READ(CLKCFG);
180 switch (clkcfg & CLKCFG_FSB_MASK) {
181 case CLKCFG_FSB_400:
182 return 100;
183 case CLKCFG_FSB_533:
184 return 133;
185 case CLKCFG_FSB_667:
186 return 166;
187 case CLKCFG_FSB_800:
188 return 200;
189 case CLKCFG_FSB_1067:
190 return 266;
191 case CLKCFG_FSB_1333:
192 return 333;
193 /* these two are just a guess; one of them might be right */
194 case CLKCFG_FSB_1600:
195 case CLKCFG_FSB_1600_ALT:
196 return 400;
197 default:
198 return 133;
199 }
200}
201
a4fc5ed6
KP		 202static int
203intel_dp_aux_ch(struct intel_output *intel_output,
204 uint8_t *send, int send_bytes,
205 uint8_t *recv, int recv_size)
206{
207 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
208 uint32_t output_reg = dp_priv->output_reg;
209 struct drm_device *dev = intel_output->base.dev;
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t ch_ctl = output_reg + 0x10;
212 uint32_t ch_data = ch_ctl + 4;
213 int i;
214 int recv_bytes;
215 uint32_t ctl;
216 uint32_t status;
fb0f8fbf
KP		 217 uint32_t aux_clock_divider;
218 int try;
a4fc5ed6
KP		 219
220 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 221 * and would like to run at 2MHz. So, take the
222 * hrawclk value and divide by 2 and use that
a4fc5ed6 223 */
32f9d658
ZW		 224 if (IS_eDP(intel_output))
225 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
226 else if (IS_IGDNG(dev))
227 aux_clock_divider = 62; /* IGDNG: input clock fixed at 125Mhz */
5eb08b69
ZW		 228 else
229 aux_clock_divider = intel_hrawclk(dev) / 2;
230
fb0f8fbf
KP		 231 /* Must try at least 3 times according to DP spec */
232 for (try = 0; try < 5; try++) {
233 /* Load the send data into the aux channel data registers */
234 for (i = 0; i < send_bytes; i += 4) {
a419aef8 235 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 236
237 I915_WRITE(ch_data + i, d);
238 }
239
240 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
241 DP_AUX_CH_CTL_TIME_OUT_400us |
242 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
243 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
244 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
245 DP_AUX_CH_CTL_DONE |
246 DP_AUX_CH_CTL_TIME_OUT_ERROR |
247 DP_AUX_CH_CTL_RECEIVE_ERROR);
248
249 /* Send the command and wait for it to complete */
250 I915_WRITE(ch_ctl, ctl);
251 (void) I915_READ(ch_ctl);
252 for (;;) {
253 udelay(100);
254 status = I915_READ(ch_ctl);
255 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
256 break;
257 }
258
259 /* Clear done status and any errors */
eebc863e 260 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 261 DP_AUX_CH_CTL_DONE |
262 DP_AUX_CH_CTL_TIME_OUT_ERROR |
263 DP_AUX_CH_CTL_RECEIVE_ERROR));
264 (void) I915_READ(ch_ctl);
265 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 266 break;
267 }
268
a4fc5ed6 269 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 270 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 271 return -EBUSY;
a4fc5ed6
KP		 272 }
273
274 /* Check for timeout or receive error.
275 * Timeouts occur when the sink is not connected
276 */
a5b3da54 277 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 278 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 279 return -EIO;
280 }
1ae8c0a5
KP		 281
282 /* Timeouts occur when the device isn't connected, so they're
283 * "normal" -- don't fill the kernel log with these */
a5b3da54 284 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1ae8c0a5 285 DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 286 return -ETIMEDOUT;
a4fc5ed6
KP		 287 }
288
289 /* Unload any bytes sent back from the other side */
290 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
291 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
292
293 if (recv_bytes > recv_size)
294 recv_bytes = recv_size;
295
296 for (i = 0; i < recv_bytes; i += 4) {
297 uint32_t d = I915_READ(ch_data + i);
298
299 unpack_aux(d, recv + i, recv_bytes - i);
300 }
301
302 return recv_bytes;
303}
304
305/* Write data to the aux channel in native mode */
306static int
307intel_dp_aux_native_write(struct intel_output *intel_output,
308 uint16_t address, uint8_t *send, int send_bytes)
309{
310 int ret;
311 uint8_t msg[20];
312 int msg_bytes;
313 uint8_t ack;
314
315 if (send_bytes > 16)
316 return -1;
317 msg[0] = AUX_NATIVE_WRITE << 4;
318 msg[1] = address >> 8;
eebc863e 319 msg[2] = address & 0xff;
a4fc5ed6
KP		 320 msg[3] = send_bytes - 1;
321 memcpy(&msg[4], send, send_bytes);
322 msg_bytes = send_bytes + 4;
323 for (;;) {
324 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
325 if (ret < 0)
326 return ret;
327 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
328 break;
329 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
330 udelay(100);
331 else
a5b3da54 332 return -EIO;
a4fc5ed6
KP		 333 }
334 return send_bytes;
335}
336
337/* Write a single byte to the aux channel in native mode */
338static int
339intel_dp_aux_native_write_1(struct intel_output *intel_output,
340 uint16_t address, uint8_t byte)
341{
342 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
343}
344
345/* read bytes from a native aux channel */
346static int
347intel_dp_aux_native_read(struct intel_output *intel_output,
348 uint16_t address, uint8_t *recv, int recv_bytes)
349{
350 uint8_t msg[4];
351 int msg_bytes;
352 uint8_t reply[20];
353 int reply_bytes;
354 uint8_t ack;
355 int ret;
356
357 msg[0] = AUX_NATIVE_READ << 4;
358 msg[1] = address >> 8;
359 msg[2] = address & 0xff;
360 msg[3] = recv_bytes - 1;
361
362 msg_bytes = 4;
363 reply_bytes = recv_bytes + 1;
364
365 for (;;) {
366 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
367 reply, reply_bytes);
a5b3da54
KP		 368 if (ret == 0)
369 return -EPROTO;
370 if (ret < 0)
a4fc5ed6
KP		 371 return ret;
372 ack = reply[0];
373 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
374 memcpy(recv, reply + 1, ret - 1);
375 return ret - 1;
376 }
377 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
378 udelay(100);
379 else
a5b3da54 380 return -EIO;
a4fc5ed6
KP		 381 }
382}
383
384static int
ab2c0672
DA		 385intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
386 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 387{
ab2c0672 388 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6
KP		 389 struct intel_dp_priv *dp_priv = container_of(adapter,
390 struct intel_dp_priv,
391 adapter);
392 struct intel_output *intel_output = dp_priv->intel_output;
ab2c0672
DA		 393 uint16_t address = algo_data->address;
394 uint8_t msg[5];
395 uint8_t reply[2];
396 int msg_bytes;
397 int reply_bytes;
398 int ret;
399
400 /* Set up the command byte */
401 if (mode & MODE_I2C_READ)
402 msg[0] = AUX_I2C_READ << 4;
403 else
404 msg[0] = AUX_I2C_WRITE << 4;
405
406 if (!(mode & MODE_I2C_STOP))
407 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 408
ab2c0672
DA		 409 msg[1] = address >> 8;
410 msg[2] = address;
411
412 switch (mode) {
413 case MODE_I2C_WRITE:
414 msg[3] = 0;
415 msg[4] = write_byte;
416 msg_bytes = 5;
417 reply_bytes = 1;
418 break;
419 case MODE_I2C_READ:
420 msg[3] = 0;
421 msg_bytes = 4;
422 reply_bytes = 2;
423 break;
424 default:
425 msg_bytes = 3;
426 reply_bytes = 1;
427 break;
428 }
429
430 for (;;) {
431 ret = intel_dp_aux_ch(intel_output,
432 msg, msg_bytes,
433 reply, reply_bytes);
434 if (ret < 0) {
435 DRM_DEBUG("aux_ch failed %d\n", ret);
436 return ret;
437 }
438 switch (reply[0] & AUX_I2C_REPLY_MASK) {
439 case AUX_I2C_REPLY_ACK:
440 if (mode == MODE_I2C_READ) {
441 *read_byte = reply[1];
442 }
443 return reply_bytes - 1;
444 case AUX_I2C_REPLY_NACK:
445 DRM_DEBUG("aux_ch nack\n");
446 return -EREMOTEIO;
447 case AUX_I2C_REPLY_DEFER:
448 DRM_DEBUG("aux_ch defer\n");
449 udelay(100);
450 break;
451 default:
452 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
453 return -EREMOTEIO;
454 }
455 }
a4fc5ed6
KP		 456}
457
458static int
459intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
460{
461 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
462
d54e9d28 463 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 464 dp_priv->algo.running = false;
465 dp_priv->algo.address = 0;
466 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
467
468 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
469 dp_priv->adapter.owner = THIS_MODULE;
470 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 471 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
472 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6
KP		 473 dp_priv->adapter.algo_data = &dp_priv->algo;
474 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
475
476 return i2c_dp_aux_add_bus(&dp_priv->adapter);
477}
478
479static bool
480intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
481 struct drm_display_mode *adjusted_mode)
482{
483 struct intel_output *intel_output = enc_to_intel_output(encoder);
484 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
485 int lane_count, clock;
486 int max_lane_count = intel_dp_max_lane_count(intel_output);
487 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
488 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
489
490 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
491 for (clock = 0; clock <= max_clock; clock++) {
492 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
493
494 if (intel_dp_link_required(mode->clock) <= link_avail) {
495 dp_priv->link_bw = bws[clock];
496 dp_priv->lane_count = lane_count;
497 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
1ae8c0a5 498 DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n",
a4fc5ed6
KP		 499 dp_priv->link_bw, dp_priv->lane_count,
500 adjusted_mode->clock);
501 return true;
502 }
503 }
504 }
505 return false;
506}
507
508struct intel_dp_m_n {
509 uint32_t tu;
510 uint32_t gmch_m;
511 uint32_t gmch_n;
512 uint32_t link_m;
513 uint32_t link_n;
514};
515
516static void
517intel_reduce_ratio(uint32_t *num, uint32_t *den)
518{
519 while (*num > 0xffffff || *den > 0xffffff) {
520 *num >>= 1;
521 *den >>= 1;
522 }
523}
524
525static void
526intel_dp_compute_m_n(int bytes_per_pixel,
527 int nlanes,
528 int pixel_clock,
529 int link_clock,
530 struct intel_dp_m_n *m_n)
531{
532 m_n->tu = 64;
533 m_n->gmch_m = pixel_clock * bytes_per_pixel;
534 m_n->gmch_n = link_clock * nlanes;
535 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
536 m_n->link_m = pixel_clock;
537 m_n->link_n = link_clock;
538 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
539}
540
541void
542intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
543 struct drm_display_mode *adjusted_mode)
544{
545 struct drm_device *dev = crtc->dev;
546 struct drm_mode_config *mode_config = &dev->mode_config;
547 struct drm_connector *connector;
548 struct drm_i915_private *dev_priv = dev->dev_private;
549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
550 int lane_count = 4;
551 struct intel_dp_m_n m_n;
552
553 /*
554 * Find the lane count in the intel_output private
555 */
556 list_for_each_entry(connector, &mode_config->connector_list, head) {
557 struct intel_output *intel_output = to_intel_output(connector);
558 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
559
560 if (!connector->encoder || connector->encoder->crtc != crtc)
561 continue;
562
563 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
564 lane_count = dp_priv->lane_count;
565 break;
566 }
567 }
568
569 /*
570 * Compute the GMCH and Link ratios. The '3' here is
571 * the number of bytes_per_pixel post-LUT, which we always
572 * set up for 8-bits of R/G/B, or 3 bytes total.
573 */
574 intel_dp_compute_m_n(3, lane_count,
575 mode->clock, adjusted_mode->clock, &m_n);
576
5eb08b69
ZW		 577 if (IS_IGDNG(dev)) {
578 if (intel_crtc->pipe == 0) {
579 I915_WRITE(TRANSA_DATA_M1,
580 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
581 m_n.gmch_m);
582 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
583 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
584 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
585 } else {
586 I915_WRITE(TRANSB_DATA_M1,
587 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
588 m_n.gmch_m);
589 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
590 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
591 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
592 }
a4fc5ed6 593 } else {
5eb08b69
ZW		 594 if (intel_crtc->pipe == 0) {
595 I915_WRITE(PIPEA_GMCH_DATA_M,
596 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
597 m_n.gmch_m);
598 I915_WRITE(PIPEA_GMCH_DATA_N,
599 m_n.gmch_n);
600 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
601 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
602 } else {
603 I915_WRITE(PIPEB_GMCH_DATA_M,
604 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
605 m_n.gmch_m);
606 I915_WRITE(PIPEB_GMCH_DATA_N,
607 m_n.gmch_n);
608 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
609 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
610 }
a4fc5ed6
KP		 611 }
612}
613
614static void
615intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
616 struct drm_display_mode *adjusted_mode)
617{
618 struct intel_output *intel_output = enc_to_intel_output(encoder);
619 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
620 struct drm_crtc *crtc = intel_output->enc.crtc;
621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
622
623 dp_priv->DP = (DP_LINK_TRAIN_OFF |
624 DP_VOLTAGE_0_4 |
625 DP_PRE_EMPHASIS_0 |
626 DP_SYNC_VS_HIGH |
627 DP_SYNC_HS_HIGH);
628
629 switch (dp_priv->lane_count) {
630 case 1:
631 dp_priv->DP |= DP_PORT_WIDTH_1;
632 break;
633 case 2:
634 dp_priv->DP |= DP_PORT_WIDTH_2;
635 break;
636 case 4:
637 dp_priv->DP |= DP_PORT_WIDTH_4;
638 break;
639 }
640 if (dp_priv->has_audio)
641 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
642
643 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
644 dp_priv->link_configuration[0] = dp_priv->link_bw;
645 dp_priv->link_configuration[1] = dp_priv->lane_count;
646
647 /*
648 * Check for DPCD version > 1.1,
649 * enable enahanced frame stuff in that case
650 */
651 if (dp_priv->dpcd[0] >= 0x11) {
652 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
653 dp_priv->DP |= DP_ENHANCED_FRAMING;
654 }
655
656 if (intel_crtc->pipe == 1)
657 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658
ZW		 658
659 if (IS_eDP(intel_output)) {
660 /* don't miss out required setting for eDP */
661 dp_priv->DP |= DP_PLL_ENABLE;
662 if (adjusted_mode->clock < 200000)
663 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
664 else
665 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
666 }
a4fc5ed6
KP		 667}
668
32f9d658
ZW		 669static void igdng_edp_backlight_on (struct drm_device *dev)
670{
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 u32 pp;
673
674 DRM_DEBUG("\n");
675 pp = I915_READ(PCH_PP_CONTROL);
676 pp |= EDP_BLC_ENABLE;
677 I915_WRITE(PCH_PP_CONTROL, pp);
678}
679
680static void igdng_edp_backlight_off (struct drm_device *dev)
681{
682 struct drm_i915_private *dev_priv = dev->dev_private;
683 u32 pp;
684
685 DRM_DEBUG("\n");
686 pp = I915_READ(PCH_PP_CONTROL);
687 pp &= ~EDP_BLC_ENABLE;
688 I915_WRITE(PCH_PP_CONTROL, pp);
689}
a4fc5ed6
KP		 690
691static void
692intel_dp_dpms(struct drm_encoder *encoder, int mode)
693{
694 struct intel_output *intel_output = enc_to_intel_output(encoder);
695 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
696 struct drm_device *dev = intel_output->base.dev;
697 struct drm_i915_private *dev_priv = dev->dev_private;
698 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
699
700 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 701 if (dp_reg & DP_PORT_EN) {
a4fc5ed6 702 intel_dp_link_down(intel_output, dp_priv->DP);
32f9d658
ZW		 703 if (IS_eDP(intel_output))
704 igdng_edp_backlight_off(dev);
705 }
a4fc5ed6 706 } else {
32f9d658 707 if (!(dp_reg & DP_PORT_EN)) {
a4fc5ed6 708 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
32f9d658
ZW		 709 if (IS_eDP(intel_output))
710 igdng_edp_backlight_on(dev);
711 }
a4fc5ed6 712 }
c8110e52 713 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 714}
715
716/*
717 * Fetch AUX CH registers 0x202 - 0x207 which contain
718 * link status information
719 */
720static bool
721intel_dp_get_link_status(struct intel_output *intel_output,
722 uint8_t link_status[DP_LINK_STATUS_SIZE])
723{
724 int ret;
725
726 ret = intel_dp_aux_native_read(intel_output,
727 DP_LANE0_1_STATUS,
728 link_status, DP_LINK_STATUS_SIZE);
729 if (ret != DP_LINK_STATUS_SIZE)
730 return false;
731 return true;
732}
733
734static uint8_t
735intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
736 int r)
737{
738 return link_status[r - DP_LANE0_1_STATUS];
739}
740
741static void
742intel_dp_save(struct drm_connector *connector)
743{
744 struct intel_output *intel_output = to_intel_output(connector);
745 struct drm_device *dev = intel_output->base.dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
748
749 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
750 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
751 dp_priv->save_link_configuration,
752 sizeof (dp_priv->save_link_configuration));
753}
754
755static uint8_t
756intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
757 int lane)
758{
759 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
760 int s = ((lane & 1) ?
761 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
762 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
763 uint8_t l = intel_dp_link_status(link_status, i);
764
765 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
766}
767
768static uint8_t
769intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
770 int lane)
771{
772 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
773 int s = ((lane & 1) ?
774 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
775 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
776 uint8_t l = intel_dp_link_status(link_status, i);
777
778 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
779}
780
781
782#if 0
783static char *voltage_names[] = {
784 "0.4V", "0.6V", "0.8V", "1.2V"
785};
786static char *pre_emph_names[] = {
787 "0dB", "3.5dB", "6dB", "9.5dB"
788};
789static char *link_train_names[] = {
790 "pattern 1", "pattern 2", "idle", "off"
791};
792#endif
793
794/*
795 * These are source-specific values; current Intel hardware supports
796 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
797 */
798#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
799
800static uint8_t
801intel_dp_pre_emphasis_max(uint8_t voltage_swing)
802{
803 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
804 case DP_TRAIN_VOLTAGE_SWING_400:
805 return DP_TRAIN_PRE_EMPHASIS_6;
806 case DP_TRAIN_VOLTAGE_SWING_600:
807 return DP_TRAIN_PRE_EMPHASIS_6;
808 case DP_TRAIN_VOLTAGE_SWING_800:
809 return DP_TRAIN_PRE_EMPHASIS_3_5;
810 case DP_TRAIN_VOLTAGE_SWING_1200:
811 default:
812 return DP_TRAIN_PRE_EMPHASIS_0;
813 }
814}
815
816static void
817intel_get_adjust_train(struct intel_output *intel_output,
818 uint8_t link_status[DP_LINK_STATUS_SIZE],
819 int lane_count,
820 uint8_t train_set[4])
821{
822 uint8_t v = 0;
823 uint8_t p = 0;
824 int lane;
825
826 for (lane = 0; lane < lane_count; lane++) {
827 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
828 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
829
830 if (this_v > v)
831 v = this_v;
832 if (this_p > p)
833 p = this_p;
834 }
835
836 if (v >= I830_DP_VOLTAGE_MAX)
837 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
838
839 if (p >= intel_dp_pre_emphasis_max(v))
840 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
841
842 for (lane = 0; lane < 4; lane++)
843 train_set[lane] = v | p;
844}
845
846static uint32_t
847intel_dp_signal_levels(uint8_t train_set, int lane_count)
848{
849 uint32_t signal_levels = 0;
850
851 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
852 case DP_TRAIN_VOLTAGE_SWING_400:
853 default:
854 signal_levels |= DP_VOLTAGE_0_4;
855 break;
856 case DP_TRAIN_VOLTAGE_SWING_600:
857 signal_levels |= DP_VOLTAGE_0_6;
858 break;
859 case DP_TRAIN_VOLTAGE_SWING_800:
860 signal_levels |= DP_VOLTAGE_0_8;
861 break;
862 case DP_TRAIN_VOLTAGE_SWING_1200:
863 signal_levels |= DP_VOLTAGE_1_2;
864 break;
865 }
866 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
867 case DP_TRAIN_PRE_EMPHASIS_0:
868 default:
869 signal_levels |= DP_PRE_EMPHASIS_0;
870 break;
871 case DP_TRAIN_PRE_EMPHASIS_3_5:
872 signal_levels |= DP_PRE_EMPHASIS_3_5;
873 break;
874 case DP_TRAIN_PRE_EMPHASIS_6:
875 signal_levels |= DP_PRE_EMPHASIS_6;
876 break;
877 case DP_TRAIN_PRE_EMPHASIS_9_5:
878 signal_levels |= DP_PRE_EMPHASIS_9_5;
879 break;
880 }
881 return signal_levels;
882}
883
884static uint8_t
885intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
886 int lane)
887{
888 int i = DP_LANE0_1_STATUS + (lane >> 1);
889 int s = (lane & 1) * 4;
890 uint8_t l = intel_dp_link_status(link_status, i);
891
892 return (l >> s) & 0xf;
893}
894
895/* Check for clock recovery is done on all channels */
896static bool
897intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
898{
899 int lane;
900 uint8_t lane_status;
901
902 for (lane = 0; lane < lane_count; lane++) {
903 lane_status = intel_get_lane_status(link_status, lane);
904 if ((lane_status & DP_LANE_CR_DONE) == 0)
905 return false;
906 }
907 return true;
908}
909
910/* Check to see if channel eq is done on all channels */
911#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
912 DP_LANE_CHANNEL_EQ_DONE|\
913 DP_LANE_SYMBOL_LOCKED)
914static bool
915intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
916{
917 uint8_t lane_align;
918 uint8_t lane_status;
919 int lane;
920
921 lane_align = intel_dp_link_status(link_status,
922 DP_LANE_ALIGN_STATUS_UPDATED);
923 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
924 return false;
925 for (lane = 0; lane < lane_count; lane++) {
926 lane_status = intel_get_lane_status(link_status, lane);
927 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
928 return false;
929 }
930 return true;
931}
932
933static bool
934intel_dp_set_link_train(struct intel_output *intel_output,
935 uint32_t dp_reg_value,
936 uint8_t dp_train_pat,
937 uint8_t train_set[4],
938 bool first)
939{
940 struct drm_device *dev = intel_output->base.dev;
941 struct drm_i915_private *dev_priv = dev->dev_private;
942 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
943 int ret;
944
945 I915_WRITE(dp_priv->output_reg, dp_reg_value);
946 POSTING_READ(dp_priv->output_reg);
947 if (first)
948 intel_wait_for_vblank(dev);
949
950 intel_dp_aux_native_write_1(intel_output,
951 DP_TRAINING_PATTERN_SET,
952 dp_train_pat);
953
954 ret = intel_dp_aux_native_write(intel_output,
955 DP_TRAINING_LANE0_SET, train_set, 4);
956 if (ret != 4)
957 return false;
958
959 return true;
960}
961
962static void
963intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
964 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
965{
966 struct drm_device *dev = intel_output->base.dev;
967 struct drm_i915_private *dev_priv = dev->dev_private;
968 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
969 uint8_t train_set[4];
970 uint8_t link_status[DP_LINK_STATUS_SIZE];
971 int i;
972 uint8_t voltage;
973 bool clock_recovery = false;
974 bool channel_eq = false;
975 bool first = true;
976 int tries;
977
978 /* Write the link configuration data */
979 intel_dp_aux_native_write(intel_output, 0x100,
980 link_configuration, DP_LINK_CONFIGURATION_SIZE);
981
982 DP |= DP_PORT_EN;
983 DP &= ~DP_LINK_TRAIN_MASK;
984 memset(train_set, 0, 4);
985 voltage = 0xff;
986 tries = 0;
987 clock_recovery = false;
988 for (;;) {
989 /* Use train_set[0] to set the voltage and pre emphasis values */
990 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
991 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
992
993 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
994 DP_TRAINING_PATTERN_1, train_set, first))
995 break;
996 first = false;
997 /* Set training pattern 1 */
998
999 udelay(100);
1000 if (!intel_dp_get_link_status(intel_output, link_status))
1001 break;
1002
1003 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1004 clock_recovery = true;
1005 break;
1006 }
1007
1008 /* Check to see if we've tried the max voltage */
1009 for (i = 0; i < dp_priv->lane_count; i++)
1010 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1011 break;
1012 if (i == dp_priv->lane_count)
1013 break;
1014
1015 /* Check to see if we've tried the same voltage 5 times */
1016 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1017 ++tries;
1018 if (tries == 5)
1019 break;
1020 } else
1021 tries = 0;
1022 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1023
1024 /* Compute new train_set as requested by target */
1025 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
1026 }
1027
1028 /* channel equalization */
1029 tries = 0;
1030 channel_eq = false;
1031 for (;;) {
1032 /* Use train_set[0] to set the voltage and pre emphasis values */
1033 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1034 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1035
1036 /* channel eq pattern */
1037 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
1038 DP_TRAINING_PATTERN_2, train_set,
1039 false))
1040 break;
1041
1042 udelay(400);
1043 if (!intel_dp_get_link_status(intel_output, link_status))
1044 break;
1045
1046 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1047 channel_eq = true;
1048 break;
1049 }
1050
1051 /* Try 5 times */
1052 if (tries > 5)
1053 break;
1054
1055 /* Compute new train_set as requested by target */
1056 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
1057 ++tries;
1058 }
1059
1060 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1061 POSTING_READ(dp_priv->output_reg);
1062 intel_dp_aux_native_write_1(intel_output,
1063 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1064}
1065
1066static void
1067intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1068{
1069 struct drm_device *dev = intel_output->base.dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1072
32f9d658
ZW		 1073 DRM_DEBUG("\n");
1074
1075 if (IS_eDP(intel_output)) {
1076 DP &= ~DP_PLL_ENABLE;
1077 I915_WRITE(dp_priv->output_reg, DP);
1078 POSTING_READ(dp_priv->output_reg);
1079 udelay(100);
1080 }
1081
5eb08b69
ZW		 1082 DP &= ~DP_LINK_TRAIN_MASK;
1083 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1084 POSTING_READ(dp_priv->output_reg);
1085
1086 udelay(17000);
1087
32f9d658
ZW		 1088 if (IS_eDP(intel_output))
1089 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1090 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1091 POSTING_READ(dp_priv->output_reg);
1092}
1093
1094static void
1095intel_dp_restore(struct drm_connector *connector)
1096{
1097 struct intel_output *intel_output = to_intel_output(connector);
1098 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1099
1100 if (dp_priv->save_DP & DP_PORT_EN)
1101 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
1102 else
1103 intel_dp_link_down(intel_output, dp_priv->save_DP);
1104}
1105
a4fc5ed6
KP		 1106/*
1107 * According to DP spec
1108 * 5.1.2:
1109 * 1. Read DPCD
1110 * 2. Configure link according to Receiver Capabilities
1111 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1112 * 4. Check link status on receipt of hot-plug interrupt
1113 */
1114
1115static void
1116intel_dp_check_link_status(struct intel_output *intel_output)
1117{
1118 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1119 uint8_t link_status[DP_LINK_STATUS_SIZE];
1120
1121 if (!intel_output->enc.crtc)
1122 return;
1123
1124 if (!intel_dp_get_link_status(intel_output, link_status)) {
1125 intel_dp_link_down(intel_output, dp_priv->DP);
1126 return;
1127 }
1128
1129 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1130 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
1131}
a4fc5ed6 1132
5eb08b69
ZW		 1133static enum drm_connector_status
1134igdng_dp_detect(struct drm_connector *connector)
1135{
1136 struct intel_output *intel_output = to_intel_output(connector);
1137 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1138 enum drm_connector_status status;
1139
1140 status = connector_status_disconnected;
1141 if (intel_dp_aux_native_read(intel_output,
1142 0x000, dp_priv->dpcd,
1143 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1144 {
1145 if (dp_priv->dpcd[0] != 0)
1146 status = connector_status_connected;
1147 }
1148 return status;
1149}
1150
a4fc5ed6
KP		 1151/**
1152 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1153 *
1154 * \return true if DP port is connected.
1155 * \return false if DP port is disconnected.
1156 */
1157static enum drm_connector_status
1158intel_dp_detect(struct drm_connector *connector)
1159{
1160 struct intel_output *intel_output = to_intel_output(connector);
1161 struct drm_device *dev = intel_output->base.dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1164 uint32_t temp, bit;
1165 enum drm_connector_status status;
1166
1167 dp_priv->has_audio = false;
1168
5eb08b69
ZW		 1169 if (IS_IGDNG(dev))
1170 return igdng_dp_detect(connector);
1171
a4fc5ed6
KP		 1172 temp = I915_READ(PORT_HOTPLUG_EN);
1173
1174 I915_WRITE(PORT_HOTPLUG_EN,
1175 temp |
1176 DPB_HOTPLUG_INT_EN |
1177 DPC_HOTPLUG_INT_EN |
1178 DPD_HOTPLUG_INT_EN);
1179
1180 POSTING_READ(PORT_HOTPLUG_EN);
1181
1182 switch (dp_priv->output_reg) {
1183 case DP_B:
1184 bit = DPB_HOTPLUG_INT_STATUS;
1185 break;
1186 case DP_C:
1187 bit = DPC_HOTPLUG_INT_STATUS;
1188 break;
1189 case DP_D:
1190 bit = DPD_HOTPLUG_INT_STATUS;
1191 break;
1192 default:
1193 return connector_status_unknown;
1194 }
1195
1196 temp = I915_READ(PORT_HOTPLUG_STAT);
1197
1198 if ((temp & bit) == 0)
1199 return connector_status_disconnected;
1200
1201 status = connector_status_disconnected;
1202 if (intel_dp_aux_native_read(intel_output,
1203 0x000, dp_priv->dpcd,
1204 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1205 {
1206 if (dp_priv->dpcd[0] != 0)
1207 status = connector_status_connected;
1208 }
1209 return status;
1210}
1211
1212static int intel_dp_get_modes(struct drm_connector *connector)
1213{
1214 struct intel_output *intel_output = to_intel_output(connector);
32f9d658
ZW		 1215 struct drm_device *dev = intel_output->base.dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 int ret;
a4fc5ed6
KP		 1218
1219 /* We should parse the EDID data and find out if it has an audio sink
1220 */
1221
32f9d658
ZW		 1222 ret = intel_ddc_get_modes(intel_output);
1223 if (ret)
1224 return ret;
1225
1226 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1227 if (IS_eDP(intel_output)) {
1228 if (dev_priv->panel_fixed_mode != NULL) {
1229 struct drm_display_mode *mode;
1230 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1231 drm_mode_probed_add(connector, mode);
1232 return 1;
1233 }
1234 }
1235 return 0;
a4fc5ed6
KP		 1236}
1237
1238static void
1239intel_dp_destroy (struct drm_connector *connector)
1240{
1241 struct intel_output *intel_output = to_intel_output(connector);
1242
1243 if (intel_output->i2c_bus)
1244 intel_i2c_destroy(intel_output->i2c_bus);
1245 drm_sysfs_connector_remove(connector);
1246 drm_connector_cleanup(connector);
1247 kfree(intel_output);
1248}
1249
1250static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1251 .dpms = intel_dp_dpms,
1252 .mode_fixup = intel_dp_mode_fixup,
1253 .prepare = intel_encoder_prepare,
1254 .mode_set = intel_dp_mode_set,
1255 .commit = intel_encoder_commit,
1256};
1257
1258static const struct drm_connector_funcs intel_dp_connector_funcs = {
1259 .dpms = drm_helper_connector_dpms,
1260 .save = intel_dp_save,
1261 .restore = intel_dp_restore,
1262 .detect = intel_dp_detect,
1263 .fill_modes = drm_helper_probe_single_connector_modes,
1264 .destroy = intel_dp_destroy,
1265};
1266
1267static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1268 .get_modes = intel_dp_get_modes,
1269 .mode_valid = intel_dp_mode_valid,
1270 .best_encoder = intel_best_encoder,
1271};
1272
1273static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1274{
1275 drm_encoder_cleanup(encoder);
1276}
1277
1278static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1279 .destroy = intel_dp_enc_destroy,
1280};
1281
c8110e52
KP		 1282void
1283intel_dp_hot_plug(struct intel_output *intel_output)
1284{
1285 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1286
1287 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1288 intel_dp_check_link_status(intel_output);
1289}
1290
a4fc5ed6
KP		 1291void
1292intel_dp_init(struct drm_device *dev, int output_reg)
1293{
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295 struct drm_connector *connector;
1296 struct intel_output *intel_output;
1297 struct intel_dp_priv *dp_priv;
5eb08b69 1298 const char *name = NULL;
a4fc5ed6
KP		 1299
1300 intel_output = kcalloc(sizeof(struct intel_output) +
1301 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1302 if (!intel_output)
1303 return;
1304
1305 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1306
1307 connector = &intel_output->base;
1308 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1309 DRM_MODE_CONNECTOR_DisplayPort);
1310 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1311
32f9d658
ZW		 1312 if (output_reg == DP_A)
1313 intel_output->type = INTEL_OUTPUT_EDP;
1314 else
1315 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
a4fc5ed6 1316
f8aed700
ML		 1317 if (output_reg == DP_B)
1318 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1319 else if (output_reg == DP_C)
1320 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1321 else if (output_reg == DP_D)
1322 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1323
1324 if (IS_eDP(intel_output)) {
1325 intel_output->crtc_mask = (1 << 1);
7c8460db 1326 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
f8aed700
ML		 1327 } else
1328 intel_output->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1329 connector->interlace_allowed = true;
1330 connector->doublescan_allowed = 0;
1331
1332 dp_priv->intel_output = intel_output;
1333 dp_priv->output_reg = output_reg;
1334 dp_priv->has_audio = false;
c8110e52 1335 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6
KP		 1336 intel_output->dev_priv = dp_priv;
1337
1338 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1339 DRM_MODE_ENCODER_TMDS);
1340 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1341
1342 drm_mode_connector_attach_encoder(&intel_output->base,
1343 &intel_output->enc);
1344 drm_sysfs_connector_add(connector);
1345
1346 /* Set up the DDC bus. */
5eb08b69 1347 switch (output_reg) {
32f9d658
ZW		 1348 case DP_A:
1349 name = "DPDDC-A";
1350 break;
5eb08b69
ZW		 1351 case DP_B:
1352 case PCH_DP_B:
1353 name = "DPDDC-B";
1354 break;
1355 case DP_C:
1356 case PCH_DP_C:
1357 name = "DPDDC-C";
1358 break;
1359 case DP_D:
1360 case PCH_DP_D:
1361 name = "DPDDC-D";
1362 break;
1363 }
1364
1365 intel_dp_i2c_init(intel_output, name);
32f9d658 1366
a4fc5ed6 1367 intel_output->ddc_bus = &dp_priv->adapter;
c8110e52 1368 intel_output->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1369
32f9d658
ZW		 1370 if (output_reg == DP_A) {
1371 /* initialize panel mode from VBT if available for eDP */
1372 if (dev_priv->lfp_lvds_vbt_mode) {
1373 dev_priv->panel_fixed_mode =
1374 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1375 if (dev_priv->panel_fixed_mode) {
1376 dev_priv->panel_fixed_mode->type |=
1377 DRM_MODE_TYPE_PREFERRED;
1378 }
1379 }
1380 }
1381
a4fc5ed6
KP		 1382 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1383 * 0xd. Failure to do so will result in spurious interrupts being
1384 * generated on the port when a cable is not attached.
1385 */
1386 if (IS_G4X(dev) && !IS_GM45(dev)) {
1387 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1388 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1389 }
1390}
Clone of davem's net-next-2.6 tree