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drm/i915: Track whether cursor needs physical address in intel_device_info
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
63eeaf38 29#include <linux/sysrq.h>
1da177e4
LT		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
1c5d22f7 34#include "i915_trace.h"
79e53945 35#include "intel_drv.h"
1da177e4 36
1da177e4 37#define MAX_NOPID ((u32)~0)
1da177e4 38
7c463586
KP		 39/**
40 * Interrupts that are always left unmasked.
41 *
42 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
43 * we leave them always unmasked in IMR and then control enabling them through
44 * PIPESTAT alone.
45 */
6b95a207
KH		 46#define I915_INTERRUPT_ENABLE_FIX \
47 (I915_ASLE_INTERRUPT | \
48 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
49 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
50 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
51 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
52 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
7c463586
KP		 53
54/** Interrupts that we mask and unmask at runtime. */
55#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
56
79e53945
JB		 57#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
58 PIPE_VBLANK_INTERRUPT_STATUS)
59
60#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
61 PIPE_VBLANK_INTERRUPT_ENABLE)
62
63#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
64 DRM_I915_VBLANK_PIPE_B)
65
036a4a7d 66void
f2b115e6 67ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d
ZW		 68{
69 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
70 dev_priv->gt_irq_mask_reg &= ~mask;
71 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
72 (void) I915_READ(GTIMR);
73 }
74}
75
76static inline void
f2b115e6 77ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d
ZW		 78{
79 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
80 dev_priv->gt_irq_mask_reg |= mask;
81 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
82 (void) I915_READ(GTIMR);
83 }
84}
85
86/* For display hotplug interrupt */
87void
f2b115e6 88ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d
ZW		 89{
90 if ((dev_priv->irq_mask_reg & mask) != 0) {
91 dev_priv->irq_mask_reg &= ~mask;
92 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
93 (void) I915_READ(DEIMR);
94 }
95}
96
97static inline void
f2b115e6 98ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d
ZW		 99{
100 if ((dev_priv->irq_mask_reg & mask) != mask) {
101 dev_priv->irq_mask_reg |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
103 (void) I915_READ(DEIMR);
104 }
105}
106
8ee1c3db 107void
ed4cb414
EA		 108i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
109{
110 if ((dev_priv->irq_mask_reg & mask) != 0) {
111 dev_priv->irq_mask_reg &= ~mask;
112 I915_WRITE(IMR, dev_priv->irq_mask_reg);
113 (void) I915_READ(IMR);
114 }
115}
116
117static inline void
118i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
119{
120 if ((dev_priv->irq_mask_reg & mask) != mask) {
121 dev_priv->irq_mask_reg |= mask;
122 I915_WRITE(IMR, dev_priv->irq_mask_reg);
123 (void) I915_READ(IMR);
124 }
125}
126
7c463586
KP		 127static inline u32
128i915_pipestat(int pipe)
129{
130 if (pipe == 0)
131 return PIPEASTAT;
132 if (pipe == 1)
133 return PIPEBSTAT;
9c84ba4e 134 BUG();
7c463586
KP		 135}
136
137void
138i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
139{
140 if ((dev_priv->pipestat[pipe] & mask) != mask) {
141 u32 reg = i915_pipestat(pipe);
142
143 dev_priv->pipestat[pipe] |= mask;
144 /* Enable the interrupt, clear any pending status */
145 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
146 (void) I915_READ(reg);
147 }
148}
149
150void
151i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
152{
153 if ((dev_priv->pipestat[pipe] & mask) != 0) {
154 u32 reg = i915_pipestat(pipe);
155
156 dev_priv->pipestat[pipe] &= ~mask;
157 I915_WRITE(reg, dev_priv->pipestat[pipe]);
158 (void) I915_READ(reg);
159 }
160}
161
01c66889
ZY		 162/**
163 * intel_enable_asle - enable ASLE interrupt for OpRegion
164 */
165void intel_enable_asle (struct drm_device *dev)
166{
167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
168
f2b115e6
AJ		 169 if (IS_IRONLAKE(dev))
170 ironlake_enable_display_irq(dev_priv, DE_GSE);
01c66889
ZY		 171 else
172 i915_enable_pipestat(dev_priv, 1,
173 I915_LEGACY_BLC_EVENT_ENABLE);
174}
175
0a3e67a4
JB		 176/**
177 * i915_pipe_enabled - check if a pipe is enabled
178 * @dev: DRM device
179 * @pipe: pipe to check
180 *
181 * Reading certain registers when the pipe is disabled can hang the chip.
182 * Use this routine to make sure the PLL is running and the pipe is active
183 * before reading such registers if unsure.
184 */
185static int
186i915_pipe_enabled(struct drm_device *dev, int pipe)
187{
188 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
189 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
190
191 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
192 return 1;
193
194 return 0;
195}
196
42f52ef8
KP		 197/* Called from drm generic code, passed a 'crtc', which
198 * we use as a pipe index
199 */
200u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 201{
202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
203 unsigned long high_frame;
204 unsigned long low_frame;
205 u32 high1, high2, low, count;
0a3e67a4 206
0a3e67a4
JB		 207 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
208 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
209
210 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61
ZY		 211 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
212 "pipe %d\n", pipe);
0a3e67a4
JB		 213 return 0;
214 }
215
216 /*
217 * High & low register fields aren't synchronized, so make sure
218 * we get a low value that's stable across two reads of the high
219 * register.
220 */
221 do {
222 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
223 PIPE_FRAME_HIGH_SHIFT);
224 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
225 PIPE_FRAME_LOW_SHIFT);
226 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
227 PIPE_FRAME_HIGH_SHIFT);
228 } while (high1 != high2);
229
230 count = (high1 << 8) | low;
231
232 return count;
233}
234
9880b7a5
JB		 235u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
236{
237 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
238 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
239
240 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61
ZY		 241 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
242 "pipe %d\n", pipe);
9880b7a5
JB		 243 return 0;
244 }
245
246 return I915_READ(reg);
247}
248
5ca58282
JB		 249/*
250 * Handle hotplug events outside the interrupt handler proper.
251 */
252static void i915_hotplug_work_func(struct work_struct *work)
253{
254 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
255 hotplug_work);
256 struct drm_device *dev = dev_priv->dev;
c31c4ba3
KP		 257 struct drm_mode_config *mode_config = &dev->mode_config;
258 struct drm_connector *connector;
259
260 if (mode_config->num_connector) {
261 list_for_each_entry(connector, &mode_config->connector_list, head) {
262 struct intel_output *intel_output = to_intel_output(connector);
263
264 if (intel_output->hot_plug)
265 (*intel_output->hot_plug) (intel_output);
266 }
267 }
5ca58282
JB		 268 /* Just fire off a uevent and let userspace tell us what to do */
269 drm_sysfs_hotplug_event(dev);
270}
271
f2b115e6 272irqreturn_t ironlake_irq_handler(struct drm_device *dev)
036a4a7d
ZW		 273{
274 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
275 int ret = IRQ_NONE;
3ff99164 276 u32 de_iir, gt_iir, de_ier, pch_iir;
c650156a 277 u32 new_de_iir, new_gt_iir, new_pch_iir;
036a4a7d
ZW		 278 struct drm_i915_master_private *master_priv;
279
2d109a84
ZN		 280 /* disable master interrupt before clearing iir */
281 de_ier = I915_READ(DEIER);
282 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
283 (void)I915_READ(DEIER);
284
036a4a7d
ZW		 285 de_iir = I915_READ(DEIIR);
286 gt_iir = I915_READ(GTIIR);
c650156a 287 pch_iir = I915_READ(SDEIIR);
036a4a7d
ZW		 288
289 for (;;) {
c650156a 290 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
036a4a7d
ZW		 291 break;
292
293 ret = IRQ_HANDLED;
294
c650156a
ZW		 295 /* should clear PCH hotplug event before clear CPU irq */
296 I915_WRITE(SDEIIR, pch_iir);
297 new_pch_iir = I915_READ(SDEIIR);
298
036a4a7d
ZW		 299 I915_WRITE(DEIIR, de_iir);
300 new_de_iir = I915_READ(DEIIR);
301 I915_WRITE(GTIIR, gt_iir);
302 new_gt_iir = I915_READ(GTIIR);
303
304 if (dev->primary->master) {
305 master_priv = dev->primary->master->driver_priv;
306 if (master_priv->sarea_priv)
307 master_priv->sarea_priv->last_dispatch =
308 READ_BREADCRUMB(dev_priv);
309 }
310
311 if (gt_iir & GT_USER_INTERRUPT) {
1c5d22f7
CW		 312 u32 seqno = i915_get_gem_seqno(dev);
313 dev_priv->mm.irq_gem_seqno = seqno;
314 trace_i915_gem_request_complete(dev, seqno);
036a4a7d
ZW		 315 DRM_WAKEUP(&dev_priv->irq_queue);
316 }
317
01c66889
ZY		 318 if (de_iir & DE_GSE)
319 ironlake_opregion_gse_intr(dev);
320
c650156a
ZW		 321 /* check event from PCH */
322 if ((de_iir & DE_PCH_EVENT) &&
323 (pch_iir & SDE_HOTPLUG_MASK)) {
324 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
325 }
326
036a4a7d
ZW		 327 de_iir = new_de_iir;
328 gt_iir = new_gt_iir;
c650156a 329 pch_iir = new_pch_iir;
036a4a7d
ZW		 330 }
331
2d109a84
ZN		 332 I915_WRITE(DEIER, de_ier);
333 (void)I915_READ(DEIER);
334
036a4a7d
ZW		 335 return ret;
336}
337
8a905236
JB		 338/**
339 * i915_error_work_func - do process context error handling work
340 * @work: work struct
341 *
342 * Fire an error uevent so userspace can see that a hang or error
343 * was detected.
344 */
345static void i915_error_work_func(struct work_struct *work)
346{
347 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
348 error_work);
349 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 350 char *error_event[] = { "ERROR=1", NULL };
351 char *reset_event[] = { "RESET=1", NULL };
352 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 353
44d98a61 354 DRM_DEBUG_DRIVER("generating error event\n");
f316a42c
BG		 355 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
356
ba1234d1 357 if (atomic_read(&dev_priv->mm.wedged)) {
f316a42c 358 if (IS_I965G(dev)) {
44d98a61 359 DRM_DEBUG_DRIVER("resetting chip\n");
f316a42c
BG		 360 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
361 if (!i965_reset(dev, GDRST_RENDER)) {
ba1234d1 362 atomic_set(&dev_priv->mm.wedged, 0);
f316a42c
BG		 363 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
364 }
365 } else {
44d98a61 366 DRM_DEBUG_DRIVER("reboot required\n");
f316a42c
BG		 367 }
368 }
8a905236
JB		 369}
370
371/**
372 * i915_capture_error_state - capture an error record for later analysis
373 * @dev: drm device
374 *
375 * Should be called when an error is detected (either a hang or an error
376 * interrupt) to capture error state from the time of the error. Fills
377 * out a structure which becomes available in debugfs for user level tools
378 * to pick up.
379 */
63eeaf38
JB		 380static void i915_capture_error_state(struct drm_device *dev)
381{
382 struct drm_i915_private *dev_priv = dev->dev_private;
383 struct drm_i915_error_state *error;
384 unsigned long flags;
385
386 spin_lock_irqsave(&dev_priv->error_lock, flags);
387 if (dev_priv->first_error)
388 goto out;
389
390 error = kmalloc(sizeof(*error), GFP_ATOMIC);
391 if (!error) {
44d98a61 392 DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n");
63eeaf38
JB		 393 goto out;
394 }
395
396 error->eir = I915_READ(EIR);
397 error->pgtbl_er = I915_READ(PGTBL_ER);
398 error->pipeastat = I915_READ(PIPEASTAT);
399 error->pipebstat = I915_READ(PIPEBSTAT);
400 error->instpm = I915_READ(INSTPM);
401 if (!IS_I965G(dev)) {
402 error->ipeir = I915_READ(IPEIR);
403 error->ipehr = I915_READ(IPEHR);
404 error->instdone = I915_READ(INSTDONE);
405 error->acthd = I915_READ(ACTHD);
406 } else {
407 error->ipeir = I915_READ(IPEIR_I965);
408 error->ipehr = I915_READ(IPEHR_I965);
409 error->instdone = I915_READ(INSTDONE_I965);
410 error->instps = I915_READ(INSTPS);
411 error->instdone1 = I915_READ(INSTDONE1);
412 error->acthd = I915_READ(ACTHD_I965);
413 }
414
8a905236
JB		 415 do_gettimeofday(&error->time);
416
63eeaf38
JB		 417 dev_priv->first_error = error;
418
419out:
420 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
421}
422
8a905236
JB		 423/**
424 * i915_handle_error - handle an error interrupt
425 * @dev: drm device
426 *
427 * Do some basic checking of regsiter state at error interrupt time and
428 * dump it to the syslog. Also call i915_capture_error_state() to make
429 * sure we get a record and make it available in debugfs. Fire a uevent
430 * so userspace knows something bad happened (should trigger collection
431 * of a ring dump etc.).
432 */
ba1234d1 433static void i915_handle_error(struct drm_device *dev, bool wedged)
8a905236
JB		 434{
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 u32 eir = I915_READ(EIR);
437 u32 pipea_stats = I915_READ(PIPEASTAT);
438 u32 pipeb_stats = I915_READ(PIPEBSTAT);
439
440 i915_capture_error_state(dev);
441
442 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
443 eir);
444
445 if (IS_G4X(dev)) {
446 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
447 u32 ipeir = I915_READ(IPEIR_I965);
448
449 printk(KERN_ERR " IPEIR: 0x%08x\n",
450 I915_READ(IPEIR_I965));
451 printk(KERN_ERR " IPEHR: 0x%08x\n",
452 I915_READ(IPEHR_I965));
453 printk(KERN_ERR " INSTDONE: 0x%08x\n",
454 I915_READ(INSTDONE_I965));
455 printk(KERN_ERR " INSTPS: 0x%08x\n",
456 I915_READ(INSTPS));
457 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
458 I915_READ(INSTDONE1));
459 printk(KERN_ERR " ACTHD: 0x%08x\n",
460 I915_READ(ACTHD_I965));
461 I915_WRITE(IPEIR_I965, ipeir);
462 (void)I915_READ(IPEIR_I965);
463 }
464 if (eir & GM45_ERROR_PAGE_TABLE) {
465 u32 pgtbl_err = I915_READ(PGTBL_ER);
466 printk(KERN_ERR "page table error\n");
467 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
468 pgtbl_err);
469 I915_WRITE(PGTBL_ER, pgtbl_err);
470 (void)I915_READ(PGTBL_ER);
471 }
472 }
473
474 if (IS_I9XX(dev)) {
475 if (eir & I915_ERROR_PAGE_TABLE) {
476 u32 pgtbl_err = I915_READ(PGTBL_ER);
477 printk(KERN_ERR "page table error\n");
478 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
479 pgtbl_err);
480 I915_WRITE(PGTBL_ER, pgtbl_err);
481 (void)I915_READ(PGTBL_ER);
482 }
483 }
484
485 if (eir & I915_ERROR_MEMORY_REFRESH) {
486 printk(KERN_ERR "memory refresh error\n");
487 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
488 pipea_stats);
489 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
490 pipeb_stats);
491 /* pipestat has already been acked */
492 }
493 if (eir & I915_ERROR_INSTRUCTION) {
494 printk(KERN_ERR "instruction error\n");
495 printk(KERN_ERR " INSTPM: 0x%08x\n",
496 I915_READ(INSTPM));
497 if (!IS_I965G(dev)) {
498 u32 ipeir = I915_READ(IPEIR);
499
500 printk(KERN_ERR " IPEIR: 0x%08x\n",
501 I915_READ(IPEIR));
502 printk(KERN_ERR " IPEHR: 0x%08x\n",
503 I915_READ(IPEHR));
504 printk(KERN_ERR " INSTDONE: 0x%08x\n",
505 I915_READ(INSTDONE));
506 printk(KERN_ERR " ACTHD: 0x%08x\n",
507 I915_READ(ACTHD));
508 I915_WRITE(IPEIR, ipeir);
509 (void)I915_READ(IPEIR);
510 } else {
511 u32 ipeir = I915_READ(IPEIR_I965);
512
513 printk(KERN_ERR " IPEIR: 0x%08x\n",
514 I915_READ(IPEIR_I965));
515 printk(KERN_ERR " IPEHR: 0x%08x\n",
516 I915_READ(IPEHR_I965));
517 printk(KERN_ERR " INSTDONE: 0x%08x\n",
518 I915_READ(INSTDONE_I965));
519 printk(KERN_ERR " INSTPS: 0x%08x\n",
520 I915_READ(INSTPS));
521 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
522 I915_READ(INSTDONE1));
523 printk(KERN_ERR " ACTHD: 0x%08x\n",
524 I915_READ(ACTHD_I965));
525 I915_WRITE(IPEIR_I965, ipeir);
526 (void)I915_READ(IPEIR_I965);
527 }
528 }
529
530 I915_WRITE(EIR, eir);
531 (void)I915_READ(EIR);
532 eir = I915_READ(EIR);
533 if (eir) {
534 /*
535 * some errors might have become stuck,
536 * mask them.
537 */
538 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
539 I915_WRITE(EMR, I915_READ(EMR) | eir);
540 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
541 }
542
ba1234d1
BG		 543 if (wedged) {
544 atomic_set(&dev_priv->mm.wedged, 1);
545
11ed50ec
BG		 546 /*
547 * Wakeup waiting processes so they don't hang
548 */
11ed50ec
BG		 549 DRM_WAKEUP(&dev_priv->irq_queue);
550 }
551
9c9fe1f8 552 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 553}
554
1da177e4
LT		 555irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
556{
84b1fd10 557 struct drm_device *dev = (struct drm_device *) arg;
1da177e4 558 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 559 struct drm_i915_master_private *master_priv;
cdfbc41f
EA		 560 u32 iir, new_iir;
561 u32 pipea_stats, pipeb_stats;
05eff845
KP		 562 u32 vblank_status;
563 u32 vblank_enable;
0a3e67a4 564 int vblank = 0;
7c463586 565 unsigned long irqflags;
05eff845
KP		 566 int irq_received;
567 int ret = IRQ_NONE;
6e5fca53 568
630681d9
EA		 569 atomic_inc(&dev_priv->irq_received);
570
f2b115e6
AJ		 571 if (IS_IRONLAKE(dev))
572 return ironlake_irq_handler(dev);
036a4a7d 573
ed4cb414 574 iir = I915_READ(IIR);
a6b54f3f 575
05eff845
KP		 576 if (IS_I965G(dev)) {
577 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
578 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
579 } else {
580 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
581 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
582 }
af6061af 583
05eff845
KP		 584 for (;;) {
585 irq_received = iir != 0;
586
587 /* Can't rely on pipestat interrupt bit in iir as it might
588 * have been cleared after the pipestat interrupt was received.
589 * It doesn't set the bit in iir again, but it still produces
590 * interrupts (for non-MSI).
591 */
592 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
593 pipea_stats = I915_READ(PIPEASTAT);
594 pipeb_stats = I915_READ(PIPEBSTAT);
79e53945 595
8a905236 596 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
ba1234d1 597 i915_handle_error(dev, false);
8a905236 598
cdfbc41f
EA		 599 /*
600 * Clear the PIPE(A|B)STAT regs before the IIR
601 */
05eff845 602 if (pipea_stats & 0x8000ffff) {
7662c8bd 603 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
44d98a61 604 DRM_DEBUG_DRIVER("pipe a underrun\n");
cdfbc41f 605 I915_WRITE(PIPEASTAT, pipea_stats);
05eff845 606 irq_received = 1;
cdfbc41f 607 }
1da177e4 608
05eff845 609 if (pipeb_stats & 0x8000ffff) {
7662c8bd 610 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
44d98a61 611 DRM_DEBUG_DRIVER("pipe b underrun\n");
cdfbc41f 612 I915_WRITE(PIPEBSTAT, pipeb_stats);
05eff845 613 irq_received = 1;
cdfbc41f 614 }
05eff845
KP		 615 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
616
617 if (!irq_received)
618 break;
619
620 ret = IRQ_HANDLED;
8ee1c3db 621
5ca58282
JB		 622 /* Consume port. Then clear IIR or we'll miss events */
623 if ((I915_HAS_HOTPLUG(dev)) &&
624 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
625 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
626
44d98a61 627 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
5ca58282
JB		 628 hotplug_status);
629 if (hotplug_status & dev_priv->hotplug_supported_mask)
9c9fe1f8
EA		 630 queue_work(dev_priv->wq,
631 &dev_priv->hotplug_work);
5ca58282
JB		 632
633 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
634 I915_READ(PORT_HOTPLUG_STAT);
635 }
636
cdfbc41f
EA		 637 I915_WRITE(IIR, iir);
638 new_iir = I915_READ(IIR); /* Flush posted writes */
7c463586 639
7c1c2871
DA		 640 if (dev->primary->master) {
641 master_priv = dev->primary->master->driver_priv;
642 if (master_priv->sarea_priv)
643 master_priv->sarea_priv->last_dispatch =
644 READ_BREADCRUMB(dev_priv);
645 }
0a3e67a4 646
cdfbc41f 647 if (iir & I915_USER_INTERRUPT) {
1c5d22f7
CW		 648 u32 seqno = i915_get_gem_seqno(dev);
649 dev_priv->mm.irq_gem_seqno = seqno;
650 trace_i915_gem_request_complete(dev, seqno);
cdfbc41f 651 DRM_WAKEUP(&dev_priv->irq_queue);
f65d9421
BG		 652 dev_priv->hangcheck_count = 0;
653 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
cdfbc41f 654 }
673a394b 655
6b95a207
KH		 656 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
657 intel_prepare_page_flip(dev, 0);
658
659 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
660 intel_prepare_page_flip(dev, 1);
661
05eff845 662 if (pipea_stats & vblank_status) {
cdfbc41f
EA		 663 vblank++;
664 drm_handle_vblank(dev, 0);
6b95a207 665 intel_finish_page_flip(dev, 0);
cdfbc41f 666 }
7c463586 667
05eff845 668 if (pipeb_stats & vblank_status) {
cdfbc41f
EA		 669 vblank++;
670 drm_handle_vblank(dev, 1);
6b95a207 671 intel_finish_page_flip(dev, 1);
cdfbc41f 672 }
7c463586 673
cdfbc41f
EA		 674 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
675 (iir & I915_ASLE_INTERRUPT))
676 opregion_asle_intr(dev);
677
678 /* With MSI, interrupts are only generated when iir
679 * transitions from zero to nonzero. If another bit got
680 * set while we were handling the existing iir bits, then
681 * we would never get another interrupt.
682 *
683 * This is fine on non-MSI as well, as if we hit this path
684 * we avoid exiting the interrupt handler only to generate
685 * another one.
686 *
687 * Note that for MSI this could cause a stray interrupt report
688 * if an interrupt landed in the time between writing IIR and
689 * the posting read. This should be rare enough to never
690 * trigger the 99% of 100,000 interrupts test for disabling
691 * stray interrupts.
692 */
693 iir = new_iir;
05eff845 694 }
0a3e67a4 695
05eff845 696 return ret;
1da177e4
LT		 697}
698
af6061af 699static int i915_emit_irq(struct drm_device * dev)
1da177e4
LT		 700{
701 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 702 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4
LT		 703 RING_LOCALS;
704
705 i915_kernel_lost_context(dev);
706
44d98a61 707 DRM_DEBUG_DRIVER("\n");
1da177e4 708
c99b058f 709 dev_priv->counter++;
c29b669c 710 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 711 dev_priv->counter = 1;
7c1c2871
DA		 712 if (master_priv->sarea_priv)
713 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
c29b669c 714
0baf823a 715 BEGIN_LP_RING(4);
585fb111 716 OUT_RING(MI_STORE_DWORD_INDEX);
0baf823a 717 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
c29b669c 718 OUT_RING(dev_priv->counter);
585fb111 719 OUT_RING(MI_USER_INTERRUPT);
1da177e4 720 ADVANCE_LP_RING();
bc5f4523 721
c29b669c 722 return dev_priv->counter;
1da177e4
LT		 723}
724
673a394b 725void i915_user_irq_get(struct drm_device *dev)
ed4cb414
EA		 726{
727 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 728 unsigned long irqflags;
ed4cb414 729
e9d21d7f 730 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
036a4a7d 731 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
f2b115e6
AJ		 732 if (IS_IRONLAKE(dev))
733 ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
036a4a7d
ZW		 734 else
735 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
736 }
e9d21d7f 737 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
ed4cb414
EA		 738}
739
0a3e67a4 740void i915_user_irq_put(struct drm_device *dev)
ed4cb414
EA		 741{
742 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 743 unsigned long irqflags;
ed4cb414 744
e9d21d7f 745 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
ed4cb414 746 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
036a4a7d 747 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
f2b115e6
AJ		 748 if (IS_IRONLAKE(dev))
749 ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
036a4a7d
ZW		 750 else
751 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
752 }
e9d21d7f 753 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
ed4cb414
EA		 754}
755
9d34e5db
CW		 756void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
757{
758 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
759
760 if (dev_priv->trace_irq_seqno == 0)
761 i915_user_irq_get(dev);
762
763 dev_priv->trace_irq_seqno = seqno;
764}
765
84b1fd10 766static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1da177e4
LT		 767{
768 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 769 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4
LT		 770 int ret = 0;
771
44d98a61 772 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1da177e4
LT		 773 READ_BREADCRUMB(dev_priv));
774
ed4cb414 775 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
7c1c2871
DA		 776 if (master_priv->sarea_priv)
777 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1da177e4 778 return 0;
ed4cb414 779 }
1da177e4 780
7c1c2871
DA		 781 if (master_priv->sarea_priv)
782 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1da177e4 783
ed4cb414 784 i915_user_irq_get(dev);
1da177e4
LT		 785 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
786 READ_BREADCRUMB(dev_priv) >= irq_nr);
ed4cb414 787 i915_user_irq_put(dev);
1da177e4 788
20caafa6 789 if (ret == -EBUSY) {
3e684eae 790 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1da177e4
LT		 791 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
792 }
793
af6061af
DA		 794 return ret;
795}
796
1da177e4
LT		 797/* Needs the lock as it touches the ring.
798 */
c153f45f
EA		 799int i915_irq_emit(struct drm_device *dev, void *data,
800 struct drm_file *file_priv)
1da177e4 801{
1da177e4 802 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 803 drm_i915_irq_emit_t *emit = data;
1da177e4
LT		 804 int result;
805
07f4f8bf 806 if (!dev_priv || !dev_priv->ring.virtual_start) {
3e684eae 807 DRM_ERROR("called with no initialization\n");
20caafa6 808 return -EINVAL;
1da177e4 809 }
299eb93c
EA		 810
811 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
812
546b0974 813 mutex_lock(&dev->struct_mutex);
1da177e4 814 result = i915_emit_irq(dev);
546b0974 815 mutex_unlock(&dev->struct_mutex);
1da177e4 816
c153f45f 817 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1da177e4 818 DRM_ERROR("copy_to_user\n");
20caafa6 819 return -EFAULT;
1da177e4
LT		 820 }
821
822 return 0;
823}
824
825/* Doesn't need the hardware lock.
826 */
c153f45f
EA		 827int i915_irq_wait(struct drm_device *dev, void *data,
828 struct drm_file *file_priv)
1da177e4 829{
1da177e4 830 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 831 drm_i915_irq_wait_t *irqwait = data;
1da177e4
LT		 832
833 if (!dev_priv) {
3e684eae 834 DRM_ERROR("called with no initialization\n");
20caafa6 835 return -EINVAL;
1da177e4
LT		 836 }
837
c153f45f 838 return i915_wait_irq(dev, irqwait->irq_seq);
1da177e4
LT		 839}
840
42f52ef8
KP		 841/* Called from drm generic code, passed 'crtc' which
842 * we use as a pipe index
843 */
844int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 845{
846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 847 unsigned long irqflags;
71e0ffa5
JB		 848 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
849 u32 pipeconf;
850
851 pipeconf = I915_READ(pipeconf_reg);
852 if (!(pipeconf & PIPEACONF_ENABLE))
853 return -EINVAL;
0a3e67a4 854
f2b115e6 855 if (IS_IRONLAKE(dev))
036a4a7d
ZW		 856 return 0;
857
e9d21d7f 858 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
e9d21d7f 859 if (IS_I965G(dev))
7c463586
KP		 860 i915_enable_pipestat(dev_priv, pipe,
861 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 862 else
7c463586
KP		 863 i915_enable_pipestat(dev_priv, pipe,
864 PIPE_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 865 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
0a3e67a4
JB		 866 return 0;
867}
868
42f52ef8
KP		 869/* Called from drm generic code, passed 'crtc' which
870 * we use as a pipe index
871 */
872void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 873{
874 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 875 unsigned long irqflags;
0a3e67a4 876
f2b115e6 877 if (IS_IRONLAKE(dev))
036a4a7d
ZW		 878 return;
879
e9d21d7f 880 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
7c463586
KP		 881 i915_disable_pipestat(dev_priv, pipe,
882 PIPE_VBLANK_INTERRUPT_ENABLE |
883 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 884 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
0a3e67a4
JB		 885}
886
79e53945
JB		 887void i915_enable_interrupt (struct drm_device *dev)
888{
889 struct drm_i915_private *dev_priv = dev->dev_private;
e170b030 890
f2b115e6 891 if (!IS_IRONLAKE(dev))
e170b030 892 opregion_enable_asle(dev);
79e53945
JB		 893 dev_priv->irq_enabled = 1;
894}
895
896
702880f2
DA		 897/* Set the vblank monitor pipe
898 */
c153f45f
EA		 899int i915_vblank_pipe_set(struct drm_device *dev, void *data,
900 struct drm_file *file_priv)
702880f2 901{
702880f2 902 drm_i915_private_t *dev_priv = dev->dev_private;
702880f2
DA		 903
904 if (!dev_priv) {
3e684eae 905 DRM_ERROR("called with no initialization\n");
20caafa6 906 return -EINVAL;
702880f2
DA		 907 }
908
5b51694a 909 return 0;
702880f2
DA		 910}
911
c153f45f
EA		 912int i915_vblank_pipe_get(struct drm_device *dev, void *data,
913 struct drm_file *file_priv)
702880f2 914{
702880f2 915 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 916 drm_i915_vblank_pipe_t *pipe = data;
702880f2
DA		 917
918 if (!dev_priv) {
3e684eae 919 DRM_ERROR("called with no initialization\n");
20caafa6 920 return -EINVAL;
702880f2
DA		 921 }
922
0a3e67a4 923 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
c153f45f 924
702880f2
DA		 925 return 0;
926}
927
a6b54f3f
MD		 928/**
929 * Schedule buffer swap at given vertical blank.
930 */
c153f45f
EA		 931int i915_vblank_swap(struct drm_device *dev, void *data,
932 struct drm_file *file_priv)
a6b54f3f 933{
bd95e0a4
EA		 934 /* The delayed swap mechanism was fundamentally racy, and has been
935 * removed. The model was that the client requested a delayed flip/swap
936 * from the kernel, then waited for vblank before continuing to perform
937 * rendering. The problem was that the kernel might wake the client
938 * up before it dispatched the vblank swap (since the lock has to be
939 * held while touching the ringbuffer), in which case the client would
940 * clear and start the next frame before the swap occurred, and
941 * flicker would occur in addition to likely missing the vblank.
942 *
943 * In the absence of this ioctl, userland falls back to a correct path
944 * of waiting for a vblank, then dispatching the swap on its own.
945 * Context switching to userland and back is plenty fast enough for
946 * meeting the requirements of vblank swapping.
0a3e67a4 947 */
bd95e0a4 948 return -EINVAL;
a6b54f3f
MD		 949}
950
f65d9421
BG		 951struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
952 drm_i915_private_t *dev_priv = dev->dev_private;
953 return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
954}
955
956/**
957 * This is called when the chip hasn't reported back with completed
958 * batchbuffers in a long time. The first time this is called we simply record
959 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
960 * again, we assume the chip is wedged and try to fix it.
961 */
962void i915_hangcheck_elapsed(unsigned long data)
963{
964 struct drm_device *dev = (struct drm_device *)data;
965 drm_i915_private_t *dev_priv = dev->dev_private;
966 uint32_t acthd;
967
968 if (!IS_I965G(dev))
969 acthd = I915_READ(ACTHD);
970 else
971 acthd = I915_READ(ACTHD_I965);
972
973 /* If all work is done then ACTHD clearly hasn't advanced. */
974 if (list_empty(&dev_priv->mm.request_list) ||
975 i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
976 dev_priv->hangcheck_count = 0;
977 return;
978 }
979
980 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
981 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
ba1234d1 982 i915_handle_error(dev, true);
f65d9421
BG		 983 return;
984 }
985
986 /* Reset timer case chip hangs without another request being added */
987 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
988
989 if (acthd != dev_priv->last_acthd)
990 dev_priv->hangcheck_count = 0;
991 else
992 dev_priv->hangcheck_count++;
993
994 dev_priv->last_acthd = acthd;
995}
996
1da177e4
LT		 997/* drm_dma.h hooks
998*/
f2b115e6 999static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1000{
1001 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1002
1003 I915_WRITE(HWSTAM, 0xeffe);
1004
1005 /* XXX hotplug from PCH */
1006
1007 I915_WRITE(DEIMR, 0xffffffff);
1008 I915_WRITE(DEIER, 0x0);
1009 (void) I915_READ(DEIER);
1010
1011 /* and GT */
1012 I915_WRITE(GTIMR, 0xffffffff);
1013 I915_WRITE(GTIER, 0x0);
1014 (void) I915_READ(GTIER);
c650156a
ZW		 1015
1016 /* south display irq */
1017 I915_WRITE(SDEIMR, 0xffffffff);
1018 I915_WRITE(SDEIER, 0x0);
1019 (void) I915_READ(SDEIER);
036a4a7d
ZW		 1020}
1021
f2b115e6 1022static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1023{
1024 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1025 /* enable kind of interrupts always enabled */
c650156a 1026 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT;
036a4a7d 1027 u32 render_mask = GT_USER_INTERRUPT;
c650156a
ZW		 1028 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1029 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
036a4a7d
ZW		 1030
1031 dev_priv->irq_mask_reg = ~display_mask;
1032 dev_priv->de_irq_enable_reg = display_mask;
1033
1034 /* should always can generate irq */
1035 I915_WRITE(DEIIR, I915_READ(DEIIR));
1036 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1037 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1038 (void) I915_READ(DEIER);
1039
1040 /* user interrupt should be enabled, but masked initial */
1041 dev_priv->gt_irq_mask_reg = 0xffffffff;
1042 dev_priv->gt_irq_enable_reg = render_mask;
1043
1044 I915_WRITE(GTIIR, I915_READ(GTIIR));
1045 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1046 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1047 (void) I915_READ(GTIER);
1048
c650156a
ZW		 1049 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1050 dev_priv->pch_irq_enable_reg = hotplug_mask;
1051
1052 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1053 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1054 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1055 (void) I915_READ(SDEIER);
1056
036a4a7d
ZW		 1057 return 0;
1058}
1059
84b1fd10 1060void i915_driver_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1061{
1062 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1063
79e53945
JB		 1064 atomic_set(&dev_priv->irq_received, 0);
1065
036a4a7d 1066 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
8a905236 1067 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
036a4a7d 1068
f2b115e6
AJ		 1069 if (IS_IRONLAKE(dev)) {
1070 ironlake_irq_preinstall(dev);
036a4a7d
ZW		 1071 return;
1072 }
1073
5ca58282
JB		 1074 if (I915_HAS_HOTPLUG(dev)) {
1075 I915_WRITE(PORT_HOTPLUG_EN, 0);
1076 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1077 }
1078
0a3e67a4 1079 I915_WRITE(HWSTAM, 0xeffe);
7c463586
KP		 1080 I915_WRITE(PIPEASTAT, 0);
1081 I915_WRITE(PIPEBSTAT, 0);
0a3e67a4 1082 I915_WRITE(IMR, 0xffffffff);
ed4cb414 1083 I915_WRITE(IER, 0x0);
7c463586 1084 (void) I915_READ(IER);
1da177e4
LT		 1085}
1086
0a3e67a4 1087int i915_driver_irq_postinstall(struct drm_device *dev)
1da177e4
LT		 1088{
1089 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5ca58282 1090 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
63eeaf38 1091 u32 error_mask;
0a3e67a4 1092
036a4a7d
ZW		 1093 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1094
0a3e67a4 1095 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
0a3e67a4 1096
f2b115e6
AJ		 1097 if (IS_IRONLAKE(dev))
1098 return ironlake_irq_postinstall(dev);
036a4a7d 1099
7c463586
KP		 1100 /* Unmask the interrupts that we always want on. */
1101 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1102
1103 dev_priv->pipestat[0] = 0;
1104 dev_priv->pipestat[1] = 0;
1105
5ca58282
JB		 1106 if (I915_HAS_HOTPLUG(dev)) {
1107 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1108
1109 /* Leave other bits alone */
1110 hotplug_en |= HOTPLUG_EN_MASK;
1111 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1112
1113 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
1114 TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
1115 SDVOB_HOTPLUG_INT_STATUS;
1116 if (IS_G4X(dev)) {
1117 dev_priv->hotplug_supported_mask |=
1118 HDMIB_HOTPLUG_INT_STATUS |
1119 HDMIC_HOTPLUG_INT_STATUS |
1120 HDMID_HOTPLUG_INT_STATUS;
1121 }
1122 /* Enable in IER... */
1123 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1124 /* and unmask in IMR */
1125 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1126 }
1127
63eeaf38
JB		 1128 /*
1129 * Enable some error detection, note the instruction error mask
1130 * bit is reserved, so we leave it masked.
1131 */
1132 if (IS_G4X(dev)) {
1133 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1134 GM45_ERROR_MEM_PRIV |
1135 GM45_ERROR_CP_PRIV |
1136 I915_ERROR_MEMORY_REFRESH);
1137 } else {
1138 error_mask = ~(I915_ERROR_PAGE_TABLE |
1139 I915_ERROR_MEMORY_REFRESH);
1140 }
1141 I915_WRITE(EMR, error_mask);
1142
7c463586
KP		 1143 /* Disable pipe interrupt enables, clear pending pipe status */
1144 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1145 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1146 /* Clear pending interrupt status */
1147 I915_WRITE(IIR, I915_READ(IIR));
8ee1c3db 1148
5ca58282 1149 I915_WRITE(IER, enable_mask);
7c463586 1150 I915_WRITE(IMR, dev_priv->irq_mask_reg);
ed4cb414
EA		 1151 (void) I915_READ(IER);
1152
8ee1c3db 1153 opregion_enable_asle(dev);
0a3e67a4
JB		 1154
1155 return 0;
1da177e4
LT		 1156}
1157
f2b115e6 1158static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1159{
1160 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1161 I915_WRITE(HWSTAM, 0xffffffff);
1162
1163 I915_WRITE(DEIMR, 0xffffffff);
1164 I915_WRITE(DEIER, 0x0);
1165 I915_WRITE(DEIIR, I915_READ(DEIIR));
1166
1167 I915_WRITE(GTIMR, 0xffffffff);
1168 I915_WRITE(GTIER, 0x0);
1169 I915_WRITE(GTIIR, I915_READ(GTIIR));
1170}
1171
84b1fd10 1172void i915_driver_irq_uninstall(struct drm_device * dev)
1da177e4
LT		 1173{
1174 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
91e3738e 1175
1da177e4
LT		 1176 if (!dev_priv)
1177 return;
1178
0a3e67a4
JB		 1179 dev_priv->vblank_pipe = 0;
1180
f2b115e6
AJ		 1181 if (IS_IRONLAKE(dev)) {
1182 ironlake_irq_uninstall(dev);
036a4a7d
ZW		 1183 return;
1184 }
1185
5ca58282
JB		 1186 if (I915_HAS_HOTPLUG(dev)) {
1187 I915_WRITE(PORT_HOTPLUG_EN, 0);
1188 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1189 }
1190
0a3e67a4 1191 I915_WRITE(HWSTAM, 0xffffffff);
7c463586
KP		 1192 I915_WRITE(PIPEASTAT, 0);
1193 I915_WRITE(PIPEBSTAT, 0);
0a3e67a4 1194 I915_WRITE(IMR, 0xffffffff);
ed4cb414 1195 I915_WRITE(IER, 0x0);
af6061af 1196
7c463586
KP		 1197 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1198 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1199 I915_WRITE(IIR, I915_READ(IIR));
1da177e4 1200}
Clone of davem's net-next-2.6 tree