]>
Commit | Line | Data |
---|---|---|
0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | ||
1da177e4 | 34 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 35 | |
ed4cb414 EA |
36 | /** These are the interrupts used by the driver */ |
37 | #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \ | |
8ee1c3db | 38 | I915_ASLE_INTERRUPT | \ |
0a3e67a4 | 39 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
8ee1c3db | 40 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) |
ed4cb414 | 41 | |
8ee1c3db | 42 | void |
ed4cb414 EA |
43 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
44 | { | |
45 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
46 | dev_priv->irq_mask_reg &= ~mask; | |
47 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
48 | (void) I915_READ(IMR); | |
49 | } | |
50 | } | |
51 | ||
52 | static inline void | |
53 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
54 | { | |
55 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
56 | dev_priv->irq_mask_reg |= mask; | |
57 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
58 | (void) I915_READ(IMR); | |
59 | } | |
60 | } | |
61 | ||
0a3e67a4 JB |
62 | /** |
63 | * i915_get_pipe - return the the pipe associated with a given plane | |
64 | * @dev: DRM device | |
65 | * @plane: plane to look for | |
66 | * | |
67 | * The Intel Mesa & 2D drivers call the vblank routines with a plane number | |
68 | * rather than a pipe number, since they may not always be equal. This routine | |
69 | * maps the given @plane back to a pipe number. | |
70 | */ | |
71 | static int | |
72 | i915_get_pipe(struct drm_device *dev, int plane) | |
73 | { | |
74 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
75 | u32 dspcntr; | |
76 | ||
77 | dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR); | |
78 | ||
79 | return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0; | |
80 | } | |
81 | ||
82 | /** | |
83 | * i915_get_plane - return the the plane associated with a given pipe | |
84 | * @dev: DRM device | |
85 | * @pipe: pipe to look for | |
86 | * | |
87 | * The Intel Mesa & 2D drivers call the vblank routines with a plane number | |
88 | * rather than a plane number, since they may not always be equal. This routine | |
89 | * maps the given @pipe back to a plane number. | |
90 | */ | |
91 | static int | |
92 | i915_get_plane(struct drm_device *dev, int pipe) | |
93 | { | |
94 | if (i915_get_pipe(dev, 0) == pipe) | |
95 | return 0; | |
96 | return 1; | |
97 | } | |
98 | ||
99 | /** | |
100 | * i915_pipe_enabled - check if a pipe is enabled | |
101 | * @dev: DRM device | |
102 | * @pipe: pipe to check | |
103 | * | |
104 | * Reading certain registers when the pipe is disabled can hang the chip. | |
105 | * Use this routine to make sure the PLL is running and the pipe is active | |
106 | * before reading such registers if unsure. | |
107 | */ | |
108 | static int | |
109 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
110 | { | |
111 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
112 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
113 | ||
114 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
115 | return 1; | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
a6b54f3f MD |
120 | /** |
121 | * Emit blits for scheduled buffer swaps. | |
122 | * | |
123 | * This function will be called with the HW lock held. | |
9e44af79 KP |
124 | * Because this function must grab the ring mutex (dev->struct_mutex), |
125 | * it can no longer run at soft irq time. We'll fix this when we do | |
126 | * the DRI2 swap buffer work. | |
a6b54f3f | 127 | */ |
84b1fd10 | 128 | static void i915_vblank_tasklet(struct drm_device *dev) |
a6b54f3f MD |
129 | { |
130 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
af6061af | 131 | unsigned long irqflags; |
3188a24c | 132 | struct list_head *list, *tmp, hits, *hit; |
af6061af | 133 | int nhits, nrects, slice[2], upper[2], lower[2], i; |
0a3e67a4 | 134 | unsigned counter[2]; |
c60ce623 | 135 | struct drm_drawable_info *drw; |
3188a24c | 136 | drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; |
af6061af | 137 | u32 cpp = dev_priv->cpp; |
3188a24c MD |
138 | u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD | |
139 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
140 | XY_SRC_COPY_BLT_WRITE_RGB) | |
141 | : XY_SRC_COPY_BLT_CMD; | |
7b832b56 KP |
142 | u32 src_pitch = sarea_priv->pitch * cpp; |
143 | u32 dst_pitch = sarea_priv->pitch * cpp; | |
144 | u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); | |
3188a24c | 145 | RING_LOCALS; |
a6b54f3f | 146 | |
9e44af79 KP |
147 | mutex_lock(&dev->struct_mutex); |
148 | ||
3d25802e | 149 | if (IS_I965G(dev) && sarea_priv->front_tiled) { |
7b832b56 KP |
150 | cmd |= XY_SRC_COPY_BLT_DST_TILED; |
151 | dst_pitch >>= 2; | |
152 | } | |
3d25802e | 153 | if (IS_I965G(dev) && sarea_priv->back_tiled) { |
7b832b56 KP |
154 | cmd |= XY_SRC_COPY_BLT_SRC_TILED; |
155 | src_pitch >>= 2; | |
156 | } | |
157 | ||
9e44af79 KP |
158 | counter[0] = drm_vblank_count(dev, i915_get_plane(dev, 0)); |
159 | counter[1] = drm_vblank_count(dev, i915_get_plane(dev, 1)); | |
0a3e67a4 | 160 | |
a6b54f3f MD |
161 | DRM_DEBUG("\n"); |
162 | ||
3188a24c MD |
163 | INIT_LIST_HEAD(&hits); |
164 | ||
165 | nhits = nrects = 0; | |
166 | ||
af6061af | 167 | spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); |
a6b54f3f | 168 | |
3188a24c | 169 | /* Find buffer swaps scheduled for this vertical blank */ |
a6b54f3f MD |
170 | list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { |
171 | drm_i915_vbl_swap_t *vbl_swap = | |
172 | list_entry(list, drm_i915_vbl_swap_t, head); | |
9e44af79 | 173 | int pipe = vbl_swap->pipe; |
a6b54f3f | 174 | |
0a3e67a4 | 175 | if ((counter[pipe] - vbl_swap->sequence) > (1<<23)) |
3188a24c MD |
176 | continue; |
177 | ||
178 | list_del(list); | |
179 | dev_priv->swaps_pending--; | |
0a3e67a4 | 180 | drm_vblank_put(dev, pipe); |
3188a24c MD |
181 | |
182 | spin_unlock(&dev_priv->swaps_lock); | |
183 | spin_lock(&dev->drw_lock); | |
a6b54f3f | 184 | |
3188a24c | 185 | drw = drm_get_drawable_info(dev, vbl_swap->drw_id); |
a6b54f3f | 186 | |
3188a24c MD |
187 | list_for_each(hit, &hits) { |
188 | drm_i915_vbl_swap_t *swap_cmp = | |
189 | list_entry(hit, drm_i915_vbl_swap_t, head); | |
c60ce623 | 190 | struct drm_drawable_info *drw_cmp = |
3188a24c | 191 | drm_get_drawable_info(dev, swap_cmp->drw_id); |
a6b54f3f | 192 | |
9e44af79 KP |
193 | /* Make sure both drawables are still |
194 | * around and have some rectangles before | |
195 | * we look inside to order them for the | |
196 | * blts below. | |
197 | */ | |
198 | if (drw_cmp && drw_cmp->num_rects > 0 && | |
199 | drw && drw->num_rects > 0 && | |
3188a24c MD |
200 | drw_cmp->rects[0].y1 > drw->rects[0].y1) { |
201 | list_add_tail(list, hit); | |
202 | break; | |
a6b54f3f | 203 | } |
3188a24c | 204 | } |
a6b54f3f | 205 | |
3188a24c | 206 | spin_unlock(&dev->drw_lock); |
a6b54f3f | 207 | |
3188a24c MD |
208 | /* List of hits was empty, or we reached the end of it */ |
209 | if (hit == &hits) | |
210 | list_add_tail(list, hits.prev); | |
a6b54f3f | 211 | |
3188a24c | 212 | nhits++; |
a6b54f3f | 213 | |
3188a24c MD |
214 | spin_lock(&dev_priv->swaps_lock); |
215 | } | |
216 | ||
af6061af DA |
217 | if (nhits == 0) { |
218 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); | |
9e44af79 | 219 | mutex_unlock(&dev->struct_mutex); |
ac741ab7 | 220 | return; |
af6061af DA |
221 | } |
222 | ||
223 | spin_unlock(&dev_priv->swaps_lock); | |
3188a24c | 224 | |
ac741ab7 | 225 | i915_kernel_lost_context(dev); |
3188a24c | 226 | |
af6061af DA |
227 | if (IS_I965G(dev)) { |
228 | BEGIN_LP_RING(4); | |
229 | ||
230 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
231 | OUT_RING(0); | |
232 | OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16)); | |
233 | OUT_RING(0); | |
234 | ADVANCE_LP_RING(); | |
235 | } else { | |
236 | BEGIN_LP_RING(6); | |
ac741ab7 | 237 | |
af6061af DA |
238 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
239 | OUT_RING(0); | |
240 | OUT_RING(0); | |
241 | OUT_RING(sarea_priv->width | sarea_priv->height << 16); | |
242 | OUT_RING(sarea_priv->width | sarea_priv->height << 16); | |
243 | OUT_RING(0); | |
244 | ||
245 | ADVANCE_LP_RING(); | |
246 | } | |
247 | ||
248 | sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT; | |
249 | ||
250 | upper[0] = upper[1] = 0; | |
251 | slice[0] = max(sarea_priv->pipeA_h / nhits, 1); | |
252 | slice[1] = max(sarea_priv->pipeB_h / nhits, 1); | |
253 | lower[0] = sarea_priv->pipeA_y + slice[0]; | |
254 | lower[1] = sarea_priv->pipeB_y + slice[0]; | |
3188a24c MD |
255 | |
256 | spin_lock(&dev->drw_lock); | |
257 | ||
258 | /* Emit blits for buffer swaps, partitioning both outputs into as many | |
259 | * slices as there are buffer swaps scheduled in order to avoid tearing | |
260 | * (based on the assumption that a single buffer swap would always | |
261 | * complete before scanout starts). | |
262 | */ | |
263 | for (i = 0; i++ < nhits; | |
264 | upper[0] = lower[0], lower[0] += slice[0], | |
265 | upper[1] = lower[1], lower[1] += slice[1]) { | |
266 | if (i == nhits) | |
267 | lower[0] = lower[1] = sarea_priv->height; | |
268 | ||
269 | list_for_each(hit, &hits) { | |
270 | drm_i915_vbl_swap_t *swap_hit = | |
271 | list_entry(hit, drm_i915_vbl_swap_t, head); | |
c60ce623 | 272 | struct drm_clip_rect *rect; |
9e44af79 | 273 | int num_rects, pipe; |
3188a24c MD |
274 | unsigned short top, bottom; |
275 | ||
276 | drw = drm_get_drawable_info(dev, swap_hit->drw_id); | |
277 | ||
9e44af79 KP |
278 | /* The drawable may have been destroyed since |
279 | * the vblank swap was queued | |
280 | */ | |
3188a24c MD |
281 | if (!drw) |
282 | continue; | |
283 | ||
284 | rect = drw->rects; | |
9e44af79 KP |
285 | pipe = swap_hit->pipe; |
286 | top = upper[pipe]; | |
287 | bottom = lower[pipe]; | |
3188a24c MD |
288 | |
289 | for (num_rects = drw->num_rects; num_rects--; rect++) { | |
290 | int y1 = max(rect->y1, top); | |
291 | int y2 = min(rect->y2, bottom); | |
292 | ||
293 | if (y1 >= y2) | |
294 | continue; | |
295 | ||
296 | BEGIN_LP_RING(8); | |
297 | ||
298 | OUT_RING(cmd); | |
7b832b56 | 299 | OUT_RING(ropcpp | dst_pitch); |
3188a24c MD |
300 | OUT_RING((y1 << 16) | rect->x1); |
301 | OUT_RING((y2 << 16) | rect->x2); | |
af6061af | 302 | OUT_RING(sarea_priv->front_offset); |
3188a24c | 303 | OUT_RING((y1 << 16) | rect->x1); |
7b832b56 | 304 | OUT_RING(src_pitch); |
af6061af | 305 | OUT_RING(sarea_priv->back_offset); |
3188a24c MD |
306 | |
307 | ADVANCE_LP_RING(); | |
308 | } | |
a6b54f3f MD |
309 | } |
310 | } | |
311 | ||
af6061af | 312 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); |
9e44af79 | 313 | mutex_unlock(&dev->struct_mutex); |
3188a24c MD |
314 | |
315 | list_for_each_safe(hit, tmp, &hits) { | |
316 | drm_i915_vbl_swap_t *swap_hit = | |
317 | list_entry(hit, drm_i915_vbl_swap_t, head); | |
318 | ||
319 | list_del(hit); | |
320 | ||
321 | drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER); | |
322 | } | |
a6b54f3f MD |
323 | } |
324 | ||
0a3e67a4 JB |
325 | u32 i915_get_vblank_counter(struct drm_device *dev, int plane) |
326 | { | |
327 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
328 | unsigned long high_frame; | |
329 | unsigned long low_frame; | |
330 | u32 high1, high2, low, count; | |
331 | int pipe; | |
332 | ||
333 | pipe = i915_get_pipe(dev, plane); | |
334 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; | |
335 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
336 | ||
337 | if (!i915_pipe_enabled(dev, pipe)) { | |
338 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); | |
339 | return 0; | |
340 | } | |
341 | ||
342 | /* | |
343 | * High & low register fields aren't synchronized, so make sure | |
344 | * we get a low value that's stable across two reads of the high | |
345 | * register. | |
346 | */ | |
347 | do { | |
348 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
349 | PIPE_FRAME_HIGH_SHIFT); | |
350 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
351 | PIPE_FRAME_LOW_SHIFT); | |
352 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
353 | PIPE_FRAME_HIGH_SHIFT); | |
354 | } while (high1 != high2); | |
355 | ||
356 | count = (high1 << 8) | low; | |
357 | ||
358 | return count; | |
359 | } | |
360 | ||
546b0974 | 361 | void |
9e44af79 | 362 | i915_vblank_work_handler(struct work_struct *work) |
546b0974 | 363 | { |
9e44af79 KP |
364 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
365 | vblank_work); | |
366 | struct drm_device *dev = dev_priv->dev; | |
367 | unsigned long irqflags; | |
368 | ||
369 | if (dev->lock.hw_lock == NULL) { | |
370 | i915_vblank_tasklet(dev); | |
371 | return; | |
372 | } | |
546b0974 | 373 | |
9e44af79 KP |
374 | spin_lock_irqsave(&dev->tasklet_lock, irqflags); |
375 | dev->locked_tasklet_func = i915_vblank_tasklet; | |
376 | spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); | |
377 | ||
378 | /* Try to get the lock now, if this fails, the lock | |
379 | * holder will execute the tasklet during unlock | |
380 | */ | |
381 | if (!drm_lock_take(&dev->lock, DRM_KERNEL_CONTEXT)) | |
382 | return; | |
383 | ||
384 | dev->lock.lock_time = jiffies; | |
385 | atomic_inc(&dev->counts[_DRM_STAT_LOCKS]); | |
386 | ||
387 | spin_lock_irqsave(&dev->tasklet_lock, irqflags); | |
388 | dev->locked_tasklet_func = NULL; | |
389 | spin_unlock_irqrestore(&dev->tasklet_lock, irqflags); | |
546b0974 | 390 | |
546b0974 | 391 | i915_vblank_tasklet(dev); |
9e44af79 | 392 | drm_lock_free(&dev->lock, DRM_KERNEL_CONTEXT); |
546b0974 EA |
393 | } |
394 | ||
1da177e4 LT |
395 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
396 | { | |
84b1fd10 | 397 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 398 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
ed4cb414 | 399 | u32 iir; |
0a3e67a4 JB |
400 | u32 pipea_stats, pipeb_stats; |
401 | int vblank = 0; | |
6e5fca53 | 402 | |
630681d9 EA |
403 | atomic_inc(&dev_priv->irq_received); |
404 | ||
ed4cb414 EA |
405 | if (dev->pdev->msi_enabled) |
406 | I915_WRITE(IMR, ~0); | |
407 | iir = I915_READ(IIR); | |
a6b54f3f | 408 | |
ed4cb414 EA |
409 | if (iir == 0) { |
410 | if (dev->pdev->msi_enabled) { | |
411 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
412 | (void) I915_READ(IMR); | |
413 | } | |
af6061af | 414 | return IRQ_NONE; |
ed4cb414 | 415 | } |
af6061af | 416 | |
0a3e67a4 JB |
417 | /* |
418 | * Clear the PIPE(A|B)STAT regs before the IIR otherwise | |
419 | * we may get extra interrupts. | |
420 | */ | |
421 | if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) { | |
422 | pipea_stats = I915_READ(PIPEASTAT); | |
423 | if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)) | |
424 | pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | | |
425 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
426 | else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| | |
427 | PIPE_VBLANK_INTERRUPT_STATUS)) { | |
428 | vblank++; | |
429 | drm_handle_vblank(dev, i915_get_plane(dev, 0)); | |
430 | } | |
af6061af | 431 | |
0a3e67a4 JB |
432 | I915_WRITE(PIPEASTAT, pipea_stats); |
433 | } | |
434 | if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) { | |
435 | pipeb_stats = I915_READ(PIPEBSTAT); | |
436 | /* Ack the event */ | |
437 | I915_WRITE(PIPEBSTAT, pipeb_stats); | |
438 | ||
439 | /* The vblank interrupt gets enabled even if we didn't ask for | |
440 | it, so make sure it's shut down again */ | |
441 | if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)) | |
442 | pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | | |
443 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
444 | else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| | |
445 | PIPE_VBLANK_INTERRUPT_STATUS)) { | |
446 | vblank++; | |
447 | drm_handle_vblank(dev, i915_get_plane(dev, 1)); | |
448 | } | |
af6061af | 449 | |
0a3e67a4 JB |
450 | if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) |
451 | opregion_asle_intr(dev); | |
452 | I915_WRITE(PIPEBSTAT, pipeb_stats); | |
0d6aa60b | 453 | } |
1da177e4 | 454 | |
673a394b EA |
455 | I915_WRITE(IIR, iir); |
456 | if (dev->pdev->msi_enabled) | |
457 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
458 | (void) I915_READ(IIR); /* Flush posted writes */ | |
8ee1c3db | 459 | |
c99b058f KH |
460 | if (dev_priv->sarea_priv) |
461 | dev_priv->sarea_priv->last_dispatch = | |
462 | READ_BREADCRUMB(dev_priv); | |
0a3e67a4 | 463 | |
673a394b EA |
464 | if (iir & I915_USER_INTERRUPT) { |
465 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); | |
466 | DRM_WAKEUP(&dev_priv->irq_queue); | |
467 | } | |
468 | ||
469 | if (iir & I915_ASLE_INTERRUPT) | |
470 | opregion_asle_intr(dev); | |
0a3e67a4 | 471 | |
9e44af79 KP |
472 | if (vblank && dev_priv->swaps_pending > 0) |
473 | schedule_work(&dev_priv->vblank_work); | |
8ee1c3db | 474 | |
1da177e4 LT |
475 | return IRQ_HANDLED; |
476 | } | |
477 | ||
af6061af | 478 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
479 | { |
480 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1da177e4 LT |
481 | RING_LOCALS; |
482 | ||
483 | i915_kernel_lost_context(dev); | |
484 | ||
3e684eae | 485 | DRM_DEBUG("\n"); |
1da177e4 | 486 | |
c99b058f | 487 | dev_priv->counter++; |
c29b669c | 488 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f KH |
489 | dev_priv->counter = 1; |
490 | if (dev_priv->sarea_priv) | |
491 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c AH |
492 | |
493 | BEGIN_LP_RING(6); | |
585fb111 JB |
494 | OUT_RING(MI_STORE_DWORD_INDEX); |
495 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); | |
c29b669c AH |
496 | OUT_RING(dev_priv->counter); |
497 | OUT_RING(0); | |
1da177e4 | 498 | OUT_RING(0); |
585fb111 | 499 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 500 | ADVANCE_LP_RING(); |
bc5f4523 | 501 | |
c29b669c | 502 | return dev_priv->counter; |
1da177e4 LT |
503 | } |
504 | ||
673a394b | 505 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
506 | { |
507 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 508 | unsigned long irqflags; |
ed4cb414 | 509 | |
e9d21d7f | 510 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
511 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) |
512 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
e9d21d7f | 513 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
514 | } |
515 | ||
0a3e67a4 | 516 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
517 | { |
518 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 519 | unsigned long irqflags; |
ed4cb414 | 520 | |
e9d21d7f | 521 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
522 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
523 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) | |
524 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
e9d21d7f | 525 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
526 | } |
527 | ||
84b1fd10 | 528 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
529 | { |
530 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
531 | int ret = 0; | |
532 | ||
3e684eae | 533 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
534 | READ_BREADCRUMB(dev_priv)); |
535 | ||
ed4cb414 | 536 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
c99b058f KH |
537 | if (dev_priv->sarea_priv) { |
538 | dev_priv->sarea_priv->last_dispatch = | |
539 | READ_BREADCRUMB(dev_priv); | |
540 | } | |
1da177e4 | 541 | return 0; |
ed4cb414 | 542 | } |
1da177e4 | 543 | |
c99b058f KH |
544 | if (dev_priv->sarea_priv) |
545 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 546 | |
ed4cb414 | 547 | i915_user_irq_get(dev); |
1da177e4 LT |
548 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
549 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 550 | i915_user_irq_put(dev); |
1da177e4 | 551 | |
20caafa6 | 552 | if (ret == -EBUSY) { |
3e684eae | 553 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
554 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
555 | } | |
556 | ||
c99b058f KH |
557 | if (dev_priv->sarea_priv) |
558 | dev_priv->sarea_priv->last_dispatch = | |
559 | READ_BREADCRUMB(dev_priv); | |
af6061af DA |
560 | |
561 | return ret; | |
562 | } | |
563 | ||
1da177e4 LT |
564 | /* Needs the lock as it touches the ring. |
565 | */ | |
c153f45f EA |
566 | int i915_irq_emit(struct drm_device *dev, void *data, |
567 | struct drm_file *file_priv) | |
1da177e4 | 568 | { |
1da177e4 | 569 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 570 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
571 | int result; |
572 | ||
546b0974 | 573 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 LT |
574 | |
575 | if (!dev_priv) { | |
3e684eae | 576 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 577 | return -EINVAL; |
1da177e4 | 578 | } |
546b0974 | 579 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 580 | result = i915_emit_irq(dev); |
546b0974 | 581 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 582 | |
c153f45f | 583 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 584 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 585 | return -EFAULT; |
1da177e4 LT |
586 | } |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
591 | /* Doesn't need the hardware lock. | |
592 | */ | |
c153f45f EA |
593 | int i915_irq_wait(struct drm_device *dev, void *data, |
594 | struct drm_file *file_priv) | |
1da177e4 | 595 | { |
1da177e4 | 596 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 597 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
598 | |
599 | if (!dev_priv) { | |
3e684eae | 600 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 601 | return -EINVAL; |
1da177e4 LT |
602 | } |
603 | ||
c153f45f | 604 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
605 | } |
606 | ||
0a3e67a4 JB |
607 | int i915_enable_vblank(struct drm_device *dev, int plane) |
608 | { | |
609 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
610 | int pipe = i915_get_pipe(dev, plane); | |
611 | u32 pipestat_reg = 0; | |
612 | u32 pipestat; | |
e9d21d7f KP |
613 | u32 interrupt = 0; |
614 | unsigned long irqflags; | |
0a3e67a4 JB |
615 | |
616 | switch (pipe) { | |
617 | case 0: | |
618 | pipestat_reg = PIPEASTAT; | |
e9d21d7f | 619 | interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; |
0a3e67a4 JB |
620 | break; |
621 | case 1: | |
622 | pipestat_reg = PIPEBSTAT; | |
e9d21d7f | 623 | interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
0a3e67a4 JB |
624 | break; |
625 | default: | |
626 | DRM_ERROR("tried to enable vblank on non-existent pipe %d\n", | |
627 | pipe); | |
e9d21d7f | 628 | return 0; |
0a3e67a4 JB |
629 | } |
630 | ||
e9d21d7f | 631 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
053d7f24 EA |
632 | /* Enabling vblank events in IMR comes before PIPESTAT write, or |
633 | * there's a race where the PIPESTAT vblank bit gets set to 1, so | |
634 | * the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in | |
635 | * ISR flashes to 1, but the IIR bit doesn't get set to 1 because | |
636 | * IMR masks it. It doesn't ever get set after we clear the masking | |
637 | * in IMR because the ISR bit is edge, not level-triggered, on the | |
638 | * OR of PIPESTAT bits. | |
639 | */ | |
640 | i915_enable_irq(dev_priv, interrupt); | |
e9d21d7f KP |
641 | pipestat = I915_READ(pipestat_reg); |
642 | if (IS_I965G(dev)) | |
643 | pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
644 | else | |
645 | pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE; | |
646 | /* Clear any stale interrupt status */ | |
647 | pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS | | |
648 | PIPE_VBLANK_INTERRUPT_STATUS); | |
649 | I915_WRITE(pipestat_reg, pipestat); | |
650 | (void) I915_READ(pipestat_reg); /* Posting read */ | |
e9d21d7f | 651 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
652 | |
653 | return 0; | |
654 | } | |
655 | ||
656 | void i915_disable_vblank(struct drm_device *dev, int plane) | |
657 | { | |
658 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
659 | int pipe = i915_get_pipe(dev, plane); | |
660 | u32 pipestat_reg = 0; | |
661 | u32 pipestat; | |
e9d21d7f KP |
662 | u32 interrupt = 0; |
663 | unsigned long irqflags; | |
0a3e67a4 JB |
664 | |
665 | switch (pipe) { | |
666 | case 0: | |
667 | pipestat_reg = PIPEASTAT; | |
e9d21d7f | 668 | interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; |
0a3e67a4 JB |
669 | break; |
670 | case 1: | |
671 | pipestat_reg = PIPEBSTAT; | |
e9d21d7f | 672 | interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
0a3e67a4 JB |
673 | break; |
674 | default: | |
675 | DRM_ERROR("tried to disable vblank on non-existent pipe %d\n", | |
676 | pipe); | |
e9d21d7f | 677 | return; |
0a3e67a4 JB |
678 | break; |
679 | } | |
680 | ||
e9d21d7f KP |
681 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
682 | i915_disable_irq(dev_priv, interrupt); | |
683 | pipestat = I915_READ(pipestat_reg); | |
684 | pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | | |
685 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
686 | /* Clear any stale interrupt status */ | |
687 | pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS | | |
688 | PIPE_VBLANK_INTERRUPT_STATUS); | |
689 | I915_WRITE(pipestat_reg, pipestat); | |
690 | (void) I915_READ(pipestat_reg); /* Posting read */ | |
691 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
0a3e67a4 JB |
692 | } |
693 | ||
702880f2 DA |
694 | /* Set the vblank monitor pipe |
695 | */ | |
c153f45f EA |
696 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
697 | struct drm_file *file_priv) | |
702880f2 | 698 | { |
702880f2 | 699 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
700 | |
701 | if (!dev_priv) { | |
3e684eae | 702 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 703 | return -EINVAL; |
702880f2 DA |
704 | } |
705 | ||
5b51694a | 706 | return 0; |
702880f2 DA |
707 | } |
708 | ||
c153f45f EA |
709 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
710 | struct drm_file *file_priv) | |
702880f2 | 711 | { |
702880f2 | 712 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 713 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
714 | |
715 | if (!dev_priv) { | |
3e684eae | 716 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 717 | return -EINVAL; |
702880f2 DA |
718 | } |
719 | ||
0a3e67a4 | 720 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 721 | |
702880f2 DA |
722 | return 0; |
723 | } | |
724 | ||
a6b54f3f MD |
725 | /** |
726 | * Schedule buffer swap at given vertical blank. | |
727 | */ | |
c153f45f EA |
728 | int i915_vblank_swap(struct drm_device *dev, void *data, |
729 | struct drm_file *file_priv) | |
a6b54f3f | 730 | { |
a6b54f3f | 731 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 732 | drm_i915_vblank_swap_t *swap = data; |
9e44af79 | 733 | drm_i915_vbl_swap_t *vbl_swap, *vbl_old; |
0a3e67a4 | 734 | unsigned int pipe, seqtype, curseq, plane; |
a0b136bb | 735 | unsigned long irqflags; |
a6b54f3f | 736 | struct list_head *list; |
0a3e67a4 | 737 | int ret; |
a6b54f3f | 738 | |
c99b058f | 739 | if (!dev_priv || !dev_priv->sarea_priv) { |
a6b54f3f | 740 | DRM_ERROR("%s called with no initialization\n", __func__); |
20caafa6 | 741 | return -EINVAL; |
a6b54f3f MD |
742 | } |
743 | ||
af6061af | 744 | if (dev_priv->sarea_priv->rotation) { |
a6b54f3f | 745 | DRM_DEBUG("Rotation not supported\n"); |
20caafa6 | 746 | return -EINVAL; |
a6b54f3f MD |
747 | } |
748 | ||
c153f45f | 749 | if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE | |
af6061af | 750 | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) { |
c153f45f | 751 | DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype); |
20caafa6 | 752 | return -EINVAL; |
541f29aa MD |
753 | } |
754 | ||
0a3e67a4 JB |
755 | plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; |
756 | pipe = i915_get_pipe(dev, plane); | |
541f29aa | 757 | |
c153f45f | 758 | seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); |
541f29aa | 759 | |
541f29aa MD |
760 | if (!(dev_priv->vblank_pipe & (1 << pipe))) { |
761 | DRM_ERROR("Invalid pipe %d\n", pipe); | |
20caafa6 | 762 | return -EINVAL; |
a6b54f3f MD |
763 | } |
764 | ||
765 | spin_lock_irqsave(&dev->drw_lock, irqflags); | |
766 | ||
c153f45f | 767 | if (!drm_get_drawable_info(dev, swap->drawable)) { |
a6b54f3f | 768 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); |
c153f45f | 769 | DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable); |
20caafa6 | 770 | return -EINVAL; |
a6b54f3f MD |
771 | } |
772 | ||
773 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); | |
774 | ||
0a3e67a4 JB |
775 | /* |
776 | * We take the ref here and put it when the swap actually completes | |
777 | * in the tasklet. | |
778 | */ | |
779 | ret = drm_vblank_get(dev, pipe); | |
780 | if (ret) | |
781 | return ret; | |
782 | curseq = drm_vblank_count(dev, pipe); | |
541f29aa | 783 | |
2228ed67 | 784 | if (seqtype == _DRM_VBLANK_RELATIVE) |
c153f45f | 785 | swap->sequence += curseq; |
2228ed67 | 786 | |
c153f45f EA |
787 | if ((curseq - swap->sequence) <= (1<<23)) { |
788 | if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) { | |
789 | swap->sequence = curseq + 1; | |
2228ed67 | 790 | } else { |
541f29aa | 791 | DRM_DEBUG("Missed target sequence\n"); |
0a3e67a4 | 792 | drm_vblank_put(dev, pipe); |
20caafa6 | 793 | return -EINVAL; |
541f29aa | 794 | } |
541f29aa MD |
795 | } |
796 | ||
9e44af79 KP |
797 | vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER); |
798 | ||
799 | if (!vbl_swap) { | |
800 | DRM_ERROR("Failed to allocate memory to queue swap\n"); | |
801 | drm_vblank_put(dev, pipe); | |
802 | return -ENOMEM; | |
803 | } | |
804 | ||
805 | vbl_swap->drw_id = swap->drawable; | |
806 | vbl_swap->pipe = pipe; | |
807 | vbl_swap->sequence = swap->sequence; | |
808 | ||
2228ed67 MD |
809 | spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); |
810 | ||
a6b54f3f | 811 | list_for_each(list, &dev_priv->vbl_swaps.head) { |
9e44af79 | 812 | vbl_old = list_entry(list, drm_i915_vbl_swap_t, head); |
a6b54f3f | 813 | |
9e44af79 KP |
814 | if (vbl_old->drw_id == swap->drawable && |
815 | vbl_old->pipe == pipe && | |
816 | vbl_old->sequence == swap->sequence) { | |
a6b54f3f | 817 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); |
35ad68c1 | 818 | drm_vblank_put(dev, pipe); |
9e44af79 | 819 | drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER); |
a6b54f3f MD |
820 | DRM_DEBUG("Already scheduled\n"); |
821 | return 0; | |
822 | } | |
823 | } | |
824 | ||
9e44af79 | 825 | if (dev_priv->swaps_pending >= 10) { |
21fa60ed | 826 | DRM_DEBUG("Too many swaps queued\n"); |
9e44af79 KP |
827 | DRM_DEBUG(" pipe 0: %d pipe 1: %d\n", |
828 | drm_vblank_count(dev, i915_get_plane(dev, 0)), | |
829 | drm_vblank_count(dev, i915_get_plane(dev, 1))); | |
830 | ||
831 | list_for_each(list, &dev_priv->vbl_swaps.head) { | |
832 | vbl_old = list_entry(list, drm_i915_vbl_swap_t, head); | |
833 | DRM_DEBUG("\tdrw %x pipe %d seq %x\n", | |
834 | vbl_old->drw_id, vbl_old->pipe, | |
835 | vbl_old->sequence); | |
836 | } | |
837 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); | |
0a3e67a4 | 838 | drm_vblank_put(dev, pipe); |
9e44af79 | 839 | drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER); |
20caafa6 | 840 | return -EBUSY; |
21fa60ed MD |
841 | } |
842 | ||
d5b0d1b5 | 843 | list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head); |
a6b54f3f MD |
844 | dev_priv->swaps_pending++; |
845 | ||
846 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); | |
847 | ||
848 | return 0; | |
849 | } | |
850 | ||
1da177e4 LT |
851 | /* drm_dma.h hooks |
852 | */ | |
84b1fd10 | 853 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
854 | { |
855 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
856 | ||
0a3e67a4 JB |
857 | I915_WRITE(HWSTAM, 0xeffe); |
858 | I915_WRITE(IMR, 0xffffffff); | |
ed4cb414 | 859 | I915_WRITE(IER, 0x0); |
1da177e4 LT |
860 | } |
861 | ||
0a3e67a4 | 862 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
863 | { |
864 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
0a3e67a4 | 865 | int ret, num_pipes = 2; |
1da177e4 | 866 | |
a6399bdd | 867 | spin_lock_init(&dev_priv->swaps_lock); |
a6b54f3f | 868 | INIT_LIST_HEAD(&dev_priv->vbl_swaps.head); |
9e44af79 | 869 | INIT_WORK(&dev_priv->vblank_work, i915_vblank_work_handler); |
a6b54f3f MD |
870 | dev_priv->swaps_pending = 0; |
871 | ||
ed4cb414 EA |
872 | /* Set initial unmasked IRQs to just the selected vblank pipes. */ |
873 | dev_priv->irq_mask_reg = ~0; | |
0a3e67a4 JB |
874 | |
875 | ret = drm_vblank_init(dev, num_pipes); | |
876 | if (ret) | |
877 | return ret; | |
878 | ||
879 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
880 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; | |
881 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
882 | ||
883 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
ed4cb414 | 884 | |
8ee1c3db MG |
885 | dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK; |
886 | ||
ed4cb414 EA |
887 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
888 | I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); | |
889 | (void) I915_READ(IER); | |
890 | ||
8ee1c3db | 891 | opregion_enable_asle(dev); |
1da177e4 | 892 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
0a3e67a4 JB |
893 | |
894 | return 0; | |
1da177e4 LT |
895 | } |
896 | ||
84b1fd10 | 897 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
898 | { |
899 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
0a3e67a4 | 900 | u32 temp; |
91e3738e | 901 | |
1da177e4 LT |
902 | if (!dev_priv) |
903 | return; | |
904 | ||
0a3e67a4 JB |
905 | dev_priv->vblank_pipe = 0; |
906 | ||
907 | I915_WRITE(HWSTAM, 0xffffffff); | |
908 | I915_WRITE(IMR, 0xffffffff); | |
ed4cb414 | 909 | I915_WRITE(IER, 0x0); |
af6061af | 910 | |
0a3e67a4 JB |
911 | temp = I915_READ(PIPEASTAT); |
912 | I915_WRITE(PIPEASTAT, temp); | |
913 | temp = I915_READ(PIPEBSTAT); | |
914 | I915_WRITE(PIPEBSTAT, temp); | |
ed4cb414 EA |
915 | temp = I915_READ(IIR); |
916 | I915_WRITE(IIR, temp); | |
1da177e4 | 917 | } |