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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | ||
1da177e4 | 34 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 35 | |
7c463586 KP |
36 | /** |
37 | * Interrupts that are always left unmasked. | |
38 | * | |
39 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
40 | * we leave them always unmasked in IMR and then control enabling them through | |
41 | * PIPESTAT alone. | |
42 | */ | |
43 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ | |
44 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
45 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) | |
46 | ||
47 | /** Interrupts that we mask and unmask at runtime. */ | |
48 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | |
49 | ||
50 | /** These are all of the interrupts used by the driver */ | |
51 | #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \ | |
52 | I915_INTERRUPT_ENABLE_VAR) | |
ed4cb414 | 53 | |
8ee1c3db | 54 | void |
ed4cb414 EA |
55 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
56 | { | |
57 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
58 | dev_priv->irq_mask_reg &= ~mask; | |
59 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
60 | (void) I915_READ(IMR); | |
61 | } | |
62 | } | |
63 | ||
64 | static inline void | |
65 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
66 | { | |
67 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
68 | dev_priv->irq_mask_reg |= mask; | |
69 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
70 | (void) I915_READ(IMR); | |
71 | } | |
72 | } | |
73 | ||
7c463586 KP |
74 | static inline u32 |
75 | i915_pipestat(int pipe) | |
76 | { | |
77 | if (pipe == 0) | |
78 | return PIPEASTAT; | |
79 | if (pipe == 1) | |
80 | return PIPEBSTAT; | |
81 | BUG_ON(1); | |
82 | } | |
83 | ||
84 | void | |
85 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
86 | { | |
87 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
88 | u32 reg = i915_pipestat(pipe); | |
89 | ||
90 | dev_priv->pipestat[pipe] |= mask; | |
91 | /* Enable the interrupt, clear any pending status */ | |
92 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
93 | (void) I915_READ(reg); | |
94 | } | |
95 | } | |
96 | ||
97 | void | |
98 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
99 | { | |
100 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
101 | u32 reg = i915_pipestat(pipe); | |
102 | ||
103 | dev_priv->pipestat[pipe] &= ~mask; | |
104 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
105 | (void) I915_READ(reg); | |
106 | } | |
107 | } | |
108 | ||
0a3e67a4 JB |
109 | /** |
110 | * i915_pipe_enabled - check if a pipe is enabled | |
111 | * @dev: DRM device | |
112 | * @pipe: pipe to check | |
113 | * | |
114 | * Reading certain registers when the pipe is disabled can hang the chip. | |
115 | * Use this routine to make sure the PLL is running and the pipe is active | |
116 | * before reading such registers if unsure. | |
117 | */ | |
118 | static int | |
119 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
120 | { | |
121 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
122 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
123 | ||
124 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
125 | return 1; | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
42f52ef8 KP |
130 | /* Called from drm generic code, passed a 'crtc', which |
131 | * we use as a pipe index | |
132 | */ | |
133 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
134 | { |
135 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
136 | unsigned long high_frame; | |
137 | unsigned long low_frame; | |
138 | u32 high1, high2, low, count; | |
0a3e67a4 | 139 | |
0a3e67a4 JB |
140 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
141 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
142 | ||
143 | if (!i915_pipe_enabled(dev, pipe)) { | |
144 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); | |
145 | return 0; | |
146 | } | |
147 | ||
148 | /* | |
149 | * High & low register fields aren't synchronized, so make sure | |
150 | * we get a low value that's stable across two reads of the high | |
151 | * register. | |
152 | */ | |
153 | do { | |
154 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
155 | PIPE_FRAME_HIGH_SHIFT); | |
156 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
157 | PIPE_FRAME_LOW_SHIFT); | |
158 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
159 | PIPE_FRAME_HIGH_SHIFT); | |
160 | } while (high1 != high2); | |
161 | ||
162 | count = (high1 << 8) | low; | |
163 | ||
164 | return count; | |
165 | } | |
166 | ||
1da177e4 LT |
167 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
168 | { | |
84b1fd10 | 169 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 170 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
ed4cb414 | 171 | u32 iir; |
7c463586 | 172 | u32 pipea_stats = 0, pipeb_stats = 0; |
0a3e67a4 | 173 | int vblank = 0; |
7c463586 | 174 | unsigned long irqflags; |
6e5fca53 | 175 | |
7c463586 | 176 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
630681d9 EA |
177 | atomic_inc(&dev_priv->irq_received); |
178 | ||
ed4cb414 EA |
179 | if (dev->pdev->msi_enabled) |
180 | I915_WRITE(IMR, ~0); | |
181 | iir = I915_READ(IIR); | |
a6b54f3f | 182 | |
ed4cb414 EA |
183 | if (iir == 0) { |
184 | if (dev->pdev->msi_enabled) { | |
185 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
186 | (void) I915_READ(IMR); | |
187 | } | |
7c463586 | 188 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
af6061af | 189 | return IRQ_NONE; |
ed4cb414 | 190 | } |
af6061af | 191 | |
0a3e67a4 | 192 | /* |
7c463586 | 193 | * Clear the PIPE(A|B)STAT regs before the IIR |
0a3e67a4 JB |
194 | */ |
195 | if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) { | |
196 | pipea_stats = I915_READ(PIPEASTAT); | |
0a3e67a4 JB |
197 | I915_WRITE(PIPEASTAT, pipea_stats); |
198 | } | |
7c463586 | 199 | |
0a3e67a4 JB |
200 | if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) { |
201 | pipeb_stats = I915_READ(PIPEBSTAT); | |
0a3e67a4 | 202 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
0d6aa60b | 203 | } |
1da177e4 | 204 | |
673a394b EA |
205 | I915_WRITE(IIR, iir); |
206 | if (dev->pdev->msi_enabled) | |
207 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
208 | (void) I915_READ(IIR); /* Flush posted writes */ | |
8ee1c3db | 209 | |
7c463586 KP |
210 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
211 | ||
c99b058f KH |
212 | if (dev_priv->sarea_priv) |
213 | dev_priv->sarea_priv->last_dispatch = | |
214 | READ_BREADCRUMB(dev_priv); | |
0a3e67a4 | 215 | |
673a394b EA |
216 | if (iir & I915_USER_INTERRUPT) { |
217 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); | |
218 | DRM_WAKEUP(&dev_priv->irq_queue); | |
219 | } | |
220 | ||
7c463586 KP |
221 | if (pipea_stats & I915_VBLANK_INTERRUPT_STATUS) { |
222 | vblank++; | |
223 | drm_handle_vblank(dev, 0); | |
224 | } | |
225 | ||
226 | if (pipeb_stats & I915_VBLANK_INTERRUPT_STATUS) { | |
227 | vblank++; | |
228 | drm_handle_vblank(dev, 1); | |
229 | } | |
230 | ||
231 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || | |
232 | (iir & I915_ASLE_INTERRUPT)) | |
673a394b | 233 | opregion_asle_intr(dev); |
0a3e67a4 | 234 | |
1da177e4 LT |
235 | return IRQ_HANDLED; |
236 | } | |
237 | ||
af6061af | 238 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
239 | { |
240 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1da177e4 LT |
241 | RING_LOCALS; |
242 | ||
243 | i915_kernel_lost_context(dev); | |
244 | ||
3e684eae | 245 | DRM_DEBUG("\n"); |
1da177e4 | 246 | |
c99b058f | 247 | dev_priv->counter++; |
c29b669c | 248 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f KH |
249 | dev_priv->counter = 1; |
250 | if (dev_priv->sarea_priv) | |
251 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 252 | |
0baf823a | 253 | BEGIN_LP_RING(4); |
585fb111 | 254 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 255 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 256 | OUT_RING(dev_priv->counter); |
585fb111 | 257 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 258 | ADVANCE_LP_RING(); |
bc5f4523 | 259 | |
c29b669c | 260 | return dev_priv->counter; |
1da177e4 LT |
261 | } |
262 | ||
673a394b | 263 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
264 | { |
265 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 266 | unsigned long irqflags; |
ed4cb414 | 267 | |
e9d21d7f | 268 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
269 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) |
270 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
e9d21d7f | 271 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
272 | } |
273 | ||
0a3e67a4 | 274 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
275 | { |
276 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 277 | unsigned long irqflags; |
ed4cb414 | 278 | |
e9d21d7f | 279 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
280 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
281 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) | |
282 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
e9d21d7f | 283 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
284 | } |
285 | ||
84b1fd10 | 286 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
287 | { |
288 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
289 | int ret = 0; | |
290 | ||
3e684eae | 291 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
292 | READ_BREADCRUMB(dev_priv)); |
293 | ||
ed4cb414 | 294 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
c99b058f KH |
295 | if (dev_priv->sarea_priv) { |
296 | dev_priv->sarea_priv->last_dispatch = | |
297 | READ_BREADCRUMB(dev_priv); | |
298 | } | |
1da177e4 | 299 | return 0; |
ed4cb414 | 300 | } |
1da177e4 | 301 | |
c99b058f KH |
302 | if (dev_priv->sarea_priv) |
303 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 304 | |
ed4cb414 | 305 | i915_user_irq_get(dev); |
1da177e4 LT |
306 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
307 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 308 | i915_user_irq_put(dev); |
1da177e4 | 309 | |
20caafa6 | 310 | if (ret == -EBUSY) { |
3e684eae | 311 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
312 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
313 | } | |
314 | ||
c99b058f KH |
315 | if (dev_priv->sarea_priv) |
316 | dev_priv->sarea_priv->last_dispatch = | |
317 | READ_BREADCRUMB(dev_priv); | |
af6061af DA |
318 | |
319 | return ret; | |
320 | } | |
321 | ||
1da177e4 LT |
322 | /* Needs the lock as it touches the ring. |
323 | */ | |
c153f45f EA |
324 | int i915_irq_emit(struct drm_device *dev, void *data, |
325 | struct drm_file *file_priv) | |
1da177e4 | 326 | { |
1da177e4 | 327 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 328 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
329 | int result; |
330 | ||
546b0974 | 331 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 LT |
332 | |
333 | if (!dev_priv) { | |
3e684eae | 334 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 335 | return -EINVAL; |
1da177e4 | 336 | } |
546b0974 | 337 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 338 | result = i915_emit_irq(dev); |
546b0974 | 339 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 340 | |
c153f45f | 341 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 342 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 343 | return -EFAULT; |
1da177e4 LT |
344 | } |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
349 | /* Doesn't need the hardware lock. | |
350 | */ | |
c153f45f EA |
351 | int i915_irq_wait(struct drm_device *dev, void *data, |
352 | struct drm_file *file_priv) | |
1da177e4 | 353 | { |
1da177e4 | 354 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 355 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
356 | |
357 | if (!dev_priv) { | |
3e684eae | 358 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 359 | return -EINVAL; |
1da177e4 LT |
360 | } |
361 | ||
c153f45f | 362 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
363 | } |
364 | ||
42f52ef8 KP |
365 | /* Called from drm generic code, passed 'crtc' which |
366 | * we use as a pipe index | |
367 | */ | |
368 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
369 | { |
370 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 371 | unsigned long irqflags; |
0a3e67a4 | 372 | |
e9d21d7f | 373 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
e9d21d7f | 374 | if (IS_I965G(dev)) |
7c463586 KP |
375 | i915_enable_pipestat(dev_priv, pipe, |
376 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 377 | else |
7c463586 KP |
378 | i915_enable_pipestat(dev_priv, pipe, |
379 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 380 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
381 | return 0; |
382 | } | |
383 | ||
42f52ef8 KP |
384 | /* Called from drm generic code, passed 'crtc' which |
385 | * we use as a pipe index | |
386 | */ | |
387 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
388 | { |
389 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 390 | unsigned long irqflags; |
0a3e67a4 | 391 | |
e9d21d7f | 392 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
7c463586 KP |
393 | i915_disable_pipestat(dev_priv, pipe, |
394 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
395 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 396 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
397 | } |
398 | ||
702880f2 DA |
399 | /* Set the vblank monitor pipe |
400 | */ | |
c153f45f EA |
401 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
402 | struct drm_file *file_priv) | |
702880f2 | 403 | { |
702880f2 | 404 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
405 | |
406 | if (!dev_priv) { | |
3e684eae | 407 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 408 | return -EINVAL; |
702880f2 DA |
409 | } |
410 | ||
5b51694a | 411 | return 0; |
702880f2 DA |
412 | } |
413 | ||
c153f45f EA |
414 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
415 | struct drm_file *file_priv) | |
702880f2 | 416 | { |
702880f2 | 417 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 418 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
419 | |
420 | if (!dev_priv) { | |
3e684eae | 421 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 422 | return -EINVAL; |
702880f2 DA |
423 | } |
424 | ||
0a3e67a4 | 425 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 426 | |
702880f2 DA |
427 | return 0; |
428 | } | |
429 | ||
a6b54f3f MD |
430 | /** |
431 | * Schedule buffer swap at given vertical blank. | |
432 | */ | |
c153f45f EA |
433 | int i915_vblank_swap(struct drm_device *dev, void *data, |
434 | struct drm_file *file_priv) | |
a6b54f3f | 435 | { |
bd95e0a4 EA |
436 | /* The delayed swap mechanism was fundamentally racy, and has been |
437 | * removed. The model was that the client requested a delayed flip/swap | |
438 | * from the kernel, then waited for vblank before continuing to perform | |
439 | * rendering. The problem was that the kernel might wake the client | |
440 | * up before it dispatched the vblank swap (since the lock has to be | |
441 | * held while touching the ringbuffer), in which case the client would | |
442 | * clear and start the next frame before the swap occurred, and | |
443 | * flicker would occur in addition to likely missing the vblank. | |
444 | * | |
445 | * In the absence of this ioctl, userland falls back to a correct path | |
446 | * of waiting for a vblank, then dispatching the swap on its own. | |
447 | * Context switching to userland and back is plenty fast enough for | |
448 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 449 | */ |
bd95e0a4 | 450 | return -EINVAL; |
a6b54f3f MD |
451 | } |
452 | ||
1da177e4 LT |
453 | /* drm_dma.h hooks |
454 | */ | |
84b1fd10 | 455 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
456 | { |
457 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
458 | ||
0a3e67a4 | 459 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
460 | I915_WRITE(PIPEASTAT, 0); |
461 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 462 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 463 | I915_WRITE(IER, 0x0); |
7c463586 | 464 | (void) I915_READ(IER); |
1da177e4 LT |
465 | } |
466 | ||
0a3e67a4 | 467 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
468 | { |
469 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
0a3e67a4 | 470 | int ret, num_pipes = 2; |
1da177e4 | 471 | |
0a3e67a4 JB |
472 | ret = drm_vblank_init(dev, num_pipes); |
473 | if (ret) | |
474 | return ret; | |
475 | ||
476 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
0a3e67a4 JB |
477 | |
478 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
ed4cb414 | 479 | |
7c463586 KP |
480 | /* Unmask the interrupts that we always want on. */ |
481 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
482 | ||
483 | dev_priv->pipestat[0] = 0; | |
484 | dev_priv->pipestat[1] = 0; | |
485 | ||
486 | /* Disable pipe interrupt enables, clear pending pipe status */ | |
487 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); | |
488 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
489 | /* Clear pending interrupt status */ | |
490 | I915_WRITE(IIR, I915_READ(IIR)); | |
8ee1c3db | 491 | |
ed4cb414 | 492 | I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); |
7c463586 | 493 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
ed4cb414 EA |
494 | (void) I915_READ(IER); |
495 | ||
8ee1c3db | 496 | opregion_enable_asle(dev); |
1da177e4 | 497 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
0a3e67a4 JB |
498 | |
499 | return 0; | |
1da177e4 LT |
500 | } |
501 | ||
84b1fd10 | 502 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
503 | { |
504 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 505 | |
1da177e4 LT |
506 | if (!dev_priv) |
507 | return; | |
508 | ||
0a3e67a4 JB |
509 | dev_priv->vblank_pipe = 0; |
510 | ||
511 | I915_WRITE(HWSTAM, 0xffffffff); | |
7c463586 KP |
512 | I915_WRITE(PIPEASTAT, 0); |
513 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 514 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 515 | I915_WRITE(IER, 0x0); |
af6061af | 516 | |
7c463586 KP |
517 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
518 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
519 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 520 | } |