[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c

/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
 */
/*
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"

#define MAX_NOPID ((u32)~0)

/** These are the interrupts used by the driver */
#define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT |		\
				    I915_ASLE_INTERRUPT |		\
				    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
				    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)

void
i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	if ((dev_priv->irq_mask_reg & mask) != 0) {
		dev_priv->irq_mask_reg &= ~mask;
		I915_WRITE(IMR, dev_priv->irq_mask_reg);
		(void) I915_READ(IMR);
	}
}

static inline void
i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
{
	if ((dev_priv->irq_mask_reg & mask) != mask) {
		dev_priv->irq_mask_reg |= mask;
		I915_WRITE(IMR, dev_priv->irq_mask_reg);
		(void) I915_READ(IMR);
	}
}

/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;

	if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
		return 1;

	return 0;
}

/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long high_frame;
	unsigned long low_frame;
	u32 high1, high2, low, count;

	high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
	low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;

	if (!i915_pipe_enabled(dev, pipe)) {
		DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
		return 0;
	}

	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
		high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
			 PIPE_FRAME_HIGH_SHIFT);
		low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
			PIPE_FRAME_LOW_SHIFT);
		high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
			 PIPE_FRAME_HIGH_SHIFT);
	} while (high1 != high2);

	count = (high1 << 8) | low;

	return count;
}

irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir;
	u32 pipea_stats, pipeb_stats;
	int vblank = 0;

	atomic_inc(&dev_priv->irq_received);

	if (dev->pdev->msi_enabled)
		I915_WRITE(IMR, ~0);
	iir = I915_READ(IIR);

	if (iir == 0) {
		if (dev->pdev->msi_enabled) {
			I915_WRITE(IMR, dev_priv->irq_mask_reg);
			(void) I915_READ(IMR);
		}
		return IRQ_NONE;
	}

	/*
	 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
	 * we may get extra interrupts.
	 */
	if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
		pipea_stats = I915_READ(PIPEASTAT);
		if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A))
			pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
					 PIPE_VBLANK_INTERRUPT_ENABLE);
		else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
					PIPE_VBLANK_INTERRUPT_STATUS)) {
			vblank++;
			drm_handle_vblank(dev, 0);
		}

		I915_WRITE(PIPEASTAT, pipea_stats);
	}
	if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
		pipeb_stats = I915_READ(PIPEBSTAT);
		/* Ack the event */
		I915_WRITE(PIPEBSTAT, pipeb_stats);

		/* The vblank interrupt gets enabled even if we didn't ask for
		   it, so make sure it's shut down again */
		if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B))
			pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
					 PIPE_VBLANK_INTERRUPT_ENABLE);
		else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
					PIPE_VBLANK_INTERRUPT_STATUS)) {
			vblank++;
			drm_handle_vblank(dev, 1);
		}

		if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS)
			opregion_asle_intr(dev);
		I915_WRITE(PIPEBSTAT, pipeb_stats);
	}

	I915_WRITE(IIR, iir);
	if (dev->pdev->msi_enabled)
		I915_WRITE(IMR, dev_priv->irq_mask_reg);
	(void) I915_READ(IIR); /* Flush posted writes */

	if (dev_priv->sarea_priv)
		dev_priv->sarea_priv->last_dispatch =
			READ_BREADCRUMB(dev_priv);

	if (iir & I915_USER_INTERRUPT) {
		dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
		DRM_WAKEUP(&dev_priv->irq_queue);
	}

	if (iir & I915_ASLE_INTERRUPT)
		opregion_asle_intr(dev);

	return IRQ_HANDLED;
}

static int i915_emit_irq(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	RING_LOCALS;

	i915_kernel_lost_context(dev);

	DRM_DEBUG("\n");

	dev_priv->counter++;
	if (dev_priv->counter > 0x7FFFFFFFUL)
		dev_priv->counter = 1;
	if (dev_priv->sarea_priv)
		dev_priv->sarea_priv->last_enqueue = dev_priv->counter;

	BEGIN_LP_RING(4);
	OUT_RING(MI_STORE_DWORD_INDEX);
	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
	OUT_RING(dev_priv->counter);
	OUT_RING(MI_USER_INTERRUPT);
	ADVANCE_LP_RING();

	return dev_priv->counter;
}

void i915_user_irq_get(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
		i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
}

void i915_user_irq_put(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
	if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
		i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
}

static int i915_wait_irq(struct drm_device * dev, int irq_nr)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int ret = 0;

	DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
		  READ_BREADCRUMB(dev_priv));

	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
		if (dev_priv->sarea_priv) {
			dev_priv->sarea_priv->last_dispatch =
				READ_BREADCRUMB(dev_priv);
		}
		return 0;
	}

	if (dev_priv->sarea_priv)
		dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;

	i915_user_irq_get(dev);
	DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
		    READ_BREADCRUMB(dev_priv) >= irq_nr);
	i915_user_irq_put(dev);

	if (ret == -EBUSY) {
		DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
			  READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
	}

	if (dev_priv->sarea_priv)
		dev_priv->sarea_priv->last_dispatch =
			READ_BREADCRUMB(dev_priv);

	return ret;
}

/* Needs the lock as it touches the ring.
 */
int i915_irq_emit(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_irq_emit_t *emit = data;
	int result;

	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}
	mutex_lock(&dev->struct_mutex);
	result = i915_emit_irq(dev);
	mutex_unlock(&dev->struct_mutex);

	if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
		DRM_ERROR("copy_to_user\n");
		return -EFAULT;
	}

	return 0;
}

/* Doesn't need the hardware lock.
 */
int i915_irq_wait(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_irq_wait_t *irqwait = data;

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	return i915_wait_irq(dev, irqwait->irq_seq);
}

/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
int i915_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32	pipestat_reg = 0;
	u32	pipestat;
	u32	interrupt = 0;
	unsigned long irqflags;

	switch (pipe) {
	case 0:
		pipestat_reg = PIPEASTAT;
		interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
		break;
	case 1:
		pipestat_reg = PIPEBSTAT;
		interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
		break;
	default:
		DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
			  pipe);
		return 0;
	}

	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	/* Enabling vblank events in IMR comes before PIPESTAT write, or
	 * there's a race where the PIPESTAT vblank bit gets set to 1, so
	 * the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in
	 * ISR flashes to 1, but the IIR bit doesn't get set to 1 because
	 * IMR masks it.  It doesn't ever get set after we clear the masking
	 * in IMR because the ISR bit is edge, not level-triggered, on the
	 * OR of PIPESTAT bits.
	 */
	i915_enable_irq(dev_priv, interrupt);
	pipestat = I915_READ(pipestat_reg);
	if (IS_I965G(dev))
		pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
	else
		pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
	/* Clear any stale interrupt status */
	pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
		     PIPE_VBLANK_INTERRUPT_STATUS);
	I915_WRITE(pipestat_reg, pipestat);
	(void) I915_READ(pipestat_reg);	/* Posting read */
	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);

	return 0;
}

/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
void i915_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32	pipestat_reg = 0;
	u32	pipestat;
	u32	interrupt = 0;
	unsigned long irqflags;

	switch (pipe) {
	case 0:
		pipestat_reg = PIPEASTAT;
		interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
		break;
	case 1:
		pipestat_reg = PIPEBSTAT;
		interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
		break;
	default:
		DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
			  pipe);
		return;
		break;
	}

	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	i915_disable_irq(dev_priv, interrupt);
	pipestat = I915_READ(pipestat_reg);
	pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
		      PIPE_VBLANK_INTERRUPT_ENABLE);
	/* Clear any stale interrupt status */
	pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
		     PIPE_VBLANK_INTERRUPT_STATUS);
	I915_WRITE(pipestat_reg, pipestat);
	(void) I915_READ(pipestat_reg);	/* Posting read */
	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
}

/* Set the vblank monitor pipe
 */
int i915_vblank_pipe_set(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	return 0;
}

int i915_vblank_pipe_get(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_vblank_pipe_t *pipe = data;

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;

	return 0;
}

/**
 * Schedule buffer swap at given vertical blank.
 */
int i915_vblank_swap(struct drm_device *dev, void *data,
		     struct drm_file *file_priv)
{
	/* The delayed swap mechanism was fundamentally racy, and has been
	 * removed.  The model was that the client requested a delayed flip/swap
	 * from the kernel, then waited for vblank before continuing to perform
	 * rendering.  The problem was that the kernel might wake the client
	 * up before it dispatched the vblank swap (since the lock has to be
	 * held while touching the ringbuffer), in which case the client would
	 * clear and start the next frame before the swap occurred, and
	 * flicker would occur in addition to likely missing the vblank.
	 *
	 * In the absence of this ioctl, userland falls back to a correct path
	 * of waiting for a vblank, then dispatching the swap on its own.
	 * Context switching to userland and back is plenty fast enough for
	 * meeting the requirements of vblank swapping.
	 */
	return -EINVAL;
}

/* drm_dma.h hooks
*/
void i915_driver_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	I915_WRITE(HWSTAM, 0xeffe);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
}

int i915_driver_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int ret, num_pipes = 2;

	/* Set initial unmasked IRQs to just the selected vblank pipes. */
	dev_priv->irq_mask_reg = ~0;

	ret = drm_vblank_init(dev, num_pipes);
	if (ret)
		return ret;

	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
	dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
	dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;

	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */

	dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK;

	I915_WRITE(IMR, dev_priv->irq_mask_reg);
	I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
	(void) I915_READ(IER);

	opregion_enable_asle(dev);
	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);

	return 0;
}

void i915_driver_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 temp;

	if (!dev_priv)
		return;

	dev_priv->vblank_pipe = 0;

	I915_WRITE(HWSTAM, 0xffffffff);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	temp = I915_READ(PIPEASTAT);
	I915_WRITE(PIPEASTAT, temp);
	temp = I915_READ(PIPEBSTAT);
	I915_WRITE(PIPEBSTAT, temp);
	temp = I915_READ(IIR);
	I915_WRITE(IIR, temp);
}
Commit	Line	Data
0d6aa60b	1	/* i915_irq.c -- IRQ support for the I915 -- linux-c --
1da177e4	2	*/
0d6aa60b	3	/*
1da177e4 LT	4	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
1da177e4 LT	5	* All Rights Reserved.
bc54fd1a DA	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a
	8	* copy of this software and associated documentation files (the
	9	* "Software"), to deal in the Software without restriction, including
	10	* without limitation the rights to use, copy, modify, merge, publish,
	11	* distribute, sub license, and/or sell copies of the Software, and to
	12	* permit persons to whom the Software is furnished to do so, subject to
	13	* the following conditions:
	14	*
	15	* The above copyright notice and this permission notice (including the
	16	* next paragraph) shall be included in all copies or substantial portions
	17	* of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	20	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	21	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	22	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	23	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	24	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	25	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	26	*
0d6aa60b	27	*/
1da177e4 LT	28
	29	#include "drmP.h"
	30	#include "drm.h"
	31	#include "i915_drm.h"
	32	#include "i915_drv.h"
	33
1da177e4	34	#define MAX_NOPID ((u32)~0)
1da177e4	35
ed4cb414 EA	36	/** These are the interrupts used by the driver */
ed4cb414 EA	37	#define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT \| \
8ee1c3db	38	I915_ASLE_INTERRUPT \| \
0a3e67a4	39	I915_DISPLAY_PIPE_A_EVENT_INTERRUPT \| \
8ee1c3db	40	I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
ed4cb414	41
8ee1c3db	42	void
ed4cb414 EA	43	i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
	44	{
	45	if ((dev_priv->irq_mask_reg & mask) != 0) {
	46	dev_priv->irq_mask_reg &= ~mask;
	47	I915_WRITE(IMR, dev_priv->irq_mask_reg);
	48	(void) I915_READ(IMR);
	49	}
	50	}
	51
	52	static inline void
	53	i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
	54	{
	55	if ((dev_priv->irq_mask_reg & mask) != mask) {
	56	dev_priv->irq_mask_reg \|= mask;
	57	I915_WRITE(IMR, dev_priv->irq_mask_reg);
	58	(void) I915_READ(IMR);
	59	}
	60	}
	61
0a3e67a4 JB	62	/**
	63	* i915_pipe_enabled - check if a pipe is enabled
	64	* @dev: DRM device
	65	* @pipe: pipe to check
	66	*
	67	* Reading certain registers when the pipe is disabled can hang the chip.
	68	* Use this routine to make sure the PLL is running and the pipe is active
	69	* before reading such registers if unsure.
	70	*/
	71	static int
	72	i915_pipe_enabled(struct drm_device *dev, int pipe)
	73	{
	74	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
	75	unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
	76
	77	if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
	78	return 1;
	79
	80	return 0;
	81	}
	82
42f52ef8 KP	83	/* Called from drm generic code, passed a 'crtc', which
	84	* we use as a pipe index
	85	*/
	86	u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4 JB	87	{
	88	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
	89	unsigned long high_frame;
	90	unsigned long low_frame;
	91	u32 high1, high2, low, count;
0a3e67a4	92
0a3e67a4 JB	93	high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
	94	low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
	95
	96	if (!i915_pipe_enabled(dev, pipe)) {
	97	DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
	98	return 0;
	99	}
	100
	101	/*
	102	* High & low register fields aren't synchronized, so make sure
	103	* we get a low value that's stable across two reads of the high
	104	* register.
	105	*/
	106	do {
	107	high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
	108	PIPE_FRAME_HIGH_SHIFT);
	109	low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
	110	PIPE_FRAME_LOW_SHIFT);
	111	high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
	112	PIPE_FRAME_HIGH_SHIFT);
	113	} while (high1 != high2);
	114
	115	count = (high1 << 8) \| low;
	116
	117	return count;
	118	}
	119
1da177e4 LT	120	irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1da177e4 LT	121	{
84b1fd10	122	struct drm_device dev = (struct drm_device ) arg;
1da177e4	123	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
ed4cb414	124	u32 iir;
0a3e67a4 JB	125	u32 pipea_stats, pipeb_stats;
0a3e67a4 JB	126	int vblank = 0;
6e5fca53	127
630681d9 EA	128	atomic_inc(&dev_priv->irq_received);
630681d9 EA	129
ed4cb414 EA	130	if (dev->pdev->msi_enabled)
	131	I915_WRITE(IMR, ~0);
	132	iir = I915_READ(IIR);
a6b54f3f	133
ed4cb414 EA	134	if (iir == 0) {
	135	if (dev->pdev->msi_enabled) {
	136	I915_WRITE(IMR, dev_priv->irq_mask_reg);
	137	(void) I915_READ(IMR);
	138	}
af6061af	139	return IRQ_NONE;
ed4cb414	140	}
af6061af	141
0a3e67a4 JB	142	/*
	143	* Clear the PIPE(A\|B)STAT regs before the IIR otherwise
	144	* we may get extra interrupts.
	145	*/
	146	if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
	147	pipea_stats = I915_READ(PIPEASTAT);
	148	if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A))
	149	pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE \|
	150	PIPE_VBLANK_INTERRUPT_ENABLE);
	151	else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS\|
	152	PIPE_VBLANK_INTERRUPT_STATUS)) {
	153	vblank++;
42f52ef8	154	drm_handle_vblank(dev, 0);
0a3e67a4	155	}
af6061af	156
0a3e67a4 JB	157	I915_WRITE(PIPEASTAT, pipea_stats);
	158	}
	159	if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
	160	pipeb_stats = I915_READ(PIPEBSTAT);
	161	/* Ack the event */
	162	I915_WRITE(PIPEBSTAT, pipeb_stats);
	163
	164	/* The vblank interrupt gets enabled even if we didn't ask for
	165	it, so make sure it's shut down again */
	166	if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B))
	167	pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE \|
	168	PIPE_VBLANK_INTERRUPT_ENABLE);
	169	else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS\|
	170	PIPE_VBLANK_INTERRUPT_STATUS)) {
	171	vblank++;
42f52ef8	172	drm_handle_vblank(dev, 1);
0a3e67a4	173	}
af6061af	174
0a3e67a4 JB	175	if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS)
	176	opregion_asle_intr(dev);
	177	I915_WRITE(PIPEBSTAT, pipeb_stats);
0d6aa60b	178	}
1da177e4	179
673a394b EA	180	I915_WRITE(IIR, iir);
	181	if (dev->pdev->msi_enabled)
	182	I915_WRITE(IMR, dev_priv->irq_mask_reg);
	183	(void) I915_READ(IIR); /* Flush posted writes */
8ee1c3db	184
c99b058f KH	185	if (dev_priv->sarea_priv)
	186	dev_priv->sarea_priv->last_dispatch =
	187	READ_BREADCRUMB(dev_priv);
0a3e67a4	188
673a394b EA	189	if (iir & I915_USER_INTERRUPT) {
	190	dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
	191	DRM_WAKEUP(&dev_priv->irq_queue);
	192	}
	193
	194	if (iir & I915_ASLE_INTERRUPT)
	195	opregion_asle_intr(dev);
0a3e67a4	196
1da177e4 LT	197	return IRQ_HANDLED;
	198	}
	199
af6061af	200	static int i915_emit_irq(struct drm_device * dev)
1da177e4 LT	201	{
1da177e4 LT	202	drm_i915_private_t *dev_priv = dev->dev_private;
1da177e4 LT	203	RING_LOCALS;
	204
	205	i915_kernel_lost_context(dev);
	206
3e684eae	207	DRM_DEBUG("\n");
1da177e4	208
c99b058f	209	dev_priv->counter++;
c29b669c	210	if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f KH	211	dev_priv->counter = 1;
	212	if (dev_priv->sarea_priv)
	213	dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
c29b669c	214
0baf823a	215	BEGIN_LP_RING(4);
585fb111	216	OUT_RING(MI_STORE_DWORD_INDEX);
0baf823a	217	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
c29b669c	218	OUT_RING(dev_priv->counter);
585fb111	219	OUT_RING(MI_USER_INTERRUPT);
1da177e4	220	ADVANCE_LP_RING();
bc5f4523	221
c29b669c	222	return dev_priv->counter;
1da177e4 LT	223	}
1da177e4 LT	224
673a394b	225	void i915_user_irq_get(struct drm_device *dev)
ed4cb414 EA	226	{
ed4cb414 EA	227	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
e9d21d7f	228	unsigned long irqflags;
ed4cb414	229
e9d21d7f	230	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
ed4cb414 EA	231	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
ed4cb414 EA	232	i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
e9d21d7f	233	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
ed4cb414 EA	234	}
ed4cb414 EA	235
0a3e67a4	236	void i915_user_irq_put(struct drm_device *dev)
ed4cb414 EA	237	{
ed4cb414 EA	238	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
e9d21d7f	239	unsigned long irqflags;
ed4cb414	240
e9d21d7f	241	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
ed4cb414 EA	242	BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
	243	if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
	244	i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
e9d21d7f	245	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
ed4cb414 EA	246	}
ed4cb414 EA	247
84b1fd10	248	static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1da177e4 LT	249	{
	250	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
	251	int ret = 0;
	252
3e684eae	253	DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
1da177e4 LT	254	READ_BREADCRUMB(dev_priv));
1da177e4 LT	255
ed4cb414	256	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
c99b058f KH	257	if (dev_priv->sarea_priv) {
	258	dev_priv->sarea_priv->last_dispatch =
	259	READ_BREADCRUMB(dev_priv);
	260	}
1da177e4	261	return 0;
ed4cb414	262	}
1da177e4	263
c99b058f KH	264	if (dev_priv->sarea_priv)
c99b058f KH	265	dev_priv->sarea_priv->perf_boxes \|= I915_BOX_WAIT;
1da177e4	266
ed4cb414	267	i915_user_irq_get(dev);
1da177e4 LT	268	DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
1da177e4 LT	269	READ_BREADCRUMB(dev_priv) >= irq_nr);
ed4cb414	270	i915_user_irq_put(dev);
1da177e4	271
20caafa6	272	if (ret == -EBUSY) {
3e684eae	273	DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1da177e4 LT	274	READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
	275	}
	276
c99b058f KH	277	if (dev_priv->sarea_priv)
	278	dev_priv->sarea_priv->last_dispatch =
	279	READ_BREADCRUMB(dev_priv);
af6061af DA	280
	281	return ret;
	282	}
	283
1da177e4 LT	284	/* Needs the lock as it touches the ring.
1da177e4 LT	285	*/
c153f45f EA	286	int i915_irq_emit(struct drm_device dev, void data,
c153f45f EA	287	struct drm_file *file_priv)
1da177e4	288	{
1da177e4	289	drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f	290	drm_i915_irq_emit_t *emit = data;
1da177e4 LT	291	int result;
1da177e4 LT	292
546b0974	293	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 LT	294
1da177e4 LT	295	if (!dev_priv) {
3e684eae	296	DRM_ERROR("called with no initialization\n");
20caafa6	297	return -EINVAL;
1da177e4	298	}
546b0974	299	mutex_lock(&dev->struct_mutex);
1da177e4	300	result = i915_emit_irq(dev);
546b0974	301	mutex_unlock(&dev->struct_mutex);
1da177e4	302
c153f45f	303	if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1da177e4	304	DRM_ERROR("copy_to_user\n");
20caafa6	305	return -EFAULT;
1da177e4 LT	306	}
	307
	308	return 0;
	309	}
	310
	311	/* Doesn't need the hardware lock.
	312	*/
c153f45f EA	313	int i915_irq_wait(struct drm_device dev, void data,
c153f45f EA	314	struct drm_file *file_priv)
1da177e4	315	{
1da177e4	316	drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f	317	drm_i915_irq_wait_t *irqwait = data;
1da177e4 LT	318
1da177e4 LT	319	if (!dev_priv) {
3e684eae	320	DRM_ERROR("called with no initialization\n");
20caafa6	321	return -EINVAL;
1da177e4 LT	322	}
1da177e4 LT	323
c153f45f	324	return i915_wait_irq(dev, irqwait->irq_seq);
1da177e4 LT	325	}
1da177e4 LT	326
42f52ef8 KP	327	/* Called from drm generic code, passed 'crtc' which
	328	* we use as a pipe index
	329	*/
	330	int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 JB	331	{
0a3e67a4 JB	332	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
0a3e67a4 JB	333	u32 pipestat_reg = 0;
0a3e67a4 JB	334	u32 pipestat;
e9d21d7f KP	335	u32 interrupt = 0;
e9d21d7f KP	336	unsigned long irqflags;
0a3e67a4 JB	337
	338	switch (pipe) {
	339	case 0:
	340	pipestat_reg = PIPEASTAT;
e9d21d7f	341	interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
0a3e67a4 JB	342	break;
	343	case 1:
	344	pipestat_reg = PIPEBSTAT;
e9d21d7f	345	interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
0a3e67a4 JB	346	break;
	347	default:
	348	DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
	349	pipe);
e9d21d7f	350	return 0;
0a3e67a4 JB	351	}
0a3e67a4 JB	352
e9d21d7f	353	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
053d7f24 EA	354	/* Enabling vblank events in IMR comes before PIPESTAT write, or
	355	* there's a race where the PIPESTAT vblank bit gets set to 1, so
	356	* the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in
	357	* ISR flashes to 1, but the IIR bit doesn't get set to 1 because
	358	* IMR masks it. It doesn't ever get set after we clear the masking
	359	* in IMR because the ISR bit is edge, not level-triggered, on the
	360	* OR of PIPESTAT bits.
	361	*/
	362	i915_enable_irq(dev_priv, interrupt);
e9d21d7f KP	363	pipestat = I915_READ(pipestat_reg);
	364	if (IS_I965G(dev))
	365	pipestat \|= PIPE_START_VBLANK_INTERRUPT_ENABLE;
	366	else
	367	pipestat \|= PIPE_VBLANK_INTERRUPT_ENABLE;
	368	/* Clear any stale interrupt status */
	369	pipestat \|= (PIPE_START_VBLANK_INTERRUPT_STATUS \|
	370	PIPE_VBLANK_INTERRUPT_STATUS);
	371	I915_WRITE(pipestat_reg, pipestat);
	372	(void) I915_READ(pipestat_reg); /* Posting read */
e9d21d7f	373	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
0a3e67a4 JB	374
	375	return 0;
	376	}
	377
42f52ef8 KP	378	/* Called from drm generic code, passed 'crtc' which
	379	* we use as a pipe index
	380	*/
	381	void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 JB	382	{
0a3e67a4 JB	383	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
0a3e67a4 JB	384	u32 pipestat_reg = 0;
0a3e67a4 JB	385	u32 pipestat;
e9d21d7f KP	386	u32 interrupt = 0;
e9d21d7f KP	387	unsigned long irqflags;
0a3e67a4 JB	388
	389	switch (pipe) {
	390	case 0:
	391	pipestat_reg = PIPEASTAT;
e9d21d7f	392	interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
0a3e67a4 JB	393	break;
	394	case 1:
	395	pipestat_reg = PIPEBSTAT;
e9d21d7f	396	interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
0a3e67a4 JB	397	break;
	398	default:
	399	DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
	400	pipe);
e9d21d7f	401	return;
0a3e67a4 JB	402	break;
	403	}
	404
e9d21d7f KP	405	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	406	i915_disable_irq(dev_priv, interrupt);
	407	pipestat = I915_READ(pipestat_reg);
	408	pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE \|
	409	PIPE_VBLANK_INTERRUPT_ENABLE);
	410	/* Clear any stale interrupt status */
	411	pipestat \|= (PIPE_START_VBLANK_INTERRUPT_STATUS \|
	412	PIPE_VBLANK_INTERRUPT_STATUS);
	413	I915_WRITE(pipestat_reg, pipestat);
	414	(void) I915_READ(pipestat_reg); /* Posting read */
	415	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
0a3e67a4 JB	416	}
0a3e67a4 JB	417
702880f2 DA	418	/* Set the vblank monitor pipe
702880f2 DA	419	*/
c153f45f EA	420	int i915_vblank_pipe_set(struct drm_device dev, void data,
c153f45f EA	421	struct drm_file *file_priv)
702880f2	422	{
702880f2	423	drm_i915_private_t *dev_priv = dev->dev_private;
702880f2 DA	424
702880f2 DA	425	if (!dev_priv) {
3e684eae	426	DRM_ERROR("called with no initialization\n");
20caafa6	427	return -EINVAL;
702880f2 DA	428	}
702880f2 DA	429
5b51694a	430	return 0;
702880f2 DA	431	}
702880f2 DA	432
c153f45f EA	433	int i915_vblank_pipe_get(struct drm_device dev, void data,
c153f45f EA	434	struct drm_file *file_priv)
702880f2	435	{
702880f2	436	drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f	437	drm_i915_vblank_pipe_t *pipe = data;
702880f2 DA	438
702880f2 DA	439	if (!dev_priv) {
3e684eae	440	DRM_ERROR("called with no initialization\n");
20caafa6	441	return -EINVAL;
702880f2 DA	442	}
702880f2 DA	443
0a3e67a4	444	pipe->pipe = DRM_I915_VBLANK_PIPE_A \| DRM_I915_VBLANK_PIPE_B;
c153f45f	445
702880f2 DA	446	return 0;
	447	}
	448
a6b54f3f MD	449	/**
	450	* Schedule buffer swap at given vertical blank.
	451	*/
c153f45f EA	452	int i915_vblank_swap(struct drm_device dev, void data,
c153f45f EA	453	struct drm_file *file_priv)
a6b54f3f	454	{
bd95e0a4 EA	455	/* The delayed swap mechanism was fundamentally racy, and has been
	456	* removed. The model was that the client requested a delayed flip/swap
	457	* from the kernel, then waited for vblank before continuing to perform
	458	* rendering. The problem was that the kernel might wake the client
	459	* up before it dispatched the vblank swap (since the lock has to be
	460	* held while touching the ringbuffer), in which case the client would
	461	* clear and start the next frame before the swap occurred, and
	462	* flicker would occur in addition to likely missing the vblank.
	463	*
	464	* In the absence of this ioctl, userland falls back to a correct path
	465	* of waiting for a vblank, then dispatching the swap on its own.
	466	* Context switching to userland and back is plenty fast enough for
	467	* meeting the requirements of vblank swapping.
0a3e67a4	468	*/
bd95e0a4	469	return -EINVAL;
a6b54f3f MD	470	}
a6b54f3f MD	471
1da177e4 LT	472	/* drm_dma.h hooks
1da177e4 LT	473	*/
84b1fd10	474	void i915_driver_irq_preinstall(struct drm_device * dev)
1da177e4 LT	475	{
	476	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
	477
0a3e67a4 JB	478	I915_WRITE(HWSTAM, 0xeffe);
0a3e67a4 JB	479	I915_WRITE(IMR, 0xffffffff);
ed4cb414	480	I915_WRITE(IER, 0x0);
1da177e4 LT	481	}
1da177e4 LT	482
0a3e67a4	483	int i915_driver_irq_postinstall(struct drm_device *dev)
1da177e4 LT	484	{
1da177e4 LT	485	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
0a3e67a4	486	int ret, num_pipes = 2;
1da177e4	487
ed4cb414 EA	488	/* Set initial unmasked IRQs to just the selected vblank pipes. */
ed4cb414 EA	489	dev_priv->irq_mask_reg = ~0;
0a3e67a4 JB	490
	491	ret = drm_vblank_init(dev, num_pipes);
	492	if (ret)
	493	return ret;
	494
	495	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A \| DRM_I915_VBLANK_PIPE_B;
	496	dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
	497	dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	498
	499	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
ed4cb414	500
8ee1c3db MG	501	dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK;
8ee1c3db MG	502
ed4cb414 EA	503	I915_WRITE(IMR, dev_priv->irq_mask_reg);
	504	I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
	505	(void) I915_READ(IER);
	506
8ee1c3db	507	opregion_enable_asle(dev);
1da177e4	508	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
0a3e67a4 JB	509
0a3e67a4 JB	510	return 0;
1da177e4 LT	511	}
1da177e4 LT	512
84b1fd10	513	void i915_driver_irq_uninstall(struct drm_device * dev)
1da177e4 LT	514	{
1da177e4 LT	515	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
0a3e67a4	516	u32 temp;
91e3738e	517
1da177e4 LT	518	if (!dev_priv)
	519	return;
	520
0a3e67a4 JB	521	dev_priv->vblank_pipe = 0;
	522
	523	I915_WRITE(HWSTAM, 0xffffffff);
	524	I915_WRITE(IMR, 0xffffffff);
ed4cb414	525	I915_WRITE(IER, 0x0);
af6061af	526
0a3e67a4 JB	527	temp = I915_READ(PIPEASTAT);
	528	I915_WRITE(PIPEASTAT, temp);
	529	temp = I915_READ(PIPEBSTAT);
	530	I915_WRITE(PIPEBSTAT, temp);
ed4cb414 EA	531	temp = I915_READ(IIR);
ed4cb414 EA	532	I915_WRITE(IIR, temp);
1da177e4	533	}