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drm/i915: embed the gem object into drm_i915_gem_object
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
673a394b 37
28dfe52a
EA		 38#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39
e47c68e9
EA		 40static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 43static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 int write);
45static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 uint64_t offset,
47 uint64_t size);
48static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 49static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 50static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 unsigned alignment);
de151cf6 52static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 53static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 54static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 55static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
56 struct drm_i915_gem_pwrite *args,
57 struct drm_file *file_priv);
673a394b 58
31169714
CW		 59static LIST_HEAD(shrink_list);
60static DEFINE_SPINLOCK(shrink_list_lock);
61
79e53945
JB		 62int i915_gem_do_init(struct drm_device *dev, unsigned long start,
63 unsigned long end)
673a394b
EA		 64{
65 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 66
79e53945
JB		 67 if (start >= end ||
68 (start & (PAGE_SIZE - 1)) != 0 ||
69 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 70 return -EINVAL;
71 }
72
79e53945
JB		 73 drm_mm_init(&dev_priv->mm.gtt_space, start,
74 end - start);
673a394b 75
79e53945
JB		 76 dev->gtt_total = (uint32_t) (end - start);
77
78 return 0;
79}
673a394b 80
79e53945
JB		 81int
82i915_gem_init_ioctl(struct drm_device *dev, void *data,
83 struct drm_file *file_priv)
84{
85 struct drm_i915_gem_init *args = data;
86 int ret;
87
88 mutex_lock(&dev->struct_mutex);
89 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 90 mutex_unlock(&dev->struct_mutex);
91
79e53945 92 return ret;
673a394b
EA		 93}
94
5a125c3c
EA		 95int
96i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
97 struct drm_file *file_priv)
98{
5a125c3c 99 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 100
101 if (!(dev->driver->driver_features & DRIVER_GEM))
102 return -ENODEV;
103
104 args->aper_size = dev->gtt_total;
2678d9d6
KP		 105 args->aper_available_size = (args->aper_size -
106 atomic_read(&dev->pin_memory));
5a125c3c
EA		 107
108 return 0;
109}
110
673a394b
EA		 111
112/**
113 * Creates a new mm object and returns a handle to it.
114 */
115int
116i915_gem_create_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv)
118{
119 struct drm_i915_gem_create *args = data;
120 struct drm_gem_object *obj;
a1a2d1d3
PP		 121 int ret;
122 u32 handle;
673a394b
EA		 123
124 args->size = roundup(args->size, PAGE_SIZE);
125
126 /* Allocate the new object */
ac52bc56 127 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 128 if (obj == NULL)
129 return -ENOMEM;
130
131 ret = drm_gem_handle_create(file_priv, obj, &handle);
bc9025bd 132 drm_gem_object_handle_unreference_unlocked(obj);
673a394b
EA		 133
134 if (ret)
135 return ret;
136
137 args->handle = handle;
138
139 return 0;
140}
141
eb01459f
EA		 142static inline int
143fast_shmem_read(struct page **pages,
144 loff_t page_base, int page_offset,
145 char __user *data,
146 int length)
147{
148 char __iomem *vaddr;
2bc43b5c 149 int unwritten;
eb01459f
EA		 150
151 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
152 if (vaddr == NULL)
153 return -ENOMEM;
2bc43b5c 154 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 155 kunmap_atomic(vaddr, KM_USER0);
156
2bc43b5c
FM		 157 if (unwritten)
158 return -EFAULT;
159
160 return 0;
eb01459f
EA		 161}
162
280b713b
EA		 163static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
164{
165 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 166 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 167
168 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
169 obj_priv->tiling_mode != I915_TILING_NONE;
170}
171
40123c1f
EA		 172static inline int
173slow_shmem_copy(struct page *dst_page,
174 int dst_offset,
175 struct page *src_page,
176 int src_offset,
177 int length)
178{
179 char *dst_vaddr, *src_vaddr;
180
181 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
182 if (dst_vaddr == NULL)
183 return -ENOMEM;
184
185 src_vaddr = kmap_atomic(src_page, KM_USER1);
186 if (src_vaddr == NULL) {
187 kunmap_atomic(dst_vaddr, KM_USER0);
188 return -ENOMEM;
189 }
190
191 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
192
193 kunmap_atomic(src_vaddr, KM_USER1);
194 kunmap_atomic(dst_vaddr, KM_USER0);
195
196 return 0;
197}
198
280b713b
EA		 199static inline int
200slow_shmem_bit17_copy(struct page *gpu_page,
201 int gpu_offset,
202 struct page *cpu_page,
203 int cpu_offset,
204 int length,
205 int is_read)
206{
207 char *gpu_vaddr, *cpu_vaddr;
208
209 /* Use the unswizzled path if this page isn't affected. */
210 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
211 if (is_read)
212 return slow_shmem_copy(cpu_page, cpu_offset,
213 gpu_page, gpu_offset, length);
214 else
215 return slow_shmem_copy(gpu_page, gpu_offset,
216 cpu_page, cpu_offset, length);
217 }
218
219 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
220 if (gpu_vaddr == NULL)
221 return -ENOMEM;
222
223 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
224 if (cpu_vaddr == NULL) {
225 kunmap_atomic(gpu_vaddr, KM_USER0);
226 return -ENOMEM;
227 }
228
229 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
230 * XORing with the other bits (A9 for Y, A9 and A10 for X)
231 */
232 while (length > 0) {
233 int cacheline_end = ALIGN(gpu_offset + 1, 64);
234 int this_length = min(cacheline_end - gpu_offset, length);
235 int swizzled_gpu_offset = gpu_offset ^ 64;
236
237 if (is_read) {
238 memcpy(cpu_vaddr + cpu_offset,
239 gpu_vaddr + swizzled_gpu_offset,
240 this_length);
241 } else {
242 memcpy(gpu_vaddr + swizzled_gpu_offset,
243 cpu_vaddr + cpu_offset,
244 this_length);
245 }
246 cpu_offset += this_length;
247 gpu_offset += this_length;
248 length -= this_length;
249 }
250
251 kunmap_atomic(cpu_vaddr, KM_USER1);
252 kunmap_atomic(gpu_vaddr, KM_USER0);
253
254 return 0;
255}
256
eb01459f
EA		 257/**
258 * This is the fast shmem pread path, which attempts to copy_from_user directly
259 * from the backing pages of the object to the user's address space. On a
260 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
261 */
262static int
263i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
264 struct drm_i915_gem_pread *args,
265 struct drm_file *file_priv)
266{
23010e43 267 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 268 ssize_t remain;
269 loff_t offset, page_base;
270 char __user *user_data;
271 int page_offset, page_length;
272 int ret;
273
274 user_data = (char __user *) (uintptr_t) args->data_ptr;
275 remain = args->size;
276
277 mutex_lock(&dev->struct_mutex);
278
4bdadb97 279 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 280 if (ret != 0)
281 goto fail_unlock;
282
283 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
284 args->size);
285 if (ret != 0)
286 goto fail_put_pages;
287
23010e43 288 obj_priv = to_intel_bo(obj);
eb01459f
EA		 289 offset = args->offset;
290
291 while (remain > 0) {
292 /* Operation in this page
293 *
294 * page_base = page offset within aperture
295 * page_offset = offset within page
296 * page_length = bytes to copy for this page
297 */
298 page_base = (offset & ~(PAGE_SIZE-1));
299 page_offset = offset & (PAGE_SIZE-1);
300 page_length = remain;
301 if ((page_offset + remain) > PAGE_SIZE)
302 page_length = PAGE_SIZE - page_offset;
303
304 ret = fast_shmem_read(obj_priv->pages,
305 page_base, page_offset,
306 user_data, page_length);
307 if (ret)
308 goto fail_put_pages;
309
310 remain -= page_length;
311 user_data += page_length;
312 offset += page_length;
313 }
314
315fail_put_pages:
316 i915_gem_object_put_pages(obj);
317fail_unlock:
318 mutex_unlock(&dev->struct_mutex);
319
320 return ret;
321}
322
07f73f69
CW		 323static int
324i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
325{
326 int ret;
327
4bdadb97 328 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 329
330 /* If we've insufficient memory to map in the pages, attempt
331 * to make some space by throwing out some old buffers.
332 */
333 if (ret == -ENOMEM) {
334 struct drm_device *dev = obj->dev;
07f73f69
CW		 335
336 ret = i915_gem_evict_something(dev, obj->size);
337 if (ret)
338 return ret;
339
4bdadb97 340 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 341 }
342
343 return ret;
344}
345
eb01459f
EA		 346/**
347 * This is the fallback shmem pread path, which allocates temporary storage
348 * in kernel space to copy_to_user into outside of the struct_mutex, so we
349 * can copy out of the object's backing pages while holding the struct mutex
350 * and not take page faults.
351 */
352static int
353i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
354 struct drm_i915_gem_pread *args,
355 struct drm_file *file_priv)
356{
23010e43 357 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 358 struct mm_struct *mm = current->mm;
359 struct page **user_pages;
360 ssize_t remain;
361 loff_t offset, pinned_pages, i;
362 loff_t first_data_page, last_data_page, num_pages;
363 int shmem_page_index, shmem_page_offset;
364 int data_page_index, data_page_offset;
365 int page_length;
366 int ret;
367 uint64_t data_ptr = args->data_ptr;
280b713b 368 int do_bit17_swizzling;
eb01459f
EA		 369
370 remain = args->size;
371
372 /* Pin the user pages containing the data. We can't fault while
373 * holding the struct mutex, yet we want to hold it while
374 * dereferencing the user data.
375 */
376 first_data_page = data_ptr / PAGE_SIZE;
377 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
378 num_pages = last_data_page - first_data_page + 1;
379
8e7d2b2c 380 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 381 if (user_pages == NULL)
382 return -ENOMEM;
383
384 down_read(&mm->mmap_sem);
385 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 386 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 387 up_read(&mm->mmap_sem);
388 if (pinned_pages < num_pages) {
389 ret = -EFAULT;
390 goto fail_put_user_pages;
391 }
392
280b713b
EA		 393 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
394
eb01459f
EA		 395 mutex_lock(&dev->struct_mutex);
396
07f73f69
CW		 397 ret = i915_gem_object_get_pages_or_evict(obj);
398 if (ret)
eb01459f
EA		 399 goto fail_unlock;
400
401 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
402 args->size);
403 if (ret != 0)
404 goto fail_put_pages;
405
23010e43 406 obj_priv = to_intel_bo(obj);
eb01459f
EA		 407 offset = args->offset;
408
409 while (remain > 0) {
410 /* Operation in this page
411 *
412 * shmem_page_index = page number within shmem file
413 * shmem_page_offset = offset within page in shmem file
414 * data_page_index = page number in get_user_pages return
415 * data_page_offset = offset with data_page_index page.
416 * page_length = bytes to copy for this page
417 */
418 shmem_page_index = offset / PAGE_SIZE;
419 shmem_page_offset = offset & ~PAGE_MASK;
420 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
421 data_page_offset = data_ptr & ~PAGE_MASK;
422
423 page_length = remain;
424 if ((shmem_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - shmem_page_offset;
426 if ((data_page_offset + page_length) > PAGE_SIZE)
427 page_length = PAGE_SIZE - data_page_offset;
428
280b713b
EA		 429 if (do_bit17_swizzling) {
430 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
431 shmem_page_offset,
432 user_pages[data_page_index],
433 data_page_offset,
434 page_length,
435 1);
436 } else {
437 ret = slow_shmem_copy(user_pages[data_page_index],
438 data_page_offset,
439 obj_priv->pages[shmem_page_index],
440 shmem_page_offset,
441 page_length);
442 }
eb01459f
EA		 443 if (ret)
444 goto fail_put_pages;
445
446 remain -= page_length;
447 data_ptr += page_length;
448 offset += page_length;
449 }
450
451fail_put_pages:
452 i915_gem_object_put_pages(obj);
453fail_unlock:
454 mutex_unlock(&dev->struct_mutex);
455fail_put_user_pages:
456 for (i = 0; i < pinned_pages; i++) {
457 SetPageDirty(user_pages[i]);
458 page_cache_release(user_pages[i]);
459 }
8e7d2b2c 460 drm_free_large(user_pages);
eb01459f
EA		 461
462 return ret;
463}
464
673a394b
EA		 465/**
466 * Reads data from the object referenced by handle.
467 *
468 * On error, the contents of *data are undefined.
469 */
470int
471i915_gem_pread_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv)
473{
474 struct drm_i915_gem_pread *args = data;
475 struct drm_gem_object *obj;
476 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 477 int ret;
478
479 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
480 if (obj == NULL)
481 return -EBADF;
23010e43 482 obj_priv = to_intel_bo(obj);
673a394b
EA		 483
484 /* Bounds check source.
485 *
486 * XXX: This could use review for overflow issues...
487 */
488 if (args->offset > obj->size || args->size > obj->size ||
489 args->offset + args->size > obj->size) {
bc9025bd 490 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 491 return -EINVAL;
492 }
493
280b713b 494 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 495 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 496 } else {
497 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
498 if (ret != 0)
499 ret = i915_gem_shmem_pread_slow(dev, obj, args,
500 file_priv);
501 }
673a394b 502
bc9025bd 503 drm_gem_object_unreference_unlocked(obj);
673a394b 504
eb01459f 505 return ret;
673a394b
EA		 506}
507
0839ccb8
KP		 508/* This is the fast write path which cannot handle
509 * page faults in the source data
9b7530cc 510 */
0839ccb8
KP		 511
512static inline int
513fast_user_write(struct io_mapping *mapping,
514 loff_t page_base, int page_offset,
515 char __user *user_data,
516 int length)
9b7530cc 517{
9b7530cc 518 char *vaddr_atomic;
0839ccb8 519 unsigned long unwritten;
9b7530cc 520
0839ccb8
KP		 521 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
522 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
523 user_data, length);
524 io_mapping_unmap_atomic(vaddr_atomic);
525 if (unwritten)
526 return -EFAULT;
527 return 0;
528}
529
530/* Here's the write path which can sleep for
531 * page faults
532 */
533
534static inline int
3de09aa3
EA		 535slow_kernel_write(struct io_mapping *mapping,
536 loff_t gtt_base, int gtt_offset,
537 struct page *user_page, int user_offset,
538 int length)
0839ccb8 539{
3de09aa3 540 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 541 unsigned long unwritten;
542
3de09aa3
EA		 543 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
544 src_vaddr = kmap_atomic(user_page, KM_USER1);
545 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
546 src_vaddr + user_offset,
547 length);
548 kunmap_atomic(src_vaddr, KM_USER1);
549 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 550 if (unwritten)
551 return -EFAULT;
9b7530cc 552 return 0;
9b7530cc
LT		 553}
554
40123c1f
EA		 555static inline int
556fast_shmem_write(struct page **pages,
557 loff_t page_base, int page_offset,
558 char __user *data,
559 int length)
560{
561 char __iomem *vaddr;
d0088775 562 unsigned long unwritten;
40123c1f
EA		 563
564 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
565 if (vaddr == NULL)
566 return -ENOMEM;
d0088775 567 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 568 kunmap_atomic(vaddr, KM_USER0);
569
d0088775
DA		 570 if (unwritten)
571 return -EFAULT;
40123c1f
EA		 572 return 0;
573}
574
3de09aa3
EA		 575/**
576 * This is the fast pwrite path, where we copy the data directly from the
577 * user into the GTT, uncached.
578 */
673a394b 579static int
3de09aa3
EA		 580i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
581 struct drm_i915_gem_pwrite *args,
582 struct drm_file *file_priv)
673a394b 583{
23010e43 584 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 585 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 586 ssize_t remain;
0839ccb8 587 loff_t offset, page_base;
673a394b 588 char __user *user_data;
0839ccb8
KP		 589 int page_offset, page_length;
590 int ret;
673a394b
EA		 591
592 user_data = (char __user *) (uintptr_t) args->data_ptr;
593 remain = args->size;
594 if (!access_ok(VERIFY_READ, user_data, remain))
595 return -EFAULT;
596
597
598 mutex_lock(&dev->struct_mutex);
599 ret = i915_gem_object_pin(obj, 0);
600 if (ret) {
601 mutex_unlock(&dev->struct_mutex);
602 return ret;
603 }
2ef7eeaa 604 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 605 if (ret)
606 goto fail;
607
23010e43 608 obj_priv = to_intel_bo(obj);
673a394b 609 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 610
611 while (remain > 0) {
612 /* Operation in this page
613 *
0839ccb8
KP		 614 * page_base = page offset within aperture
615 * page_offset = offset within page
616 * page_length = bytes to copy for this page
673a394b 617 */
0839ccb8
KP		 618 page_base = (offset & ~(PAGE_SIZE-1));
619 page_offset = offset & (PAGE_SIZE-1);
620 page_length = remain;
621 if ((page_offset + remain) > PAGE_SIZE)
622 page_length = PAGE_SIZE - page_offset;
623
624 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
625 page_offset, user_data, page_length);
626
627 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
0839ccb8 630 */
3de09aa3
EA		 631 if (ret)
632 goto fail;
673a394b 633
0839ccb8
KP		 634 remain -= page_length;
635 user_data += page_length;
636 offset += page_length;
673a394b 637 }
673a394b
EA		 638
639fail:
640 i915_gem_object_unpin(obj);
641 mutex_unlock(&dev->struct_mutex);
642
643 return ret;
644}
645
3de09aa3
EA		 646/**
647 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
648 * the memory and maps it using kmap_atomic for copying.
649 *
650 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
651 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
652 */
3043c60c 653static int
3de09aa3
EA		 654i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
655 struct drm_i915_gem_pwrite *args,
656 struct drm_file *file_priv)
673a394b 657{
23010e43 658 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 659 drm_i915_private_t *dev_priv = dev->dev_private;
660 ssize_t remain;
661 loff_t gtt_page_base, offset;
662 loff_t first_data_page, last_data_page, num_pages;
663 loff_t pinned_pages, i;
664 struct page **user_pages;
665 struct mm_struct *mm = current->mm;
666 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 667 int ret;
3de09aa3
EA		 668 uint64_t data_ptr = args->data_ptr;
669
670 remain = args->size;
671
672 /* Pin the user pages containing the data. We can't fault while
673 * holding the struct mutex, and all of the pwrite implementations
674 * want to hold it while dereferencing the user data.
675 */
676 first_data_page = data_ptr / PAGE_SIZE;
677 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
678 num_pages = last_data_page - first_data_page + 1;
679
8e7d2b2c 680 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 681 if (user_pages == NULL)
682 return -ENOMEM;
683
684 down_read(&mm->mmap_sem);
685 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
686 num_pages, 0, 0, user_pages, NULL);
687 up_read(&mm->mmap_sem);
688 if (pinned_pages < num_pages) {
689 ret = -EFAULT;
690 goto out_unpin_pages;
691 }
673a394b
EA		 692
693 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 694 ret = i915_gem_object_pin(obj, 0);
695 if (ret)
696 goto out_unlock;
697
698 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
699 if (ret)
700 goto out_unpin_object;
701
23010e43 702 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 703 offset = obj_priv->gtt_offset + args->offset;
704
705 while (remain > 0) {
706 /* Operation in this page
707 *
708 * gtt_page_base = page offset within aperture
709 * gtt_page_offset = offset within page in aperture
710 * data_page_index = page number in get_user_pages return
711 * data_page_offset = offset with data_page_index page.
712 * page_length = bytes to copy for this page
713 */
714 gtt_page_base = offset & PAGE_MASK;
715 gtt_page_offset = offset & ~PAGE_MASK;
716 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
717 data_page_offset = data_ptr & ~PAGE_MASK;
718
719 page_length = remain;
720 if ((gtt_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - gtt_page_offset;
722 if ((data_page_offset + page_length) > PAGE_SIZE)
723 page_length = PAGE_SIZE - data_page_offset;
724
725 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
726 gtt_page_base, gtt_page_offset,
727 user_pages[data_page_index],
728 data_page_offset,
729 page_length);
730
731 /* If we get a fault while copying data, then (presumably) our
732 * source page isn't available. Return the error and we'll
733 * retry in the slow path.
734 */
735 if (ret)
736 goto out_unpin_object;
737
738 remain -= page_length;
739 offset += page_length;
740 data_ptr += page_length;
741 }
742
743out_unpin_object:
744 i915_gem_object_unpin(obj);
745out_unlock:
746 mutex_unlock(&dev->struct_mutex);
747out_unpin_pages:
748 for (i = 0; i < pinned_pages; i++)
749 page_cache_release(user_pages[i]);
8e7d2b2c 750 drm_free_large(user_pages);
3de09aa3
EA		 751
752 return ret;
753}
754
40123c1f
EA		 755/**
756 * This is the fast shmem pwrite path, which attempts to directly
757 * copy_from_user into the kmapped pages backing the object.
758 */
3043c60c 759static int
40123c1f
EA		 760i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
761 struct drm_i915_gem_pwrite *args,
762 struct drm_file *file_priv)
673a394b 763{
23010e43 764 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 765 ssize_t remain;
766 loff_t offset, page_base;
767 char __user *user_data;
768 int page_offset, page_length;
673a394b 769 int ret;
40123c1f
EA		 770
771 user_data = (char __user *) (uintptr_t) args->data_ptr;
772 remain = args->size;
673a394b
EA		 773
774 mutex_lock(&dev->struct_mutex);
775
4bdadb97 776 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 777 if (ret != 0)
778 goto fail_unlock;
673a394b 779
e47c68e9 780 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 781 if (ret != 0)
782 goto fail_put_pages;
783
23010e43 784 obj_priv = to_intel_bo(obj);
40123c1f
EA		 785 offset = args->offset;
786 obj_priv->dirty = 1;
787
788 while (remain > 0) {
789 /* Operation in this page
790 *
791 * page_base = page offset within aperture
792 * page_offset = offset within page
793 * page_length = bytes to copy for this page
794 */
795 page_base = (offset & ~(PAGE_SIZE-1));
796 page_offset = offset & (PAGE_SIZE-1);
797 page_length = remain;
798 if ((page_offset + remain) > PAGE_SIZE)
799 page_length = PAGE_SIZE - page_offset;
800
801 ret = fast_shmem_write(obj_priv->pages,
802 page_base, page_offset,
803 user_data, page_length);
804 if (ret)
805 goto fail_put_pages;
806
807 remain -= page_length;
808 user_data += page_length;
809 offset += page_length;
810 }
811
812fail_put_pages:
813 i915_gem_object_put_pages(obj);
814fail_unlock:
815 mutex_unlock(&dev->struct_mutex);
816
817 return ret;
818}
819
820/**
821 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
822 * the memory and maps it using kmap_atomic for copying.
823 *
824 * This avoids taking mmap_sem for faulting on the user's address while the
825 * struct_mutex is held.
826 */
827static int
828i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
829 struct drm_i915_gem_pwrite *args,
830 struct drm_file *file_priv)
831{
23010e43 832 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 833 struct mm_struct *mm = current->mm;
834 struct page **user_pages;
835 ssize_t remain;
836 loff_t offset, pinned_pages, i;
837 loff_t first_data_page, last_data_page, num_pages;
838 int shmem_page_index, shmem_page_offset;
839 int data_page_index, data_page_offset;
840 int page_length;
841 int ret;
842 uint64_t data_ptr = args->data_ptr;
280b713b 843 int do_bit17_swizzling;
40123c1f
EA		 844
845 remain = args->size;
846
847 /* Pin the user pages containing the data. We can't fault while
848 * holding the struct mutex, and all of the pwrite implementations
849 * want to hold it while dereferencing the user data.
850 */
851 first_data_page = data_ptr / PAGE_SIZE;
852 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
853 num_pages = last_data_page - first_data_page + 1;
854
8e7d2b2c 855 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 856 if (user_pages == NULL)
857 return -ENOMEM;
858
859 down_read(&mm->mmap_sem);
860 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
861 num_pages, 0, 0, user_pages, NULL);
862 up_read(&mm->mmap_sem);
863 if (pinned_pages < num_pages) {
864 ret = -EFAULT;
865 goto fail_put_user_pages;
673a394b
EA		 866 }
867
280b713b
EA		 868 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
869
40123c1f
EA		 870 mutex_lock(&dev->struct_mutex);
871
07f73f69
CW		 872 ret = i915_gem_object_get_pages_or_evict(obj);
873 if (ret)
40123c1f
EA		 874 goto fail_unlock;
875
876 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
877 if (ret != 0)
878 goto fail_put_pages;
879
23010e43 880 obj_priv = to_intel_bo(obj);
673a394b 881 offset = args->offset;
40123c1f 882 obj_priv->dirty = 1;
673a394b 883
40123c1f
EA		 884 while (remain > 0) {
885 /* Operation in this page
886 *
887 * shmem_page_index = page number within shmem file
888 * shmem_page_offset = offset within page in shmem file
889 * data_page_index = page number in get_user_pages return
890 * data_page_offset = offset with data_page_index page.
891 * page_length = bytes to copy for this page
892 */
893 shmem_page_index = offset / PAGE_SIZE;
894 shmem_page_offset = offset & ~PAGE_MASK;
895 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
896 data_page_offset = data_ptr & ~PAGE_MASK;
897
898 page_length = remain;
899 if ((shmem_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - shmem_page_offset;
901 if ((data_page_offset + page_length) > PAGE_SIZE)
902 page_length = PAGE_SIZE - data_page_offset;
903
280b713b
EA		 904 if (do_bit17_swizzling) {
905 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
906 shmem_page_offset,
907 user_pages[data_page_index],
908 data_page_offset,
909 page_length,
910 0);
911 } else {
912 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
913 shmem_page_offset,
914 user_pages[data_page_index],
915 data_page_offset,
916 page_length);
917 }
40123c1f
EA		 918 if (ret)
919 goto fail_put_pages;
920
921 remain -= page_length;
922 data_ptr += page_length;
923 offset += page_length;
673a394b
EA		 924 }
925
40123c1f
EA		 926fail_put_pages:
927 i915_gem_object_put_pages(obj);
928fail_unlock:
673a394b 929 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 930fail_put_user_pages:
931 for (i = 0; i < pinned_pages; i++)
932 page_cache_release(user_pages[i]);
8e7d2b2c 933 drm_free_large(user_pages);
673a394b 934
40123c1f 935 return ret;
673a394b
EA		 936}
937
938/**
939 * Writes data to the object referenced by handle.
940 *
941 * On error, the contents of the buffer that were to be modified are undefined.
942 */
943int
944i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
945 struct drm_file *file_priv)
946{
947 struct drm_i915_gem_pwrite *args = data;
948 struct drm_gem_object *obj;
949 struct drm_i915_gem_object *obj_priv;
950 int ret = 0;
951
952 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
953 if (obj == NULL)
954 return -EBADF;
23010e43 955 obj_priv = to_intel_bo(obj);
673a394b
EA		 956
957 /* Bounds check destination.
958 *
959 * XXX: This could use review for overflow issues...
960 */
961 if (args->offset > obj->size || args->size > obj->size ||
962 args->offset + args->size > obj->size) {
bc9025bd 963 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 964 return -EINVAL;
965 }
966
967 /* We can only do the GTT pwrite on untiled buffers, as otherwise
968 * it would end up going through the fenced access, and we'll get
969 * different detiling behavior between reading and writing.
970 * pread/pwrite currently are reading and writing from the CPU
971 * perspective, requiring manual detiling by the client.
972 */
71acb5eb
DA		 973 if (obj_priv->phys_obj)
974 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
975 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 976 dev->gtt_total != 0) {
977 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
978 if (ret == -EFAULT) {
979 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
980 file_priv);
981 }
280b713b
EA		 982 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
983 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 984 } else {
985 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
986 if (ret == -EFAULT) {
987 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
988 file_priv);
989 }
990 }
673a394b
EA		 991
992#if WATCH_PWRITE
993 if (ret)
994 DRM_INFO("pwrite failed %d\n", ret);
995#endif
996
bc9025bd 997 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 998
999 return ret;
1000}
1001
1002/**
2ef7eeaa
EA		 1003 * Called when user space prepares to use an object with the CPU, either
1004 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1005 */
1006int
1007i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv)
1009{
a09ba7fa 1010 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1011 struct drm_i915_gem_set_domain *args = data;
1012 struct drm_gem_object *obj;
652c393a 1013 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1014 uint32_t read_domains = args->read_domains;
1015 uint32_t write_domain = args->write_domain;
673a394b
EA		 1016 int ret;
1017
1018 if (!(dev->driver->driver_features & DRIVER_GEM))
1019 return -ENODEV;
1020
2ef7eeaa 1021 /* Only handle setting domains to types used by the CPU. */
21d509e3 1022 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1023 return -EINVAL;
1024
21d509e3 1025 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1026 return -EINVAL;
1027
1028 /* Having something in the write domain implies it's in the read
1029 * domain, and only that read domain. Enforce that in the request.
1030 */
1031 if (write_domain != 0 && read_domains != write_domain)
1032 return -EINVAL;
1033
673a394b
EA		 1034 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1035 if (obj == NULL)
1036 return -EBADF;
23010e43 1037 obj_priv = to_intel_bo(obj);
673a394b
EA		 1038
1039 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1040
1041 intel_mark_busy(dev, obj);
1042
673a394b 1043#if WATCH_BUF
cfd43c02 1044 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1045 obj, obj->size, read_domains, write_domain);
673a394b 1046#endif
2ef7eeaa
EA		 1047 if (read_domains & I915_GEM_DOMAIN_GTT) {
1048 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1049
a09ba7fa
EA		 1050 /* Update the LRU on the fence for the CPU access that's
1051 * about to occur.
1052 */
1053 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1054 list_move_tail(&obj_priv->fence_list,
1055 &dev_priv->mm.fence_list);
1056 }
1057
02354392
EA		 1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1061 */
1062 if (ret == -EINVAL)
1063 ret = 0;
2ef7eeaa 1064 } else {
e47c68e9 1065 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1066 }
1067
673a394b
EA		 1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1070 return ret;
1071}
1072
1073/**
1074 * Called when user space has done writes to this buffer
1075 */
1076int
1077i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1079{
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1083 int ret = 0;
1084
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1086 return -ENODEV;
1087
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1090 if (obj == NULL) {
1091 mutex_unlock(&dev->struct_mutex);
1092 return -EBADF;
1093 }
1094
1095#if WATCH_BUF
cfd43c02 1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1097 __func__, args->handle, obj, obj->size);
1098#endif
23010e43 1099 obj_priv = to_intel_bo(obj);
673a394b
EA		 1100
1101 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1104
673a394b
EA		 1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1107 return ret;
1108}
1109
1110/**
1111 * Maps the contents of an object, returning the address it is mapped
1112 * into.
1113 *
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1116 */
1117int
1118i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1120{
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1123 loff_t offset;
1124 unsigned long addr;
1125
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1127 return -ENODEV;
1128
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1130 if (obj == NULL)
1131 return -EBADF;
1132
1133 offset = args->offset;
1134
1135 down_write(&current->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1138 args->offset);
1139 up_write(&current->mm->mmap_sem);
bc9025bd 1140 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1141 if (IS_ERR((void *)addr))
1142 return addr;
1143
1144 args->addr_ptr = (uint64_t) addr;
1145
1146 return 0;
1147}
1148
de151cf6
JB		 1149/**
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1152 * vmf: fault info
1153 *
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1159 *
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1163 * left.
1164 */
1165int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1166{
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1171 pgoff_t page_offset;
1172 unsigned long pfn;
1173 int ret = 0;
0f973f27 1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1175
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1178 PAGE_SHIFT;
1179
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
e67b8ce1 1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1184 if (ret)
1185 goto unlock;
07f4f3e8 1186
14b60391 1187 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1188
1189 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1190 if (ret)
1191 goto unlock;
de151cf6
JB		 1192 }
1193
1194 /* Need a new fence register? */
a09ba7fa 1195 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1196 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1197 if (ret)
1198 goto unlock;
d9ddcb96 1199 }
de151cf6
JB		 1200
1201 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1202 page_offset;
1203
1204 /* Finally, remap it using the new GTT offset */
1205 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1206unlock:
de151cf6
JB		 1207 mutex_unlock(&dev->struct_mutex);
1208
1209 switch (ret) {
c715089f
CW		 1210 case 0:
1211 case -ERESTARTSYS:
1212 return VM_FAULT_NOPAGE;
de151cf6
JB		 1213 case -ENOMEM:
1214 case -EAGAIN:
1215 return VM_FAULT_OOM;
de151cf6 1216 default:
c715089f 1217 return VM_FAULT_SIGBUS;
de151cf6
JB		 1218 }
1219}
1220
1221/**
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1224 *
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1228 * structures.
1229 *
1230 * This routine allocates and attaches a fake offset for @obj.
1231 */
1232static int
1233i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1234{
1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1238 struct drm_map_list *list;
f77d390c 1239 struct drm_local_map *map;
de151cf6
JB		 1240 int ret = 0;
1241
1242 /* Set the object up for mmap'ing */
1243 list = &obj->map_list;
9a298b2a 1244 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1245 if (!list->map)
1246 return -ENOMEM;
1247
1248 map = list->map;
1249 map->type = _DRM_GEM;
1250 map->size = obj->size;
1251 map->handle = obj;
1252
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1255 obj->size / PAGE_SIZE, 0, 0);
1256 if (!list->file_offset_node) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1258 ret = -ENOMEM;
1259 goto out_free_list;
1260 }
1261
1262 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1263 obj->size / PAGE_SIZE, 0);
1264 if (!list->file_offset_node) {
1265 ret = -ENOMEM;
1266 goto out_free_list;
1267 }
1268
1269 list->hash.key = list->file_offset_node->start;
1270 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1271 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1272 ret = -ENOMEM;
de151cf6
JB		 1273 goto out_free_mm;
1274 }
1275
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1279
1280 return 0;
1281
1282out_free_mm:
1283 drm_mm_put_block(list->file_offset_node);
1284out_free_list:
9a298b2a 1285 kfree(list->map);
de151cf6
JB		 1286
1287 return ret;
1288}
1289
901782b2
CW		 1290/**
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1293 *
af901ca1 1294 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1295 * relinquish ownership of the pages back to the system.
1296 *
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1303 */
d05ca301 1304void
901782b2
CW		 1305i915_gem_release_mmap(struct drm_gem_object *obj)
1306{
1307 struct drm_device *dev = obj->dev;
23010e43 1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1309
1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping,
1312 obj_priv->mmap_offset, obj->size, 1);
1313}
1314
ab00b3e5
JB		 1315static void
1316i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1317{
1318 struct drm_device *dev = obj->dev;
23010e43 1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list;
1322
1323 list = &obj->map_list;
1324 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1325
1326 if (list->file_offset_node) {
1327 drm_mm_put_block(list->file_offset_node);
1328 list->file_offset_node = NULL;
1329 }
1330
1331 if (list->map) {
9a298b2a 1332 kfree(list->map);
ab00b3e5
JB		 1333 list->map = NULL;
1334 }
1335
1336 obj_priv->mmap_offset = 0;
1337}
1338
de151cf6
JB		 1339/**
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1342 *
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1345 */
1346static uint32_t
1347i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1348{
1349 struct drm_device *dev = obj->dev;
23010e43 1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1351 int start, i;
1352
1353 /*
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1356 */
1357 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1358 return 4096;
1359
1360 /*
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1363 */
1364 if (IS_I9XX(dev))
1365 start = 1024*1024;
1366 else
1367 start = 512*1024;
1368
1369 for (i = start; i < obj->size; i <<= 1)
1370 ;
1371
1372 return i;
1373}
1374
1375/**
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @dev: DRM device
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1380 *
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1384 *
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1388 * userspace.
1389 */
1390int
1391i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv)
1393{
1394 struct drm_i915_gem_mmap_gtt *args = data;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1398 int ret;
1399
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1401 return -ENODEV;
1402
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1404 if (obj == NULL)
1405 return -EBADF;
1406
1407 mutex_lock(&dev->struct_mutex);
1408
23010e43 1409 obj_priv = to_intel_bo(obj);
de151cf6 1410
ab18282d
CW		 1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1415 return -EINVAL;
1416 }
1417
1418
de151cf6
JB		 1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1421 if (ret) {
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
de151cf6 1424 return ret;
13af1062 1425 }
de151cf6
JB		 1426 }
1427
1428 args->offset = obj_priv->mmap_offset;
1429
de151cf6
JB		 1430 /*
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1433 */
1434 if (!obj_priv->agp_mem) {
e67b8ce1 1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1436 if (ret) {
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1439 return ret;
1440 }
14b60391 1441 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1442 }
1443
1444 drm_gem_object_unreference(obj);
1445 mutex_unlock(&dev->struct_mutex);
1446
1447 return 0;
1448}
1449
6911a9b8 1450void
856fa198 1451i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1452{
23010e43 1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1454 int page_count = obj->size / PAGE_SIZE;
1455 int i;
1456
856fa198 1457 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1458 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1459
856fa198
EA		 1460 if (--obj_priv->pages_refcount != 0)
1461 return;
673a394b 1462
280b713b
EA		 1463 if (obj_priv->tiling_mode != I915_TILING_NONE)
1464 i915_gem_object_save_bit_17_swizzle(obj);
1465
3ef94daa 1466 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1467 obj_priv->dirty = 0;
3ef94daa
CW		 1468
1469 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1470 if (obj_priv->dirty)
1471 set_page_dirty(obj_priv->pages[i]);
1472
1473 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1474 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1475
1476 page_cache_release(obj_priv->pages[i]);
1477 }
673a394b
EA		 1478 obj_priv->dirty = 0;
1479
8e7d2b2c 1480 drm_free_large(obj_priv->pages);
856fa198 1481 obj_priv->pages = NULL;
673a394b
EA		 1482}
1483
1484static void
ce44b0ea 1485i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
673a394b
EA		 1486{
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1490
1491 /* Add a reference if we're newly entering the active list. */
1492 if (!obj_priv->active) {
1493 drm_gem_object_reference(obj);
1494 obj_priv->active = 1;
1495 }
1496 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1497 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1498 list_move_tail(&obj_priv->list,
1499 &dev_priv->mm.active_list);
5e118f41 1500 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1501 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1502}
1503
ce44b0ea
EA		 1504static void
1505i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1506{
1507 struct drm_device *dev = obj->dev;
1508 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1510
1511 BUG_ON(!obj_priv->active);
1512 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1513 obj_priv->last_rendering_seqno = 0;
1514}
673a394b 1515
963b4836
CW		 1516/* Immediately discard the backing storage */
1517static void
1518i915_gem_object_truncate(struct drm_gem_object *obj)
1519{
23010e43 1520 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1521 struct inode *inode;
963b4836 1522
bb6baf76
CW		 1523 inode = obj->filp->f_path.dentry->d_inode;
1524 if (inode->i_op->truncate)
1525 inode->i_op->truncate (inode);
1526
1527 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1528}
1529
1530static inline int
1531i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1532{
1533 return obj_priv->madv == I915_MADV_DONTNEED;
1534}
1535
673a394b
EA		 1536static void
1537i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1538{
1539 struct drm_device *dev = obj->dev;
1540 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1541 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1542
1543 i915_verify_inactive(dev, __FILE__, __LINE__);
1544 if (obj_priv->pin_count != 0)
1545 list_del_init(&obj_priv->list);
1546 else
1547 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1548
99fcb766
DV		 1549 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1550
ce44b0ea 1551 obj_priv->last_rendering_seqno = 0;
673a394b
EA		 1552 if (obj_priv->active) {
1553 obj_priv->active = 0;
1554 drm_gem_object_unreference(obj);
1555 }
1556 i915_verify_inactive(dev, __FILE__, __LINE__);
1557}
1558
63560396
DV		 1559static void
1560i915_gem_process_flushing_list(struct drm_device *dev,
1561 uint32_t flush_domains, uint32_t seqno)
1562{
1563 drm_i915_private_t *dev_priv = dev->dev_private;
1564 struct drm_i915_gem_object *obj_priv, *next;
1565
1566 list_for_each_entry_safe(obj_priv, next,
1567 &dev_priv->mm.gpu_write_list,
1568 gpu_write_list) {
1569 struct drm_gem_object *obj = obj_priv->obj;
1570
1571 if ((obj->write_domain & flush_domains) ==
1572 obj->write_domain) {
1573 uint32_t old_write_domain = obj->write_domain;
1574
1575 obj->write_domain = 0;
1576 list_del_init(&obj_priv->gpu_write_list);
1577 i915_gem_object_move_to_active(obj, seqno);
1578
1579 /* update the fence lru list */
1580 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1581 list_move_tail(&obj_priv->fence_list,
1582 &dev_priv->mm.fence_list);
1583
1584 trace_i915_gem_object_change_domain(obj,
1585 obj->read_domains,
1586 old_write_domain);
1587 }
1588 }
1589}
1590
673a394b
EA		 1591/**
1592 * Creates a new sequence number, emitting a write of it to the status page
1593 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1594 *
1595 * Must be called with struct_lock held.
1596 *
1597 * Returned sequence numbers are nonzero on success.
1598 */
5a5a0c64 1599uint32_t
b962442e
EA		 1600i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1601 uint32_t flush_domains)
673a394b
EA		 1602{
1603 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1604 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1605 struct drm_i915_gem_request *request;
1606 uint32_t seqno;
1607 int was_empty;
1608 RING_LOCALS;
1609
b962442e
EA		 1610 if (file_priv != NULL)
1611 i915_file_priv = file_priv->driver_priv;
1612
9a298b2a 1613 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1614 if (request == NULL)
1615 return 0;
1616
1617 /* Grab the seqno we're going to make this request be, and bump the
1618 * next (skipping 0 so it can be the reserved no-seqno value).
1619 */
1620 seqno = dev_priv->mm.next_gem_seqno;
1621 dev_priv->mm.next_gem_seqno++;
1622 if (dev_priv->mm.next_gem_seqno == 0)
1623 dev_priv->mm.next_gem_seqno++;
1624
1625 BEGIN_LP_RING(4);
1626 OUT_RING(MI_STORE_DWORD_INDEX);
1627 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1628 OUT_RING(seqno);
1629
1630 OUT_RING(MI_USER_INTERRUPT);
1631 ADVANCE_LP_RING();
1632
44d98a61 1633 DRM_DEBUG_DRIVER("%d\n", seqno);
673a394b
EA		 1634
1635 request->seqno = seqno;
1636 request->emitted_jiffies = jiffies;
673a394b
EA		 1637 was_empty = list_empty(&dev_priv->mm.request_list);
1638 list_add_tail(&request->list, &dev_priv->mm.request_list);
b962442e
EA		 1639 if (i915_file_priv) {
1640 list_add_tail(&request->client_list,
1641 &i915_file_priv->mm.request_list);
1642 } else {
1643 INIT_LIST_HEAD(&request->client_list);
1644 }
673a394b 1645
ce44b0ea
EA		 1646 /* Associate any objects on the flushing list matching the write
1647 * domain we're flushing with our flush.
1648 */
63560396
DV		 1649 if (flush_domains != 0)
1650 i915_gem_process_flushing_list(dev, flush_domains, seqno);
ce44b0ea 1651
f65d9421
BG		 1652 if (!dev_priv->mm.suspended) {
1653 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1654 if (was_empty)
1655 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1656 }
673a394b
EA		 1657 return seqno;
1658}
1659
1660/**
1661 * Command execution barrier
1662 *
1663 * Ensures that all commands in the ring are finished
1664 * before signalling the CPU
1665 */
3043c60c 1666static uint32_t
673a394b
EA		 1667i915_retire_commands(struct drm_device *dev)
1668{
1669 drm_i915_private_t *dev_priv = dev->dev_private;
1670 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1671 uint32_t flush_domains = 0;
1672 RING_LOCALS;
1673
1674 /* The sampler always gets flushed on i965 (sigh) */
1675 if (IS_I965G(dev))
1676 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1677 BEGIN_LP_RING(2);
1678 OUT_RING(cmd);
1679 OUT_RING(0); /* noop */
1680 ADVANCE_LP_RING();
1681 return flush_domains;
1682}
1683
1684/**
1685 * Moves buffers associated only with the given active seqno from the active
1686 * to inactive list, potentially freeing them.
1687 */
1688static void
1689i915_gem_retire_request(struct drm_device *dev,
1690 struct drm_i915_gem_request *request)
1691{
1692 drm_i915_private_t *dev_priv = dev->dev_private;
1693
1c5d22f7
CW		 1694 trace_i915_gem_request_retire(dev, request->seqno);
1695
673a394b
EA		 1696 /* Move any buffers on the active list that are no longer referenced
1697 * by the ringbuffer to the flushing/inactive lists as appropriate.
1698 */
5e118f41 1699 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1700 while (!list_empty(&dev_priv->mm.active_list)) {
1701 struct drm_gem_object *obj;
1702 struct drm_i915_gem_object *obj_priv;
1703
1704 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1705 struct drm_i915_gem_object,
1706 list);
1707 obj = obj_priv->obj;
1708
1709 /* If the seqno being retired doesn't match the oldest in the
1710 * list, then the oldest in the list must still be newer than
1711 * this seqno.
1712 */
1713 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1714 goto out;
de151cf6 1715
673a394b
EA		 1716#if WATCH_LRU
1717 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1718 __func__, request->seqno, obj);
1719#endif
1720
ce44b0ea
EA		 1721 if (obj->write_domain != 0)
1722 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1723 else {
1724 /* Take a reference on the object so it won't be
1725 * freed while the spinlock is held. The list
1726 * protection for this spinlock is safe when breaking
1727 * the lock like this since the next thing we do
1728 * is just get the head of the list again.
1729 */
1730 drm_gem_object_reference(obj);
673a394b 1731 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1732 spin_unlock(&dev_priv->mm.active_list_lock);
1733 drm_gem_object_unreference(obj);
1734 spin_lock(&dev_priv->mm.active_list_lock);
1735 }
673a394b 1736 }
5e118f41
CW		 1737out:
1738 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1739}
1740
1741/**
1742 * Returns true if seq1 is later than seq2.
1743 */
22be1724 1744bool
673a394b
EA		 1745i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1746{
1747 return (int32_t)(seq1 - seq2) >= 0;
1748}
1749
1750uint32_t
1751i915_get_gem_seqno(struct drm_device *dev)
1752{
1753 drm_i915_private_t *dev_priv = dev->dev_private;
1754
1755 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1756}
1757
1758/**
1759 * This function clears the request list as sequence numbers are passed.
1760 */
1761void
1762i915_gem_retire_requests(struct drm_device *dev)
1763{
1764 drm_i915_private_t *dev_priv = dev->dev_private;
1765 uint32_t seqno;
1766
9d34e5db 1767 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
6c0594a3
KW		 1768 return;
1769
673a394b
EA		 1770 seqno = i915_get_gem_seqno(dev);
1771
1772 while (!list_empty(&dev_priv->mm.request_list)) {
1773 struct drm_i915_gem_request *request;
1774 uint32_t retiring_seqno;
1775
1776 request = list_first_entry(&dev_priv->mm.request_list,
1777 struct drm_i915_gem_request,
1778 list);
1779 retiring_seqno = request->seqno;
1780
1781 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1782 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1783 i915_gem_retire_request(dev, request);
1784
1785 list_del(&request->list);
b962442e 1786 list_del(&request->client_list);
9a298b2a 1787 kfree(request);
673a394b
EA		 1788 } else
1789 break;
1790 }
9d34e5db
CW		 1791
1792 if (unlikely (dev_priv->trace_irq_seqno &&
1793 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1794 i915_user_irq_put(dev);
1795 dev_priv->trace_irq_seqno = 0;
1796 }
673a394b
EA		 1797}
1798
1799void
1800i915_gem_retire_work_handler(struct work_struct *work)
1801{
1802 drm_i915_private_t *dev_priv;
1803 struct drm_device *dev;
1804
1805 dev_priv = container_of(work, drm_i915_private_t,
1806 mm.retire_work.work);
1807 dev = dev_priv->dev;
1808
1809 mutex_lock(&dev->struct_mutex);
1810 i915_gem_retire_requests(dev);
6dbe2772
KP		 1811 if (!dev_priv->mm.suspended &&
1812 !list_empty(&dev_priv->mm.request_list))
9c9fe1f8 1813 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1814 mutex_unlock(&dev->struct_mutex);
1815}
1816
5a5a0c64 1817int
48764bf4 1818i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
673a394b
EA		 1819{
1820 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1821 u32 ier;
673a394b
EA		 1822 int ret = 0;
1823
1824 BUG_ON(seqno == 0);
1825
ba1234d1 1826 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1827 return -EIO;
1828
673a394b 1829 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
bad720ff 1830 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1831 ier = I915_READ(DEIER) | I915_READ(GTIER);
1832 else
1833 ier = I915_READ(IER);
802c7eb6
JB		 1834 if (!ier) {
1835 DRM_ERROR("something (likely vbetool) disabled "
1836 "interrupts, re-enabling\n");
1837 i915_driver_irq_preinstall(dev);
1838 i915_driver_irq_postinstall(dev);
1839 }
1840
1c5d22f7
CW		 1841 trace_i915_gem_request_wait_begin(dev, seqno);
1842
673a394b
EA		 1843 dev_priv->mm.waiting_gem_seqno = seqno;
1844 i915_user_irq_get(dev);
48764bf4
DV		 1845 if (interruptible)
1846 ret = wait_event_interruptible(dev_priv->irq_queue,
1847 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1848 atomic_read(&dev_priv->mm.wedged));
1849 else
1850 wait_event(dev_priv->irq_queue,
1851 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1852 atomic_read(&dev_priv->mm.wedged));
1853
673a394b
EA		 1854 i915_user_irq_put(dev);
1855 dev_priv->mm.waiting_gem_seqno = 0;
1c5d22f7
CW		 1856
1857 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1858 }
ba1234d1 1859 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1860 ret = -EIO;
1861
1862 if (ret && ret != -ERESTARTSYS)
1863 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1864 __func__, ret, seqno, i915_get_gem_seqno(dev));
1865
1866 /* Directly dispatch request retiring. While we have the work queue
1867 * to handle this, the waiter on a request often wants an associated
1868 * buffer to have made it to the inactive list, and we would need
1869 * a separate wait queue to handle that.
1870 */
1871 if (ret == 0)
1872 i915_gem_retire_requests(dev);
1873
1874 return ret;
1875}
1876
48764bf4
DV		 1877/**
1878 * Waits for a sequence number to be signaled, and cleans up the
1879 * request and object lists appropriately for that event.
1880 */
1881static int
1882i915_wait_request(struct drm_device *dev, uint32_t seqno)
1883{
1884 return i915_do_wait_request(dev, seqno, 1);
1885}
1886
673a394b
EA		 1887static void
1888i915_gem_flush(struct drm_device *dev,
1889 uint32_t invalidate_domains,
1890 uint32_t flush_domains)
1891{
1892 drm_i915_private_t *dev_priv = dev->dev_private;
1893 uint32_t cmd;
1894 RING_LOCALS;
1895
1896#if WATCH_EXEC
1897 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1898 invalidate_domains, flush_domains);
1899#endif
1c5d22f7
CW		 1900 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1901 invalidate_domains, flush_domains);
673a394b
EA		 1902
1903 if (flush_domains & I915_GEM_DOMAIN_CPU)
1904 drm_agp_chipset_flush(dev);
1905
21d509e3 1906 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
673a394b
EA		 1907 /*
1908 * read/write caches:
1909 *
1910 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1911 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1912 * also flushed at 2d versus 3d pipeline switches.
1913 *
1914 * read-only caches:
1915 *
1916 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1917 * MI_READ_FLUSH is set, and is always flushed on 965.
1918 *
1919 * I915_GEM_DOMAIN_COMMAND may not exist?
1920 *
1921 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1922 * invalidated when MI_EXE_FLUSH is set.
1923 *
1924 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1925 * invalidated with every MI_FLUSH.
1926 *
1927 * TLBs:
1928 *
1929 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1930 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1931 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1932 * are flushed at any MI_FLUSH.
1933 */
1934
1935 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1936 if ((invalidate_domains|flush_domains) &
1937 I915_GEM_DOMAIN_RENDER)
1938 cmd &= ~MI_NO_WRITE_FLUSH;
1939 if (!IS_I965G(dev)) {
1940 /*
1941 * On the 965, the sampler cache always gets flushed
1942 * and this bit is reserved.
1943 */
1944 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1945 cmd |= MI_READ_FLUSH;
1946 }
1947 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1948 cmd |= MI_EXE_FLUSH;
1949
1950#if WATCH_EXEC
1951 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1952#endif
1953 BEGIN_LP_RING(2);
1954 OUT_RING(cmd);
48764bf4 1955 OUT_RING(MI_NOOP);
673a394b
EA		 1956 ADVANCE_LP_RING();
1957 }
1958}
1959
1960/**
1961 * Ensures that all rendering to the object has completed and the object is
1962 * safe to unbind from the GTT or access from the CPU.
1963 */
1964static int
1965i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1966{
1967 struct drm_device *dev = obj->dev;
23010e43 1968 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1969 int ret;
1970
e47c68e9
EA		 1971 /* This function only exists to support waiting for existing rendering,
1972 * not for emitting required flushes.
673a394b 1973 */
e47c68e9 1974 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1975
1976 /* If there is rendering queued on the buffer being evicted, wait for
1977 * it.
1978 */
1979 if (obj_priv->active) {
1980#if WATCH_BUF
1981 DRM_INFO("%s: object %p wait for seqno %08x\n",
1982 __func__, obj, obj_priv->last_rendering_seqno);
1983#endif
1984 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1985 if (ret != 0)
1986 return ret;
1987 }
1988
1989 return 0;
1990}
1991
1992/**
1993 * Unbinds an object from the GTT aperture.
1994 */
0f973f27 1995int
673a394b
EA		 1996i915_gem_object_unbind(struct drm_gem_object *obj)
1997{
1998 struct drm_device *dev = obj->dev;
4a87b8ca 1999 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2000 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2001 int ret = 0;
2002
2003#if WATCH_BUF
2004 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2005 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2006#endif
2007 if (obj_priv->gtt_space == NULL)
2008 return 0;
2009
2010 if (obj_priv->pin_count != 0) {
2011 DRM_ERROR("Attempting to unbind pinned buffer\n");
2012 return -EINVAL;
2013 }
2014
5323fd04
EA		 2015 /* blow away mappings if mapped through GTT */
2016 i915_gem_release_mmap(obj);
2017
673a394b
EA		 2018 /* Move the object to the CPU domain to ensure that
2019 * any possible CPU writes while it's not in the GTT
2020 * are flushed when we go to remap it. This will
2021 * also ensure that all pending GPU writes are finished
2022 * before we unbind.
2023 */
e47c68e9 2024 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 2025 if (ret) {
e47c68e9
EA		 2026 if (ret != -ERESTARTSYS)
2027 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 2028 return ret;
2029 }
2030
5323fd04
EA		 2031 BUG_ON(obj_priv->active);
2032
96b47b65
DV		 2033 /* release the fence reg _after_ flushing */
2034 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2035 i915_gem_clear_fence_reg(obj);
2036
673a394b
EA		 2037 if (obj_priv->agp_mem != NULL) {
2038 drm_unbind_agp(obj_priv->agp_mem);
2039 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2040 obj_priv->agp_mem = NULL;
2041 }
2042
856fa198 2043 i915_gem_object_put_pages(obj);
a32808c0 2044 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 2045
2046 if (obj_priv->gtt_space) {
2047 atomic_dec(&dev->gtt_count);
2048 atomic_sub(obj->size, &dev->gtt_memory);
2049
2050 drm_mm_put_block(obj_priv->gtt_space);
2051 obj_priv->gtt_space = NULL;
2052 }
2053
2054 /* Remove ourselves from the LRU list if present. */
4a87b8ca 2055 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 2056 if (!list_empty(&obj_priv->list))
2057 list_del_init(&obj_priv->list);
4a87b8ca 2058 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 2059
963b4836
CW		 2060 if (i915_gem_object_is_purgeable(obj_priv))
2061 i915_gem_object_truncate(obj);
2062
1c5d22f7
CW		 2063 trace_i915_gem_object_unbind(obj);
2064
673a394b
EA		 2065 return 0;
2066}
2067
07f73f69
CW		 2068static struct drm_gem_object *
2069i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2070{
2071 drm_i915_private_t *dev_priv = dev->dev_private;
2072 struct drm_i915_gem_object *obj_priv;
2073 struct drm_gem_object *best = NULL;
2074 struct drm_gem_object *first = NULL;
2075
2076 /* Try to find the smallest clean object */
2077 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2078 struct drm_gem_object *obj = obj_priv->obj;
2079 if (obj->size >= min_size) {
963b4836
CW		 2080 if ((!obj_priv->dirty ||
2081 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2082 (!best || obj->size < best->size)) {
2083 best = obj;
2084 if (best->size == min_size)
2085 return best;
2086 }
2087 if (!first)
2088 first = obj;
2089 }
2090 }
2091
2092 return best ? best : first;
2093}
2094
4df2faf4
DV		 2095static int
2096i915_gpu_idle(struct drm_device *dev)
2097{
2098 drm_i915_private_t *dev_priv = dev->dev_private;
2099 bool lists_empty;
2100 uint32_t seqno;
2101
2102 spin_lock(&dev_priv->mm.active_list_lock);
2103 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
2104 list_empty(&dev_priv->mm.active_list);
2105 spin_unlock(&dev_priv->mm.active_list_lock);
2106
2107 if (lists_empty)
2108 return 0;
2109
2110 /* Flush everything onto the inactive list. */
2111 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2112 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2113 if (seqno == 0)
2114 return -ENOMEM;
2115
2116 return i915_wait_request(dev, seqno);
2117}
2118
673a394b 2119static int
07f73f69
CW		 2120i915_gem_evict_everything(struct drm_device *dev)
2121{
2122 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69
CW		 2123 int ret;
2124 bool lists_empty;
2125
07f73f69
CW		 2126 spin_lock(&dev_priv->mm.active_list_lock);
2127 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2128 list_empty(&dev_priv->mm.flushing_list) &&
2129 list_empty(&dev_priv->mm.active_list));
2130 spin_unlock(&dev_priv->mm.active_list_lock);
2131
9731129c 2132 if (lists_empty)
07f73f69 2133 return -ENOSPC;
07f73f69
CW		 2134
2135 /* Flush everything (on to the inactive lists) and evict */
4df2faf4 2136 ret = i915_gpu_idle(dev);
07f73f69
CW		 2137 if (ret)
2138 return ret;
2139
99fcb766
DV		 2140 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2141
ab5ee576 2142 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2143 if (ret)
2144 return ret;
2145
2146 spin_lock(&dev_priv->mm.active_list_lock);
2147 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2148 list_empty(&dev_priv->mm.flushing_list) &&
2149 list_empty(&dev_priv->mm.active_list));
2150 spin_unlock(&dev_priv->mm.active_list_lock);
2151 BUG_ON(!lists_empty);
2152
2153 return 0;
2154}
2155
673a394b 2156static int
07f73f69 2157i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2158{
2159 drm_i915_private_t *dev_priv = dev->dev_private;
2160 struct drm_gem_object *obj;
07f73f69 2161 int ret;
673a394b
EA		 2162
2163 for (;;) {
07f73f69
CW		 2164 i915_gem_retire_requests(dev);
2165
673a394b
EA		 2166 /* If there's an inactive buffer available now, grab it
2167 * and be done.
2168 */
07f73f69
CW		 2169 obj = i915_gem_find_inactive_object(dev, min_size);
2170 if (obj) {
2171 struct drm_i915_gem_object *obj_priv;
2172
673a394b
EA		 2173#if WATCH_LRU
2174 DRM_INFO("%s: evicting %p\n", __func__, obj);
2175#endif
23010e43 2176 obj_priv = to_intel_bo(obj);
07f73f69 2177 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2178 BUG_ON(obj_priv->active);
2179
2180 /* Wait on the rendering and unbind the buffer. */
07f73f69 2181 return i915_gem_object_unbind(obj);
673a394b
EA		 2182 }
2183
2184 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2185 * things, wait for the next to finish and hopefully leave us
2186 * a buffer to evict.
673a394b
EA		 2187 */
2188 if (!list_empty(&dev_priv->mm.request_list)) {
2189 struct drm_i915_gem_request *request;
2190
2191 request = list_first_entry(&dev_priv->mm.request_list,
2192 struct drm_i915_gem_request,
2193 list);
2194
2195 ret = i915_wait_request(dev, request->seqno);
2196 if (ret)
07f73f69 2197 return ret;
673a394b 2198
07f73f69 2199 continue;
673a394b
EA		 2200 }
2201
2202 /* If we didn't have anything on the request list but there
2203 * are buffers awaiting a flush, emit one and try again.
2204 * When we wait on it, those buffers waiting for that flush
2205 * will get moved to inactive.
2206 */
2207 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2208 struct drm_i915_gem_object *obj_priv;
673a394b 2209
9a1e2582
CW		 2210 /* Find an object that we can immediately reuse */
2211 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2212 obj = obj_priv->obj;
2213 if (obj->size >= min_size)
2214 break;
673a394b 2215
9a1e2582
CW		 2216 obj = NULL;
2217 }
673a394b 2218
9a1e2582
CW		 2219 if (obj != NULL) {
2220 uint32_t seqno;
673a394b 2221
9a1e2582
CW		 2222 i915_gem_flush(dev,
2223 obj->write_domain,
2224 obj->write_domain);
2225 seqno = i915_add_request(dev, NULL, obj->write_domain);
2226 if (seqno == 0)
2227 return -ENOMEM;
9a1e2582
CW		 2228 continue;
2229 }
673a394b
EA		 2230 }
2231
07f73f69
CW		 2232 /* If we didn't do any of the above, there's no single buffer
2233 * large enough to swap out for the new one, so just evict
2234 * everything and start again. (This should be rare.)
673a394b 2235 */
9731129c 2236 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2237 return i915_gem_evict_from_inactive_list(dev);
9731129c 2238 else
07f73f69 2239 return i915_gem_evict_everything(dev);
ac94a962 2240 }
ac94a962
KP		 2241}
2242
6911a9b8 2243int
4bdadb97
CW		 2244i915_gem_object_get_pages(struct drm_gem_object *obj,
2245 gfp_t gfpmask)
673a394b 2246{
23010e43 2247 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2248 int page_count, i;
2249 struct address_space *mapping;
2250 struct inode *inode;
2251 struct page *page;
673a394b 2252
856fa198 2253 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2254 return 0;
2255
2256 /* Get the list of pages out of our struct file. They'll be pinned
2257 * at this point until we release them.
2258 */
2259 page_count = obj->size / PAGE_SIZE;
856fa198 2260 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2261 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2262 if (obj_priv->pages == NULL) {
856fa198 2263 obj_priv->pages_refcount--;
673a394b
EA		 2264 return -ENOMEM;
2265 }
2266
2267 inode = obj->filp->f_path.dentry->d_inode;
2268 mapping = inode->i_mapping;
2269 for (i = 0; i < page_count; i++) {
4bdadb97
CW		 2270 page = read_cache_page_gfp(mapping, i,
2271 mapping_gfp_mask (mapping) |
2272 __GFP_COLD |
2273 gfpmask);
1f2b1013
CW		 2274 if (IS_ERR(page))
2275 goto err_pages;
2276
856fa198 2277 obj_priv->pages[i] = page;
673a394b 2278 }
280b713b
EA		 2279
2280 if (obj_priv->tiling_mode != I915_TILING_NONE)
2281 i915_gem_object_do_bit_17_swizzle(obj);
2282
673a394b 2283 return 0;
1f2b1013
CW		 2284
2285err_pages:
2286 while (i--)
2287 page_cache_release(obj_priv->pages[i]);
2288
2289 drm_free_large(obj_priv->pages);
2290 obj_priv->pages = NULL;
2291 obj_priv->pages_refcount--;
2292 return PTR_ERR(page);
673a394b
EA		 2293}
2294
4e901fdc
EA		 2295static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2296{
2297 struct drm_gem_object *obj = reg->obj;
2298 struct drm_device *dev = obj->dev;
2299 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2301 int regnum = obj_priv->fence_reg;
2302 uint64_t val;
2303
2304 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2305 0xfffff000) << 32;
2306 val |= obj_priv->gtt_offset & 0xfffff000;
2307 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2308 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2309
2310 if (obj_priv->tiling_mode == I915_TILING_Y)
2311 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2312 val |= I965_FENCE_REG_VALID;
2313
2314 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2315}
2316
de151cf6
JB		 2317static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2318{
2319 struct drm_gem_object *obj = reg->obj;
2320 struct drm_device *dev = obj->dev;
2321 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2322 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2323 int regnum = obj_priv->fence_reg;
2324 uint64_t val;
2325
2326 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2327 0xfffff000) << 32;
2328 val |= obj_priv->gtt_offset & 0xfffff000;
2329 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2330 if (obj_priv->tiling_mode == I915_TILING_Y)
2331 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2332 val |= I965_FENCE_REG_VALID;
2333
2334 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2335}
2336
2337static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2338{
2339 struct drm_gem_object *obj = reg->obj;
2340 struct drm_device *dev = obj->dev;
2341 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2343 int regnum = obj_priv->fence_reg;
0f973f27 2344 int tile_width;
dc529a4f 2345 uint32_t fence_reg, val;
de151cf6
JB		 2346 uint32_t pitch_val;
2347
2348 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2349 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2350 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2351 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2352 return;
2353 }
2354
0f973f27
JB		 2355 if (obj_priv->tiling_mode == I915_TILING_Y &&
2356 HAS_128_BYTE_Y_TILING(dev))
2357 tile_width = 128;
de151cf6 2358 else
0f973f27
JB		 2359 tile_width = 512;
2360
2361 /* Note: pitch better be a power of two tile widths */
2362 pitch_val = obj_priv->stride / tile_width;
2363 pitch_val = ffs(pitch_val) - 1;
de151cf6
JB		 2364
2365 val = obj_priv->gtt_offset;
2366 if (obj_priv->tiling_mode == I915_TILING_Y)
2367 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2368 val |= I915_FENCE_SIZE_BITS(obj->size);
2369 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2370 val |= I830_FENCE_REG_VALID;
2371
dc529a4f
EA		 2372 if (regnum < 8)
2373 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2374 else
2375 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2376 I915_WRITE(fence_reg, val);
de151cf6
JB		 2377}
2378
2379static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2380{
2381 struct drm_gem_object *obj = reg->obj;
2382 struct drm_device *dev = obj->dev;
2383 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2384 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2385 int regnum = obj_priv->fence_reg;
2386 uint32_t val;
2387 uint32_t pitch_val;
8d7773a3 2388 uint32_t fence_size_bits;
de151cf6 2389
8d7773a3 2390 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2391 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2392 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2393 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2394 return;
2395 }
2396
e76a16de
EA		 2397 pitch_val = obj_priv->stride / 128;
2398 pitch_val = ffs(pitch_val) - 1;
2399 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2400
de151cf6
JB		 2401 val = obj_priv->gtt_offset;
2402 if (obj_priv->tiling_mode == I915_TILING_Y)
2403 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2404 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2405 WARN_ON(fence_size_bits & ~0x00000f00);
2406 val |= fence_size_bits;
de151cf6
JB		 2407 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2408 val |= I830_FENCE_REG_VALID;
2409
2410 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2411}
2412
ae3db24a
DV		 2413static int i915_find_fence_reg(struct drm_device *dev)
2414{
2415 struct drm_i915_fence_reg *reg = NULL;
2416 struct drm_i915_gem_object *obj_priv = NULL;
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct drm_gem_object *obj = NULL;
2419 int i, avail, ret;
2420
2421 /* First try to find a free reg */
2422 avail = 0;
2423 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2424 reg = &dev_priv->fence_regs[i];
2425 if (!reg->obj)
2426 return i;
2427
23010e43 2428 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2429 if (!obj_priv->pin_count)
2430 avail++;
2431 }
2432
2433 if (avail == 0)
2434 return -ENOSPC;
2435
2436 /* None available, try to steal one or wait for a user to finish */
2437 i = I915_FENCE_REG_NONE;
2438 list_for_each_entry(obj_priv, &dev_priv->mm.fence_list,
2439 fence_list) {
2440 obj = obj_priv->obj;
2441
2442 if (obj_priv->pin_count)
2443 continue;
2444
2445 /* found one! */
2446 i = obj_priv->fence_reg;
2447 break;
2448 }
2449
2450 BUG_ON(i == I915_FENCE_REG_NONE);
2451
2452 /* We only have a reference on obj from the active list. put_fence_reg
2453 * might drop that one, causing a use-after-free in it. So hold a
2454 * private reference to obj like the other callers of put_fence_reg
2455 * (set_tiling ioctl) do. */
2456 drm_gem_object_reference(obj);
2457 ret = i915_gem_object_put_fence_reg(obj);
2458 drm_gem_object_unreference(obj);
2459 if (ret != 0)
2460 return ret;
2461
2462 return i;
2463}
2464
de151cf6
JB		 2465/**
2466 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2467 * @obj: object to map through a fence reg
2468 *
2469 * When mapping objects through the GTT, userspace wants to be able to write
2470 * to them without having to worry about swizzling if the object is tiled.
2471 *
2472 * This function walks the fence regs looking for a free one for @obj,
2473 * stealing one if it can't find any.
2474 *
2475 * It then sets up the reg based on the object's properties: address, pitch
2476 * and tiling format.
2477 */
8c4b8c3f
CW		 2478int
2479i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2480{
2481 struct drm_device *dev = obj->dev;
79e53945 2482 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2483 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2484 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2485 int ret;
de151cf6 2486
a09ba7fa
EA		 2487 /* Just update our place in the LRU if our fence is getting used. */
2488 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2489 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2490 return 0;
2491 }
2492
de151cf6
JB		 2493 switch (obj_priv->tiling_mode) {
2494 case I915_TILING_NONE:
2495 WARN(1, "allocating a fence for non-tiled object?\n");
2496 break;
2497 case I915_TILING_X:
0f973f27
JB		 2498 if (!obj_priv->stride)
2499 return -EINVAL;
2500 WARN((obj_priv->stride & (512 - 1)),
2501 "object 0x%08x is X tiled but has non-512B pitch\n",
2502 obj_priv->gtt_offset);
de151cf6
JB		 2503 break;
2504 case I915_TILING_Y:
0f973f27
JB		 2505 if (!obj_priv->stride)
2506 return -EINVAL;
2507 WARN((obj_priv->stride & (128 - 1)),
2508 "object 0x%08x is Y tiled but has non-128B pitch\n",
2509 obj_priv->gtt_offset);
de151cf6
JB		 2510 break;
2511 }
2512
ae3db24a
DV		 2513 ret = i915_find_fence_reg(dev);
2514 if (ret < 0)
2515 return ret;
de151cf6 2516
ae3db24a
DV		 2517 obj_priv->fence_reg = ret;
2518 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
a09ba7fa
EA		 2519 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2520
de151cf6
JB		 2521 reg->obj = obj;
2522
4e901fdc
EA		 2523 if (IS_GEN6(dev))
2524 sandybridge_write_fence_reg(reg);
2525 else if (IS_I965G(dev))
de151cf6
JB		 2526 i965_write_fence_reg(reg);
2527 else if (IS_I9XX(dev))
2528 i915_write_fence_reg(reg);
2529 else
2530 i830_write_fence_reg(reg);
d9ddcb96 2531
ae3db24a
DV		 2532 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2533 obj_priv->tiling_mode);
1c5d22f7 2534
d9ddcb96 2535 return 0;
de151cf6
JB		 2536}
2537
2538/**
2539 * i915_gem_clear_fence_reg - clear out fence register info
2540 * @obj: object to clear
2541 *
2542 * Zeroes out the fence register itself and clears out the associated
2543 * data structures in dev_priv and obj_priv.
2544 */
2545static void
2546i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2547{
2548 struct drm_device *dev = obj->dev;
79e53945 2549 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2550 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2551
4e901fdc
EA		 2552 if (IS_GEN6(dev)) {
2553 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2554 (obj_priv->fence_reg * 8), 0);
2555 } else if (IS_I965G(dev)) {
de151cf6 2556 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2557 } else {
dc529a4f
EA		 2558 uint32_t fence_reg;
2559
2560 if (obj_priv->fence_reg < 8)
2561 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2562 else
2563 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2564 8) * 4;
2565
2566 I915_WRITE(fence_reg, 0);
2567 }
de151cf6
JB		 2568
2569 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2570 obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2571 list_del_init(&obj_priv->fence_list);
de151cf6
JB		 2572}
2573
52dc7d32
CW		 2574/**
2575 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2576 * to the buffer to finish, and then resets the fence register.
2577 * @obj: tiled object holding a fence register.
2578 *
2579 * Zeroes out the fence register itself and clears out the associated
2580 * data structures in dev_priv and obj_priv.
2581 */
2582int
2583i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2584{
2585 struct drm_device *dev = obj->dev;
23010e43 2586 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2587
2588 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2589 return 0;
2590
10ae9bd2
DV		 2591 /* If we've changed tiling, GTT-mappings of the object
2592 * need to re-fault to ensure that the correct fence register
2593 * setup is in place.
2594 */
2595 i915_gem_release_mmap(obj);
2596
52dc7d32
CW		 2597 /* On the i915, GPU access to tiled buffers is via a fence,
2598 * therefore we must wait for any outstanding access to complete
2599 * before clearing the fence.
2600 */
2601 if (!IS_I965G(dev)) {
2602 int ret;
2603
2604 i915_gem_object_flush_gpu_write_domain(obj);
52dc7d32
CW		 2605 ret = i915_gem_object_wait_rendering(obj);
2606 if (ret != 0)
2607 return ret;
2608 }
2609
4a726612 2610 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2611 i915_gem_clear_fence_reg (obj);
2612
2613 return 0;
2614}
2615
673a394b
EA		 2616/**
2617 * Finds free space in the GTT aperture and binds the object there.
2618 */
2619static int
2620i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2621{
2622 struct drm_device *dev = obj->dev;
2623 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2624 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2625 struct drm_mm_node *free_space;
4bdadb97 2626 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2627 int ret;
673a394b 2628
bb6baf76 2629 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2630 DRM_ERROR("Attempting to bind a purgeable object\n");
2631 return -EINVAL;
2632 }
2633
673a394b 2634 if (alignment == 0)
0f973f27 2635 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2636 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2637 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2638 return -EINVAL;
2639 }
2640
2641 search_free:
2642 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2643 obj->size, alignment, 0);
2644 if (free_space != NULL) {
2645 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2646 alignment);
2647 if (obj_priv->gtt_space != NULL) {
2648 obj_priv->gtt_space->private = obj;
2649 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2650 }
2651 }
2652 if (obj_priv->gtt_space == NULL) {
2653 /* If the gtt is empty and we're still having trouble
2654 * fitting our object in, we're out of memory.
2655 */
2656#if WATCH_LRU
2657 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2658#endif
07f73f69 2659 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2660 if (ret)
673a394b 2661 return ret;
9731129c 2662
673a394b
EA		 2663 goto search_free;
2664 }
2665
2666#if WATCH_BUF
cfd43c02 2667 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2668 obj->size, obj_priv->gtt_offset);
2669#endif
4bdadb97 2670 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2671 if (ret) {
2672 drm_mm_put_block(obj_priv->gtt_space);
2673 obj_priv->gtt_space = NULL;
07f73f69
CW		 2674
2675 if (ret == -ENOMEM) {
2676 /* first try to clear up some space from the GTT */
2677 ret = i915_gem_evict_something(dev, obj->size);
2678 if (ret) {
07f73f69 2679 /* now try to shrink everyone else */
4bdadb97
CW		 2680 if (gfpmask) {
2681 gfpmask = 0;
2682 goto search_free;
07f73f69
CW		 2683 }
2684
2685 return ret;
2686 }
2687
2688 goto search_free;
2689 }
2690
673a394b
EA		 2691 return ret;
2692 }
2693
673a394b
EA		 2694 /* Create an AGP memory structure pointing at our pages, and bind it
2695 * into the GTT.
2696 */
2697 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2698 obj_priv->pages,
07f73f69 2699 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2700 obj_priv->gtt_offset,
2701 obj_priv->agp_type);
673a394b 2702 if (obj_priv->agp_mem == NULL) {
856fa198 2703 i915_gem_object_put_pages(obj);
673a394b
EA		 2704 drm_mm_put_block(obj_priv->gtt_space);
2705 obj_priv->gtt_space = NULL;
07f73f69
CW		 2706
2707 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2708 if (ret)
07f73f69 2709 return ret;
07f73f69
CW		 2710
2711 goto search_free;
673a394b
EA		 2712 }
2713 atomic_inc(&dev->gtt_count);
2714 atomic_add(obj->size, &dev->gtt_memory);
2715
2716 /* Assert that the object is not currently in any GPU domain. As it
2717 * wasn't in the GTT, there shouldn't be any way it could have been in
2718 * a GPU cache
2719 */
21d509e3
CW		 2720 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2721 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2722
1c5d22f7
CW		 2723 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2724
673a394b
EA		 2725 return 0;
2726}
2727
2728void
2729i915_gem_clflush_object(struct drm_gem_object *obj)
2730{
23010e43 2731 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2732
2733 /* If we don't have a page list set up, then we're not pinned
2734 * to GPU, and we can ignore the cache flush because it'll happen
2735 * again at bind time.
2736 */
856fa198 2737 if (obj_priv->pages == NULL)
673a394b
EA		 2738 return;
2739
1c5d22f7 2740 trace_i915_gem_object_clflush(obj);
cfa16a0d 2741
856fa198 2742 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2743}
2744
e47c68e9
EA		 2745/** Flushes any GPU write domain for the object if it's dirty. */
2746static void
2747i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2748{
2749 struct drm_device *dev = obj->dev;
1c5d22f7 2750 uint32_t old_write_domain;
e47c68e9
EA		 2751
2752 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2753 return;
2754
2755 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2756 old_write_domain = obj->write_domain;
e47c68e9 2757 i915_gem_flush(dev, 0, obj->write_domain);
922a2efc 2758 (void) i915_add_request(dev, NULL, obj->write_domain);
99fcb766 2759 BUG_ON(obj->write_domain);
1c5d22f7
CW		 2760
2761 trace_i915_gem_object_change_domain(obj,
2762 obj->read_domains,
2763 old_write_domain);
e47c68e9
EA		 2764}
2765
2766/** Flushes the GTT write domain for the object if it's dirty. */
2767static void
2768i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2769{
1c5d22f7
CW		 2770 uint32_t old_write_domain;
2771
e47c68e9
EA		 2772 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2773 return;
2774
2775 /* No actual flushing is required for the GTT write domain. Writes
2776 * to it immediately go to main memory as far as we know, so there's
2777 * no chipset flush. It also doesn't land in render cache.
2778 */
1c5d22f7 2779 old_write_domain = obj->write_domain;
e47c68e9 2780 obj->write_domain = 0;
1c5d22f7
CW		 2781
2782 trace_i915_gem_object_change_domain(obj,
2783 obj->read_domains,
2784 old_write_domain);
e47c68e9
EA		 2785}
2786
2787/** Flushes the CPU write domain for the object if it's dirty. */
2788static void
2789i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2790{
2791 struct drm_device *dev = obj->dev;
1c5d22f7 2792 uint32_t old_write_domain;
e47c68e9
EA		 2793
2794 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2795 return;
2796
2797 i915_gem_clflush_object(obj);
2798 drm_agp_chipset_flush(dev);
1c5d22f7 2799 old_write_domain = obj->write_domain;
e47c68e9 2800 obj->write_domain = 0;
1c5d22f7
CW		 2801
2802 trace_i915_gem_object_change_domain(obj,
2803 obj->read_domains,
2804 old_write_domain);
e47c68e9
EA		 2805}
2806
6b95a207
KH		 2807void
2808i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2809{
2810 switch (obj->write_domain) {
2811 case I915_GEM_DOMAIN_GTT:
2812 i915_gem_object_flush_gtt_write_domain(obj);
2813 break;
2814 case I915_GEM_DOMAIN_CPU:
2815 i915_gem_object_flush_cpu_write_domain(obj);
2816 break;
2817 default:
2818 i915_gem_object_flush_gpu_write_domain(obj);
2819 break;
2820 }
2821}
2822
2ef7eeaa
EA		 2823/**
2824 * Moves a single object to the GTT read, and possibly write domain.
2825 *
2826 * This function returns when the move is complete, including waiting on
2827 * flushes to occur.
2828 */
79e53945 2829int
2ef7eeaa
EA		 2830i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2831{
23010e43 2832 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2833 uint32_t old_write_domain, old_read_domains;
e47c68e9 2834 int ret;
2ef7eeaa 2835
02354392
EA		 2836 /* Not valid to be called on unbound objects. */
2837 if (obj_priv->gtt_space == NULL)
2838 return -EINVAL;
2839
e47c68e9
EA		 2840 i915_gem_object_flush_gpu_write_domain(obj);
2841 /* Wait on any GPU rendering and flushing to occur. */
2842 ret = i915_gem_object_wait_rendering(obj);
2843 if (ret != 0)
2844 return ret;
2845
1c5d22f7
CW		 2846 old_write_domain = obj->write_domain;
2847 old_read_domains = obj->read_domains;
2848
e47c68e9
EA		 2849 /* If we're writing through the GTT domain, then CPU and GPU caches
2850 * will need to be invalidated at next use.
2ef7eeaa 2851 */
e47c68e9
EA		 2852 if (write)
2853 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2854
e47c68e9 2855 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2856
e47c68e9
EA		 2857 /* It should now be out of any other write domains, and we can update
2858 * the domain values for our changes.
2859 */
2860 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2861 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2862 if (write) {
2863 obj->write_domain = I915_GEM_DOMAIN_GTT;
2864 obj_priv->dirty = 1;
2ef7eeaa
EA		 2865 }
2866
1c5d22f7
CW		 2867 trace_i915_gem_object_change_domain(obj,
2868 old_read_domains,
2869 old_write_domain);
2870
e47c68e9
EA		 2871 return 0;
2872}
2873
b9241ea3
ZW		 2874/*
2875 * Prepare buffer for display plane. Use uninterruptible for possible flush
2876 * wait, as in modesetting process we're not supposed to be interrupted.
2877 */
2878int
2879i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2880{
2881 struct drm_device *dev = obj->dev;
23010e43 2882 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2883 uint32_t old_write_domain, old_read_domains;
2884 int ret;
2885
2886 /* Not valid to be called on unbound objects. */
2887 if (obj_priv->gtt_space == NULL)
2888 return -EINVAL;
2889
2890 i915_gem_object_flush_gpu_write_domain(obj);
2891
2892 /* Wait on any GPU rendering and flushing to occur. */
2893 if (obj_priv->active) {
2894#if WATCH_BUF
2895 DRM_INFO("%s: object %p wait for seqno %08x\n",
2896 __func__, obj, obj_priv->last_rendering_seqno);
2897#endif
2898 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2899 if (ret != 0)
2900 return ret;
2901 }
2902
2903 old_write_domain = obj->write_domain;
2904 old_read_domains = obj->read_domains;
2905
2906 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2907
2908 i915_gem_object_flush_cpu_write_domain(obj);
2909
2910 /* It should now be out of any other write domains, and we can update
2911 * the domain values for our changes.
2912 */
2913 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2914 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2915 obj->write_domain = I915_GEM_DOMAIN_GTT;
2916 obj_priv->dirty = 1;
2917
2918 trace_i915_gem_object_change_domain(obj,
2919 old_read_domains,
2920 old_write_domain);
2921
2922 return 0;
2923}
2924
e47c68e9
EA		 2925/**
2926 * Moves a single object to the CPU read, and possibly write domain.
2927 *
2928 * This function returns when the move is complete, including waiting on
2929 * flushes to occur.
2930 */
2931static int
2932i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2933{
1c5d22f7 2934 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2935 int ret;
2936
2937 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2938 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2939 ret = i915_gem_object_wait_rendering(obj);
2940 if (ret != 0)
2941 return ret;
2ef7eeaa 2942
e47c68e9 2943 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2944
e47c68e9
EA		 2945 /* If we have a partially-valid cache of the object in the CPU,
2946 * finish invalidating it and free the per-page flags.
2ef7eeaa 2947 */
e47c68e9 2948 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2949
1c5d22f7
CW		 2950 old_write_domain = obj->write_domain;
2951 old_read_domains = obj->read_domains;
2952
e47c68e9
EA		 2953 /* Flush the CPU cache if it's still invalid. */
2954 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2955 i915_gem_clflush_object(obj);
2ef7eeaa 2956
e47c68e9 2957 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2958 }
2959
2960 /* It should now be out of any other write domains, and we can update
2961 * the domain values for our changes.
2962 */
e47c68e9
EA		 2963 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2964
2965 /* If we're writing through the CPU, then the GPU read domains will
2966 * need to be invalidated at next use.
2967 */
2968 if (write) {
2969 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2970 obj->write_domain = I915_GEM_DOMAIN_CPU;
2971 }
2ef7eeaa 2972
1c5d22f7
CW		 2973 trace_i915_gem_object_change_domain(obj,
2974 old_read_domains,
2975 old_write_domain);
2976
2ef7eeaa
EA		 2977 return 0;
2978}
2979
673a394b
EA		 2980/*
2981 * Set the next domain for the specified object. This
2982 * may not actually perform the necessary flushing/invaliding though,
2983 * as that may want to be batched with other set_domain operations
2984 *
2985 * This is (we hope) the only really tricky part of gem. The goal
2986 * is fairly simple -- track which caches hold bits of the object
2987 * and make sure they remain coherent. A few concrete examples may
2988 * help to explain how it works. For shorthand, we use the notation
2989 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2990 * a pair of read and write domain masks.
2991 *
2992 * Case 1: the batch buffer
2993 *
2994 * 1. Allocated
2995 * 2. Written by CPU
2996 * 3. Mapped to GTT
2997 * 4. Read by GPU
2998 * 5. Unmapped from GTT
2999 * 6. Freed
3000 *
3001 * Let's take these a step at a time
3002 *
3003 * 1. Allocated
3004 * Pages allocated from the kernel may still have
3005 * cache contents, so we set them to (CPU, CPU) always.
3006 * 2. Written by CPU (using pwrite)
3007 * The pwrite function calls set_domain (CPU, CPU) and
3008 * this function does nothing (as nothing changes)
3009 * 3. Mapped by GTT
3010 * This function asserts that the object is not
3011 * currently in any GPU-based read or write domains
3012 * 4. Read by GPU
3013 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3014 * As write_domain is zero, this function adds in the
3015 * current read domains (CPU+COMMAND, 0).
3016 * flush_domains is set to CPU.
3017 * invalidate_domains is set to COMMAND
3018 * clflush is run to get data out of the CPU caches
3019 * then i915_dev_set_domain calls i915_gem_flush to
3020 * emit an MI_FLUSH and drm_agp_chipset_flush
3021 * 5. Unmapped from GTT
3022 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3023 * flush_domains and invalidate_domains end up both zero
3024 * so no flushing/invalidating happens
3025 * 6. Freed
3026 * yay, done
3027 *
3028 * Case 2: The shared render buffer
3029 *
3030 * 1. Allocated
3031 * 2. Mapped to GTT
3032 * 3. Read/written by GPU
3033 * 4. set_domain to (CPU,CPU)
3034 * 5. Read/written by CPU
3035 * 6. Read/written by GPU
3036 *
3037 * 1. Allocated
3038 * Same as last example, (CPU, CPU)
3039 * 2. Mapped to GTT
3040 * Nothing changes (assertions find that it is not in the GPU)
3041 * 3. Read/written by GPU
3042 * execbuffer calls set_domain (RENDER, RENDER)
3043 * flush_domains gets CPU
3044 * invalidate_domains gets GPU
3045 * clflush (obj)
3046 * MI_FLUSH and drm_agp_chipset_flush
3047 * 4. set_domain (CPU, CPU)
3048 * flush_domains gets GPU
3049 * invalidate_domains gets CPU
3050 * wait_rendering (obj) to make sure all drawing is complete.
3051 * This will include an MI_FLUSH to get the data from GPU
3052 * to memory
3053 * clflush (obj) to invalidate the CPU cache
3054 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3055 * 5. Read/written by CPU
3056 * cache lines are loaded and dirtied
3057 * 6. Read written by GPU
3058 * Same as last GPU access
3059 *
3060 * Case 3: The constant buffer
3061 *
3062 * 1. Allocated
3063 * 2. Written by CPU
3064 * 3. Read by GPU
3065 * 4. Updated (written) by CPU again
3066 * 5. Read by GPU
3067 *
3068 * 1. Allocated
3069 * (CPU, CPU)
3070 * 2. Written by CPU
3071 * (CPU, CPU)
3072 * 3. Read by GPU
3073 * (CPU+RENDER, 0)
3074 * flush_domains = CPU
3075 * invalidate_domains = RENDER
3076 * clflush (obj)
3077 * MI_FLUSH
3078 * drm_agp_chipset_flush
3079 * 4. Updated (written) by CPU again
3080 * (CPU, CPU)
3081 * flush_domains = 0 (no previous write domain)
3082 * invalidate_domains = 0 (no new read domains)
3083 * 5. Read by GPU
3084 * (CPU+RENDER, 0)
3085 * flush_domains = CPU
3086 * invalidate_domains = RENDER
3087 * clflush (obj)
3088 * MI_FLUSH
3089 * drm_agp_chipset_flush
3090 */
c0d90829 3091static void
8b0e378a 3092i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3093{
3094 struct drm_device *dev = obj->dev;
23010e43 3095 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3096 uint32_t invalidate_domains = 0;
3097 uint32_t flush_domains = 0;
1c5d22f7 3098 uint32_t old_read_domains;
e47c68e9 3099
8b0e378a
EA		 3100 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3101 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3102
652c393a
JB		 3103 intel_mark_busy(dev, obj);
3104
673a394b
EA		 3105#if WATCH_BUF
3106 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3107 __func__, obj,
8b0e378a
EA		 3108 obj->read_domains, obj->pending_read_domains,
3109 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3110#endif
3111 /*
3112 * If the object isn't moving to a new write domain,
3113 * let the object stay in multiple read domains
3114 */
8b0e378a
EA		 3115 if (obj->pending_write_domain == 0)
3116 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3117 else
3118 obj_priv->dirty = 1;
3119
3120 /*
3121 * Flush the current write domain if
3122 * the new read domains don't match. Invalidate
3123 * any read domains which differ from the old
3124 * write domain
3125 */
8b0e378a
EA		 3126 if (obj->write_domain &&
3127 obj->write_domain != obj->pending_read_domains) {
673a394b 3128 flush_domains |= obj->write_domain;
8b0e378a
EA		 3129 invalidate_domains |=
3130 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3131 }
3132 /*
3133 * Invalidate any read caches which may have
3134 * stale data. That is, any new read domains.
3135 */
8b0e378a 3136 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3137 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3138#if WATCH_BUF
3139 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3140 __func__, flush_domains, invalidate_domains);
3141#endif
673a394b
EA		 3142 i915_gem_clflush_object(obj);
3143 }
3144
1c5d22f7
CW		 3145 old_read_domains = obj->read_domains;
3146
efbeed96
EA		 3147 /* The actual obj->write_domain will be updated with
3148 * pending_write_domain after we emit the accumulated flush for all
3149 * of our domain changes in execbuffers (which clears objects'
3150 * write_domains). So if we have a current write domain that we
3151 * aren't changing, set pending_write_domain to that.
3152 */
3153 if (flush_domains == 0 && obj->pending_write_domain == 0)
3154 obj->pending_write_domain = obj->write_domain;
8b0e378a 3155 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3156
3157 dev->invalidate_domains |= invalidate_domains;
3158 dev->flush_domains |= flush_domains;
3159#if WATCH_BUF
3160 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3161 __func__,
3162 obj->read_domains, obj->write_domain,
3163 dev->invalidate_domains, dev->flush_domains);
3164#endif
1c5d22f7
CW		 3165
3166 trace_i915_gem_object_change_domain(obj,
3167 old_read_domains,
3168 obj->write_domain);
673a394b
EA		 3169}
3170
3171/**
e47c68e9 3172 * Moves the object from a partially CPU read to a full one.
673a394b 3173 *
e47c68e9
EA		 3174 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3175 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3176 */
e47c68e9
EA		 3177static void
3178i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3179{
23010e43 3180 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3181
e47c68e9
EA		 3182 if (!obj_priv->page_cpu_valid)
3183 return;
3184
3185 /* If we're partially in the CPU read domain, finish moving it in.
3186 */
3187 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3188 int i;
3189
3190 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3191 if (obj_priv->page_cpu_valid[i])
3192 continue;
856fa198 3193 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3194 }
e47c68e9
EA		 3195 }
3196
3197 /* Free the page_cpu_valid mappings which are now stale, whether
3198 * or not we've got I915_GEM_DOMAIN_CPU.
3199 */
9a298b2a 3200 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3201 obj_priv->page_cpu_valid = NULL;
3202}
3203
3204/**
3205 * Set the CPU read domain on a range of the object.
3206 *
3207 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3208 * not entirely valid. The page_cpu_valid member of the object flags which
3209 * pages have been flushed, and will be respected by
3210 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3211 * of the whole object.
3212 *
3213 * This function returns when the move is complete, including waiting on
3214 * flushes to occur.
3215 */
3216static int
3217i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3218 uint64_t offset, uint64_t size)
3219{
23010e43 3220 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3221 uint32_t old_read_domains;
e47c68e9 3222 int i, ret;
673a394b 3223
e47c68e9
EA		 3224 if (offset == 0 && size == obj->size)
3225 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3226
e47c68e9
EA		 3227 i915_gem_object_flush_gpu_write_domain(obj);
3228 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3229 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3230 if (ret != 0)
6a47baa6 3231 return ret;
e47c68e9
EA		 3232 i915_gem_object_flush_gtt_write_domain(obj);
3233
3234 /* If we're already fully in the CPU read domain, we're done. */
3235 if (obj_priv->page_cpu_valid == NULL &&
3236 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3237 return 0;
673a394b 3238
e47c68e9
EA		 3239 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3240 * newly adding I915_GEM_DOMAIN_CPU
3241 */
673a394b 3242 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3243 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3244 GFP_KERNEL);
e47c68e9
EA		 3245 if (obj_priv->page_cpu_valid == NULL)
3246 return -ENOMEM;
3247 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3248 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3249
3250 /* Flush the cache on any pages that are still invalid from the CPU's
3251 * perspective.
3252 */
e47c68e9
EA		 3253 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3254 i++) {
673a394b
EA		 3255 if (obj_priv->page_cpu_valid[i])
3256 continue;
3257
856fa198 3258 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3259
3260 obj_priv->page_cpu_valid[i] = 1;
3261 }
3262
e47c68e9
EA		 3263 /* It should now be out of any other write domains, and we can update
3264 * the domain values for our changes.
3265 */
3266 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3267
1c5d22f7 3268 old_read_domains = obj->read_domains;
e47c68e9
EA		 3269 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3270
1c5d22f7
CW		 3271 trace_i915_gem_object_change_domain(obj,
3272 old_read_domains,
3273 obj->write_domain);
3274
673a394b
EA		 3275 return 0;
3276}
3277
673a394b
EA		 3278/**
3279 * Pin an object to the GTT and evaluate the relocations landing in it.
3280 */
3281static int
3282i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3283 struct drm_file *file_priv,
76446cac 3284 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3285 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3286{
3287 struct drm_device *dev = obj->dev;
0839ccb8 3288 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3289 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3290 int i, ret;
0839ccb8 3291 void __iomem *reloc_page;
76446cac
JB		 3292 bool need_fence;
3293
3294 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3295 obj_priv->tiling_mode != I915_TILING_NONE;
3296
3297 /* Check fence reg constraints and rebind if necessary */
f590d279
OA		 3298 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3299 obj_priv->tiling_mode))
76446cac 3300 i915_gem_object_unbind(obj);
673a394b
EA		 3301
3302 /* Choose the GTT offset for our buffer and put it there. */
3303 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3304 if (ret)
3305 return ret;
3306
76446cac
JB		 3307 /*
3308 * Pre-965 chips need a fence register set up in order to
3309 * properly handle blits to/from tiled surfaces.
3310 */
3311 if (need_fence) {
3312 ret = i915_gem_object_get_fence_reg(obj);
3313 if (ret != 0) {
3314 if (ret != -EBUSY && ret != -ERESTARTSYS)
3315 DRM_ERROR("Failure to install fence: %d\n",
3316 ret);
3317 i915_gem_object_unpin(obj);
3318 return ret;
3319 }
3320 }
3321
673a394b
EA		 3322 entry->offset = obj_priv->gtt_offset;
3323
673a394b
EA		 3324 /* Apply the relocations, using the GTT aperture to avoid cache
3325 * flushing requirements.
3326 */
3327 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3328 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3329 struct drm_gem_object *target_obj;
3330 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3331 uint32_t reloc_val, reloc_offset;
3332 uint32_t __iomem *reloc_entry;
673a394b 3333
673a394b 3334 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3335 reloc->target_handle);
673a394b
EA		 3336 if (target_obj == NULL) {
3337 i915_gem_object_unpin(obj);
3338 return -EBADF;
3339 }
23010e43 3340 target_obj_priv = to_intel_bo(target_obj);
673a394b 3341
8542a0bb
CW		 3342#if WATCH_RELOC
3343 DRM_INFO("%s: obj %p offset %08x target %d "
3344 "read %08x write %08x gtt %08x "
3345 "presumed %08x delta %08x\n",
3346 __func__,
3347 obj,
3348 (int) reloc->offset,
3349 (int) reloc->target_handle,
3350 (int) reloc->read_domains,
3351 (int) reloc->write_domain,
3352 (int) target_obj_priv->gtt_offset,
3353 (int) reloc->presumed_offset,
3354 reloc->delta);
3355#endif
3356
673a394b
EA		 3357 /* The target buffer should have appeared before us in the
3358 * exec_object list, so it should have a GTT space bound by now.
3359 */
3360 if (target_obj_priv->gtt_space == NULL) {
3361 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3362 reloc->target_handle);
673a394b
EA		 3363 drm_gem_object_unreference(target_obj);
3364 i915_gem_object_unpin(obj);
3365 return -EINVAL;
3366 }
3367
8542a0bb 3368 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3369 if (reloc->write_domain & (reloc->write_domain - 1)) {
3370 DRM_ERROR("reloc with multiple write domains: "
3371 "obj %p target %d offset %d "
3372 "read %08x write %08x",
3373 obj, reloc->target_handle,
3374 (int) reloc->offset,
3375 reloc->read_domains,
3376 reloc->write_domain);
3377 return -EINVAL;
3378 }
40a5f0de
EA		 3379 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3380 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3381 DRM_ERROR("reloc with read/write CPU domains: "
3382 "obj %p target %d offset %d "
3383 "read %08x write %08x",
40a5f0de
EA		 3384 obj, reloc->target_handle,
3385 (int) reloc->offset,
3386 reloc->read_domains,
3387 reloc->write_domain);
491152b8
CW		 3388 drm_gem_object_unreference(target_obj);
3389 i915_gem_object_unpin(obj);
e47c68e9
EA		 3390 return -EINVAL;
3391 }
40a5f0de
EA		 3392 if (reloc->write_domain && target_obj->pending_write_domain &&
3393 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3394 DRM_ERROR("Write domain conflict: "
3395 "obj %p target %d offset %d "
3396 "new %08x old %08x\n",
40a5f0de
EA		 3397 obj, reloc->target_handle,
3398 (int) reloc->offset,
3399 reloc->write_domain,
673a394b
EA		 3400 target_obj->pending_write_domain);
3401 drm_gem_object_unreference(target_obj);
3402 i915_gem_object_unpin(obj);
3403 return -EINVAL;
3404 }
3405
40a5f0de
EA		 3406 target_obj->pending_read_domains |= reloc->read_domains;
3407 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3408
3409 /* If the relocation already has the right value in it, no
3410 * more work needs to be done.
3411 */
40a5f0de 3412 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3413 drm_gem_object_unreference(target_obj);
3414 continue;
3415 }
3416
8542a0bb
CW		 3417 /* Check that the relocation address is valid... */
3418 if (reloc->offset > obj->size - 4) {
3419 DRM_ERROR("Relocation beyond object bounds: "
3420 "obj %p target %d offset %d size %d.\n",
3421 obj, reloc->target_handle,
3422 (int) reloc->offset, (int) obj->size);
3423 drm_gem_object_unreference(target_obj);
3424 i915_gem_object_unpin(obj);
3425 return -EINVAL;
3426 }
3427 if (reloc->offset & 3) {
3428 DRM_ERROR("Relocation not 4-byte aligned: "
3429 "obj %p target %d offset %d.\n",
3430 obj, reloc->target_handle,
3431 (int) reloc->offset);
3432 drm_gem_object_unreference(target_obj);
3433 i915_gem_object_unpin(obj);
3434 return -EINVAL;
3435 }
3436
3437 /* and points to somewhere within the target object. */
3438 if (reloc->delta >= target_obj->size) {
3439 DRM_ERROR("Relocation beyond target object bounds: "
3440 "obj %p target %d delta %d size %d.\n",
3441 obj, reloc->target_handle,
3442 (int) reloc->delta, (int) target_obj->size);
3443 drm_gem_object_unreference(target_obj);
3444 i915_gem_object_unpin(obj);
3445 return -EINVAL;
3446 }
3447
2ef7eeaa
EA		 3448 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3449 if (ret != 0) {
3450 drm_gem_object_unreference(target_obj);
3451 i915_gem_object_unpin(obj);
3452 return -EINVAL;
673a394b
EA		 3453 }
3454
3455 /* Map the page containing the relocation we're going to
3456 * perform.
3457 */
40a5f0de 3458 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3459 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3460 (reloc_offset &
3461 ~(PAGE_SIZE - 1)));
3043c60c 3462 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3463 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3464 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3465
3466#if WATCH_BUF
3467 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3468 obj, (unsigned int) reloc->offset,
673a394b
EA		 3469 readl(reloc_entry), reloc_val);
3470#endif
3471 writel(reloc_val, reloc_entry);
0839ccb8 3472 io_mapping_unmap_atomic(reloc_page);
673a394b 3473
40a5f0de
EA		 3474 /* The updated presumed offset for this entry will be
3475 * copied back out to the user.
673a394b 3476 */
40a5f0de 3477 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3478
3479 drm_gem_object_unreference(target_obj);
3480 }
3481
673a394b
EA		 3482#if WATCH_BUF
3483 if (0)
3484 i915_gem_dump_object(obj, 128, __func__, ~0);
3485#endif
3486 return 0;
3487}
3488
3489/** Dispatch a batchbuffer to the ring
3490 */
3491static int
3492i915_dispatch_gem_execbuffer(struct drm_device *dev,
76446cac 3493 struct drm_i915_gem_execbuffer2 *exec,
201361a5 3494 struct drm_clip_rect *cliprects,
673a394b
EA		 3495 uint64_t exec_offset)
3496{
3497 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3498 int nbox = exec->num_cliprects;
3499 int i = 0, count;
83d60795 3500 uint32_t exec_start, exec_len;
673a394b
EA		 3501 RING_LOCALS;
3502
3503 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3504 exec_len = (uint32_t) exec->batch_len;
3505
8f0dc5bf 3506 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
1c5d22f7 3507
673a394b
EA		 3508 count = nbox ? nbox : 1;
3509
3510 for (i = 0; i < count; i++) {
3511 if (i < nbox) {
201361a5 3512 int ret = i915_emit_box(dev, cliprects, i,
673a394b
EA		 3513 exec->DR1, exec->DR4);
3514 if (ret)
3515 return ret;
3516 }
3517
3518 if (IS_I830(dev) || IS_845G(dev)) {
3519 BEGIN_LP_RING(4);
3520 OUT_RING(MI_BATCH_BUFFER);
3521 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3522 OUT_RING(exec_start + exec_len - 4);
3523 OUT_RING(0);
3524 ADVANCE_LP_RING();
3525 } else {
3526 BEGIN_LP_RING(2);
3527 if (IS_I965G(dev)) {
3528 OUT_RING(MI_BATCH_BUFFER_START |
3529 (2 << 6) |
3530 MI_BATCH_NON_SECURE_I965);
3531 OUT_RING(exec_start);
3532 } else {
3533 OUT_RING(MI_BATCH_BUFFER_START |
3534 (2 << 6));
3535 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3536 }
3537 ADVANCE_LP_RING();
3538 }
3539 }
3540
3541 /* XXX breadcrumb */
3542 return 0;
3543}
3544
3545/* Throttle our rendering by waiting until the ring has completed our requests
3546 * emitted over 20 msec ago.
3547 *
b962442e
EA		 3548 * Note that if we were to use the current jiffies each time around the loop,
3549 * we wouldn't escape the function with any frames outstanding if the time to
3550 * render a frame was over 20ms.
3551 *
673a394b
EA		 3552 * This should get us reasonable parallelism between CPU and GPU but also
3553 * relatively low latency when blocking on a particular request to finish.
3554 */
3555static int
3556i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3557{
3558 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3559 int ret = 0;
b962442e 3560 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3561
3562 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3563 while (!list_empty(&i915_file_priv->mm.request_list)) {
3564 struct drm_i915_gem_request *request;
3565
3566 request = list_first_entry(&i915_file_priv->mm.request_list,
3567 struct drm_i915_gem_request,
3568 client_list);
3569
3570 if (time_after_eq(request->emitted_jiffies, recent_enough))
3571 break;
3572
3573 ret = i915_wait_request(dev, request->seqno);
3574 if (ret != 0)
3575 break;
3576 }
673a394b 3577 mutex_unlock(&dev->struct_mutex);
b962442e 3578
673a394b
EA		 3579 return ret;
3580}
3581
40a5f0de 3582static int
76446cac 3583i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3584 uint32_t buffer_count,
3585 struct drm_i915_gem_relocation_entry **relocs)
3586{
3587 uint32_t reloc_count = 0, reloc_index = 0, i;
3588 int ret;
3589
3590 *relocs = NULL;
3591 for (i = 0; i < buffer_count; i++) {
3592 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3593 return -EINVAL;
3594 reloc_count += exec_list[i].relocation_count;
3595 }
3596
8e7d2b2c 3597 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3598 if (*relocs == NULL) {
3599 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3600 return -ENOMEM;
76446cac 3601 }
40a5f0de
EA		 3602
3603 for (i = 0; i < buffer_count; i++) {
3604 struct drm_i915_gem_relocation_entry __user *user_relocs;
3605
3606 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3607
3608 ret = copy_from_user(&(*relocs)[reloc_index],
3609 user_relocs,
3610 exec_list[i].relocation_count *
3611 sizeof(**relocs));
3612 if (ret != 0) {
8e7d2b2c 3613 drm_free_large(*relocs);
40a5f0de 3614 *relocs = NULL;
2bc43b5c 3615 return -EFAULT;
40a5f0de
EA		 3616 }
3617
3618 reloc_index += exec_list[i].relocation_count;
3619 }
3620
2bc43b5c 3621 return 0;
40a5f0de
EA		 3622}
3623
3624static int
76446cac 3625i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3626 uint32_t buffer_count,
3627 struct drm_i915_gem_relocation_entry *relocs)
3628{
3629 uint32_t reloc_count = 0, i;
2bc43b5c 3630 int ret = 0;
40a5f0de 3631
93533c29
CW		 3632 if (relocs == NULL)
3633 return 0;
3634
40a5f0de
EA		 3635 for (i = 0; i < buffer_count; i++) {
3636 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3637 int unwritten;
40a5f0de
EA		 3638
3639 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3640
2bc43b5c
FM		 3641 unwritten = copy_to_user(user_relocs,
3642 &relocs[reloc_count],
3643 exec_list[i].relocation_count *
3644 sizeof(*relocs));
3645
3646 if (unwritten) {
3647 ret = -EFAULT;
3648 goto err;
40a5f0de
EA		 3649 }
3650
3651 reloc_count += exec_list[i].relocation_count;
3652 }
3653
2bc43b5c 3654err:
8e7d2b2c 3655 drm_free_large(relocs);
40a5f0de
EA		 3656
3657 return ret;
3658}
3659
83d60795 3660static int
76446cac 3661i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3662 uint64_t exec_offset)
3663{
3664 uint32_t exec_start, exec_len;
3665
3666 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3667 exec_len = (uint32_t) exec->batch_len;
3668
3669 if ((exec_start | exec_len) & 0x7)
3670 return -EINVAL;
3671
3672 if (!exec_start)
3673 return -EINVAL;
3674
3675 return 0;
3676}
3677
6b95a207
KH		 3678static int
3679i915_gem_wait_for_pending_flip(struct drm_device *dev,
3680 struct drm_gem_object **object_list,
3681 int count)
3682{
3683 drm_i915_private_t *dev_priv = dev->dev_private;
3684 struct drm_i915_gem_object *obj_priv;
3685 DEFINE_WAIT(wait);
3686 int i, ret = 0;
3687
3688 for (;;) {
3689 prepare_to_wait(&dev_priv->pending_flip_queue,
3690 &wait, TASK_INTERRUPTIBLE);
3691 for (i = 0; i < count; i++) {
23010e43 3692 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3693 if (atomic_read(&obj_priv->pending_flip) > 0)
3694 break;
3695 }
3696 if (i == count)
3697 break;
3698
3699 if (!signal_pending(current)) {
3700 mutex_unlock(&dev->struct_mutex);
3701 schedule();
3702 mutex_lock(&dev->struct_mutex);
3703 continue;
3704 }
3705 ret = -ERESTARTSYS;
3706 break;
3707 }
3708 finish_wait(&dev_priv->pending_flip_queue, &wait);
3709
3710 return ret;
3711}
3712
673a394b 3713int
76446cac
JB		 3714i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3715 struct drm_file *file_priv,
3716 struct drm_i915_gem_execbuffer2 *args,
3717 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3718{
3719 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3720 struct drm_gem_object **object_list = NULL;
3721 struct drm_gem_object *batch_obj;
b70d11da 3722 struct drm_i915_gem_object *obj_priv;
201361a5 3723 struct drm_clip_rect *cliprects = NULL;
93533c29 3724 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3725 int ret = 0, ret2, i, pinned = 0;
673a394b 3726 uint64_t exec_offset;
40a5f0de 3727 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3728 int pin_tries, flips;
673a394b
EA		 3729
3730#if WATCH_EXEC
3731 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3732 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3733#endif
3734
4f481ed2
EA		 3735 if (args->buffer_count < 1) {
3736 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3737 return -EINVAL;
3738 }
c8e0f93a 3739 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3740 if (object_list == NULL) {
3741 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3742 args->buffer_count);
3743 ret = -ENOMEM;
3744 goto pre_mutex_err;
3745 }
673a394b 3746
201361a5 3747 if (args->num_cliprects != 0) {
9a298b2a
EA		 3748 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3749 GFP_KERNEL);
a40e8d31
OA		 3750 if (cliprects == NULL) {
3751 ret = -ENOMEM;
201361a5 3752 goto pre_mutex_err;
a40e8d31 3753 }
201361a5
EA		 3754
3755 ret = copy_from_user(cliprects,
3756 (struct drm_clip_rect __user *)
3757 (uintptr_t) args->cliprects_ptr,
3758 sizeof(*cliprects) * args->num_cliprects);
3759 if (ret != 0) {
3760 DRM_ERROR("copy %d cliprects failed: %d\n",
3761 args->num_cliprects, ret);
3762 goto pre_mutex_err;
3763 }
3764 }
3765
40a5f0de
EA		 3766 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3767 &relocs);
3768 if (ret != 0)
3769 goto pre_mutex_err;
3770
673a394b
EA		 3771 mutex_lock(&dev->struct_mutex);
3772
3773 i915_verify_inactive(dev, __FILE__, __LINE__);
3774
ba1234d1 3775 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3776 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3777 ret = -EIO;
3778 goto pre_mutex_err;
673a394b
EA		 3779 }
3780
3781 if (dev_priv->mm.suspended) {
673a394b 3782 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3783 ret = -EBUSY;
3784 goto pre_mutex_err;
673a394b
EA		 3785 }
3786
ac94a962 3787 /* Look up object handles */
6b95a207 3788 flips = 0;
673a394b
EA		 3789 for (i = 0; i < args->buffer_count; i++) {
3790 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3791 exec_list[i].handle);
3792 if (object_list[i] == NULL) {
3793 DRM_ERROR("Invalid object handle %d at index %d\n",
3794 exec_list[i].handle, i);
0ce907f8
CW		 3795 /* prevent error path from reading uninitialized data */
3796 args->buffer_count = i + 1;
673a394b
EA		 3797 ret = -EBADF;
3798 goto err;
3799 }
b70d11da 3800
23010e43 3801 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3802 if (obj_priv->in_execbuffer) {
3803 DRM_ERROR("Object %p appears more than once in object list\n",
3804 object_list[i]);
0ce907f8
CW		 3805 /* prevent error path from reading uninitialized data */
3806 args->buffer_count = i + 1;
b70d11da
KH		 3807 ret = -EBADF;
3808 goto err;
3809 }
3810 obj_priv->in_execbuffer = true;
6b95a207
KH		 3811 flips += atomic_read(&obj_priv->pending_flip);
3812 }
3813
3814 if (flips > 0) {
3815 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3816 args->buffer_count);
3817 if (ret)
3818 goto err;
ac94a962 3819 }
673a394b 3820
ac94a962
KP		 3821 /* Pin and relocate */
3822 for (pin_tries = 0; ; pin_tries++) {
3823 ret = 0;
40a5f0de
EA		 3824 reloc_index = 0;
3825
ac94a962
KP		 3826 for (i = 0; i < args->buffer_count; i++) {
3827 object_list[i]->pending_read_domains = 0;
3828 object_list[i]->pending_write_domain = 0;
3829 ret = i915_gem_object_pin_and_relocate(object_list[i],
3830 file_priv,
40a5f0de
EA		 3831 &exec_list[i],
3832 &relocs[reloc_index]);
ac94a962
KP		 3833 if (ret)
3834 break;
3835 pinned = i + 1;
40a5f0de 3836 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3837 }
3838 /* success */
3839 if (ret == 0)
3840 break;
3841
3842 /* error other than GTT full, or we've already tried again */
2939e1f5 3843 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3844 if (ret != -ERESTARTSYS) {
3845 unsigned long long total_size = 0;
3846 for (i = 0; i < args->buffer_count; i++)
3847 total_size += object_list[i]->size;
3848 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3849 pinned+1, args->buffer_count,
3850 total_size, ret);
3851 DRM_ERROR("%d objects [%d pinned], "
3852 "%d object bytes [%d pinned], "
3853 "%d/%d gtt bytes\n",
3854 atomic_read(&dev->object_count),
3855 atomic_read(&dev->pin_count),
3856 atomic_read(&dev->object_memory),
3857 atomic_read(&dev->pin_memory),
3858 atomic_read(&dev->gtt_memory),
3859 dev->gtt_total);
3860 }
673a394b
EA		 3861 goto err;
3862 }
ac94a962
KP		 3863
3864 /* unpin all of our buffers */
3865 for (i = 0; i < pinned; i++)
3866 i915_gem_object_unpin(object_list[i]);
b1177636 3867 pinned = 0;
ac94a962
KP		 3868
3869 /* evict everyone we can from the aperture */
3870 ret = i915_gem_evict_everything(dev);
07f73f69 3871 if (ret && ret != -ENOSPC)
ac94a962 3872 goto err;
673a394b
EA		 3873 }
3874
3875 /* Set the pending read domains for the batch buffer to COMMAND */
3876 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3877 if (batch_obj->pending_write_domain) {
3878 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3879 ret = -EINVAL;
3880 goto err;
3881 }
3882 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3883
83d60795
CW		 3884 /* Sanity check the batch buffer, prior to moving objects */
3885 exec_offset = exec_list[args->buffer_count - 1].offset;
3886 ret = i915_gem_check_execbuffer (args, exec_offset);
3887 if (ret != 0) {
3888 DRM_ERROR("execbuf with invalid offset/length\n");
3889 goto err;
3890 }
3891
673a394b
EA		 3892 i915_verify_inactive(dev, __FILE__, __LINE__);
3893
646f0f6e
KP		 3894 /* Zero the global flush/invalidate flags. These
3895 * will be modified as new domains are computed
3896 * for each object
3897 */
3898 dev->invalidate_domains = 0;
3899 dev->flush_domains = 0;
3900
673a394b
EA		 3901 for (i = 0; i < args->buffer_count; i++) {
3902 struct drm_gem_object *obj = object_list[i];
673a394b 3903
646f0f6e 3904 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3905 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3906 }
3907
3908 i915_verify_inactive(dev, __FILE__, __LINE__);
3909
646f0f6e
KP		 3910 if (dev->invalidate_domains | dev->flush_domains) {
3911#if WATCH_EXEC
3912 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3913 __func__,
3914 dev->invalidate_domains,
3915 dev->flush_domains);
3916#endif
3917 i915_gem_flush(dev,
3918 dev->invalidate_domains,
3919 dev->flush_domains);
99fcb766 3920 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
b962442e
EA		 3921 (void)i915_add_request(dev, file_priv,
3922 dev->flush_domains);
646f0f6e 3923 }
673a394b 3924
efbeed96
EA		 3925 for (i = 0; i < args->buffer_count; i++) {
3926 struct drm_gem_object *obj = object_list[i];
23010e43 3927 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3928 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3929
3930 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3931 if (obj->write_domain)
3932 list_move_tail(&obj_priv->gpu_write_list,
3933 &dev_priv->mm.gpu_write_list);
3934 else
3935 list_del_init(&obj_priv->gpu_write_list);
3936
1c5d22f7
CW		 3937 trace_i915_gem_object_change_domain(obj,
3938 obj->read_domains,
3939 old_write_domain);
efbeed96
EA		 3940 }
3941
673a394b
EA		 3942 i915_verify_inactive(dev, __FILE__, __LINE__);
3943
3944#if WATCH_COHERENCY
3945 for (i = 0; i < args->buffer_count; i++) {
3946 i915_gem_object_check_coherency(object_list[i],
3947 exec_list[i].handle);
3948 }
3949#endif
3950
673a394b 3951#if WATCH_EXEC
6911a9b8 3952 i915_gem_dump_object(batch_obj,
673a394b
EA		 3953 args->batch_len,
3954 __func__,
3955 ~0);
3956#endif
3957
673a394b 3958 /* Exec the batchbuffer */
201361a5 3959 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
673a394b
EA		 3960 if (ret) {
3961 DRM_ERROR("dispatch failed %d\n", ret);
3962 goto err;
3963 }
3964
3965 /*
3966 * Ensure that the commands in the batch buffer are
3967 * finished before the interrupt fires
3968 */
3969 flush_domains = i915_retire_commands(dev);
3970
3971 i915_verify_inactive(dev, __FILE__, __LINE__);
3972
3973 /*
3974 * Get a seqno representing the execution of the current buffer,
3975 * which we can wait on. We would like to mitigate these interrupts,
3976 * likely by only creating seqnos occasionally (so that we have
3977 * *some* interrupts representing completion of buffers that we can
3978 * wait on when trying to clear up gtt space).
3979 */
b962442e 3980 seqno = i915_add_request(dev, file_priv, flush_domains);
673a394b 3981 BUG_ON(seqno == 0);
673a394b
EA		 3982 for (i = 0; i < args->buffer_count; i++) {
3983 struct drm_gem_object *obj = object_list[i];
673a394b 3984
ce44b0ea 3985 i915_gem_object_move_to_active(obj, seqno);
673a394b
EA		 3986#if WATCH_LRU
3987 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3988#endif
3989 }
3990#if WATCH_LRU
3991 i915_dump_lru(dev, __func__);
3992#endif
3993
3994 i915_verify_inactive(dev, __FILE__, __LINE__);
3995
673a394b 3996err:
aad87dff
JL		 3997 for (i = 0; i < pinned; i++)
3998 i915_gem_object_unpin(object_list[i]);
3999
b70d11da
KH		 4000 for (i = 0; i < args->buffer_count; i++) {
4001 if (object_list[i]) {
23010e43 4002 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 4003 obj_priv->in_execbuffer = false;
4004 }
aad87dff 4005 drm_gem_object_unreference(object_list[i]);
b70d11da 4006 }
673a394b 4007
673a394b
EA		 4008 mutex_unlock(&dev->struct_mutex);
4009
93533c29 4010pre_mutex_err:
40a5f0de
EA		 4011 /* Copy the updated relocations out regardless of current error
4012 * state. Failure to update the relocs would mean that the next
4013 * time userland calls execbuf, it would do so with presumed offset
4014 * state that didn't match the actual object state.
4015 */
4016 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4017 relocs);
4018 if (ret2 != 0) {
4019 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4020
4021 if (ret == 0)
4022 ret = ret2;
4023 }
4024
8e7d2b2c 4025 drm_free_large(object_list);
9a298b2a 4026 kfree(cliprects);
673a394b
EA		 4027
4028 return ret;
4029}
4030
76446cac
JB		 4031/*
4032 * Legacy execbuffer just creates an exec2 list from the original exec object
4033 * list array and passes it to the real function.
4034 */
4035int
4036i915_gem_execbuffer(struct drm_device *dev, void *data,
4037 struct drm_file *file_priv)
4038{
4039 struct drm_i915_gem_execbuffer *args = data;
4040 struct drm_i915_gem_execbuffer2 exec2;
4041 struct drm_i915_gem_exec_object *exec_list = NULL;
4042 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4043 int ret, i;
4044
4045#if WATCH_EXEC
4046 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4047 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4048#endif
4049
4050 if (args->buffer_count < 1) {
4051 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4052 return -EINVAL;
4053 }
4054
4055 /* Copy in the exec list from userland */
4056 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4057 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4058 if (exec_list == NULL || exec2_list == NULL) {
4059 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4060 args->buffer_count);
4061 drm_free_large(exec_list);
4062 drm_free_large(exec2_list);
4063 return -ENOMEM;
4064 }
4065 ret = copy_from_user(exec_list,
4066 (struct drm_i915_relocation_entry __user *)
4067 (uintptr_t) args->buffers_ptr,
4068 sizeof(*exec_list) * args->buffer_count);
4069 if (ret != 0) {
4070 DRM_ERROR("copy %d exec entries failed %d\n",
4071 args->buffer_count, ret);
4072 drm_free_large(exec_list);
4073 drm_free_large(exec2_list);
4074 return -EFAULT;
4075 }
4076
4077 for (i = 0; i < args->buffer_count; i++) {
4078 exec2_list[i].handle = exec_list[i].handle;
4079 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4080 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4081 exec2_list[i].alignment = exec_list[i].alignment;
4082 exec2_list[i].offset = exec_list[i].offset;
4083 if (!IS_I965G(dev))
4084 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4085 else
4086 exec2_list[i].flags = 0;
4087 }
4088
4089 exec2.buffers_ptr = args->buffers_ptr;
4090 exec2.buffer_count = args->buffer_count;
4091 exec2.batch_start_offset = args->batch_start_offset;
4092 exec2.batch_len = args->batch_len;
4093 exec2.DR1 = args->DR1;
4094 exec2.DR4 = args->DR4;
4095 exec2.num_cliprects = args->num_cliprects;
4096 exec2.cliprects_ptr = args->cliprects_ptr;
4097 exec2.flags = 0;
4098
4099 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4100 if (!ret) {
4101 /* Copy the new buffer offsets back to the user's exec list. */
4102 for (i = 0; i < args->buffer_count; i++)
4103 exec_list[i].offset = exec2_list[i].offset;
4104 /* ... and back out to userspace */
4105 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4106 (uintptr_t) args->buffers_ptr,
4107 exec_list,
4108 sizeof(*exec_list) * args->buffer_count);
4109 if (ret) {
4110 ret = -EFAULT;
4111 DRM_ERROR("failed to copy %d exec entries "
4112 "back to user (%d)\n",
4113 args->buffer_count, ret);
4114 }
76446cac
JB		 4115 }
4116
4117 drm_free_large(exec_list);
4118 drm_free_large(exec2_list);
4119 return ret;
4120}
4121
4122int
4123i915_gem_execbuffer2(struct drm_device *dev, void *data,
4124 struct drm_file *file_priv)
4125{
4126 struct drm_i915_gem_execbuffer2 *args = data;
4127 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4128 int ret;
4129
4130#if WATCH_EXEC
4131 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4132 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4133#endif
4134
4135 if (args->buffer_count < 1) {
4136 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4137 return -EINVAL;
4138 }
4139
4140 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4141 if (exec2_list == NULL) {
4142 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4143 args->buffer_count);
4144 return -ENOMEM;
4145 }
4146 ret = copy_from_user(exec2_list,
4147 (struct drm_i915_relocation_entry __user *)
4148 (uintptr_t) args->buffers_ptr,
4149 sizeof(*exec2_list) * args->buffer_count);
4150 if (ret != 0) {
4151 DRM_ERROR("copy %d exec entries failed %d\n",
4152 args->buffer_count, ret);
4153 drm_free_large(exec2_list);
4154 return -EFAULT;
4155 }
4156
4157 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4158 if (!ret) {
4159 /* Copy the new buffer offsets back to the user's exec list. */
4160 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4161 (uintptr_t) args->buffers_ptr,
4162 exec2_list,
4163 sizeof(*exec2_list) * args->buffer_count);
4164 if (ret) {
4165 ret = -EFAULT;
4166 DRM_ERROR("failed to copy %d exec entries "
4167 "back to user (%d)\n",
4168 args->buffer_count, ret);
4169 }
4170 }
4171
4172 drm_free_large(exec2_list);
4173 return ret;
4174}
4175
673a394b
EA		 4176int
4177i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4178{
4179 struct drm_device *dev = obj->dev;
23010e43 4180 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4181 int ret;
4182
4183 i915_verify_inactive(dev, __FILE__, __LINE__);
4184 if (obj_priv->gtt_space == NULL) {
4185 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4186 if (ret)
673a394b 4187 return ret;
22c344e9 4188 }
76446cac 4189
673a394b
EA		 4190 obj_priv->pin_count++;
4191
4192 /* If the object is not active and not pending a flush,
4193 * remove it from the inactive list
4194 */
4195 if (obj_priv->pin_count == 1) {
4196 atomic_inc(&dev->pin_count);
4197 atomic_add(obj->size, &dev->pin_memory);
4198 if (!obj_priv->active &&
21d509e3 4199 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4200 !list_empty(&obj_priv->list))
4201 list_del_init(&obj_priv->list);
4202 }
4203 i915_verify_inactive(dev, __FILE__, __LINE__);
4204
4205 return 0;
4206}
4207
4208void
4209i915_gem_object_unpin(struct drm_gem_object *obj)
4210{
4211 struct drm_device *dev = obj->dev;
4212 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4213 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4214
4215 i915_verify_inactive(dev, __FILE__, __LINE__);
4216 obj_priv->pin_count--;
4217 BUG_ON(obj_priv->pin_count < 0);
4218 BUG_ON(obj_priv->gtt_space == NULL);
4219
4220 /* If the object is no longer pinned, and is
4221 * neither active nor being flushed, then stick it on
4222 * the inactive list
4223 */
4224 if (obj_priv->pin_count == 0) {
4225 if (!obj_priv->active &&
21d509e3 4226 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4227 list_move_tail(&obj_priv->list,
4228 &dev_priv->mm.inactive_list);
4229 atomic_dec(&dev->pin_count);
4230 atomic_sub(obj->size, &dev->pin_memory);
4231 }
4232 i915_verify_inactive(dev, __FILE__, __LINE__);
4233}
4234
4235int
4236i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4237 struct drm_file *file_priv)
4238{
4239 struct drm_i915_gem_pin *args = data;
4240 struct drm_gem_object *obj;
4241 struct drm_i915_gem_object *obj_priv;
4242 int ret;
4243
4244 mutex_lock(&dev->struct_mutex);
4245
4246 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4247 if (obj == NULL) {
4248 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4249 args->handle);
4250 mutex_unlock(&dev->struct_mutex);
4251 return -EBADF;
4252 }
23010e43 4253 obj_priv = to_intel_bo(obj);
673a394b 4254
bb6baf76
CW		 4255 if (obj_priv->madv != I915_MADV_WILLNEED) {
4256 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4257 drm_gem_object_unreference(obj);
4258 mutex_unlock(&dev->struct_mutex);
4259 return -EINVAL;
4260 }
4261
79e53945
JB		 4262 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4263 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4264 args->handle);
96dec61d 4265 drm_gem_object_unreference(obj);
673a394b 4266 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4267 return -EINVAL;
4268 }
4269
4270 obj_priv->user_pin_count++;
4271 obj_priv->pin_filp = file_priv;
4272 if (obj_priv->user_pin_count == 1) {
4273 ret = i915_gem_object_pin(obj, args->alignment);
4274 if (ret != 0) {
4275 drm_gem_object_unreference(obj);
4276 mutex_unlock(&dev->struct_mutex);
4277 return ret;
4278 }
673a394b
EA		 4279 }
4280
4281 /* XXX - flush the CPU caches for pinned objects
4282 * as the X server doesn't manage domains yet
4283 */
e47c68e9 4284 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4285 args->offset = obj_priv->gtt_offset;
4286 drm_gem_object_unreference(obj);
4287 mutex_unlock(&dev->struct_mutex);
4288
4289 return 0;
4290}
4291
4292int
4293i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4294 struct drm_file *file_priv)
4295{
4296 struct drm_i915_gem_pin *args = data;
4297 struct drm_gem_object *obj;
79e53945 4298 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4299
4300 mutex_lock(&dev->struct_mutex);
4301
4302 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4303 if (obj == NULL) {
4304 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4305 args->handle);
4306 mutex_unlock(&dev->struct_mutex);
4307 return -EBADF;
4308 }
4309
23010e43 4310 obj_priv = to_intel_bo(obj);
79e53945
JB		 4311 if (obj_priv->pin_filp != file_priv) {
4312 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4313 args->handle);
4314 drm_gem_object_unreference(obj);
4315 mutex_unlock(&dev->struct_mutex);
4316 return -EINVAL;
4317 }
4318 obj_priv->user_pin_count--;
4319 if (obj_priv->user_pin_count == 0) {
4320 obj_priv->pin_filp = NULL;
4321 i915_gem_object_unpin(obj);
4322 }
673a394b
EA		 4323
4324 drm_gem_object_unreference(obj);
4325 mutex_unlock(&dev->struct_mutex);
4326 return 0;
4327}
4328
4329int
4330i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4331 struct drm_file *file_priv)
4332{
4333 struct drm_i915_gem_busy *args = data;
4334 struct drm_gem_object *obj;
4335 struct drm_i915_gem_object *obj_priv;
4336
673a394b
EA		 4337 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4338 if (obj == NULL) {
4339 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4340 args->handle);
673a394b
EA		 4341 return -EBADF;
4342 }
4343
b1ce786c 4344 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4345 /* Update the active list for the hardware's current position.
4346 * Otherwise this only updates on a delayed timer or when irqs are
4347 * actually unmasked, and our working set ends up being larger than
4348 * required.
4349 */
4350 i915_gem_retire_requests(dev);
4351
23010e43 4352 obj_priv = to_intel_bo(obj);
c4de0a5d
EA		 4353 /* Don't count being on the flushing list against the object being
4354 * done. Otherwise, a buffer left on the flushing list but not getting
4355 * flushed (because nobody's flushing that domain) won't ever return
4356 * unbusy and get reused by libdrm's bo cache. The other expected
4357 * consumer of this interface, OpenGL's occlusion queries, also specs
4358 * that the objects get unbusy "eventually" without any interference.
4359 */
4360 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4361
4362 drm_gem_object_unreference(obj);
4363 mutex_unlock(&dev->struct_mutex);
4364 return 0;
4365}
4366
4367int
4368i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4369 struct drm_file *file_priv)
4370{
4371 return i915_gem_ring_throttle(dev, file_priv);
4372}
4373
3ef94daa
CW		 4374int
4375i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4376 struct drm_file *file_priv)
4377{
4378 struct drm_i915_gem_madvise *args = data;
4379 struct drm_gem_object *obj;
4380 struct drm_i915_gem_object *obj_priv;
4381
4382 switch (args->madv) {
4383 case I915_MADV_DONTNEED:
4384 case I915_MADV_WILLNEED:
4385 break;
4386 default:
4387 return -EINVAL;
4388 }
4389
4390 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4391 if (obj == NULL) {
4392 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4393 args->handle);
4394 return -EBADF;
4395 }
4396
4397 mutex_lock(&dev->struct_mutex);
23010e43 4398 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4399
4400 if (obj_priv->pin_count) {
4401 drm_gem_object_unreference(obj);
4402 mutex_unlock(&dev->struct_mutex);
4403
4404 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4405 return -EINVAL;
4406 }
4407
bb6baf76
CW		 4408 if (obj_priv->madv != __I915_MADV_PURGED)
4409 obj_priv->madv = args->madv;
3ef94daa 4410
2d7ef395
CW		 4411 /* if the object is no longer bound, discard its backing storage */
4412 if (i915_gem_object_is_purgeable(obj_priv) &&
4413 obj_priv->gtt_space == NULL)
4414 i915_gem_object_truncate(obj);
4415
bb6baf76
CW		 4416 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4417
3ef94daa
CW		 4418 drm_gem_object_unreference(obj);
4419 mutex_unlock(&dev->struct_mutex);
4420
4421 return 0;
4422}
4423
ac52bc56
DV		 4424struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4425 size_t size)
4426{
c397b908 4427 struct drm_i915_gem_object *obj;
ac52bc56 4428
c397b908
DV		 4429 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4430 if (obj == NULL)
4431 return NULL;
673a394b 4432
c397b908
DV		 4433 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4434 kfree(obj);
4435 return NULL;
4436 }
673a394b 4437
c397b908
DV		 4438 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4439 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4440
c397b908 4441 obj->agp_type = AGP_USER_MEMORY;
ba1eb1d8 4442
c397b908
DV		 4443 obj->base.driver_private = obj;
4444 obj->obj = &obj->base;
4445 obj->fence_reg = I915_FENCE_REG_NONE;
4446 INIT_LIST_HEAD(&obj->list);
4447 INIT_LIST_HEAD(&obj->gpu_write_list);
4448 INIT_LIST_HEAD(&obj->fence_list);
4449 obj->madv = I915_MADV_WILLNEED;
de151cf6 4450
c397b908
DV		 4451 trace_i915_gem_object_create(&obj->base);
4452
4453 return &obj->base;
4454}
4455
4456int i915_gem_init_object(struct drm_gem_object *obj)
4457{
4458 BUG();
de151cf6 4459
673a394b
EA		 4460 return 0;
4461}
4462
4463void i915_gem_free_object(struct drm_gem_object *obj)
4464{
de151cf6 4465 struct drm_device *dev = obj->dev;
23010e43 4466 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 4467
1c5d22f7
CW		 4468 trace_i915_gem_object_destroy(obj);
4469
673a394b
EA		 4470 while (obj_priv->pin_count > 0)
4471 i915_gem_object_unpin(obj);
4472
71acb5eb
DA		 4473 if (obj_priv->phys_obj)
4474 i915_gem_detach_phys_object(dev, obj);
4475
673a394b
EA		 4476 i915_gem_object_unbind(obj);
4477
7e616158
CW		 4478 if (obj_priv->mmap_offset)
4479 i915_gem_free_mmap_offset(obj);
de151cf6 4480
c397b908
DV		 4481 drm_gem_object_release(obj);
4482
9a298b2a 4483 kfree(obj_priv->page_cpu_valid);
280b713b 4484 kfree(obj_priv->bit_17);
c397b908 4485 kfree(obj_priv);
673a394b
EA		 4486}
4487
ab5ee576 4488/** Unbinds all inactive objects. */
673a394b 4489static int
ab5ee576 4490i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4491{
ab5ee576 4492 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4493
ab5ee576
CW		 4494 while (!list_empty(&dev_priv->mm.inactive_list)) {
4495 struct drm_gem_object *obj;
4496 int ret;
673a394b 4497
ab5ee576
CW		 4498 obj = list_first_entry(&dev_priv->mm.inactive_list,
4499 struct drm_i915_gem_object,
4500 list)->obj;
673a394b
EA		 4501
4502 ret = i915_gem_object_unbind(obj);
4503 if (ret != 0) {
ab5ee576 4504 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4505 return ret;
4506 }
4507 }
4508
673a394b
EA		 4509 return 0;
4510}
4511
29105ccc
CW		 4512int
4513i915_gem_idle(struct drm_device *dev)
4514{
4515 drm_i915_private_t *dev_priv = dev->dev_private;
4516 int ret;
28dfe52a 4517
29105ccc 4518 mutex_lock(&dev->struct_mutex);
1c5d22f7 4519
29105ccc
CW		 4520 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4521 mutex_unlock(&dev->struct_mutex);
4522 return 0;
28dfe52a
EA		 4523 }
4524
29105ccc 4525 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4526 if (ret) {
4527 mutex_unlock(&dev->struct_mutex);
673a394b 4528 return ret;
6dbe2772 4529 }
673a394b 4530
29105ccc
CW		 4531 /* Under UMS, be paranoid and evict. */
4532 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4533 ret = i915_gem_evict_from_inactive_list(dev);
4534 if (ret) {
4535 mutex_unlock(&dev->struct_mutex);
4536 return ret;
4537 }
4538 }
4539
4540 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4541 * We need to replace this with a semaphore, or something.
4542 * And not confound mm.suspended!
4543 */
4544 dev_priv->mm.suspended = 1;
4545 del_timer(&dev_priv->hangcheck_timer);
4546
4547 i915_kernel_lost_context(dev);
6dbe2772 4548 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4549
6dbe2772
KP		 4550 mutex_unlock(&dev->struct_mutex);
4551
29105ccc
CW		 4552 /* Cancel the retire work handler, which should be idle now. */
4553 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4554
673a394b
EA		 4555 return 0;
4556}
4557
4558static int
4559i915_gem_init_hws(struct drm_device *dev)
4560{
4561 drm_i915_private_t *dev_priv = dev->dev_private;
4562 struct drm_gem_object *obj;
4563 struct drm_i915_gem_object *obj_priv;
4564 int ret;
4565
4566 /* If we need a physical address for the status page, it's already
4567 * initialized at driver load time.
4568 */
4569 if (!I915_NEED_GFX_HWS(dev))
4570 return 0;
4571
ac52bc56 4572 obj = i915_gem_alloc_object(dev, 4096);
673a394b
EA		 4573 if (obj == NULL) {
4574 DRM_ERROR("Failed to allocate status page\n");
4575 return -ENOMEM;
4576 }
23010e43 4577 obj_priv = to_intel_bo(obj);
ba1eb1d8 4578 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
673a394b
EA		 4579
4580 ret = i915_gem_object_pin(obj, 4096);
4581 if (ret != 0) {
4582 drm_gem_object_unreference(obj);
4583 return ret;
4584 }
4585
4586 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
673a394b 4587
856fa198 4588 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
ba1eb1d8 4589 if (dev_priv->hw_status_page == NULL) {
673a394b
EA		 4590 DRM_ERROR("Failed to map status page.\n");
4591 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3eb2ee77 4592 i915_gem_object_unpin(obj);
673a394b
EA		 4593 drm_gem_object_unreference(obj);
4594 return -EINVAL;
4595 }
4596 dev_priv->hws_obj = obj;
673a394b 4597 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
f6e450a6
EA		 4598 if (IS_GEN6(dev)) {
4599 I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
4600 I915_READ(HWS_PGA_GEN6); /* posting read */
4601 } else {
4602 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4603 I915_READ(HWS_PGA); /* posting read */
4604 }
44d98a61 4605 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
673a394b
EA		 4606
4607 return 0;
4608}
4609
85a7bb98
CW		 4610static void
4611i915_gem_cleanup_hws(struct drm_device *dev)
4612{
4613 drm_i915_private_t *dev_priv = dev->dev_private;
bab2d1f6
CW		 4614 struct drm_gem_object *obj;
4615 struct drm_i915_gem_object *obj_priv;
85a7bb98
CW		 4616
4617 if (dev_priv->hws_obj == NULL)
4618 return;
4619
bab2d1f6 4620 obj = dev_priv->hws_obj;
23010e43 4621 obj_priv = to_intel_bo(obj);
bab2d1f6 4622
856fa198 4623 kunmap(obj_priv->pages[0]);
85a7bb98
CW		 4624 i915_gem_object_unpin(obj);
4625 drm_gem_object_unreference(obj);
4626 dev_priv->hws_obj = NULL;
bab2d1f6 4627
85a7bb98
CW		 4628 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4629 dev_priv->hw_status_page = NULL;
4630
4631 /* Write high address into HWS_PGA when disabling. */
4632 I915_WRITE(HWS_PGA, 0x1ffff000);
4633}
4634
79e53945 4635int
673a394b
EA		 4636i915_gem_init_ringbuffer(struct drm_device *dev)
4637{
4638 drm_i915_private_t *dev_priv = dev->dev_private;
4639 struct drm_gem_object *obj;
4640 struct drm_i915_gem_object *obj_priv;
79e53945 4641 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
673a394b 4642 int ret;
50aa253d 4643 u32 head;
673a394b
EA		 4644
4645 ret = i915_gem_init_hws(dev);
4646 if (ret != 0)
4647 return ret;
4648
ac52bc56 4649 obj = i915_gem_alloc_object(dev, 128 * 1024);
673a394b
EA		 4650 if (obj == NULL) {
4651 DRM_ERROR("Failed to allocate ringbuffer\n");
85a7bb98 4652 i915_gem_cleanup_hws(dev);
673a394b
EA		 4653 return -ENOMEM;
4654 }
23010e43 4655 obj_priv = to_intel_bo(obj);
673a394b
EA		 4656
4657 ret = i915_gem_object_pin(obj, 4096);
4658 if (ret != 0) {
4659 drm_gem_object_unreference(obj);
85a7bb98 4660 i915_gem_cleanup_hws(dev);
673a394b
EA		 4661 return ret;
4662 }
4663
4664 /* Set up the kernel mapping for the ring. */
79e53945 4665 ring->Size = obj->size;
673a394b 4666
79e53945
JB		 4667 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4668 ring->map.size = obj->size;
4669 ring->map.type = 0;
4670 ring->map.flags = 0;
4671 ring->map.mtrr = 0;
673a394b 4672
79e53945
JB		 4673 drm_core_ioremap_wc(&ring->map, dev);
4674 if (ring->map.handle == NULL) {
673a394b
EA		 4675 DRM_ERROR("Failed to map ringbuffer.\n");
4676 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
47ed185a 4677 i915_gem_object_unpin(obj);
673a394b 4678 drm_gem_object_unreference(obj);
85a7bb98 4679 i915_gem_cleanup_hws(dev);
673a394b
EA		 4680 return -EINVAL;
4681 }
79e53945
JB		 4682 ring->ring_obj = obj;
4683 ring->virtual_start = ring->map.handle;
673a394b
EA		 4684
4685 /* Stop the ring if it's running. */
4686 I915_WRITE(PRB0_CTL, 0);
673a394b 4687 I915_WRITE(PRB0_TAIL, 0);
50aa253d 4688 I915_WRITE(PRB0_HEAD, 0);
673a394b
EA		 4689
4690 /* Initialize the ring. */
4691 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
50aa253d
KP		 4692 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4693
4694 /* G45 ring initialization fails to reset head to zero */
4695 if (head != 0) {
4696 DRM_ERROR("Ring head not reset to zero "
4697 "ctl %08x head %08x tail %08x start %08x\n",
4698 I915_READ(PRB0_CTL),
4699 I915_READ(PRB0_HEAD),
4700 I915_READ(PRB0_TAIL),
4701 I915_READ(PRB0_START));
4702 I915_WRITE(PRB0_HEAD, 0);
4703
4704 DRM_ERROR("Ring head forced to zero "
4705 "ctl %08x head %08x tail %08x start %08x\n",
4706 I915_READ(PRB0_CTL),
4707 I915_READ(PRB0_HEAD),
4708 I915_READ(PRB0_TAIL),
4709 I915_READ(PRB0_START));
4710 }
4711
673a394b
EA		 4712 I915_WRITE(PRB0_CTL,
4713 ((obj->size - 4096) & RING_NR_PAGES) |
4714 RING_NO_REPORT |
4715 RING_VALID);
4716
50aa253d
KP		 4717 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4718
4719 /* If the head is still not zero, the ring is dead */
4720 if (head != 0) {
4721 DRM_ERROR("Ring initialization failed "
4722 "ctl %08x head %08x tail %08x start %08x\n",
4723 I915_READ(PRB0_CTL),
4724 I915_READ(PRB0_HEAD),
4725 I915_READ(PRB0_TAIL),
4726 I915_READ(PRB0_START));
4727 return -EIO;
4728 }
4729
673a394b 4730 /* Update our cache of the ring state */
79e53945
JB		 4731 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4732 i915_kernel_lost_context(dev);
4733 else {
4734 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4735 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4736 ring->space = ring->head - (ring->tail + 8);
4737 if (ring->space < 0)
4738 ring->space += ring->Size;
4739 }
673a394b 4740
71cf39b1
EA		 4741 if (IS_I9XX(dev) && !IS_GEN3(dev)) {
4742 I915_WRITE(MI_MODE,
4743 (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
4744 }
4745
673a394b
EA		 4746 return 0;
4747}
4748
79e53945 4749void
673a394b
EA		 4750i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4751{
4752 drm_i915_private_t *dev_priv = dev->dev_private;
4753
4754 if (dev_priv->ring.ring_obj == NULL)
4755 return;
4756
4757 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4758
4759 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4760 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4761 dev_priv->ring.ring_obj = NULL;
4762 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4763
85a7bb98 4764 i915_gem_cleanup_hws(dev);
673a394b
EA		 4765}
4766
4767int
4768i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4769 struct drm_file *file_priv)
4770{
4771 drm_i915_private_t *dev_priv = dev->dev_private;
4772 int ret;
4773
79e53945
JB		 4774 if (drm_core_check_feature(dev, DRIVER_MODESET))
4775 return 0;
4776
ba1234d1 4777 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4778 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4779 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4780 }
4781
673a394b 4782 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4783 dev_priv->mm.suspended = 0;
4784
4785 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4786 if (ret != 0) {
4787 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4788 return ret;
d816f6ac 4789 }
9bb2d6f9 4790
5e118f41 4791 spin_lock(&dev_priv->mm.active_list_lock);
673a394b 4792 BUG_ON(!list_empty(&dev_priv->mm.active_list));
5e118f41
CW		 4793 spin_unlock(&dev_priv->mm.active_list_lock);
4794
673a394b
EA		 4795 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4796 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4797 BUG_ON(!list_empty(&dev_priv->mm.request_list));
673a394b 4798 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4799
4800 drm_irq_install(dev);
4801
673a394b
EA		 4802 return 0;
4803}
4804
4805int
4806i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4807 struct drm_file *file_priv)
4808{
79e53945
JB		 4809 if (drm_core_check_feature(dev, DRIVER_MODESET))
4810 return 0;
4811
dbb19d30 4812 drm_irq_uninstall(dev);
e6890f6f 4813 return i915_gem_idle(dev);
673a394b
EA		 4814}
4815
4816void
4817i915_gem_lastclose(struct drm_device *dev)
4818{
4819 int ret;
673a394b 4820
e806b495
EA		 4821 if (drm_core_check_feature(dev, DRIVER_MODESET))
4822 return;
4823
6dbe2772
KP		 4824 ret = i915_gem_idle(dev);
4825 if (ret)
4826 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4827}
4828
4829void
4830i915_gem_load(struct drm_device *dev)
4831{
b5aa8a0f 4832 int i;
673a394b
EA		 4833 drm_i915_private_t *dev_priv = dev->dev_private;
4834
5e118f41 4835 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b
EA		 4836 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4837 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4838 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b
EA		 4839 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4840 INIT_LIST_HEAD(&dev_priv->mm.request_list);
a09ba7fa 4841 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
673a394b
EA		 4842 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4843 i915_gem_retire_work_handler);
4844 dev_priv->mm.next_gem_seqno = 1;
4845
31169714
CW		 4846 spin_lock(&shrink_list_lock);
4847 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4848 spin_unlock(&shrink_list_lock);
4849
de151cf6 4850 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4851 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4852 dev_priv->fence_reg_start = 3;
de151cf6 4853
0f973f27 4854 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4855 dev_priv->num_fence_regs = 16;
4856 else
4857 dev_priv->num_fence_regs = 8;
4858
b5aa8a0f
GH		 4859 /* Initialize fence registers to zero */
4860 if (IS_I965G(dev)) {
4861 for (i = 0; i < 16; i++)
4862 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4863 } else {
4864 for (i = 0; i < 8; i++)
4865 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4866 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4867 for (i = 0; i < 8; i++)
4868 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4869 }
673a394b 4870 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4871 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4872}
71acb5eb
DA		 4873
4874/*
4875 * Create a physically contiguous memory object for this object
4876 * e.g. for cursor + overlay regs
4877 */
4878int i915_gem_init_phys_object(struct drm_device *dev,
4879 int id, int size)
4880{
4881 drm_i915_private_t *dev_priv = dev->dev_private;
4882 struct drm_i915_gem_phys_object *phys_obj;
4883 int ret;
4884
4885 if (dev_priv->mm.phys_objs[id - 1] || !size)
4886 return 0;
4887
9a298b2a 4888 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4889 if (!phys_obj)
4890 return -ENOMEM;
4891
4892 phys_obj->id = id;
4893
e6be8d9d 4894 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4895 if (!phys_obj->handle) {
4896 ret = -ENOMEM;
4897 goto kfree_obj;
4898 }
4899#ifdef CONFIG_X86
4900 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4901#endif
4902
4903 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4904
4905 return 0;
4906kfree_obj:
9a298b2a 4907 kfree(phys_obj);
71acb5eb
DA		 4908 return ret;
4909}
4910
4911void i915_gem_free_phys_object(struct drm_device *dev, int id)
4912{
4913 drm_i915_private_t *dev_priv = dev->dev_private;
4914 struct drm_i915_gem_phys_object *phys_obj;
4915
4916 if (!dev_priv->mm.phys_objs[id - 1])
4917 return;
4918
4919 phys_obj = dev_priv->mm.phys_objs[id - 1];
4920 if (phys_obj->cur_obj) {
4921 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4922 }
4923
4924#ifdef CONFIG_X86
4925 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4926#endif
4927 drm_pci_free(dev, phys_obj->handle);
4928 kfree(phys_obj);
4929 dev_priv->mm.phys_objs[id - 1] = NULL;
4930}
4931
4932void i915_gem_free_all_phys_object(struct drm_device *dev)
4933{
4934 int i;
4935
260883c8 4936 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4937 i915_gem_free_phys_object(dev, i);
4938}
4939
4940void i915_gem_detach_phys_object(struct drm_device *dev,
4941 struct drm_gem_object *obj)
4942{
4943 struct drm_i915_gem_object *obj_priv;
4944 int i;
4945 int ret;
4946 int page_count;
4947
23010e43 4948 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4949 if (!obj_priv->phys_obj)
4950 return;
4951
4bdadb97 4952 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4953 if (ret)
4954 goto out;
4955
4956 page_count = obj->size / PAGE_SIZE;
4957
4958 for (i = 0; i < page_count; i++) {
856fa198 4959 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4960 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4961
4962 memcpy(dst, src, PAGE_SIZE);
4963 kunmap_atomic(dst, KM_USER0);
4964 }
856fa198 4965 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4966 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4967
4968 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4969out:
4970 obj_priv->phys_obj->cur_obj = NULL;
4971 obj_priv->phys_obj = NULL;
4972}
4973
4974int
4975i915_gem_attach_phys_object(struct drm_device *dev,
4976 struct drm_gem_object *obj, int id)
4977{
4978 drm_i915_private_t *dev_priv = dev->dev_private;
4979 struct drm_i915_gem_object *obj_priv;
4980 int ret = 0;
4981 int page_count;
4982 int i;
4983
4984 if (id > I915_MAX_PHYS_OBJECT)
4985 return -EINVAL;
4986
23010e43 4987 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4988
4989 if (obj_priv->phys_obj) {
4990 if (obj_priv->phys_obj->id == id)
4991 return 0;
4992 i915_gem_detach_phys_object(dev, obj);
4993 }
4994
4995
4996 /* create a new object */
4997 if (!dev_priv->mm.phys_objs[id - 1]) {
4998 ret = i915_gem_init_phys_object(dev, id,
4999 obj->size);
5000 if (ret) {
aeb565df 5001 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 5002 goto out;
5003 }
5004 }
5005
5006 /* bind to the object */
5007 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
5008 obj_priv->phys_obj->cur_obj = obj;
5009
4bdadb97 5010 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 5011 if (ret) {
5012 DRM_ERROR("failed to get page list\n");
5013 goto out;
5014 }
5015
5016 page_count = obj->size / PAGE_SIZE;
5017
5018 for (i = 0; i < page_count; i++) {
856fa198 5019 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 5020 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5021
5022 memcpy(dst, src, PAGE_SIZE);
5023 kunmap_atomic(src, KM_USER0);
5024 }
5025
d78b47b9
CW		 5026 i915_gem_object_put_pages(obj);
5027
71acb5eb
DA		 5028 return 0;
5029out:
5030 return ret;
5031}
5032
5033static int
5034i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5035 struct drm_i915_gem_pwrite *args,
5036 struct drm_file *file_priv)
5037{
23010e43 5038 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 5039 void *obj_addr;
5040 int ret;
5041 char __user *user_data;
5042
5043 user_data = (char __user *) (uintptr_t) args->data_ptr;
5044 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5045
44d98a61 5046 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 5047 ret = copy_from_user(obj_addr, user_data, args->size);
5048 if (ret)
5049 return -EFAULT;
5050
5051 drm_agp_chipset_flush(dev);
5052 return 0;
5053}
b962442e
EA		 5054
5055void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5056{
5057 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5058
5059 /* Clean up our request list when the client is going away, so that
5060 * later retire_requests won't dereference our soon-to-be-gone
5061 * file_priv.
5062 */
5063 mutex_lock(&dev->struct_mutex);
5064 while (!list_empty(&i915_file_priv->mm.request_list))
5065 list_del_init(i915_file_priv->mm.request_list.next);
5066 mutex_unlock(&dev->struct_mutex);
5067}
31169714 5068
31169714
CW		 5069static int
5070i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5071{
5072 drm_i915_private_t *dev_priv, *next_dev;
5073 struct drm_i915_gem_object *obj_priv, *next_obj;
5074 int cnt = 0;
5075 int would_deadlock = 1;
5076
5077 /* "fast-path" to count number of available objects */
5078 if (nr_to_scan == 0) {
5079 spin_lock(&shrink_list_lock);
5080 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5081 struct drm_device *dev = dev_priv->dev;
5082
5083 if (mutex_trylock(&dev->struct_mutex)) {
5084 list_for_each_entry(obj_priv,
5085 &dev_priv->mm.inactive_list,
5086 list)
5087 cnt++;
5088 mutex_unlock(&dev->struct_mutex);
5089 }
5090 }
5091 spin_unlock(&shrink_list_lock);
5092
5093 return (cnt / 100) * sysctl_vfs_cache_pressure;
5094 }
5095
5096 spin_lock(&shrink_list_lock);
5097
5098 /* first scan for clean buffers */
5099 list_for_each_entry_safe(dev_priv, next_dev,
5100 &shrink_list, mm.shrink_list) {
5101 struct drm_device *dev = dev_priv->dev;
5102
5103 if (! mutex_trylock(&dev->struct_mutex))
5104 continue;
5105
5106 spin_unlock(&shrink_list_lock);
5107
5108 i915_gem_retire_requests(dev);
5109
5110 list_for_each_entry_safe(obj_priv, next_obj,
5111 &dev_priv->mm.inactive_list,
5112 list) {
5113 if (i915_gem_object_is_purgeable(obj_priv)) {
963b4836 5114 i915_gem_object_unbind(obj_priv->obj);
31169714
CW		 5115 if (--nr_to_scan <= 0)
5116 break;
5117 }
5118 }
5119
5120 spin_lock(&shrink_list_lock);
5121 mutex_unlock(&dev->struct_mutex);
5122
963b4836
CW		 5123 would_deadlock = 0;
5124
31169714
CW		 5125 if (nr_to_scan <= 0)
5126 break;
5127 }
5128
5129 /* second pass, evict/count anything still on the inactive list */
5130 list_for_each_entry_safe(dev_priv, next_dev,
5131 &shrink_list, mm.shrink_list) {
5132 struct drm_device *dev = dev_priv->dev;
5133
5134 if (! mutex_trylock(&dev->struct_mutex))
5135 continue;
5136
5137 spin_unlock(&shrink_list_lock);
5138
5139 list_for_each_entry_safe(obj_priv, next_obj,
5140 &dev_priv->mm.inactive_list,
5141 list) {
5142 if (nr_to_scan > 0) {
963b4836 5143 i915_gem_object_unbind(obj_priv->obj);
31169714
CW		 5144 nr_to_scan--;
5145 } else
5146 cnt++;
5147 }
5148
5149 spin_lock(&shrink_list_lock);
5150 mutex_unlock(&dev->struct_mutex);
5151
5152 would_deadlock = 0;
5153 }
5154
5155 spin_unlock(&shrink_list_lock);
5156
5157 if (would_deadlock)
5158 return -1;
5159 else if (cnt > 0)
5160 return (cnt / 100) * sysctl_vfs_cache_pressure;
5161 else
5162 return 0;
5163}
5164
5165static struct shrinker shrinker = {
5166 .shrink = i915_gem_shrink,
5167 .seeks = DEFAULT_SEEKS,
5168};
5169
5170__init void
5171i915_gem_shrinker_init(void)
5172{
5173 register_shrinker(&shrinker);
5174}
5175
5176__exit void
5177i915_gem_shrinker_exit(void)
5178{
5179 unregister_shrinker(&shrinker);
5180}
Clone of davem's net-next-2.6 tree