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drm/i915: Refactor i915_gem_retire_requests()
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
673a394b 37
2dafb1e0 38static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 int write);
43static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
44 uint64_t offset,
45 uint64_t size);
46static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 47static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment);
de151cf6 50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 51static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 52static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
673a394b 56
31169714
CW		 57static LIST_HEAD(shrink_list);
58static DEFINE_SPINLOCK(shrink_list_lock);
59
79e53945
JB		 60int i915_gem_do_init(struct drm_device *dev, unsigned long start,
61 unsigned long end)
673a394b
EA		 62{
63 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 64
79e53945
JB		 65 if (start >= end ||
66 (start & (PAGE_SIZE - 1)) != 0 ||
67 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 68 return -EINVAL;
69 }
70
79e53945
JB		 71 drm_mm_init(&dev_priv->mm.gtt_space, start,
72 end - start);
673a394b 73
79e53945
JB		 74 dev->gtt_total = (uint32_t) (end - start);
75
76 return 0;
77}
673a394b 78
79e53945
JB		 79int
80i915_gem_init_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *file_priv)
82{
83 struct drm_i915_gem_init *args = data;
84 int ret;
85
86 mutex_lock(&dev->struct_mutex);
87 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 88 mutex_unlock(&dev->struct_mutex);
89
79e53945 90 return ret;
673a394b
EA		 91}
92
5a125c3c
EA		 93int
94i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
95 struct drm_file *file_priv)
96{
5a125c3c 97 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 98
99 if (!(dev->driver->driver_features & DRIVER_GEM))
100 return -ENODEV;
101
102 args->aper_size = dev->gtt_total;
2678d9d6
KP		 103 args->aper_available_size = (args->aper_size -
104 atomic_read(&dev->pin_memory));
5a125c3c
EA		 105
106 return 0;
107}
108
673a394b
EA		 109
110/**
111 * Creates a new mm object and returns a handle to it.
112 */
113int
114i915_gem_create_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
116{
117 struct drm_i915_gem_create *args = data;
118 struct drm_gem_object *obj;
a1a2d1d3
PP		 119 int ret;
120 u32 handle;
673a394b
EA		 121
122 args->size = roundup(args->size, PAGE_SIZE);
123
124 /* Allocate the new object */
ac52bc56 125 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 126 if (obj == NULL)
127 return -ENOMEM;
128
129 ret = drm_gem_handle_create(file_priv, obj, &handle);
bc9025bd 130 drm_gem_object_handle_unreference_unlocked(obj);
673a394b
EA		 131
132 if (ret)
133 return ret;
134
135 args->handle = handle;
136
137 return 0;
138}
139
eb01459f
EA		 140static inline int
141fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
143 char __user *data,
144 int length)
145{
146 char __iomem *vaddr;
2bc43b5c 147 int unwritten;
eb01459f
EA		 148
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 if (vaddr == NULL)
151 return -ENOMEM;
2bc43b5c 152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 153 kunmap_atomic(vaddr, KM_USER0);
154
2bc43b5c
FM		 155 if (unwritten)
156 return -EFAULT;
157
158 return 0;
eb01459f
EA		 159}
160
280b713b
EA		 161static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
162{
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 165
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
168}
169
99a03df5 170static inline void
40123c1f
EA		 171slow_shmem_copy(struct page *dst_page,
172 int dst_offset,
173 struct page *src_page,
174 int src_offset,
175 int length)
176{
177 char *dst_vaddr, *src_vaddr;
178
99a03df5
CW		 179 dst_vaddr = kmap(dst_page);
180 src_vaddr = kmap(src_page);
40123c1f
EA		 181
182 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
183
99a03df5
CW		 184 kunmap(src_page);
185 kunmap(dst_page);
40123c1f
EA		 186}
187
99a03df5 188static inline void
280b713b
EA		 189slow_shmem_bit17_copy(struct page *gpu_page,
190 int gpu_offset,
191 struct page *cpu_page,
192 int cpu_offset,
193 int length,
194 int is_read)
195{
196 char *gpu_vaddr, *cpu_vaddr;
197
198 /* Use the unswizzled path if this page isn't affected. */
199 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
200 if (is_read)
201 return slow_shmem_copy(cpu_page, cpu_offset,
202 gpu_page, gpu_offset, length);
203 else
204 return slow_shmem_copy(gpu_page, gpu_offset,
205 cpu_page, cpu_offset, length);
206 }
207
99a03df5
CW		 208 gpu_vaddr = kmap(gpu_page);
209 cpu_vaddr = kmap(cpu_page);
280b713b
EA		 210
211 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
212 * XORing with the other bits (A9 for Y, A9 and A10 for X)
213 */
214 while (length > 0) {
215 int cacheline_end = ALIGN(gpu_offset + 1, 64);
216 int this_length = min(cacheline_end - gpu_offset, length);
217 int swizzled_gpu_offset = gpu_offset ^ 64;
218
219 if (is_read) {
220 memcpy(cpu_vaddr + cpu_offset,
221 gpu_vaddr + swizzled_gpu_offset,
222 this_length);
223 } else {
224 memcpy(gpu_vaddr + swizzled_gpu_offset,
225 cpu_vaddr + cpu_offset,
226 this_length);
227 }
228 cpu_offset += this_length;
229 gpu_offset += this_length;
230 length -= this_length;
231 }
232
99a03df5
CW		 233 kunmap(cpu_page);
234 kunmap(gpu_page);
280b713b
EA		 235}
236
eb01459f
EA		 237/**
238 * This is the fast shmem pread path, which attempts to copy_from_user directly
239 * from the backing pages of the object to the user's address space. On a
240 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
241 */
242static int
243i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
244 struct drm_i915_gem_pread *args,
245 struct drm_file *file_priv)
246{
23010e43 247 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 248 ssize_t remain;
249 loff_t offset, page_base;
250 char __user *user_data;
251 int page_offset, page_length;
252 int ret;
253
254 user_data = (char __user *) (uintptr_t) args->data_ptr;
255 remain = args->size;
256
257 mutex_lock(&dev->struct_mutex);
258
4bdadb97 259 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 260 if (ret != 0)
261 goto fail_unlock;
262
263 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
264 args->size);
265 if (ret != 0)
266 goto fail_put_pages;
267
23010e43 268 obj_priv = to_intel_bo(obj);
eb01459f
EA		 269 offset = args->offset;
270
271 while (remain > 0) {
272 /* Operation in this page
273 *
274 * page_base = page offset within aperture
275 * page_offset = offset within page
276 * page_length = bytes to copy for this page
277 */
278 page_base = (offset & ~(PAGE_SIZE-1));
279 page_offset = offset & (PAGE_SIZE-1);
280 page_length = remain;
281 if ((page_offset + remain) > PAGE_SIZE)
282 page_length = PAGE_SIZE - page_offset;
283
284 ret = fast_shmem_read(obj_priv->pages,
285 page_base, page_offset,
286 user_data, page_length);
287 if (ret)
288 goto fail_put_pages;
289
290 remain -= page_length;
291 user_data += page_length;
292 offset += page_length;
293 }
294
295fail_put_pages:
296 i915_gem_object_put_pages(obj);
297fail_unlock:
298 mutex_unlock(&dev->struct_mutex);
299
300 return ret;
301}
302
07f73f69
CW		 303static int
304i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
305{
306 int ret;
307
4bdadb97 308 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 309
310 /* If we've insufficient memory to map in the pages, attempt
311 * to make some space by throwing out some old buffers.
312 */
313 if (ret == -ENOMEM) {
314 struct drm_device *dev = obj->dev;
07f73f69
CW		 315
316 ret = i915_gem_evict_something(dev, obj->size);
317 if (ret)
318 return ret;
319
4bdadb97 320 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 321 }
322
323 return ret;
324}
325
eb01459f
EA		 326/**
327 * This is the fallback shmem pread path, which allocates temporary storage
328 * in kernel space to copy_to_user into outside of the struct_mutex, so we
329 * can copy out of the object's backing pages while holding the struct mutex
330 * and not take page faults.
331 */
332static int
333i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
334 struct drm_i915_gem_pread *args,
335 struct drm_file *file_priv)
336{
23010e43 337 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 338 struct mm_struct *mm = current->mm;
339 struct page **user_pages;
340 ssize_t remain;
341 loff_t offset, pinned_pages, i;
342 loff_t first_data_page, last_data_page, num_pages;
343 int shmem_page_index, shmem_page_offset;
344 int data_page_index, data_page_offset;
345 int page_length;
346 int ret;
347 uint64_t data_ptr = args->data_ptr;
280b713b 348 int do_bit17_swizzling;
eb01459f
EA		 349
350 remain = args->size;
351
352 /* Pin the user pages containing the data. We can't fault while
353 * holding the struct mutex, yet we want to hold it while
354 * dereferencing the user data.
355 */
356 first_data_page = data_ptr / PAGE_SIZE;
357 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
358 num_pages = last_data_page - first_data_page + 1;
359
8e7d2b2c 360 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 361 if (user_pages == NULL)
362 return -ENOMEM;
363
364 down_read(&mm->mmap_sem);
365 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 366 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 367 up_read(&mm->mmap_sem);
368 if (pinned_pages < num_pages) {
369 ret = -EFAULT;
370 goto fail_put_user_pages;
371 }
372
280b713b
EA		 373 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
374
eb01459f
EA		 375 mutex_lock(&dev->struct_mutex);
376
07f73f69
CW		 377 ret = i915_gem_object_get_pages_or_evict(obj);
378 if (ret)
eb01459f
EA		 379 goto fail_unlock;
380
381 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
382 args->size);
383 if (ret != 0)
384 goto fail_put_pages;
385
23010e43 386 obj_priv = to_intel_bo(obj);
eb01459f
EA		 387 offset = args->offset;
388
389 while (remain > 0) {
390 /* Operation in this page
391 *
392 * shmem_page_index = page number within shmem file
393 * shmem_page_offset = offset within page in shmem file
394 * data_page_index = page number in get_user_pages return
395 * data_page_offset = offset with data_page_index page.
396 * page_length = bytes to copy for this page
397 */
398 shmem_page_index = offset / PAGE_SIZE;
399 shmem_page_offset = offset & ~PAGE_MASK;
400 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
401 data_page_offset = data_ptr & ~PAGE_MASK;
402
403 page_length = remain;
404 if ((shmem_page_offset + page_length) > PAGE_SIZE)
405 page_length = PAGE_SIZE - shmem_page_offset;
406 if ((data_page_offset + page_length) > PAGE_SIZE)
407 page_length = PAGE_SIZE - data_page_offset;
408
280b713b 409 if (do_bit17_swizzling) {
99a03df5 410 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b 411 shmem_page_offset,
99a03df5
CW		 412 user_pages[data_page_index],
413 data_page_offset,
414 page_length,
415 1);
416 } else {
417 slow_shmem_copy(user_pages[data_page_index],
418 data_page_offset,
419 obj_priv->pages[shmem_page_index],
420 shmem_page_offset,
421 page_length);
280b713b 422 }
eb01459f
EA		 423
424 remain -= page_length;
425 data_ptr += page_length;
426 offset += page_length;
427 }
428
429fail_put_pages:
430 i915_gem_object_put_pages(obj);
431fail_unlock:
432 mutex_unlock(&dev->struct_mutex);
433fail_put_user_pages:
434 for (i = 0; i < pinned_pages; i++) {
435 SetPageDirty(user_pages[i]);
436 page_cache_release(user_pages[i]);
437 }
8e7d2b2c 438 drm_free_large(user_pages);
eb01459f
EA		 439
440 return ret;
441}
442
673a394b
EA		 443/**
444 * Reads data from the object referenced by handle.
445 *
446 * On error, the contents of *data are undefined.
447 */
448int
449i915_gem_pread_ioctl(struct drm_device *dev, void *data,
450 struct drm_file *file_priv)
451{
452 struct drm_i915_gem_pread *args = data;
453 struct drm_gem_object *obj;
454 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 455 int ret;
456
457 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
458 if (obj == NULL)
459 return -EBADF;
23010e43 460 obj_priv = to_intel_bo(obj);
673a394b
EA		 461
462 /* Bounds check source.
463 *
464 * XXX: This could use review for overflow issues...
465 */
466 if (args->offset > obj->size || args->size > obj->size ||
467 args->offset + args->size > obj->size) {
bc9025bd 468 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 469 return -EINVAL;
470 }
471
280b713b 472 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 473 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 474 } else {
475 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
476 if (ret != 0)
477 ret = i915_gem_shmem_pread_slow(dev, obj, args,
478 file_priv);
479 }
673a394b 480
bc9025bd 481 drm_gem_object_unreference_unlocked(obj);
673a394b 482
eb01459f 483 return ret;
673a394b
EA		 484}
485
0839ccb8
KP		 486/* This is the fast write path which cannot handle
487 * page faults in the source data
9b7530cc 488 */
0839ccb8
KP		 489
490static inline int
491fast_user_write(struct io_mapping *mapping,
492 loff_t page_base, int page_offset,
493 char __user *user_data,
494 int length)
9b7530cc 495{
9b7530cc 496 char *vaddr_atomic;
0839ccb8 497 unsigned long unwritten;
9b7530cc 498
0839ccb8
KP		 499 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
500 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
501 user_data, length);
502 io_mapping_unmap_atomic(vaddr_atomic);
503 if (unwritten)
504 return -EFAULT;
505 return 0;
506}
507
508/* Here's the write path which can sleep for
509 * page faults
510 */
511
ab34c226 512static inline void
3de09aa3
EA		 513slow_kernel_write(struct io_mapping *mapping,
514 loff_t gtt_base, int gtt_offset,
515 struct page *user_page, int user_offset,
516 int length)
0839ccb8 517{
ab34c226
CW		 518 char __iomem *dst_vaddr;
519 char *src_vaddr;
0839ccb8 520
ab34c226
CW		 521 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
522 src_vaddr = kmap(user_page);
523
524 memcpy_toio(dst_vaddr + gtt_offset,
525 src_vaddr + user_offset,
526 length);
527
528 kunmap(user_page);
529 io_mapping_unmap(dst_vaddr);
9b7530cc
LT		 530}
531
40123c1f
EA		 532static inline int
533fast_shmem_write(struct page **pages,
534 loff_t page_base, int page_offset,
535 char __user *data,
536 int length)
537{
538 char __iomem *vaddr;
d0088775 539 unsigned long unwritten;
40123c1f
EA		 540
541 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
542 if (vaddr == NULL)
543 return -ENOMEM;
d0088775 544 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 545 kunmap_atomic(vaddr, KM_USER0);
546
d0088775
DA		 547 if (unwritten)
548 return -EFAULT;
40123c1f
EA		 549 return 0;
550}
551
3de09aa3
EA		 552/**
553 * This is the fast pwrite path, where we copy the data directly from the
554 * user into the GTT, uncached.
555 */
673a394b 556static int
3de09aa3
EA		 557i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
558 struct drm_i915_gem_pwrite *args,
559 struct drm_file *file_priv)
673a394b 560{
23010e43 561 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 562 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 563 ssize_t remain;
0839ccb8 564 loff_t offset, page_base;
673a394b 565 char __user *user_data;
0839ccb8
KP		 566 int page_offset, page_length;
567 int ret;
673a394b
EA		 568
569 user_data = (char __user *) (uintptr_t) args->data_ptr;
570 remain = args->size;
571 if (!access_ok(VERIFY_READ, user_data, remain))
572 return -EFAULT;
573
574
575 mutex_lock(&dev->struct_mutex);
576 ret = i915_gem_object_pin(obj, 0);
577 if (ret) {
578 mutex_unlock(&dev->struct_mutex);
579 return ret;
580 }
2ef7eeaa 581 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 582 if (ret)
583 goto fail;
584
23010e43 585 obj_priv = to_intel_bo(obj);
673a394b 586 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 587
588 while (remain > 0) {
589 /* Operation in this page
590 *
0839ccb8
KP		 591 * page_base = page offset within aperture
592 * page_offset = offset within page
593 * page_length = bytes to copy for this page
673a394b 594 */
0839ccb8
KP		 595 page_base = (offset & ~(PAGE_SIZE-1));
596 page_offset = offset & (PAGE_SIZE-1);
597 page_length = remain;
598 if ((page_offset + remain) > PAGE_SIZE)
599 page_length = PAGE_SIZE - page_offset;
600
601 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
602 page_offset, user_data, page_length);
603
604 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 605 * source page isn't available. Return the error and we'll
606 * retry in the slow path.
0839ccb8 607 */
3de09aa3
EA		 608 if (ret)
609 goto fail;
673a394b 610
0839ccb8
KP		 611 remain -= page_length;
612 user_data += page_length;
613 offset += page_length;
673a394b 614 }
673a394b
EA		 615
616fail:
617 i915_gem_object_unpin(obj);
618 mutex_unlock(&dev->struct_mutex);
619
620 return ret;
621}
622
3de09aa3
EA		 623/**
624 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
625 * the memory and maps it using kmap_atomic for copying.
626 *
627 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
628 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
629 */
3043c60c 630static int
3de09aa3
EA		 631i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
632 struct drm_i915_gem_pwrite *args,
633 struct drm_file *file_priv)
673a394b 634{
23010e43 635 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 636 drm_i915_private_t *dev_priv = dev->dev_private;
637 ssize_t remain;
638 loff_t gtt_page_base, offset;
639 loff_t first_data_page, last_data_page, num_pages;
640 loff_t pinned_pages, i;
641 struct page **user_pages;
642 struct mm_struct *mm = current->mm;
643 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 644 int ret;
3de09aa3
EA		 645 uint64_t data_ptr = args->data_ptr;
646
647 remain = args->size;
648
649 /* Pin the user pages containing the data. We can't fault while
650 * holding the struct mutex, and all of the pwrite implementations
651 * want to hold it while dereferencing the user data.
652 */
653 first_data_page = data_ptr / PAGE_SIZE;
654 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
655 num_pages = last_data_page - first_data_page + 1;
656
8e7d2b2c 657 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 658 if (user_pages == NULL)
659 return -ENOMEM;
660
661 down_read(&mm->mmap_sem);
662 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
663 num_pages, 0, 0, user_pages, NULL);
664 up_read(&mm->mmap_sem);
665 if (pinned_pages < num_pages) {
666 ret = -EFAULT;
667 goto out_unpin_pages;
668 }
673a394b
EA		 669
670 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 671 ret = i915_gem_object_pin(obj, 0);
672 if (ret)
673 goto out_unlock;
674
675 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
676 if (ret)
677 goto out_unpin_object;
678
23010e43 679 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 680 offset = obj_priv->gtt_offset + args->offset;
681
682 while (remain > 0) {
683 /* Operation in this page
684 *
685 * gtt_page_base = page offset within aperture
686 * gtt_page_offset = offset within page in aperture
687 * data_page_index = page number in get_user_pages return
688 * data_page_offset = offset with data_page_index page.
689 * page_length = bytes to copy for this page
690 */
691 gtt_page_base = offset & PAGE_MASK;
692 gtt_page_offset = offset & ~PAGE_MASK;
693 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
694 data_page_offset = data_ptr & ~PAGE_MASK;
695
696 page_length = remain;
697 if ((gtt_page_offset + page_length) > PAGE_SIZE)
698 page_length = PAGE_SIZE - gtt_page_offset;
699 if ((data_page_offset + page_length) > PAGE_SIZE)
700 page_length = PAGE_SIZE - data_page_offset;
701
ab34c226
CW		 702 slow_kernel_write(dev_priv->mm.gtt_mapping,
703 gtt_page_base, gtt_page_offset,
704 user_pages[data_page_index],
705 data_page_offset,
706 page_length);
3de09aa3
EA		 707
708 remain -= page_length;
709 offset += page_length;
710 data_ptr += page_length;
711 }
712
713out_unpin_object:
714 i915_gem_object_unpin(obj);
715out_unlock:
716 mutex_unlock(&dev->struct_mutex);
717out_unpin_pages:
718 for (i = 0; i < pinned_pages; i++)
719 page_cache_release(user_pages[i]);
8e7d2b2c 720 drm_free_large(user_pages);
3de09aa3
EA		 721
722 return ret;
723}
724
40123c1f
EA		 725/**
726 * This is the fast shmem pwrite path, which attempts to directly
727 * copy_from_user into the kmapped pages backing the object.
728 */
3043c60c 729static int
40123c1f
EA		 730i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
731 struct drm_i915_gem_pwrite *args,
732 struct drm_file *file_priv)
673a394b 733{
23010e43 734 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 735 ssize_t remain;
736 loff_t offset, page_base;
737 char __user *user_data;
738 int page_offset, page_length;
673a394b 739 int ret;
40123c1f
EA		 740
741 user_data = (char __user *) (uintptr_t) args->data_ptr;
742 remain = args->size;
673a394b
EA		 743
744 mutex_lock(&dev->struct_mutex);
745
4bdadb97 746 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 747 if (ret != 0)
748 goto fail_unlock;
673a394b 749
e47c68e9 750 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 751 if (ret != 0)
752 goto fail_put_pages;
753
23010e43 754 obj_priv = to_intel_bo(obj);
40123c1f
EA		 755 offset = args->offset;
756 obj_priv->dirty = 1;
757
758 while (remain > 0) {
759 /* Operation in this page
760 *
761 * page_base = page offset within aperture
762 * page_offset = offset within page
763 * page_length = bytes to copy for this page
764 */
765 page_base = (offset & ~(PAGE_SIZE-1));
766 page_offset = offset & (PAGE_SIZE-1);
767 page_length = remain;
768 if ((page_offset + remain) > PAGE_SIZE)
769 page_length = PAGE_SIZE - page_offset;
770
771 ret = fast_shmem_write(obj_priv->pages,
772 page_base, page_offset,
773 user_data, page_length);
774 if (ret)
775 goto fail_put_pages;
776
777 remain -= page_length;
778 user_data += page_length;
779 offset += page_length;
780 }
781
782fail_put_pages:
783 i915_gem_object_put_pages(obj);
784fail_unlock:
785 mutex_unlock(&dev->struct_mutex);
786
787 return ret;
788}
789
790/**
791 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
792 * the memory and maps it using kmap_atomic for copying.
793 *
794 * This avoids taking mmap_sem for faulting on the user's address while the
795 * struct_mutex is held.
796 */
797static int
798i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
799 struct drm_i915_gem_pwrite *args,
800 struct drm_file *file_priv)
801{
23010e43 802 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 803 struct mm_struct *mm = current->mm;
804 struct page **user_pages;
805 ssize_t remain;
806 loff_t offset, pinned_pages, i;
807 loff_t first_data_page, last_data_page, num_pages;
808 int shmem_page_index, shmem_page_offset;
809 int data_page_index, data_page_offset;
810 int page_length;
811 int ret;
812 uint64_t data_ptr = args->data_ptr;
280b713b 813 int do_bit17_swizzling;
40123c1f
EA		 814
815 remain = args->size;
816
817 /* Pin the user pages containing the data. We can't fault while
818 * holding the struct mutex, and all of the pwrite implementations
819 * want to hold it while dereferencing the user data.
820 */
821 first_data_page = data_ptr / PAGE_SIZE;
822 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
823 num_pages = last_data_page - first_data_page + 1;
824
8e7d2b2c 825 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 826 if (user_pages == NULL)
827 return -ENOMEM;
828
829 down_read(&mm->mmap_sem);
830 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
831 num_pages, 0, 0, user_pages, NULL);
832 up_read(&mm->mmap_sem);
833 if (pinned_pages < num_pages) {
834 ret = -EFAULT;
835 goto fail_put_user_pages;
673a394b
EA		 836 }
837
280b713b
EA		 838 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
839
40123c1f
EA		 840 mutex_lock(&dev->struct_mutex);
841
07f73f69
CW		 842 ret = i915_gem_object_get_pages_or_evict(obj);
843 if (ret)
40123c1f
EA		 844 goto fail_unlock;
845
846 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
847 if (ret != 0)
848 goto fail_put_pages;
849
23010e43 850 obj_priv = to_intel_bo(obj);
673a394b 851 offset = args->offset;
40123c1f 852 obj_priv->dirty = 1;
673a394b 853
40123c1f
EA		 854 while (remain > 0) {
855 /* Operation in this page
856 *
857 * shmem_page_index = page number within shmem file
858 * shmem_page_offset = offset within page in shmem file
859 * data_page_index = page number in get_user_pages return
860 * data_page_offset = offset with data_page_index page.
861 * page_length = bytes to copy for this page
862 */
863 shmem_page_index = offset / PAGE_SIZE;
864 shmem_page_offset = offset & ~PAGE_MASK;
865 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
866 data_page_offset = data_ptr & ~PAGE_MASK;
867
868 page_length = remain;
869 if ((shmem_page_offset + page_length) > PAGE_SIZE)
870 page_length = PAGE_SIZE - shmem_page_offset;
871 if ((data_page_offset + page_length) > PAGE_SIZE)
872 page_length = PAGE_SIZE - data_page_offset;
873
280b713b 874 if (do_bit17_swizzling) {
99a03df5 875 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b
EA		 876 shmem_page_offset,
877 user_pages[data_page_index],
878 data_page_offset,
99a03df5
CW		 879 page_length,
880 0);
881 } else {
882 slow_shmem_copy(obj_priv->pages[shmem_page_index],
883 shmem_page_offset,
884 user_pages[data_page_index],
885 data_page_offset,
886 page_length);
280b713b 887 }
40123c1f
EA		 888
889 remain -= page_length;
890 data_ptr += page_length;
891 offset += page_length;
673a394b
EA		 892 }
893
40123c1f
EA		 894fail_put_pages:
895 i915_gem_object_put_pages(obj);
896fail_unlock:
673a394b 897 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 898fail_put_user_pages:
899 for (i = 0; i < pinned_pages; i++)
900 page_cache_release(user_pages[i]);
8e7d2b2c 901 drm_free_large(user_pages);
673a394b 902
40123c1f 903 return ret;
673a394b
EA		 904}
905
906/**
907 * Writes data to the object referenced by handle.
908 *
909 * On error, the contents of the buffer that were to be modified are undefined.
910 */
911int
912i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
913 struct drm_file *file_priv)
914{
915 struct drm_i915_gem_pwrite *args = data;
916 struct drm_gem_object *obj;
917 struct drm_i915_gem_object *obj_priv;
918 int ret = 0;
919
920 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
921 if (obj == NULL)
922 return -EBADF;
23010e43 923 obj_priv = to_intel_bo(obj);
673a394b
EA		 924
925 /* Bounds check destination.
926 *
927 * XXX: This could use review for overflow issues...
928 */
929 if (args->offset > obj->size || args->size > obj->size ||
930 args->offset + args->size > obj->size) {
bc9025bd 931 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 932 return -EINVAL;
933 }
934
935 /* We can only do the GTT pwrite on untiled buffers, as otherwise
936 * it would end up going through the fenced access, and we'll get
937 * different detiling behavior between reading and writing.
938 * pread/pwrite currently are reading and writing from the CPU
939 * perspective, requiring manual detiling by the client.
940 */
71acb5eb
DA		 941 if (obj_priv->phys_obj)
942 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
943 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
9b8c4a0b
CW		 944 dev->gtt_total != 0 &&
945 obj->write_domain != I915_GEM_DOMAIN_CPU) {
3de09aa3
EA		 946 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
947 if (ret == -EFAULT) {
948 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
949 file_priv);
950 }
280b713b
EA		 951 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
952 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 953 } else {
954 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
955 if (ret == -EFAULT) {
956 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
957 file_priv);
958 }
959 }
673a394b
EA		 960
961#if WATCH_PWRITE
962 if (ret)
963 DRM_INFO("pwrite failed %d\n", ret);
964#endif
965
bc9025bd 966 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 967
968 return ret;
969}
970
971/**
2ef7eeaa
EA		 972 * Called when user space prepares to use an object with the CPU, either
973 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 974 */
975int
976i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *file_priv)
978{
a09ba7fa 979 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 980 struct drm_i915_gem_set_domain *args = data;
981 struct drm_gem_object *obj;
652c393a 982 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 983 uint32_t read_domains = args->read_domains;
984 uint32_t write_domain = args->write_domain;
673a394b
EA		 985 int ret;
986
987 if (!(dev->driver->driver_features & DRIVER_GEM))
988 return -ENODEV;
989
2ef7eeaa 990 /* Only handle setting domains to types used by the CPU. */
21d509e3 991 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 992 return -EINVAL;
993
21d509e3 994 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 995 return -EINVAL;
996
997 /* Having something in the write domain implies it's in the read
998 * domain, and only that read domain. Enforce that in the request.
999 */
1000 if (write_domain != 0 && read_domains != write_domain)
1001 return -EINVAL;
1002
673a394b
EA		 1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1004 if (obj == NULL)
1005 return -EBADF;
23010e43 1006 obj_priv = to_intel_bo(obj);
673a394b
EA		 1007
1008 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1009
1010 intel_mark_busy(dev, obj);
1011
673a394b 1012#if WATCH_BUF
cfd43c02 1013 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1014 obj, obj->size, read_domains, write_domain);
673a394b 1015#endif
2ef7eeaa
EA		 1016 if (read_domains & I915_GEM_DOMAIN_GTT) {
1017 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1018
a09ba7fa
EA		 1019 /* Update the LRU on the fence for the CPU access that's
1020 * about to occur.
1021 */
1022 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1023 struct drm_i915_fence_reg *reg =
1024 &dev_priv->fence_regs[obj_priv->fence_reg];
1025 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1026 &dev_priv->mm.fence_list);
1027 }
1028
02354392
EA		 1029 /* Silently promote "you're not bound, there was nothing to do"
1030 * to success, since the client was just asking us to
1031 * make sure everything was done.
1032 */
1033 if (ret == -EINVAL)
1034 ret = 0;
2ef7eeaa 1035 } else {
e47c68e9 1036 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1037 }
1038
673a394b
EA		 1039 drm_gem_object_unreference(obj);
1040 mutex_unlock(&dev->struct_mutex);
1041 return ret;
1042}
1043
1044/**
1045 * Called when user space has done writes to this buffer
1046 */
1047int
1048i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv)
1050{
1051 struct drm_i915_gem_sw_finish *args = data;
1052 struct drm_gem_object *obj;
1053 struct drm_i915_gem_object *obj_priv;
1054 int ret = 0;
1055
1056 if (!(dev->driver->driver_features & DRIVER_GEM))
1057 return -ENODEV;
1058
1059 mutex_lock(&dev->struct_mutex);
1060 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1061 if (obj == NULL) {
1062 mutex_unlock(&dev->struct_mutex);
1063 return -EBADF;
1064 }
1065
1066#if WATCH_BUF
cfd43c02 1067 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1068 __func__, args->handle, obj, obj->size);
1069#endif
23010e43 1070 obj_priv = to_intel_bo(obj);
673a394b
EA		 1071
1072 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1073 if (obj_priv->pin_count)
1074 i915_gem_object_flush_cpu_write_domain(obj);
1075
673a394b
EA		 1076 drm_gem_object_unreference(obj);
1077 mutex_unlock(&dev->struct_mutex);
1078 return ret;
1079}
1080
1081/**
1082 * Maps the contents of an object, returning the address it is mapped
1083 * into.
1084 *
1085 * While the mapping holds a reference on the contents of the object, it doesn't
1086 * imply a ref on the object itself.
1087 */
1088int
1089i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1090 struct drm_file *file_priv)
1091{
1092 struct drm_i915_gem_mmap *args = data;
1093 struct drm_gem_object *obj;
1094 loff_t offset;
1095 unsigned long addr;
1096
1097 if (!(dev->driver->driver_features & DRIVER_GEM))
1098 return -ENODEV;
1099
1100 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1101 if (obj == NULL)
1102 return -EBADF;
1103
1104 offset = args->offset;
1105
1106 down_write(&current->mm->mmap_sem);
1107 addr = do_mmap(obj->filp, 0, args->size,
1108 PROT_READ | PROT_WRITE, MAP_SHARED,
1109 args->offset);
1110 up_write(&current->mm->mmap_sem);
bc9025bd 1111 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1112 if (IS_ERR((void *)addr))
1113 return addr;
1114
1115 args->addr_ptr = (uint64_t) addr;
1116
1117 return 0;
1118}
1119
de151cf6
JB		 1120/**
1121 * i915_gem_fault - fault a page into the GTT
1122 * vma: VMA in question
1123 * vmf: fault info
1124 *
1125 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1126 * from userspace. The fault handler takes care of binding the object to
1127 * the GTT (if needed), allocating and programming a fence register (again,
1128 * only if needed based on whether the old reg is still valid or the object
1129 * is tiled) and inserting a new PTE into the faulting process.
1130 *
1131 * Note that the faulting process may involve evicting existing objects
1132 * from the GTT and/or fence registers to make room. So performance may
1133 * suffer if the GTT working set is large or there are few fence registers
1134 * left.
1135 */
1136int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1137{
1138 struct drm_gem_object *obj = vma->vm_private_data;
1139 struct drm_device *dev = obj->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 1141 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1142 pgoff_t page_offset;
1143 unsigned long pfn;
1144 int ret = 0;
0f973f27 1145 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1146
1147 /* We don't use vmf->pgoff since that has the fake offset */
1148 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1149 PAGE_SHIFT;
1150
1151 /* Now bind it into the GTT if needed */
1152 mutex_lock(&dev->struct_mutex);
1153 if (!obj_priv->gtt_space) {
e67b8ce1 1154 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1155 if (ret)
1156 goto unlock;
07f4f3e8 1157
14b60391 1158 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1159
1160 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1161 if (ret)
1162 goto unlock;
de151cf6
JB		 1163 }
1164
1165 /* Need a new fence register? */
a09ba7fa 1166 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1167 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1168 if (ret)
1169 goto unlock;
d9ddcb96 1170 }
de151cf6
JB		 1171
1172 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1173 page_offset;
1174
1175 /* Finally, remap it using the new GTT offset */
1176 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1177unlock:
de151cf6
JB		 1178 mutex_unlock(&dev->struct_mutex);
1179
1180 switch (ret) {
c715089f
CW		 1181 case 0:
1182 case -ERESTARTSYS:
1183 return VM_FAULT_NOPAGE;
de151cf6
JB		 1184 case -ENOMEM:
1185 case -EAGAIN:
1186 return VM_FAULT_OOM;
de151cf6 1187 default:
c715089f 1188 return VM_FAULT_SIGBUS;
de151cf6
JB		 1189 }
1190}
1191
1192/**
1193 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1194 * @obj: obj in question
1195 *
1196 * GEM memory mapping works by handing back to userspace a fake mmap offset
1197 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1198 * up the object based on the offset and sets up the various memory mapping
1199 * structures.
1200 *
1201 * This routine allocates and attaches a fake offset for @obj.
1202 */
1203static int
1204i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1205{
1206 struct drm_device *dev = obj->dev;
1207 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1208 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1209 struct drm_map_list *list;
f77d390c 1210 struct drm_local_map *map;
de151cf6
JB		 1211 int ret = 0;
1212
1213 /* Set the object up for mmap'ing */
1214 list = &obj->map_list;
9a298b2a 1215 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1216 if (!list->map)
1217 return -ENOMEM;
1218
1219 map = list->map;
1220 map->type = _DRM_GEM;
1221 map->size = obj->size;
1222 map->handle = obj;
1223
1224 /* Get a DRM GEM mmap offset allocated... */
1225 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1226 obj->size / PAGE_SIZE, 0, 0);
1227 if (!list->file_offset_node) {
1228 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1229 ret = -ENOMEM;
1230 goto out_free_list;
1231 }
1232
1233 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1234 obj->size / PAGE_SIZE, 0);
1235 if (!list->file_offset_node) {
1236 ret = -ENOMEM;
1237 goto out_free_list;
1238 }
1239
1240 list->hash.key = list->file_offset_node->start;
1241 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1242 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1243 ret = -ENOMEM;
de151cf6
JB		 1244 goto out_free_mm;
1245 }
1246
1247 /* By now we should be all set, any drm_mmap request on the offset
1248 * below will get to our mmap & fault handler */
1249 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1250
1251 return 0;
1252
1253out_free_mm:
1254 drm_mm_put_block(list->file_offset_node);
1255out_free_list:
9a298b2a 1256 kfree(list->map);
de151cf6
JB		 1257
1258 return ret;
1259}
1260
901782b2
CW		 1261/**
1262 * i915_gem_release_mmap - remove physical page mappings
1263 * @obj: obj in question
1264 *
af901ca1 1265 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1266 * relinquish ownership of the pages back to the system.
1267 *
1268 * It is vital that we remove the page mapping if we have mapped a tiled
1269 * object through the GTT and then lose the fence register due to
1270 * resource pressure. Similarly if the object has been moved out of the
1271 * aperture, than pages mapped into userspace must be revoked. Removing the
1272 * mapping will then trigger a page fault on the next user access, allowing
1273 * fixup by i915_gem_fault().
1274 */
d05ca301 1275void
901782b2
CW		 1276i915_gem_release_mmap(struct drm_gem_object *obj)
1277{
1278 struct drm_device *dev = obj->dev;
23010e43 1279 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1280
1281 if (dev->dev_mapping)
1282 unmap_mapping_range(dev->dev_mapping,
1283 obj_priv->mmap_offset, obj->size, 1);
1284}
1285
ab00b3e5
JB		 1286static void
1287i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1288{
1289 struct drm_device *dev = obj->dev;
23010e43 1290 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1291 struct drm_gem_mm *mm = dev->mm_private;
1292 struct drm_map_list *list;
1293
1294 list = &obj->map_list;
1295 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1296
1297 if (list->file_offset_node) {
1298 drm_mm_put_block(list->file_offset_node);
1299 list->file_offset_node = NULL;
1300 }
1301
1302 if (list->map) {
9a298b2a 1303 kfree(list->map);
ab00b3e5
JB		 1304 list->map = NULL;
1305 }
1306
1307 obj_priv->mmap_offset = 0;
1308}
1309
de151cf6
JB		 1310/**
1311 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1312 * @obj: object to check
1313 *
1314 * Return the required GTT alignment for an object, taking into account
1315 * potential fence register mapping if needed.
1316 */
1317static uint32_t
1318i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1319{
1320 struct drm_device *dev = obj->dev;
23010e43 1321 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1322 int start, i;
1323
1324 /*
1325 * Minimum alignment is 4k (GTT page size), but might be greater
1326 * if a fence register is needed for the object.
1327 */
1328 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1329 return 4096;
1330
1331 /*
1332 * Previous chips need to be aligned to the size of the smallest
1333 * fence register that can contain the object.
1334 */
1335 if (IS_I9XX(dev))
1336 start = 1024*1024;
1337 else
1338 start = 512*1024;
1339
1340 for (i = start; i < obj->size; i <<= 1)
1341 ;
1342
1343 return i;
1344}
1345
1346/**
1347 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1348 * @dev: DRM device
1349 * @data: GTT mapping ioctl data
1350 * @file_priv: GEM object info
1351 *
1352 * Simply returns the fake offset to userspace so it can mmap it.
1353 * The mmap call will end up in drm_gem_mmap(), which will set things
1354 * up so we can get faults in the handler above.
1355 *
1356 * The fault handler will take care of binding the object into the GTT
1357 * (since it may have been evicted to make room for something), allocating
1358 * a fence register, and mapping the appropriate aperture address into
1359 * userspace.
1360 */
1361int
1362i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1363 struct drm_file *file_priv)
1364{
1365 struct drm_i915_gem_mmap_gtt *args = data;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 struct drm_gem_object *obj;
1368 struct drm_i915_gem_object *obj_priv;
1369 int ret;
1370
1371 if (!(dev->driver->driver_features & DRIVER_GEM))
1372 return -ENODEV;
1373
1374 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1375 if (obj == NULL)
1376 return -EBADF;
1377
1378 mutex_lock(&dev->struct_mutex);
1379
23010e43 1380 obj_priv = to_intel_bo(obj);
de151cf6 1381
ab18282d
CW		 1382 if (obj_priv->madv != I915_MADV_WILLNEED) {
1383 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1384 drm_gem_object_unreference(obj);
1385 mutex_unlock(&dev->struct_mutex);
1386 return -EINVAL;
1387 }
1388
1389
de151cf6
JB		 1390 if (!obj_priv->mmap_offset) {
1391 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1392 if (ret) {
1393 drm_gem_object_unreference(obj);
1394 mutex_unlock(&dev->struct_mutex);
de151cf6 1395 return ret;
13af1062 1396 }
de151cf6
JB		 1397 }
1398
1399 args->offset = obj_priv->mmap_offset;
1400
de151cf6
JB		 1401 /*
1402 * Pull it into the GTT so that we have a page list (makes the
1403 * initial fault faster and any subsequent flushing possible).
1404 */
1405 if (!obj_priv->agp_mem) {
e67b8ce1 1406 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1407 if (ret) {
1408 drm_gem_object_unreference(obj);
1409 mutex_unlock(&dev->struct_mutex);
1410 return ret;
1411 }
14b60391 1412 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1413 }
1414
1415 drm_gem_object_unreference(obj);
1416 mutex_unlock(&dev->struct_mutex);
1417
1418 return 0;
1419}
1420
6911a9b8 1421void
856fa198 1422i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1423{
23010e43 1424 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1425 int page_count = obj->size / PAGE_SIZE;
1426 int i;
1427
856fa198 1428 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1429 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1430
856fa198
EA		 1431 if (--obj_priv->pages_refcount != 0)
1432 return;
673a394b 1433
280b713b
EA		 1434 if (obj_priv->tiling_mode != I915_TILING_NONE)
1435 i915_gem_object_save_bit_17_swizzle(obj);
1436
3ef94daa 1437 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1438 obj_priv->dirty = 0;
3ef94daa
CW		 1439
1440 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1441 if (obj_priv->dirty)
1442 set_page_dirty(obj_priv->pages[i]);
1443
1444 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1445 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1446
1447 page_cache_release(obj_priv->pages[i]);
1448 }
673a394b
EA		 1449 obj_priv->dirty = 0;
1450
8e7d2b2c 1451 drm_free_large(obj_priv->pages);
856fa198 1452 obj_priv->pages = NULL;
673a394b
EA		 1453}
1454
1455static void
852835f3
ZN		 1456i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1457 struct intel_ring_buffer *ring)
673a394b
EA		 1458{
1459 struct drm_device *dev = obj->dev;
1460 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1461 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
852835f3
ZN		 1462 BUG_ON(ring == NULL);
1463 obj_priv->ring = ring;
673a394b
EA		 1464
1465 /* Add a reference if we're newly entering the active list. */
1466 if (!obj_priv->active) {
1467 drm_gem_object_reference(obj);
1468 obj_priv->active = 1;
1469 }
1470 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1471 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1472 list_move_tail(&obj_priv->list, &ring->active_list);
5e118f41 1473 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1474 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1475}
1476
ce44b0ea
EA		 1477static void
1478i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1479{
1480 struct drm_device *dev = obj->dev;
1481 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1482 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1483
1484 BUG_ON(!obj_priv->active);
1485 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1486 obj_priv->last_rendering_seqno = 0;
1487}
673a394b 1488
963b4836
CW		 1489/* Immediately discard the backing storage */
1490static void
1491i915_gem_object_truncate(struct drm_gem_object *obj)
1492{
23010e43 1493 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1494 struct inode *inode;
963b4836 1495
bb6baf76
CW		 1496 inode = obj->filp->f_path.dentry->d_inode;
1497 if (inode->i_op->truncate)
1498 inode->i_op->truncate (inode);
1499
1500 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1501}
1502
1503static inline int
1504i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1505{
1506 return obj_priv->madv == I915_MADV_DONTNEED;
1507}
1508
673a394b
EA		 1509static void
1510i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1511{
1512 struct drm_device *dev = obj->dev;
1513 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1514 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1515
1516 i915_verify_inactive(dev, __FILE__, __LINE__);
1517 if (obj_priv->pin_count != 0)
1518 list_del_init(&obj_priv->list);
1519 else
1520 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1521
99fcb766
DV		 1522 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1523
ce44b0ea 1524 obj_priv->last_rendering_seqno = 0;
852835f3 1525 obj_priv->ring = NULL;
673a394b
EA		 1526 if (obj_priv->active) {
1527 obj_priv->active = 0;
1528 drm_gem_object_unreference(obj);
1529 }
1530 i915_verify_inactive(dev, __FILE__, __LINE__);
1531}
1532
63560396
DV		 1533static void
1534i915_gem_process_flushing_list(struct drm_device *dev,
852835f3
ZN		 1535 uint32_t flush_domains, uint32_t seqno,
1536 struct intel_ring_buffer *ring)
63560396
DV		 1537{
1538 drm_i915_private_t *dev_priv = dev->dev_private;
1539 struct drm_i915_gem_object *obj_priv, *next;
1540
1541 list_for_each_entry_safe(obj_priv, next,
1542 &dev_priv->mm.gpu_write_list,
1543 gpu_write_list) {
a8089e84 1544 struct drm_gem_object *obj = &obj_priv->base;
63560396
DV		 1545
1546 if ((obj->write_domain & flush_domains) ==
852835f3
ZN		 1547 obj->write_domain &&
1548 obj_priv->ring->ring_flag == ring->ring_flag) {
63560396
DV		 1549 uint32_t old_write_domain = obj->write_domain;
1550
1551 obj->write_domain = 0;
1552 list_del_init(&obj_priv->gpu_write_list);
852835f3 1553 i915_gem_object_move_to_active(obj, seqno, ring);
63560396
DV		 1554
1555 /* update the fence lru list */
007cc8ac
DV		 1556 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1557 struct drm_i915_fence_reg *reg =
1558 &dev_priv->fence_regs[obj_priv->fence_reg];
1559 list_move_tail(&reg->lru_list,
63560396 1560 &dev_priv->mm.fence_list);
007cc8ac 1561 }
63560396
DV		 1562
1563 trace_i915_gem_object_change_domain(obj,
1564 obj->read_domains,
1565 old_write_domain);
1566 }
1567 }
1568}
8187a2b7 1569
5a5a0c64 1570uint32_t
b962442e 1571i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
852835f3 1572 uint32_t flush_domains, struct intel_ring_buffer *ring)
673a394b
EA		 1573{
1574 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1575 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1576 struct drm_i915_gem_request *request;
1577 uint32_t seqno;
1578 int was_empty;
673a394b 1579
b962442e
EA		 1580 if (file_priv != NULL)
1581 i915_file_priv = file_priv->driver_priv;
1582
9a298b2a 1583 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1584 if (request == NULL)
1585 return 0;
1586
852835f3 1587 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
673a394b
EA		 1588
1589 request->seqno = seqno;
852835f3 1590 request->ring = ring;
673a394b 1591 request->emitted_jiffies = jiffies;
852835f3
ZN		 1592 was_empty = list_empty(&ring->request_list);
1593 list_add_tail(&request->list, &ring->request_list);
1594
b962442e
EA		 1595 if (i915_file_priv) {
1596 list_add_tail(&request->client_list,
1597 &i915_file_priv->mm.request_list);
1598 } else {
1599 INIT_LIST_HEAD(&request->client_list);
1600 }
673a394b 1601
ce44b0ea
EA		 1602 /* Associate any objects on the flushing list matching the write
1603 * domain we're flushing with our flush.
1604 */
63560396 1605 if (flush_domains != 0)
852835f3 1606 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
ce44b0ea 1607
f65d9421
BG		 1608 if (!dev_priv->mm.suspended) {
1609 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1610 if (was_empty)
1611 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1612 }
673a394b
EA		 1613 return seqno;
1614}
1615
1616/**
1617 * Command execution barrier
1618 *
1619 * Ensures that all commands in the ring are finished
1620 * before signalling the CPU
1621 */
3043c60c 1622static uint32_t
852835f3 1623i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
673a394b 1624{
673a394b 1625 uint32_t flush_domains = 0;
673a394b
EA		 1626
1627 /* The sampler always gets flushed on i965 (sigh) */
1628 if (IS_I965G(dev))
1629 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
852835f3
ZN		 1630
1631 ring->flush(dev, ring,
1632 I915_GEM_DOMAIN_COMMAND, flush_domains);
673a394b
EA		 1633 return flush_domains;
1634}
1635
1636/**
1637 * Moves buffers associated only with the given active seqno from the active
1638 * to inactive list, potentially freeing them.
1639 */
1640static void
1641i915_gem_retire_request(struct drm_device *dev,
1642 struct drm_i915_gem_request *request)
1643{
1644 drm_i915_private_t *dev_priv = dev->dev_private;
1645
1c5d22f7
CW		 1646 trace_i915_gem_request_retire(dev, request->seqno);
1647
673a394b
EA		 1648 /* Move any buffers on the active list that are no longer referenced
1649 * by the ringbuffer to the flushing/inactive lists as appropriate.
1650 */
5e118f41 1651 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1652 while (!list_empty(&request->ring->active_list)) {
673a394b
EA		 1653 struct drm_gem_object *obj;
1654 struct drm_i915_gem_object *obj_priv;
1655
852835f3 1656 obj_priv = list_first_entry(&request->ring->active_list,
673a394b
EA		 1657 struct drm_i915_gem_object,
1658 list);
a8089e84 1659 obj = &obj_priv->base;
673a394b
EA		 1660
1661 /* If the seqno being retired doesn't match the oldest in the
1662 * list, then the oldest in the list must still be newer than
1663 * this seqno.
1664 */
1665 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1666 goto out;
de151cf6 1667
673a394b
EA		 1668#if WATCH_LRU
1669 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1670 __func__, request->seqno, obj);
1671#endif
1672
ce44b0ea
EA		 1673 if (obj->write_domain != 0)
1674 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1675 else {
1676 /* Take a reference on the object so it won't be
1677 * freed while the spinlock is held. The list
1678 * protection for this spinlock is safe when breaking
1679 * the lock like this since the next thing we do
1680 * is just get the head of the list again.
1681 */
1682 drm_gem_object_reference(obj);
673a394b 1683 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1684 spin_unlock(&dev_priv->mm.active_list_lock);
1685 drm_gem_object_unreference(obj);
1686 spin_lock(&dev_priv->mm.active_list_lock);
1687 }
673a394b 1688 }
5e118f41
CW		 1689out:
1690 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1691}
1692
1693/**
1694 * Returns true if seq1 is later than seq2.
1695 */
22be1724 1696bool
673a394b
EA		 1697i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1698{
1699 return (int32_t)(seq1 - seq2) >= 0;
1700}
1701
1702uint32_t
852835f3 1703i915_get_gem_seqno(struct drm_device *dev,
d1b851fc 1704 struct intel_ring_buffer *ring)
673a394b 1705{
852835f3 1706 return ring->get_gem_seqno(dev, ring);
673a394b
EA		 1707}
1708
1709/**
1710 * This function clears the request list as sequence numbers are passed.
1711 */
b09a1fec
CW		 1712static void
1713i915_gem_retire_requests_ring(struct drm_device *dev,
1714 struct intel_ring_buffer *ring)
673a394b
EA		 1715{
1716 drm_i915_private_t *dev_priv = dev->dev_private;
1717 uint32_t seqno;
1718
8187a2b7 1719 if (!ring->status_page.page_addr
852835f3 1720 || list_empty(&ring->request_list))
6c0594a3
KW		 1721 return;
1722
852835f3 1723 seqno = i915_get_gem_seqno(dev, ring);
673a394b 1724
852835f3 1725 while (!list_empty(&ring->request_list)) {
673a394b
EA		 1726 struct drm_i915_gem_request *request;
1727 uint32_t retiring_seqno;
1728
852835f3 1729 request = list_first_entry(&ring->request_list,
673a394b
EA		 1730 struct drm_i915_gem_request,
1731 list);
1732 retiring_seqno = request->seqno;
1733
1734 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1735 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1736 i915_gem_retire_request(dev, request);
1737
1738 list_del(&request->list);
b962442e 1739 list_del(&request->client_list);
9a298b2a 1740 kfree(request);
673a394b
EA		 1741 } else
1742 break;
1743 }
9d34e5db
CW		 1744
1745 if (unlikely (dev_priv->trace_irq_seqno &&
1746 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7
ZN		 1747
1748 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1749 dev_priv->trace_irq_seqno = 0;
1750 }
673a394b
EA		 1751}
1752
b09a1fec
CW		 1753void
1754i915_gem_retire_requests(struct drm_device *dev)
1755{
1756 drm_i915_private_t *dev_priv = dev->dev_private;
1757
1758 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1759 if (HAS_BSD(dev))
1760 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1761}
1762
673a394b
EA		 1763void
1764i915_gem_retire_work_handler(struct work_struct *work)
1765{
1766 drm_i915_private_t *dev_priv;
1767 struct drm_device *dev;
1768
1769 dev_priv = container_of(work, drm_i915_private_t,
1770 mm.retire_work.work);
1771 dev = dev_priv->dev;
1772
1773 mutex_lock(&dev->struct_mutex);
b09a1fec 1774 i915_gem_retire_requests(dev);
d1b851fc 1775
6dbe2772 1776 if (!dev_priv->mm.suspended &&
d1b851fc
ZN		 1777 (!list_empty(&dev_priv->render_ring.request_list) ||
1778 (HAS_BSD(dev) &&
1779 !list_empty(&dev_priv->bsd_ring.request_list))))
9c9fe1f8 1780 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1781 mutex_unlock(&dev->struct_mutex);
1782}
1783
5a5a0c64 1784int
852835f3
ZN		 1785i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1786 int interruptible, struct intel_ring_buffer *ring)
673a394b
EA		 1787{
1788 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1789 u32 ier;
673a394b
EA		 1790 int ret = 0;
1791
1792 BUG_ON(seqno == 0);
1793
ba1234d1 1794 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1795 return -EIO;
1796
852835f3 1797 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
bad720ff 1798 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1799 ier = I915_READ(DEIER) | I915_READ(GTIER);
1800 else
1801 ier = I915_READ(IER);
802c7eb6
JB		 1802 if (!ier) {
1803 DRM_ERROR("something (likely vbetool) disabled "
1804 "interrupts, re-enabling\n");
1805 i915_driver_irq_preinstall(dev);
1806 i915_driver_irq_postinstall(dev);
1807 }
1808
1c5d22f7
CW		 1809 trace_i915_gem_request_wait_begin(dev, seqno);
1810
852835f3 1811 ring->waiting_gem_seqno = seqno;
8187a2b7 1812 ring->user_irq_get(dev, ring);
48764bf4 1813 if (interruptible)
852835f3
ZN		 1814 ret = wait_event_interruptible(ring->irq_queue,
1815 i915_seqno_passed(
1816 ring->get_gem_seqno(dev, ring), seqno)
1817 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1818 else
852835f3
ZN		 1819 wait_event(ring->irq_queue,
1820 i915_seqno_passed(
1821 ring->get_gem_seqno(dev, ring), seqno)
1822 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1823
8187a2b7 1824 ring->user_irq_put(dev, ring);
852835f3 1825 ring->waiting_gem_seqno = 0;
1c5d22f7
CW		 1826
1827 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1828 }
ba1234d1 1829 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1830 ret = -EIO;
1831
1832 if (ret && ret != -ERESTARTSYS)
1833 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
852835f3 1834 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
673a394b
EA		 1835
1836 /* Directly dispatch request retiring. While we have the work queue
1837 * to handle this, the waiter on a request often wants an associated
1838 * buffer to have made it to the inactive list, and we would need
1839 * a separate wait queue to handle that.
1840 */
1841 if (ret == 0)
b09a1fec 1842 i915_gem_retire_requests_ring(dev, ring);
673a394b
EA		 1843
1844 return ret;
1845}
1846
48764bf4
DV		 1847/**
1848 * Waits for a sequence number to be signaled, and cleans up the
1849 * request and object lists appropriately for that event.
1850 */
1851static int
852835f3
ZN		 1852i915_wait_request(struct drm_device *dev, uint32_t seqno,
1853 struct intel_ring_buffer *ring)
48764bf4 1854{
852835f3 1855 return i915_do_wait_request(dev, seqno, 1, ring);
48764bf4
DV		 1856}
1857
8187a2b7
ZN		 1858static void
1859i915_gem_flush(struct drm_device *dev,
1860 uint32_t invalidate_domains,
1861 uint32_t flush_domains)
1862{
1863 drm_i915_private_t *dev_priv = dev->dev_private;
1864 if (flush_domains & I915_GEM_DOMAIN_CPU)
1865 drm_agp_chipset_flush(dev);
1866 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1867 invalidate_domains,
1868 flush_domains);
d1b851fc
ZN		 1869
1870 if (HAS_BSD(dev))
1871 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1872 invalidate_domains,
1873 flush_domains);
8187a2b7
ZN		 1874}
1875
852835f3
ZN		 1876static void
1877i915_gem_flush_ring(struct drm_device *dev,
1878 uint32_t invalidate_domains,
1879 uint32_t flush_domains,
1880 struct intel_ring_buffer *ring)
1881{
1882 if (flush_domains & I915_GEM_DOMAIN_CPU)
1883 drm_agp_chipset_flush(dev);
1884 ring->flush(dev, ring,
1885 invalidate_domains,
1886 flush_domains);
1887}
1888
673a394b
EA		 1889/**
1890 * Ensures that all rendering to the object has completed and the object is
1891 * safe to unbind from the GTT or access from the CPU.
1892 */
1893static int
1894i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1895{
1896 struct drm_device *dev = obj->dev;
23010e43 1897 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1898 int ret;
1899
e47c68e9
EA		 1900 /* This function only exists to support waiting for existing rendering,
1901 * not for emitting required flushes.
673a394b 1902 */
e47c68e9 1903 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1904
1905 /* If there is rendering queued on the buffer being evicted, wait for
1906 * it.
1907 */
1908 if (obj_priv->active) {
1909#if WATCH_BUF
1910 DRM_INFO("%s: object %p wait for seqno %08x\n",
1911 __func__, obj, obj_priv->last_rendering_seqno);
1912#endif
852835f3
ZN		 1913 ret = i915_wait_request(dev,
1914 obj_priv->last_rendering_seqno, obj_priv->ring);
673a394b
EA		 1915 if (ret != 0)
1916 return ret;
1917 }
1918
1919 return 0;
1920}
1921
1922/**
1923 * Unbinds an object from the GTT aperture.
1924 */
0f973f27 1925int
673a394b
EA		 1926i915_gem_object_unbind(struct drm_gem_object *obj)
1927{
1928 struct drm_device *dev = obj->dev;
4a87b8ca 1929 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1930 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1931 int ret = 0;
1932
1933#if WATCH_BUF
1934 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1935 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1936#endif
1937 if (obj_priv->gtt_space == NULL)
1938 return 0;
1939
1940 if (obj_priv->pin_count != 0) {
1941 DRM_ERROR("Attempting to unbind pinned buffer\n");
1942 return -EINVAL;
1943 }
1944
5323fd04
EA		 1945 /* blow away mappings if mapped through GTT */
1946 i915_gem_release_mmap(obj);
1947
673a394b
EA		 1948 /* Move the object to the CPU domain to ensure that
1949 * any possible CPU writes while it's not in the GTT
1950 * are flushed when we go to remap it. This will
1951 * also ensure that all pending GPU writes are finished
1952 * before we unbind.
1953 */
e47c68e9 1954 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 1955 if (ret) {
e47c68e9
EA		 1956 if (ret != -ERESTARTSYS)
1957 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 1958 return ret;
1959 }
1960
5323fd04
EA		 1961 BUG_ON(obj_priv->active);
1962
96b47b65
DV		 1963 /* release the fence reg _after_ flushing */
1964 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1965 i915_gem_clear_fence_reg(obj);
1966
673a394b
EA		 1967 if (obj_priv->agp_mem != NULL) {
1968 drm_unbind_agp(obj_priv->agp_mem);
1969 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1970 obj_priv->agp_mem = NULL;
1971 }
1972
856fa198 1973 i915_gem_object_put_pages(obj);
a32808c0 1974 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 1975
1976 if (obj_priv->gtt_space) {
1977 atomic_dec(&dev->gtt_count);
1978 atomic_sub(obj->size, &dev->gtt_memory);
1979
1980 drm_mm_put_block(obj_priv->gtt_space);
1981 obj_priv->gtt_space = NULL;
1982 }
1983
1984 /* Remove ourselves from the LRU list if present. */
4a87b8ca 1985 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1986 if (!list_empty(&obj_priv->list))
1987 list_del_init(&obj_priv->list);
4a87b8ca 1988 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 1989
963b4836
CW		 1990 if (i915_gem_object_is_purgeable(obj_priv))
1991 i915_gem_object_truncate(obj);
1992
1c5d22f7
CW		 1993 trace_i915_gem_object_unbind(obj);
1994
673a394b
EA		 1995 return 0;
1996}
1997
07f73f69
CW		 1998static struct drm_gem_object *
1999i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2000{
2001 drm_i915_private_t *dev_priv = dev->dev_private;
2002 struct drm_i915_gem_object *obj_priv;
2003 struct drm_gem_object *best = NULL;
2004 struct drm_gem_object *first = NULL;
2005
2006 /* Try to find the smallest clean object */
2007 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
a8089e84 2008 struct drm_gem_object *obj = &obj_priv->base;
07f73f69 2009 if (obj->size >= min_size) {
963b4836
CW		 2010 if ((!obj_priv->dirty ||
2011 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2012 (!best || obj->size < best->size)) {
2013 best = obj;
2014 if (best->size == min_size)
2015 return best;
2016 }
2017 if (!first)
2018 first = obj;
2019 }
2020 }
2021
2022 return best ? best : first;
2023}
2024
4df2faf4
DV		 2025static int
2026i915_gpu_idle(struct drm_device *dev)
2027{
2028 drm_i915_private_t *dev_priv = dev->dev_private;
2029 bool lists_empty;
d1b851fc 2030 uint32_t seqno1, seqno2;
852835f3 2031 int ret;
4df2faf4
DV		 2032
2033 spin_lock(&dev_priv->mm.active_list_lock);
d1b851fc
ZN		 2034 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2035 list_empty(&dev_priv->render_ring.active_list) &&
2036 (!HAS_BSD(dev) ||
2037 list_empty(&dev_priv->bsd_ring.active_list)));
4df2faf4
DV		 2038 spin_unlock(&dev_priv->mm.active_list_lock);
2039
2040 if (lists_empty)
2041 return 0;
2042
2043 /* Flush everything onto the inactive list. */
2044 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
d1b851fc 2045 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
852835f3 2046 &dev_priv->render_ring);
d1b851fc 2047 if (seqno1 == 0)
4df2faf4 2048 return -ENOMEM;
d1b851fc
ZN		 2049 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2050
2051 if (HAS_BSD(dev)) {
2052 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2053 &dev_priv->bsd_ring);
2054 if (seqno2 == 0)
2055 return -ENOMEM;
2056
2057 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2058 if (ret)
2059 return ret;
2060 }
2061
4df2faf4 2062
852835f3 2063 return ret;
4df2faf4
DV		 2064}
2065
673a394b 2066static int
07f73f69
CW		 2067i915_gem_evict_everything(struct drm_device *dev)
2068{
2069 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69
CW		 2070 int ret;
2071 bool lists_empty;
2072
07f73f69
CW		 2073 spin_lock(&dev_priv->mm.active_list_lock);
2074 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2075 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2076 list_empty(&dev_priv->render_ring.active_list) &&
2077 (!HAS_BSD(dev)
2078 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2079 spin_unlock(&dev_priv->mm.active_list_lock);
2080
9731129c 2081 if (lists_empty)
07f73f69 2082 return -ENOSPC;
07f73f69
CW		 2083
2084 /* Flush everything (on to the inactive lists) and evict */
4df2faf4 2085 ret = i915_gpu_idle(dev);
07f73f69
CW		 2086 if (ret)
2087 return ret;
2088
99fcb766
DV		 2089 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2090
ab5ee576 2091 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2092 if (ret)
2093 return ret;
2094
2095 spin_lock(&dev_priv->mm.active_list_lock);
2096 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2097 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2098 list_empty(&dev_priv->render_ring.active_list) &&
2099 (!HAS_BSD(dev)
2100 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2101 spin_unlock(&dev_priv->mm.active_list_lock);
2102 BUG_ON(!lists_empty);
2103
2104 return 0;
2105}
2106
673a394b 2107static int
07f73f69 2108i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2109{
2110 drm_i915_private_t *dev_priv = dev->dev_private;
2111 struct drm_gem_object *obj;
07f73f69 2112 int ret;
673a394b 2113
852835f3 2114 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
d1b851fc 2115 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
673a394b 2116 for (;;) {
b09a1fec 2117 i915_gem_retire_requests(dev);
d1b851fc 2118
673a394b
EA		 2119 /* If there's an inactive buffer available now, grab it
2120 * and be done.
2121 */
07f73f69
CW		 2122 obj = i915_gem_find_inactive_object(dev, min_size);
2123 if (obj) {
2124 struct drm_i915_gem_object *obj_priv;
2125
673a394b
EA		 2126#if WATCH_LRU
2127 DRM_INFO("%s: evicting %p\n", __func__, obj);
2128#endif
23010e43 2129 obj_priv = to_intel_bo(obj);
07f73f69 2130 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2131 BUG_ON(obj_priv->active);
2132
2133 /* Wait on the rendering and unbind the buffer. */
07f73f69 2134 return i915_gem_object_unbind(obj);
673a394b
EA		 2135 }
2136
2137 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2138 * things, wait for the next to finish and hopefully leave us
2139 * a buffer to evict.
673a394b 2140 */
852835f3 2141 if (!list_empty(&render_ring->request_list)) {
673a394b
EA		 2142 struct drm_i915_gem_request *request;
2143
852835f3 2144 request = list_first_entry(&render_ring->request_list,
673a394b
EA		 2145 struct drm_i915_gem_request,
2146 list);
2147
852835f3
ZN		 2148 ret = i915_wait_request(dev,
2149 request->seqno, request->ring);
673a394b 2150 if (ret)
07f73f69 2151 return ret;
673a394b 2152
07f73f69 2153 continue;
673a394b
EA		 2154 }
2155
d1b851fc
ZN		 2156 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2157 struct drm_i915_gem_request *request;
2158
2159 request = list_first_entry(&bsd_ring->request_list,
2160 struct drm_i915_gem_request,
2161 list);
2162
2163 ret = i915_wait_request(dev,
2164 request->seqno, request->ring);
2165 if (ret)
2166 return ret;
2167
2168 continue;
2169 }
2170
673a394b
EA		 2171 /* If we didn't have anything on the request list but there
2172 * are buffers awaiting a flush, emit one and try again.
2173 * When we wait on it, those buffers waiting for that flush
2174 * will get moved to inactive.
2175 */
2176 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2177 struct drm_i915_gem_object *obj_priv;
673a394b 2178
9a1e2582
CW		 2179 /* Find an object that we can immediately reuse */
2180 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
a8089e84 2181 obj = &obj_priv->base;
9a1e2582
CW		 2182 if (obj->size >= min_size)
2183 break;
673a394b 2184
9a1e2582
CW		 2185 obj = NULL;
2186 }
673a394b 2187
9a1e2582
CW		 2188 if (obj != NULL) {
2189 uint32_t seqno;
673a394b 2190
852835f3
ZN		 2191 i915_gem_flush_ring(dev,
2192 obj->write_domain,
9a1e2582 2193 obj->write_domain,
852835f3
ZN		 2194 obj_priv->ring);
2195 seqno = i915_add_request(dev, NULL,
2196 obj->write_domain,
2197 obj_priv->ring);
9a1e2582
CW		 2198 if (seqno == 0)
2199 return -ENOMEM;
9a1e2582
CW		 2200 continue;
2201 }
673a394b
EA		 2202 }
2203
07f73f69
CW		 2204 /* If we didn't do any of the above, there's no single buffer
2205 * large enough to swap out for the new one, so just evict
2206 * everything and start again. (This should be rare.)
673a394b 2207 */
9731129c 2208 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2209 return i915_gem_evict_from_inactive_list(dev);
9731129c 2210 else
07f73f69 2211 return i915_gem_evict_everything(dev);
ac94a962 2212 }
ac94a962
KP		 2213}
2214
6911a9b8 2215int
4bdadb97
CW		 2216i915_gem_object_get_pages(struct drm_gem_object *obj,
2217 gfp_t gfpmask)
673a394b 2218{
23010e43 2219 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2220 int page_count, i;
2221 struct address_space *mapping;
2222 struct inode *inode;
2223 struct page *page;
673a394b 2224
778c3544
DV		 2225 BUG_ON(obj_priv->pages_refcount
2226 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2227
856fa198 2228 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2229 return 0;
2230
2231 /* Get the list of pages out of our struct file. They'll be pinned
2232 * at this point until we release them.
2233 */
2234 page_count = obj->size / PAGE_SIZE;
856fa198 2235 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2236 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2237 if (obj_priv->pages == NULL) {
856fa198 2238 obj_priv->pages_refcount--;
673a394b
EA		 2239 return -ENOMEM;
2240 }
2241
2242 inode = obj->filp->f_path.dentry->d_inode;
2243 mapping = inode->i_mapping;
2244 for (i = 0; i < page_count; i++) {
4bdadb97 2245 page = read_cache_page_gfp(mapping, i,
985b823b 2246 GFP_HIGHUSER |
4bdadb97 2247 __GFP_COLD |
cd9f040d 2248 __GFP_RECLAIMABLE |
4bdadb97 2249 gfpmask);
1f2b1013
CW		 2250 if (IS_ERR(page))
2251 goto err_pages;
2252
856fa198 2253 obj_priv->pages[i] = page;
673a394b 2254 }
280b713b
EA		 2255
2256 if (obj_priv->tiling_mode != I915_TILING_NONE)
2257 i915_gem_object_do_bit_17_swizzle(obj);
2258
673a394b 2259 return 0;
1f2b1013
CW		 2260
2261err_pages:
2262 while (i--)
2263 page_cache_release(obj_priv->pages[i]);
2264
2265 drm_free_large(obj_priv->pages);
2266 obj_priv->pages = NULL;
2267 obj_priv->pages_refcount--;
2268 return PTR_ERR(page);
673a394b
EA		 2269}
2270
4e901fdc
EA		 2271static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2272{
2273 struct drm_gem_object *obj = reg->obj;
2274 struct drm_device *dev = obj->dev;
2275 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2276 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2277 int regnum = obj_priv->fence_reg;
2278 uint64_t val;
2279
2280 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2281 0xfffff000) << 32;
2282 val |= obj_priv->gtt_offset & 0xfffff000;
2283 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2284 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2285
2286 if (obj_priv->tiling_mode == I915_TILING_Y)
2287 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2288 val |= I965_FENCE_REG_VALID;
2289
2290 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2291}
2292
de151cf6
JB		 2293static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2294{
2295 struct drm_gem_object *obj = reg->obj;
2296 struct drm_device *dev = obj->dev;
2297 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2298 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2299 int regnum = obj_priv->fence_reg;
2300 uint64_t val;
2301
2302 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2303 0xfffff000) << 32;
2304 val |= obj_priv->gtt_offset & 0xfffff000;
2305 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2306 if (obj_priv->tiling_mode == I915_TILING_Y)
2307 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2308 val |= I965_FENCE_REG_VALID;
2309
2310 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2311}
2312
2313static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2314{
2315 struct drm_gem_object *obj = reg->obj;
2316 struct drm_device *dev = obj->dev;
2317 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2318 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2319 int regnum = obj_priv->fence_reg;
0f973f27 2320 int tile_width;
dc529a4f 2321 uint32_t fence_reg, val;
de151cf6
JB		 2322 uint32_t pitch_val;
2323
2324 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2325 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2326 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2327 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2328 return;
2329 }
2330
0f973f27
JB		 2331 if (obj_priv->tiling_mode == I915_TILING_Y &&
2332 HAS_128_BYTE_Y_TILING(dev))
2333 tile_width = 128;
de151cf6 2334 else
0f973f27
JB		 2335 tile_width = 512;
2336
2337 /* Note: pitch better be a power of two tile widths */
2338 pitch_val = obj_priv->stride / tile_width;
2339 pitch_val = ffs(pitch_val) - 1;
de151cf6 2340
c36a2a6d
DV		 2341 if (obj_priv->tiling_mode == I915_TILING_Y &&
2342 HAS_128_BYTE_Y_TILING(dev))
2343 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2344 else
2345 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2346
de151cf6
JB		 2347 val = obj_priv->gtt_offset;
2348 if (obj_priv->tiling_mode == I915_TILING_Y)
2349 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2350 val |= I915_FENCE_SIZE_BITS(obj->size);
2351 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2352 val |= I830_FENCE_REG_VALID;
2353
dc529a4f
EA		 2354 if (regnum < 8)
2355 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2356 else
2357 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2358 I915_WRITE(fence_reg, val);
de151cf6
JB		 2359}
2360
2361static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2362{
2363 struct drm_gem_object *obj = reg->obj;
2364 struct drm_device *dev = obj->dev;
2365 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2366 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2367 int regnum = obj_priv->fence_reg;
2368 uint32_t val;
2369 uint32_t pitch_val;
8d7773a3 2370 uint32_t fence_size_bits;
de151cf6 2371
8d7773a3 2372 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2373 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2374 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2375 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2376 return;
2377 }
2378
e76a16de
EA		 2379 pitch_val = obj_priv->stride / 128;
2380 pitch_val = ffs(pitch_val) - 1;
2381 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2382
de151cf6
JB		 2383 val = obj_priv->gtt_offset;
2384 if (obj_priv->tiling_mode == I915_TILING_Y)
2385 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2386 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2387 WARN_ON(fence_size_bits & ~0x00000f00);
2388 val |= fence_size_bits;
de151cf6
JB		 2389 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2390 val |= I830_FENCE_REG_VALID;
2391
2392 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2393}
2394
ae3db24a
DV		 2395static int i915_find_fence_reg(struct drm_device *dev)
2396{
2397 struct drm_i915_fence_reg *reg = NULL;
2398 struct drm_i915_gem_object *obj_priv = NULL;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct drm_gem_object *obj = NULL;
2401 int i, avail, ret;
2402
2403 /* First try to find a free reg */
2404 avail = 0;
2405 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2406 reg = &dev_priv->fence_regs[i];
2407 if (!reg->obj)
2408 return i;
2409
23010e43 2410 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2411 if (!obj_priv->pin_count)
2412 avail++;
2413 }
2414
2415 if (avail == 0)
2416 return -ENOSPC;
2417
2418 /* None available, try to steal one or wait for a user to finish */
2419 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2420 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2421 lru_list) {
2422 obj = reg->obj;
2423 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2424
2425 if (obj_priv->pin_count)
2426 continue;
2427
2428 /* found one! */
2429 i = obj_priv->fence_reg;
2430 break;
2431 }
2432
2433 BUG_ON(i == I915_FENCE_REG_NONE);
2434
2435 /* We only have a reference on obj from the active list. put_fence_reg
2436 * might drop that one, causing a use-after-free in it. So hold a
2437 * private reference to obj like the other callers of put_fence_reg
2438 * (set_tiling ioctl) do. */
2439 drm_gem_object_reference(obj);
2440 ret = i915_gem_object_put_fence_reg(obj);
2441 drm_gem_object_unreference(obj);
2442 if (ret != 0)
2443 return ret;
2444
2445 return i;
2446}
2447
de151cf6
JB		 2448/**
2449 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2450 * @obj: object to map through a fence reg
2451 *
2452 * When mapping objects through the GTT, userspace wants to be able to write
2453 * to them without having to worry about swizzling if the object is tiled.
2454 *
2455 * This function walks the fence regs looking for a free one for @obj,
2456 * stealing one if it can't find any.
2457 *
2458 * It then sets up the reg based on the object's properties: address, pitch
2459 * and tiling format.
2460 */
8c4b8c3f
CW		 2461int
2462i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2463{
2464 struct drm_device *dev = obj->dev;
79e53945 2465 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2466 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2467 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2468 int ret;
de151cf6 2469
a09ba7fa
EA		 2470 /* Just update our place in the LRU if our fence is getting used. */
2471 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2472 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2473 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2474 return 0;
2475 }
2476
de151cf6
JB		 2477 switch (obj_priv->tiling_mode) {
2478 case I915_TILING_NONE:
2479 WARN(1, "allocating a fence for non-tiled object?\n");
2480 break;
2481 case I915_TILING_X:
0f973f27
JB		 2482 if (!obj_priv->stride)
2483 return -EINVAL;
2484 WARN((obj_priv->stride & (512 - 1)),
2485 "object 0x%08x is X tiled but has non-512B pitch\n",
2486 obj_priv->gtt_offset);
de151cf6
JB		 2487 break;
2488 case I915_TILING_Y:
0f973f27
JB		 2489 if (!obj_priv->stride)
2490 return -EINVAL;
2491 WARN((obj_priv->stride & (128 - 1)),
2492 "object 0x%08x is Y tiled but has non-128B pitch\n",
2493 obj_priv->gtt_offset);
de151cf6
JB		 2494 break;
2495 }
2496
ae3db24a
DV		 2497 ret = i915_find_fence_reg(dev);
2498 if (ret < 0)
2499 return ret;
de151cf6 2500
ae3db24a
DV		 2501 obj_priv->fence_reg = ret;
2502 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2503 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2504
de151cf6
JB		 2505 reg->obj = obj;
2506
4e901fdc
EA		 2507 if (IS_GEN6(dev))
2508 sandybridge_write_fence_reg(reg);
2509 else if (IS_I965G(dev))
de151cf6
JB		 2510 i965_write_fence_reg(reg);
2511 else if (IS_I9XX(dev))
2512 i915_write_fence_reg(reg);
2513 else
2514 i830_write_fence_reg(reg);
d9ddcb96 2515
ae3db24a
DV		 2516 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2517 obj_priv->tiling_mode);
1c5d22f7 2518
d9ddcb96 2519 return 0;
de151cf6
JB		 2520}
2521
2522/**
2523 * i915_gem_clear_fence_reg - clear out fence register info
2524 * @obj: object to clear
2525 *
2526 * Zeroes out the fence register itself and clears out the associated
2527 * data structures in dev_priv and obj_priv.
2528 */
2529static void
2530i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2531{
2532 struct drm_device *dev = obj->dev;
79e53945 2533 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2534 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2535 struct drm_i915_fence_reg *reg =
2536 &dev_priv->fence_regs[obj_priv->fence_reg];
de151cf6 2537
4e901fdc
EA		 2538 if (IS_GEN6(dev)) {
2539 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2540 (obj_priv->fence_reg * 8), 0);
2541 } else if (IS_I965G(dev)) {
de151cf6 2542 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2543 } else {
dc529a4f
EA		 2544 uint32_t fence_reg;
2545
2546 if (obj_priv->fence_reg < 8)
2547 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2548 else
2549 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2550 8) * 4;
2551
2552 I915_WRITE(fence_reg, 0);
2553 }
de151cf6 2554
007cc8ac 2555 reg->obj = NULL;
de151cf6 2556 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2557 list_del_init(&reg->lru_list);
de151cf6
JB		 2558}
2559
52dc7d32
CW		 2560/**
2561 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2562 * to the buffer to finish, and then resets the fence register.
2563 * @obj: tiled object holding a fence register.
2564 *
2565 * Zeroes out the fence register itself and clears out the associated
2566 * data structures in dev_priv and obj_priv.
2567 */
2568int
2569i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2570{
2571 struct drm_device *dev = obj->dev;
23010e43 2572 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2573
2574 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2575 return 0;
2576
10ae9bd2
DV		 2577 /* If we've changed tiling, GTT-mappings of the object
2578 * need to re-fault to ensure that the correct fence register
2579 * setup is in place.
2580 */
2581 i915_gem_release_mmap(obj);
2582
52dc7d32
CW		 2583 /* On the i915, GPU access to tiled buffers is via a fence,
2584 * therefore we must wait for any outstanding access to complete
2585 * before clearing the fence.
2586 */
2587 if (!IS_I965G(dev)) {
2588 int ret;
2589
2dafb1e0
CW		 2590 ret = i915_gem_object_flush_gpu_write_domain(obj);
2591 if (ret != 0)
2592 return ret;
2593
52dc7d32
CW		 2594 ret = i915_gem_object_wait_rendering(obj);
2595 if (ret != 0)
2596 return ret;
2597 }
2598
4a726612 2599 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2600 i915_gem_clear_fence_reg (obj);
2601
2602 return 0;
2603}
2604
673a394b
EA		 2605/**
2606 * Finds free space in the GTT aperture and binds the object there.
2607 */
2608static int
2609i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2610{
2611 struct drm_device *dev = obj->dev;
2612 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2613 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2614 struct drm_mm_node *free_space;
4bdadb97 2615 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2616 int ret;
673a394b 2617
bb6baf76 2618 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2619 DRM_ERROR("Attempting to bind a purgeable object\n");
2620 return -EINVAL;
2621 }
2622
673a394b 2623 if (alignment == 0)
0f973f27 2624 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2625 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2626 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2627 return -EINVAL;
2628 }
2629
654fc607
CW		 2630 /* If the object is bigger than the entire aperture, reject it early
2631 * before evicting everything in a vain attempt to find space.
2632 */
2633 if (obj->size > dev->gtt_total) {
2634 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2635 return -E2BIG;
2636 }
2637
673a394b
EA		 2638 search_free:
2639 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2640 obj->size, alignment, 0);
2641 if (free_space != NULL) {
2642 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2643 alignment);
db3307a9 2644 if (obj_priv->gtt_space != NULL)
673a394b 2645 obj_priv->gtt_offset = obj_priv->gtt_space->start;
673a394b
EA		 2646 }
2647 if (obj_priv->gtt_space == NULL) {
2648 /* If the gtt is empty and we're still having trouble
2649 * fitting our object in, we're out of memory.
2650 */
2651#if WATCH_LRU
2652 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2653#endif
07f73f69 2654 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2655 if (ret)
673a394b 2656 return ret;
9731129c 2657
673a394b
EA		 2658 goto search_free;
2659 }
2660
2661#if WATCH_BUF
cfd43c02 2662 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2663 obj->size, obj_priv->gtt_offset);
2664#endif
4bdadb97 2665 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2666 if (ret) {
2667 drm_mm_put_block(obj_priv->gtt_space);
2668 obj_priv->gtt_space = NULL;
07f73f69
CW		 2669
2670 if (ret == -ENOMEM) {
2671 /* first try to clear up some space from the GTT */
2672 ret = i915_gem_evict_something(dev, obj->size);
2673 if (ret) {
07f73f69 2674 /* now try to shrink everyone else */
4bdadb97
CW		 2675 if (gfpmask) {
2676 gfpmask = 0;
2677 goto search_free;
07f73f69
CW		 2678 }
2679
2680 return ret;
2681 }
2682
2683 goto search_free;
2684 }
2685
673a394b
EA		 2686 return ret;
2687 }
2688
673a394b
EA		 2689 /* Create an AGP memory structure pointing at our pages, and bind it
2690 * into the GTT.
2691 */
2692 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2693 obj_priv->pages,
07f73f69 2694 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2695 obj_priv->gtt_offset,
2696 obj_priv->agp_type);
673a394b 2697 if (obj_priv->agp_mem == NULL) {
856fa198 2698 i915_gem_object_put_pages(obj);
673a394b
EA		 2699 drm_mm_put_block(obj_priv->gtt_space);
2700 obj_priv->gtt_space = NULL;
07f73f69
CW		 2701
2702 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2703 if (ret)
07f73f69 2704 return ret;
07f73f69
CW		 2705
2706 goto search_free;
673a394b
EA		 2707 }
2708 atomic_inc(&dev->gtt_count);
2709 atomic_add(obj->size, &dev->gtt_memory);
2710
2711 /* Assert that the object is not currently in any GPU domain. As it
2712 * wasn't in the GTT, there shouldn't be any way it could have been in
2713 * a GPU cache
2714 */
21d509e3
CW		 2715 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2716 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2717
1c5d22f7
CW		 2718 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2719
673a394b
EA		 2720 return 0;
2721}
2722
2723void
2724i915_gem_clflush_object(struct drm_gem_object *obj)
2725{
23010e43 2726 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2727
2728 /* If we don't have a page list set up, then we're not pinned
2729 * to GPU, and we can ignore the cache flush because it'll happen
2730 * again at bind time.
2731 */
856fa198 2732 if (obj_priv->pages == NULL)
673a394b
EA		 2733 return;
2734
1c5d22f7 2735 trace_i915_gem_object_clflush(obj);
cfa16a0d 2736
856fa198 2737 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2738}
2739
e47c68e9 2740/** Flushes any GPU write domain for the object if it's dirty. */
2dafb1e0 2741static int
e47c68e9
EA		 2742i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2743{
2744 struct drm_device *dev = obj->dev;
1c5d22f7 2745 uint32_t old_write_domain;
852835f3 2746 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
e47c68e9
EA		 2747
2748 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2dafb1e0 2749 return 0;
e47c68e9
EA		 2750
2751 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2752 old_write_domain = obj->write_domain;
e47c68e9 2753 i915_gem_flush(dev, 0, obj->write_domain);
2dafb1e0
CW		 2754 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2755 return -ENOMEM;
1c5d22f7
CW		 2756
2757 trace_i915_gem_object_change_domain(obj,
2758 obj->read_domains,
2759 old_write_domain);
2dafb1e0 2760 return 0;
e47c68e9
EA		 2761}
2762
2763/** Flushes the GTT write domain for the object if it's dirty. */
2764static void
2765i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2766{
1c5d22f7
CW		 2767 uint32_t old_write_domain;
2768
e47c68e9
EA		 2769 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2770 return;
2771
2772 /* No actual flushing is required for the GTT write domain. Writes
2773 * to it immediately go to main memory as far as we know, so there's
2774 * no chipset flush. It also doesn't land in render cache.
2775 */
1c5d22f7 2776 old_write_domain = obj->write_domain;
e47c68e9 2777 obj->write_domain = 0;
1c5d22f7
CW		 2778
2779 trace_i915_gem_object_change_domain(obj,
2780 obj->read_domains,
2781 old_write_domain);
e47c68e9
EA		 2782}
2783
2784/** Flushes the CPU write domain for the object if it's dirty. */
2785static void
2786i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2787{
2788 struct drm_device *dev = obj->dev;
1c5d22f7 2789 uint32_t old_write_domain;
e47c68e9
EA		 2790
2791 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2792 return;
2793
2794 i915_gem_clflush_object(obj);
2795 drm_agp_chipset_flush(dev);
1c5d22f7 2796 old_write_domain = obj->write_domain;
e47c68e9 2797 obj->write_domain = 0;
1c5d22f7
CW		 2798
2799 trace_i915_gem_object_change_domain(obj,
2800 obj->read_domains,
2801 old_write_domain);
e47c68e9
EA		 2802}
2803
2dafb1e0 2804int
6b95a207
KH		 2805i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2806{
2dafb1e0
CW		 2807 int ret = 0;
2808
6b95a207
KH		 2809 switch (obj->write_domain) {
2810 case I915_GEM_DOMAIN_GTT:
2811 i915_gem_object_flush_gtt_write_domain(obj);
2812 break;
2813 case I915_GEM_DOMAIN_CPU:
2814 i915_gem_object_flush_cpu_write_domain(obj);
2815 break;
2816 default:
2dafb1e0 2817 ret = i915_gem_object_flush_gpu_write_domain(obj);
6b95a207
KH		 2818 break;
2819 }
2dafb1e0
CW		 2820
2821 return ret;
6b95a207
KH		 2822}
2823
2ef7eeaa
EA		 2824/**
2825 * Moves a single object to the GTT read, and possibly write domain.
2826 *
2827 * This function returns when the move is complete, including waiting on
2828 * flushes to occur.
2829 */
79e53945 2830int
2ef7eeaa
EA		 2831i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2832{
23010e43 2833 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2834 uint32_t old_write_domain, old_read_domains;
e47c68e9 2835 int ret;
2ef7eeaa 2836
02354392
EA		 2837 /* Not valid to be called on unbound objects. */
2838 if (obj_priv->gtt_space == NULL)
2839 return -EINVAL;
2840
2dafb1e0
CW		 2841 ret = i915_gem_object_flush_gpu_write_domain(obj);
2842 if (ret != 0)
2843 return ret;
2844
e47c68e9
EA		 2845 /* Wait on any GPU rendering and flushing to occur. */
2846 ret = i915_gem_object_wait_rendering(obj);
2847 if (ret != 0)
2848 return ret;
2849
1c5d22f7
CW		 2850 old_write_domain = obj->write_domain;
2851 old_read_domains = obj->read_domains;
2852
e47c68e9
EA		 2853 /* If we're writing through the GTT domain, then CPU and GPU caches
2854 * will need to be invalidated at next use.
2ef7eeaa 2855 */
e47c68e9
EA		 2856 if (write)
2857 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2858
e47c68e9 2859 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2860
e47c68e9
EA		 2861 /* It should now be out of any other write domains, and we can update
2862 * the domain values for our changes.
2863 */
2864 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2865 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2866 if (write) {
2867 obj->write_domain = I915_GEM_DOMAIN_GTT;
2868 obj_priv->dirty = 1;
2ef7eeaa
EA		 2869 }
2870
1c5d22f7
CW		 2871 trace_i915_gem_object_change_domain(obj,
2872 old_read_domains,
2873 old_write_domain);
2874
e47c68e9
EA		 2875 return 0;
2876}
2877
b9241ea3
ZW		 2878/*
2879 * Prepare buffer for display plane. Use uninterruptible for possible flush
2880 * wait, as in modesetting process we're not supposed to be interrupted.
2881 */
2882int
2883i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2884{
2885 struct drm_device *dev = obj->dev;
23010e43 2886 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2887 uint32_t old_write_domain, old_read_domains;
2888 int ret;
2889
2890 /* Not valid to be called on unbound objects. */
2891 if (obj_priv->gtt_space == NULL)
2892 return -EINVAL;
2893
2dafb1e0
CW		 2894 ret = i915_gem_object_flush_gpu_write_domain(obj);
2895 if (ret)
2896 return ret;
b9241ea3
ZW		 2897
2898 /* Wait on any GPU rendering and flushing to occur. */
2899 if (obj_priv->active) {
2900#if WATCH_BUF
2901 DRM_INFO("%s: object %p wait for seqno %08x\n",
2902 __func__, obj, obj_priv->last_rendering_seqno);
2903#endif
852835f3
ZN		 2904 ret = i915_do_wait_request(dev,
2905 obj_priv->last_rendering_seqno,
2906 0,
2907 obj_priv->ring);
b9241ea3
ZW		 2908 if (ret != 0)
2909 return ret;
2910 }
2911
b118c1e3
CW		 2912 i915_gem_object_flush_cpu_write_domain(obj);
2913
b9241ea3
ZW		 2914 old_write_domain = obj->write_domain;
2915 old_read_domains = obj->read_domains;
2916
b9241ea3
ZW		 2917 /* It should now be out of any other write domains, and we can update
2918 * the domain values for our changes.
2919 */
2920 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
b118c1e3 2921 obj->read_domains = I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 2922 obj->write_domain = I915_GEM_DOMAIN_GTT;
2923 obj_priv->dirty = 1;
2924
2925 trace_i915_gem_object_change_domain(obj,
2926 old_read_domains,
2927 old_write_domain);
2928
2929 return 0;
2930}
2931
e47c68e9
EA		 2932/**
2933 * Moves a single object to the CPU read, and possibly write domain.
2934 *
2935 * This function returns when the move is complete, including waiting on
2936 * flushes to occur.
2937 */
2938static int
2939i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2940{
1c5d22f7 2941 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2942 int ret;
2943
2dafb1e0
CW		 2944 ret = i915_gem_object_flush_gpu_write_domain(obj);
2945 if (ret)
2946 return ret;
2947
2ef7eeaa 2948 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2949 ret = i915_gem_object_wait_rendering(obj);
2950 if (ret != 0)
2951 return ret;
2ef7eeaa 2952
e47c68e9 2953 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2954
e47c68e9
EA		 2955 /* If we have a partially-valid cache of the object in the CPU,
2956 * finish invalidating it and free the per-page flags.
2ef7eeaa 2957 */
e47c68e9 2958 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2959
1c5d22f7
CW		 2960 old_write_domain = obj->write_domain;
2961 old_read_domains = obj->read_domains;
2962
e47c68e9
EA		 2963 /* Flush the CPU cache if it's still invalid. */
2964 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2965 i915_gem_clflush_object(obj);
2ef7eeaa 2966
e47c68e9 2967 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2968 }
2969
2970 /* It should now be out of any other write domains, and we can update
2971 * the domain values for our changes.
2972 */
e47c68e9
EA		 2973 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2974
2975 /* If we're writing through the CPU, then the GPU read domains will
2976 * need to be invalidated at next use.
2977 */
2978 if (write) {
2979 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2980 obj->write_domain = I915_GEM_DOMAIN_CPU;
2981 }
2ef7eeaa 2982
1c5d22f7
CW		 2983 trace_i915_gem_object_change_domain(obj,
2984 old_read_domains,
2985 old_write_domain);
2986
2ef7eeaa
EA		 2987 return 0;
2988}
2989
673a394b
EA		 2990/*
2991 * Set the next domain for the specified object. This
2992 * may not actually perform the necessary flushing/invaliding though,
2993 * as that may want to be batched with other set_domain operations
2994 *
2995 * This is (we hope) the only really tricky part of gem. The goal
2996 * is fairly simple -- track which caches hold bits of the object
2997 * and make sure they remain coherent. A few concrete examples may
2998 * help to explain how it works. For shorthand, we use the notation
2999 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3000 * a pair of read and write domain masks.
3001 *
3002 * Case 1: the batch buffer
3003 *
3004 * 1. Allocated
3005 * 2. Written by CPU
3006 * 3. Mapped to GTT
3007 * 4. Read by GPU
3008 * 5. Unmapped from GTT
3009 * 6. Freed
3010 *
3011 * Let's take these a step at a time
3012 *
3013 * 1. Allocated
3014 * Pages allocated from the kernel may still have
3015 * cache contents, so we set them to (CPU, CPU) always.
3016 * 2. Written by CPU (using pwrite)
3017 * The pwrite function calls set_domain (CPU, CPU) and
3018 * this function does nothing (as nothing changes)
3019 * 3. Mapped by GTT
3020 * This function asserts that the object is not
3021 * currently in any GPU-based read or write domains
3022 * 4. Read by GPU
3023 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3024 * As write_domain is zero, this function adds in the
3025 * current read domains (CPU+COMMAND, 0).
3026 * flush_domains is set to CPU.
3027 * invalidate_domains is set to COMMAND
3028 * clflush is run to get data out of the CPU caches
3029 * then i915_dev_set_domain calls i915_gem_flush to
3030 * emit an MI_FLUSH and drm_agp_chipset_flush
3031 * 5. Unmapped from GTT
3032 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3033 * flush_domains and invalidate_domains end up both zero
3034 * so no flushing/invalidating happens
3035 * 6. Freed
3036 * yay, done
3037 *
3038 * Case 2: The shared render buffer
3039 *
3040 * 1. Allocated
3041 * 2. Mapped to GTT
3042 * 3. Read/written by GPU
3043 * 4. set_domain to (CPU,CPU)
3044 * 5. Read/written by CPU
3045 * 6. Read/written by GPU
3046 *
3047 * 1. Allocated
3048 * Same as last example, (CPU, CPU)
3049 * 2. Mapped to GTT
3050 * Nothing changes (assertions find that it is not in the GPU)
3051 * 3. Read/written by GPU
3052 * execbuffer calls set_domain (RENDER, RENDER)
3053 * flush_domains gets CPU
3054 * invalidate_domains gets GPU
3055 * clflush (obj)
3056 * MI_FLUSH and drm_agp_chipset_flush
3057 * 4. set_domain (CPU, CPU)
3058 * flush_domains gets GPU
3059 * invalidate_domains gets CPU
3060 * wait_rendering (obj) to make sure all drawing is complete.
3061 * This will include an MI_FLUSH to get the data from GPU
3062 * to memory
3063 * clflush (obj) to invalidate the CPU cache
3064 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3065 * 5. Read/written by CPU
3066 * cache lines are loaded and dirtied
3067 * 6. Read written by GPU
3068 * Same as last GPU access
3069 *
3070 * Case 3: The constant buffer
3071 *
3072 * 1. Allocated
3073 * 2. Written by CPU
3074 * 3. Read by GPU
3075 * 4. Updated (written) by CPU again
3076 * 5. Read by GPU
3077 *
3078 * 1. Allocated
3079 * (CPU, CPU)
3080 * 2. Written by CPU
3081 * (CPU, CPU)
3082 * 3. Read by GPU
3083 * (CPU+RENDER, 0)
3084 * flush_domains = CPU
3085 * invalidate_domains = RENDER
3086 * clflush (obj)
3087 * MI_FLUSH
3088 * drm_agp_chipset_flush
3089 * 4. Updated (written) by CPU again
3090 * (CPU, CPU)
3091 * flush_domains = 0 (no previous write domain)
3092 * invalidate_domains = 0 (no new read domains)
3093 * 5. Read by GPU
3094 * (CPU+RENDER, 0)
3095 * flush_domains = CPU
3096 * invalidate_domains = RENDER
3097 * clflush (obj)
3098 * MI_FLUSH
3099 * drm_agp_chipset_flush
3100 */
c0d90829 3101static void
8b0e378a 3102i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3103{
3104 struct drm_device *dev = obj->dev;
23010e43 3105 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3106 uint32_t invalidate_domains = 0;
3107 uint32_t flush_domains = 0;
1c5d22f7 3108 uint32_t old_read_domains;
e47c68e9 3109
8b0e378a
EA		 3110 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3111 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3112
652c393a
JB		 3113 intel_mark_busy(dev, obj);
3114
673a394b
EA		 3115#if WATCH_BUF
3116 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3117 __func__, obj,
8b0e378a
EA		 3118 obj->read_domains, obj->pending_read_domains,
3119 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3120#endif
3121 /*
3122 * If the object isn't moving to a new write domain,
3123 * let the object stay in multiple read domains
3124 */
8b0e378a
EA		 3125 if (obj->pending_write_domain == 0)
3126 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3127 else
3128 obj_priv->dirty = 1;
3129
3130 /*
3131 * Flush the current write domain if
3132 * the new read domains don't match. Invalidate
3133 * any read domains which differ from the old
3134 * write domain
3135 */
8b0e378a
EA		 3136 if (obj->write_domain &&
3137 obj->write_domain != obj->pending_read_domains) {
673a394b 3138 flush_domains |= obj->write_domain;
8b0e378a
EA		 3139 invalidate_domains |=
3140 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3141 }
3142 /*
3143 * Invalidate any read caches which may have
3144 * stale data. That is, any new read domains.
3145 */
8b0e378a 3146 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3147 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3148#if WATCH_BUF
3149 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3150 __func__, flush_domains, invalidate_domains);
3151#endif
673a394b
EA		 3152 i915_gem_clflush_object(obj);
3153 }
3154
1c5d22f7
CW		 3155 old_read_domains = obj->read_domains;
3156
efbeed96
EA		 3157 /* The actual obj->write_domain will be updated with
3158 * pending_write_domain after we emit the accumulated flush for all
3159 * of our domain changes in execbuffers (which clears objects'
3160 * write_domains). So if we have a current write domain that we
3161 * aren't changing, set pending_write_domain to that.
3162 */
3163 if (flush_domains == 0 && obj->pending_write_domain == 0)
3164 obj->pending_write_domain = obj->write_domain;
8b0e378a 3165 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3166
3167 dev->invalidate_domains |= invalidate_domains;
3168 dev->flush_domains |= flush_domains;
3169#if WATCH_BUF
3170 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3171 __func__,
3172 obj->read_domains, obj->write_domain,
3173 dev->invalidate_domains, dev->flush_domains);
3174#endif
1c5d22f7
CW		 3175
3176 trace_i915_gem_object_change_domain(obj,
3177 old_read_domains,
3178 obj->write_domain);
673a394b
EA		 3179}
3180
3181/**
e47c68e9 3182 * Moves the object from a partially CPU read to a full one.
673a394b 3183 *
e47c68e9
EA		 3184 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3185 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3186 */
e47c68e9
EA		 3187static void
3188i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3189{
23010e43 3190 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3191
e47c68e9
EA		 3192 if (!obj_priv->page_cpu_valid)
3193 return;
3194
3195 /* If we're partially in the CPU read domain, finish moving it in.
3196 */
3197 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3198 int i;
3199
3200 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3201 if (obj_priv->page_cpu_valid[i])
3202 continue;
856fa198 3203 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3204 }
e47c68e9
EA		 3205 }
3206
3207 /* Free the page_cpu_valid mappings which are now stale, whether
3208 * or not we've got I915_GEM_DOMAIN_CPU.
3209 */
9a298b2a 3210 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3211 obj_priv->page_cpu_valid = NULL;
3212}
3213
3214/**
3215 * Set the CPU read domain on a range of the object.
3216 *
3217 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3218 * not entirely valid. The page_cpu_valid member of the object flags which
3219 * pages have been flushed, and will be respected by
3220 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3221 * of the whole object.
3222 *
3223 * This function returns when the move is complete, including waiting on
3224 * flushes to occur.
3225 */
3226static int
3227i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3228 uint64_t offset, uint64_t size)
3229{
23010e43 3230 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3231 uint32_t old_read_domains;
e47c68e9 3232 int i, ret;
673a394b 3233
e47c68e9
EA		 3234 if (offset == 0 && size == obj->size)
3235 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3236
2dafb1e0
CW		 3237 ret = i915_gem_object_flush_gpu_write_domain(obj);
3238 if (ret)
3239 return ret;
3240
e47c68e9 3241 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3242 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3243 if (ret != 0)
6a47baa6 3244 return ret;
e47c68e9
EA		 3245 i915_gem_object_flush_gtt_write_domain(obj);
3246
3247 /* If we're already fully in the CPU read domain, we're done. */
3248 if (obj_priv->page_cpu_valid == NULL &&
3249 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3250 return 0;
673a394b 3251
e47c68e9
EA		 3252 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3253 * newly adding I915_GEM_DOMAIN_CPU
3254 */
673a394b 3255 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3256 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3257 GFP_KERNEL);
e47c68e9
EA		 3258 if (obj_priv->page_cpu_valid == NULL)
3259 return -ENOMEM;
3260 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3261 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3262
3263 /* Flush the cache on any pages that are still invalid from the CPU's
3264 * perspective.
3265 */
e47c68e9
EA		 3266 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3267 i++) {
673a394b
EA		 3268 if (obj_priv->page_cpu_valid[i])
3269 continue;
3270
856fa198 3271 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3272
3273 obj_priv->page_cpu_valid[i] = 1;
3274 }
3275
e47c68e9
EA		 3276 /* It should now be out of any other write domains, and we can update
3277 * the domain values for our changes.
3278 */
3279 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3280
1c5d22f7 3281 old_read_domains = obj->read_domains;
e47c68e9
EA		 3282 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3283
1c5d22f7
CW		 3284 trace_i915_gem_object_change_domain(obj,
3285 old_read_domains,
3286 obj->write_domain);
3287
673a394b
EA		 3288 return 0;
3289}
3290
673a394b
EA		 3291/**
3292 * Pin an object to the GTT and evaluate the relocations landing in it.
3293 */
3294static int
3295i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3296 struct drm_file *file_priv,
76446cac 3297 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3298 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3299{
3300 struct drm_device *dev = obj->dev;
0839ccb8 3301 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3302 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3303 int i, ret;
0839ccb8 3304 void __iomem *reloc_page;
76446cac
JB		 3305 bool need_fence;
3306
3307 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3308 obj_priv->tiling_mode != I915_TILING_NONE;
3309
3310 /* Check fence reg constraints and rebind if necessary */
808b24d6
CW		 3311 if (need_fence &&
3312 !i915_gem_object_fence_offset_ok(obj,
3313 obj_priv->tiling_mode)) {
3314 ret = i915_gem_object_unbind(obj);
3315 if (ret)
3316 return ret;
3317 }
673a394b
EA		 3318
3319 /* Choose the GTT offset for our buffer and put it there. */
3320 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3321 if (ret)
3322 return ret;
3323
76446cac
JB		 3324 /*
3325 * Pre-965 chips need a fence register set up in order to
3326 * properly handle blits to/from tiled surfaces.
3327 */
3328 if (need_fence) {
3329 ret = i915_gem_object_get_fence_reg(obj);
3330 if (ret != 0) {
76446cac
JB		 3331 i915_gem_object_unpin(obj);
3332 return ret;
3333 }
3334 }
3335
673a394b
EA		 3336 entry->offset = obj_priv->gtt_offset;
3337
673a394b
EA		 3338 /* Apply the relocations, using the GTT aperture to avoid cache
3339 * flushing requirements.
3340 */
3341 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3342 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3343 struct drm_gem_object *target_obj;
3344 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3345 uint32_t reloc_val, reloc_offset;
3346 uint32_t __iomem *reloc_entry;
673a394b 3347
673a394b 3348 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3349 reloc->target_handle);
673a394b
EA		 3350 if (target_obj == NULL) {
3351 i915_gem_object_unpin(obj);
3352 return -EBADF;
3353 }
23010e43 3354 target_obj_priv = to_intel_bo(target_obj);
673a394b 3355
8542a0bb
CW		 3356#if WATCH_RELOC
3357 DRM_INFO("%s: obj %p offset %08x target %d "
3358 "read %08x write %08x gtt %08x "
3359 "presumed %08x delta %08x\n",
3360 __func__,
3361 obj,
3362 (int) reloc->offset,
3363 (int) reloc->target_handle,
3364 (int) reloc->read_domains,
3365 (int) reloc->write_domain,
3366 (int) target_obj_priv->gtt_offset,
3367 (int) reloc->presumed_offset,
3368 reloc->delta);
3369#endif
3370
673a394b
EA		 3371 /* The target buffer should have appeared before us in the
3372 * exec_object list, so it should have a GTT space bound by now.
3373 */
3374 if (target_obj_priv->gtt_space == NULL) {
3375 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3376 reloc->target_handle);
673a394b
EA		 3377 drm_gem_object_unreference(target_obj);
3378 i915_gem_object_unpin(obj);
3379 return -EINVAL;
3380 }
3381
8542a0bb 3382 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3383 if (reloc->write_domain & (reloc->write_domain - 1)) {
3384 DRM_ERROR("reloc with multiple write domains: "
3385 "obj %p target %d offset %d "
3386 "read %08x write %08x",
3387 obj, reloc->target_handle,
3388 (int) reloc->offset,
3389 reloc->read_domains,
3390 reloc->write_domain);
3391 return -EINVAL;
3392 }
40a5f0de
EA		 3393 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3394 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3395 DRM_ERROR("reloc with read/write CPU domains: "
3396 "obj %p target %d offset %d "
3397 "read %08x write %08x",
40a5f0de
EA		 3398 obj, reloc->target_handle,
3399 (int) reloc->offset,
3400 reloc->read_domains,
3401 reloc->write_domain);
491152b8
CW		 3402 drm_gem_object_unreference(target_obj);
3403 i915_gem_object_unpin(obj);
e47c68e9
EA		 3404 return -EINVAL;
3405 }
40a5f0de
EA		 3406 if (reloc->write_domain && target_obj->pending_write_domain &&
3407 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3408 DRM_ERROR("Write domain conflict: "
3409 "obj %p target %d offset %d "
3410 "new %08x old %08x\n",
40a5f0de
EA		 3411 obj, reloc->target_handle,
3412 (int) reloc->offset,
3413 reloc->write_domain,
673a394b
EA		 3414 target_obj->pending_write_domain);
3415 drm_gem_object_unreference(target_obj);
3416 i915_gem_object_unpin(obj);
3417 return -EINVAL;
3418 }
3419
40a5f0de
EA		 3420 target_obj->pending_read_domains |= reloc->read_domains;
3421 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3422
3423 /* If the relocation already has the right value in it, no
3424 * more work needs to be done.
3425 */
40a5f0de 3426 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3427 drm_gem_object_unreference(target_obj);
3428 continue;
3429 }
3430
8542a0bb
CW		 3431 /* Check that the relocation address is valid... */
3432 if (reloc->offset > obj->size - 4) {
3433 DRM_ERROR("Relocation beyond object bounds: "
3434 "obj %p target %d offset %d size %d.\n",
3435 obj, reloc->target_handle,
3436 (int) reloc->offset, (int) obj->size);
3437 drm_gem_object_unreference(target_obj);
3438 i915_gem_object_unpin(obj);
3439 return -EINVAL;
3440 }
3441 if (reloc->offset & 3) {
3442 DRM_ERROR("Relocation not 4-byte aligned: "
3443 "obj %p target %d offset %d.\n",
3444 obj, reloc->target_handle,
3445 (int) reloc->offset);
3446 drm_gem_object_unreference(target_obj);
3447 i915_gem_object_unpin(obj);
3448 return -EINVAL;
3449 }
3450
3451 /* and points to somewhere within the target object. */
3452 if (reloc->delta >= target_obj->size) {
3453 DRM_ERROR("Relocation beyond target object bounds: "
3454 "obj %p target %d delta %d size %d.\n",
3455 obj, reloc->target_handle,
3456 (int) reloc->delta, (int) target_obj->size);
3457 drm_gem_object_unreference(target_obj);
3458 i915_gem_object_unpin(obj);
3459 return -EINVAL;
3460 }
3461
2ef7eeaa
EA		 3462 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3463 if (ret != 0) {
3464 drm_gem_object_unreference(target_obj);
3465 i915_gem_object_unpin(obj);
3466 return -EINVAL;
673a394b
EA		 3467 }
3468
3469 /* Map the page containing the relocation we're going to
3470 * perform.
3471 */
40a5f0de 3472 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3473 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3474 (reloc_offset &
3475 ~(PAGE_SIZE - 1)));
3043c60c 3476 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3477 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3478 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3479
3480#if WATCH_BUF
3481 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3482 obj, (unsigned int) reloc->offset,
673a394b
EA		 3483 readl(reloc_entry), reloc_val);
3484#endif
3485 writel(reloc_val, reloc_entry);
0839ccb8 3486 io_mapping_unmap_atomic(reloc_page);
673a394b 3487
40a5f0de
EA		 3488 /* The updated presumed offset for this entry will be
3489 * copied back out to the user.
673a394b 3490 */
40a5f0de 3491 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3492
3493 drm_gem_object_unreference(target_obj);
3494 }
3495
673a394b
EA		 3496#if WATCH_BUF
3497 if (0)
3498 i915_gem_dump_object(obj, 128, __func__, ~0);
3499#endif
3500 return 0;
3501}
3502
673a394b
EA		 3503/* Throttle our rendering by waiting until the ring has completed our requests
3504 * emitted over 20 msec ago.
3505 *
b962442e
EA		 3506 * Note that if we were to use the current jiffies each time around the loop,
3507 * we wouldn't escape the function with any frames outstanding if the time to
3508 * render a frame was over 20ms.
3509 *
673a394b
EA		 3510 * This should get us reasonable parallelism between CPU and GPU but also
3511 * relatively low latency when blocking on a particular request to finish.
3512 */
3513static int
3514i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3515{
3516 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3517 int ret = 0;
b962442e 3518 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3519
3520 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3521 while (!list_empty(&i915_file_priv->mm.request_list)) {
3522 struct drm_i915_gem_request *request;
3523
3524 request = list_first_entry(&i915_file_priv->mm.request_list,
3525 struct drm_i915_gem_request,
3526 client_list);
3527
3528 if (time_after_eq(request->emitted_jiffies, recent_enough))
3529 break;
3530
852835f3 3531 ret = i915_wait_request(dev, request->seqno, request->ring);
b962442e
EA		 3532 if (ret != 0)
3533 break;
3534 }
673a394b 3535 mutex_unlock(&dev->struct_mutex);
b962442e 3536
673a394b
EA		 3537 return ret;
3538}
3539
40a5f0de 3540static int
76446cac 3541i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3542 uint32_t buffer_count,
3543 struct drm_i915_gem_relocation_entry **relocs)
3544{
3545 uint32_t reloc_count = 0, reloc_index = 0, i;
3546 int ret;
3547
3548 *relocs = NULL;
3549 for (i = 0; i < buffer_count; i++) {
3550 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3551 return -EINVAL;
3552 reloc_count += exec_list[i].relocation_count;
3553 }
3554
8e7d2b2c 3555 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3556 if (*relocs == NULL) {
3557 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3558 return -ENOMEM;
76446cac 3559 }
40a5f0de
EA		 3560
3561 for (i = 0; i < buffer_count; i++) {
3562 struct drm_i915_gem_relocation_entry __user *user_relocs;
3563
3564 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3565
3566 ret = copy_from_user(&(*relocs)[reloc_index],
3567 user_relocs,
3568 exec_list[i].relocation_count *
3569 sizeof(**relocs));
3570 if (ret != 0) {
8e7d2b2c 3571 drm_free_large(*relocs);
40a5f0de 3572 *relocs = NULL;
2bc43b5c 3573 return -EFAULT;
40a5f0de
EA		 3574 }
3575
3576 reloc_index += exec_list[i].relocation_count;
3577 }
3578
2bc43b5c 3579 return 0;
40a5f0de
EA		 3580}
3581
3582static int
76446cac 3583i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3584 uint32_t buffer_count,
3585 struct drm_i915_gem_relocation_entry *relocs)
3586{
3587 uint32_t reloc_count = 0, i;
2bc43b5c 3588 int ret = 0;
40a5f0de 3589
93533c29
CW		 3590 if (relocs == NULL)
3591 return 0;
3592
40a5f0de
EA		 3593 for (i = 0; i < buffer_count; i++) {
3594 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3595 int unwritten;
40a5f0de
EA		 3596
3597 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3598
2bc43b5c
FM		 3599 unwritten = copy_to_user(user_relocs,
3600 &relocs[reloc_count],
3601 exec_list[i].relocation_count *
3602 sizeof(*relocs));
3603
3604 if (unwritten) {
3605 ret = -EFAULT;
3606 goto err;
40a5f0de
EA		 3607 }
3608
3609 reloc_count += exec_list[i].relocation_count;
3610 }
3611
2bc43b5c 3612err:
8e7d2b2c 3613 drm_free_large(relocs);
40a5f0de
EA		 3614
3615 return ret;
3616}
3617
83d60795 3618static int
76446cac 3619i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3620 uint64_t exec_offset)
3621{
3622 uint32_t exec_start, exec_len;
3623
3624 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3625 exec_len = (uint32_t) exec->batch_len;
3626
3627 if ((exec_start | exec_len) & 0x7)
3628 return -EINVAL;
3629
3630 if (!exec_start)
3631 return -EINVAL;
3632
3633 return 0;
3634}
3635
6b95a207
KH		 3636static int
3637i915_gem_wait_for_pending_flip(struct drm_device *dev,
3638 struct drm_gem_object **object_list,
3639 int count)
3640{
3641 drm_i915_private_t *dev_priv = dev->dev_private;
3642 struct drm_i915_gem_object *obj_priv;
3643 DEFINE_WAIT(wait);
3644 int i, ret = 0;
3645
3646 for (;;) {
3647 prepare_to_wait(&dev_priv->pending_flip_queue,
3648 &wait, TASK_INTERRUPTIBLE);
3649 for (i = 0; i < count; i++) {
23010e43 3650 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3651 if (atomic_read(&obj_priv->pending_flip) > 0)
3652 break;
3653 }
3654 if (i == count)
3655 break;
3656
3657 if (!signal_pending(current)) {
3658 mutex_unlock(&dev->struct_mutex);
3659 schedule();
3660 mutex_lock(&dev->struct_mutex);
3661 continue;
3662 }
3663 ret = -ERESTARTSYS;
3664 break;
3665 }
3666 finish_wait(&dev_priv->pending_flip_queue, &wait);
3667
3668 return ret;
3669}
3670
43b27f40 3671
673a394b 3672int
76446cac
JB		 3673i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3674 struct drm_file *file_priv,
3675 struct drm_i915_gem_execbuffer2 *args,
3676 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3677{
3678 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3679 struct drm_gem_object **object_list = NULL;
3680 struct drm_gem_object *batch_obj;
b70d11da 3681 struct drm_i915_gem_object *obj_priv;
201361a5 3682 struct drm_clip_rect *cliprects = NULL;
93533c29 3683 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3684 int ret = 0, ret2, i, pinned = 0;
673a394b 3685 uint64_t exec_offset;
40a5f0de 3686 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3687 int pin_tries, flips;
673a394b 3688
852835f3
ZN		 3689 struct intel_ring_buffer *ring = NULL;
3690
673a394b
EA		 3691#if WATCH_EXEC
3692 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3693 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3694#endif
d1b851fc
ZN		 3695 if (args->flags & I915_EXEC_BSD) {
3696 if (!HAS_BSD(dev)) {
3697 DRM_ERROR("execbuf with wrong flag\n");
3698 return -EINVAL;
3699 }
3700 ring = &dev_priv->bsd_ring;
3701 } else {
3702 ring = &dev_priv->render_ring;
3703 }
3704
673a394b 3705
4f481ed2
EA		 3706 if (args->buffer_count < 1) {
3707 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3708 return -EINVAL;
3709 }
c8e0f93a 3710 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3711 if (object_list == NULL) {
3712 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3713 args->buffer_count);
3714 ret = -ENOMEM;
3715 goto pre_mutex_err;
3716 }
673a394b 3717
201361a5 3718 if (args->num_cliprects != 0) {
9a298b2a
EA		 3719 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3720 GFP_KERNEL);
a40e8d31
OA		 3721 if (cliprects == NULL) {
3722 ret = -ENOMEM;
201361a5 3723 goto pre_mutex_err;
a40e8d31 3724 }
201361a5
EA		 3725
3726 ret = copy_from_user(cliprects,
3727 (struct drm_clip_rect __user *)
3728 (uintptr_t) args->cliprects_ptr,
3729 sizeof(*cliprects) * args->num_cliprects);
3730 if (ret != 0) {
3731 DRM_ERROR("copy %d cliprects failed: %d\n",
3732 args->num_cliprects, ret);
3733 goto pre_mutex_err;
3734 }
3735 }
3736
40a5f0de
EA		 3737 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3738 &relocs);
3739 if (ret != 0)
3740 goto pre_mutex_err;
3741
673a394b
EA		 3742 mutex_lock(&dev->struct_mutex);
3743
3744 i915_verify_inactive(dev, __FILE__, __LINE__);
3745
ba1234d1 3746 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3747 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3748 ret = -EIO;
3749 goto pre_mutex_err;
673a394b
EA		 3750 }
3751
3752 if (dev_priv->mm.suspended) {
673a394b 3753 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3754 ret = -EBUSY;
3755 goto pre_mutex_err;
673a394b
EA		 3756 }
3757
ac94a962 3758 /* Look up object handles */
6b95a207 3759 flips = 0;
673a394b
EA		 3760 for (i = 0; i < args->buffer_count; i++) {
3761 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3762 exec_list[i].handle);
3763 if (object_list[i] == NULL) {
3764 DRM_ERROR("Invalid object handle %d at index %d\n",
3765 exec_list[i].handle, i);
0ce907f8
CW		 3766 /* prevent error path from reading uninitialized data */
3767 args->buffer_count = i + 1;
673a394b
EA		 3768 ret = -EBADF;
3769 goto err;
3770 }
b70d11da 3771
23010e43 3772 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3773 if (obj_priv->in_execbuffer) {
3774 DRM_ERROR("Object %p appears more than once in object list\n",
3775 object_list[i]);
0ce907f8
CW		 3776 /* prevent error path from reading uninitialized data */
3777 args->buffer_count = i + 1;
b70d11da
KH		 3778 ret = -EBADF;
3779 goto err;
3780 }
3781 obj_priv->in_execbuffer = true;
6b95a207
KH		 3782 flips += atomic_read(&obj_priv->pending_flip);
3783 }
3784
3785 if (flips > 0) {
3786 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3787 args->buffer_count);
3788 if (ret)
3789 goto err;
ac94a962 3790 }
673a394b 3791
ac94a962
KP		 3792 /* Pin and relocate */
3793 for (pin_tries = 0; ; pin_tries++) {
3794 ret = 0;
40a5f0de
EA		 3795 reloc_index = 0;
3796
ac94a962
KP		 3797 for (i = 0; i < args->buffer_count; i++) {
3798 object_list[i]->pending_read_domains = 0;
3799 object_list[i]->pending_write_domain = 0;
3800 ret = i915_gem_object_pin_and_relocate(object_list[i],
3801 file_priv,
40a5f0de
EA		 3802 &exec_list[i],
3803 &relocs[reloc_index]);
ac94a962
KP		 3804 if (ret)
3805 break;
3806 pinned = i + 1;
40a5f0de 3807 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3808 }
3809 /* success */
3810 if (ret == 0)
3811 break;
3812
3813 /* error other than GTT full, or we've already tried again */
2939e1f5 3814 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3815 if (ret != -ERESTARTSYS) {
3816 unsigned long long total_size = 0;
3d1cc470
CW		 3817 int num_fences = 0;
3818 for (i = 0; i < args->buffer_count; i++) {
43b27f40 3819 obj_priv = to_intel_bo(object_list[i]);
3d1cc470 3820
07f73f69 3821 total_size += object_list[i]->size;
3d1cc470
CW		 3822 num_fences +=
3823 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3824 obj_priv->tiling_mode != I915_TILING_NONE;
3825 }
3826 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
07f73f69 3827 pinned+1, args->buffer_count,
3d1cc470
CW		 3828 total_size, num_fences,
3829 ret);
07f73f69
CW		 3830 DRM_ERROR("%d objects [%d pinned], "
3831 "%d object bytes [%d pinned], "
3832 "%d/%d gtt bytes\n",
3833 atomic_read(&dev->object_count),
3834 atomic_read(&dev->pin_count),
3835 atomic_read(&dev->object_memory),
3836 atomic_read(&dev->pin_memory),
3837 atomic_read(&dev->gtt_memory),
3838 dev->gtt_total);
3839 }
673a394b
EA		 3840 goto err;
3841 }
ac94a962
KP		 3842
3843 /* unpin all of our buffers */
3844 for (i = 0; i < pinned; i++)
3845 i915_gem_object_unpin(object_list[i]);
b1177636 3846 pinned = 0;
ac94a962
KP		 3847
3848 /* evict everyone we can from the aperture */
3849 ret = i915_gem_evict_everything(dev);
07f73f69 3850 if (ret && ret != -ENOSPC)
ac94a962 3851 goto err;
673a394b
EA		 3852 }
3853
3854 /* Set the pending read domains for the batch buffer to COMMAND */
3855 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3856 if (batch_obj->pending_write_domain) {
3857 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3858 ret = -EINVAL;
3859 goto err;
3860 }
3861 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3862
83d60795
CW		 3863 /* Sanity check the batch buffer, prior to moving objects */
3864 exec_offset = exec_list[args->buffer_count - 1].offset;
3865 ret = i915_gem_check_execbuffer (args, exec_offset);
3866 if (ret != 0) {
3867 DRM_ERROR("execbuf with invalid offset/length\n");
3868 goto err;
3869 }
3870
673a394b
EA		 3871 i915_verify_inactive(dev, __FILE__, __LINE__);
3872
646f0f6e
KP		 3873 /* Zero the global flush/invalidate flags. These
3874 * will be modified as new domains are computed
3875 * for each object
3876 */
3877 dev->invalidate_domains = 0;
3878 dev->flush_domains = 0;
3879
673a394b
EA		 3880 for (i = 0; i < args->buffer_count; i++) {
3881 struct drm_gem_object *obj = object_list[i];
673a394b 3882
646f0f6e 3883 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3884 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3885 }
3886
3887 i915_verify_inactive(dev, __FILE__, __LINE__);
3888
646f0f6e
KP		 3889 if (dev->invalidate_domains | dev->flush_domains) {
3890#if WATCH_EXEC
3891 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3892 __func__,
3893 dev->invalidate_domains,
3894 dev->flush_domains);
3895#endif
3896 i915_gem_flush(dev,
3897 dev->invalidate_domains,
3898 dev->flush_domains);
852835f3 3899 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
b962442e 3900 (void)i915_add_request(dev, file_priv,
852835f3
ZN		 3901 dev->flush_domains,
3902 &dev_priv->render_ring);
3903
d1b851fc
ZN		 3904 if (HAS_BSD(dev))
3905 (void)i915_add_request(dev, file_priv,
3906 dev->flush_domains,
3907 &dev_priv->bsd_ring);
852835f3 3908 }
646f0f6e 3909 }
673a394b 3910
efbeed96
EA		 3911 for (i = 0; i < args->buffer_count; i++) {
3912 struct drm_gem_object *obj = object_list[i];
23010e43 3913 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3914 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3915
3916 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3917 if (obj->write_domain)
3918 list_move_tail(&obj_priv->gpu_write_list,
3919 &dev_priv->mm.gpu_write_list);
3920 else
3921 list_del_init(&obj_priv->gpu_write_list);
3922
1c5d22f7
CW		 3923 trace_i915_gem_object_change_domain(obj,
3924 obj->read_domains,
3925 old_write_domain);
efbeed96
EA		 3926 }
3927
673a394b
EA		 3928 i915_verify_inactive(dev, __FILE__, __LINE__);
3929
3930#if WATCH_COHERENCY
3931 for (i = 0; i < args->buffer_count; i++) {
3932 i915_gem_object_check_coherency(object_list[i],
3933 exec_list[i].handle);
3934 }
3935#endif
3936
673a394b 3937#if WATCH_EXEC
6911a9b8 3938 i915_gem_dump_object(batch_obj,
673a394b
EA		 3939 args->batch_len,
3940 __func__,
3941 ~0);
3942#endif
3943
673a394b 3944 /* Exec the batchbuffer */
852835f3
ZN		 3945 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3946 cliprects, exec_offset);
673a394b
EA		 3947 if (ret) {
3948 DRM_ERROR("dispatch failed %d\n", ret);
3949 goto err;
3950 }
3951
3952 /*
3953 * Ensure that the commands in the batch buffer are
3954 * finished before the interrupt fires
3955 */
852835f3 3956 flush_domains = i915_retire_commands(dev, ring);
673a394b
EA		 3957
3958 i915_verify_inactive(dev, __FILE__, __LINE__);
3959
3960 /*
3961 * Get a seqno representing the execution of the current buffer,
3962 * which we can wait on. We would like to mitigate these interrupts,
3963 * likely by only creating seqnos occasionally (so that we have
3964 * *some* interrupts representing completion of buffers that we can
3965 * wait on when trying to clear up gtt space).
3966 */
852835f3 3967 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
673a394b 3968 BUG_ON(seqno == 0);
673a394b
EA		 3969 for (i = 0; i < args->buffer_count; i++) {
3970 struct drm_gem_object *obj = object_list[i];
852835f3 3971 obj_priv = to_intel_bo(obj);
673a394b 3972
852835f3 3973 i915_gem_object_move_to_active(obj, seqno, ring);
673a394b
EA		 3974#if WATCH_LRU
3975 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3976#endif
3977 }
3978#if WATCH_LRU
3979 i915_dump_lru(dev, __func__);
3980#endif
3981
3982 i915_verify_inactive(dev, __FILE__, __LINE__);
3983
673a394b 3984err:
aad87dff
JL		 3985 for (i = 0; i < pinned; i++)
3986 i915_gem_object_unpin(object_list[i]);
3987
b70d11da
KH		 3988 for (i = 0; i < args->buffer_count; i++) {
3989 if (object_list[i]) {
23010e43 3990 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3991 obj_priv->in_execbuffer = false;
3992 }
aad87dff 3993 drm_gem_object_unreference(object_list[i]);
b70d11da 3994 }
673a394b 3995
673a394b
EA		 3996 mutex_unlock(&dev->struct_mutex);
3997
93533c29 3998pre_mutex_err:
40a5f0de
EA		 3999 /* Copy the updated relocations out regardless of current error
4000 * state. Failure to update the relocs would mean that the next
4001 * time userland calls execbuf, it would do so with presumed offset
4002 * state that didn't match the actual object state.
4003 */
4004 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4005 relocs);
4006 if (ret2 != 0) {
4007 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4008
4009 if (ret == 0)
4010 ret = ret2;
4011 }
4012
8e7d2b2c 4013 drm_free_large(object_list);
9a298b2a 4014 kfree(cliprects);
673a394b
EA		 4015
4016 return ret;
4017}
4018
76446cac
JB		 4019/*
4020 * Legacy execbuffer just creates an exec2 list from the original exec object
4021 * list array and passes it to the real function.
4022 */
4023int
4024i915_gem_execbuffer(struct drm_device *dev, void *data,
4025 struct drm_file *file_priv)
4026{
4027 struct drm_i915_gem_execbuffer *args = data;
4028 struct drm_i915_gem_execbuffer2 exec2;
4029 struct drm_i915_gem_exec_object *exec_list = NULL;
4030 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4031 int ret, i;
4032
4033#if WATCH_EXEC
4034 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4035 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4036#endif
4037
4038 if (args->buffer_count < 1) {
4039 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4040 return -EINVAL;
4041 }
4042
4043 /* Copy in the exec list from userland */
4044 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4045 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4046 if (exec_list == NULL || exec2_list == NULL) {
4047 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4048 args->buffer_count);
4049 drm_free_large(exec_list);
4050 drm_free_large(exec2_list);
4051 return -ENOMEM;
4052 }
4053 ret = copy_from_user(exec_list,
4054 (struct drm_i915_relocation_entry __user *)
4055 (uintptr_t) args->buffers_ptr,
4056 sizeof(*exec_list) * args->buffer_count);
4057 if (ret != 0) {
4058 DRM_ERROR("copy %d exec entries failed %d\n",
4059 args->buffer_count, ret);
4060 drm_free_large(exec_list);
4061 drm_free_large(exec2_list);
4062 return -EFAULT;
4063 }
4064
4065 for (i = 0; i < args->buffer_count; i++) {
4066 exec2_list[i].handle = exec_list[i].handle;
4067 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4068 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4069 exec2_list[i].alignment = exec_list[i].alignment;
4070 exec2_list[i].offset = exec_list[i].offset;
4071 if (!IS_I965G(dev))
4072 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4073 else
4074 exec2_list[i].flags = 0;
4075 }
4076
4077 exec2.buffers_ptr = args->buffers_ptr;
4078 exec2.buffer_count = args->buffer_count;
4079 exec2.batch_start_offset = args->batch_start_offset;
4080 exec2.batch_len = args->batch_len;
4081 exec2.DR1 = args->DR1;
4082 exec2.DR4 = args->DR4;
4083 exec2.num_cliprects = args->num_cliprects;
4084 exec2.cliprects_ptr = args->cliprects_ptr;
852835f3 4085 exec2.flags = I915_EXEC_RENDER;
76446cac
JB		 4086
4087 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4088 if (!ret) {
4089 /* Copy the new buffer offsets back to the user's exec list. */
4090 for (i = 0; i < args->buffer_count; i++)
4091 exec_list[i].offset = exec2_list[i].offset;
4092 /* ... and back out to userspace */
4093 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4094 (uintptr_t) args->buffers_ptr,
4095 exec_list,
4096 sizeof(*exec_list) * args->buffer_count);
4097 if (ret) {
4098 ret = -EFAULT;
4099 DRM_ERROR("failed to copy %d exec entries "
4100 "back to user (%d)\n",
4101 args->buffer_count, ret);
4102 }
76446cac
JB		 4103 }
4104
4105 drm_free_large(exec_list);
4106 drm_free_large(exec2_list);
4107 return ret;
4108}
4109
4110int
4111i915_gem_execbuffer2(struct drm_device *dev, void *data,
4112 struct drm_file *file_priv)
4113{
4114 struct drm_i915_gem_execbuffer2 *args = data;
4115 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4116 int ret;
4117
4118#if WATCH_EXEC
4119 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4120 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4121#endif
4122
4123 if (args->buffer_count < 1) {
4124 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4125 return -EINVAL;
4126 }
4127
4128 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4129 if (exec2_list == NULL) {
4130 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4131 args->buffer_count);
4132 return -ENOMEM;
4133 }
4134 ret = copy_from_user(exec2_list,
4135 (struct drm_i915_relocation_entry __user *)
4136 (uintptr_t) args->buffers_ptr,
4137 sizeof(*exec2_list) * args->buffer_count);
4138 if (ret != 0) {
4139 DRM_ERROR("copy %d exec entries failed %d\n",
4140 args->buffer_count, ret);
4141 drm_free_large(exec2_list);
4142 return -EFAULT;
4143 }
4144
4145 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4146 if (!ret) {
4147 /* Copy the new buffer offsets back to the user's exec list. */
4148 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4149 (uintptr_t) args->buffers_ptr,
4150 exec2_list,
4151 sizeof(*exec2_list) * args->buffer_count);
4152 if (ret) {
4153 ret = -EFAULT;
4154 DRM_ERROR("failed to copy %d exec entries "
4155 "back to user (%d)\n",
4156 args->buffer_count, ret);
4157 }
4158 }
4159
4160 drm_free_large(exec2_list);
4161 return ret;
4162}
4163
673a394b
EA		 4164int
4165i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4166{
4167 struct drm_device *dev = obj->dev;
23010e43 4168 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4169 int ret;
4170
778c3544
DV		 4171 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4172
673a394b 4173 i915_verify_inactive(dev, __FILE__, __LINE__);
ac0c6b5a
CW		 4174
4175 if (obj_priv->gtt_space != NULL) {
4176 if (alignment == 0)
4177 alignment = i915_gem_get_gtt_alignment(obj);
4178 if (obj_priv->gtt_offset & (alignment - 1)) {
4179 ret = i915_gem_object_unbind(obj);
4180 if (ret)
4181 return ret;
4182 }
4183 }
4184
673a394b
EA		 4185 if (obj_priv->gtt_space == NULL) {
4186 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4187 if (ret)
673a394b 4188 return ret;
22c344e9 4189 }
76446cac 4190
673a394b
EA		 4191 obj_priv->pin_count++;
4192
4193 /* If the object is not active and not pending a flush,
4194 * remove it from the inactive list
4195 */
4196 if (obj_priv->pin_count == 1) {
4197 atomic_inc(&dev->pin_count);
4198 atomic_add(obj->size, &dev->pin_memory);
4199 if (!obj_priv->active &&
21d509e3 4200 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4201 !list_empty(&obj_priv->list))
4202 list_del_init(&obj_priv->list);
4203 }
4204 i915_verify_inactive(dev, __FILE__, __LINE__);
4205
4206 return 0;
4207}
4208
4209void
4210i915_gem_object_unpin(struct drm_gem_object *obj)
4211{
4212 struct drm_device *dev = obj->dev;
4213 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4214 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4215
4216 i915_verify_inactive(dev, __FILE__, __LINE__);
4217 obj_priv->pin_count--;
4218 BUG_ON(obj_priv->pin_count < 0);
4219 BUG_ON(obj_priv->gtt_space == NULL);
4220
4221 /* If the object is no longer pinned, and is
4222 * neither active nor being flushed, then stick it on
4223 * the inactive list
4224 */
4225 if (obj_priv->pin_count == 0) {
4226 if (!obj_priv->active &&
21d509e3 4227 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4228 list_move_tail(&obj_priv->list,
4229 &dev_priv->mm.inactive_list);
4230 atomic_dec(&dev->pin_count);
4231 atomic_sub(obj->size, &dev->pin_memory);
4232 }
4233 i915_verify_inactive(dev, __FILE__, __LINE__);
4234}
4235
4236int
4237i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4238 struct drm_file *file_priv)
4239{
4240 struct drm_i915_gem_pin *args = data;
4241 struct drm_gem_object *obj;
4242 struct drm_i915_gem_object *obj_priv;
4243 int ret;
4244
4245 mutex_lock(&dev->struct_mutex);
4246
4247 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4248 if (obj == NULL) {
4249 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4250 args->handle);
4251 mutex_unlock(&dev->struct_mutex);
4252 return -EBADF;
4253 }
23010e43 4254 obj_priv = to_intel_bo(obj);
673a394b 4255
bb6baf76
CW		 4256 if (obj_priv->madv != I915_MADV_WILLNEED) {
4257 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4258 drm_gem_object_unreference(obj);
4259 mutex_unlock(&dev->struct_mutex);
4260 return -EINVAL;
4261 }
4262
79e53945
JB		 4263 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4264 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4265 args->handle);
96dec61d 4266 drm_gem_object_unreference(obj);
673a394b 4267 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4268 return -EINVAL;
4269 }
4270
4271 obj_priv->user_pin_count++;
4272 obj_priv->pin_filp = file_priv;
4273 if (obj_priv->user_pin_count == 1) {
4274 ret = i915_gem_object_pin(obj, args->alignment);
4275 if (ret != 0) {
4276 drm_gem_object_unreference(obj);
4277 mutex_unlock(&dev->struct_mutex);
4278 return ret;
4279 }
673a394b
EA		 4280 }
4281
4282 /* XXX - flush the CPU caches for pinned objects
4283 * as the X server doesn't manage domains yet
4284 */
e47c68e9 4285 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4286 args->offset = obj_priv->gtt_offset;
4287 drm_gem_object_unreference(obj);
4288 mutex_unlock(&dev->struct_mutex);
4289
4290 return 0;
4291}
4292
4293int
4294i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4295 struct drm_file *file_priv)
4296{
4297 struct drm_i915_gem_pin *args = data;
4298 struct drm_gem_object *obj;
79e53945 4299 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4300
4301 mutex_lock(&dev->struct_mutex);
4302
4303 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4304 if (obj == NULL) {
4305 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4306 args->handle);
4307 mutex_unlock(&dev->struct_mutex);
4308 return -EBADF;
4309 }
4310
23010e43 4311 obj_priv = to_intel_bo(obj);
79e53945
JB		 4312 if (obj_priv->pin_filp != file_priv) {
4313 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4314 args->handle);
4315 drm_gem_object_unreference(obj);
4316 mutex_unlock(&dev->struct_mutex);
4317 return -EINVAL;
4318 }
4319 obj_priv->user_pin_count--;
4320 if (obj_priv->user_pin_count == 0) {
4321 obj_priv->pin_filp = NULL;
4322 i915_gem_object_unpin(obj);
4323 }
673a394b
EA		 4324
4325 drm_gem_object_unreference(obj);
4326 mutex_unlock(&dev->struct_mutex);
4327 return 0;
4328}
4329
4330int
4331i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4332 struct drm_file *file_priv)
4333{
4334 struct drm_i915_gem_busy *args = data;
4335 struct drm_gem_object *obj;
4336 struct drm_i915_gem_object *obj_priv;
4337
673a394b
EA		 4338 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4339 if (obj == NULL) {
4340 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4341 args->handle);
673a394b
EA		 4342 return -EBADF;
4343 }
4344
b1ce786c 4345 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4346 /* Update the active list for the hardware's current position.
4347 * Otherwise this only updates on a delayed timer or when irqs are
4348 * actually unmasked, and our working set ends up being larger than
4349 * required.
4350 */
b09a1fec 4351 i915_gem_retire_requests(dev);
d1b851fc 4352
23010e43 4353 obj_priv = to_intel_bo(obj);
c4de0a5d
EA		 4354 /* Don't count being on the flushing list against the object being
4355 * done. Otherwise, a buffer left on the flushing list but not getting
4356 * flushed (because nobody's flushing that domain) won't ever return
4357 * unbusy and get reused by libdrm's bo cache. The other expected
4358 * consumer of this interface, OpenGL's occlusion queries, also specs
4359 * that the objects get unbusy "eventually" without any interference.
4360 */
4361 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4362
4363 drm_gem_object_unreference(obj);
4364 mutex_unlock(&dev->struct_mutex);
4365 return 0;
4366}
4367
4368int
4369i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4370 struct drm_file *file_priv)
4371{
4372 return i915_gem_ring_throttle(dev, file_priv);
4373}
4374
3ef94daa
CW		 4375int
4376i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4377 struct drm_file *file_priv)
4378{
4379 struct drm_i915_gem_madvise *args = data;
4380 struct drm_gem_object *obj;
4381 struct drm_i915_gem_object *obj_priv;
4382
4383 switch (args->madv) {
4384 case I915_MADV_DONTNEED:
4385 case I915_MADV_WILLNEED:
4386 break;
4387 default:
4388 return -EINVAL;
4389 }
4390
4391 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4392 if (obj == NULL) {
4393 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4394 args->handle);
4395 return -EBADF;
4396 }
4397
4398 mutex_lock(&dev->struct_mutex);
23010e43 4399 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4400
4401 if (obj_priv->pin_count) {
4402 drm_gem_object_unreference(obj);
4403 mutex_unlock(&dev->struct_mutex);
4404
4405 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4406 return -EINVAL;
4407 }
4408
bb6baf76
CW		 4409 if (obj_priv->madv != __I915_MADV_PURGED)
4410 obj_priv->madv = args->madv;
3ef94daa 4411
2d7ef395
CW		 4412 /* if the object is no longer bound, discard its backing storage */
4413 if (i915_gem_object_is_purgeable(obj_priv) &&
4414 obj_priv->gtt_space == NULL)
4415 i915_gem_object_truncate(obj);
4416
bb6baf76
CW		 4417 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4418
3ef94daa
CW		 4419 drm_gem_object_unreference(obj);
4420 mutex_unlock(&dev->struct_mutex);
4421
4422 return 0;
4423}
4424
ac52bc56
DV		 4425struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4426 size_t size)
4427{
c397b908 4428 struct drm_i915_gem_object *obj;
ac52bc56 4429
c397b908
DV		 4430 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4431 if (obj == NULL)
4432 return NULL;
673a394b 4433
c397b908
DV		 4434 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4435 kfree(obj);
4436 return NULL;
4437 }
673a394b 4438
c397b908
DV		 4439 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4440 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4441
c397b908 4442 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4443 obj->base.driver_private = NULL;
c397b908
DV		 4444 obj->fence_reg = I915_FENCE_REG_NONE;
4445 INIT_LIST_HEAD(&obj->list);
4446 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4447 obj->madv = I915_MADV_WILLNEED;
de151cf6 4448
c397b908
DV		 4449 trace_i915_gem_object_create(&obj->base);
4450
4451 return &obj->base;
4452}
4453
4454int i915_gem_init_object(struct drm_gem_object *obj)
4455{
4456 BUG();
de151cf6 4457
673a394b
EA		 4458 return 0;
4459}
4460
4461void i915_gem_free_object(struct drm_gem_object *obj)
4462{
de151cf6 4463 struct drm_device *dev = obj->dev;
23010e43 4464 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 4465
1c5d22f7
CW		 4466 trace_i915_gem_object_destroy(obj);
4467
673a394b
EA		 4468 while (obj_priv->pin_count > 0)
4469 i915_gem_object_unpin(obj);
4470
71acb5eb
DA		 4471 if (obj_priv->phys_obj)
4472 i915_gem_detach_phys_object(dev, obj);
4473
673a394b
EA		 4474 i915_gem_object_unbind(obj);
4475
7e616158
CW		 4476 if (obj_priv->mmap_offset)
4477 i915_gem_free_mmap_offset(obj);
de151cf6 4478
c397b908
DV		 4479 drm_gem_object_release(obj);
4480
9a298b2a 4481 kfree(obj_priv->page_cpu_valid);
280b713b 4482 kfree(obj_priv->bit_17);
c397b908 4483 kfree(obj_priv);
673a394b
EA		 4484}
4485
ab5ee576 4486/** Unbinds all inactive objects. */
673a394b 4487static int
ab5ee576 4488i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4489{
ab5ee576 4490 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4491
ab5ee576
CW		 4492 while (!list_empty(&dev_priv->mm.inactive_list)) {
4493 struct drm_gem_object *obj;
4494 int ret;
673a394b 4495
a8089e84
DV		 4496 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4497 struct drm_i915_gem_object,
4498 list)->base;
673a394b
EA		 4499
4500 ret = i915_gem_object_unbind(obj);
4501 if (ret != 0) {
ab5ee576 4502 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4503 return ret;
4504 }
4505 }
4506
673a394b
EA		 4507 return 0;
4508}
4509
29105ccc
CW		 4510int
4511i915_gem_idle(struct drm_device *dev)
4512{
4513 drm_i915_private_t *dev_priv = dev->dev_private;
4514 int ret;
28dfe52a 4515
29105ccc 4516 mutex_lock(&dev->struct_mutex);
1c5d22f7 4517
8187a2b7 4518 if (dev_priv->mm.suspended ||
d1b851fc
ZN		 4519 (dev_priv->render_ring.gem_object == NULL) ||
4520 (HAS_BSD(dev) &&
4521 dev_priv->bsd_ring.gem_object == NULL)) {
29105ccc
CW		 4522 mutex_unlock(&dev->struct_mutex);
4523 return 0;
28dfe52a
EA		 4524 }
4525
29105ccc 4526 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4527 if (ret) {
4528 mutex_unlock(&dev->struct_mutex);
673a394b 4529 return ret;
6dbe2772 4530 }
673a394b 4531
29105ccc
CW		 4532 /* Under UMS, be paranoid and evict. */
4533 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4534 ret = i915_gem_evict_from_inactive_list(dev);
4535 if (ret) {
4536 mutex_unlock(&dev->struct_mutex);
4537 return ret;
4538 }
4539 }
4540
4541 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4542 * We need to replace this with a semaphore, or something.
4543 * And not confound mm.suspended!
4544 */
4545 dev_priv->mm.suspended = 1;
4546 del_timer(&dev_priv->hangcheck_timer);
4547
4548 i915_kernel_lost_context(dev);
6dbe2772 4549 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4550
6dbe2772
KP		 4551 mutex_unlock(&dev->struct_mutex);
4552
29105ccc
CW		 4553 /* Cancel the retire work handler, which should be idle now. */
4554 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4555
673a394b
EA		 4556 return 0;
4557}
4558
e552eb70
JB		 4559/*
4560 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4561 * over cache flushing.
4562 */
8187a2b7 4563static int
e552eb70
JB		 4564i915_gem_init_pipe_control(struct drm_device *dev)
4565{
4566 drm_i915_private_t *dev_priv = dev->dev_private;
4567 struct drm_gem_object *obj;
4568 struct drm_i915_gem_object *obj_priv;
4569 int ret;
4570
34dc4d44 4571 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4572 if (obj == NULL) {
4573 DRM_ERROR("Failed to allocate seqno page\n");
4574 ret = -ENOMEM;
4575 goto err;
4576 }
4577 obj_priv = to_intel_bo(obj);
4578 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4579
4580 ret = i915_gem_object_pin(obj, 4096);
4581 if (ret)
4582 goto err_unref;
4583
4584 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4585 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4586 if (dev_priv->seqno_page == NULL)
4587 goto err_unpin;
4588
4589 dev_priv->seqno_obj = obj;
4590 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4591
4592 return 0;
4593
4594err_unpin:
4595 i915_gem_object_unpin(obj);
4596err_unref:
4597 drm_gem_object_unreference(obj);
4598err:
4599 return ret;
4600}
4601
8187a2b7
ZN		 4602
4603static void
e552eb70
JB		 4604i915_gem_cleanup_pipe_control(struct drm_device *dev)
4605{
4606 drm_i915_private_t *dev_priv = dev->dev_private;
4607 struct drm_gem_object *obj;
4608 struct drm_i915_gem_object *obj_priv;
4609
4610 obj = dev_priv->seqno_obj;
4611 obj_priv = to_intel_bo(obj);
4612 kunmap(obj_priv->pages[0]);
4613 i915_gem_object_unpin(obj);
4614 drm_gem_object_unreference(obj);
4615 dev_priv->seqno_obj = NULL;
4616
4617 dev_priv->seqno_page = NULL;
673a394b
EA		 4618}
4619
8187a2b7
ZN		 4620int
4621i915_gem_init_ringbuffer(struct drm_device *dev)
4622{
4623 drm_i915_private_t *dev_priv = dev->dev_private;
4624 int ret;
68f95ba9 4625
8187a2b7 4626 dev_priv->render_ring = render_ring;
68f95ba9 4627
8187a2b7
ZN		 4628 if (!I915_NEED_GFX_HWS(dev)) {
4629 dev_priv->render_ring.status_page.page_addr
4630 = dev_priv->status_page_dmah->vaddr;
4631 memset(dev_priv->render_ring.status_page.page_addr,
4632 0, PAGE_SIZE);
4633 }
68f95ba9 4634
8187a2b7
ZN		 4635 if (HAS_PIPE_CONTROL(dev)) {
4636 ret = i915_gem_init_pipe_control(dev);
4637 if (ret)
4638 return ret;
4639 }
68f95ba9 4640
8187a2b7 4641 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
68f95ba9
CW		 4642 if (ret)
4643 goto cleanup_pipe_control;
4644
4645 if (HAS_BSD(dev)) {
d1b851fc
ZN		 4646 dev_priv->bsd_ring = bsd_ring;
4647 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
68f95ba9
CW		 4648 if (ret)
4649 goto cleanup_render_ring;
d1b851fc 4650 }
68f95ba9
CW		 4651
4652 return 0;
4653
4654cleanup_render_ring:
4655 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4656cleanup_pipe_control:
4657 if (HAS_PIPE_CONTROL(dev))
4658 i915_gem_cleanup_pipe_control(dev);
8187a2b7
ZN		 4659 return ret;
4660}
4661
4662void
4663i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4664{
4665 drm_i915_private_t *dev_priv = dev->dev_private;
4666
4667 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4668 if (HAS_BSD(dev))
4669 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
8187a2b7
ZN		 4670 if (HAS_PIPE_CONTROL(dev))
4671 i915_gem_cleanup_pipe_control(dev);
4672}
4673
673a394b
EA		 4674int
4675i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4676 struct drm_file *file_priv)
4677{
4678 drm_i915_private_t *dev_priv = dev->dev_private;
4679 int ret;
4680
79e53945
JB		 4681 if (drm_core_check_feature(dev, DRIVER_MODESET))
4682 return 0;
4683
ba1234d1 4684 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4685 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4686 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4687 }
4688
673a394b 4689 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4690 dev_priv->mm.suspended = 0;
4691
4692 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4693 if (ret != 0) {
4694 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4695 return ret;
d816f6ac 4696 }
9bb2d6f9 4697
5e118f41 4698 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 4699 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
d1b851fc 4700 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
5e118f41
CW		 4701 spin_unlock(&dev_priv->mm.active_list_lock);
4702
673a394b
EA		 4703 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4704 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
852835f3 4705 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
d1b851fc 4706 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
673a394b 4707 mutex_unlock(&dev->struct_mutex);
dbb19d30 4708
5f35308b
CW		 4709 ret = drm_irq_install(dev);
4710 if (ret)
4711 goto cleanup_ringbuffer;
dbb19d30 4712
673a394b 4713 return 0;
5f35308b
CW		 4714
4715cleanup_ringbuffer:
4716 mutex_lock(&dev->struct_mutex);
4717 i915_gem_cleanup_ringbuffer(dev);
4718 dev_priv->mm.suspended = 1;
4719 mutex_unlock(&dev->struct_mutex);
4720
4721 return ret;
673a394b
EA		 4722}
4723
4724int
4725i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4726 struct drm_file *file_priv)
4727{
79e53945
JB		 4728 if (drm_core_check_feature(dev, DRIVER_MODESET))
4729 return 0;
4730
dbb19d30 4731 drm_irq_uninstall(dev);
e6890f6f 4732 return i915_gem_idle(dev);
673a394b
EA		 4733}
4734
4735void
4736i915_gem_lastclose(struct drm_device *dev)
4737{
4738 int ret;
673a394b 4739
e806b495
EA		 4740 if (drm_core_check_feature(dev, DRIVER_MODESET))
4741 return;
4742
6dbe2772
KP		 4743 ret = i915_gem_idle(dev);
4744 if (ret)
4745 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4746}
4747
4748void
4749i915_gem_load(struct drm_device *dev)
4750{
b5aa8a0f 4751 int i;
673a394b
EA		 4752 drm_i915_private_t *dev_priv = dev->dev_private;
4753
5e118f41 4754 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b 4755 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4756 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b 4757 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
a09ba7fa 4758 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
852835f3
ZN		 4759 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4760 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
d1b851fc
ZN		 4761 if (HAS_BSD(dev)) {
4762 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4763 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4764 }
007cc8ac
DV		 4765 for (i = 0; i < 16; i++)
4766 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4767 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4768 i915_gem_retire_work_handler);
31169714
CW		 4769 spin_lock(&shrink_list_lock);
4770 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4771 spin_unlock(&shrink_list_lock);
4772
94400120
DA		 4773 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4774 if (IS_GEN3(dev)) {
4775 u32 tmp = I915_READ(MI_ARB_STATE);
4776 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4777 /* arb state is a masked write, so set bit + bit in mask */
4778 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4779 I915_WRITE(MI_ARB_STATE, tmp);
4780 }
4781 }
4782
de151cf6 4783 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4784 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4785 dev_priv->fence_reg_start = 3;
de151cf6 4786
0f973f27 4787 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4788 dev_priv->num_fence_regs = 16;
4789 else
4790 dev_priv->num_fence_regs = 8;
4791
b5aa8a0f
GH		 4792 /* Initialize fence registers to zero */
4793 if (IS_I965G(dev)) {
4794 for (i = 0; i < 16; i++)
4795 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4796 } else {
4797 for (i = 0; i < 8; i++)
4798 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4799 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4800 for (i = 0; i < 8; i++)
4801 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4802 }
673a394b 4803 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4804 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4805}
71acb5eb
DA		 4806
4807/*
4808 * Create a physically contiguous memory object for this object
4809 * e.g. for cursor + overlay regs
4810 */
4811int i915_gem_init_phys_object(struct drm_device *dev,
4812 int id, int size)
4813{
4814 drm_i915_private_t *dev_priv = dev->dev_private;
4815 struct drm_i915_gem_phys_object *phys_obj;
4816 int ret;
4817
4818 if (dev_priv->mm.phys_objs[id - 1] || !size)
4819 return 0;
4820
9a298b2a 4821 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4822 if (!phys_obj)
4823 return -ENOMEM;
4824
4825 phys_obj->id = id;
4826
e6be8d9d 4827 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4828 if (!phys_obj->handle) {
4829 ret = -ENOMEM;
4830 goto kfree_obj;
4831 }
4832#ifdef CONFIG_X86
4833 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4834#endif
4835
4836 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4837
4838 return 0;
4839kfree_obj:
9a298b2a 4840 kfree(phys_obj);
71acb5eb
DA		 4841 return ret;
4842}
4843
4844void i915_gem_free_phys_object(struct drm_device *dev, int id)
4845{
4846 drm_i915_private_t *dev_priv = dev->dev_private;
4847 struct drm_i915_gem_phys_object *phys_obj;
4848
4849 if (!dev_priv->mm.phys_objs[id - 1])
4850 return;
4851
4852 phys_obj = dev_priv->mm.phys_objs[id - 1];
4853 if (phys_obj->cur_obj) {
4854 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4855 }
4856
4857#ifdef CONFIG_X86
4858 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4859#endif
4860 drm_pci_free(dev, phys_obj->handle);
4861 kfree(phys_obj);
4862 dev_priv->mm.phys_objs[id - 1] = NULL;
4863}
4864
4865void i915_gem_free_all_phys_object(struct drm_device *dev)
4866{
4867 int i;
4868
260883c8 4869 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4870 i915_gem_free_phys_object(dev, i);
4871}
4872
4873void i915_gem_detach_phys_object(struct drm_device *dev,
4874 struct drm_gem_object *obj)
4875{
4876 struct drm_i915_gem_object *obj_priv;
4877 int i;
4878 int ret;
4879 int page_count;
4880
23010e43 4881 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4882 if (!obj_priv->phys_obj)
4883 return;
4884
4bdadb97 4885 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4886 if (ret)
4887 goto out;
4888
4889 page_count = obj->size / PAGE_SIZE;
4890
4891 for (i = 0; i < page_count; i++) {
856fa198 4892 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4893 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4894
4895 memcpy(dst, src, PAGE_SIZE);
4896 kunmap_atomic(dst, KM_USER0);
4897 }
856fa198 4898 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4899 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4900
4901 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4902out:
4903 obj_priv->phys_obj->cur_obj = NULL;
4904 obj_priv->phys_obj = NULL;
4905}
4906
4907int
4908i915_gem_attach_phys_object(struct drm_device *dev,
4909 struct drm_gem_object *obj, int id)
4910{
4911 drm_i915_private_t *dev_priv = dev->dev_private;
4912 struct drm_i915_gem_object *obj_priv;
4913 int ret = 0;
4914 int page_count;
4915 int i;
4916
4917 if (id > I915_MAX_PHYS_OBJECT)
4918 return -EINVAL;
4919
23010e43 4920 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4921
4922 if (obj_priv->phys_obj) {
4923 if (obj_priv->phys_obj->id == id)
4924 return 0;
4925 i915_gem_detach_phys_object(dev, obj);
4926 }
4927
4928
4929 /* create a new object */
4930 if (!dev_priv->mm.phys_objs[id - 1]) {
4931 ret = i915_gem_init_phys_object(dev, id,
4932 obj->size);
4933 if (ret) {
aeb565df 4934 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4935 goto out;
4936 }
4937 }
4938
4939 /* bind to the object */
4940 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4941 obj_priv->phys_obj->cur_obj = obj;
4942
4bdadb97 4943 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4944 if (ret) {
4945 DRM_ERROR("failed to get page list\n");
4946 goto out;
4947 }
4948
4949 page_count = obj->size / PAGE_SIZE;
4950
4951 for (i = 0; i < page_count; i++) {
856fa198 4952 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4953 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4954
4955 memcpy(dst, src, PAGE_SIZE);
4956 kunmap_atomic(src, KM_USER0);
4957 }
4958
d78b47b9
CW		 4959 i915_gem_object_put_pages(obj);
4960
71acb5eb
DA		 4961 return 0;
4962out:
4963 return ret;
4964}
4965
4966static int
4967i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4968 struct drm_i915_gem_pwrite *args,
4969 struct drm_file *file_priv)
4970{
23010e43 4971 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4972 void *obj_addr;
4973 int ret;
4974 char __user *user_data;
4975
4976 user_data = (char __user *) (uintptr_t) args->data_ptr;
4977 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4978
44d98a61 4979 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4980 ret = copy_from_user(obj_addr, user_data, args->size);
4981 if (ret)
4982 return -EFAULT;
4983
4984 drm_agp_chipset_flush(dev);
4985 return 0;
4986}
b962442e
EA		 4987
4988void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4989{
4990 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4991
4992 /* Clean up our request list when the client is going away, so that
4993 * later retire_requests won't dereference our soon-to-be-gone
4994 * file_priv.
4995 */
4996 mutex_lock(&dev->struct_mutex);
4997 while (!list_empty(&i915_file_priv->mm.request_list))
4998 list_del_init(i915_file_priv->mm.request_list.next);
4999 mutex_unlock(&dev->struct_mutex);
5000}
31169714 5001
1637ef41
CW		 5002static int
5003i915_gpu_is_active(struct drm_device *dev)
5004{
5005 drm_i915_private_t *dev_priv = dev->dev_private;
5006 int lists_empty;
5007
5008 spin_lock(&dev_priv->mm.active_list_lock);
5009 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
852835f3 5010 list_empty(&dev_priv->render_ring.active_list);
d1b851fc
ZN		 5011 if (HAS_BSD(dev))
5012 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
1637ef41
CW		 5013 spin_unlock(&dev_priv->mm.active_list_lock);
5014
5015 return !lists_empty;
5016}
5017
31169714 5018static int
7f8275d0 5019i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
31169714
CW		 5020{
5021 drm_i915_private_t *dev_priv, *next_dev;
5022 struct drm_i915_gem_object *obj_priv, *next_obj;
5023 int cnt = 0;
5024 int would_deadlock = 1;
5025
5026 /* "fast-path" to count number of available objects */
5027 if (nr_to_scan == 0) {
5028 spin_lock(&shrink_list_lock);
5029 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5030 struct drm_device *dev = dev_priv->dev;
5031
5032 if (mutex_trylock(&dev->struct_mutex)) {
5033 list_for_each_entry(obj_priv,
5034 &dev_priv->mm.inactive_list,
5035 list)
5036 cnt++;
5037 mutex_unlock(&dev->struct_mutex);
5038 }
5039 }
5040 spin_unlock(&shrink_list_lock);
5041
5042 return (cnt / 100) * sysctl_vfs_cache_pressure;
5043 }
5044
5045 spin_lock(&shrink_list_lock);
5046
1637ef41 5047rescan:
31169714
CW		 5048 /* first scan for clean buffers */
5049 list_for_each_entry_safe(dev_priv, next_dev,
5050 &shrink_list, mm.shrink_list) {
5051 struct drm_device *dev = dev_priv->dev;
5052
5053 if (! mutex_trylock(&dev->struct_mutex))
5054 continue;
5055
5056 spin_unlock(&shrink_list_lock);
b09a1fec 5057 i915_gem_retire_requests(dev);
31169714
CW		 5058
5059 list_for_each_entry_safe(obj_priv, next_obj,
5060 &dev_priv->mm.inactive_list,
5061 list) {
5062 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 5063 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5064 if (--nr_to_scan <= 0)
5065 break;
5066 }
5067 }
5068
5069 spin_lock(&shrink_list_lock);
5070 mutex_unlock(&dev->struct_mutex);
5071
963b4836
CW		 5072 would_deadlock = 0;
5073
31169714
CW		 5074 if (nr_to_scan <= 0)
5075 break;
5076 }
5077
5078 /* second pass, evict/count anything still on the inactive list */
5079 list_for_each_entry_safe(dev_priv, next_dev,
5080 &shrink_list, mm.shrink_list) {
5081 struct drm_device *dev = dev_priv->dev;
5082
5083 if (! mutex_trylock(&dev->struct_mutex))
5084 continue;
5085
5086 spin_unlock(&shrink_list_lock);
5087
5088 list_for_each_entry_safe(obj_priv, next_obj,
5089 &dev_priv->mm.inactive_list,
5090 list) {
5091 if (nr_to_scan > 0) {
a8089e84 5092 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5093 nr_to_scan--;
5094 } else
5095 cnt++;
5096 }
5097
5098 spin_lock(&shrink_list_lock);
5099 mutex_unlock(&dev->struct_mutex);
5100
5101 would_deadlock = 0;
5102 }
5103
1637ef41
CW		 5104 if (nr_to_scan) {
5105 int active = 0;
5106
5107 /*
5108 * We are desperate for pages, so as a last resort, wait
5109 * for the GPU to finish and discard whatever we can.
5110 * This has a dramatic impact to reduce the number of
5111 * OOM-killer events whilst running the GPU aggressively.
5112 */
5113 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5114 struct drm_device *dev = dev_priv->dev;
5115
5116 if (!mutex_trylock(&dev->struct_mutex))
5117 continue;
5118
5119 spin_unlock(&shrink_list_lock);
5120
5121 if (i915_gpu_is_active(dev)) {
5122 i915_gpu_idle(dev);
5123 active++;
5124 }
5125
5126 spin_lock(&shrink_list_lock);
5127 mutex_unlock(&dev->struct_mutex);
5128 }
5129
5130 if (active)
5131 goto rescan;
5132 }
5133
31169714
CW		 5134 spin_unlock(&shrink_list_lock);
5135
5136 if (would_deadlock)
5137 return -1;
5138 else if (cnt > 0)
5139 return (cnt / 100) * sysctl_vfs_cache_pressure;
5140 else
5141 return 0;
5142}
5143
5144static struct shrinker shrinker = {
5145 .shrink = i915_gem_shrink,
5146 .seeks = DEFAULT_SEEKS,
5147};
5148
5149__init void
5150i915_gem_shrinker_init(void)
5151{
5152 register_shrinker(&shrinker);
5153}
5154
5155__exit void
5156i915_gem_shrinker_exit(void)
5157{
5158 unregister_shrinker(&shrinker);
5159}
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