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[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
673a394b 34#include <linux/swap.h>
79e53945 35#include <linux/pci.h>
673a394b 36
28dfe52a
EA		 37#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
e47c68e9
EA		 39static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 42static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 int write);
44static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 48static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 49static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 unsigned alignment);
de151cf6 51static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 52static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 53static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 54static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
673a394b 57
31169714
CW		 58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
79e53945
JB		 61int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
673a394b
EA		 63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 65
79e53945
JB		 66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 69 return -EINVAL;
70 }
71
79e53945
JB		 72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
673a394b 74
79e53945
JB		 75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
673a394b 79
79e53945
JB		 80int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
84 struct drm_i915_gem_init *args = data;
85 int ret;
86
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 89 mutex_unlock(&dev->struct_mutex);
90
79e53945 91 return ret;
673a394b
EA		 92}
93
5a125c3c
EA		 94int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
5a125c3c 98 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 99
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
2678d9d6
KP		 104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
5a125c3c
EA		 106
107 return 0;
108}
109
673a394b
EA		 110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
a1a2d1d3
PP		 120 int ret;
121 u32 handle;
673a394b
EA		 122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
134
135 if (ret)
136 return ret;
137
138 args->handle = handle;
139
140 return 0;
141}
142
eb01459f
EA		 143static inline int
144fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
146 char __user *data,
147 int length)
148{
149 char __iomem *vaddr;
2bc43b5c 150 int unwritten;
eb01459f
EA		 151
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 if (vaddr == NULL)
154 return -ENOMEM;
2bc43b5c 155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 156 kunmap_atomic(vaddr, KM_USER0);
157
2bc43b5c
FM		 158 if (unwritten)
159 return -EFAULT;
160
161 return 0;
eb01459f
EA		 162}
163
280b713b
EA		 164static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165{
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
171}
172
40123c1f
EA		 173static inline int
174slow_shmem_copy(struct page *dst_page,
175 int dst_offset,
176 struct page *src_page,
177 int src_offset,
178 int length)
179{
180 char *dst_vaddr, *src_vaddr;
181
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
184 return -ENOMEM;
185
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
189 return -ENOMEM;
190 }
191
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
196
197 return 0;
198}
199
280b713b
EA		 200static inline int
201slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
207{
208 char *gpu_vaddr, *cpu_vaddr;
209
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
218 }
219
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
222 return -ENOMEM;
223
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
227 return -ENOMEM;
228 }
229
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 */
233 while (length > 0) {
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238 if (is_read) {
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
241 this_length);
242 } else {
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
245 this_length);
246 }
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
250 }
251
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
254
255 return 0;
256}
257
eb01459f
EA		 258/**
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 */
263static int
264i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
267{
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
269 ssize_t remain;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
273 int ret;
274
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 remain = args->size;
277
278 mutex_lock(&dev->struct_mutex);
279
280 ret = i915_gem_object_get_pages(obj);
281 if (ret != 0)
282 goto fail_unlock;
283
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285 args->size);
286 if (ret != 0)
287 goto fail_put_pages;
288
289 obj_priv = obj->driver_private;
290 offset = args->offset;
291
292 while (remain > 0) {
293 /* Operation in this page
294 *
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
298 */
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
304
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
308 if (ret)
309 goto fail_put_pages;
310
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
314 }
315
316fail_put_pages:
317 i915_gem_object_put_pages(obj);
318fail_unlock:
319 mutex_unlock(&dev->struct_mutex);
320
321 return ret;
322}
323
07f73f69
CW		 324static inline gfp_t
325i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326{
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328}
329
330static inline void
331i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332{
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334}
335
336static int
337i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338{
339 int ret;
340
341 ret = i915_gem_object_get_pages(obj);
342
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
345 */
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
348 gfp_t gfp;
349
350 ret = i915_gem_evict_something(dev, obj->size);
351 if (ret)
352 return ret;
353
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
358 }
359
360 return ret;
361}
362
eb01459f
EA		 363/**
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
368 */
369static int
370i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
373{
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
377 ssize_t remain;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
382 int page_length;
383 int ret;
384 uint64_t data_ptr = args->data_ptr;
280b713b 385 int do_bit17_swizzling;
eb01459f
EA		 386
387 remain = args->size;
388
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
392 */
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
396
8e7d2b2c 397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 398 if (user_pages == NULL)
399 return -ENOMEM;
400
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 403 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
406 ret = -EFAULT;
407 goto fail_put_user_pages;
408 }
409
280b713b
EA		 410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
411
eb01459f
EA		 412 mutex_lock(&dev->struct_mutex);
413
07f73f69
CW		 414 ret = i915_gem_object_get_pages_or_evict(obj);
415 if (ret)
eb01459f
EA		 416 goto fail_unlock;
417
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
419 args->size);
420 if (ret != 0)
421 goto fail_put_pages;
422
423 obj_priv = obj->driver_private;
424 offset = args->offset;
425
426 while (remain > 0) {
427 /* Operation in this page
428 *
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
434 */
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
439
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
445
280b713b
EA		 446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
448 shmem_page_offset,
449 user_pages[data_page_index],
450 data_page_offset,
451 page_length,
452 1);
453 } else {
454 ret = slow_shmem_copy(user_pages[data_page_index],
455 data_page_offset,
456 obj_priv->pages[shmem_page_index],
457 shmem_page_offset,
458 page_length);
459 }
eb01459f
EA		 460 if (ret)
461 goto fail_put_pages;
462
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
466 }
467
468fail_put_pages:
469 i915_gem_object_put_pages(obj);
470fail_unlock:
471 mutex_unlock(&dev->struct_mutex);
472fail_put_user_pages:
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
476 }
8e7d2b2c 477 drm_free_large(user_pages);
eb01459f
EA		 478
479 return ret;
480}
481
673a394b
EA		 482/**
483 * Reads data from the object referenced by handle.
484 *
485 * On error, the contents of *data are undefined.
486 */
487int
488i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
490{
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 494 int ret;
495
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
497 if (obj == NULL)
498 return -EBADF;
499 obj_priv = obj->driver_private;
500
501 /* Bounds check source.
502 *
503 * XXX: This could use review for overflow issues...
504 */
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
508 return -EINVAL;
509 }
510
280b713b 511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 513 } else {
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
515 if (ret != 0)
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
517 file_priv);
518 }
673a394b
EA		 519
520 drm_gem_object_unreference(obj);
673a394b 521
eb01459f 522 return ret;
673a394b
EA		 523}
524
0839ccb8
KP		 525/* This is the fast write path which cannot handle
526 * page faults in the source data
9b7530cc 527 */
0839ccb8
KP		 528
529static inline int
530fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
533 int length)
9b7530cc 534{
9b7530cc 535 char *vaddr_atomic;
0839ccb8 536 unsigned long unwritten;
9b7530cc 537
0839ccb8
KP		 538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
540 user_data, length);
541 io_mapping_unmap_atomic(vaddr_atomic);
542 if (unwritten)
543 return -EFAULT;
544 return 0;
545}
546
547/* Here's the write path which can sleep for
548 * page faults
549 */
550
551static inline int
3de09aa3
EA		 552slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
555 int length)
0839ccb8 556{
3de09aa3 557 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 558 unsigned long unwritten;
559
3de09aa3
EA		 560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
564 length);
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 567 if (unwritten)
568 return -EFAULT;
9b7530cc 569 return 0;
9b7530cc
LT		 570}
571
40123c1f
EA		 572static inline int
573fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
575 char __user *data,
576 int length)
577{
578 char __iomem *vaddr;
d0088775 579 unsigned long unwritten;
40123c1f
EA		 580
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
582 if (vaddr == NULL)
583 return -ENOMEM;
d0088775 584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 585 kunmap_atomic(vaddr, KM_USER0);
586
d0088775
DA		 587 if (unwritten)
588 return -EFAULT;
40123c1f
EA		 589 return 0;
590}
591
3de09aa3
EA		 592/**
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
595 */
673a394b 596static int
3de09aa3
EA		 597i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
673a394b
EA		 600{
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
0839ccb8 602 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 603 ssize_t remain;
0839ccb8 604 loff_t offset, page_base;
673a394b 605 char __user *user_data;
0839ccb8
KP		 606 int page_offset, page_length;
607 int ret;
673a394b
EA		 608
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
610 remain = args->size;
611 if (!access_ok(VERIFY_READ, user_data, remain))
612 return -EFAULT;
613
614
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
617 if (ret) {
618 mutex_unlock(&dev->struct_mutex);
619 return ret;
620 }
2ef7eeaa 621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 622 if (ret)
623 goto fail;
624
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 627
628 while (remain > 0) {
629 /* Operation in this page
630 *
0839ccb8
KP		 631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
673a394b 634 */
0839ccb8
KP		 635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
640
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
643
644 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
0839ccb8 647 */
3de09aa3
EA		 648 if (ret)
649 goto fail;
673a394b 650
0839ccb8
KP		 651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
673a394b 654 }
673a394b
EA		 655
656fail:
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
659
660 return ret;
661}
662
3de09aa3
EA		 663/**
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
666 *
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
669 */
3043c60c 670static int
3de09aa3
EA		 671i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
673a394b 674{
3de09aa3
EA		 675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
677 ssize_t remain;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 684 int ret;
3de09aa3
EA		 685 uint64_t data_ptr = args->data_ptr;
686
687 remain = args->size;
688
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
692 */
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
696
8e7d2b2c 697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 698 if (user_pages == NULL)
699 return -ENOMEM;
700
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
706 ret = -EFAULT;
707 goto out_unpin_pages;
708 }
673a394b
EA		 709
710 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 711 ret = i915_gem_object_pin(obj, 0);
712 if (ret)
713 goto out_unlock;
714
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
716 if (ret)
717 goto out_unpin_object;
718
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
721
722 while (remain > 0) {
723 /* Operation in this page
724 *
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
730 */
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
735
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
741
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
745 data_page_offset,
746 page_length);
747
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
751 */
752 if (ret)
753 goto out_unpin_object;
754
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
758 }
759
760out_unpin_object:
761 i915_gem_object_unpin(obj);
762out_unlock:
763 mutex_unlock(&dev->struct_mutex);
764out_unpin_pages:
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
8e7d2b2c 767 drm_free_large(user_pages);
3de09aa3
EA		 768
769 return ret;
770}
771
40123c1f
EA		 772/**
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
775 */
3043c60c 776static int
40123c1f
EA		 777i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
673a394b 780{
40123c1f
EA		 781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
782 ssize_t remain;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
673a394b 786 int ret;
40123c1f
EA		 787
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
789 remain = args->size;
673a394b
EA		 790
791 mutex_lock(&dev->struct_mutex);
792
40123c1f
EA		 793 ret = i915_gem_object_get_pages(obj);
794 if (ret != 0)
795 goto fail_unlock;
673a394b 796
e47c68e9 797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 798 if (ret != 0)
799 goto fail_put_pages;
800
801 obj_priv = obj->driver_private;
802 offset = args->offset;
803 obj_priv->dirty = 1;
804
805 while (remain > 0) {
806 /* Operation in this page
807 *
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
811 */
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
817
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
821 if (ret)
822 goto fail_put_pages;
823
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
827 }
828
829fail_put_pages:
830 i915_gem_object_put_pages(obj);
831fail_unlock:
832 mutex_unlock(&dev->struct_mutex);
833
834 return ret;
835}
836
837/**
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
840 *
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
843 */
844static int
845i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
848{
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
852 ssize_t remain;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
857 int page_length;
858 int ret;
859 uint64_t data_ptr = args->data_ptr;
280b713b 860 int do_bit17_swizzling;
40123c1f
EA		 861
862 remain = args->size;
863
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
867 */
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
871
8e7d2b2c 872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 873 if (user_pages == NULL)
874 return -ENOMEM;
875
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
881 ret = -EFAULT;
882 goto fail_put_user_pages;
673a394b
EA		 883 }
884
280b713b
EA		 885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
886
40123c1f
EA		 887 mutex_lock(&dev->struct_mutex);
888
07f73f69
CW		 889 ret = i915_gem_object_get_pages_or_evict(obj);
890 if (ret)
40123c1f
EA		 891 goto fail_unlock;
892
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
894 if (ret != 0)
895 goto fail_put_pages;
896
897 obj_priv = obj->driver_private;
673a394b 898 offset = args->offset;
40123c1f 899 obj_priv->dirty = 1;
673a394b 900
40123c1f
EA		 901 while (remain > 0) {
902 /* Operation in this page
903 *
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
909 */
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
914
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
920
280b713b
EA		 921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
923 shmem_page_offset,
924 user_pages[data_page_index],
925 data_page_offset,
926 page_length,
927 0);
928 } else {
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
930 shmem_page_offset,
931 user_pages[data_page_index],
932 data_page_offset,
933 page_length);
934 }
40123c1f
EA		 935 if (ret)
936 goto fail_put_pages;
937
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
673a394b
EA		 941 }
942
40123c1f
EA		 943fail_put_pages:
944 i915_gem_object_put_pages(obj);
945fail_unlock:
673a394b 946 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 947fail_put_user_pages:
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
8e7d2b2c 950 drm_free_large(user_pages);
673a394b 951
40123c1f 952 return ret;
673a394b
EA		 953}
954
955/**
956 * Writes data to the object referenced by handle.
957 *
958 * On error, the contents of the buffer that were to be modified are undefined.
959 */
960int
961i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
963{
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
967 int ret = 0;
968
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
970 if (obj == NULL)
971 return -EBADF;
972 obj_priv = obj->driver_private;
973
974 /* Bounds check destination.
975 *
976 * XXX: This could use review for overflow issues...
977 */
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
981 return -EINVAL;
982 }
983
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
989 */
71acb5eb
DA		 990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
997 file_priv);
998 }
280b713b
EA		 999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 1001 } else {
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1005 file_priv);
1006 }
1007 }
673a394b
EA		 1008
1009#if WATCH_PWRITE
1010 if (ret)
1011 DRM_INFO("pwrite failed %d\n", ret);
1012#endif
1013
1014 drm_gem_object_unreference(obj);
1015
1016 return ret;
1017}
1018
1019/**
2ef7eeaa
EA		 1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1022 */
1023int
1024i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1026{
a09ba7fa 1027 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
652c393a 1030 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
673a394b
EA		 1033 int ret;
1034
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1036 return -ENODEV;
1037
2ef7eeaa 1038 /* Only handle setting domains to types used by the CPU. */
21d509e3 1039 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1040 return -EINVAL;
1041
21d509e3 1042 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1043 return -EINVAL;
1044
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1047 */
1048 if (write_domain != 0 && read_domains != write_domain)
1049 return -EINVAL;
1050
673a394b
EA		 1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1052 if (obj == NULL)
1053 return -EBADF;
652c393a 1054 obj_priv = obj->driver_private;
673a394b
EA		 1055
1056 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1057
1058 intel_mark_busy(dev, obj);
1059
673a394b 1060#if WATCH_BUF
cfd43c02 1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1062 obj, obj->size, read_domains, write_domain);
673a394b 1063#endif
2ef7eeaa
EA		 1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1066
a09ba7fa
EA		 1067 /* Update the LRU on the fence for the CPU access that's
1068 * about to occur.
1069 */
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1073 }
1074
02354392
EA		 1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1078 */
1079 if (ret == -EINVAL)
1080 ret = 0;
2ef7eeaa 1081 } else {
e47c68e9 1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1083 }
1084
673a394b
EA		 1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1087 return ret;
1088}
1089
1090/**
1091 * Called when user space has done writes to this buffer
1092 */
1093int
1094i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1096{
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1100 int ret = 0;
1101
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1103 return -ENODEV;
1104
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1107 if (obj == NULL) {
1108 mutex_unlock(&dev->struct_mutex);
1109 return -EBADF;
1110 }
1111
1112#if WATCH_BUF
cfd43c02 1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1114 __func__, args->handle, obj, obj->size);
1115#endif
1116 obj_priv = obj->driver_private;
1117
1118 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1121
673a394b
EA		 1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1124 return ret;
1125}
1126
1127/**
1128 * Maps the contents of an object, returning the address it is mapped
1129 * into.
1130 *
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1133 */
1134int
1135i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1137{
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1140 loff_t offset;
1141 unsigned long addr;
1142
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1144 return -ENODEV;
1145
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1147 if (obj == NULL)
1148 return -EBADF;
1149
1150 offset = args->offset;
1151
1152 down_write(&current->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1155 args->offset);
1156 up_write(&current->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1161 return addr;
1162
1163 args->addr_ptr = (uint64_t) addr;
1164
1165 return 0;
1166}
1167
de151cf6
JB		 1168/**
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1171 * vmf: fault info
1172 *
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1178 *
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1182 * left.
1183 */
1184int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1185{
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1191 unsigned long pfn;
1192 int ret = 0;
0f973f27 1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1194
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1197 PAGE_SHIFT;
1198
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
e67b8ce1 1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1203 if (ret) {
1204 mutex_unlock(&dev->struct_mutex);
1205 return VM_FAULT_SIGBUS;
1206 }
4960aaca 1207 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1208
1209 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1210 if (ret) {
1211 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_SIGBUS;
1213 }
de151cf6
JB		 1214 }
1215
1216 /* Need a new fence register? */
a09ba7fa 1217 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1218 ret = i915_gem_object_get_fence_reg(obj);
7d8d58b2
CW		 1219 if (ret) {
1220 mutex_unlock(&dev->struct_mutex);
d9ddcb96 1221 return VM_FAULT_SIGBUS;
7d8d58b2 1222 }
d9ddcb96 1223 }
de151cf6
JB		 1224
1225 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1226 page_offset;
1227
1228 /* Finally, remap it using the new GTT offset */
1229 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1230
1231 mutex_unlock(&dev->struct_mutex);
1232
1233 switch (ret) {
1234 case -ENOMEM:
1235 case -EAGAIN:
1236 return VM_FAULT_OOM;
1237 case -EFAULT:
959b887c 1238 case -EINVAL:
de151cf6
JB		 1239 return VM_FAULT_SIGBUS;
1240 default:
1241 return VM_FAULT_NOPAGE;
1242 }
1243}
1244
1245/**
1246 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1247 * @obj: obj in question
1248 *
1249 * GEM memory mapping works by handing back to userspace a fake mmap offset
1250 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1251 * up the object based on the offset and sets up the various memory mapping
1252 * structures.
1253 *
1254 * This routine allocates and attaches a fake offset for @obj.
1255 */
1256static int
1257i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1258{
1259 struct drm_device *dev = obj->dev;
1260 struct drm_gem_mm *mm = dev->mm_private;
1261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262 struct drm_map_list *list;
f77d390c 1263 struct drm_local_map *map;
de151cf6
JB		 1264 int ret = 0;
1265
1266 /* Set the object up for mmap'ing */
1267 list = &obj->map_list;
9a298b2a 1268 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1269 if (!list->map)
1270 return -ENOMEM;
1271
1272 map = list->map;
1273 map->type = _DRM_GEM;
1274 map->size = obj->size;
1275 map->handle = obj;
1276
1277 /* Get a DRM GEM mmap offset allocated... */
1278 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1279 obj->size / PAGE_SIZE, 0, 0);
1280 if (!list->file_offset_node) {
1281 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1282 ret = -ENOMEM;
1283 goto out_free_list;
1284 }
1285
1286 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1287 obj->size / PAGE_SIZE, 0);
1288 if (!list->file_offset_node) {
1289 ret = -ENOMEM;
1290 goto out_free_list;
1291 }
1292
1293 list->hash.key = list->file_offset_node->start;
1294 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1295 DRM_ERROR("failed to add to map hash\n");
1296 goto out_free_mm;
1297 }
1298
1299 /* By now we should be all set, any drm_mmap request on the offset
1300 * below will get to our mmap & fault handler */
1301 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1302
1303 return 0;
1304
1305out_free_mm:
1306 drm_mm_put_block(list->file_offset_node);
1307out_free_list:
9a298b2a 1308 kfree(list->map);
de151cf6
JB		 1309
1310 return ret;
1311}
1312
901782b2
CW		 1313/**
1314 * i915_gem_release_mmap - remove physical page mappings
1315 * @obj: obj in question
1316 *
1317 * Preserve the reservation of the mmaping with the DRM core code, but
1318 * relinquish ownership of the pages back to the system.
1319 *
1320 * It is vital that we remove the page mapping if we have mapped a tiled
1321 * object through the GTT and then lose the fence register due to
1322 * resource pressure. Similarly if the object has been moved out of the
1323 * aperture, than pages mapped into userspace must be revoked. Removing the
1324 * mapping will then trigger a page fault on the next user access, allowing
1325 * fixup by i915_gem_fault().
1326 */
d05ca301 1327void
901782b2
CW		 1328i915_gem_release_mmap(struct drm_gem_object *obj)
1329{
1330 struct drm_device *dev = obj->dev;
1331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1332
1333 if (dev->dev_mapping)
1334 unmap_mapping_range(dev->dev_mapping,
1335 obj_priv->mmap_offset, obj->size, 1);
1336}
1337
ab00b3e5
JB		 1338static void
1339i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1340{
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1343 struct drm_gem_mm *mm = dev->mm_private;
1344 struct drm_map_list *list;
1345
1346 list = &obj->map_list;
1347 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1348
1349 if (list->file_offset_node) {
1350 drm_mm_put_block(list->file_offset_node);
1351 list->file_offset_node = NULL;
1352 }
1353
1354 if (list->map) {
9a298b2a 1355 kfree(list->map);
ab00b3e5
JB		 1356 list->map = NULL;
1357 }
1358
1359 obj_priv->mmap_offset = 0;
1360}
1361
de151cf6
JB		 1362/**
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1365 *
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping if needed.
1368 */
1369static uint32_t
1370i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1371{
1372 struct drm_device *dev = obj->dev;
1373 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1374 int start, i;
1375
1376 /*
1377 * Minimum alignment is 4k (GTT page size), but might be greater
1378 * if a fence register is needed for the object.
1379 */
1380 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1381 return 4096;
1382
1383 /*
1384 * Previous chips need to be aligned to the size of the smallest
1385 * fence register that can contain the object.
1386 */
1387 if (IS_I9XX(dev))
1388 start = 1024*1024;
1389 else
1390 start = 512*1024;
1391
1392 for (i = start; i < obj->size; i <<= 1)
1393 ;
1394
1395 return i;
1396}
1397
1398/**
1399 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1400 * @dev: DRM device
1401 * @data: GTT mapping ioctl data
1402 * @file_priv: GEM object info
1403 *
1404 * Simply returns the fake offset to userspace so it can mmap it.
1405 * The mmap call will end up in drm_gem_mmap(), which will set things
1406 * up so we can get faults in the handler above.
1407 *
1408 * The fault handler will take care of binding the object into the GTT
1409 * (since it may have been evicted to make room for something), allocating
1410 * a fence register, and mapping the appropriate aperture address into
1411 * userspace.
1412 */
1413int
1414i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1416{
1417 struct drm_i915_gem_mmap_gtt *args = data;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct drm_gem_object *obj;
1420 struct drm_i915_gem_object *obj_priv;
1421 int ret;
1422
1423 if (!(dev->driver->driver_features & DRIVER_GEM))
1424 return -ENODEV;
1425
1426 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1427 if (obj == NULL)
1428 return -EBADF;
1429
1430 mutex_lock(&dev->struct_mutex);
1431
1432 obj_priv = obj->driver_private;
1433
1434 if (!obj_priv->mmap_offset) {
1435 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1436 if (ret) {
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
de151cf6 1439 return ret;
13af1062 1440 }
de151cf6
JB		 1441 }
1442
1443 args->offset = obj_priv->mmap_offset;
1444
de151cf6
JB		 1445 /*
1446 * Pull it into the GTT so that we have a page list (makes the
1447 * initial fault faster and any subsequent flushing possible).
1448 */
1449 if (!obj_priv->agp_mem) {
e67b8ce1 1450 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1451 if (ret) {
1452 drm_gem_object_unreference(obj);
1453 mutex_unlock(&dev->struct_mutex);
1454 return ret;
1455 }
14b60391 1456 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1457 }
1458
1459 drm_gem_object_unreference(obj);
1460 mutex_unlock(&dev->struct_mutex);
1461
1462 return 0;
1463}
1464
6911a9b8 1465void
856fa198 1466i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b
EA		 1467{
1468 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1469 int page_count = obj->size / PAGE_SIZE;
1470 int i;
1471
856fa198 1472 BUG_ON(obj_priv->pages_refcount == 0);
673a394b 1473
856fa198
EA		 1474 if (--obj_priv->pages_refcount != 0)
1475 return;
673a394b 1476
280b713b
EA		 1477 if (obj_priv->tiling_mode != I915_TILING_NONE)
1478 i915_gem_object_save_bit_17_swizzle(obj);
1479
3ef94daa
CW		 1480 if (obj_priv->madv == I915_MADV_DONTNEED)
1481 obj_priv->dirty = 0;
1482
1483 for (i = 0; i < page_count; i++) {
1484 if (obj_priv->pages[i] == NULL)
1485 break;
1486
1487 if (obj_priv->dirty)
1488 set_page_dirty(obj_priv->pages[i]);
1489
1490 if (obj_priv->madv == I915_MADV_WILLNEED)
1491 mark_page_accessed(obj_priv->pages[i]);
1492
1493 page_cache_release(obj_priv->pages[i]);
1494 }
673a394b
EA		 1495 obj_priv->dirty = 0;
1496
8e7d2b2c 1497 drm_free_large(obj_priv->pages);
856fa198 1498 obj_priv->pages = NULL;
673a394b
EA		 1499}
1500
1501static void
ce44b0ea 1502i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
673a394b
EA		 1503{
1504 struct drm_device *dev = obj->dev;
1505 drm_i915_private_t *dev_priv = dev->dev_private;
1506 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1507
1508 /* Add a reference if we're newly entering the active list. */
1509 if (!obj_priv->active) {
1510 drm_gem_object_reference(obj);
1511 obj_priv->active = 1;
1512 }
1513 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1514 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1515 list_move_tail(&obj_priv->list,
1516 &dev_priv->mm.active_list);
5e118f41 1517 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1518 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1519}
1520
ce44b0ea
EA		 1521static void
1522i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1523{
1524 struct drm_device *dev = obj->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
1526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1527
1528 BUG_ON(!obj_priv->active);
1529 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1530 obj_priv->last_rendering_seqno = 0;
1531}
673a394b
EA		 1532
1533static void
1534i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1535{
1536 struct drm_device *dev = obj->dev;
1537 drm_i915_private_t *dev_priv = dev->dev_private;
1538 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1539
1540 i915_verify_inactive(dev, __FILE__, __LINE__);
1541 if (obj_priv->pin_count != 0)
1542 list_del_init(&obj_priv->list);
1543 else
1544 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1545
ce44b0ea 1546 obj_priv->last_rendering_seqno = 0;
673a394b
EA		 1547 if (obj_priv->active) {
1548 obj_priv->active = 0;
1549 drm_gem_object_unreference(obj);
1550 }
1551 i915_verify_inactive(dev, __FILE__, __LINE__);
1552}
1553
1554/**
1555 * Creates a new sequence number, emitting a write of it to the status page
1556 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1557 *
1558 * Must be called with struct_lock held.
1559 *
1560 * Returned sequence numbers are nonzero on success.
1561 */
1562static uint32_t
b962442e
EA		 1563i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1564 uint32_t flush_domains)
673a394b
EA		 1565{
1566 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1567 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1568 struct drm_i915_gem_request *request;
1569 uint32_t seqno;
1570 int was_empty;
1571 RING_LOCALS;
1572
b962442e
EA		 1573 if (file_priv != NULL)
1574 i915_file_priv = file_priv->driver_priv;
1575
9a298b2a 1576 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1577 if (request == NULL)
1578 return 0;
1579
1580 /* Grab the seqno we're going to make this request be, and bump the
1581 * next (skipping 0 so it can be the reserved no-seqno value).
1582 */
1583 seqno = dev_priv->mm.next_gem_seqno;
1584 dev_priv->mm.next_gem_seqno++;
1585 if (dev_priv->mm.next_gem_seqno == 0)
1586 dev_priv->mm.next_gem_seqno++;
1587
1588 BEGIN_LP_RING(4);
1589 OUT_RING(MI_STORE_DWORD_INDEX);
1590 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1591 OUT_RING(seqno);
1592
1593 OUT_RING(MI_USER_INTERRUPT);
1594 ADVANCE_LP_RING();
1595
1596 DRM_DEBUG("%d\n", seqno);
1597
1598 request->seqno = seqno;
1599 request->emitted_jiffies = jiffies;
673a394b
EA		 1600 was_empty = list_empty(&dev_priv->mm.request_list);
1601 list_add_tail(&request->list, &dev_priv->mm.request_list);
b962442e
EA		 1602 if (i915_file_priv) {
1603 list_add_tail(&request->client_list,
1604 &i915_file_priv->mm.request_list);
1605 } else {
1606 INIT_LIST_HEAD(&request->client_list);
1607 }
673a394b 1608
ce44b0ea
EA		 1609 /* Associate any objects on the flushing list matching the write
1610 * domain we're flushing with our flush.
1611 */
1612 if (flush_domains != 0) {
1613 struct drm_i915_gem_object *obj_priv, *next;
1614
1615 list_for_each_entry_safe(obj_priv, next,
1616 &dev_priv->mm.flushing_list, list) {
1617 struct drm_gem_object *obj = obj_priv->obj;
1618
1619 if ((obj->write_domain & flush_domains) ==
1620 obj->write_domain) {
1c5d22f7
CW		 1621 uint32_t old_write_domain = obj->write_domain;
1622
ce44b0ea
EA		 1623 obj->write_domain = 0;
1624 i915_gem_object_move_to_active(obj, seqno);
1c5d22f7
CW		 1625
1626 trace_i915_gem_object_change_domain(obj,
1627 obj->read_domains,
1628 old_write_domain);
ce44b0ea
EA		 1629 }
1630 }
1631
1632 }
1633
f65d9421
BG		 1634 if (!dev_priv->mm.suspended) {
1635 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1636 if (was_empty)
1637 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1638 }
673a394b
EA		 1639 return seqno;
1640}
1641
1642/**
1643 * Command execution barrier
1644 *
1645 * Ensures that all commands in the ring are finished
1646 * before signalling the CPU
1647 */
3043c60c 1648static uint32_t
673a394b
EA		 1649i915_retire_commands(struct drm_device *dev)
1650{
1651 drm_i915_private_t *dev_priv = dev->dev_private;
1652 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1653 uint32_t flush_domains = 0;
1654 RING_LOCALS;
1655
1656 /* The sampler always gets flushed on i965 (sigh) */
1657 if (IS_I965G(dev))
1658 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1659 BEGIN_LP_RING(2);
1660 OUT_RING(cmd);
1661 OUT_RING(0); /* noop */
1662 ADVANCE_LP_RING();
1663 return flush_domains;
1664}
1665
1666/**
1667 * Moves buffers associated only with the given active seqno from the active
1668 * to inactive list, potentially freeing them.
1669 */
1670static void
1671i915_gem_retire_request(struct drm_device *dev,
1672 struct drm_i915_gem_request *request)
1673{
1674 drm_i915_private_t *dev_priv = dev->dev_private;
1675
1c5d22f7
CW		 1676 trace_i915_gem_request_retire(dev, request->seqno);
1677
673a394b
EA		 1678 /* Move any buffers on the active list that are no longer referenced
1679 * by the ringbuffer to the flushing/inactive lists as appropriate.
1680 */
5e118f41 1681 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1682 while (!list_empty(&dev_priv->mm.active_list)) {
1683 struct drm_gem_object *obj;
1684 struct drm_i915_gem_object *obj_priv;
1685
1686 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1687 struct drm_i915_gem_object,
1688 list);
1689 obj = obj_priv->obj;
1690
1691 /* If the seqno being retired doesn't match the oldest in the
1692 * list, then the oldest in the list must still be newer than
1693 * this seqno.
1694 */
1695 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1696 goto out;
de151cf6 1697
673a394b
EA		 1698#if WATCH_LRU
1699 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1700 __func__, request->seqno, obj);
1701#endif
1702
ce44b0ea
EA		 1703 if (obj->write_domain != 0)
1704 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1705 else {
1706 /* Take a reference on the object so it won't be
1707 * freed while the spinlock is held. The list
1708 * protection for this spinlock is safe when breaking
1709 * the lock like this since the next thing we do
1710 * is just get the head of the list again.
1711 */
1712 drm_gem_object_reference(obj);
673a394b 1713 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1714 spin_unlock(&dev_priv->mm.active_list_lock);
1715 drm_gem_object_unreference(obj);
1716 spin_lock(&dev_priv->mm.active_list_lock);
1717 }
673a394b 1718 }
5e118f41
CW		 1719out:
1720 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1721}
1722
1723/**
1724 * Returns true if seq1 is later than seq2.
1725 */
22be1724 1726bool
673a394b
EA		 1727i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1728{
1729 return (int32_t)(seq1 - seq2) >= 0;
1730}
1731
1732uint32_t
1733i915_get_gem_seqno(struct drm_device *dev)
1734{
1735 drm_i915_private_t *dev_priv = dev->dev_private;
1736
1737 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1738}
1739
1740/**
1741 * This function clears the request list as sequence numbers are passed.
1742 */
1743void
1744i915_gem_retire_requests(struct drm_device *dev)
1745{
1746 drm_i915_private_t *dev_priv = dev->dev_private;
1747 uint32_t seqno;
1748
6c0594a3
KW		 1749 if (!dev_priv->hw_status_page)
1750 return;
1751
673a394b
EA		 1752 seqno = i915_get_gem_seqno(dev);
1753
1754 while (!list_empty(&dev_priv->mm.request_list)) {
1755 struct drm_i915_gem_request *request;
1756 uint32_t retiring_seqno;
1757
1758 request = list_first_entry(&dev_priv->mm.request_list,
1759 struct drm_i915_gem_request,
1760 list);
1761 retiring_seqno = request->seqno;
1762
1763 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1764 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1765 i915_gem_retire_request(dev, request);
1766
1767 list_del(&request->list);
b962442e 1768 list_del(&request->client_list);
9a298b2a 1769 kfree(request);
673a394b
EA		 1770 } else
1771 break;
1772 }
1773}
1774
1775void
1776i915_gem_retire_work_handler(struct work_struct *work)
1777{
1778 drm_i915_private_t *dev_priv;
1779 struct drm_device *dev;
1780
1781 dev_priv = container_of(work, drm_i915_private_t,
1782 mm.retire_work.work);
1783 dev = dev_priv->dev;
1784
1785 mutex_lock(&dev->struct_mutex);
1786 i915_gem_retire_requests(dev);
6dbe2772
KP		 1787 if (!dev_priv->mm.suspended &&
1788 !list_empty(&dev_priv->mm.request_list))
9c9fe1f8 1789 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1790 mutex_unlock(&dev->struct_mutex);
1791}
1792
1793/**
1794 * Waits for a sequence number to be signaled, and cleans up the
1795 * request and object lists appropriately for that event.
1796 */
3043c60c 1797static int
673a394b
EA		 1798i915_wait_request(struct drm_device *dev, uint32_t seqno)
1799{
1800 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1801 u32 ier;
673a394b
EA		 1802 int ret = 0;
1803
1804 BUG_ON(seqno == 0);
1805
ba1234d1 1806 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1807 return -EIO;
1808
673a394b 1809 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
036a4a7d
ZW		 1810 if (IS_IGDNG(dev))
1811 ier = I915_READ(DEIER) | I915_READ(GTIER);
1812 else
1813 ier = I915_READ(IER);
802c7eb6
JB		 1814 if (!ier) {
1815 DRM_ERROR("something (likely vbetool) disabled "
1816 "interrupts, re-enabling\n");
1817 i915_driver_irq_preinstall(dev);
1818 i915_driver_irq_postinstall(dev);
1819 }
1820
1c5d22f7
CW		 1821 trace_i915_gem_request_wait_begin(dev, seqno);
1822
673a394b
EA		 1823 dev_priv->mm.waiting_gem_seqno = seqno;
1824 i915_user_irq_get(dev);
1825 ret = wait_event_interruptible(dev_priv->irq_queue,
1826 i915_seqno_passed(i915_get_gem_seqno(dev),
1827 seqno) ||
ba1234d1 1828 atomic_read(&dev_priv->mm.wedged));
673a394b
EA		 1829 i915_user_irq_put(dev);
1830 dev_priv->mm.waiting_gem_seqno = 0;
1c5d22f7
CW		 1831
1832 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1833 }
ba1234d1 1834 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1835 ret = -EIO;
1836
1837 if (ret && ret != -ERESTARTSYS)
1838 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1839 __func__, ret, seqno, i915_get_gem_seqno(dev));
1840
1841 /* Directly dispatch request retiring. While we have the work queue
1842 * to handle this, the waiter on a request often wants an associated
1843 * buffer to have made it to the inactive list, and we would need
1844 * a separate wait queue to handle that.
1845 */
1846 if (ret == 0)
1847 i915_gem_retire_requests(dev);
1848
1849 return ret;
1850}
1851
1852static void
1853i915_gem_flush(struct drm_device *dev,
1854 uint32_t invalidate_domains,
1855 uint32_t flush_domains)
1856{
1857 drm_i915_private_t *dev_priv = dev->dev_private;
1858 uint32_t cmd;
1859 RING_LOCALS;
1860
1861#if WATCH_EXEC
1862 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1863 invalidate_domains, flush_domains);
1864#endif
1c5d22f7
CW		 1865 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1866 invalidate_domains, flush_domains);
673a394b
EA		 1867
1868 if (flush_domains & I915_GEM_DOMAIN_CPU)
1869 drm_agp_chipset_flush(dev);
1870
21d509e3 1871 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
673a394b
EA		 1872 /*
1873 * read/write caches:
1874 *
1875 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1876 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1877 * also flushed at 2d versus 3d pipeline switches.
1878 *
1879 * read-only caches:
1880 *
1881 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1882 * MI_READ_FLUSH is set, and is always flushed on 965.
1883 *
1884 * I915_GEM_DOMAIN_COMMAND may not exist?
1885 *
1886 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1887 * invalidated when MI_EXE_FLUSH is set.
1888 *
1889 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1890 * invalidated with every MI_FLUSH.
1891 *
1892 * TLBs:
1893 *
1894 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1895 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1896 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1897 * are flushed at any MI_FLUSH.
1898 */
1899
1900 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1901 if ((invalidate_domains|flush_domains) &
1902 I915_GEM_DOMAIN_RENDER)
1903 cmd &= ~MI_NO_WRITE_FLUSH;
1904 if (!IS_I965G(dev)) {
1905 /*
1906 * On the 965, the sampler cache always gets flushed
1907 * and this bit is reserved.
1908 */
1909 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1910 cmd |= MI_READ_FLUSH;
1911 }
1912 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1913 cmd |= MI_EXE_FLUSH;
1914
1915#if WATCH_EXEC
1916 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1917#endif
1918 BEGIN_LP_RING(2);
1919 OUT_RING(cmd);
1920 OUT_RING(0); /* noop */
1921 ADVANCE_LP_RING();
1922 }
1923}
1924
1925/**
1926 * Ensures that all rendering to the object has completed and the object is
1927 * safe to unbind from the GTT or access from the CPU.
1928 */
1929static int
1930i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1931{
1932 struct drm_device *dev = obj->dev;
1933 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1934 int ret;
1935
e47c68e9
EA		 1936 /* This function only exists to support waiting for existing rendering,
1937 * not for emitting required flushes.
673a394b 1938 */
e47c68e9 1939 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1940
1941 /* If there is rendering queued on the buffer being evicted, wait for
1942 * it.
1943 */
1944 if (obj_priv->active) {
1945#if WATCH_BUF
1946 DRM_INFO("%s: object %p wait for seqno %08x\n",
1947 __func__, obj, obj_priv->last_rendering_seqno);
1948#endif
1949 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1950 if (ret != 0)
1951 return ret;
1952 }
1953
1954 return 0;
1955}
1956
1957/**
1958 * Unbinds an object from the GTT aperture.
1959 */
0f973f27 1960int
673a394b
EA		 1961i915_gem_object_unbind(struct drm_gem_object *obj)
1962{
1963 struct drm_device *dev = obj->dev;
1964 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1965 int ret = 0;
1966
1967#if WATCH_BUF
1968 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1969 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1970#endif
1971 if (obj_priv->gtt_space == NULL)
1972 return 0;
1973
1974 if (obj_priv->pin_count != 0) {
1975 DRM_ERROR("Attempting to unbind pinned buffer\n");
1976 return -EINVAL;
1977 }
1978
5323fd04
EA		 1979 /* blow away mappings if mapped through GTT */
1980 i915_gem_release_mmap(obj);
1981
1982 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1983 i915_gem_clear_fence_reg(obj);
1984
673a394b
EA		 1985 /* Move the object to the CPU domain to ensure that
1986 * any possible CPU writes while it's not in the GTT
1987 * are flushed when we go to remap it. This will
1988 * also ensure that all pending GPU writes are finished
1989 * before we unbind.
1990 */
e47c68e9 1991 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 1992 if (ret) {
e47c68e9
EA		 1993 if (ret != -ERESTARTSYS)
1994 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 1995 return ret;
1996 }
1997
5323fd04
EA		 1998 BUG_ON(obj_priv->active);
1999
673a394b
EA		 2000 if (obj_priv->agp_mem != NULL) {
2001 drm_unbind_agp(obj_priv->agp_mem);
2002 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2003 obj_priv->agp_mem = NULL;
2004 }
2005
856fa198 2006 i915_gem_object_put_pages(obj);
673a394b
EA		 2007
2008 if (obj_priv->gtt_space) {
2009 atomic_dec(&dev->gtt_count);
2010 atomic_sub(obj->size, &dev->gtt_memory);
2011
2012 drm_mm_put_block(obj_priv->gtt_space);
2013 obj_priv->gtt_space = NULL;
2014 }
2015
2016 /* Remove ourselves from the LRU list if present. */
2017 if (!list_empty(&obj_priv->list))
2018 list_del_init(&obj_priv->list);
2019
1c5d22f7
CW		 2020 trace_i915_gem_object_unbind(obj);
2021
673a394b
EA		 2022 return 0;
2023}
2024
07f73f69
CW		 2025static inline int
2026i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
2027{
2028 return !obj_priv->dirty || obj_priv->madv == I915_MADV_DONTNEED;
2029}
2030
2031static struct drm_gem_object *
2032i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2033{
2034 drm_i915_private_t *dev_priv = dev->dev_private;
2035 struct drm_i915_gem_object *obj_priv;
2036 struct drm_gem_object *best = NULL;
2037 struct drm_gem_object *first = NULL;
2038
2039 /* Try to find the smallest clean object */
2040 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2041 struct drm_gem_object *obj = obj_priv->obj;
2042 if (obj->size >= min_size) {
2043 if (i915_gem_object_is_purgeable(obj_priv) &&
2044 (!best || obj->size < best->size)) {
2045 best = obj;
2046 if (best->size == min_size)
2047 return best;
2048 }
2049 if (!first)
2050 first = obj;
2051 }
2052 }
2053
2054 return best ? best : first;
2055}
2056
2057static int
2058i915_gem_evict_everything(struct drm_device *dev)
2059{
2060 drm_i915_private_t *dev_priv = dev->dev_private;
2061 uint32_t seqno;
2062 int ret;
2063 bool lists_empty;
2064
2065 DRM_INFO("GTT full, evicting everything: "
2066 "%d objects [%d pinned], "
2067 "%d object bytes [%d pinned], "
2068 "%d/%d gtt bytes\n",
2069 atomic_read(&dev->object_count),
2070 atomic_read(&dev->pin_count),
2071 atomic_read(&dev->object_memory),
2072 atomic_read(&dev->pin_memory),
2073 atomic_read(&dev->gtt_memory),
2074 dev->gtt_total);
2075
2076 spin_lock(&dev_priv->mm.active_list_lock);
2077 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2078 list_empty(&dev_priv->mm.flushing_list) &&
2079 list_empty(&dev_priv->mm.active_list));
2080 spin_unlock(&dev_priv->mm.active_list_lock);
2081
2082 if (lists_empty) {
2083 DRM_ERROR("GTT full, but lists empty!\n");
2084 return -ENOSPC;
2085 }
2086
2087 /* Flush everything (on to the inactive lists) and evict */
2088 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2089 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2090 if (seqno == 0)
2091 return -ENOMEM;
2092
2093 ret = i915_wait_request(dev, seqno);
2094 if (ret)
2095 return ret;
2096
ab5ee576 2097 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2098 if (ret)
2099 return ret;
2100
2101 spin_lock(&dev_priv->mm.active_list_lock);
2102 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2103 list_empty(&dev_priv->mm.flushing_list) &&
2104 list_empty(&dev_priv->mm.active_list));
2105 spin_unlock(&dev_priv->mm.active_list_lock);
2106 BUG_ON(!lists_empty);
2107
2108 return 0;
2109}
2110
673a394b 2111static int
07f73f69 2112i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2113{
2114 drm_i915_private_t *dev_priv = dev->dev_private;
2115 struct drm_gem_object *obj;
07f73f69 2116 int ret;
673a394b
EA		 2117
2118 for (;;) {
07f73f69
CW		 2119 i915_gem_retire_requests(dev);
2120
673a394b
EA		 2121 /* If there's an inactive buffer available now, grab it
2122 * and be done.
2123 */
07f73f69
CW		 2124 obj = i915_gem_find_inactive_object(dev, min_size);
2125 if (obj) {
2126 struct drm_i915_gem_object *obj_priv;
2127
673a394b
EA		 2128#if WATCH_LRU
2129 DRM_INFO("%s: evicting %p\n", __func__, obj);
2130#endif
07f73f69
CW		 2131 obj_priv = obj->driver_private;
2132 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2133 BUG_ON(obj_priv->active);
2134
2135 /* Wait on the rendering and unbind the buffer. */
07f73f69 2136 return i915_gem_object_unbind(obj);
673a394b
EA		 2137 }
2138
2139 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2140 * things, wait for the next to finish and hopefully leave us
2141 * a buffer to evict.
673a394b
EA		 2142 */
2143 if (!list_empty(&dev_priv->mm.request_list)) {
2144 struct drm_i915_gem_request *request;
2145
2146 request = list_first_entry(&dev_priv->mm.request_list,
2147 struct drm_i915_gem_request,
2148 list);
2149
2150 ret = i915_wait_request(dev, request->seqno);
2151 if (ret)
07f73f69 2152 return ret;
673a394b 2153
07f73f69 2154 continue;
673a394b
EA		 2155 }
2156
2157 /* If we didn't have anything on the request list but there
2158 * are buffers awaiting a flush, emit one and try again.
2159 * When we wait on it, those buffers waiting for that flush
2160 * will get moved to inactive.
2161 */
2162 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2163 struct drm_i915_gem_object *obj_priv;
07f73f69 2164
9a1e2582
CW		 2165 /* Find an object that we can immediately reuse */
2166 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2167 obj = obj_priv->obj;
2168 if (obj->size >= min_size)
2169 break;
673a394b 2170
9a1e2582
CW		 2171 obj = NULL;
2172 }
07f73f69 2173
9a1e2582
CW		 2174 if (obj != NULL) {
2175 uint32_t seqno;
673a394b 2176
9a1e2582
CW		 2177 i915_gem_flush(dev,
2178 obj->write_domain,
2179 obj->write_domain);
2180 seqno = i915_add_request(dev, NULL, obj->write_domain);
2181 if (seqno == 0)
2182 return -ENOMEM;
2183
2184 ret = i915_wait_request(dev, seqno);
2185 if (ret)
2186 return ret;
2187
2188 continue;
2189 }
673a394b
EA		 2190 }
2191
07f73f69
CW		 2192 /* If we didn't do any of the above, there's no single buffer
2193 * large enough to swap out for the new one, so just evict
2194 * everything and start again. (This should be rare.)
673a394b 2195 */
07f73f69
CW		 2196 if (!list_empty (&dev_priv->mm.inactive_list)) {
2197 DRM_INFO("GTT full, evicting inactive buffers\n");
ab5ee576 2198 return i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2199 } else
2200 return i915_gem_evict_everything(dev);
ac94a962 2201 }
ac94a962
KP		 2202}
2203
6911a9b8 2204int
856fa198 2205i915_gem_object_get_pages(struct drm_gem_object *obj)
673a394b
EA		 2206{
2207 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2208 int page_count, i;
2209 struct address_space *mapping;
2210 struct inode *inode;
2211 struct page *page;
2212 int ret;
2213
856fa198 2214 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2215 return 0;
2216
2217 /* Get the list of pages out of our struct file. They'll be pinned
2218 * at this point until we release them.
2219 */
2220 page_count = obj->size / PAGE_SIZE;
856fa198 2221 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2222 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2223 if (obj_priv->pages == NULL) {
07f73f69 2224 DRM_ERROR("Failed to allocate page list\n");
856fa198 2225 obj_priv->pages_refcount--;
673a394b
EA		 2226 return -ENOMEM;
2227 }
2228
2229 inode = obj->filp->f_path.dentry->d_inode;
2230 mapping = inode->i_mapping;
2231 for (i = 0; i < page_count; i++) {
2232 page = read_mapping_page(mapping, i, NULL);
2233 if (IS_ERR(page)) {
2234 ret = PTR_ERR(page);
856fa198 2235 i915_gem_object_put_pages(obj);
673a394b
EA		 2236 return ret;
2237 }
856fa198 2238 obj_priv->pages[i] = page;
673a394b 2239 }
280b713b
EA		 2240
2241 if (obj_priv->tiling_mode != I915_TILING_NONE)
2242 i915_gem_object_do_bit_17_swizzle(obj);
2243
673a394b
EA		 2244 return 0;
2245}
2246
de151cf6
JB		 2247static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2248{
2249 struct drm_gem_object *obj = reg->obj;
2250 struct drm_device *dev = obj->dev;
2251 drm_i915_private_t *dev_priv = dev->dev_private;
2252 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2253 int regnum = obj_priv->fence_reg;
2254 uint64_t val;
2255
2256 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2257 0xfffff000) << 32;
2258 val |= obj_priv->gtt_offset & 0xfffff000;
2259 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2260 if (obj_priv->tiling_mode == I915_TILING_Y)
2261 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2262 val |= I965_FENCE_REG_VALID;
2263
2264 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2265}
2266
2267static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2268{
2269 struct drm_gem_object *obj = reg->obj;
2270 struct drm_device *dev = obj->dev;
2271 drm_i915_private_t *dev_priv = dev->dev_private;
2272 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2273 int regnum = obj_priv->fence_reg;
0f973f27 2274 int tile_width;
dc529a4f 2275 uint32_t fence_reg, val;
de151cf6
JB		 2276 uint32_t pitch_val;
2277
2278 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2279 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2280 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2281 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2282 return;
2283 }
2284
0f973f27
JB		 2285 if (obj_priv->tiling_mode == I915_TILING_Y &&
2286 HAS_128_BYTE_Y_TILING(dev))
2287 tile_width = 128;
de151cf6 2288 else
0f973f27
JB		 2289 tile_width = 512;
2290
2291 /* Note: pitch better be a power of two tile widths */
2292 pitch_val = obj_priv->stride / tile_width;
2293 pitch_val = ffs(pitch_val) - 1;
de151cf6
JB		 2294
2295 val = obj_priv->gtt_offset;
2296 if (obj_priv->tiling_mode == I915_TILING_Y)
2297 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2298 val |= I915_FENCE_SIZE_BITS(obj->size);
2299 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2300 val |= I830_FENCE_REG_VALID;
2301
dc529a4f
EA		 2302 if (regnum < 8)
2303 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2304 else
2305 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2306 I915_WRITE(fence_reg, val);
de151cf6
JB		 2307}
2308
2309static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2310{
2311 struct drm_gem_object *obj = reg->obj;
2312 struct drm_device *dev = obj->dev;
2313 drm_i915_private_t *dev_priv = dev->dev_private;
2314 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2315 int regnum = obj_priv->fence_reg;
2316 uint32_t val;
2317 uint32_t pitch_val;
8d7773a3 2318 uint32_t fence_size_bits;
de151cf6 2319
8d7773a3 2320 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2321 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2322 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2323 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2324 return;
2325 }
2326
e76a16de
EA		 2327 pitch_val = obj_priv->stride / 128;
2328 pitch_val = ffs(pitch_val) - 1;
2329 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2330
de151cf6
JB		 2331 val = obj_priv->gtt_offset;
2332 if (obj_priv->tiling_mode == I915_TILING_Y)
2333 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2334 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2335 WARN_ON(fence_size_bits & ~0x00000f00);
2336 val |= fence_size_bits;
de151cf6
JB		 2337 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2338 val |= I830_FENCE_REG_VALID;
2339
2340 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2341}
2342
2343/**
2344 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2345 * @obj: object to map through a fence reg
2346 *
2347 * When mapping objects through the GTT, userspace wants to be able to write
2348 * to them without having to worry about swizzling if the object is tiled.
2349 *
2350 * This function walks the fence regs looking for a free one for @obj,
2351 * stealing one if it can't find any.
2352 *
2353 * It then sets up the reg based on the object's properties: address, pitch
2354 * and tiling format.
2355 */
8c4b8c3f
CW		 2356int
2357i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2358{
2359 struct drm_device *dev = obj->dev;
79e53945 2360 struct drm_i915_private *dev_priv = dev->dev_private;
de151cf6
JB		 2361 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2362 struct drm_i915_fence_reg *reg = NULL;
fc7170ba
CW		 2363 struct drm_i915_gem_object *old_obj_priv = NULL;
2364 int i, ret, avail;
de151cf6 2365
a09ba7fa
EA		 2366 /* Just update our place in the LRU if our fence is getting used. */
2367 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2368 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2369 return 0;
2370 }
2371
de151cf6
JB		 2372 switch (obj_priv->tiling_mode) {
2373 case I915_TILING_NONE:
2374 WARN(1, "allocating a fence for non-tiled object?\n");
2375 break;
2376 case I915_TILING_X:
0f973f27
JB		 2377 if (!obj_priv->stride)
2378 return -EINVAL;
2379 WARN((obj_priv->stride & (512 - 1)),
2380 "object 0x%08x is X tiled but has non-512B pitch\n",
2381 obj_priv->gtt_offset);
de151cf6
JB		 2382 break;
2383 case I915_TILING_Y:
0f973f27
JB		 2384 if (!obj_priv->stride)
2385 return -EINVAL;
2386 WARN((obj_priv->stride & (128 - 1)),
2387 "object 0x%08x is Y tiled but has non-128B pitch\n",
2388 obj_priv->gtt_offset);
de151cf6
JB		 2389 break;
2390 }
2391
2392 /* First try to find a free reg */
fc7170ba 2393 avail = 0;
de151cf6
JB		 2394 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2395 reg = &dev_priv->fence_regs[i];
2396 if (!reg->obj)
2397 break;
fc7170ba
CW		 2398
2399 old_obj_priv = reg->obj->driver_private;
2400 if (!old_obj_priv->pin_count)
2401 avail++;
de151cf6
JB		 2402 }
2403
2404 /* None available, try to steal one or wait for a user to finish */
2405 if (i == dev_priv->num_fence_regs) {
a09ba7fa 2406 struct drm_gem_object *old_obj = NULL;
de151cf6 2407
fc7170ba 2408 if (avail == 0)
2939e1f5 2409 return -ENOSPC;
fc7170ba 2410
a09ba7fa
EA		 2411 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2412 fence_list) {
2413 old_obj = old_obj_priv->obj;
d7619c4b
CW		 2414
2415 if (old_obj_priv->pin_count)
2416 continue;
2417
a09ba7fa
EA		 2418 /* Take a reference, as otherwise the wait_rendering
2419 * below may cause the object to get freed out from
2420 * under us.
2421 */
2422 drm_gem_object_reference(old_obj);
2423
d7619c4b
CW		 2424 /* i915 uses fences for GPU access to tiled buffers */
2425 if (IS_I965G(dev) || !old_obj_priv->active)
de151cf6 2426 break;
d7619c4b 2427
a09ba7fa
EA		 2428 /* This brings the object to the head of the LRU if it
2429 * had been written to. The only way this should
2430 * result in us waiting longer than the expected
2431 * optimal amount of time is if there was a
2432 * fence-using buffer later that was read-only.
2433 */
2434 i915_gem_object_flush_gpu_write_domain(old_obj);
2435 ret = i915_gem_object_wait_rendering(old_obj);
58c2fb64
CW		 2436 if (ret != 0) {
2437 drm_gem_object_unreference(old_obj);
d7619c4b 2438 return ret;
de151cf6 2439 }
d7619c4b 2440
a09ba7fa 2441 break;
de151cf6
JB		 2442 }
2443
2444 /*
2445 * Zap this virtual mapping so we can set up a fence again
2446 * for this object next time we need it.
2447 */
58c2fb64
CW		 2448 i915_gem_release_mmap(old_obj);
2449
a09ba7fa 2450 i = old_obj_priv->fence_reg;
58c2fb64
CW		 2451 reg = &dev_priv->fence_regs[i];
2452
de151cf6 2453 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2454 list_del_init(&old_obj_priv->fence_list);
58c2fb64 2455
a09ba7fa 2456 drm_gem_object_unreference(old_obj);
de151cf6
JB		 2457 }
2458
2459 obj_priv->fence_reg = i;
a09ba7fa
EA		 2460 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2461
de151cf6
JB		 2462 reg->obj = obj;
2463
2464 if (IS_I965G(dev))
2465 i965_write_fence_reg(reg);
2466 else if (IS_I9XX(dev))
2467 i915_write_fence_reg(reg);
2468 else
2469 i830_write_fence_reg(reg);
d9ddcb96 2470
1c5d22f7
CW		 2471 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2472
d9ddcb96 2473 return 0;
de151cf6
JB		 2474}
2475
2476/**
2477 * i915_gem_clear_fence_reg - clear out fence register info
2478 * @obj: object to clear
2479 *
2480 * Zeroes out the fence register itself and clears out the associated
2481 * data structures in dev_priv and obj_priv.
2482 */
2483static void
2484i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2485{
2486 struct drm_device *dev = obj->dev;
79e53945 2487 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6
JB		 2488 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2489
2490 if (IS_I965G(dev))
2491 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
dc529a4f
EA		 2492 else {
2493 uint32_t fence_reg;
2494
2495 if (obj_priv->fence_reg < 8)
2496 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2497 else
2498 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2499 8) * 4;
2500
2501 I915_WRITE(fence_reg, 0);
2502 }
de151cf6
JB		 2503
2504 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2505 obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2506 list_del_init(&obj_priv->fence_list);
de151cf6
JB		 2507}
2508
52dc7d32
CW		 2509/**
2510 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2511 * to the buffer to finish, and then resets the fence register.
2512 * @obj: tiled object holding a fence register.
2513 *
2514 * Zeroes out the fence register itself and clears out the associated
2515 * data structures in dev_priv and obj_priv.
2516 */
2517int
2518i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2519{
2520 struct drm_device *dev = obj->dev;
2521 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2522
2523 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2524 return 0;
2525
2526 /* On the i915, GPU access to tiled buffers is via a fence,
2527 * therefore we must wait for any outstanding access to complete
2528 * before clearing the fence.
2529 */
2530 if (!IS_I965G(dev)) {
2531 int ret;
2532
2533 i915_gem_object_flush_gpu_write_domain(obj);
2534 i915_gem_object_flush_gtt_write_domain(obj);
2535 ret = i915_gem_object_wait_rendering(obj);
2536 if (ret != 0)
2537 return ret;
2538 }
2539
2540 i915_gem_clear_fence_reg (obj);
2541
2542 return 0;
2543}
2544
673a394b
EA		 2545/**
2546 * Finds free space in the GTT aperture and binds the object there.
2547 */
2548static int
2549i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2550{
2551 struct drm_device *dev = obj->dev;
2552 drm_i915_private_t *dev_priv = dev->dev_private;
2553 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2554 struct drm_mm_node *free_space;
07f73f69
CW		 2555 bool retry_alloc = false;
2556 int ret;
673a394b 2557
9bb2d6f9
EA		 2558 if (dev_priv->mm.suspended)
2559 return -EBUSY;
3ef94daa
CW		 2560
2561 if (obj_priv->madv == I915_MADV_DONTNEED) {
2562 DRM_ERROR("Attempting to bind a purgeable object\n");
2563 return -EINVAL;
2564 }
2565
673a394b 2566 if (alignment == 0)
0f973f27 2567 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2568 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2569 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2570 return -EINVAL;
2571 }
2572
2573 search_free:
2574 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2575 obj->size, alignment, 0);
2576 if (free_space != NULL) {
2577 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2578 alignment);
2579 if (obj_priv->gtt_space != NULL) {
2580 obj_priv->gtt_space->private = obj;
2581 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2582 }
2583 }
2584 if (obj_priv->gtt_space == NULL) {
2585 /* If the gtt is empty and we're still having trouble
2586 * fitting our object in, we're out of memory.
2587 */
2588#if WATCH_LRU
2589 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2590#endif
07f73f69 2591 ret = i915_gem_evict_something(dev, obj->size);
673a394b 2592 if (ret != 0) {
ac94a962
KP		 2593 if (ret != -ERESTARTSYS)
2594 DRM_ERROR("Failed to evict a buffer %d\n", ret);
673a394b
EA		 2595 return ret;
2596 }
2597 goto search_free;
2598 }
2599
2600#if WATCH_BUF
cfd43c02 2601 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2602 obj->size, obj_priv->gtt_offset);
2603#endif
07f73f69
CW		 2604 if (retry_alloc) {
2605 i915_gem_object_set_page_gfp_mask (obj,
2606 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2607 }
856fa198 2608 ret = i915_gem_object_get_pages(obj);
07f73f69
CW		 2609 if (retry_alloc) {
2610 i915_gem_object_set_page_gfp_mask (obj,
2611 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2612 }
673a394b
EA		 2613 if (ret) {
2614 drm_mm_put_block(obj_priv->gtt_space);
2615 obj_priv->gtt_space = NULL;
07f73f69
CW		 2616
2617 if (ret == -ENOMEM) {
2618 /* first try to clear up some space from the GTT */
2619 ret = i915_gem_evict_something(dev, obj->size);
2620 if (ret) {
2621 if (ret != -ERESTARTSYS)
2622 DRM_ERROR("Failed to allocate space for backing pages %d\n", ret);
2623
2624 /* now try to shrink everyone else */
2625 if (! retry_alloc) {
2626 retry_alloc = true;
2627 goto search_free;
2628 }
2629
2630 return ret;
2631 }
2632
2633 goto search_free;
2634 }
2635
673a394b
EA		 2636 return ret;
2637 }
2638
673a394b
EA		 2639 /* Create an AGP memory structure pointing at our pages, and bind it
2640 * into the GTT.
2641 */
2642 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2643 obj_priv->pages,
07f73f69 2644 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2645 obj_priv->gtt_offset,
2646 obj_priv->agp_type);
673a394b 2647 if (obj_priv->agp_mem == NULL) {
856fa198 2648 i915_gem_object_put_pages(obj);
673a394b
EA		 2649 drm_mm_put_block(obj_priv->gtt_space);
2650 obj_priv->gtt_space = NULL;
07f73f69
CW		 2651
2652 ret = i915_gem_evict_something(dev, obj->size);
2653 if (ret) {
2654 if (ret != -ERESTARTSYS)
2655 DRM_ERROR("Failed to allocate space to bind AGP: %d\n", ret);
2656 return ret;
2657 }
2658
2659 goto search_free;
673a394b
EA		 2660 }
2661 atomic_inc(&dev->gtt_count);
2662 atomic_add(obj->size, &dev->gtt_memory);
2663
2664 /* Assert that the object is not currently in any GPU domain. As it
2665 * wasn't in the GTT, there shouldn't be any way it could have been in
2666 * a GPU cache
2667 */
21d509e3
CW		 2668 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2669 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2670
1c5d22f7
CW		 2671 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2672
673a394b
EA		 2673 return 0;
2674}
2675
2676void
2677i915_gem_clflush_object(struct drm_gem_object *obj)
2678{
2679 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2680
2681 /* If we don't have a page list set up, then we're not pinned
2682 * to GPU, and we can ignore the cache flush because it'll happen
2683 * again at bind time.
2684 */
856fa198 2685 if (obj_priv->pages == NULL)
673a394b
EA		 2686 return;
2687
1c5d22f7
CW		 2688 trace_i915_gem_object_clflush(obj);
2689
856fa198 2690 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2691}
2692
e47c68e9
EA		 2693/** Flushes any GPU write domain for the object if it's dirty. */
2694static void
2695i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2696{
2697 struct drm_device *dev = obj->dev;
2698 uint32_t seqno;
1c5d22f7 2699 uint32_t old_write_domain;
e47c68e9
EA		 2700
2701 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2702 return;
2703
2704 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2705 old_write_domain = obj->write_domain;
e47c68e9 2706 i915_gem_flush(dev, 0, obj->write_domain);
b962442e 2707 seqno = i915_add_request(dev, NULL, obj->write_domain);
e47c68e9
EA		 2708 obj->write_domain = 0;
2709 i915_gem_object_move_to_active(obj, seqno);
1c5d22f7
CW		 2710
2711 trace_i915_gem_object_change_domain(obj,
2712 obj->read_domains,
2713 old_write_domain);
e47c68e9
EA		 2714}
2715
2716/** Flushes the GTT write domain for the object if it's dirty. */
2717static void
2718i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2719{
1c5d22f7
CW		 2720 uint32_t old_write_domain;
2721
e47c68e9
EA		 2722 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2723 return;
2724
2725 /* No actual flushing is required for the GTT write domain. Writes
2726 * to it immediately go to main memory as far as we know, so there's
2727 * no chipset flush. It also doesn't land in render cache.
2728 */
1c5d22f7 2729 old_write_domain = obj->write_domain;
e47c68e9 2730 obj->write_domain = 0;
1c5d22f7
CW		 2731
2732 trace_i915_gem_object_change_domain(obj,
2733 obj->read_domains,
2734 old_write_domain);
e47c68e9
EA		 2735}
2736
2737/** Flushes the CPU write domain for the object if it's dirty. */
2738static void
2739i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2740{
2741 struct drm_device *dev = obj->dev;
1c5d22f7 2742 uint32_t old_write_domain;
e47c68e9
EA		 2743
2744 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2745 return;
2746
2747 i915_gem_clflush_object(obj);
2748 drm_agp_chipset_flush(dev);
1c5d22f7 2749 old_write_domain = obj->write_domain;
e47c68e9 2750 obj->write_domain = 0;
1c5d22f7
CW		 2751
2752 trace_i915_gem_object_change_domain(obj,
2753 obj->read_domains,
2754 old_write_domain);
e47c68e9
EA		 2755}
2756
2ef7eeaa
EA		 2757/**
2758 * Moves a single object to the GTT read, and possibly write domain.
2759 *
2760 * This function returns when the move is complete, including waiting on
2761 * flushes to occur.
2762 */
79e53945 2763int
2ef7eeaa
EA		 2764i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2765{
2ef7eeaa 2766 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 2767 uint32_t old_write_domain, old_read_domains;
e47c68e9 2768 int ret;
2ef7eeaa 2769
02354392
EA		 2770 /* Not valid to be called on unbound objects. */
2771 if (obj_priv->gtt_space == NULL)
2772 return -EINVAL;
2773
e47c68e9
EA		 2774 i915_gem_object_flush_gpu_write_domain(obj);
2775 /* Wait on any GPU rendering and flushing to occur. */
2776 ret = i915_gem_object_wait_rendering(obj);
2777 if (ret != 0)
2778 return ret;
2779
1c5d22f7
CW		 2780 old_write_domain = obj->write_domain;
2781 old_read_domains = obj->read_domains;
2782
e47c68e9
EA		 2783 /* If we're writing through the GTT domain, then CPU and GPU caches
2784 * will need to be invalidated at next use.
2ef7eeaa 2785 */
e47c68e9
EA		 2786 if (write)
2787 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2788
e47c68e9 2789 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2790
e47c68e9
EA		 2791 /* It should now be out of any other write domains, and we can update
2792 * the domain values for our changes.
2793 */
2794 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2795 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2796 if (write) {
2797 obj->write_domain = I915_GEM_DOMAIN_GTT;
2798 obj_priv->dirty = 1;
2ef7eeaa
EA		 2799 }
2800
1c5d22f7
CW		 2801 trace_i915_gem_object_change_domain(obj,
2802 old_read_domains,
2803 old_write_domain);
2804
e47c68e9
EA		 2805 return 0;
2806}
2807
2808/**
2809 * Moves a single object to the CPU read, and possibly write domain.
2810 *
2811 * This function returns when the move is complete, including waiting on
2812 * flushes to occur.
2813 */
2814static int
2815i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2816{
1c5d22f7 2817 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2818 int ret;
2819
2820 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2821 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2822 ret = i915_gem_object_wait_rendering(obj);
2823 if (ret != 0)
2824 return ret;
2ef7eeaa 2825
e47c68e9 2826 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2827
e47c68e9
EA		 2828 /* If we have a partially-valid cache of the object in the CPU,
2829 * finish invalidating it and free the per-page flags.
2ef7eeaa 2830 */
e47c68e9 2831 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2832
1c5d22f7
CW		 2833 old_write_domain = obj->write_domain;
2834 old_read_domains = obj->read_domains;
2835
e47c68e9
EA		 2836 /* Flush the CPU cache if it's still invalid. */
2837 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2838 i915_gem_clflush_object(obj);
2ef7eeaa 2839
e47c68e9 2840 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2841 }
2842
2843 /* It should now be out of any other write domains, and we can update
2844 * the domain values for our changes.
2845 */
e47c68e9
EA		 2846 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2847
2848 /* If we're writing through the CPU, then the GPU read domains will
2849 * need to be invalidated at next use.
2850 */
2851 if (write) {
2852 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2853 obj->write_domain = I915_GEM_DOMAIN_CPU;
2854 }
2ef7eeaa 2855
1c5d22f7
CW		 2856 trace_i915_gem_object_change_domain(obj,
2857 old_read_domains,
2858 old_write_domain);
2859
2ef7eeaa
EA		 2860 return 0;
2861}
2862
673a394b
EA		 2863/*
2864 * Set the next domain for the specified object. This
2865 * may not actually perform the necessary flushing/invaliding though,
2866 * as that may want to be batched with other set_domain operations
2867 *
2868 * This is (we hope) the only really tricky part of gem. The goal
2869 * is fairly simple -- track which caches hold bits of the object
2870 * and make sure they remain coherent. A few concrete examples may
2871 * help to explain how it works. For shorthand, we use the notation
2872 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2873 * a pair of read and write domain masks.
2874 *
2875 * Case 1: the batch buffer
2876 *
2877 * 1. Allocated
2878 * 2. Written by CPU
2879 * 3. Mapped to GTT
2880 * 4. Read by GPU
2881 * 5. Unmapped from GTT
2882 * 6. Freed
2883 *
2884 * Let's take these a step at a time
2885 *
2886 * 1. Allocated
2887 * Pages allocated from the kernel may still have
2888 * cache contents, so we set them to (CPU, CPU) always.
2889 * 2. Written by CPU (using pwrite)
2890 * The pwrite function calls set_domain (CPU, CPU) and
2891 * this function does nothing (as nothing changes)
2892 * 3. Mapped by GTT
2893 * This function asserts that the object is not
2894 * currently in any GPU-based read or write domains
2895 * 4. Read by GPU
2896 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2897 * As write_domain is zero, this function adds in the
2898 * current read domains (CPU+COMMAND, 0).
2899 * flush_domains is set to CPU.
2900 * invalidate_domains is set to COMMAND
2901 * clflush is run to get data out of the CPU caches
2902 * then i915_dev_set_domain calls i915_gem_flush to
2903 * emit an MI_FLUSH and drm_agp_chipset_flush
2904 * 5. Unmapped from GTT
2905 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2906 * flush_domains and invalidate_domains end up both zero
2907 * so no flushing/invalidating happens
2908 * 6. Freed
2909 * yay, done
2910 *
2911 * Case 2: The shared render buffer
2912 *
2913 * 1. Allocated
2914 * 2. Mapped to GTT
2915 * 3. Read/written by GPU
2916 * 4. set_domain to (CPU,CPU)
2917 * 5. Read/written by CPU
2918 * 6. Read/written by GPU
2919 *
2920 * 1. Allocated
2921 * Same as last example, (CPU, CPU)
2922 * 2. Mapped to GTT
2923 * Nothing changes (assertions find that it is not in the GPU)
2924 * 3. Read/written by GPU
2925 * execbuffer calls set_domain (RENDER, RENDER)
2926 * flush_domains gets CPU
2927 * invalidate_domains gets GPU
2928 * clflush (obj)
2929 * MI_FLUSH and drm_agp_chipset_flush
2930 * 4. set_domain (CPU, CPU)
2931 * flush_domains gets GPU
2932 * invalidate_domains gets CPU
2933 * wait_rendering (obj) to make sure all drawing is complete.
2934 * This will include an MI_FLUSH to get the data from GPU
2935 * to memory
2936 * clflush (obj) to invalidate the CPU cache
2937 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2938 * 5. Read/written by CPU
2939 * cache lines are loaded and dirtied
2940 * 6. Read written by GPU
2941 * Same as last GPU access
2942 *
2943 * Case 3: The constant buffer
2944 *
2945 * 1. Allocated
2946 * 2. Written by CPU
2947 * 3. Read by GPU
2948 * 4. Updated (written) by CPU again
2949 * 5. Read by GPU
2950 *
2951 * 1. Allocated
2952 * (CPU, CPU)
2953 * 2. Written by CPU
2954 * (CPU, CPU)
2955 * 3. Read by GPU
2956 * (CPU+RENDER, 0)
2957 * flush_domains = CPU
2958 * invalidate_domains = RENDER
2959 * clflush (obj)
2960 * MI_FLUSH
2961 * drm_agp_chipset_flush
2962 * 4. Updated (written) by CPU again
2963 * (CPU, CPU)
2964 * flush_domains = 0 (no previous write domain)
2965 * invalidate_domains = 0 (no new read domains)
2966 * 5. Read by GPU
2967 * (CPU+RENDER, 0)
2968 * flush_domains = CPU
2969 * invalidate_domains = RENDER
2970 * clflush (obj)
2971 * MI_FLUSH
2972 * drm_agp_chipset_flush
2973 */
c0d90829 2974static void
8b0e378a 2975i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 2976{
2977 struct drm_device *dev = obj->dev;
2978 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2979 uint32_t invalidate_domains = 0;
2980 uint32_t flush_domains = 0;
1c5d22f7 2981 uint32_t old_read_domains;
e47c68e9 2982
8b0e378a
EA		 2983 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2984 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 2985
652c393a
JB		 2986 intel_mark_busy(dev, obj);
2987
673a394b
EA		 2988#if WATCH_BUF
2989 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2990 __func__, obj,
8b0e378a
EA		 2991 obj->read_domains, obj->pending_read_domains,
2992 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 2993#endif
2994 /*
2995 * If the object isn't moving to a new write domain,
2996 * let the object stay in multiple read domains
2997 */
8b0e378a
EA		 2998 if (obj->pending_write_domain == 0)
2999 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3000 else
3001 obj_priv->dirty = 1;
3002
3003 /*
3004 * Flush the current write domain if
3005 * the new read domains don't match. Invalidate
3006 * any read domains which differ from the old
3007 * write domain
3008 */
8b0e378a
EA		 3009 if (obj->write_domain &&
3010 obj->write_domain != obj->pending_read_domains) {
673a394b 3011 flush_domains |= obj->write_domain;
8b0e378a
EA		 3012 invalidate_domains |=
3013 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3014 }
3015 /*
3016 * Invalidate any read caches which may have
3017 * stale data. That is, any new read domains.
3018 */
8b0e378a 3019 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3020 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3021#if WATCH_BUF
3022 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3023 __func__, flush_domains, invalidate_domains);
3024#endif
673a394b
EA		 3025 i915_gem_clflush_object(obj);
3026 }
3027
1c5d22f7
CW		 3028 old_read_domains = obj->read_domains;
3029
efbeed96
EA		 3030 /* The actual obj->write_domain will be updated with
3031 * pending_write_domain after we emit the accumulated flush for all
3032 * of our domain changes in execbuffers (which clears objects'
3033 * write_domains). So if we have a current write domain that we
3034 * aren't changing, set pending_write_domain to that.
3035 */
3036 if (flush_domains == 0 && obj->pending_write_domain == 0)
3037 obj->pending_write_domain = obj->write_domain;
8b0e378a 3038 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3039
3040 dev->invalidate_domains |= invalidate_domains;
3041 dev->flush_domains |= flush_domains;
3042#if WATCH_BUF
3043 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3044 __func__,
3045 obj->read_domains, obj->write_domain,
3046 dev->invalidate_domains, dev->flush_domains);
3047#endif
1c5d22f7
CW		 3048
3049 trace_i915_gem_object_change_domain(obj,
3050 old_read_domains,
3051 obj->write_domain);
673a394b
EA		 3052}
3053
3054/**
e47c68e9 3055 * Moves the object from a partially CPU read to a full one.
673a394b 3056 *
e47c68e9
EA		 3057 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3058 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3059 */
e47c68e9
EA		 3060static void
3061i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b
EA		 3062{
3063 struct drm_i915_gem_object *obj_priv = obj->driver_private;
673a394b 3064
e47c68e9
EA		 3065 if (!obj_priv->page_cpu_valid)
3066 return;
3067
3068 /* If we're partially in the CPU read domain, finish moving it in.
3069 */
3070 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3071 int i;
3072
3073 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3074 if (obj_priv->page_cpu_valid[i])
3075 continue;
856fa198 3076 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3077 }
e47c68e9
EA		 3078 }
3079
3080 /* Free the page_cpu_valid mappings which are now stale, whether
3081 * or not we've got I915_GEM_DOMAIN_CPU.
3082 */
9a298b2a 3083 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3084 obj_priv->page_cpu_valid = NULL;
3085}
3086
3087/**
3088 * Set the CPU read domain on a range of the object.
3089 *
3090 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3091 * not entirely valid. The page_cpu_valid member of the object flags which
3092 * pages have been flushed, and will be respected by
3093 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3094 * of the whole object.
3095 *
3096 * This function returns when the move is complete, including waiting on
3097 * flushes to occur.
3098 */
3099static int
3100i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3101 uint64_t offset, uint64_t size)
3102{
3103 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 3104 uint32_t old_read_domains;
e47c68e9 3105 int i, ret;
673a394b 3106
e47c68e9
EA		 3107 if (offset == 0 && size == obj->size)
3108 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3109
e47c68e9
EA		 3110 i915_gem_object_flush_gpu_write_domain(obj);
3111 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3112 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3113 if (ret != 0)
6a47baa6 3114 return ret;
e47c68e9
EA		 3115 i915_gem_object_flush_gtt_write_domain(obj);
3116
3117 /* If we're already fully in the CPU read domain, we're done. */
3118 if (obj_priv->page_cpu_valid == NULL &&
3119 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3120 return 0;
673a394b 3121
e47c68e9
EA		 3122 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3123 * newly adding I915_GEM_DOMAIN_CPU
3124 */
673a394b 3125 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3126 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3127 GFP_KERNEL);
e47c68e9
EA		 3128 if (obj_priv->page_cpu_valid == NULL)
3129 return -ENOMEM;
3130 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3131 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3132
3133 /* Flush the cache on any pages that are still invalid from the CPU's
3134 * perspective.
3135 */
e47c68e9
EA		 3136 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3137 i++) {
673a394b
EA		 3138 if (obj_priv->page_cpu_valid[i])
3139 continue;
3140
856fa198 3141 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3142
3143 obj_priv->page_cpu_valid[i] = 1;
3144 }
3145
e47c68e9
EA		 3146 /* It should now be out of any other write domains, and we can update
3147 * the domain values for our changes.
3148 */
3149 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3150
1c5d22f7 3151 old_read_domains = obj->read_domains;
e47c68e9
EA		 3152 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3153
1c5d22f7
CW		 3154 trace_i915_gem_object_change_domain(obj,
3155 old_read_domains,
3156 obj->write_domain);
3157
673a394b
EA		 3158 return 0;
3159}
3160
673a394b
EA		 3161/**
3162 * Pin an object to the GTT and evaluate the relocations landing in it.
3163 */
3164static int
3165i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3166 struct drm_file *file_priv,
40a5f0de
EA		 3167 struct drm_i915_gem_exec_object *entry,
3168 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3169{
3170 struct drm_device *dev = obj->dev;
0839ccb8 3171 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3172 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3173 int i, ret;
0839ccb8 3174 void __iomem *reloc_page;
673a394b
EA		 3175
3176 /* Choose the GTT offset for our buffer and put it there. */
3177 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3178 if (ret)
3179 return ret;
3180
3181 entry->offset = obj_priv->gtt_offset;
3182
673a394b
EA		 3183 /* Apply the relocations, using the GTT aperture to avoid cache
3184 * flushing requirements.
3185 */
3186 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3187 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3188 struct drm_gem_object *target_obj;
3189 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3190 uint32_t reloc_val, reloc_offset;
3191 uint32_t __iomem *reloc_entry;
673a394b 3192
673a394b 3193 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3194 reloc->target_handle);
673a394b
EA		 3195 if (target_obj == NULL) {
3196 i915_gem_object_unpin(obj);
3197 return -EBADF;
3198 }
3199 target_obj_priv = target_obj->driver_private;
3200
8542a0bb
CW		 3201#if WATCH_RELOC
3202 DRM_INFO("%s: obj %p offset %08x target %d "
3203 "read %08x write %08x gtt %08x "
3204 "presumed %08x delta %08x\n",
3205 __func__,
3206 obj,
3207 (int) reloc->offset,
3208 (int) reloc->target_handle,
3209 (int) reloc->read_domains,
3210 (int) reloc->write_domain,
3211 (int) target_obj_priv->gtt_offset,
3212 (int) reloc->presumed_offset,
3213 reloc->delta);
3214#endif
3215
673a394b
EA		 3216 /* The target buffer should have appeared before us in the
3217 * exec_object list, so it should have a GTT space bound by now.
3218 */
3219 if (target_obj_priv->gtt_space == NULL) {
3220 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3221 reloc->target_handle);
673a394b
EA		 3222 drm_gem_object_unreference(target_obj);
3223 i915_gem_object_unpin(obj);
3224 return -EINVAL;
3225 }
3226
8542a0bb 3227 /* Validate that the target is in a valid r/w GPU domain */
40a5f0de
EA		 3228 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3229 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3230 DRM_ERROR("reloc with read/write CPU domains: "
3231 "obj %p target %d offset %d "
3232 "read %08x write %08x",
40a5f0de
EA		 3233 obj, reloc->target_handle,
3234 (int) reloc->offset,
3235 reloc->read_domains,
3236 reloc->write_domain);
491152b8
CW		 3237 drm_gem_object_unreference(target_obj);
3238 i915_gem_object_unpin(obj);
e47c68e9
EA		 3239 return -EINVAL;
3240 }
40a5f0de
EA		 3241 if (reloc->write_domain && target_obj->pending_write_domain &&
3242 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3243 DRM_ERROR("Write domain conflict: "
3244 "obj %p target %d offset %d "
3245 "new %08x old %08x\n",
40a5f0de
EA		 3246 obj, reloc->target_handle,
3247 (int) reloc->offset,
3248 reloc->write_domain,
673a394b
EA		 3249 target_obj->pending_write_domain);
3250 drm_gem_object_unreference(target_obj);
3251 i915_gem_object_unpin(obj);
3252 return -EINVAL;
3253 }
3254
40a5f0de
EA		 3255 target_obj->pending_read_domains |= reloc->read_domains;
3256 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3257
3258 /* If the relocation already has the right value in it, no
3259 * more work needs to be done.
3260 */
40a5f0de 3261 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3262 drm_gem_object_unreference(target_obj);
3263 continue;
3264 }
3265
8542a0bb
CW		 3266 /* Check that the relocation address is valid... */
3267 if (reloc->offset > obj->size - 4) {
3268 DRM_ERROR("Relocation beyond object bounds: "
3269 "obj %p target %d offset %d size %d.\n",
3270 obj, reloc->target_handle,
3271 (int) reloc->offset, (int) obj->size);
3272 drm_gem_object_unreference(target_obj);
3273 i915_gem_object_unpin(obj);
3274 return -EINVAL;
3275 }
3276 if (reloc->offset & 3) {
3277 DRM_ERROR("Relocation not 4-byte aligned: "
3278 "obj %p target %d offset %d.\n",
3279 obj, reloc->target_handle,
3280 (int) reloc->offset);
3281 drm_gem_object_unreference(target_obj);
3282 i915_gem_object_unpin(obj);
3283 return -EINVAL;
3284 }
3285
3286 /* and points to somewhere within the target object. */
3287 if (reloc->delta >= target_obj->size) {
3288 DRM_ERROR("Relocation beyond target object bounds: "
3289 "obj %p target %d delta %d size %d.\n",
3290 obj, reloc->target_handle,
3291 (int) reloc->delta, (int) target_obj->size);
3292 drm_gem_object_unreference(target_obj);
3293 i915_gem_object_unpin(obj);
3294 return -EINVAL;
3295 }
3296
2ef7eeaa
EA		 3297 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3298 if (ret != 0) {
3299 drm_gem_object_unreference(target_obj);
3300 i915_gem_object_unpin(obj);
3301 return -EINVAL;
673a394b
EA		 3302 }
3303
3304 /* Map the page containing the relocation we're going to
3305 * perform.
3306 */
40a5f0de 3307 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3308 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3309 (reloc_offset &
3310 ~(PAGE_SIZE - 1)));
3043c60c 3311 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3312 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3313 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3314
3315#if WATCH_BUF
3316 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3317 obj, (unsigned int) reloc->offset,
673a394b
EA		 3318 readl(reloc_entry), reloc_val);
3319#endif
3320 writel(reloc_val, reloc_entry);
0839ccb8 3321 io_mapping_unmap_atomic(reloc_page);
673a394b 3322
40a5f0de
EA		 3323 /* The updated presumed offset for this entry will be
3324 * copied back out to the user.
673a394b 3325 */
40a5f0de 3326 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3327
3328 drm_gem_object_unreference(target_obj);
3329 }
3330
673a394b
EA		 3331#if WATCH_BUF
3332 if (0)
3333 i915_gem_dump_object(obj, 128, __func__, ~0);
3334#endif
3335 return 0;
3336}
3337
3338/** Dispatch a batchbuffer to the ring
3339 */
3340static int
3341i915_dispatch_gem_execbuffer(struct drm_device *dev,
3342 struct drm_i915_gem_execbuffer *exec,
201361a5 3343 struct drm_clip_rect *cliprects,
673a394b
EA		 3344 uint64_t exec_offset)
3345{
3346 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3347 int nbox = exec->num_cliprects;
3348 int i = 0, count;
83d60795 3349 uint32_t exec_start, exec_len;
673a394b
EA		 3350 RING_LOCALS;
3351
3352 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3353 exec_len = (uint32_t) exec->batch_len;
3354
1c5d22f7
CW		 3355 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3356
673a394b
EA		 3357 count = nbox ? nbox : 1;
3358
3359 for (i = 0; i < count; i++) {
3360 if (i < nbox) {
201361a5 3361 int ret = i915_emit_box(dev, cliprects, i,
673a394b
EA		 3362 exec->DR1, exec->DR4);
3363 if (ret)
3364 return ret;
3365 }
3366
3367 if (IS_I830(dev) || IS_845G(dev)) {
3368 BEGIN_LP_RING(4);
3369 OUT_RING(MI_BATCH_BUFFER);
3370 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3371 OUT_RING(exec_start + exec_len - 4);
3372 OUT_RING(0);
3373 ADVANCE_LP_RING();
3374 } else {
3375 BEGIN_LP_RING(2);
3376 if (IS_I965G(dev)) {
3377 OUT_RING(MI_BATCH_BUFFER_START |
3378 (2 << 6) |
3379 MI_BATCH_NON_SECURE_I965);
3380 OUT_RING(exec_start);
3381 } else {
3382 OUT_RING(MI_BATCH_BUFFER_START |
3383 (2 << 6));
3384 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3385 }
3386 ADVANCE_LP_RING();
3387 }
3388 }
3389
3390 /* XXX breadcrumb */
3391 return 0;
3392}
3393
3394/* Throttle our rendering by waiting until the ring has completed our requests
3395 * emitted over 20 msec ago.
3396 *
b962442e
EA		 3397 * Note that if we were to use the current jiffies each time around the loop,
3398 * we wouldn't escape the function with any frames outstanding if the time to
3399 * render a frame was over 20ms.
3400 *
673a394b
EA		 3401 * This should get us reasonable parallelism between CPU and GPU but also
3402 * relatively low latency when blocking on a particular request to finish.
3403 */
3404static int
3405i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3406{
3407 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3408 int ret = 0;
b962442e 3409 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3410
3411 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3412 while (!list_empty(&i915_file_priv->mm.request_list)) {
3413 struct drm_i915_gem_request *request;
3414
3415 request = list_first_entry(&i915_file_priv->mm.request_list,
3416 struct drm_i915_gem_request,
3417 client_list);
3418
3419 if (time_after_eq(request->emitted_jiffies, recent_enough))
3420 break;
3421
3422 ret = i915_wait_request(dev, request->seqno);
3423 if (ret != 0)
3424 break;
3425 }
673a394b 3426 mutex_unlock(&dev->struct_mutex);
b962442e 3427
673a394b
EA		 3428 return ret;
3429}
3430
40a5f0de
EA		 3431static int
3432i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3433 uint32_t buffer_count,
3434 struct drm_i915_gem_relocation_entry **relocs)
3435{
3436 uint32_t reloc_count = 0, reloc_index = 0, i;
3437 int ret;
3438
3439 *relocs = NULL;
3440 for (i = 0; i < buffer_count; i++) {
3441 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3442 return -EINVAL;
3443 reloc_count += exec_list[i].relocation_count;
3444 }
3445
8e7d2b2c 3446 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
40a5f0de
EA		 3447 if (*relocs == NULL)
3448 return -ENOMEM;
3449
3450 for (i = 0; i < buffer_count; i++) {
3451 struct drm_i915_gem_relocation_entry __user *user_relocs;
3452
3453 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3454
3455 ret = copy_from_user(&(*relocs)[reloc_index],
3456 user_relocs,
3457 exec_list[i].relocation_count *
3458 sizeof(**relocs));
3459 if (ret != 0) {
8e7d2b2c 3460 drm_free_large(*relocs);
40a5f0de 3461 *relocs = NULL;
2bc43b5c 3462 return -EFAULT;
40a5f0de
EA		 3463 }
3464
3465 reloc_index += exec_list[i].relocation_count;
3466 }
3467
2bc43b5c 3468 return 0;
40a5f0de
EA		 3469}
3470
3471static int
3472i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3473 uint32_t buffer_count,
3474 struct drm_i915_gem_relocation_entry *relocs)
3475{
3476 uint32_t reloc_count = 0, i;
2bc43b5c 3477 int ret = 0;
40a5f0de
EA		 3478
3479 for (i = 0; i < buffer_count; i++) {
3480 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3481 int unwritten;
40a5f0de
EA		 3482
3483 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3484
2bc43b5c
FM		 3485 unwritten = copy_to_user(user_relocs,
3486 &relocs[reloc_count],
3487 exec_list[i].relocation_count *
3488 sizeof(*relocs));
3489
3490 if (unwritten) {
3491 ret = -EFAULT;
3492 goto err;
40a5f0de
EA		 3493 }
3494
3495 reloc_count += exec_list[i].relocation_count;
3496 }
3497
2bc43b5c 3498err:
8e7d2b2c 3499 drm_free_large(relocs);
40a5f0de
EA		 3500
3501 return ret;
3502}
3503
83d60795
CW		 3504static int
3505i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3506 uint64_t exec_offset)
3507{
3508 uint32_t exec_start, exec_len;
3509
3510 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3511 exec_len = (uint32_t) exec->batch_len;
3512
3513 if ((exec_start | exec_len) & 0x7)
3514 return -EINVAL;
3515
3516 if (!exec_start)
3517 return -EINVAL;
3518
3519 return 0;
3520}
3521
673a394b
EA		 3522int
3523i915_gem_execbuffer(struct drm_device *dev, void *data,
3524 struct drm_file *file_priv)
3525{
3526 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3527 struct drm_i915_gem_execbuffer *args = data;
3528 struct drm_i915_gem_exec_object *exec_list = NULL;
3529 struct drm_gem_object **object_list = NULL;
3530 struct drm_gem_object *batch_obj;
b70d11da 3531 struct drm_i915_gem_object *obj_priv;
201361a5 3532 struct drm_clip_rect *cliprects = NULL;
40a5f0de
EA		 3533 struct drm_i915_gem_relocation_entry *relocs;
3534 int ret, ret2, i, pinned = 0;
673a394b 3535 uint64_t exec_offset;
40a5f0de 3536 uint32_t seqno, flush_domains, reloc_index;
ac94a962 3537 int pin_tries;
673a394b
EA		 3538
3539#if WATCH_EXEC
3540 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3541 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3542#endif
3543
4f481ed2
EA		 3544 if (args->buffer_count < 1) {
3545 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3546 return -EINVAL;
3547 }
673a394b 3548 /* Copy in the exec list from userland */
8e7d2b2c
JB		 3549 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3550 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
673a394b
EA		 3551 if (exec_list == NULL || object_list == NULL) {
3552 DRM_ERROR("Failed to allocate exec or object list "
3553 "for %d buffers\n",
3554 args->buffer_count);
3555 ret = -ENOMEM;
3556 goto pre_mutex_err;
3557 }
3558 ret = copy_from_user(exec_list,
3559 (struct drm_i915_relocation_entry __user *)
3560 (uintptr_t) args->buffers_ptr,
3561 sizeof(*exec_list) * args->buffer_count);
3562 if (ret != 0) {
3563 DRM_ERROR("copy %d exec entries failed %d\n",
3564 args->buffer_count, ret);
3565 goto pre_mutex_err;
3566 }
3567
201361a5 3568 if (args->num_cliprects != 0) {
9a298b2a
EA		 3569 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3570 GFP_KERNEL);
201361a5
EA		 3571 if (cliprects == NULL)
3572 goto pre_mutex_err;
3573
3574 ret = copy_from_user(cliprects,
3575 (struct drm_clip_rect __user *)
3576 (uintptr_t) args->cliprects_ptr,
3577 sizeof(*cliprects) * args->num_cliprects);
3578 if (ret != 0) {
3579 DRM_ERROR("copy %d cliprects failed: %d\n",
3580 args->num_cliprects, ret);
3581 goto pre_mutex_err;
3582 }
3583 }
3584
40a5f0de
EA		 3585 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3586 &relocs);
3587 if (ret != 0)
3588 goto pre_mutex_err;
3589
673a394b
EA		 3590 mutex_lock(&dev->struct_mutex);
3591
3592 i915_verify_inactive(dev, __FILE__, __LINE__);
3593
ba1234d1 3594 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 3595 DRM_ERROR("Execbuf while wedged\n");
3596 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3597 ret = -EIO;
3598 goto pre_mutex_err;
673a394b
EA		 3599 }
3600
3601 if (dev_priv->mm.suspended) {
3602 DRM_ERROR("Execbuf while VT-switched.\n");
3603 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3604 ret = -EBUSY;
3605 goto pre_mutex_err;
673a394b
EA		 3606 }
3607
ac94a962 3608 /* Look up object handles */
673a394b
EA		 3609 for (i = 0; i < args->buffer_count; i++) {
3610 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3611 exec_list[i].handle);
3612 if (object_list[i] == NULL) {
3613 DRM_ERROR("Invalid object handle %d at index %d\n",
3614 exec_list[i].handle, i);
3615 ret = -EBADF;
3616 goto err;
3617 }
b70d11da
KH		 3618
3619 obj_priv = object_list[i]->driver_private;
3620 if (obj_priv->in_execbuffer) {
3621 DRM_ERROR("Object %p appears more than once in object list\n",
3622 object_list[i]);
3623 ret = -EBADF;
3624 goto err;
3625 }
3626 obj_priv->in_execbuffer = true;
ac94a962 3627 }
673a394b 3628
ac94a962
KP		 3629 /* Pin and relocate */
3630 for (pin_tries = 0; ; pin_tries++) {
3631 ret = 0;
40a5f0de
EA		 3632 reloc_index = 0;
3633
ac94a962
KP		 3634 for (i = 0; i < args->buffer_count; i++) {
3635 object_list[i]->pending_read_domains = 0;
3636 object_list[i]->pending_write_domain = 0;
3637 ret = i915_gem_object_pin_and_relocate(object_list[i],
3638 file_priv,
40a5f0de
EA		 3639 &exec_list[i],
3640 &relocs[reloc_index]);
ac94a962
KP		 3641 if (ret)
3642 break;
3643 pinned = i + 1;
40a5f0de 3644 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3645 }
3646 /* success */
3647 if (ret == 0)
3648 break;
3649
3650 /* error other than GTT full, or we've already tried again */
2939e1f5 3651 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3652 if (ret != -ERESTARTSYS) {
3653 unsigned long long total_size = 0;
3654 for (i = 0; i < args->buffer_count; i++)
3655 total_size += object_list[i]->size;
3656 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3657 pinned+1, args->buffer_count,
3658 total_size, ret);
3659 DRM_ERROR("%d objects [%d pinned], "
3660 "%d object bytes [%d pinned], "
3661 "%d/%d gtt bytes\n",
3662 atomic_read(&dev->object_count),
3663 atomic_read(&dev->pin_count),
3664 atomic_read(&dev->object_memory),
3665 atomic_read(&dev->pin_memory),
3666 atomic_read(&dev->gtt_memory),
3667 dev->gtt_total);
3668 }
673a394b
EA		 3669 goto err;
3670 }
ac94a962
KP		 3671
3672 /* unpin all of our buffers */
3673 for (i = 0; i < pinned; i++)
3674 i915_gem_object_unpin(object_list[i]);
b1177636 3675 pinned = 0;
ac94a962
KP		 3676
3677 /* evict everyone we can from the aperture */
3678 ret = i915_gem_evict_everything(dev);
07f73f69 3679 if (ret && ret != -ENOSPC)
ac94a962 3680 goto err;
673a394b
EA		 3681 }
3682
3683 /* Set the pending read domains for the batch buffer to COMMAND */
3684 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3685 if (batch_obj->pending_write_domain) {
3686 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3687 ret = -EINVAL;
3688 goto err;
3689 }
3690 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3691
83d60795
CW		 3692 /* Sanity check the batch buffer, prior to moving objects */
3693 exec_offset = exec_list[args->buffer_count - 1].offset;
3694 ret = i915_gem_check_execbuffer (args, exec_offset);
3695 if (ret != 0) {
3696 DRM_ERROR("execbuf with invalid offset/length\n");
3697 goto err;
3698 }
3699
673a394b
EA		 3700 i915_verify_inactive(dev, __FILE__, __LINE__);
3701
646f0f6e
KP		 3702 /* Zero the global flush/invalidate flags. These
3703 * will be modified as new domains are computed
3704 * for each object
3705 */
3706 dev->invalidate_domains = 0;
3707 dev->flush_domains = 0;
3708
673a394b
EA		 3709 for (i = 0; i < args->buffer_count; i++) {
3710 struct drm_gem_object *obj = object_list[i];
673a394b 3711
646f0f6e 3712 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3713 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3714 }
3715
3716 i915_verify_inactive(dev, __FILE__, __LINE__);
3717
646f0f6e
KP		 3718 if (dev->invalidate_domains | dev->flush_domains) {
3719#if WATCH_EXEC
3720 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3721 __func__,
3722 dev->invalidate_domains,
3723 dev->flush_domains);
3724#endif
3725 i915_gem_flush(dev,
3726 dev->invalidate_domains,
3727 dev->flush_domains);
3728 if (dev->flush_domains)
b962442e
EA		 3729 (void)i915_add_request(dev, file_priv,
3730 dev->flush_domains);
646f0f6e 3731 }
673a394b 3732
efbeed96
EA		 3733 for (i = 0; i < args->buffer_count; i++) {
3734 struct drm_gem_object *obj = object_list[i];
1c5d22f7 3735 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3736
3737 obj->write_domain = obj->pending_write_domain;
1c5d22f7
CW		 3738 trace_i915_gem_object_change_domain(obj,
3739 obj->read_domains,
3740 old_write_domain);
efbeed96
EA		 3741 }
3742
673a394b
EA		 3743 i915_verify_inactive(dev, __FILE__, __LINE__);
3744
3745#if WATCH_COHERENCY
3746 for (i = 0; i < args->buffer_count; i++) {
3747 i915_gem_object_check_coherency(object_list[i],
3748 exec_list[i].handle);
3749 }
3750#endif
3751
673a394b 3752#if WATCH_EXEC
6911a9b8 3753 i915_gem_dump_object(batch_obj,
673a394b
EA		 3754 args->batch_len,
3755 __func__,
3756 ~0);
3757#endif
3758
673a394b 3759 /* Exec the batchbuffer */
201361a5 3760 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
673a394b
EA		 3761 if (ret) {
3762 DRM_ERROR("dispatch failed %d\n", ret);
3763 goto err;
3764 }
3765
3766 /*
3767 * Ensure that the commands in the batch buffer are
3768 * finished before the interrupt fires
3769 */
3770 flush_domains = i915_retire_commands(dev);
3771
3772 i915_verify_inactive(dev, __FILE__, __LINE__);
3773
3774 /*
3775 * Get a seqno representing the execution of the current buffer,
3776 * which we can wait on. We would like to mitigate these interrupts,
3777 * likely by only creating seqnos occasionally (so that we have
3778 * *some* interrupts representing completion of buffers that we can
3779 * wait on when trying to clear up gtt space).
3780 */
b962442e 3781 seqno = i915_add_request(dev, file_priv, flush_domains);
673a394b 3782 BUG_ON(seqno == 0);
673a394b
EA		 3783 for (i = 0; i < args->buffer_count; i++) {
3784 struct drm_gem_object *obj = object_list[i];
673a394b 3785
ce44b0ea 3786 i915_gem_object_move_to_active(obj, seqno);
673a394b
EA		 3787#if WATCH_LRU
3788 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3789#endif
3790 }
3791#if WATCH_LRU
3792 i915_dump_lru(dev, __func__);
3793#endif
3794
3795 i915_verify_inactive(dev, __FILE__, __LINE__);
3796
673a394b 3797err:
aad87dff
JL		 3798 for (i = 0; i < pinned; i++)
3799 i915_gem_object_unpin(object_list[i]);
3800
b70d11da
KH		 3801 for (i = 0; i < args->buffer_count; i++) {
3802 if (object_list[i]) {
3803 obj_priv = object_list[i]->driver_private;
3804 obj_priv->in_execbuffer = false;
3805 }
aad87dff 3806 drm_gem_object_unreference(object_list[i]);
b70d11da 3807 }
673a394b 3808
673a394b
EA		 3809 mutex_unlock(&dev->struct_mutex);
3810
a35f2e2b
RD		 3811 if (!ret) {
3812 /* Copy the new buffer offsets back to the user's exec list. */
3813 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3814 (uintptr_t) args->buffers_ptr,
3815 exec_list,
3816 sizeof(*exec_list) * args->buffer_count);
2bc43b5c
FM		 3817 if (ret) {
3818 ret = -EFAULT;
a35f2e2b
RD		 3819 DRM_ERROR("failed to copy %d exec entries "
3820 "back to user (%d)\n",
3821 args->buffer_count, ret);
2bc43b5c 3822 }
a35f2e2b
RD		 3823 }
3824
40a5f0de
EA		 3825 /* Copy the updated relocations out regardless of current error
3826 * state. Failure to update the relocs would mean that the next
3827 * time userland calls execbuf, it would do so with presumed offset
3828 * state that didn't match the actual object state.
3829 */
3830 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3831 relocs);
3832 if (ret2 != 0) {
3833 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3834
3835 if (ret == 0)
3836 ret = ret2;
3837 }
3838
673a394b 3839pre_mutex_err:
8e7d2b2c
JB		 3840 drm_free_large(object_list);
3841 drm_free_large(exec_list);
9a298b2a 3842 kfree(cliprects);
673a394b
EA		 3843
3844 return ret;
3845}
3846
3847int
3848i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3849{
3850 struct drm_device *dev = obj->dev;
3851 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3852 int ret;
3853
3854 i915_verify_inactive(dev, __FILE__, __LINE__);
3855 if (obj_priv->gtt_space == NULL) {
3856 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3857 if (ret != 0) {
9bb2d6f9 3858 if (ret != -EBUSY && ret != -ERESTARTSYS)
0fce81e3 3859 DRM_ERROR("Failure to bind: %d\n", ret);
673a394b
EA		 3860 return ret;
3861 }
22c344e9
CW		 3862 }
3863 /*
3864 * Pre-965 chips need a fence register set up in order to
3865 * properly handle tiled surfaces.
3866 */
a09ba7fa 3867 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 3868 ret = i915_gem_object_get_fence_reg(obj);
22c344e9
CW		 3869 if (ret != 0) {
3870 if (ret != -EBUSY && ret != -ERESTARTSYS)
3871 DRM_ERROR("Failure to install fence: %d\n",
3872 ret);
3873 return ret;
3874 }
673a394b
EA		 3875 }
3876 obj_priv->pin_count++;
3877
3878 /* If the object is not active and not pending a flush,
3879 * remove it from the inactive list
3880 */
3881 if (obj_priv->pin_count == 1) {
3882 atomic_inc(&dev->pin_count);
3883 atomic_add(obj->size, &dev->pin_memory);
3884 if (!obj_priv->active &&
21d509e3 3885 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 3886 !list_empty(&obj_priv->list))
3887 list_del_init(&obj_priv->list);
3888 }
3889 i915_verify_inactive(dev, __FILE__, __LINE__);
3890
3891 return 0;
3892}
3893
3894void
3895i915_gem_object_unpin(struct drm_gem_object *obj)
3896{
3897 struct drm_device *dev = obj->dev;
3898 drm_i915_private_t *dev_priv = dev->dev_private;
3899 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3900
3901 i915_verify_inactive(dev, __FILE__, __LINE__);
3902 obj_priv->pin_count--;
3903 BUG_ON(obj_priv->pin_count < 0);
3904 BUG_ON(obj_priv->gtt_space == NULL);
3905
3906 /* If the object is no longer pinned, and is
3907 * neither active nor being flushed, then stick it on
3908 * the inactive list
3909 */
3910 if (obj_priv->pin_count == 0) {
3911 if (!obj_priv->active &&
21d509e3 3912 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 3913 list_move_tail(&obj_priv->list,
3914 &dev_priv->mm.inactive_list);
3915 atomic_dec(&dev->pin_count);
3916 atomic_sub(obj->size, &dev->pin_memory);
3917 }
3918 i915_verify_inactive(dev, __FILE__, __LINE__);
3919}
3920
3921int
3922i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3923 struct drm_file *file_priv)
3924{
3925 struct drm_i915_gem_pin *args = data;
3926 struct drm_gem_object *obj;
3927 struct drm_i915_gem_object *obj_priv;
3928 int ret;
3929
3930 mutex_lock(&dev->struct_mutex);
3931
3932 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3933 if (obj == NULL) {
3934 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3935 args->handle);
3936 mutex_unlock(&dev->struct_mutex);
3937 return -EBADF;
3938 }
3939 obj_priv = obj->driver_private;
3940
3ef94daa
CW		 3941 if (obj_priv->madv == I915_MADV_DONTNEED) {
3942 DRM_ERROR("Attempting to pin a I915_MADV_DONTNEED buffer\n");
3943 drm_gem_object_unreference(obj);
3944 mutex_unlock(&dev->struct_mutex);
3945 return -EINVAL;
3946 }
3947
79e53945
JB		 3948 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3949 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3950 args->handle);
96dec61d 3951 drm_gem_object_unreference(obj);
673a394b 3952 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 3953 return -EINVAL;
3954 }
3955
3956 obj_priv->user_pin_count++;
3957 obj_priv->pin_filp = file_priv;
3958 if (obj_priv->user_pin_count == 1) {
3959 ret = i915_gem_object_pin(obj, args->alignment);
3960 if (ret != 0) {
3961 drm_gem_object_unreference(obj);
3962 mutex_unlock(&dev->struct_mutex);
3963 return ret;
3964 }
673a394b
EA		 3965 }
3966
3967 /* XXX - flush the CPU caches for pinned objects
3968 * as the X server doesn't manage domains yet
3969 */
e47c68e9 3970 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 3971 args->offset = obj_priv->gtt_offset;
3972 drm_gem_object_unreference(obj);
3973 mutex_unlock(&dev->struct_mutex);
3974
3975 return 0;
3976}
3977
3978int
3979i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3980 struct drm_file *file_priv)
3981{
3982 struct drm_i915_gem_pin *args = data;
3983 struct drm_gem_object *obj;
79e53945 3984 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 3985
3986 mutex_lock(&dev->struct_mutex);
3987
3988 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3989 if (obj == NULL) {
3990 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3991 args->handle);
3992 mutex_unlock(&dev->struct_mutex);
3993 return -EBADF;
3994 }
3995
79e53945
JB		 3996 obj_priv = obj->driver_private;
3997 if (obj_priv->pin_filp != file_priv) {
3998 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3999 args->handle);
4000 drm_gem_object_unreference(obj);
4001 mutex_unlock(&dev->struct_mutex);
4002 return -EINVAL;
4003 }
4004 obj_priv->user_pin_count--;
4005 if (obj_priv->user_pin_count == 0) {
4006 obj_priv->pin_filp = NULL;
4007 i915_gem_object_unpin(obj);
4008 }
673a394b
EA		 4009
4010 drm_gem_object_unreference(obj);
4011 mutex_unlock(&dev->struct_mutex);
4012 return 0;
4013}
4014
4015int
4016i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4017 struct drm_file *file_priv)
4018{
4019 struct drm_i915_gem_busy *args = data;
4020 struct drm_gem_object *obj;
4021 struct drm_i915_gem_object *obj_priv;
4022
673a394b
EA		 4023 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4024 if (obj == NULL) {
4025 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4026 args->handle);
673a394b
EA		 4027 return -EBADF;
4028 }
4029
b1ce786c 4030 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4031 /* Update the active list for the hardware's current position.
4032 * Otherwise this only updates on a delayed timer or when irqs are
4033 * actually unmasked, and our working set ends up being larger than
4034 * required.
4035 */
4036 i915_gem_retire_requests(dev);
4037
673a394b 4038 obj_priv = obj->driver_private;
c4de0a5d
EA		 4039 /* Don't count being on the flushing list against the object being
4040 * done. Otherwise, a buffer left on the flushing list but not getting
4041 * flushed (because nobody's flushing that domain) won't ever return
4042 * unbusy and get reused by libdrm's bo cache. The other expected
4043 * consumer of this interface, OpenGL's occlusion queries, also specs
4044 * that the objects get unbusy "eventually" without any interference.
4045 */
4046 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4047
4048 drm_gem_object_unreference(obj);
4049 mutex_unlock(&dev->struct_mutex);
4050 return 0;
4051}
4052
4053int
4054i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4055 struct drm_file *file_priv)
4056{
4057 return i915_gem_ring_throttle(dev, file_priv);
4058}
4059
3ef94daa
CW		 4060int
4061i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4062 struct drm_file *file_priv)
4063{
4064 struct drm_i915_gem_madvise *args = data;
4065 struct drm_gem_object *obj;
4066 struct drm_i915_gem_object *obj_priv;
4067
4068 switch (args->madv) {
4069 case I915_MADV_DONTNEED:
4070 case I915_MADV_WILLNEED:
4071 break;
4072 default:
4073 return -EINVAL;
4074 }
4075
4076 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4077 if (obj == NULL) {
4078 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4079 args->handle);
4080 return -EBADF;
4081 }
4082
4083 mutex_lock(&dev->struct_mutex);
4084 obj_priv = obj->driver_private;
4085
4086 if (obj_priv->pin_count) {
4087 drm_gem_object_unreference(obj);
4088 mutex_unlock(&dev->struct_mutex);
4089
4090 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4091 return -EINVAL;
4092 }
4093
4094 obj_priv->madv = args->madv;
4095 args->retained = obj_priv->gtt_space != NULL;
4096
4097 drm_gem_object_unreference(obj);
4098 mutex_unlock(&dev->struct_mutex);
4099
4100 return 0;
4101}
4102
673a394b
EA		 4103int i915_gem_init_object(struct drm_gem_object *obj)
4104{
4105 struct drm_i915_gem_object *obj_priv;
4106
9a298b2a 4107 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
673a394b
EA		 4108 if (obj_priv == NULL)
4109 return -ENOMEM;
4110
4111 /*
4112 * We've just allocated pages from the kernel,
4113 * so they've just been written by the CPU with
4114 * zeros. They'll need to be clflushed before we
4115 * use them with the GPU.
4116 */
4117 obj->write_domain = I915_GEM_DOMAIN_CPU;
4118 obj->read_domains = I915_GEM_DOMAIN_CPU;
4119
ba1eb1d8
KP		 4120 obj_priv->agp_type = AGP_USER_MEMORY;
4121
673a394b
EA		 4122 obj->driver_private = obj_priv;
4123 obj_priv->obj = obj;
de151cf6 4124 obj_priv->fence_reg = I915_FENCE_REG_NONE;
673a394b 4125 INIT_LIST_HEAD(&obj_priv->list);
a09ba7fa 4126 INIT_LIST_HEAD(&obj_priv->fence_list);
3ef94daa 4127 obj_priv->madv = I915_MADV_WILLNEED;
de151cf6 4128
1c5d22f7
CW		 4129 trace_i915_gem_object_create(obj);
4130
673a394b
EA		 4131 return 0;
4132}
4133
4134void i915_gem_free_object(struct drm_gem_object *obj)
4135{
de151cf6 4136 struct drm_device *dev = obj->dev;
673a394b
EA		 4137 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4138
1c5d22f7
CW		 4139 trace_i915_gem_object_destroy(obj);
4140
673a394b
EA		 4141 while (obj_priv->pin_count > 0)
4142 i915_gem_object_unpin(obj);
4143
71acb5eb
DA		 4144 if (obj_priv->phys_obj)
4145 i915_gem_detach_phys_object(dev, obj);
4146
673a394b
EA		 4147 i915_gem_object_unbind(obj);
4148
7e616158
CW		 4149 if (obj_priv->mmap_offset)
4150 i915_gem_free_mmap_offset(obj);
de151cf6 4151
9a298b2a 4152 kfree(obj_priv->page_cpu_valid);
280b713b 4153 kfree(obj_priv->bit_17);
9a298b2a 4154 kfree(obj->driver_private);
673a394b
EA		 4155}
4156
ab5ee576 4157/** Unbinds all inactive objects. */
673a394b 4158static int
ab5ee576 4159i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4160{
ab5ee576 4161 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4162
ab5ee576
CW		 4163 while (!list_empty(&dev_priv->mm.inactive_list)) {
4164 struct drm_gem_object *obj;
4165 int ret;
673a394b 4166
ab5ee576
CW		 4167 obj = list_first_entry(&dev_priv->mm.inactive_list,
4168 struct drm_i915_gem_object,
4169 list)->obj;
673a394b
EA		 4170
4171 ret = i915_gem_object_unbind(obj);
4172 if (ret != 0) {
ab5ee576 4173 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4174 return ret;
4175 }
4176 }
4177
673a394b
EA		 4178 return 0;
4179}
4180
5669fcac 4181int
673a394b
EA		 4182i915_gem_idle(struct drm_device *dev)
4183{
4184 drm_i915_private_t *dev_priv = dev->dev_private;
4185 uint32_t seqno, cur_seqno, last_seqno;
4186 int stuck, ret;
4187
6dbe2772
KP		 4188 mutex_lock(&dev->struct_mutex);
4189
4190 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4191 mutex_unlock(&dev->struct_mutex);
673a394b 4192 return 0;
6dbe2772 4193 }
673a394b
EA		 4194
4195 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4196 * We need to replace this with a semaphore, or something.
4197 */
4198 dev_priv->mm.suspended = 1;
f65d9421 4199 del_timer(&dev_priv->hangcheck_timer);
673a394b 4200
6dbe2772
KP		 4201 /* Cancel the retire work handler, wait for it to finish if running
4202 */
4203 mutex_unlock(&dev->struct_mutex);
4204 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4205 mutex_lock(&dev->struct_mutex);
4206
673a394b
EA		 4207 i915_kernel_lost_context(dev);
4208
4209 /* Flush the GPU along with all non-CPU write domains
4210 */
21d509e3
CW		 4211 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4212 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
673a394b
EA		 4213
4214 if (seqno == 0) {
4215 mutex_unlock(&dev->struct_mutex);
4216 return -ENOMEM;
4217 }
4218
4219 dev_priv->mm.waiting_gem_seqno = seqno;
4220 last_seqno = 0;
4221 stuck = 0;
4222 for (;;) {
4223 cur_seqno = i915_get_gem_seqno(dev);
4224 if (i915_seqno_passed(cur_seqno, seqno))
4225 break;
4226 if (last_seqno == cur_seqno) {
4227 if (stuck++ > 100) {
4228 DRM_ERROR("hardware wedged\n");
ba1234d1 4229 atomic_set(&dev_priv->mm.wedged, 1);
673a394b
EA		 4230 DRM_WAKEUP(&dev_priv->irq_queue);
4231 break;
4232 }
4233 }
4234 msleep(10);
4235 last_seqno = cur_seqno;
4236 }
4237 dev_priv->mm.waiting_gem_seqno = 0;
4238
4239 i915_gem_retire_requests(dev);
4240
5e118f41 4241 spin_lock(&dev_priv->mm.active_list_lock);
ba1234d1 4242 if (!atomic_read(&dev_priv->mm.wedged)) {
28dfe52a
EA		 4243 /* Active and flushing should now be empty as we've
4244 * waited for a sequence higher than any pending execbuffer
4245 */
4246 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4247 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4248 /* Request should now be empty as we've also waited
4249 * for the last request in the list
4250 */
4251 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4252 }
673a394b 4253
28dfe52a
EA		 4254 /* Empty the active and flushing lists to inactive. If there's
4255 * anything left at this point, it means that we're wedged and
4256 * nothing good's going to happen by leaving them there. So strip
4257 * the GPU domains and just stuff them onto inactive.
673a394b 4258 */
28dfe52a 4259 while (!list_empty(&dev_priv->mm.active_list)) {
1c5d22f7
CW		 4260 struct drm_gem_object *obj;
4261 uint32_t old_write_domain;
4262
4263 obj = list_first_entry(&dev_priv->mm.active_list,
4264 struct drm_i915_gem_object,
4265 list)->obj;
4266 old_write_domain = obj->write_domain;
4267 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4268 i915_gem_object_move_to_inactive(obj);
4269
4270 trace_i915_gem_object_change_domain(obj,
4271 obj->read_domains,
4272 old_write_domain);
28dfe52a 4273 }
5e118f41 4274 spin_unlock(&dev_priv->mm.active_list_lock);
28dfe52a
EA		 4275
4276 while (!list_empty(&dev_priv->mm.flushing_list)) {
1c5d22f7
CW		 4277 struct drm_gem_object *obj;
4278 uint32_t old_write_domain;
4279
4280 obj = list_first_entry(&dev_priv->mm.flushing_list,
4281 struct drm_i915_gem_object,
4282 list)->obj;
4283 old_write_domain = obj->write_domain;
4284 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4285 i915_gem_object_move_to_inactive(obj);
4286
4287 trace_i915_gem_object_change_domain(obj,
4288 obj->read_domains,
4289 old_write_domain);
28dfe52a
EA		 4290 }
4291
4292
4293 /* Move all inactive buffers out of the GTT. */
ab5ee576 4294 ret = i915_gem_evict_from_inactive_list(dev);
28dfe52a 4295 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
6dbe2772
KP		 4296 if (ret) {
4297 mutex_unlock(&dev->struct_mutex);
673a394b 4298 return ret;
6dbe2772 4299 }
673a394b 4300
6dbe2772
KP		 4301 i915_gem_cleanup_ringbuffer(dev);
4302 mutex_unlock(&dev->struct_mutex);
4303
673a394b
EA		 4304 return 0;
4305}
4306
4307static int
4308i915_gem_init_hws(struct drm_device *dev)
4309{
4310 drm_i915_private_t *dev_priv = dev->dev_private;
4311 struct drm_gem_object *obj;
4312 struct drm_i915_gem_object *obj_priv;
4313 int ret;
4314
4315 /* If we need a physical address for the status page, it's already
4316 * initialized at driver load time.
4317 */
4318 if (!I915_NEED_GFX_HWS(dev))
4319 return 0;
4320
4321 obj = drm_gem_object_alloc(dev, 4096);
4322 if (obj == NULL) {
4323 DRM_ERROR("Failed to allocate status page\n");
4324 return -ENOMEM;
4325 }
4326 obj_priv = obj->driver_private;
ba1eb1d8 4327 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
673a394b
EA		 4328
4329 ret = i915_gem_object_pin(obj, 4096);
4330 if (ret != 0) {
4331 drm_gem_object_unreference(obj);
4332 return ret;
4333 }
4334
4335 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
673a394b 4336
856fa198 4337 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
ba1eb1d8 4338 if (dev_priv->hw_status_page == NULL) {
673a394b
EA		 4339 DRM_ERROR("Failed to map status page.\n");
4340 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3eb2ee77 4341 i915_gem_object_unpin(obj);
673a394b
EA		 4342 drm_gem_object_unreference(obj);
4343 return -EINVAL;
4344 }
4345 dev_priv->hws_obj = obj;
673a394b
EA		 4346 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4347 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
ba1eb1d8 4348 I915_READ(HWS_PGA); /* posting read */
673a394b
EA		 4349 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4350
4351 return 0;
4352}
4353
85a7bb98
CW		 4354static void
4355i915_gem_cleanup_hws(struct drm_device *dev)
4356{
4357 drm_i915_private_t *dev_priv = dev->dev_private;
bab2d1f6
CW		 4358 struct drm_gem_object *obj;
4359 struct drm_i915_gem_object *obj_priv;
85a7bb98
CW		 4360
4361 if (dev_priv->hws_obj == NULL)
4362 return;
4363
bab2d1f6
CW		 4364 obj = dev_priv->hws_obj;
4365 obj_priv = obj->driver_private;
4366
856fa198 4367 kunmap(obj_priv->pages[0]);
85a7bb98
CW		 4368 i915_gem_object_unpin(obj);
4369 drm_gem_object_unreference(obj);
4370 dev_priv->hws_obj = NULL;
bab2d1f6 4371
85a7bb98
CW		 4372 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4373 dev_priv->hw_status_page = NULL;
4374
4375 /* Write high address into HWS_PGA when disabling. */
4376 I915_WRITE(HWS_PGA, 0x1ffff000);
4377}
4378
79e53945 4379int
673a394b
EA		 4380i915_gem_init_ringbuffer(struct drm_device *dev)
4381{
4382 drm_i915_private_t *dev_priv = dev->dev_private;
4383 struct drm_gem_object *obj;
4384 struct drm_i915_gem_object *obj_priv;
79e53945 4385 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
673a394b 4386 int ret;
50aa253d 4387 u32 head;
673a394b
EA		 4388
4389 ret = i915_gem_init_hws(dev);
4390 if (ret != 0)
4391 return ret;
4392
4393 obj = drm_gem_object_alloc(dev, 128 * 1024);
4394 if (obj == NULL) {
4395 DRM_ERROR("Failed to allocate ringbuffer\n");
85a7bb98 4396 i915_gem_cleanup_hws(dev);
673a394b
EA		 4397 return -ENOMEM;
4398 }
4399 obj_priv = obj->driver_private;
4400
4401 ret = i915_gem_object_pin(obj, 4096);
4402 if (ret != 0) {
4403 drm_gem_object_unreference(obj);
85a7bb98 4404 i915_gem_cleanup_hws(dev);
673a394b
EA		 4405 return ret;
4406 }
4407
4408 /* Set up the kernel mapping for the ring. */
79e53945 4409 ring->Size = obj->size;
673a394b 4410
79e53945
JB		 4411 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4412 ring->map.size = obj->size;
4413 ring->map.type = 0;
4414 ring->map.flags = 0;
4415 ring->map.mtrr = 0;
673a394b 4416
79e53945
JB		 4417 drm_core_ioremap_wc(&ring->map, dev);
4418 if (ring->map.handle == NULL) {
673a394b
EA		 4419 DRM_ERROR("Failed to map ringbuffer.\n");
4420 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
47ed185a 4421 i915_gem_object_unpin(obj);
673a394b 4422 drm_gem_object_unreference(obj);
85a7bb98 4423 i915_gem_cleanup_hws(dev);
673a394b
EA		 4424 return -EINVAL;
4425 }
79e53945
JB		 4426 ring->ring_obj = obj;
4427 ring->virtual_start = ring->map.handle;
673a394b
EA		 4428
4429 /* Stop the ring if it's running. */
4430 I915_WRITE(PRB0_CTL, 0);
673a394b 4431 I915_WRITE(PRB0_TAIL, 0);
50aa253d 4432 I915_WRITE(PRB0_HEAD, 0);
673a394b
EA		 4433
4434 /* Initialize the ring. */
4435 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
50aa253d
KP		 4436 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4437
4438 /* G45 ring initialization fails to reset head to zero */
4439 if (head != 0) {
4440 DRM_ERROR("Ring head not reset to zero "
4441 "ctl %08x head %08x tail %08x start %08x\n",
4442 I915_READ(PRB0_CTL),
4443 I915_READ(PRB0_HEAD),
4444 I915_READ(PRB0_TAIL),
4445 I915_READ(PRB0_START));
4446 I915_WRITE(PRB0_HEAD, 0);
4447
4448 DRM_ERROR("Ring head forced to zero "
4449 "ctl %08x head %08x tail %08x start %08x\n",
4450 I915_READ(PRB0_CTL),
4451 I915_READ(PRB0_HEAD),
4452 I915_READ(PRB0_TAIL),
4453 I915_READ(PRB0_START));
4454 }
4455
673a394b
EA		 4456 I915_WRITE(PRB0_CTL,
4457 ((obj->size - 4096) & RING_NR_PAGES) |
4458 RING_NO_REPORT |
4459 RING_VALID);
4460
50aa253d
KP		 4461 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4462
4463 /* If the head is still not zero, the ring is dead */
4464 if (head != 0) {
4465 DRM_ERROR("Ring initialization failed "
4466 "ctl %08x head %08x tail %08x start %08x\n",
4467 I915_READ(PRB0_CTL),
4468 I915_READ(PRB0_HEAD),
4469 I915_READ(PRB0_TAIL),
4470 I915_READ(PRB0_START));
4471 return -EIO;
4472 }
4473
673a394b 4474 /* Update our cache of the ring state */
79e53945
JB		 4475 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4476 i915_kernel_lost_context(dev);
4477 else {
4478 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4479 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4480 ring->space = ring->head - (ring->tail + 8);
4481 if (ring->space < 0)
4482 ring->space += ring->Size;
4483 }
673a394b
EA		 4484
4485 return 0;
4486}
4487
79e53945 4488void
673a394b
EA		 4489i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4490{
4491 drm_i915_private_t *dev_priv = dev->dev_private;
4492
4493 if (dev_priv->ring.ring_obj == NULL)
4494 return;
4495
4496 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4497
4498 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4499 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4500 dev_priv->ring.ring_obj = NULL;
4501 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4502
85a7bb98 4503 i915_gem_cleanup_hws(dev);
673a394b
EA		 4504}
4505
4506int
4507i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4508 struct drm_file *file_priv)
4509{
4510 drm_i915_private_t *dev_priv = dev->dev_private;
4511 int ret;
4512
79e53945
JB		 4513 if (drm_core_check_feature(dev, DRIVER_MODESET))
4514 return 0;
4515
ba1234d1 4516 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4517 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4518 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4519 }
4520
673a394b 4521 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4522 dev_priv->mm.suspended = 0;
4523
4524 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4525 if (ret != 0) {
4526 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4527 return ret;
d816f6ac 4528 }
9bb2d6f9 4529
5e118f41 4530 spin_lock(&dev_priv->mm.active_list_lock);
673a394b 4531 BUG_ON(!list_empty(&dev_priv->mm.active_list));
5e118f41
CW		 4532 spin_unlock(&dev_priv->mm.active_list_lock);
4533
673a394b
EA		 4534 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4535 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4536 BUG_ON(!list_empty(&dev_priv->mm.request_list));
673a394b 4537 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4538
4539 drm_irq_install(dev);
4540
673a394b
EA		 4541 return 0;
4542}
4543
4544int
4545i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4546 struct drm_file *file_priv)
4547{
4548 int ret;
4549
79e53945
JB		 4550 if (drm_core_check_feature(dev, DRIVER_MODESET))
4551 return 0;
4552
673a394b 4553 ret = i915_gem_idle(dev);
dbb19d30
KH		 4554 drm_irq_uninstall(dev);
4555
6dbe2772 4556 return ret;
673a394b
EA		 4557}
4558
4559void
4560i915_gem_lastclose(struct drm_device *dev)
4561{
4562 int ret;
673a394b 4563
e806b495
EA		 4564 if (drm_core_check_feature(dev, DRIVER_MODESET))
4565 return;
4566
6dbe2772
KP		 4567 ret = i915_gem_idle(dev);
4568 if (ret)
4569 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4570}
4571
4572void
4573i915_gem_load(struct drm_device *dev)
4574{
b5aa8a0f 4575 int i;
673a394b
EA		 4576 drm_i915_private_t *dev_priv = dev->dev_private;
4577
5e118f41 4578 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b
EA		 4579 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4580 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4581 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4582 INIT_LIST_HEAD(&dev_priv->mm.request_list);
a09ba7fa 4583 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
673a394b
EA		 4584 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4585 i915_gem_retire_work_handler);
4586 dev_priv->mm.next_gem_seqno = 1;
4587
31169714
CW		 4588 spin_lock(&shrink_list_lock);
4589 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4590 spin_unlock(&shrink_list_lock);
4591
de151cf6
JB		 4592 /* Old X drivers will take 0-2 for front, back, depth buffers */
4593 dev_priv->fence_reg_start = 3;
4594
0f973f27 4595 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4596 dev_priv->num_fence_regs = 16;
4597 else
4598 dev_priv->num_fence_regs = 8;
4599
b5aa8a0f
GH		 4600 /* Initialize fence registers to zero */
4601 if (IS_I965G(dev)) {
4602 for (i = 0; i < 16; i++)
4603 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4604 } else {
4605 for (i = 0; i < 8; i++)
4606 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4607 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4608 for (i = 0; i < 8; i++)
4609 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4610 }
4611
673a394b
EA		 4612 i915_gem_detect_bit_6_swizzle(dev);
4613}
71acb5eb
DA		 4614
4615/*
4616 * Create a physically contiguous memory object for this object
4617 * e.g. for cursor + overlay regs
4618 */
4619int i915_gem_init_phys_object(struct drm_device *dev,
4620 int id, int size)
4621{
4622 drm_i915_private_t *dev_priv = dev->dev_private;
4623 struct drm_i915_gem_phys_object *phys_obj;
4624 int ret;
4625
4626 if (dev_priv->mm.phys_objs[id - 1] || !size)
4627 return 0;
4628
9a298b2a 4629 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4630 if (!phys_obj)
4631 return -ENOMEM;
4632
4633 phys_obj->id = id;
4634
4635 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4636 if (!phys_obj->handle) {
4637 ret = -ENOMEM;
4638 goto kfree_obj;
4639 }
4640#ifdef CONFIG_X86
4641 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4642#endif
4643
4644 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4645
4646 return 0;
4647kfree_obj:
9a298b2a 4648 kfree(phys_obj);
71acb5eb
DA		 4649 return ret;
4650}
4651
4652void i915_gem_free_phys_object(struct drm_device *dev, int id)
4653{
4654 drm_i915_private_t *dev_priv = dev->dev_private;
4655 struct drm_i915_gem_phys_object *phys_obj;
4656
4657 if (!dev_priv->mm.phys_objs[id - 1])
4658 return;
4659
4660 phys_obj = dev_priv->mm.phys_objs[id - 1];
4661 if (phys_obj->cur_obj) {
4662 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4663 }
4664
4665#ifdef CONFIG_X86
4666 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4667#endif
4668 drm_pci_free(dev, phys_obj->handle);
4669 kfree(phys_obj);
4670 dev_priv->mm.phys_objs[id - 1] = NULL;
4671}
4672
4673void i915_gem_free_all_phys_object(struct drm_device *dev)
4674{
4675 int i;
4676
260883c8 4677 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4678 i915_gem_free_phys_object(dev, i);
4679}
4680
4681void i915_gem_detach_phys_object(struct drm_device *dev,
4682 struct drm_gem_object *obj)
4683{
4684 struct drm_i915_gem_object *obj_priv;
4685 int i;
4686 int ret;
4687 int page_count;
4688
4689 obj_priv = obj->driver_private;
4690 if (!obj_priv->phys_obj)
4691 return;
4692
856fa198 4693 ret = i915_gem_object_get_pages(obj);
71acb5eb
DA		 4694 if (ret)
4695 goto out;
4696
4697 page_count = obj->size / PAGE_SIZE;
4698
4699 for (i = 0; i < page_count; i++) {
856fa198 4700 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4701 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4702
4703 memcpy(dst, src, PAGE_SIZE);
4704 kunmap_atomic(dst, KM_USER0);
4705 }
856fa198 4706 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4707 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4708
4709 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4710out:
4711 obj_priv->phys_obj->cur_obj = NULL;
4712 obj_priv->phys_obj = NULL;
4713}
4714
4715int
4716i915_gem_attach_phys_object(struct drm_device *dev,
4717 struct drm_gem_object *obj, int id)
4718{
4719 drm_i915_private_t *dev_priv = dev->dev_private;
4720 struct drm_i915_gem_object *obj_priv;
4721 int ret = 0;
4722 int page_count;
4723 int i;
4724
4725 if (id > I915_MAX_PHYS_OBJECT)
4726 return -EINVAL;
4727
4728 obj_priv = obj->driver_private;
4729
4730 if (obj_priv->phys_obj) {
4731 if (obj_priv->phys_obj->id == id)
4732 return 0;
4733 i915_gem_detach_phys_object(dev, obj);
4734 }
4735
4736
4737 /* create a new object */
4738 if (!dev_priv->mm.phys_objs[id - 1]) {
4739 ret = i915_gem_init_phys_object(dev, id,
4740 obj->size);
4741 if (ret) {
aeb565df 4742 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4743 goto out;
4744 }
4745 }
4746
4747 /* bind to the object */
4748 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4749 obj_priv->phys_obj->cur_obj = obj;
4750
856fa198 4751 ret = i915_gem_object_get_pages(obj);
71acb5eb
DA		 4752 if (ret) {
4753 DRM_ERROR("failed to get page list\n");
4754 goto out;
4755 }
4756
4757 page_count = obj->size / PAGE_SIZE;
4758
4759 for (i = 0; i < page_count; i++) {
856fa198 4760 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4761 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4762
4763 memcpy(dst, src, PAGE_SIZE);
4764 kunmap_atomic(src, KM_USER0);
4765 }
4766
d78b47b9
CW		 4767 i915_gem_object_put_pages(obj);
4768
71acb5eb
DA		 4769 return 0;
4770out:
4771 return ret;
4772}
4773
4774static int
4775i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4776 struct drm_i915_gem_pwrite *args,
4777 struct drm_file *file_priv)
4778{
4779 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4780 void *obj_addr;
4781 int ret;
4782 char __user *user_data;
4783
4784 user_data = (char __user *) (uintptr_t) args->data_ptr;
4785 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4786
e08fb4f6 4787 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4788 ret = copy_from_user(obj_addr, user_data, args->size);
4789 if (ret)
4790 return -EFAULT;
4791
4792 drm_agp_chipset_flush(dev);
4793 return 0;
4794}
b962442e
EA		 4795
4796void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4797{
4798 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4799
4800 /* Clean up our request list when the client is going away, so that
4801 * later retire_requests won't dereference our soon-to-be-gone
4802 * file_priv.
4803 */
4804 mutex_lock(&dev->struct_mutex);
4805 while (!list_empty(&i915_file_priv->mm.request_list))
4806 list_del_init(i915_file_priv->mm.request_list.next);
4807 mutex_unlock(&dev->struct_mutex);
4808}
31169714
CW		 4809
4810/* Immediately discard the backing storage */
4811static void
4812i915_gem_object_truncate(struct drm_gem_object *obj)
4813{
4814 struct inode *inode;
4815
4816 inode = obj->filp->f_path.dentry->d_inode;
4817
4818 mutex_lock(&inode->i_mutex);
4819 truncate_inode_pages(inode->i_mapping, 0);
4820 mutex_unlock(&inode->i_mutex);
4821}
4822
31169714
CW		 4823static int
4824i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4825{
4826 drm_i915_private_t *dev_priv, *next_dev;
4827 struct drm_i915_gem_object *obj_priv, *next_obj;
4828 int cnt = 0;
4829 int would_deadlock = 1;
4830
4831 /* "fast-path" to count number of available objects */
4832 if (nr_to_scan == 0) {
4833 spin_lock(&shrink_list_lock);
4834 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4835 struct drm_device *dev = dev_priv->dev;
4836
4837 if (mutex_trylock(&dev->struct_mutex)) {
4838 list_for_each_entry(obj_priv,
4839 &dev_priv->mm.inactive_list,
4840 list)
4841 cnt++;
4842 mutex_unlock(&dev->struct_mutex);
4843 }
4844 }
4845 spin_unlock(&shrink_list_lock);
4846
4847 return (cnt / 100) * sysctl_vfs_cache_pressure;
4848 }
4849
4850 spin_lock(&shrink_list_lock);
4851
4852 /* first scan for clean buffers */
4853 list_for_each_entry_safe(dev_priv, next_dev,
4854 &shrink_list, mm.shrink_list) {
4855 struct drm_device *dev = dev_priv->dev;
4856
4857 if (! mutex_trylock(&dev->struct_mutex))
4858 continue;
4859
4860 spin_unlock(&shrink_list_lock);
4861
4862 i915_gem_retire_requests(dev);
4863
4864 list_for_each_entry_safe(obj_priv, next_obj,
4865 &dev_priv->mm.inactive_list,
4866 list) {
4867 if (i915_gem_object_is_purgeable(obj_priv)) {
4868 struct drm_gem_object *obj = obj_priv->obj;
4869 i915_gem_object_unbind(obj);
4870 i915_gem_object_truncate(obj);
4871
4872 if (--nr_to_scan <= 0)
4873 break;
4874 }
4875 }
4876
4877 spin_lock(&shrink_list_lock);
4878 mutex_unlock(&dev->struct_mutex);
4879
4880 if (nr_to_scan <= 0)
4881 break;
4882 }
4883
4884 /* second pass, evict/count anything still on the inactive list */
4885 list_for_each_entry_safe(dev_priv, next_dev,
4886 &shrink_list, mm.shrink_list) {
4887 struct drm_device *dev = dev_priv->dev;
4888
4889 if (! mutex_trylock(&dev->struct_mutex))
4890 continue;
4891
4892 spin_unlock(&shrink_list_lock);
4893
4894 list_for_each_entry_safe(obj_priv, next_obj,
4895 &dev_priv->mm.inactive_list,
4896 list) {
4897 if (nr_to_scan > 0) {
4898 struct drm_gem_object *obj = obj_priv->obj;
4899 i915_gem_object_unbind(obj);
4900 if (i915_gem_object_is_purgeable(obj_priv))
4901 i915_gem_object_truncate(obj);
4902
4903 nr_to_scan--;
4904 } else
4905 cnt++;
4906 }
4907
4908 spin_lock(&shrink_list_lock);
4909 mutex_unlock(&dev->struct_mutex);
4910
4911 would_deadlock = 0;
4912 }
4913
4914 spin_unlock(&shrink_list_lock);
4915
4916 if (would_deadlock)
4917 return -1;
4918 else if (cnt > 0)
4919 return (cnt / 100) * sysctl_vfs_cache_pressure;
4920 else
4921 return 0;
4922}
4923
4924static struct shrinker shrinker = {
4925 .shrink = i915_gem_shrink,
4926 .seeks = DEFAULT_SEEKS,
4927};
4928
4929__init void
4930i915_gem_shrinker_init(void)
4931{
4932 register_shrinker(&shrinker);
4933}
4934
4935__exit void
4936i915_gem_shrinker_exit(void)
4937{
4938 unregister_shrinker(&shrinker);
4939}
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