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drm/i915: Propagate error from drm_vblank_get() during page-flipping.
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
673a394b 37
e47c68e9
EA		 38static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 int write);
43static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
44 uint64_t offset,
45 uint64_t size);
46static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 47static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment);
de151cf6 50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 51static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 52static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
673a394b 56
31169714
CW		 57static LIST_HEAD(shrink_list);
58static DEFINE_SPINLOCK(shrink_list_lock);
59
79e53945
JB		 60int i915_gem_do_init(struct drm_device *dev, unsigned long start,
61 unsigned long end)
673a394b
EA		 62{
63 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 64
79e53945
JB		 65 if (start >= end ||
66 (start & (PAGE_SIZE - 1)) != 0 ||
67 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 68 return -EINVAL;
69 }
70
79e53945
JB		 71 drm_mm_init(&dev_priv->mm.gtt_space, start,
72 end - start);
673a394b 73
79e53945
JB		 74 dev->gtt_total = (uint32_t) (end - start);
75
76 return 0;
77}
673a394b 78
79e53945
JB		 79int
80i915_gem_init_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *file_priv)
82{
83 struct drm_i915_gem_init *args = data;
84 int ret;
85
86 mutex_lock(&dev->struct_mutex);
87 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 88 mutex_unlock(&dev->struct_mutex);
89
79e53945 90 return ret;
673a394b
EA		 91}
92
5a125c3c
EA		 93int
94i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
95 struct drm_file *file_priv)
96{
5a125c3c 97 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 98
99 if (!(dev->driver->driver_features & DRIVER_GEM))
100 return -ENODEV;
101
102 args->aper_size = dev->gtt_total;
2678d9d6
KP		 103 args->aper_available_size = (args->aper_size -
104 atomic_read(&dev->pin_memory));
5a125c3c
EA		 105
106 return 0;
107}
108
673a394b
EA		 109
110/**
111 * Creates a new mm object and returns a handle to it.
112 */
113int
114i915_gem_create_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
116{
117 struct drm_i915_gem_create *args = data;
118 struct drm_gem_object *obj;
a1a2d1d3
PP		 119 int ret;
120 u32 handle;
673a394b
EA		 121
122 args->size = roundup(args->size, PAGE_SIZE);
123
124 /* Allocate the new object */
ac52bc56 125 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 126 if (obj == NULL)
127 return -ENOMEM;
128
129 ret = drm_gem_handle_create(file_priv, obj, &handle);
bc9025bd 130 drm_gem_object_handle_unreference_unlocked(obj);
673a394b
EA		 131
132 if (ret)
133 return ret;
134
135 args->handle = handle;
136
137 return 0;
138}
139
eb01459f
EA		 140static inline int
141fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
143 char __user *data,
144 int length)
145{
146 char __iomem *vaddr;
2bc43b5c 147 int unwritten;
eb01459f
EA		 148
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 if (vaddr == NULL)
151 return -ENOMEM;
2bc43b5c 152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 153 kunmap_atomic(vaddr, KM_USER0);
154
2bc43b5c
FM		 155 if (unwritten)
156 return -EFAULT;
157
158 return 0;
eb01459f
EA		 159}
160
280b713b
EA		 161static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
162{
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 165
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
168}
169
99a03df5 170static inline void
40123c1f
EA		 171slow_shmem_copy(struct page *dst_page,
172 int dst_offset,
173 struct page *src_page,
174 int src_offset,
175 int length)
176{
177 char *dst_vaddr, *src_vaddr;
178
99a03df5
CW		 179 dst_vaddr = kmap(dst_page);
180 src_vaddr = kmap(src_page);
40123c1f
EA		 181
182 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
183
99a03df5
CW		 184 kunmap(src_page);
185 kunmap(dst_page);
40123c1f
EA		 186}
187
99a03df5 188static inline void
280b713b
EA		 189slow_shmem_bit17_copy(struct page *gpu_page,
190 int gpu_offset,
191 struct page *cpu_page,
192 int cpu_offset,
193 int length,
194 int is_read)
195{
196 char *gpu_vaddr, *cpu_vaddr;
197
198 /* Use the unswizzled path if this page isn't affected. */
199 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
200 if (is_read)
201 return slow_shmem_copy(cpu_page, cpu_offset,
202 gpu_page, gpu_offset, length);
203 else
204 return slow_shmem_copy(gpu_page, gpu_offset,
205 cpu_page, cpu_offset, length);
206 }
207
99a03df5
CW		 208 gpu_vaddr = kmap(gpu_page);
209 cpu_vaddr = kmap(cpu_page);
280b713b
EA		 210
211 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
212 * XORing with the other bits (A9 for Y, A9 and A10 for X)
213 */
214 while (length > 0) {
215 int cacheline_end = ALIGN(gpu_offset + 1, 64);
216 int this_length = min(cacheline_end - gpu_offset, length);
217 int swizzled_gpu_offset = gpu_offset ^ 64;
218
219 if (is_read) {
220 memcpy(cpu_vaddr + cpu_offset,
221 gpu_vaddr + swizzled_gpu_offset,
222 this_length);
223 } else {
224 memcpy(gpu_vaddr + swizzled_gpu_offset,
225 cpu_vaddr + cpu_offset,
226 this_length);
227 }
228 cpu_offset += this_length;
229 gpu_offset += this_length;
230 length -= this_length;
231 }
232
99a03df5
CW		 233 kunmap(cpu_page);
234 kunmap(gpu_page);
280b713b
EA		 235}
236
eb01459f
EA		 237/**
238 * This is the fast shmem pread path, which attempts to copy_from_user directly
239 * from the backing pages of the object to the user's address space. On a
240 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
241 */
242static int
243i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
244 struct drm_i915_gem_pread *args,
245 struct drm_file *file_priv)
246{
23010e43 247 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 248 ssize_t remain;
249 loff_t offset, page_base;
250 char __user *user_data;
251 int page_offset, page_length;
252 int ret;
253
254 user_data = (char __user *) (uintptr_t) args->data_ptr;
255 remain = args->size;
256
257 mutex_lock(&dev->struct_mutex);
258
4bdadb97 259 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 260 if (ret != 0)
261 goto fail_unlock;
262
263 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
264 args->size);
265 if (ret != 0)
266 goto fail_put_pages;
267
23010e43 268 obj_priv = to_intel_bo(obj);
eb01459f
EA		 269 offset = args->offset;
270
271 while (remain > 0) {
272 /* Operation in this page
273 *
274 * page_base = page offset within aperture
275 * page_offset = offset within page
276 * page_length = bytes to copy for this page
277 */
278 page_base = (offset & ~(PAGE_SIZE-1));
279 page_offset = offset & (PAGE_SIZE-1);
280 page_length = remain;
281 if ((page_offset + remain) > PAGE_SIZE)
282 page_length = PAGE_SIZE - page_offset;
283
284 ret = fast_shmem_read(obj_priv->pages,
285 page_base, page_offset,
286 user_data, page_length);
287 if (ret)
288 goto fail_put_pages;
289
290 remain -= page_length;
291 user_data += page_length;
292 offset += page_length;
293 }
294
295fail_put_pages:
296 i915_gem_object_put_pages(obj);
297fail_unlock:
298 mutex_unlock(&dev->struct_mutex);
299
300 return ret;
301}
302
07f73f69
CW		 303static int
304i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
305{
306 int ret;
307
4bdadb97 308 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 309
310 /* If we've insufficient memory to map in the pages, attempt
311 * to make some space by throwing out some old buffers.
312 */
313 if (ret == -ENOMEM) {
314 struct drm_device *dev = obj->dev;
07f73f69
CW		 315
316 ret = i915_gem_evict_something(dev, obj->size);
317 if (ret)
318 return ret;
319
4bdadb97 320 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 321 }
322
323 return ret;
324}
325
eb01459f
EA		 326/**
327 * This is the fallback shmem pread path, which allocates temporary storage
328 * in kernel space to copy_to_user into outside of the struct_mutex, so we
329 * can copy out of the object's backing pages while holding the struct mutex
330 * and not take page faults.
331 */
332static int
333i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
334 struct drm_i915_gem_pread *args,
335 struct drm_file *file_priv)
336{
23010e43 337 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 338 struct mm_struct *mm = current->mm;
339 struct page **user_pages;
340 ssize_t remain;
341 loff_t offset, pinned_pages, i;
342 loff_t first_data_page, last_data_page, num_pages;
343 int shmem_page_index, shmem_page_offset;
344 int data_page_index, data_page_offset;
345 int page_length;
346 int ret;
347 uint64_t data_ptr = args->data_ptr;
280b713b 348 int do_bit17_swizzling;
eb01459f
EA		 349
350 remain = args->size;
351
352 /* Pin the user pages containing the data. We can't fault while
353 * holding the struct mutex, yet we want to hold it while
354 * dereferencing the user data.
355 */
356 first_data_page = data_ptr / PAGE_SIZE;
357 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
358 num_pages = last_data_page - first_data_page + 1;
359
8e7d2b2c 360 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 361 if (user_pages == NULL)
362 return -ENOMEM;
363
364 down_read(&mm->mmap_sem);
365 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 366 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 367 up_read(&mm->mmap_sem);
368 if (pinned_pages < num_pages) {
369 ret = -EFAULT;
370 goto fail_put_user_pages;
371 }
372
280b713b
EA		 373 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
374
eb01459f
EA		 375 mutex_lock(&dev->struct_mutex);
376
07f73f69
CW		 377 ret = i915_gem_object_get_pages_or_evict(obj);
378 if (ret)
eb01459f
EA		 379 goto fail_unlock;
380
381 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
382 args->size);
383 if (ret != 0)
384 goto fail_put_pages;
385
23010e43 386 obj_priv = to_intel_bo(obj);
eb01459f
EA		 387 offset = args->offset;
388
389 while (remain > 0) {
390 /* Operation in this page
391 *
392 * shmem_page_index = page number within shmem file
393 * shmem_page_offset = offset within page in shmem file
394 * data_page_index = page number in get_user_pages return
395 * data_page_offset = offset with data_page_index page.
396 * page_length = bytes to copy for this page
397 */
398 shmem_page_index = offset / PAGE_SIZE;
399 shmem_page_offset = offset & ~PAGE_MASK;
400 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
401 data_page_offset = data_ptr & ~PAGE_MASK;
402
403 page_length = remain;
404 if ((shmem_page_offset + page_length) > PAGE_SIZE)
405 page_length = PAGE_SIZE - shmem_page_offset;
406 if ((data_page_offset + page_length) > PAGE_SIZE)
407 page_length = PAGE_SIZE - data_page_offset;
408
280b713b 409 if (do_bit17_swizzling) {
99a03df5 410 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b 411 shmem_page_offset,
99a03df5
CW		 412 user_pages[data_page_index],
413 data_page_offset,
414 page_length,
415 1);
416 } else {
417 slow_shmem_copy(user_pages[data_page_index],
418 data_page_offset,
419 obj_priv->pages[shmem_page_index],
420 shmem_page_offset,
421 page_length);
280b713b 422 }
eb01459f
EA		 423
424 remain -= page_length;
425 data_ptr += page_length;
426 offset += page_length;
427 }
428
429fail_put_pages:
430 i915_gem_object_put_pages(obj);
431fail_unlock:
432 mutex_unlock(&dev->struct_mutex);
433fail_put_user_pages:
434 for (i = 0; i < pinned_pages; i++) {
435 SetPageDirty(user_pages[i]);
436 page_cache_release(user_pages[i]);
437 }
8e7d2b2c 438 drm_free_large(user_pages);
eb01459f
EA		 439
440 return ret;
441}
442
673a394b
EA		 443/**
444 * Reads data from the object referenced by handle.
445 *
446 * On error, the contents of *data are undefined.
447 */
448int
449i915_gem_pread_ioctl(struct drm_device *dev, void *data,
450 struct drm_file *file_priv)
451{
452 struct drm_i915_gem_pread *args = data;
453 struct drm_gem_object *obj;
454 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 455 int ret;
456
457 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
458 if (obj == NULL)
459 return -EBADF;
23010e43 460 obj_priv = to_intel_bo(obj);
673a394b
EA		 461
462 /* Bounds check source.
463 *
464 * XXX: This could use review for overflow issues...
465 */
466 if (args->offset > obj->size || args->size > obj->size ||
467 args->offset + args->size > obj->size) {
bc9025bd 468 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 469 return -EINVAL;
470 }
471
280b713b 472 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 473 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 474 } else {
475 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
476 if (ret != 0)
477 ret = i915_gem_shmem_pread_slow(dev, obj, args,
478 file_priv);
479 }
673a394b 480
bc9025bd 481 drm_gem_object_unreference_unlocked(obj);
673a394b 482
eb01459f 483 return ret;
673a394b
EA		 484}
485
0839ccb8
KP		 486/* This is the fast write path which cannot handle
487 * page faults in the source data
9b7530cc 488 */
0839ccb8
KP		 489
490static inline int
491fast_user_write(struct io_mapping *mapping,
492 loff_t page_base, int page_offset,
493 char __user *user_data,
494 int length)
9b7530cc 495{
9b7530cc 496 char *vaddr_atomic;
0839ccb8 497 unsigned long unwritten;
9b7530cc 498
0839ccb8
KP		 499 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
500 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
501 user_data, length);
502 io_mapping_unmap_atomic(vaddr_atomic);
503 if (unwritten)
504 return -EFAULT;
505 return 0;
506}
507
508/* Here's the write path which can sleep for
509 * page faults
510 */
511
ab34c226 512static inline void
3de09aa3
EA		 513slow_kernel_write(struct io_mapping *mapping,
514 loff_t gtt_base, int gtt_offset,
515 struct page *user_page, int user_offset,
516 int length)
0839ccb8 517{
ab34c226
CW		 518 char __iomem *dst_vaddr;
519 char *src_vaddr;
0839ccb8 520
ab34c226
CW		 521 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
522 src_vaddr = kmap(user_page);
523
524 memcpy_toio(dst_vaddr + gtt_offset,
525 src_vaddr + user_offset,
526 length);
527
528 kunmap(user_page);
529 io_mapping_unmap(dst_vaddr);
9b7530cc
LT		 530}
531
40123c1f
EA		 532static inline int
533fast_shmem_write(struct page **pages,
534 loff_t page_base, int page_offset,
535 char __user *data,
536 int length)
537{
538 char __iomem *vaddr;
d0088775 539 unsigned long unwritten;
40123c1f
EA		 540
541 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
542 if (vaddr == NULL)
543 return -ENOMEM;
d0088775 544 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 545 kunmap_atomic(vaddr, KM_USER0);
546
d0088775
DA		 547 if (unwritten)
548 return -EFAULT;
40123c1f
EA		 549 return 0;
550}
551
3de09aa3
EA		 552/**
553 * This is the fast pwrite path, where we copy the data directly from the
554 * user into the GTT, uncached.
555 */
673a394b 556static int
3de09aa3
EA		 557i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
558 struct drm_i915_gem_pwrite *args,
559 struct drm_file *file_priv)
673a394b 560{
23010e43 561 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 562 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 563 ssize_t remain;
0839ccb8 564 loff_t offset, page_base;
673a394b 565 char __user *user_data;
0839ccb8
KP		 566 int page_offset, page_length;
567 int ret;
673a394b
EA		 568
569 user_data = (char __user *) (uintptr_t) args->data_ptr;
570 remain = args->size;
571 if (!access_ok(VERIFY_READ, user_data, remain))
572 return -EFAULT;
573
574
575 mutex_lock(&dev->struct_mutex);
576 ret = i915_gem_object_pin(obj, 0);
577 if (ret) {
578 mutex_unlock(&dev->struct_mutex);
579 return ret;
580 }
2ef7eeaa 581 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 582 if (ret)
583 goto fail;
584
23010e43 585 obj_priv = to_intel_bo(obj);
673a394b 586 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 587
588 while (remain > 0) {
589 /* Operation in this page
590 *
0839ccb8
KP		 591 * page_base = page offset within aperture
592 * page_offset = offset within page
593 * page_length = bytes to copy for this page
673a394b 594 */
0839ccb8
KP		 595 page_base = (offset & ~(PAGE_SIZE-1));
596 page_offset = offset & (PAGE_SIZE-1);
597 page_length = remain;
598 if ((page_offset + remain) > PAGE_SIZE)
599 page_length = PAGE_SIZE - page_offset;
600
601 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
602 page_offset, user_data, page_length);
603
604 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 605 * source page isn't available. Return the error and we'll
606 * retry in the slow path.
0839ccb8 607 */
3de09aa3
EA		 608 if (ret)
609 goto fail;
673a394b 610
0839ccb8
KP		 611 remain -= page_length;
612 user_data += page_length;
613 offset += page_length;
673a394b 614 }
673a394b
EA		 615
616fail:
617 i915_gem_object_unpin(obj);
618 mutex_unlock(&dev->struct_mutex);
619
620 return ret;
621}
622
3de09aa3
EA		 623/**
624 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
625 * the memory and maps it using kmap_atomic for copying.
626 *
627 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
628 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
629 */
3043c60c 630static int
3de09aa3
EA		 631i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
632 struct drm_i915_gem_pwrite *args,
633 struct drm_file *file_priv)
673a394b 634{
23010e43 635 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 636 drm_i915_private_t *dev_priv = dev->dev_private;
637 ssize_t remain;
638 loff_t gtt_page_base, offset;
639 loff_t first_data_page, last_data_page, num_pages;
640 loff_t pinned_pages, i;
641 struct page **user_pages;
642 struct mm_struct *mm = current->mm;
643 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 644 int ret;
3de09aa3
EA		 645 uint64_t data_ptr = args->data_ptr;
646
647 remain = args->size;
648
649 /* Pin the user pages containing the data. We can't fault while
650 * holding the struct mutex, and all of the pwrite implementations
651 * want to hold it while dereferencing the user data.
652 */
653 first_data_page = data_ptr / PAGE_SIZE;
654 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
655 num_pages = last_data_page - first_data_page + 1;
656
8e7d2b2c 657 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 658 if (user_pages == NULL)
659 return -ENOMEM;
660
661 down_read(&mm->mmap_sem);
662 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
663 num_pages, 0, 0, user_pages, NULL);
664 up_read(&mm->mmap_sem);
665 if (pinned_pages < num_pages) {
666 ret = -EFAULT;
667 goto out_unpin_pages;
668 }
673a394b
EA		 669
670 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 671 ret = i915_gem_object_pin(obj, 0);
672 if (ret)
673 goto out_unlock;
674
675 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
676 if (ret)
677 goto out_unpin_object;
678
23010e43 679 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 680 offset = obj_priv->gtt_offset + args->offset;
681
682 while (remain > 0) {
683 /* Operation in this page
684 *
685 * gtt_page_base = page offset within aperture
686 * gtt_page_offset = offset within page in aperture
687 * data_page_index = page number in get_user_pages return
688 * data_page_offset = offset with data_page_index page.
689 * page_length = bytes to copy for this page
690 */
691 gtt_page_base = offset & PAGE_MASK;
692 gtt_page_offset = offset & ~PAGE_MASK;
693 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
694 data_page_offset = data_ptr & ~PAGE_MASK;
695
696 page_length = remain;
697 if ((gtt_page_offset + page_length) > PAGE_SIZE)
698 page_length = PAGE_SIZE - gtt_page_offset;
699 if ((data_page_offset + page_length) > PAGE_SIZE)
700 page_length = PAGE_SIZE - data_page_offset;
701
ab34c226
CW		 702 slow_kernel_write(dev_priv->mm.gtt_mapping,
703 gtt_page_base, gtt_page_offset,
704 user_pages[data_page_index],
705 data_page_offset,
706 page_length);
3de09aa3
EA		 707
708 remain -= page_length;
709 offset += page_length;
710 data_ptr += page_length;
711 }
712
713out_unpin_object:
714 i915_gem_object_unpin(obj);
715out_unlock:
716 mutex_unlock(&dev->struct_mutex);
717out_unpin_pages:
718 for (i = 0; i < pinned_pages; i++)
719 page_cache_release(user_pages[i]);
8e7d2b2c 720 drm_free_large(user_pages);
3de09aa3
EA		 721
722 return ret;
723}
724
40123c1f
EA		 725/**
726 * This is the fast shmem pwrite path, which attempts to directly
727 * copy_from_user into the kmapped pages backing the object.
728 */
3043c60c 729static int
40123c1f
EA		 730i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
731 struct drm_i915_gem_pwrite *args,
732 struct drm_file *file_priv)
673a394b 733{
23010e43 734 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 735 ssize_t remain;
736 loff_t offset, page_base;
737 char __user *user_data;
738 int page_offset, page_length;
673a394b 739 int ret;
40123c1f
EA		 740
741 user_data = (char __user *) (uintptr_t) args->data_ptr;
742 remain = args->size;
673a394b
EA		 743
744 mutex_lock(&dev->struct_mutex);
745
4bdadb97 746 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 747 if (ret != 0)
748 goto fail_unlock;
673a394b 749
e47c68e9 750 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 751 if (ret != 0)
752 goto fail_put_pages;
753
23010e43 754 obj_priv = to_intel_bo(obj);
40123c1f
EA		 755 offset = args->offset;
756 obj_priv->dirty = 1;
757
758 while (remain > 0) {
759 /* Operation in this page
760 *
761 * page_base = page offset within aperture
762 * page_offset = offset within page
763 * page_length = bytes to copy for this page
764 */
765 page_base = (offset & ~(PAGE_SIZE-1));
766 page_offset = offset & (PAGE_SIZE-1);
767 page_length = remain;
768 if ((page_offset + remain) > PAGE_SIZE)
769 page_length = PAGE_SIZE - page_offset;
770
771 ret = fast_shmem_write(obj_priv->pages,
772 page_base, page_offset,
773 user_data, page_length);
774 if (ret)
775 goto fail_put_pages;
776
777 remain -= page_length;
778 user_data += page_length;
779 offset += page_length;
780 }
781
782fail_put_pages:
783 i915_gem_object_put_pages(obj);
784fail_unlock:
785 mutex_unlock(&dev->struct_mutex);
786
787 return ret;
788}
789
790/**
791 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
792 * the memory and maps it using kmap_atomic for copying.
793 *
794 * This avoids taking mmap_sem for faulting on the user's address while the
795 * struct_mutex is held.
796 */
797static int
798i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
799 struct drm_i915_gem_pwrite *args,
800 struct drm_file *file_priv)
801{
23010e43 802 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 803 struct mm_struct *mm = current->mm;
804 struct page **user_pages;
805 ssize_t remain;
806 loff_t offset, pinned_pages, i;
807 loff_t first_data_page, last_data_page, num_pages;
808 int shmem_page_index, shmem_page_offset;
809 int data_page_index, data_page_offset;
810 int page_length;
811 int ret;
812 uint64_t data_ptr = args->data_ptr;
280b713b 813 int do_bit17_swizzling;
40123c1f
EA		 814
815 remain = args->size;
816
817 /* Pin the user pages containing the data. We can't fault while
818 * holding the struct mutex, and all of the pwrite implementations
819 * want to hold it while dereferencing the user data.
820 */
821 first_data_page = data_ptr / PAGE_SIZE;
822 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
823 num_pages = last_data_page - first_data_page + 1;
824
8e7d2b2c 825 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 826 if (user_pages == NULL)
827 return -ENOMEM;
828
829 down_read(&mm->mmap_sem);
830 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
831 num_pages, 0, 0, user_pages, NULL);
832 up_read(&mm->mmap_sem);
833 if (pinned_pages < num_pages) {
834 ret = -EFAULT;
835 goto fail_put_user_pages;
673a394b
EA		 836 }
837
280b713b
EA		 838 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
839
40123c1f
EA		 840 mutex_lock(&dev->struct_mutex);
841
07f73f69
CW		 842 ret = i915_gem_object_get_pages_or_evict(obj);
843 if (ret)
40123c1f
EA		 844 goto fail_unlock;
845
846 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
847 if (ret != 0)
848 goto fail_put_pages;
849
23010e43 850 obj_priv = to_intel_bo(obj);
673a394b 851 offset = args->offset;
40123c1f 852 obj_priv->dirty = 1;
673a394b 853
40123c1f
EA		 854 while (remain > 0) {
855 /* Operation in this page
856 *
857 * shmem_page_index = page number within shmem file
858 * shmem_page_offset = offset within page in shmem file
859 * data_page_index = page number in get_user_pages return
860 * data_page_offset = offset with data_page_index page.
861 * page_length = bytes to copy for this page
862 */
863 shmem_page_index = offset / PAGE_SIZE;
864 shmem_page_offset = offset & ~PAGE_MASK;
865 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
866 data_page_offset = data_ptr & ~PAGE_MASK;
867
868 page_length = remain;
869 if ((shmem_page_offset + page_length) > PAGE_SIZE)
870 page_length = PAGE_SIZE - shmem_page_offset;
871 if ((data_page_offset + page_length) > PAGE_SIZE)
872 page_length = PAGE_SIZE - data_page_offset;
873
280b713b 874 if (do_bit17_swizzling) {
99a03df5 875 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b
EA		 876 shmem_page_offset,
877 user_pages[data_page_index],
878 data_page_offset,
99a03df5
CW		 879 page_length,
880 0);
881 } else {
882 slow_shmem_copy(obj_priv->pages[shmem_page_index],
883 shmem_page_offset,
884 user_pages[data_page_index],
885 data_page_offset,
886 page_length);
280b713b 887 }
40123c1f
EA		 888
889 remain -= page_length;
890 data_ptr += page_length;
891 offset += page_length;
673a394b
EA		 892 }
893
40123c1f
EA		 894fail_put_pages:
895 i915_gem_object_put_pages(obj);
896fail_unlock:
673a394b 897 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 898fail_put_user_pages:
899 for (i = 0; i < pinned_pages; i++)
900 page_cache_release(user_pages[i]);
8e7d2b2c 901 drm_free_large(user_pages);
673a394b 902
40123c1f 903 return ret;
673a394b
EA		 904}
905
906/**
907 * Writes data to the object referenced by handle.
908 *
909 * On error, the contents of the buffer that were to be modified are undefined.
910 */
911int
912i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
913 struct drm_file *file_priv)
914{
915 struct drm_i915_gem_pwrite *args = data;
916 struct drm_gem_object *obj;
917 struct drm_i915_gem_object *obj_priv;
918 int ret = 0;
919
920 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
921 if (obj == NULL)
922 return -EBADF;
23010e43 923 obj_priv = to_intel_bo(obj);
673a394b
EA		 924
925 /* Bounds check destination.
926 *
927 * XXX: This could use review for overflow issues...
928 */
929 if (args->offset > obj->size || args->size > obj->size ||
930 args->offset + args->size > obj->size) {
bc9025bd 931 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 932 return -EINVAL;
933 }
934
935 /* We can only do the GTT pwrite on untiled buffers, as otherwise
936 * it would end up going through the fenced access, and we'll get
937 * different detiling behavior between reading and writing.
938 * pread/pwrite currently are reading and writing from the CPU
939 * perspective, requiring manual detiling by the client.
940 */
71acb5eb
DA		 941 if (obj_priv->phys_obj)
942 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
943 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
9b8c4a0b
CW		 944 dev->gtt_total != 0 &&
945 obj->write_domain != I915_GEM_DOMAIN_CPU) {
3de09aa3
EA		 946 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
947 if (ret == -EFAULT) {
948 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
949 file_priv);
950 }
280b713b
EA		 951 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
952 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 953 } else {
954 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
955 if (ret == -EFAULT) {
956 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
957 file_priv);
958 }
959 }
673a394b
EA		 960
961#if WATCH_PWRITE
962 if (ret)
963 DRM_INFO("pwrite failed %d\n", ret);
964#endif
965
bc9025bd 966 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 967
968 return ret;
969}
970
971/**
2ef7eeaa
EA		 972 * Called when user space prepares to use an object with the CPU, either
973 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 974 */
975int
976i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *file_priv)
978{
a09ba7fa 979 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 980 struct drm_i915_gem_set_domain *args = data;
981 struct drm_gem_object *obj;
652c393a 982 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 983 uint32_t read_domains = args->read_domains;
984 uint32_t write_domain = args->write_domain;
673a394b
EA		 985 int ret;
986
987 if (!(dev->driver->driver_features & DRIVER_GEM))
988 return -ENODEV;
989
2ef7eeaa 990 /* Only handle setting domains to types used by the CPU. */
21d509e3 991 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 992 return -EINVAL;
993
21d509e3 994 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 995 return -EINVAL;
996
997 /* Having something in the write domain implies it's in the read
998 * domain, and only that read domain. Enforce that in the request.
999 */
1000 if (write_domain != 0 && read_domains != write_domain)
1001 return -EINVAL;
1002
673a394b
EA		 1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1004 if (obj == NULL)
1005 return -EBADF;
23010e43 1006 obj_priv = to_intel_bo(obj);
673a394b
EA		 1007
1008 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1009
1010 intel_mark_busy(dev, obj);
1011
673a394b 1012#if WATCH_BUF
cfd43c02 1013 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1014 obj, obj->size, read_domains, write_domain);
673a394b 1015#endif
2ef7eeaa
EA		 1016 if (read_domains & I915_GEM_DOMAIN_GTT) {
1017 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1018
a09ba7fa
EA		 1019 /* Update the LRU on the fence for the CPU access that's
1020 * about to occur.
1021 */
1022 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1023 struct drm_i915_fence_reg *reg =
1024 &dev_priv->fence_regs[obj_priv->fence_reg];
1025 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1026 &dev_priv->mm.fence_list);
1027 }
1028
02354392
EA		 1029 /* Silently promote "you're not bound, there was nothing to do"
1030 * to success, since the client was just asking us to
1031 * make sure everything was done.
1032 */
1033 if (ret == -EINVAL)
1034 ret = 0;
2ef7eeaa 1035 } else {
e47c68e9 1036 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1037 }
1038
673a394b
EA		 1039 drm_gem_object_unreference(obj);
1040 mutex_unlock(&dev->struct_mutex);
1041 return ret;
1042}
1043
1044/**
1045 * Called when user space has done writes to this buffer
1046 */
1047int
1048i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv)
1050{
1051 struct drm_i915_gem_sw_finish *args = data;
1052 struct drm_gem_object *obj;
1053 struct drm_i915_gem_object *obj_priv;
1054 int ret = 0;
1055
1056 if (!(dev->driver->driver_features & DRIVER_GEM))
1057 return -ENODEV;
1058
1059 mutex_lock(&dev->struct_mutex);
1060 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1061 if (obj == NULL) {
1062 mutex_unlock(&dev->struct_mutex);
1063 return -EBADF;
1064 }
1065
1066#if WATCH_BUF
cfd43c02 1067 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1068 __func__, args->handle, obj, obj->size);
1069#endif
23010e43 1070 obj_priv = to_intel_bo(obj);
673a394b
EA		 1071
1072 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1073 if (obj_priv->pin_count)
1074 i915_gem_object_flush_cpu_write_domain(obj);
1075
673a394b
EA		 1076 drm_gem_object_unreference(obj);
1077 mutex_unlock(&dev->struct_mutex);
1078 return ret;
1079}
1080
1081/**
1082 * Maps the contents of an object, returning the address it is mapped
1083 * into.
1084 *
1085 * While the mapping holds a reference on the contents of the object, it doesn't
1086 * imply a ref on the object itself.
1087 */
1088int
1089i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1090 struct drm_file *file_priv)
1091{
1092 struct drm_i915_gem_mmap *args = data;
1093 struct drm_gem_object *obj;
1094 loff_t offset;
1095 unsigned long addr;
1096
1097 if (!(dev->driver->driver_features & DRIVER_GEM))
1098 return -ENODEV;
1099
1100 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1101 if (obj == NULL)
1102 return -EBADF;
1103
1104 offset = args->offset;
1105
1106 down_write(&current->mm->mmap_sem);
1107 addr = do_mmap(obj->filp, 0, args->size,
1108 PROT_READ | PROT_WRITE, MAP_SHARED,
1109 args->offset);
1110 up_write(&current->mm->mmap_sem);
bc9025bd 1111 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1112 if (IS_ERR((void *)addr))
1113 return addr;
1114
1115 args->addr_ptr = (uint64_t) addr;
1116
1117 return 0;
1118}
1119
de151cf6
JB		 1120/**
1121 * i915_gem_fault - fault a page into the GTT
1122 * vma: VMA in question
1123 * vmf: fault info
1124 *
1125 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1126 * from userspace. The fault handler takes care of binding the object to
1127 * the GTT (if needed), allocating and programming a fence register (again,
1128 * only if needed based on whether the old reg is still valid or the object
1129 * is tiled) and inserting a new PTE into the faulting process.
1130 *
1131 * Note that the faulting process may involve evicting existing objects
1132 * from the GTT and/or fence registers to make room. So performance may
1133 * suffer if the GTT working set is large or there are few fence registers
1134 * left.
1135 */
1136int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1137{
1138 struct drm_gem_object *obj = vma->vm_private_data;
1139 struct drm_device *dev = obj->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 1141 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1142 pgoff_t page_offset;
1143 unsigned long pfn;
1144 int ret = 0;
0f973f27 1145 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1146
1147 /* We don't use vmf->pgoff since that has the fake offset */
1148 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1149 PAGE_SHIFT;
1150
1151 /* Now bind it into the GTT if needed */
1152 mutex_lock(&dev->struct_mutex);
1153 if (!obj_priv->gtt_space) {
e67b8ce1 1154 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1155 if (ret)
1156 goto unlock;
07f4f3e8 1157
14b60391 1158 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1159
1160 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1161 if (ret)
1162 goto unlock;
de151cf6
JB		 1163 }
1164
1165 /* Need a new fence register? */
a09ba7fa 1166 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1167 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1168 if (ret)
1169 goto unlock;
d9ddcb96 1170 }
de151cf6
JB		 1171
1172 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1173 page_offset;
1174
1175 /* Finally, remap it using the new GTT offset */
1176 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1177unlock:
de151cf6
JB		 1178 mutex_unlock(&dev->struct_mutex);
1179
1180 switch (ret) {
c715089f
CW		 1181 case 0:
1182 case -ERESTARTSYS:
1183 return VM_FAULT_NOPAGE;
de151cf6
JB		 1184 case -ENOMEM:
1185 case -EAGAIN:
1186 return VM_FAULT_OOM;
de151cf6 1187 default:
c715089f 1188 return VM_FAULT_SIGBUS;
de151cf6
JB		 1189 }
1190}
1191
1192/**
1193 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1194 * @obj: obj in question
1195 *
1196 * GEM memory mapping works by handing back to userspace a fake mmap offset
1197 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1198 * up the object based on the offset and sets up the various memory mapping
1199 * structures.
1200 *
1201 * This routine allocates and attaches a fake offset for @obj.
1202 */
1203static int
1204i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1205{
1206 struct drm_device *dev = obj->dev;
1207 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1208 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1209 struct drm_map_list *list;
f77d390c 1210 struct drm_local_map *map;
de151cf6
JB		 1211 int ret = 0;
1212
1213 /* Set the object up for mmap'ing */
1214 list = &obj->map_list;
9a298b2a 1215 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1216 if (!list->map)
1217 return -ENOMEM;
1218
1219 map = list->map;
1220 map->type = _DRM_GEM;
1221 map->size = obj->size;
1222 map->handle = obj;
1223
1224 /* Get a DRM GEM mmap offset allocated... */
1225 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1226 obj->size / PAGE_SIZE, 0, 0);
1227 if (!list->file_offset_node) {
1228 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1229 ret = -ENOMEM;
1230 goto out_free_list;
1231 }
1232
1233 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1234 obj->size / PAGE_SIZE, 0);
1235 if (!list->file_offset_node) {
1236 ret = -ENOMEM;
1237 goto out_free_list;
1238 }
1239
1240 list->hash.key = list->file_offset_node->start;
1241 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1242 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1243 ret = -ENOMEM;
de151cf6
JB		 1244 goto out_free_mm;
1245 }
1246
1247 /* By now we should be all set, any drm_mmap request on the offset
1248 * below will get to our mmap & fault handler */
1249 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1250
1251 return 0;
1252
1253out_free_mm:
1254 drm_mm_put_block(list->file_offset_node);
1255out_free_list:
9a298b2a 1256 kfree(list->map);
de151cf6
JB		 1257
1258 return ret;
1259}
1260
901782b2
CW		 1261/**
1262 * i915_gem_release_mmap - remove physical page mappings
1263 * @obj: obj in question
1264 *
af901ca1 1265 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1266 * relinquish ownership of the pages back to the system.
1267 *
1268 * It is vital that we remove the page mapping if we have mapped a tiled
1269 * object through the GTT and then lose the fence register due to
1270 * resource pressure. Similarly if the object has been moved out of the
1271 * aperture, than pages mapped into userspace must be revoked. Removing the
1272 * mapping will then trigger a page fault on the next user access, allowing
1273 * fixup by i915_gem_fault().
1274 */
d05ca301 1275void
901782b2
CW		 1276i915_gem_release_mmap(struct drm_gem_object *obj)
1277{
1278 struct drm_device *dev = obj->dev;
23010e43 1279 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1280
1281 if (dev->dev_mapping)
1282 unmap_mapping_range(dev->dev_mapping,
1283 obj_priv->mmap_offset, obj->size, 1);
1284}
1285
ab00b3e5
JB		 1286static void
1287i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1288{
1289 struct drm_device *dev = obj->dev;
23010e43 1290 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1291 struct drm_gem_mm *mm = dev->mm_private;
1292 struct drm_map_list *list;
1293
1294 list = &obj->map_list;
1295 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1296
1297 if (list->file_offset_node) {
1298 drm_mm_put_block(list->file_offset_node);
1299 list->file_offset_node = NULL;
1300 }
1301
1302 if (list->map) {
9a298b2a 1303 kfree(list->map);
ab00b3e5
JB		 1304 list->map = NULL;
1305 }
1306
1307 obj_priv->mmap_offset = 0;
1308}
1309
de151cf6
JB		 1310/**
1311 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1312 * @obj: object to check
1313 *
1314 * Return the required GTT alignment for an object, taking into account
1315 * potential fence register mapping if needed.
1316 */
1317static uint32_t
1318i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1319{
1320 struct drm_device *dev = obj->dev;
23010e43 1321 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1322 int start, i;
1323
1324 /*
1325 * Minimum alignment is 4k (GTT page size), but might be greater
1326 * if a fence register is needed for the object.
1327 */
1328 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1329 return 4096;
1330
1331 /*
1332 * Previous chips need to be aligned to the size of the smallest
1333 * fence register that can contain the object.
1334 */
1335 if (IS_I9XX(dev))
1336 start = 1024*1024;
1337 else
1338 start = 512*1024;
1339
1340 for (i = start; i < obj->size; i <<= 1)
1341 ;
1342
1343 return i;
1344}
1345
1346/**
1347 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1348 * @dev: DRM device
1349 * @data: GTT mapping ioctl data
1350 * @file_priv: GEM object info
1351 *
1352 * Simply returns the fake offset to userspace so it can mmap it.
1353 * The mmap call will end up in drm_gem_mmap(), which will set things
1354 * up so we can get faults in the handler above.
1355 *
1356 * The fault handler will take care of binding the object into the GTT
1357 * (since it may have been evicted to make room for something), allocating
1358 * a fence register, and mapping the appropriate aperture address into
1359 * userspace.
1360 */
1361int
1362i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1363 struct drm_file *file_priv)
1364{
1365 struct drm_i915_gem_mmap_gtt *args = data;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 struct drm_gem_object *obj;
1368 struct drm_i915_gem_object *obj_priv;
1369 int ret;
1370
1371 if (!(dev->driver->driver_features & DRIVER_GEM))
1372 return -ENODEV;
1373
1374 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1375 if (obj == NULL)
1376 return -EBADF;
1377
1378 mutex_lock(&dev->struct_mutex);
1379
23010e43 1380 obj_priv = to_intel_bo(obj);
de151cf6 1381
ab18282d
CW		 1382 if (obj_priv->madv != I915_MADV_WILLNEED) {
1383 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1384 drm_gem_object_unreference(obj);
1385 mutex_unlock(&dev->struct_mutex);
1386 return -EINVAL;
1387 }
1388
1389
de151cf6
JB		 1390 if (!obj_priv->mmap_offset) {
1391 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1392 if (ret) {
1393 drm_gem_object_unreference(obj);
1394 mutex_unlock(&dev->struct_mutex);
de151cf6 1395 return ret;
13af1062 1396 }
de151cf6
JB		 1397 }
1398
1399 args->offset = obj_priv->mmap_offset;
1400
de151cf6
JB		 1401 /*
1402 * Pull it into the GTT so that we have a page list (makes the
1403 * initial fault faster and any subsequent flushing possible).
1404 */
1405 if (!obj_priv->agp_mem) {
e67b8ce1 1406 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1407 if (ret) {
1408 drm_gem_object_unreference(obj);
1409 mutex_unlock(&dev->struct_mutex);
1410 return ret;
1411 }
14b60391 1412 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1413 }
1414
1415 drm_gem_object_unreference(obj);
1416 mutex_unlock(&dev->struct_mutex);
1417
1418 return 0;
1419}
1420
6911a9b8 1421void
856fa198 1422i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1423{
23010e43 1424 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1425 int page_count = obj->size / PAGE_SIZE;
1426 int i;
1427
856fa198 1428 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1429 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1430
856fa198
EA		 1431 if (--obj_priv->pages_refcount != 0)
1432 return;
673a394b 1433
280b713b
EA		 1434 if (obj_priv->tiling_mode != I915_TILING_NONE)
1435 i915_gem_object_save_bit_17_swizzle(obj);
1436
3ef94daa 1437 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1438 obj_priv->dirty = 0;
3ef94daa
CW		 1439
1440 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1441 if (obj_priv->dirty)
1442 set_page_dirty(obj_priv->pages[i]);
1443
1444 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1445 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1446
1447 page_cache_release(obj_priv->pages[i]);
1448 }
673a394b
EA		 1449 obj_priv->dirty = 0;
1450
8e7d2b2c 1451 drm_free_large(obj_priv->pages);
856fa198 1452 obj_priv->pages = NULL;
673a394b
EA		 1453}
1454
1455static void
852835f3
ZN		 1456i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1457 struct intel_ring_buffer *ring)
673a394b
EA		 1458{
1459 struct drm_device *dev = obj->dev;
1460 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1461 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
852835f3
ZN		 1462 BUG_ON(ring == NULL);
1463 obj_priv->ring = ring;
673a394b
EA		 1464
1465 /* Add a reference if we're newly entering the active list. */
1466 if (!obj_priv->active) {
1467 drm_gem_object_reference(obj);
1468 obj_priv->active = 1;
1469 }
1470 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1471 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1472 list_move_tail(&obj_priv->list, &ring->active_list);
5e118f41 1473 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1474 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1475}
1476
ce44b0ea
EA		 1477static void
1478i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1479{
1480 struct drm_device *dev = obj->dev;
1481 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1482 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1483
1484 BUG_ON(!obj_priv->active);
1485 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1486 obj_priv->last_rendering_seqno = 0;
1487}
673a394b 1488
963b4836
CW		 1489/* Immediately discard the backing storage */
1490static void
1491i915_gem_object_truncate(struct drm_gem_object *obj)
1492{
23010e43 1493 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1494 struct inode *inode;
963b4836 1495
bb6baf76
CW		 1496 inode = obj->filp->f_path.dentry->d_inode;
1497 if (inode->i_op->truncate)
1498 inode->i_op->truncate (inode);
1499
1500 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1501}
1502
1503static inline int
1504i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1505{
1506 return obj_priv->madv == I915_MADV_DONTNEED;
1507}
1508
673a394b
EA		 1509static void
1510i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1511{
1512 struct drm_device *dev = obj->dev;
1513 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1514 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1515
1516 i915_verify_inactive(dev, __FILE__, __LINE__);
1517 if (obj_priv->pin_count != 0)
1518 list_del_init(&obj_priv->list);
1519 else
1520 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1521
99fcb766
DV		 1522 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1523
ce44b0ea 1524 obj_priv->last_rendering_seqno = 0;
852835f3 1525 obj_priv->ring = NULL;
673a394b
EA		 1526 if (obj_priv->active) {
1527 obj_priv->active = 0;
1528 drm_gem_object_unreference(obj);
1529 }
1530 i915_verify_inactive(dev, __FILE__, __LINE__);
1531}
1532
63560396
DV		 1533static void
1534i915_gem_process_flushing_list(struct drm_device *dev,
852835f3
ZN		 1535 uint32_t flush_domains, uint32_t seqno,
1536 struct intel_ring_buffer *ring)
63560396
DV		 1537{
1538 drm_i915_private_t *dev_priv = dev->dev_private;
1539 struct drm_i915_gem_object *obj_priv, *next;
1540
1541 list_for_each_entry_safe(obj_priv, next,
1542 &dev_priv->mm.gpu_write_list,
1543 gpu_write_list) {
a8089e84 1544 struct drm_gem_object *obj = &obj_priv->base;
63560396
DV		 1545
1546 if ((obj->write_domain & flush_domains) ==
852835f3
ZN		 1547 obj->write_domain &&
1548 obj_priv->ring->ring_flag == ring->ring_flag) {
63560396
DV		 1549 uint32_t old_write_domain = obj->write_domain;
1550
1551 obj->write_domain = 0;
1552 list_del_init(&obj_priv->gpu_write_list);
852835f3 1553 i915_gem_object_move_to_active(obj, seqno, ring);
63560396
DV		 1554
1555 /* update the fence lru list */
007cc8ac
DV		 1556 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1557 struct drm_i915_fence_reg *reg =
1558 &dev_priv->fence_regs[obj_priv->fence_reg];
1559 list_move_tail(&reg->lru_list,
63560396 1560 &dev_priv->mm.fence_list);
007cc8ac 1561 }
63560396
DV		 1562
1563 trace_i915_gem_object_change_domain(obj,
1564 obj->read_domains,
1565 old_write_domain);
1566 }
1567 }
1568}
8187a2b7 1569
5a5a0c64 1570uint32_t
b962442e 1571i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
852835f3 1572 uint32_t flush_domains, struct intel_ring_buffer *ring)
673a394b
EA		 1573{
1574 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1575 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1576 struct drm_i915_gem_request *request;
1577 uint32_t seqno;
1578 int was_empty;
673a394b 1579
b962442e
EA		 1580 if (file_priv != NULL)
1581 i915_file_priv = file_priv->driver_priv;
1582
9a298b2a 1583 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1584 if (request == NULL)
1585 return 0;
1586
852835f3 1587 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
673a394b
EA		 1588
1589 request->seqno = seqno;
852835f3 1590 request->ring = ring;
673a394b 1591 request->emitted_jiffies = jiffies;
852835f3
ZN		 1592 was_empty = list_empty(&ring->request_list);
1593 list_add_tail(&request->list, &ring->request_list);
1594
b962442e
EA		 1595 if (i915_file_priv) {
1596 list_add_tail(&request->client_list,
1597 &i915_file_priv->mm.request_list);
1598 } else {
1599 INIT_LIST_HEAD(&request->client_list);
1600 }
673a394b 1601
ce44b0ea
EA		 1602 /* Associate any objects on the flushing list matching the write
1603 * domain we're flushing with our flush.
1604 */
63560396 1605 if (flush_domains != 0)
852835f3 1606 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
ce44b0ea 1607
f65d9421
BG		 1608 if (!dev_priv->mm.suspended) {
1609 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1610 if (was_empty)
1611 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1612 }
673a394b
EA		 1613 return seqno;
1614}
1615
1616/**
1617 * Command execution barrier
1618 *
1619 * Ensures that all commands in the ring are finished
1620 * before signalling the CPU
1621 */
3043c60c 1622static uint32_t
852835f3 1623i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
673a394b 1624{
673a394b 1625 uint32_t flush_domains = 0;
673a394b
EA		 1626
1627 /* The sampler always gets flushed on i965 (sigh) */
1628 if (IS_I965G(dev))
1629 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
852835f3
ZN		 1630
1631 ring->flush(dev, ring,
1632 I915_GEM_DOMAIN_COMMAND, flush_domains);
673a394b
EA		 1633 return flush_domains;
1634}
1635
1636/**
1637 * Moves buffers associated only with the given active seqno from the active
1638 * to inactive list, potentially freeing them.
1639 */
1640static void
1641i915_gem_retire_request(struct drm_device *dev,
1642 struct drm_i915_gem_request *request)
1643{
1644 drm_i915_private_t *dev_priv = dev->dev_private;
1645
1c5d22f7
CW		 1646 trace_i915_gem_request_retire(dev, request->seqno);
1647
673a394b
EA		 1648 /* Move any buffers on the active list that are no longer referenced
1649 * by the ringbuffer to the flushing/inactive lists as appropriate.
1650 */
5e118f41 1651 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1652 while (!list_empty(&request->ring->active_list)) {
673a394b
EA		 1653 struct drm_gem_object *obj;
1654 struct drm_i915_gem_object *obj_priv;
1655
852835f3 1656 obj_priv = list_first_entry(&request->ring->active_list,
673a394b
EA		 1657 struct drm_i915_gem_object,
1658 list);
a8089e84 1659 obj = &obj_priv->base;
673a394b
EA		 1660
1661 /* If the seqno being retired doesn't match the oldest in the
1662 * list, then the oldest in the list must still be newer than
1663 * this seqno.
1664 */
1665 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1666 goto out;
de151cf6 1667
673a394b
EA		 1668#if WATCH_LRU
1669 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1670 __func__, request->seqno, obj);
1671#endif
1672
ce44b0ea
EA		 1673 if (obj->write_domain != 0)
1674 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1675 else {
1676 /* Take a reference on the object so it won't be
1677 * freed while the spinlock is held. The list
1678 * protection for this spinlock is safe when breaking
1679 * the lock like this since the next thing we do
1680 * is just get the head of the list again.
1681 */
1682 drm_gem_object_reference(obj);
673a394b 1683 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1684 spin_unlock(&dev_priv->mm.active_list_lock);
1685 drm_gem_object_unreference(obj);
1686 spin_lock(&dev_priv->mm.active_list_lock);
1687 }
673a394b 1688 }
5e118f41
CW		 1689out:
1690 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1691}
1692
1693/**
1694 * Returns true if seq1 is later than seq2.
1695 */
22be1724 1696bool
673a394b
EA		 1697i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1698{
1699 return (int32_t)(seq1 - seq2) >= 0;
1700}
1701
1702uint32_t
852835f3 1703i915_get_gem_seqno(struct drm_device *dev,
d1b851fc 1704 struct intel_ring_buffer *ring)
673a394b 1705{
852835f3 1706 return ring->get_gem_seqno(dev, ring);
673a394b
EA		 1707}
1708
1709/**
1710 * This function clears the request list as sequence numbers are passed.
1711 */
1712void
852835f3
ZN		 1713i915_gem_retire_requests(struct drm_device *dev,
1714 struct intel_ring_buffer *ring)
673a394b
EA		 1715{
1716 drm_i915_private_t *dev_priv = dev->dev_private;
1717 uint32_t seqno;
1718
8187a2b7 1719 if (!ring->status_page.page_addr
852835f3 1720 || list_empty(&ring->request_list))
6c0594a3
KW		 1721 return;
1722
852835f3 1723 seqno = i915_get_gem_seqno(dev, ring);
673a394b 1724
852835f3 1725 while (!list_empty(&ring->request_list)) {
673a394b
EA		 1726 struct drm_i915_gem_request *request;
1727 uint32_t retiring_seqno;
1728
852835f3 1729 request = list_first_entry(&ring->request_list,
673a394b
EA		 1730 struct drm_i915_gem_request,
1731 list);
1732 retiring_seqno = request->seqno;
1733
1734 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1735 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1736 i915_gem_retire_request(dev, request);
1737
1738 list_del(&request->list);
b962442e 1739 list_del(&request->client_list);
9a298b2a 1740 kfree(request);
673a394b
EA		 1741 } else
1742 break;
1743 }
9d34e5db
CW		 1744
1745 if (unlikely (dev_priv->trace_irq_seqno &&
1746 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7
ZN		 1747
1748 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1749 dev_priv->trace_irq_seqno = 0;
1750 }
673a394b
EA		 1751}
1752
1753void
1754i915_gem_retire_work_handler(struct work_struct *work)
1755{
1756 drm_i915_private_t *dev_priv;
1757 struct drm_device *dev;
1758
1759 dev_priv = container_of(work, drm_i915_private_t,
1760 mm.retire_work.work);
1761 dev = dev_priv->dev;
1762
1763 mutex_lock(&dev->struct_mutex);
852835f3
ZN		 1764 i915_gem_retire_requests(dev, &dev_priv->render_ring);
1765
d1b851fc
ZN		 1766 if (HAS_BSD(dev))
1767 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
1768
6dbe2772 1769 if (!dev_priv->mm.suspended &&
d1b851fc
ZN		 1770 (!list_empty(&dev_priv->render_ring.request_list) ||
1771 (HAS_BSD(dev) &&
1772 !list_empty(&dev_priv->bsd_ring.request_list))))
9c9fe1f8 1773 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1774 mutex_unlock(&dev->struct_mutex);
1775}
1776
5a5a0c64 1777int
852835f3
ZN		 1778i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1779 int interruptible, struct intel_ring_buffer *ring)
673a394b
EA		 1780{
1781 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1782 u32 ier;
673a394b
EA		 1783 int ret = 0;
1784
1785 BUG_ON(seqno == 0);
1786
ba1234d1 1787 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1788 return -EIO;
1789
852835f3 1790 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
bad720ff 1791 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1792 ier = I915_READ(DEIER) | I915_READ(GTIER);
1793 else
1794 ier = I915_READ(IER);
802c7eb6
JB		 1795 if (!ier) {
1796 DRM_ERROR("something (likely vbetool) disabled "
1797 "interrupts, re-enabling\n");
1798 i915_driver_irq_preinstall(dev);
1799 i915_driver_irq_postinstall(dev);
1800 }
1801
1c5d22f7
CW		 1802 trace_i915_gem_request_wait_begin(dev, seqno);
1803
852835f3 1804 ring->waiting_gem_seqno = seqno;
8187a2b7 1805 ring->user_irq_get(dev, ring);
48764bf4 1806 if (interruptible)
852835f3
ZN		 1807 ret = wait_event_interruptible(ring->irq_queue,
1808 i915_seqno_passed(
1809 ring->get_gem_seqno(dev, ring), seqno)
1810 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1811 else
852835f3
ZN		 1812 wait_event(ring->irq_queue,
1813 i915_seqno_passed(
1814 ring->get_gem_seqno(dev, ring), seqno)
1815 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1816
8187a2b7 1817 ring->user_irq_put(dev, ring);
852835f3 1818 ring->waiting_gem_seqno = 0;
1c5d22f7
CW		 1819
1820 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1821 }
ba1234d1 1822 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1823 ret = -EIO;
1824
1825 if (ret && ret != -ERESTARTSYS)
1826 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
852835f3 1827 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
673a394b
EA		 1828
1829 /* Directly dispatch request retiring. While we have the work queue
1830 * to handle this, the waiter on a request often wants an associated
1831 * buffer to have made it to the inactive list, and we would need
1832 * a separate wait queue to handle that.
1833 */
1834 if (ret == 0)
852835f3 1835 i915_gem_retire_requests(dev, ring);
673a394b
EA		 1836
1837 return ret;
1838}
1839
48764bf4
DV		 1840/**
1841 * Waits for a sequence number to be signaled, and cleans up the
1842 * request and object lists appropriately for that event.
1843 */
1844static int
852835f3
ZN		 1845i915_wait_request(struct drm_device *dev, uint32_t seqno,
1846 struct intel_ring_buffer *ring)
48764bf4 1847{
852835f3 1848 return i915_do_wait_request(dev, seqno, 1, ring);
48764bf4
DV		 1849}
1850
8187a2b7
ZN		 1851static void
1852i915_gem_flush(struct drm_device *dev,
1853 uint32_t invalidate_domains,
1854 uint32_t flush_domains)
1855{
1856 drm_i915_private_t *dev_priv = dev->dev_private;
1857 if (flush_domains & I915_GEM_DOMAIN_CPU)
1858 drm_agp_chipset_flush(dev);
1859 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1860 invalidate_domains,
1861 flush_domains);
d1b851fc
ZN		 1862
1863 if (HAS_BSD(dev))
1864 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1865 invalidate_domains,
1866 flush_domains);
8187a2b7
ZN		 1867}
1868
852835f3
ZN		 1869static void
1870i915_gem_flush_ring(struct drm_device *dev,
1871 uint32_t invalidate_domains,
1872 uint32_t flush_domains,
1873 struct intel_ring_buffer *ring)
1874{
1875 if (flush_domains & I915_GEM_DOMAIN_CPU)
1876 drm_agp_chipset_flush(dev);
1877 ring->flush(dev, ring,
1878 invalidate_domains,
1879 flush_domains);
1880}
1881
673a394b
EA		 1882/**
1883 * Ensures that all rendering to the object has completed and the object is
1884 * safe to unbind from the GTT or access from the CPU.
1885 */
1886static int
1887i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1888{
1889 struct drm_device *dev = obj->dev;
23010e43 1890 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1891 int ret;
1892
e47c68e9
EA		 1893 /* This function only exists to support waiting for existing rendering,
1894 * not for emitting required flushes.
673a394b 1895 */
e47c68e9 1896 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1897
1898 /* If there is rendering queued on the buffer being evicted, wait for
1899 * it.
1900 */
1901 if (obj_priv->active) {
1902#if WATCH_BUF
1903 DRM_INFO("%s: object %p wait for seqno %08x\n",
1904 __func__, obj, obj_priv->last_rendering_seqno);
1905#endif
852835f3
ZN		 1906 ret = i915_wait_request(dev,
1907 obj_priv->last_rendering_seqno, obj_priv->ring);
673a394b
EA		 1908 if (ret != 0)
1909 return ret;
1910 }
1911
1912 return 0;
1913}
1914
1915/**
1916 * Unbinds an object from the GTT aperture.
1917 */
0f973f27 1918int
673a394b
EA		 1919i915_gem_object_unbind(struct drm_gem_object *obj)
1920{
1921 struct drm_device *dev = obj->dev;
4a87b8ca 1922 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1923 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1924 int ret = 0;
1925
1926#if WATCH_BUF
1927 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1928 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1929#endif
1930 if (obj_priv->gtt_space == NULL)
1931 return 0;
1932
1933 if (obj_priv->pin_count != 0) {
1934 DRM_ERROR("Attempting to unbind pinned buffer\n");
1935 return -EINVAL;
1936 }
1937
5323fd04
EA		 1938 /* blow away mappings if mapped through GTT */
1939 i915_gem_release_mmap(obj);
1940
673a394b
EA		 1941 /* Move the object to the CPU domain to ensure that
1942 * any possible CPU writes while it's not in the GTT
1943 * are flushed when we go to remap it. This will
1944 * also ensure that all pending GPU writes are finished
1945 * before we unbind.
1946 */
e47c68e9 1947 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 1948 if (ret) {
e47c68e9
EA		 1949 if (ret != -ERESTARTSYS)
1950 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 1951 return ret;
1952 }
1953
5323fd04
EA		 1954 BUG_ON(obj_priv->active);
1955
96b47b65
DV		 1956 /* release the fence reg _after_ flushing */
1957 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1958 i915_gem_clear_fence_reg(obj);
1959
673a394b
EA		 1960 if (obj_priv->agp_mem != NULL) {
1961 drm_unbind_agp(obj_priv->agp_mem);
1962 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1963 obj_priv->agp_mem = NULL;
1964 }
1965
856fa198 1966 i915_gem_object_put_pages(obj);
a32808c0 1967 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 1968
1969 if (obj_priv->gtt_space) {
1970 atomic_dec(&dev->gtt_count);
1971 atomic_sub(obj->size, &dev->gtt_memory);
1972
1973 drm_mm_put_block(obj_priv->gtt_space);
1974 obj_priv->gtt_space = NULL;
1975 }
1976
1977 /* Remove ourselves from the LRU list if present. */
4a87b8ca 1978 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1979 if (!list_empty(&obj_priv->list))
1980 list_del_init(&obj_priv->list);
4a87b8ca 1981 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 1982
963b4836
CW		 1983 if (i915_gem_object_is_purgeable(obj_priv))
1984 i915_gem_object_truncate(obj);
1985
1c5d22f7
CW		 1986 trace_i915_gem_object_unbind(obj);
1987
673a394b
EA		 1988 return 0;
1989}
1990
07f73f69
CW		 1991static struct drm_gem_object *
1992i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
1993{
1994 drm_i915_private_t *dev_priv = dev->dev_private;
1995 struct drm_i915_gem_object *obj_priv;
1996 struct drm_gem_object *best = NULL;
1997 struct drm_gem_object *first = NULL;
1998
1999 /* Try to find the smallest clean object */
2000 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
a8089e84 2001 struct drm_gem_object *obj = &obj_priv->base;
07f73f69 2002 if (obj->size >= min_size) {
963b4836
CW		 2003 if ((!obj_priv->dirty ||
2004 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2005 (!best || obj->size < best->size)) {
2006 best = obj;
2007 if (best->size == min_size)
2008 return best;
2009 }
2010 if (!first)
2011 first = obj;
2012 }
2013 }
2014
2015 return best ? best : first;
2016}
2017
4df2faf4
DV		 2018static int
2019i915_gpu_idle(struct drm_device *dev)
2020{
2021 drm_i915_private_t *dev_priv = dev->dev_private;
2022 bool lists_empty;
d1b851fc 2023 uint32_t seqno1, seqno2;
852835f3 2024 int ret;
4df2faf4
DV		 2025
2026 spin_lock(&dev_priv->mm.active_list_lock);
d1b851fc
ZN		 2027 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2028 list_empty(&dev_priv->render_ring.active_list) &&
2029 (!HAS_BSD(dev) ||
2030 list_empty(&dev_priv->bsd_ring.active_list)));
4df2faf4
DV		 2031 spin_unlock(&dev_priv->mm.active_list_lock);
2032
2033 if (lists_empty)
2034 return 0;
2035
2036 /* Flush everything onto the inactive list. */
2037 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
d1b851fc 2038 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
852835f3 2039 &dev_priv->render_ring);
d1b851fc 2040 if (seqno1 == 0)
4df2faf4 2041 return -ENOMEM;
d1b851fc
ZN		 2042 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2043
2044 if (HAS_BSD(dev)) {
2045 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2046 &dev_priv->bsd_ring);
2047 if (seqno2 == 0)
2048 return -ENOMEM;
2049
2050 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2051 if (ret)
2052 return ret;
2053 }
2054
4df2faf4 2055
852835f3 2056 return ret;
4df2faf4
DV		 2057}
2058
673a394b 2059static int
07f73f69
CW		 2060i915_gem_evict_everything(struct drm_device *dev)
2061{
2062 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69
CW		 2063 int ret;
2064 bool lists_empty;
2065
07f73f69
CW		 2066 spin_lock(&dev_priv->mm.active_list_lock);
2067 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2068 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2069 list_empty(&dev_priv->render_ring.active_list) &&
2070 (!HAS_BSD(dev)
2071 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2072 spin_unlock(&dev_priv->mm.active_list_lock);
2073
9731129c 2074 if (lists_empty)
07f73f69 2075 return -ENOSPC;
07f73f69
CW		 2076
2077 /* Flush everything (on to the inactive lists) and evict */
4df2faf4 2078 ret = i915_gpu_idle(dev);
07f73f69
CW		 2079 if (ret)
2080 return ret;
2081
99fcb766
DV		 2082 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2083
ab5ee576 2084 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2085 if (ret)
2086 return ret;
2087
2088 spin_lock(&dev_priv->mm.active_list_lock);
2089 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2091 list_empty(&dev_priv->render_ring.active_list) &&
2092 (!HAS_BSD(dev)
2093 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2094 spin_unlock(&dev_priv->mm.active_list_lock);
2095 BUG_ON(!lists_empty);
2096
2097 return 0;
2098}
2099
673a394b 2100static int
07f73f69 2101i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2102{
2103 drm_i915_private_t *dev_priv = dev->dev_private;
2104 struct drm_gem_object *obj;
07f73f69 2105 int ret;
673a394b 2106
852835f3 2107 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
d1b851fc 2108 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
673a394b 2109 for (;;) {
852835f3 2110 i915_gem_retire_requests(dev, render_ring);
07f73f69 2111
d1b851fc
ZN		 2112 if (HAS_BSD(dev))
2113 i915_gem_retire_requests(dev, bsd_ring);
2114
673a394b
EA		 2115 /* If there's an inactive buffer available now, grab it
2116 * and be done.
2117 */
07f73f69
CW		 2118 obj = i915_gem_find_inactive_object(dev, min_size);
2119 if (obj) {
2120 struct drm_i915_gem_object *obj_priv;
2121
673a394b
EA		 2122#if WATCH_LRU
2123 DRM_INFO("%s: evicting %p\n", __func__, obj);
2124#endif
23010e43 2125 obj_priv = to_intel_bo(obj);
07f73f69 2126 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2127 BUG_ON(obj_priv->active);
2128
2129 /* Wait on the rendering and unbind the buffer. */
07f73f69 2130 return i915_gem_object_unbind(obj);
673a394b
EA		 2131 }
2132
2133 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2134 * things, wait for the next to finish and hopefully leave us
2135 * a buffer to evict.
673a394b 2136 */
852835f3 2137 if (!list_empty(&render_ring->request_list)) {
673a394b
EA		 2138 struct drm_i915_gem_request *request;
2139
852835f3 2140 request = list_first_entry(&render_ring->request_list,
673a394b
EA		 2141 struct drm_i915_gem_request,
2142 list);
2143
852835f3
ZN		 2144 ret = i915_wait_request(dev,
2145 request->seqno, request->ring);
673a394b 2146 if (ret)
07f73f69 2147 return ret;
673a394b 2148
07f73f69 2149 continue;
673a394b
EA		 2150 }
2151
d1b851fc
ZN		 2152 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2153 struct drm_i915_gem_request *request;
2154
2155 request = list_first_entry(&bsd_ring->request_list,
2156 struct drm_i915_gem_request,
2157 list);
2158
2159 ret = i915_wait_request(dev,
2160 request->seqno, request->ring);
2161 if (ret)
2162 return ret;
2163
2164 continue;
2165 }
2166
673a394b
EA		 2167 /* If we didn't have anything on the request list but there
2168 * are buffers awaiting a flush, emit one and try again.
2169 * When we wait on it, those buffers waiting for that flush
2170 * will get moved to inactive.
2171 */
2172 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2173 struct drm_i915_gem_object *obj_priv;
673a394b 2174
9a1e2582
CW		 2175 /* Find an object that we can immediately reuse */
2176 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
a8089e84 2177 obj = &obj_priv->base;
9a1e2582
CW		 2178 if (obj->size >= min_size)
2179 break;
673a394b 2180
9a1e2582
CW		 2181 obj = NULL;
2182 }
673a394b 2183
9a1e2582
CW		 2184 if (obj != NULL) {
2185 uint32_t seqno;
673a394b 2186
852835f3
ZN		 2187 i915_gem_flush_ring(dev,
2188 obj->write_domain,
9a1e2582 2189 obj->write_domain,
852835f3
ZN		 2190 obj_priv->ring);
2191 seqno = i915_add_request(dev, NULL,
2192 obj->write_domain,
2193 obj_priv->ring);
9a1e2582
CW		 2194 if (seqno == 0)
2195 return -ENOMEM;
9a1e2582
CW		 2196 continue;
2197 }
673a394b
EA		 2198 }
2199
07f73f69
CW		 2200 /* If we didn't do any of the above, there's no single buffer
2201 * large enough to swap out for the new one, so just evict
2202 * everything and start again. (This should be rare.)
673a394b 2203 */
9731129c 2204 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2205 return i915_gem_evict_from_inactive_list(dev);
9731129c 2206 else
07f73f69 2207 return i915_gem_evict_everything(dev);
ac94a962 2208 }
ac94a962
KP		 2209}
2210
6911a9b8 2211int
4bdadb97
CW		 2212i915_gem_object_get_pages(struct drm_gem_object *obj,
2213 gfp_t gfpmask)
673a394b 2214{
23010e43 2215 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2216 int page_count, i;
2217 struct address_space *mapping;
2218 struct inode *inode;
2219 struct page *page;
673a394b 2220
778c3544
DV		 2221 BUG_ON(obj_priv->pages_refcount
2222 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2223
856fa198 2224 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2225 return 0;
2226
2227 /* Get the list of pages out of our struct file. They'll be pinned
2228 * at this point until we release them.
2229 */
2230 page_count = obj->size / PAGE_SIZE;
856fa198 2231 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2232 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2233 if (obj_priv->pages == NULL) {
856fa198 2234 obj_priv->pages_refcount--;
673a394b
EA		 2235 return -ENOMEM;
2236 }
2237
2238 inode = obj->filp->f_path.dentry->d_inode;
2239 mapping = inode->i_mapping;
2240 for (i = 0; i < page_count; i++) {
4bdadb97 2241 page = read_cache_page_gfp(mapping, i,
985b823b 2242 GFP_HIGHUSER |
4bdadb97 2243 __GFP_COLD |
cd9f040d 2244 __GFP_RECLAIMABLE |
4bdadb97 2245 gfpmask);
1f2b1013
CW		 2246 if (IS_ERR(page))
2247 goto err_pages;
2248
856fa198 2249 obj_priv->pages[i] = page;
673a394b 2250 }
280b713b
EA		 2251
2252 if (obj_priv->tiling_mode != I915_TILING_NONE)
2253 i915_gem_object_do_bit_17_swizzle(obj);
2254
673a394b 2255 return 0;
1f2b1013
CW		 2256
2257err_pages:
2258 while (i--)
2259 page_cache_release(obj_priv->pages[i]);
2260
2261 drm_free_large(obj_priv->pages);
2262 obj_priv->pages = NULL;
2263 obj_priv->pages_refcount--;
2264 return PTR_ERR(page);
673a394b
EA		 2265}
2266
4e901fdc
EA		 2267static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2268{
2269 struct drm_gem_object *obj = reg->obj;
2270 struct drm_device *dev = obj->dev;
2271 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2272 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2273 int regnum = obj_priv->fence_reg;
2274 uint64_t val;
2275
2276 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2277 0xfffff000) << 32;
2278 val |= obj_priv->gtt_offset & 0xfffff000;
2279 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2280 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2281
2282 if (obj_priv->tiling_mode == I915_TILING_Y)
2283 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2284 val |= I965_FENCE_REG_VALID;
2285
2286 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2287}
2288
de151cf6
JB		 2289static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2290{
2291 struct drm_gem_object *obj = reg->obj;
2292 struct drm_device *dev = obj->dev;
2293 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2294 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2295 int regnum = obj_priv->fence_reg;
2296 uint64_t val;
2297
2298 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2299 0xfffff000) << 32;
2300 val |= obj_priv->gtt_offset & 0xfffff000;
2301 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2302 if (obj_priv->tiling_mode == I915_TILING_Y)
2303 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2304 val |= I965_FENCE_REG_VALID;
2305
2306 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2307}
2308
2309static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2310{
2311 struct drm_gem_object *obj = reg->obj;
2312 struct drm_device *dev = obj->dev;
2313 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2314 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2315 int regnum = obj_priv->fence_reg;
0f973f27 2316 int tile_width;
dc529a4f 2317 uint32_t fence_reg, val;
de151cf6
JB		 2318 uint32_t pitch_val;
2319
2320 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2321 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2322 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2323 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2324 return;
2325 }
2326
0f973f27
JB		 2327 if (obj_priv->tiling_mode == I915_TILING_Y &&
2328 HAS_128_BYTE_Y_TILING(dev))
2329 tile_width = 128;
de151cf6 2330 else
0f973f27
JB		 2331 tile_width = 512;
2332
2333 /* Note: pitch better be a power of two tile widths */
2334 pitch_val = obj_priv->stride / tile_width;
2335 pitch_val = ffs(pitch_val) - 1;
de151cf6 2336
c36a2a6d
DV		 2337 if (obj_priv->tiling_mode == I915_TILING_Y &&
2338 HAS_128_BYTE_Y_TILING(dev))
2339 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2340 else
2341 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2342
de151cf6
JB		 2343 val = obj_priv->gtt_offset;
2344 if (obj_priv->tiling_mode == I915_TILING_Y)
2345 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2346 val |= I915_FENCE_SIZE_BITS(obj->size);
2347 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2348 val |= I830_FENCE_REG_VALID;
2349
dc529a4f
EA		 2350 if (regnum < 8)
2351 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2352 else
2353 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2354 I915_WRITE(fence_reg, val);
de151cf6
JB		 2355}
2356
2357static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2358{
2359 struct drm_gem_object *obj = reg->obj;
2360 struct drm_device *dev = obj->dev;
2361 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2362 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2363 int regnum = obj_priv->fence_reg;
2364 uint32_t val;
2365 uint32_t pitch_val;
8d7773a3 2366 uint32_t fence_size_bits;
de151cf6 2367
8d7773a3 2368 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2369 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2370 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2371 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2372 return;
2373 }
2374
e76a16de
EA		 2375 pitch_val = obj_priv->stride / 128;
2376 pitch_val = ffs(pitch_val) - 1;
2377 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2378
de151cf6
JB		 2379 val = obj_priv->gtt_offset;
2380 if (obj_priv->tiling_mode == I915_TILING_Y)
2381 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2382 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2383 WARN_ON(fence_size_bits & ~0x00000f00);
2384 val |= fence_size_bits;
de151cf6
JB		 2385 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2386 val |= I830_FENCE_REG_VALID;
2387
2388 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2389}
2390
ae3db24a
DV		 2391static int i915_find_fence_reg(struct drm_device *dev)
2392{
2393 struct drm_i915_fence_reg *reg = NULL;
2394 struct drm_i915_gem_object *obj_priv = NULL;
2395 struct drm_i915_private *dev_priv = dev->dev_private;
2396 struct drm_gem_object *obj = NULL;
2397 int i, avail, ret;
2398
2399 /* First try to find a free reg */
2400 avail = 0;
2401 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2402 reg = &dev_priv->fence_regs[i];
2403 if (!reg->obj)
2404 return i;
2405
23010e43 2406 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2407 if (!obj_priv->pin_count)
2408 avail++;
2409 }
2410
2411 if (avail == 0)
2412 return -ENOSPC;
2413
2414 /* None available, try to steal one or wait for a user to finish */
2415 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2416 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2417 lru_list) {
2418 obj = reg->obj;
2419 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2420
2421 if (obj_priv->pin_count)
2422 continue;
2423
2424 /* found one! */
2425 i = obj_priv->fence_reg;
2426 break;
2427 }
2428
2429 BUG_ON(i == I915_FENCE_REG_NONE);
2430
2431 /* We only have a reference on obj from the active list. put_fence_reg
2432 * might drop that one, causing a use-after-free in it. So hold a
2433 * private reference to obj like the other callers of put_fence_reg
2434 * (set_tiling ioctl) do. */
2435 drm_gem_object_reference(obj);
2436 ret = i915_gem_object_put_fence_reg(obj);
2437 drm_gem_object_unreference(obj);
2438 if (ret != 0)
2439 return ret;
2440
2441 return i;
2442}
2443
de151cf6
JB		 2444/**
2445 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2446 * @obj: object to map through a fence reg
2447 *
2448 * When mapping objects through the GTT, userspace wants to be able to write
2449 * to them without having to worry about swizzling if the object is tiled.
2450 *
2451 * This function walks the fence regs looking for a free one for @obj,
2452 * stealing one if it can't find any.
2453 *
2454 * It then sets up the reg based on the object's properties: address, pitch
2455 * and tiling format.
2456 */
8c4b8c3f
CW		 2457int
2458i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2459{
2460 struct drm_device *dev = obj->dev;
79e53945 2461 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2462 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2463 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2464 int ret;
de151cf6 2465
a09ba7fa
EA		 2466 /* Just update our place in the LRU if our fence is getting used. */
2467 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2468 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2469 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2470 return 0;
2471 }
2472
de151cf6
JB		 2473 switch (obj_priv->tiling_mode) {
2474 case I915_TILING_NONE:
2475 WARN(1, "allocating a fence for non-tiled object?\n");
2476 break;
2477 case I915_TILING_X:
0f973f27
JB		 2478 if (!obj_priv->stride)
2479 return -EINVAL;
2480 WARN((obj_priv->stride & (512 - 1)),
2481 "object 0x%08x is X tiled but has non-512B pitch\n",
2482 obj_priv->gtt_offset);
de151cf6
JB		 2483 break;
2484 case I915_TILING_Y:
0f973f27
JB		 2485 if (!obj_priv->stride)
2486 return -EINVAL;
2487 WARN((obj_priv->stride & (128 - 1)),
2488 "object 0x%08x is Y tiled but has non-128B pitch\n",
2489 obj_priv->gtt_offset);
de151cf6
JB		 2490 break;
2491 }
2492
ae3db24a
DV		 2493 ret = i915_find_fence_reg(dev);
2494 if (ret < 0)
2495 return ret;
de151cf6 2496
ae3db24a
DV		 2497 obj_priv->fence_reg = ret;
2498 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2499 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2500
de151cf6
JB		 2501 reg->obj = obj;
2502
4e901fdc
EA		 2503 if (IS_GEN6(dev))
2504 sandybridge_write_fence_reg(reg);
2505 else if (IS_I965G(dev))
de151cf6
JB		 2506 i965_write_fence_reg(reg);
2507 else if (IS_I9XX(dev))
2508 i915_write_fence_reg(reg);
2509 else
2510 i830_write_fence_reg(reg);
d9ddcb96 2511
ae3db24a
DV		 2512 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2513 obj_priv->tiling_mode);
1c5d22f7 2514
d9ddcb96 2515 return 0;
de151cf6
JB		 2516}
2517
2518/**
2519 * i915_gem_clear_fence_reg - clear out fence register info
2520 * @obj: object to clear
2521 *
2522 * Zeroes out the fence register itself and clears out the associated
2523 * data structures in dev_priv and obj_priv.
2524 */
2525static void
2526i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2527{
2528 struct drm_device *dev = obj->dev;
79e53945 2529 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2530 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2531 struct drm_i915_fence_reg *reg =
2532 &dev_priv->fence_regs[obj_priv->fence_reg];
de151cf6 2533
4e901fdc
EA		 2534 if (IS_GEN6(dev)) {
2535 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2536 (obj_priv->fence_reg * 8), 0);
2537 } else if (IS_I965G(dev)) {
de151cf6 2538 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2539 } else {
dc529a4f
EA		 2540 uint32_t fence_reg;
2541
2542 if (obj_priv->fence_reg < 8)
2543 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2544 else
2545 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2546 8) * 4;
2547
2548 I915_WRITE(fence_reg, 0);
2549 }
de151cf6 2550
007cc8ac 2551 reg->obj = NULL;
de151cf6 2552 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2553 list_del_init(&reg->lru_list);
de151cf6
JB		 2554}
2555
52dc7d32
CW		 2556/**
2557 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2558 * to the buffer to finish, and then resets the fence register.
2559 * @obj: tiled object holding a fence register.
2560 *
2561 * Zeroes out the fence register itself and clears out the associated
2562 * data structures in dev_priv and obj_priv.
2563 */
2564int
2565i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2566{
2567 struct drm_device *dev = obj->dev;
23010e43 2568 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2569
2570 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2571 return 0;
2572
10ae9bd2
DV		 2573 /* If we've changed tiling, GTT-mappings of the object
2574 * need to re-fault to ensure that the correct fence register
2575 * setup is in place.
2576 */
2577 i915_gem_release_mmap(obj);
2578
52dc7d32
CW		 2579 /* On the i915, GPU access to tiled buffers is via a fence,
2580 * therefore we must wait for any outstanding access to complete
2581 * before clearing the fence.
2582 */
2583 if (!IS_I965G(dev)) {
2584 int ret;
2585
2586 i915_gem_object_flush_gpu_write_domain(obj);
52dc7d32
CW		 2587 ret = i915_gem_object_wait_rendering(obj);
2588 if (ret != 0)
2589 return ret;
2590 }
2591
4a726612 2592 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2593 i915_gem_clear_fence_reg (obj);
2594
2595 return 0;
2596}
2597
673a394b
EA		 2598/**
2599 * Finds free space in the GTT aperture and binds the object there.
2600 */
2601static int
2602i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2603{
2604 struct drm_device *dev = obj->dev;
2605 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2606 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2607 struct drm_mm_node *free_space;
4bdadb97 2608 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2609 int ret;
673a394b 2610
bb6baf76 2611 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2612 DRM_ERROR("Attempting to bind a purgeable object\n");
2613 return -EINVAL;
2614 }
2615
673a394b 2616 if (alignment == 0)
0f973f27 2617 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2618 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2619 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2620 return -EINVAL;
2621 }
2622
654fc607
CW		 2623 /* If the object is bigger than the entire aperture, reject it early
2624 * before evicting everything in a vain attempt to find space.
2625 */
2626 if (obj->size > dev->gtt_total) {
2627 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2628 return -E2BIG;
2629 }
2630
673a394b
EA		 2631 search_free:
2632 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2633 obj->size, alignment, 0);
2634 if (free_space != NULL) {
2635 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2636 alignment);
db3307a9 2637 if (obj_priv->gtt_space != NULL)
673a394b 2638 obj_priv->gtt_offset = obj_priv->gtt_space->start;
673a394b
EA		 2639 }
2640 if (obj_priv->gtt_space == NULL) {
2641 /* If the gtt is empty and we're still having trouble
2642 * fitting our object in, we're out of memory.
2643 */
2644#if WATCH_LRU
2645 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2646#endif
07f73f69 2647 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2648 if (ret)
673a394b 2649 return ret;
9731129c 2650
673a394b
EA		 2651 goto search_free;
2652 }
2653
2654#if WATCH_BUF
cfd43c02 2655 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2656 obj->size, obj_priv->gtt_offset);
2657#endif
4bdadb97 2658 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2659 if (ret) {
2660 drm_mm_put_block(obj_priv->gtt_space);
2661 obj_priv->gtt_space = NULL;
07f73f69
CW		 2662
2663 if (ret == -ENOMEM) {
2664 /* first try to clear up some space from the GTT */
2665 ret = i915_gem_evict_something(dev, obj->size);
2666 if (ret) {
07f73f69 2667 /* now try to shrink everyone else */
4bdadb97
CW		 2668 if (gfpmask) {
2669 gfpmask = 0;
2670 goto search_free;
07f73f69
CW		 2671 }
2672
2673 return ret;
2674 }
2675
2676 goto search_free;
2677 }
2678
673a394b
EA		 2679 return ret;
2680 }
2681
673a394b
EA		 2682 /* Create an AGP memory structure pointing at our pages, and bind it
2683 * into the GTT.
2684 */
2685 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2686 obj_priv->pages,
07f73f69 2687 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2688 obj_priv->gtt_offset,
2689 obj_priv->agp_type);
673a394b 2690 if (obj_priv->agp_mem == NULL) {
856fa198 2691 i915_gem_object_put_pages(obj);
673a394b
EA		 2692 drm_mm_put_block(obj_priv->gtt_space);
2693 obj_priv->gtt_space = NULL;
07f73f69
CW		 2694
2695 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2696 if (ret)
07f73f69 2697 return ret;
07f73f69
CW		 2698
2699 goto search_free;
673a394b
EA		 2700 }
2701 atomic_inc(&dev->gtt_count);
2702 atomic_add(obj->size, &dev->gtt_memory);
2703
2704 /* Assert that the object is not currently in any GPU domain. As it
2705 * wasn't in the GTT, there shouldn't be any way it could have been in
2706 * a GPU cache
2707 */
21d509e3
CW		 2708 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2709 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2710
1c5d22f7
CW		 2711 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2712
673a394b
EA		 2713 return 0;
2714}
2715
2716void
2717i915_gem_clflush_object(struct drm_gem_object *obj)
2718{
23010e43 2719 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2720
2721 /* If we don't have a page list set up, then we're not pinned
2722 * to GPU, and we can ignore the cache flush because it'll happen
2723 * again at bind time.
2724 */
856fa198 2725 if (obj_priv->pages == NULL)
673a394b
EA		 2726 return;
2727
1c5d22f7 2728 trace_i915_gem_object_clflush(obj);
cfa16a0d 2729
856fa198 2730 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2731}
2732
e47c68e9
EA		 2733/** Flushes any GPU write domain for the object if it's dirty. */
2734static void
2735i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2736{
2737 struct drm_device *dev = obj->dev;
1c5d22f7 2738 uint32_t old_write_domain;
852835f3 2739 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
e47c68e9
EA		 2740
2741 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2742 return;
2743
2744 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2745 old_write_domain = obj->write_domain;
e47c68e9 2746 i915_gem_flush(dev, 0, obj->write_domain);
852835f3 2747 (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring);
99fcb766 2748 BUG_ON(obj->write_domain);
1c5d22f7
CW		 2749
2750 trace_i915_gem_object_change_domain(obj,
2751 obj->read_domains,
2752 old_write_domain);
e47c68e9
EA		 2753}
2754
2755/** Flushes the GTT write domain for the object if it's dirty. */
2756static void
2757i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2758{
1c5d22f7
CW		 2759 uint32_t old_write_domain;
2760
e47c68e9
EA		 2761 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2762 return;
2763
2764 /* No actual flushing is required for the GTT write domain. Writes
2765 * to it immediately go to main memory as far as we know, so there's
2766 * no chipset flush. It also doesn't land in render cache.
2767 */
1c5d22f7 2768 old_write_domain = obj->write_domain;
e47c68e9 2769 obj->write_domain = 0;
1c5d22f7
CW		 2770
2771 trace_i915_gem_object_change_domain(obj,
2772 obj->read_domains,
2773 old_write_domain);
e47c68e9
EA		 2774}
2775
2776/** Flushes the CPU write domain for the object if it's dirty. */
2777static void
2778i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2779{
2780 struct drm_device *dev = obj->dev;
1c5d22f7 2781 uint32_t old_write_domain;
e47c68e9
EA		 2782
2783 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2784 return;
2785
2786 i915_gem_clflush_object(obj);
2787 drm_agp_chipset_flush(dev);
1c5d22f7 2788 old_write_domain = obj->write_domain;
e47c68e9 2789 obj->write_domain = 0;
1c5d22f7
CW		 2790
2791 trace_i915_gem_object_change_domain(obj,
2792 obj->read_domains,
2793 old_write_domain);
e47c68e9
EA		 2794}
2795
6b95a207
KH		 2796void
2797i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2798{
2799 switch (obj->write_domain) {
2800 case I915_GEM_DOMAIN_GTT:
2801 i915_gem_object_flush_gtt_write_domain(obj);
2802 break;
2803 case I915_GEM_DOMAIN_CPU:
2804 i915_gem_object_flush_cpu_write_domain(obj);
2805 break;
2806 default:
2807 i915_gem_object_flush_gpu_write_domain(obj);
2808 break;
2809 }
2810}
2811
2ef7eeaa
EA		 2812/**
2813 * Moves a single object to the GTT read, and possibly write domain.
2814 *
2815 * This function returns when the move is complete, including waiting on
2816 * flushes to occur.
2817 */
79e53945 2818int
2ef7eeaa
EA		 2819i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2820{
23010e43 2821 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2822 uint32_t old_write_domain, old_read_domains;
e47c68e9 2823 int ret;
2ef7eeaa 2824
02354392
EA		 2825 /* Not valid to be called on unbound objects. */
2826 if (obj_priv->gtt_space == NULL)
2827 return -EINVAL;
2828
e47c68e9
EA		 2829 i915_gem_object_flush_gpu_write_domain(obj);
2830 /* Wait on any GPU rendering and flushing to occur. */
2831 ret = i915_gem_object_wait_rendering(obj);
2832 if (ret != 0)
2833 return ret;
2834
1c5d22f7
CW		 2835 old_write_domain = obj->write_domain;
2836 old_read_domains = obj->read_domains;
2837
e47c68e9
EA		 2838 /* If we're writing through the GTT domain, then CPU and GPU caches
2839 * will need to be invalidated at next use.
2ef7eeaa 2840 */
e47c68e9
EA		 2841 if (write)
2842 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2843
e47c68e9 2844 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2845
e47c68e9
EA		 2846 /* It should now be out of any other write domains, and we can update
2847 * the domain values for our changes.
2848 */
2849 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2850 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2851 if (write) {
2852 obj->write_domain = I915_GEM_DOMAIN_GTT;
2853 obj_priv->dirty = 1;
2ef7eeaa
EA		 2854 }
2855
1c5d22f7
CW		 2856 trace_i915_gem_object_change_domain(obj,
2857 old_read_domains,
2858 old_write_domain);
2859
e47c68e9
EA		 2860 return 0;
2861}
2862
b9241ea3
ZW		 2863/*
2864 * Prepare buffer for display plane. Use uninterruptible for possible flush
2865 * wait, as in modesetting process we're not supposed to be interrupted.
2866 */
2867int
2868i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2869{
2870 struct drm_device *dev = obj->dev;
23010e43 2871 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2872 uint32_t old_write_domain, old_read_domains;
2873 int ret;
2874
2875 /* Not valid to be called on unbound objects. */
2876 if (obj_priv->gtt_space == NULL)
2877 return -EINVAL;
2878
2879 i915_gem_object_flush_gpu_write_domain(obj);
2880
2881 /* Wait on any GPU rendering and flushing to occur. */
2882 if (obj_priv->active) {
2883#if WATCH_BUF
2884 DRM_INFO("%s: object %p wait for seqno %08x\n",
2885 __func__, obj, obj_priv->last_rendering_seqno);
2886#endif
852835f3
ZN		 2887 ret = i915_do_wait_request(dev,
2888 obj_priv->last_rendering_seqno,
2889 0,
2890 obj_priv->ring);
b9241ea3
ZW		 2891 if (ret != 0)
2892 return ret;
2893 }
2894
b118c1e3
CW		 2895 i915_gem_object_flush_cpu_write_domain(obj);
2896
b9241ea3
ZW		 2897 old_write_domain = obj->write_domain;
2898 old_read_domains = obj->read_domains;
2899
b9241ea3
ZW		 2900 /* It should now be out of any other write domains, and we can update
2901 * the domain values for our changes.
2902 */
2903 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
b118c1e3 2904 obj->read_domains = I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 2905 obj->write_domain = I915_GEM_DOMAIN_GTT;
2906 obj_priv->dirty = 1;
2907
2908 trace_i915_gem_object_change_domain(obj,
2909 old_read_domains,
2910 old_write_domain);
2911
2912 return 0;
2913}
2914
e47c68e9
EA		 2915/**
2916 * Moves a single object to the CPU read, and possibly write domain.
2917 *
2918 * This function returns when the move is complete, including waiting on
2919 * flushes to occur.
2920 */
2921static int
2922i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2923{
1c5d22f7 2924 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2925 int ret;
2926
2927 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2928 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2929 ret = i915_gem_object_wait_rendering(obj);
2930 if (ret != 0)
2931 return ret;
2ef7eeaa 2932
e47c68e9 2933 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2934
e47c68e9
EA		 2935 /* If we have a partially-valid cache of the object in the CPU,
2936 * finish invalidating it and free the per-page flags.
2ef7eeaa 2937 */
e47c68e9 2938 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2939
1c5d22f7
CW		 2940 old_write_domain = obj->write_domain;
2941 old_read_domains = obj->read_domains;
2942
e47c68e9
EA		 2943 /* Flush the CPU cache if it's still invalid. */
2944 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2945 i915_gem_clflush_object(obj);
2ef7eeaa 2946
e47c68e9 2947 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2948 }
2949
2950 /* It should now be out of any other write domains, and we can update
2951 * the domain values for our changes.
2952 */
e47c68e9
EA		 2953 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2954
2955 /* If we're writing through the CPU, then the GPU read domains will
2956 * need to be invalidated at next use.
2957 */
2958 if (write) {
2959 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2960 obj->write_domain = I915_GEM_DOMAIN_CPU;
2961 }
2ef7eeaa 2962
1c5d22f7
CW		 2963 trace_i915_gem_object_change_domain(obj,
2964 old_read_domains,
2965 old_write_domain);
2966
2ef7eeaa
EA		 2967 return 0;
2968}
2969
673a394b
EA		 2970/*
2971 * Set the next domain for the specified object. This
2972 * may not actually perform the necessary flushing/invaliding though,
2973 * as that may want to be batched with other set_domain operations
2974 *
2975 * This is (we hope) the only really tricky part of gem. The goal
2976 * is fairly simple -- track which caches hold bits of the object
2977 * and make sure they remain coherent. A few concrete examples may
2978 * help to explain how it works. For shorthand, we use the notation
2979 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2980 * a pair of read and write domain masks.
2981 *
2982 * Case 1: the batch buffer
2983 *
2984 * 1. Allocated
2985 * 2. Written by CPU
2986 * 3. Mapped to GTT
2987 * 4. Read by GPU
2988 * 5. Unmapped from GTT
2989 * 6. Freed
2990 *
2991 * Let's take these a step at a time
2992 *
2993 * 1. Allocated
2994 * Pages allocated from the kernel may still have
2995 * cache contents, so we set them to (CPU, CPU) always.
2996 * 2. Written by CPU (using pwrite)
2997 * The pwrite function calls set_domain (CPU, CPU) and
2998 * this function does nothing (as nothing changes)
2999 * 3. Mapped by GTT
3000 * This function asserts that the object is not
3001 * currently in any GPU-based read or write domains
3002 * 4. Read by GPU
3003 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3004 * As write_domain is zero, this function adds in the
3005 * current read domains (CPU+COMMAND, 0).
3006 * flush_domains is set to CPU.
3007 * invalidate_domains is set to COMMAND
3008 * clflush is run to get data out of the CPU caches
3009 * then i915_dev_set_domain calls i915_gem_flush to
3010 * emit an MI_FLUSH and drm_agp_chipset_flush
3011 * 5. Unmapped from GTT
3012 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3013 * flush_domains and invalidate_domains end up both zero
3014 * so no flushing/invalidating happens
3015 * 6. Freed
3016 * yay, done
3017 *
3018 * Case 2: The shared render buffer
3019 *
3020 * 1. Allocated
3021 * 2. Mapped to GTT
3022 * 3. Read/written by GPU
3023 * 4. set_domain to (CPU,CPU)
3024 * 5. Read/written by CPU
3025 * 6. Read/written by GPU
3026 *
3027 * 1. Allocated
3028 * Same as last example, (CPU, CPU)
3029 * 2. Mapped to GTT
3030 * Nothing changes (assertions find that it is not in the GPU)
3031 * 3. Read/written by GPU
3032 * execbuffer calls set_domain (RENDER, RENDER)
3033 * flush_domains gets CPU
3034 * invalidate_domains gets GPU
3035 * clflush (obj)
3036 * MI_FLUSH and drm_agp_chipset_flush
3037 * 4. set_domain (CPU, CPU)
3038 * flush_domains gets GPU
3039 * invalidate_domains gets CPU
3040 * wait_rendering (obj) to make sure all drawing is complete.
3041 * This will include an MI_FLUSH to get the data from GPU
3042 * to memory
3043 * clflush (obj) to invalidate the CPU cache
3044 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3045 * 5. Read/written by CPU
3046 * cache lines are loaded and dirtied
3047 * 6. Read written by GPU
3048 * Same as last GPU access
3049 *
3050 * Case 3: The constant buffer
3051 *
3052 * 1. Allocated
3053 * 2. Written by CPU
3054 * 3. Read by GPU
3055 * 4. Updated (written) by CPU again
3056 * 5. Read by GPU
3057 *
3058 * 1. Allocated
3059 * (CPU, CPU)
3060 * 2. Written by CPU
3061 * (CPU, CPU)
3062 * 3. Read by GPU
3063 * (CPU+RENDER, 0)
3064 * flush_domains = CPU
3065 * invalidate_domains = RENDER
3066 * clflush (obj)
3067 * MI_FLUSH
3068 * drm_agp_chipset_flush
3069 * 4. Updated (written) by CPU again
3070 * (CPU, CPU)
3071 * flush_domains = 0 (no previous write domain)
3072 * invalidate_domains = 0 (no new read domains)
3073 * 5. Read by GPU
3074 * (CPU+RENDER, 0)
3075 * flush_domains = CPU
3076 * invalidate_domains = RENDER
3077 * clflush (obj)
3078 * MI_FLUSH
3079 * drm_agp_chipset_flush
3080 */
c0d90829 3081static void
8b0e378a 3082i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3083{
3084 struct drm_device *dev = obj->dev;
23010e43 3085 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3086 uint32_t invalidate_domains = 0;
3087 uint32_t flush_domains = 0;
1c5d22f7 3088 uint32_t old_read_domains;
e47c68e9 3089
8b0e378a
EA		 3090 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3091 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3092
652c393a
JB		 3093 intel_mark_busy(dev, obj);
3094
673a394b
EA		 3095#if WATCH_BUF
3096 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3097 __func__, obj,
8b0e378a
EA		 3098 obj->read_domains, obj->pending_read_domains,
3099 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3100#endif
3101 /*
3102 * If the object isn't moving to a new write domain,
3103 * let the object stay in multiple read domains
3104 */
8b0e378a
EA		 3105 if (obj->pending_write_domain == 0)
3106 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3107 else
3108 obj_priv->dirty = 1;
3109
3110 /*
3111 * Flush the current write domain if
3112 * the new read domains don't match. Invalidate
3113 * any read domains which differ from the old
3114 * write domain
3115 */
8b0e378a
EA		 3116 if (obj->write_domain &&
3117 obj->write_domain != obj->pending_read_domains) {
673a394b 3118 flush_domains |= obj->write_domain;
8b0e378a
EA		 3119 invalidate_domains |=
3120 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3121 }
3122 /*
3123 * Invalidate any read caches which may have
3124 * stale data. That is, any new read domains.
3125 */
8b0e378a 3126 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3127 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3128#if WATCH_BUF
3129 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3130 __func__, flush_domains, invalidate_domains);
3131#endif
673a394b
EA		 3132 i915_gem_clflush_object(obj);
3133 }
3134
1c5d22f7
CW		 3135 old_read_domains = obj->read_domains;
3136
efbeed96
EA		 3137 /* The actual obj->write_domain will be updated with
3138 * pending_write_domain after we emit the accumulated flush for all
3139 * of our domain changes in execbuffers (which clears objects'
3140 * write_domains). So if we have a current write domain that we
3141 * aren't changing, set pending_write_domain to that.
3142 */
3143 if (flush_domains == 0 && obj->pending_write_domain == 0)
3144 obj->pending_write_domain = obj->write_domain;
8b0e378a 3145 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3146
3147 dev->invalidate_domains |= invalidate_domains;
3148 dev->flush_domains |= flush_domains;
3149#if WATCH_BUF
3150 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3151 __func__,
3152 obj->read_domains, obj->write_domain,
3153 dev->invalidate_domains, dev->flush_domains);
3154#endif
1c5d22f7
CW		 3155
3156 trace_i915_gem_object_change_domain(obj,
3157 old_read_domains,
3158 obj->write_domain);
673a394b
EA		 3159}
3160
3161/**
e47c68e9 3162 * Moves the object from a partially CPU read to a full one.
673a394b 3163 *
e47c68e9
EA		 3164 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3165 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3166 */
e47c68e9
EA		 3167static void
3168i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3169{
23010e43 3170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3171
e47c68e9
EA		 3172 if (!obj_priv->page_cpu_valid)
3173 return;
3174
3175 /* If we're partially in the CPU read domain, finish moving it in.
3176 */
3177 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3178 int i;
3179
3180 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3181 if (obj_priv->page_cpu_valid[i])
3182 continue;
856fa198 3183 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3184 }
e47c68e9
EA		 3185 }
3186
3187 /* Free the page_cpu_valid mappings which are now stale, whether
3188 * or not we've got I915_GEM_DOMAIN_CPU.
3189 */
9a298b2a 3190 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3191 obj_priv->page_cpu_valid = NULL;
3192}
3193
3194/**
3195 * Set the CPU read domain on a range of the object.
3196 *
3197 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3198 * not entirely valid. The page_cpu_valid member of the object flags which
3199 * pages have been flushed, and will be respected by
3200 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3201 * of the whole object.
3202 *
3203 * This function returns when the move is complete, including waiting on
3204 * flushes to occur.
3205 */
3206static int
3207i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3208 uint64_t offset, uint64_t size)
3209{
23010e43 3210 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3211 uint32_t old_read_domains;
e47c68e9 3212 int i, ret;
673a394b 3213
e47c68e9
EA		 3214 if (offset == 0 && size == obj->size)
3215 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3216
e47c68e9
EA		 3217 i915_gem_object_flush_gpu_write_domain(obj);
3218 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3219 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3220 if (ret != 0)
6a47baa6 3221 return ret;
e47c68e9
EA		 3222 i915_gem_object_flush_gtt_write_domain(obj);
3223
3224 /* If we're already fully in the CPU read domain, we're done. */
3225 if (obj_priv->page_cpu_valid == NULL &&
3226 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3227 return 0;
673a394b 3228
e47c68e9
EA		 3229 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3230 * newly adding I915_GEM_DOMAIN_CPU
3231 */
673a394b 3232 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3233 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3234 GFP_KERNEL);
e47c68e9
EA		 3235 if (obj_priv->page_cpu_valid == NULL)
3236 return -ENOMEM;
3237 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3238 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3239
3240 /* Flush the cache on any pages that are still invalid from the CPU's
3241 * perspective.
3242 */
e47c68e9
EA		 3243 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3244 i++) {
673a394b
EA		 3245 if (obj_priv->page_cpu_valid[i])
3246 continue;
3247
856fa198 3248 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3249
3250 obj_priv->page_cpu_valid[i] = 1;
3251 }
3252
e47c68e9
EA		 3253 /* It should now be out of any other write domains, and we can update
3254 * the domain values for our changes.
3255 */
3256 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3257
1c5d22f7 3258 old_read_domains = obj->read_domains;
e47c68e9
EA		 3259 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3260
1c5d22f7
CW		 3261 trace_i915_gem_object_change_domain(obj,
3262 old_read_domains,
3263 obj->write_domain);
3264
673a394b
EA		 3265 return 0;
3266}
3267
673a394b
EA		 3268/**
3269 * Pin an object to the GTT and evaluate the relocations landing in it.
3270 */
3271static int
3272i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3273 struct drm_file *file_priv,
76446cac 3274 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3275 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3276{
3277 struct drm_device *dev = obj->dev;
0839ccb8 3278 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3279 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3280 int i, ret;
0839ccb8 3281 void __iomem *reloc_page;
76446cac
JB		 3282 bool need_fence;
3283
3284 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3285 obj_priv->tiling_mode != I915_TILING_NONE;
3286
3287 /* Check fence reg constraints and rebind if necessary */
808b24d6
CW		 3288 if (need_fence &&
3289 !i915_gem_object_fence_offset_ok(obj,
3290 obj_priv->tiling_mode)) {
3291 ret = i915_gem_object_unbind(obj);
3292 if (ret)
3293 return ret;
3294 }
673a394b
EA		 3295
3296 /* Choose the GTT offset for our buffer and put it there. */
3297 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3298 if (ret)
3299 return ret;
3300
76446cac
JB		 3301 /*
3302 * Pre-965 chips need a fence register set up in order to
3303 * properly handle blits to/from tiled surfaces.
3304 */
3305 if (need_fence) {
3306 ret = i915_gem_object_get_fence_reg(obj);
3307 if (ret != 0) {
76446cac
JB		 3308 i915_gem_object_unpin(obj);
3309 return ret;
3310 }
3311 }
3312
673a394b
EA		 3313 entry->offset = obj_priv->gtt_offset;
3314
673a394b
EA		 3315 /* Apply the relocations, using the GTT aperture to avoid cache
3316 * flushing requirements.
3317 */
3318 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3319 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3320 struct drm_gem_object *target_obj;
3321 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3322 uint32_t reloc_val, reloc_offset;
3323 uint32_t __iomem *reloc_entry;
673a394b 3324
673a394b 3325 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3326 reloc->target_handle);
673a394b
EA		 3327 if (target_obj == NULL) {
3328 i915_gem_object_unpin(obj);
3329 return -EBADF;
3330 }
23010e43 3331 target_obj_priv = to_intel_bo(target_obj);
673a394b 3332
8542a0bb
CW		 3333#if WATCH_RELOC
3334 DRM_INFO("%s: obj %p offset %08x target %d "
3335 "read %08x write %08x gtt %08x "
3336 "presumed %08x delta %08x\n",
3337 __func__,
3338 obj,
3339 (int) reloc->offset,
3340 (int) reloc->target_handle,
3341 (int) reloc->read_domains,
3342 (int) reloc->write_domain,
3343 (int) target_obj_priv->gtt_offset,
3344 (int) reloc->presumed_offset,
3345 reloc->delta);
3346#endif
3347
673a394b
EA		 3348 /* The target buffer should have appeared before us in the
3349 * exec_object list, so it should have a GTT space bound by now.
3350 */
3351 if (target_obj_priv->gtt_space == NULL) {
3352 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3353 reloc->target_handle);
673a394b
EA		 3354 drm_gem_object_unreference(target_obj);
3355 i915_gem_object_unpin(obj);
3356 return -EINVAL;
3357 }
3358
8542a0bb 3359 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3360 if (reloc->write_domain & (reloc->write_domain - 1)) {
3361 DRM_ERROR("reloc with multiple write domains: "
3362 "obj %p target %d offset %d "
3363 "read %08x write %08x",
3364 obj, reloc->target_handle,
3365 (int) reloc->offset,
3366 reloc->read_domains,
3367 reloc->write_domain);
3368 return -EINVAL;
3369 }
40a5f0de
EA		 3370 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3371 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3372 DRM_ERROR("reloc with read/write CPU domains: "
3373 "obj %p target %d offset %d "
3374 "read %08x write %08x",
40a5f0de
EA		 3375 obj, reloc->target_handle,
3376 (int) reloc->offset,
3377 reloc->read_domains,
3378 reloc->write_domain);
491152b8
CW		 3379 drm_gem_object_unreference(target_obj);
3380 i915_gem_object_unpin(obj);
e47c68e9
EA		 3381 return -EINVAL;
3382 }
40a5f0de
EA		 3383 if (reloc->write_domain && target_obj->pending_write_domain &&
3384 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3385 DRM_ERROR("Write domain conflict: "
3386 "obj %p target %d offset %d "
3387 "new %08x old %08x\n",
40a5f0de
EA		 3388 obj, reloc->target_handle,
3389 (int) reloc->offset,
3390 reloc->write_domain,
673a394b
EA		 3391 target_obj->pending_write_domain);
3392 drm_gem_object_unreference(target_obj);
3393 i915_gem_object_unpin(obj);
3394 return -EINVAL;
3395 }
3396
40a5f0de
EA		 3397 target_obj->pending_read_domains |= reloc->read_domains;
3398 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3399
3400 /* If the relocation already has the right value in it, no
3401 * more work needs to be done.
3402 */
40a5f0de 3403 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3404 drm_gem_object_unreference(target_obj);
3405 continue;
3406 }
3407
8542a0bb
CW		 3408 /* Check that the relocation address is valid... */
3409 if (reloc->offset > obj->size - 4) {
3410 DRM_ERROR("Relocation beyond object bounds: "
3411 "obj %p target %d offset %d size %d.\n",
3412 obj, reloc->target_handle,
3413 (int) reloc->offset, (int) obj->size);
3414 drm_gem_object_unreference(target_obj);
3415 i915_gem_object_unpin(obj);
3416 return -EINVAL;
3417 }
3418 if (reloc->offset & 3) {
3419 DRM_ERROR("Relocation not 4-byte aligned: "
3420 "obj %p target %d offset %d.\n",
3421 obj, reloc->target_handle,
3422 (int) reloc->offset);
3423 drm_gem_object_unreference(target_obj);
3424 i915_gem_object_unpin(obj);
3425 return -EINVAL;
3426 }
3427
3428 /* and points to somewhere within the target object. */
3429 if (reloc->delta >= target_obj->size) {
3430 DRM_ERROR("Relocation beyond target object bounds: "
3431 "obj %p target %d delta %d size %d.\n",
3432 obj, reloc->target_handle,
3433 (int) reloc->delta, (int) target_obj->size);
3434 drm_gem_object_unreference(target_obj);
3435 i915_gem_object_unpin(obj);
3436 return -EINVAL;
3437 }
3438
2ef7eeaa
EA		 3439 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3440 if (ret != 0) {
3441 drm_gem_object_unreference(target_obj);
3442 i915_gem_object_unpin(obj);
3443 return -EINVAL;
673a394b
EA		 3444 }
3445
3446 /* Map the page containing the relocation we're going to
3447 * perform.
3448 */
40a5f0de 3449 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3450 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3451 (reloc_offset &
3452 ~(PAGE_SIZE - 1)));
3043c60c 3453 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3454 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3455 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3456
3457#if WATCH_BUF
3458 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3459 obj, (unsigned int) reloc->offset,
673a394b
EA		 3460 readl(reloc_entry), reloc_val);
3461#endif
3462 writel(reloc_val, reloc_entry);
0839ccb8 3463 io_mapping_unmap_atomic(reloc_page);
673a394b 3464
40a5f0de
EA		 3465 /* The updated presumed offset for this entry will be
3466 * copied back out to the user.
673a394b 3467 */
40a5f0de 3468 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3469
3470 drm_gem_object_unreference(target_obj);
3471 }
3472
673a394b
EA		 3473#if WATCH_BUF
3474 if (0)
3475 i915_gem_dump_object(obj, 128, __func__, ~0);
3476#endif
3477 return 0;
3478}
3479
673a394b
EA		 3480/* Throttle our rendering by waiting until the ring has completed our requests
3481 * emitted over 20 msec ago.
3482 *
b962442e
EA		 3483 * Note that if we were to use the current jiffies each time around the loop,
3484 * we wouldn't escape the function with any frames outstanding if the time to
3485 * render a frame was over 20ms.
3486 *
673a394b
EA		 3487 * This should get us reasonable parallelism between CPU and GPU but also
3488 * relatively low latency when blocking on a particular request to finish.
3489 */
3490static int
3491i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3492{
3493 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3494 int ret = 0;
b962442e 3495 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3496
3497 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3498 while (!list_empty(&i915_file_priv->mm.request_list)) {
3499 struct drm_i915_gem_request *request;
3500
3501 request = list_first_entry(&i915_file_priv->mm.request_list,
3502 struct drm_i915_gem_request,
3503 client_list);
3504
3505 if (time_after_eq(request->emitted_jiffies, recent_enough))
3506 break;
3507
852835f3 3508 ret = i915_wait_request(dev, request->seqno, request->ring);
b962442e
EA		 3509 if (ret != 0)
3510 break;
3511 }
673a394b 3512 mutex_unlock(&dev->struct_mutex);
b962442e 3513
673a394b
EA		 3514 return ret;
3515}
3516
40a5f0de 3517static int
76446cac 3518i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3519 uint32_t buffer_count,
3520 struct drm_i915_gem_relocation_entry **relocs)
3521{
3522 uint32_t reloc_count = 0, reloc_index = 0, i;
3523 int ret;
3524
3525 *relocs = NULL;
3526 for (i = 0; i < buffer_count; i++) {
3527 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3528 return -EINVAL;
3529 reloc_count += exec_list[i].relocation_count;
3530 }
3531
8e7d2b2c 3532 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3533 if (*relocs == NULL) {
3534 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3535 return -ENOMEM;
76446cac 3536 }
40a5f0de
EA		 3537
3538 for (i = 0; i < buffer_count; i++) {
3539 struct drm_i915_gem_relocation_entry __user *user_relocs;
3540
3541 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3542
3543 ret = copy_from_user(&(*relocs)[reloc_index],
3544 user_relocs,
3545 exec_list[i].relocation_count *
3546 sizeof(**relocs));
3547 if (ret != 0) {
8e7d2b2c 3548 drm_free_large(*relocs);
40a5f0de 3549 *relocs = NULL;
2bc43b5c 3550 return -EFAULT;
40a5f0de
EA		 3551 }
3552
3553 reloc_index += exec_list[i].relocation_count;
3554 }
3555
2bc43b5c 3556 return 0;
40a5f0de
EA		 3557}
3558
3559static int
76446cac 3560i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3561 uint32_t buffer_count,
3562 struct drm_i915_gem_relocation_entry *relocs)
3563{
3564 uint32_t reloc_count = 0, i;
2bc43b5c 3565 int ret = 0;
40a5f0de 3566
93533c29
CW		 3567 if (relocs == NULL)
3568 return 0;
3569
40a5f0de
EA		 3570 for (i = 0; i < buffer_count; i++) {
3571 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3572 int unwritten;
40a5f0de
EA		 3573
3574 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3575
2bc43b5c
FM		 3576 unwritten = copy_to_user(user_relocs,
3577 &relocs[reloc_count],
3578 exec_list[i].relocation_count *
3579 sizeof(*relocs));
3580
3581 if (unwritten) {
3582 ret = -EFAULT;
3583 goto err;
40a5f0de
EA		 3584 }
3585
3586 reloc_count += exec_list[i].relocation_count;
3587 }
3588
2bc43b5c 3589err:
8e7d2b2c 3590 drm_free_large(relocs);
40a5f0de
EA		 3591
3592 return ret;
3593}
3594
83d60795 3595static int
76446cac 3596i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3597 uint64_t exec_offset)
3598{
3599 uint32_t exec_start, exec_len;
3600
3601 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3602 exec_len = (uint32_t) exec->batch_len;
3603
3604 if ((exec_start | exec_len) & 0x7)
3605 return -EINVAL;
3606
3607 if (!exec_start)
3608 return -EINVAL;
3609
3610 return 0;
3611}
3612
6b95a207
KH		 3613static int
3614i915_gem_wait_for_pending_flip(struct drm_device *dev,
3615 struct drm_gem_object **object_list,
3616 int count)
3617{
3618 drm_i915_private_t *dev_priv = dev->dev_private;
3619 struct drm_i915_gem_object *obj_priv;
3620 DEFINE_WAIT(wait);
3621 int i, ret = 0;
3622
3623 for (;;) {
3624 prepare_to_wait(&dev_priv->pending_flip_queue,
3625 &wait, TASK_INTERRUPTIBLE);
3626 for (i = 0; i < count; i++) {
23010e43 3627 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3628 if (atomic_read(&obj_priv->pending_flip) > 0)
3629 break;
3630 }
3631 if (i == count)
3632 break;
3633
3634 if (!signal_pending(current)) {
3635 mutex_unlock(&dev->struct_mutex);
3636 schedule();
3637 mutex_lock(&dev->struct_mutex);
3638 continue;
3639 }
3640 ret = -ERESTARTSYS;
3641 break;
3642 }
3643 finish_wait(&dev_priv->pending_flip_queue, &wait);
3644
3645 return ret;
3646}
3647
43b27f40 3648
673a394b 3649int
76446cac
JB		 3650i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3651 struct drm_file *file_priv,
3652 struct drm_i915_gem_execbuffer2 *args,
3653 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3654{
3655 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3656 struct drm_gem_object **object_list = NULL;
3657 struct drm_gem_object *batch_obj;
b70d11da 3658 struct drm_i915_gem_object *obj_priv;
201361a5 3659 struct drm_clip_rect *cliprects = NULL;
93533c29 3660 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3661 int ret = 0, ret2, i, pinned = 0;
673a394b 3662 uint64_t exec_offset;
40a5f0de 3663 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3664 int pin_tries, flips;
673a394b 3665
852835f3
ZN		 3666 struct intel_ring_buffer *ring = NULL;
3667
673a394b
EA		 3668#if WATCH_EXEC
3669 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3670 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3671#endif
d1b851fc
ZN		 3672 if (args->flags & I915_EXEC_BSD) {
3673 if (!HAS_BSD(dev)) {
3674 DRM_ERROR("execbuf with wrong flag\n");
3675 return -EINVAL;
3676 }
3677 ring = &dev_priv->bsd_ring;
3678 } else {
3679 ring = &dev_priv->render_ring;
3680 }
3681
673a394b 3682
4f481ed2
EA		 3683 if (args->buffer_count < 1) {
3684 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3685 return -EINVAL;
3686 }
c8e0f93a 3687 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3688 if (object_list == NULL) {
3689 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3690 args->buffer_count);
3691 ret = -ENOMEM;
3692 goto pre_mutex_err;
3693 }
673a394b 3694
201361a5 3695 if (args->num_cliprects != 0) {
9a298b2a
EA		 3696 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3697 GFP_KERNEL);
a40e8d31
OA		 3698 if (cliprects == NULL) {
3699 ret = -ENOMEM;
201361a5 3700 goto pre_mutex_err;
a40e8d31 3701 }
201361a5
EA		 3702
3703 ret = copy_from_user(cliprects,
3704 (struct drm_clip_rect __user *)
3705 (uintptr_t) args->cliprects_ptr,
3706 sizeof(*cliprects) * args->num_cliprects);
3707 if (ret != 0) {
3708 DRM_ERROR("copy %d cliprects failed: %d\n",
3709 args->num_cliprects, ret);
3710 goto pre_mutex_err;
3711 }
3712 }
3713
40a5f0de
EA		 3714 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3715 &relocs);
3716 if (ret != 0)
3717 goto pre_mutex_err;
3718
673a394b
EA		 3719 mutex_lock(&dev->struct_mutex);
3720
3721 i915_verify_inactive(dev, __FILE__, __LINE__);
3722
ba1234d1 3723 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3724 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3725 ret = -EIO;
3726 goto pre_mutex_err;
673a394b
EA		 3727 }
3728
3729 if (dev_priv->mm.suspended) {
673a394b 3730 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3731 ret = -EBUSY;
3732 goto pre_mutex_err;
673a394b
EA		 3733 }
3734
ac94a962 3735 /* Look up object handles */
6b95a207 3736 flips = 0;
673a394b
EA		 3737 for (i = 0; i < args->buffer_count; i++) {
3738 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3739 exec_list[i].handle);
3740 if (object_list[i] == NULL) {
3741 DRM_ERROR("Invalid object handle %d at index %d\n",
3742 exec_list[i].handle, i);
0ce907f8
CW		 3743 /* prevent error path from reading uninitialized data */
3744 args->buffer_count = i + 1;
673a394b
EA		 3745 ret = -EBADF;
3746 goto err;
3747 }
b70d11da 3748
23010e43 3749 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3750 if (obj_priv->in_execbuffer) {
3751 DRM_ERROR("Object %p appears more than once in object list\n",
3752 object_list[i]);
0ce907f8
CW		 3753 /* prevent error path from reading uninitialized data */
3754 args->buffer_count = i + 1;
b70d11da
KH		 3755 ret = -EBADF;
3756 goto err;
3757 }
3758 obj_priv->in_execbuffer = true;
6b95a207
KH		 3759 flips += atomic_read(&obj_priv->pending_flip);
3760 }
3761
3762 if (flips > 0) {
3763 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3764 args->buffer_count);
3765 if (ret)
3766 goto err;
ac94a962 3767 }
673a394b 3768
ac94a962
KP		 3769 /* Pin and relocate */
3770 for (pin_tries = 0; ; pin_tries++) {
3771 ret = 0;
40a5f0de
EA		 3772 reloc_index = 0;
3773
ac94a962
KP		 3774 for (i = 0; i < args->buffer_count; i++) {
3775 object_list[i]->pending_read_domains = 0;
3776 object_list[i]->pending_write_domain = 0;
3777 ret = i915_gem_object_pin_and_relocate(object_list[i],
3778 file_priv,
40a5f0de
EA		 3779 &exec_list[i],
3780 &relocs[reloc_index]);
ac94a962
KP		 3781 if (ret)
3782 break;
3783 pinned = i + 1;
40a5f0de 3784 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3785 }
3786 /* success */
3787 if (ret == 0)
3788 break;
3789
3790 /* error other than GTT full, or we've already tried again */
2939e1f5 3791 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3792 if (ret != -ERESTARTSYS) {
3793 unsigned long long total_size = 0;
3d1cc470
CW		 3794 int num_fences = 0;
3795 for (i = 0; i < args->buffer_count; i++) {
43b27f40 3796 obj_priv = to_intel_bo(object_list[i]);
3d1cc470 3797
07f73f69 3798 total_size += object_list[i]->size;
3d1cc470
CW		 3799 num_fences +=
3800 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3801 obj_priv->tiling_mode != I915_TILING_NONE;
3802 }
3803 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
07f73f69 3804 pinned+1, args->buffer_count,
3d1cc470
CW		 3805 total_size, num_fences,
3806 ret);
07f73f69
CW		 3807 DRM_ERROR("%d objects [%d pinned], "
3808 "%d object bytes [%d pinned], "
3809 "%d/%d gtt bytes\n",
3810 atomic_read(&dev->object_count),
3811 atomic_read(&dev->pin_count),
3812 atomic_read(&dev->object_memory),
3813 atomic_read(&dev->pin_memory),
3814 atomic_read(&dev->gtt_memory),
3815 dev->gtt_total);
3816 }
673a394b
EA		 3817 goto err;
3818 }
ac94a962
KP		 3819
3820 /* unpin all of our buffers */
3821 for (i = 0; i < pinned; i++)
3822 i915_gem_object_unpin(object_list[i]);
b1177636 3823 pinned = 0;
ac94a962
KP		 3824
3825 /* evict everyone we can from the aperture */
3826 ret = i915_gem_evict_everything(dev);
07f73f69 3827 if (ret && ret != -ENOSPC)
ac94a962 3828 goto err;
673a394b
EA		 3829 }
3830
3831 /* Set the pending read domains for the batch buffer to COMMAND */
3832 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3833 if (batch_obj->pending_write_domain) {
3834 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3835 ret = -EINVAL;
3836 goto err;
3837 }
3838 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3839
83d60795
CW		 3840 /* Sanity check the batch buffer, prior to moving objects */
3841 exec_offset = exec_list[args->buffer_count - 1].offset;
3842 ret = i915_gem_check_execbuffer (args, exec_offset);
3843 if (ret != 0) {
3844 DRM_ERROR("execbuf with invalid offset/length\n");
3845 goto err;
3846 }
3847
673a394b
EA		 3848 i915_verify_inactive(dev, __FILE__, __LINE__);
3849
646f0f6e
KP		 3850 /* Zero the global flush/invalidate flags. These
3851 * will be modified as new domains are computed
3852 * for each object
3853 */
3854 dev->invalidate_domains = 0;
3855 dev->flush_domains = 0;
3856
673a394b
EA		 3857 for (i = 0; i < args->buffer_count; i++) {
3858 struct drm_gem_object *obj = object_list[i];
673a394b 3859
646f0f6e 3860 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3861 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3862 }
3863
3864 i915_verify_inactive(dev, __FILE__, __LINE__);
3865
646f0f6e
KP		 3866 if (dev->invalidate_domains | dev->flush_domains) {
3867#if WATCH_EXEC
3868 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3869 __func__,
3870 dev->invalidate_domains,
3871 dev->flush_domains);
3872#endif
3873 i915_gem_flush(dev,
3874 dev->invalidate_domains,
3875 dev->flush_domains);
852835f3 3876 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
b962442e 3877 (void)i915_add_request(dev, file_priv,
852835f3
ZN		 3878 dev->flush_domains,
3879 &dev_priv->render_ring);
3880
d1b851fc
ZN		 3881 if (HAS_BSD(dev))
3882 (void)i915_add_request(dev, file_priv,
3883 dev->flush_domains,
3884 &dev_priv->bsd_ring);
852835f3 3885 }
646f0f6e 3886 }
673a394b 3887
efbeed96
EA		 3888 for (i = 0; i < args->buffer_count; i++) {
3889 struct drm_gem_object *obj = object_list[i];
23010e43 3890 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3891 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3892
3893 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3894 if (obj->write_domain)
3895 list_move_tail(&obj_priv->gpu_write_list,
3896 &dev_priv->mm.gpu_write_list);
3897 else
3898 list_del_init(&obj_priv->gpu_write_list);
3899
1c5d22f7
CW		 3900 trace_i915_gem_object_change_domain(obj,
3901 obj->read_domains,
3902 old_write_domain);
efbeed96
EA		 3903 }
3904
673a394b
EA		 3905 i915_verify_inactive(dev, __FILE__, __LINE__);
3906
3907#if WATCH_COHERENCY
3908 for (i = 0; i < args->buffer_count; i++) {
3909 i915_gem_object_check_coherency(object_list[i],
3910 exec_list[i].handle);
3911 }
3912#endif
3913
673a394b 3914#if WATCH_EXEC
6911a9b8 3915 i915_gem_dump_object(batch_obj,
673a394b
EA		 3916 args->batch_len,
3917 __func__,
3918 ~0);
3919#endif
3920
673a394b 3921 /* Exec the batchbuffer */
852835f3
ZN		 3922 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3923 cliprects, exec_offset);
673a394b
EA		 3924 if (ret) {
3925 DRM_ERROR("dispatch failed %d\n", ret);
3926 goto err;
3927 }
3928
3929 /*
3930 * Ensure that the commands in the batch buffer are
3931 * finished before the interrupt fires
3932 */
852835f3 3933 flush_domains = i915_retire_commands(dev, ring);
673a394b
EA		 3934
3935 i915_verify_inactive(dev, __FILE__, __LINE__);
3936
3937 /*
3938 * Get a seqno representing the execution of the current buffer,
3939 * which we can wait on. We would like to mitigate these interrupts,
3940 * likely by only creating seqnos occasionally (so that we have
3941 * *some* interrupts representing completion of buffers that we can
3942 * wait on when trying to clear up gtt space).
3943 */
852835f3 3944 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
673a394b 3945 BUG_ON(seqno == 0);
673a394b
EA		 3946 for (i = 0; i < args->buffer_count; i++) {
3947 struct drm_gem_object *obj = object_list[i];
852835f3 3948 obj_priv = to_intel_bo(obj);
673a394b 3949
852835f3 3950 i915_gem_object_move_to_active(obj, seqno, ring);
673a394b
EA		 3951#if WATCH_LRU
3952 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3953#endif
3954 }
3955#if WATCH_LRU
3956 i915_dump_lru(dev, __func__);
3957#endif
3958
3959 i915_verify_inactive(dev, __FILE__, __LINE__);
3960
673a394b 3961err:
aad87dff
JL		 3962 for (i = 0; i < pinned; i++)
3963 i915_gem_object_unpin(object_list[i]);
3964
b70d11da
KH		 3965 for (i = 0; i < args->buffer_count; i++) {
3966 if (object_list[i]) {
23010e43 3967 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3968 obj_priv->in_execbuffer = false;
3969 }
aad87dff 3970 drm_gem_object_unreference(object_list[i]);
b70d11da 3971 }
673a394b 3972
673a394b
EA		 3973 mutex_unlock(&dev->struct_mutex);
3974
93533c29 3975pre_mutex_err:
40a5f0de
EA		 3976 /* Copy the updated relocations out regardless of current error
3977 * state. Failure to update the relocs would mean that the next
3978 * time userland calls execbuf, it would do so with presumed offset
3979 * state that didn't match the actual object state.
3980 */
3981 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3982 relocs);
3983 if (ret2 != 0) {
3984 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3985
3986 if (ret == 0)
3987 ret = ret2;
3988 }
3989
8e7d2b2c 3990 drm_free_large(object_list);
9a298b2a 3991 kfree(cliprects);
673a394b
EA		 3992
3993 return ret;
3994}
3995
76446cac
JB		 3996/*
3997 * Legacy execbuffer just creates an exec2 list from the original exec object
3998 * list array and passes it to the real function.
3999 */
4000int
4001i915_gem_execbuffer(struct drm_device *dev, void *data,
4002 struct drm_file *file_priv)
4003{
4004 struct drm_i915_gem_execbuffer *args = data;
4005 struct drm_i915_gem_execbuffer2 exec2;
4006 struct drm_i915_gem_exec_object *exec_list = NULL;
4007 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4008 int ret, i;
4009
4010#if WATCH_EXEC
4011 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4012 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4013#endif
4014
4015 if (args->buffer_count < 1) {
4016 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4017 return -EINVAL;
4018 }
4019
4020 /* Copy in the exec list from userland */
4021 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4022 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4023 if (exec_list == NULL || exec2_list == NULL) {
4024 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4025 args->buffer_count);
4026 drm_free_large(exec_list);
4027 drm_free_large(exec2_list);
4028 return -ENOMEM;
4029 }
4030 ret = copy_from_user(exec_list,
4031 (struct drm_i915_relocation_entry __user *)
4032 (uintptr_t) args->buffers_ptr,
4033 sizeof(*exec_list) * args->buffer_count);
4034 if (ret != 0) {
4035 DRM_ERROR("copy %d exec entries failed %d\n",
4036 args->buffer_count, ret);
4037 drm_free_large(exec_list);
4038 drm_free_large(exec2_list);
4039 return -EFAULT;
4040 }
4041
4042 for (i = 0; i < args->buffer_count; i++) {
4043 exec2_list[i].handle = exec_list[i].handle;
4044 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4045 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4046 exec2_list[i].alignment = exec_list[i].alignment;
4047 exec2_list[i].offset = exec_list[i].offset;
4048 if (!IS_I965G(dev))
4049 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4050 else
4051 exec2_list[i].flags = 0;
4052 }
4053
4054 exec2.buffers_ptr = args->buffers_ptr;
4055 exec2.buffer_count = args->buffer_count;
4056 exec2.batch_start_offset = args->batch_start_offset;
4057 exec2.batch_len = args->batch_len;
4058 exec2.DR1 = args->DR1;
4059 exec2.DR4 = args->DR4;
4060 exec2.num_cliprects = args->num_cliprects;
4061 exec2.cliprects_ptr = args->cliprects_ptr;
852835f3 4062 exec2.flags = I915_EXEC_RENDER;
76446cac
JB		 4063
4064 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4065 if (!ret) {
4066 /* Copy the new buffer offsets back to the user's exec list. */
4067 for (i = 0; i < args->buffer_count; i++)
4068 exec_list[i].offset = exec2_list[i].offset;
4069 /* ... and back out to userspace */
4070 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4071 (uintptr_t) args->buffers_ptr,
4072 exec_list,
4073 sizeof(*exec_list) * args->buffer_count);
4074 if (ret) {
4075 ret = -EFAULT;
4076 DRM_ERROR("failed to copy %d exec entries "
4077 "back to user (%d)\n",
4078 args->buffer_count, ret);
4079 }
76446cac
JB		 4080 }
4081
4082 drm_free_large(exec_list);
4083 drm_free_large(exec2_list);
4084 return ret;
4085}
4086
4087int
4088i915_gem_execbuffer2(struct drm_device *dev, void *data,
4089 struct drm_file *file_priv)
4090{
4091 struct drm_i915_gem_execbuffer2 *args = data;
4092 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4093 int ret;
4094
4095#if WATCH_EXEC
4096 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4097 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4098#endif
4099
4100 if (args->buffer_count < 1) {
4101 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4102 return -EINVAL;
4103 }
4104
4105 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4106 if (exec2_list == NULL) {
4107 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4108 args->buffer_count);
4109 return -ENOMEM;
4110 }
4111 ret = copy_from_user(exec2_list,
4112 (struct drm_i915_relocation_entry __user *)
4113 (uintptr_t) args->buffers_ptr,
4114 sizeof(*exec2_list) * args->buffer_count);
4115 if (ret != 0) {
4116 DRM_ERROR("copy %d exec entries failed %d\n",
4117 args->buffer_count, ret);
4118 drm_free_large(exec2_list);
4119 return -EFAULT;
4120 }
4121
4122 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4123 if (!ret) {
4124 /* Copy the new buffer offsets back to the user's exec list. */
4125 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4126 (uintptr_t) args->buffers_ptr,
4127 exec2_list,
4128 sizeof(*exec2_list) * args->buffer_count);
4129 if (ret) {
4130 ret = -EFAULT;
4131 DRM_ERROR("failed to copy %d exec entries "
4132 "back to user (%d)\n",
4133 args->buffer_count, ret);
4134 }
4135 }
4136
4137 drm_free_large(exec2_list);
4138 return ret;
4139}
4140
673a394b
EA		 4141int
4142i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4143{
4144 struct drm_device *dev = obj->dev;
23010e43 4145 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4146 int ret;
4147
778c3544
DV		 4148 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4149
673a394b 4150 i915_verify_inactive(dev, __FILE__, __LINE__);
ac0c6b5a
CW		 4151
4152 if (obj_priv->gtt_space != NULL) {
4153 if (alignment == 0)
4154 alignment = i915_gem_get_gtt_alignment(obj);
4155 if (obj_priv->gtt_offset & (alignment - 1)) {
4156 ret = i915_gem_object_unbind(obj);
4157 if (ret)
4158 return ret;
4159 }
4160 }
4161
673a394b
EA		 4162 if (obj_priv->gtt_space == NULL) {
4163 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4164 if (ret)
673a394b 4165 return ret;
22c344e9 4166 }
76446cac 4167
673a394b
EA		 4168 obj_priv->pin_count++;
4169
4170 /* If the object is not active and not pending a flush,
4171 * remove it from the inactive list
4172 */
4173 if (obj_priv->pin_count == 1) {
4174 atomic_inc(&dev->pin_count);
4175 atomic_add(obj->size, &dev->pin_memory);
4176 if (!obj_priv->active &&
21d509e3 4177 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4178 !list_empty(&obj_priv->list))
4179 list_del_init(&obj_priv->list);
4180 }
4181 i915_verify_inactive(dev, __FILE__, __LINE__);
4182
4183 return 0;
4184}
4185
4186void
4187i915_gem_object_unpin(struct drm_gem_object *obj)
4188{
4189 struct drm_device *dev = obj->dev;
4190 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4191 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4192
4193 i915_verify_inactive(dev, __FILE__, __LINE__);
4194 obj_priv->pin_count--;
4195 BUG_ON(obj_priv->pin_count < 0);
4196 BUG_ON(obj_priv->gtt_space == NULL);
4197
4198 /* If the object is no longer pinned, and is
4199 * neither active nor being flushed, then stick it on
4200 * the inactive list
4201 */
4202 if (obj_priv->pin_count == 0) {
4203 if (!obj_priv->active &&
21d509e3 4204 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4205 list_move_tail(&obj_priv->list,
4206 &dev_priv->mm.inactive_list);
4207 atomic_dec(&dev->pin_count);
4208 atomic_sub(obj->size, &dev->pin_memory);
4209 }
4210 i915_verify_inactive(dev, __FILE__, __LINE__);
4211}
4212
4213int
4214i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4215 struct drm_file *file_priv)
4216{
4217 struct drm_i915_gem_pin *args = data;
4218 struct drm_gem_object *obj;
4219 struct drm_i915_gem_object *obj_priv;
4220 int ret;
4221
4222 mutex_lock(&dev->struct_mutex);
4223
4224 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4225 if (obj == NULL) {
4226 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4227 args->handle);
4228 mutex_unlock(&dev->struct_mutex);
4229 return -EBADF;
4230 }
23010e43 4231 obj_priv = to_intel_bo(obj);
673a394b 4232
bb6baf76
CW		 4233 if (obj_priv->madv != I915_MADV_WILLNEED) {
4234 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4235 drm_gem_object_unreference(obj);
4236 mutex_unlock(&dev->struct_mutex);
4237 return -EINVAL;
4238 }
4239
79e53945
JB		 4240 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4241 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4242 args->handle);
96dec61d 4243 drm_gem_object_unreference(obj);
673a394b 4244 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4245 return -EINVAL;
4246 }
4247
4248 obj_priv->user_pin_count++;
4249 obj_priv->pin_filp = file_priv;
4250 if (obj_priv->user_pin_count == 1) {
4251 ret = i915_gem_object_pin(obj, args->alignment);
4252 if (ret != 0) {
4253 drm_gem_object_unreference(obj);
4254 mutex_unlock(&dev->struct_mutex);
4255 return ret;
4256 }
673a394b
EA		 4257 }
4258
4259 /* XXX - flush the CPU caches for pinned objects
4260 * as the X server doesn't manage domains yet
4261 */
e47c68e9 4262 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4263 args->offset = obj_priv->gtt_offset;
4264 drm_gem_object_unreference(obj);
4265 mutex_unlock(&dev->struct_mutex);
4266
4267 return 0;
4268}
4269
4270int
4271i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4272 struct drm_file *file_priv)
4273{
4274 struct drm_i915_gem_pin *args = data;
4275 struct drm_gem_object *obj;
79e53945 4276 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4277
4278 mutex_lock(&dev->struct_mutex);
4279
4280 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4281 if (obj == NULL) {
4282 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4283 args->handle);
4284 mutex_unlock(&dev->struct_mutex);
4285 return -EBADF;
4286 }
4287
23010e43 4288 obj_priv = to_intel_bo(obj);
79e53945
JB		 4289 if (obj_priv->pin_filp != file_priv) {
4290 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4291 args->handle);
4292 drm_gem_object_unreference(obj);
4293 mutex_unlock(&dev->struct_mutex);
4294 return -EINVAL;
4295 }
4296 obj_priv->user_pin_count--;
4297 if (obj_priv->user_pin_count == 0) {
4298 obj_priv->pin_filp = NULL;
4299 i915_gem_object_unpin(obj);
4300 }
673a394b
EA		 4301
4302 drm_gem_object_unreference(obj);
4303 mutex_unlock(&dev->struct_mutex);
4304 return 0;
4305}
4306
4307int
4308i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4309 struct drm_file *file_priv)
4310{
4311 struct drm_i915_gem_busy *args = data;
4312 struct drm_gem_object *obj;
4313 struct drm_i915_gem_object *obj_priv;
852835f3 4314 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4315
673a394b
EA		 4316 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4317 if (obj == NULL) {
4318 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4319 args->handle);
673a394b
EA		 4320 return -EBADF;
4321 }
4322
b1ce786c 4323 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4324 /* Update the active list for the hardware's current position.
4325 * Otherwise this only updates on a delayed timer or when irqs are
4326 * actually unmasked, and our working set ends up being larger than
4327 * required.
4328 */
852835f3 4329 i915_gem_retire_requests(dev, &dev_priv->render_ring);
f21289b3 4330
d1b851fc
ZN		 4331 if (HAS_BSD(dev))
4332 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
4333
23010e43 4334 obj_priv = to_intel_bo(obj);
c4de0a5d
EA		 4335 /* Don't count being on the flushing list against the object being
4336 * done. Otherwise, a buffer left on the flushing list but not getting
4337 * flushed (because nobody's flushing that domain) won't ever return
4338 * unbusy and get reused by libdrm's bo cache. The other expected
4339 * consumer of this interface, OpenGL's occlusion queries, also specs
4340 * that the objects get unbusy "eventually" without any interference.
4341 */
4342 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4343
4344 drm_gem_object_unreference(obj);
4345 mutex_unlock(&dev->struct_mutex);
4346 return 0;
4347}
4348
4349int
4350i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4351 struct drm_file *file_priv)
4352{
4353 return i915_gem_ring_throttle(dev, file_priv);
4354}
4355
3ef94daa
CW		 4356int
4357i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4358 struct drm_file *file_priv)
4359{
4360 struct drm_i915_gem_madvise *args = data;
4361 struct drm_gem_object *obj;
4362 struct drm_i915_gem_object *obj_priv;
4363
4364 switch (args->madv) {
4365 case I915_MADV_DONTNEED:
4366 case I915_MADV_WILLNEED:
4367 break;
4368 default:
4369 return -EINVAL;
4370 }
4371
4372 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4373 if (obj == NULL) {
4374 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4375 args->handle);
4376 return -EBADF;
4377 }
4378
4379 mutex_lock(&dev->struct_mutex);
23010e43 4380 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4381
4382 if (obj_priv->pin_count) {
4383 drm_gem_object_unreference(obj);
4384 mutex_unlock(&dev->struct_mutex);
4385
4386 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4387 return -EINVAL;
4388 }
4389
bb6baf76
CW		 4390 if (obj_priv->madv != __I915_MADV_PURGED)
4391 obj_priv->madv = args->madv;
3ef94daa 4392
2d7ef395
CW		 4393 /* if the object is no longer bound, discard its backing storage */
4394 if (i915_gem_object_is_purgeable(obj_priv) &&
4395 obj_priv->gtt_space == NULL)
4396 i915_gem_object_truncate(obj);
4397
bb6baf76
CW		 4398 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4399
3ef94daa
CW		 4400 drm_gem_object_unreference(obj);
4401 mutex_unlock(&dev->struct_mutex);
4402
4403 return 0;
4404}
4405
ac52bc56
DV		 4406struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4407 size_t size)
4408{
c397b908 4409 struct drm_i915_gem_object *obj;
ac52bc56 4410
c397b908
DV		 4411 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4412 if (obj == NULL)
4413 return NULL;
673a394b 4414
c397b908
DV		 4415 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4416 kfree(obj);
4417 return NULL;
4418 }
673a394b 4419
c397b908
DV		 4420 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4421 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4422
c397b908 4423 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4424 obj->base.driver_private = NULL;
c397b908
DV		 4425 obj->fence_reg = I915_FENCE_REG_NONE;
4426 INIT_LIST_HEAD(&obj->list);
4427 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4428 obj->madv = I915_MADV_WILLNEED;
de151cf6 4429
c397b908
DV		 4430 trace_i915_gem_object_create(&obj->base);
4431
4432 return &obj->base;
4433}
4434
4435int i915_gem_init_object(struct drm_gem_object *obj)
4436{
4437 BUG();
de151cf6 4438
673a394b
EA		 4439 return 0;
4440}
4441
4442void i915_gem_free_object(struct drm_gem_object *obj)
4443{
de151cf6 4444 struct drm_device *dev = obj->dev;
23010e43 4445 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 4446
1c5d22f7
CW		 4447 trace_i915_gem_object_destroy(obj);
4448
673a394b
EA		 4449 while (obj_priv->pin_count > 0)
4450 i915_gem_object_unpin(obj);
4451
71acb5eb
DA		 4452 if (obj_priv->phys_obj)
4453 i915_gem_detach_phys_object(dev, obj);
4454
673a394b
EA		 4455 i915_gem_object_unbind(obj);
4456
7e616158
CW		 4457 if (obj_priv->mmap_offset)
4458 i915_gem_free_mmap_offset(obj);
de151cf6 4459
c397b908
DV		 4460 drm_gem_object_release(obj);
4461
9a298b2a 4462 kfree(obj_priv->page_cpu_valid);
280b713b 4463 kfree(obj_priv->bit_17);
c397b908 4464 kfree(obj_priv);
673a394b
EA		 4465}
4466
ab5ee576 4467/** Unbinds all inactive objects. */
673a394b 4468static int
ab5ee576 4469i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4470{
ab5ee576 4471 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4472
ab5ee576
CW		 4473 while (!list_empty(&dev_priv->mm.inactive_list)) {
4474 struct drm_gem_object *obj;
4475 int ret;
673a394b 4476
a8089e84
DV		 4477 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4478 struct drm_i915_gem_object,
4479 list)->base;
673a394b
EA		 4480
4481 ret = i915_gem_object_unbind(obj);
4482 if (ret != 0) {
ab5ee576 4483 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4484 return ret;
4485 }
4486 }
4487
673a394b
EA		 4488 return 0;
4489}
4490
29105ccc
CW		 4491int
4492i915_gem_idle(struct drm_device *dev)
4493{
4494 drm_i915_private_t *dev_priv = dev->dev_private;
4495 int ret;
28dfe52a 4496
29105ccc 4497 mutex_lock(&dev->struct_mutex);
1c5d22f7 4498
8187a2b7 4499 if (dev_priv->mm.suspended ||
d1b851fc
ZN		 4500 (dev_priv->render_ring.gem_object == NULL) ||
4501 (HAS_BSD(dev) &&
4502 dev_priv->bsd_ring.gem_object == NULL)) {
29105ccc
CW		 4503 mutex_unlock(&dev->struct_mutex);
4504 return 0;
28dfe52a
EA		 4505 }
4506
29105ccc 4507 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4508 if (ret) {
4509 mutex_unlock(&dev->struct_mutex);
673a394b 4510 return ret;
6dbe2772 4511 }
673a394b 4512
29105ccc
CW		 4513 /* Under UMS, be paranoid and evict. */
4514 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4515 ret = i915_gem_evict_from_inactive_list(dev);
4516 if (ret) {
4517 mutex_unlock(&dev->struct_mutex);
4518 return ret;
4519 }
4520 }
4521
4522 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4523 * We need to replace this with a semaphore, or something.
4524 * And not confound mm.suspended!
4525 */
4526 dev_priv->mm.suspended = 1;
4527 del_timer(&dev_priv->hangcheck_timer);
4528
4529 i915_kernel_lost_context(dev);
6dbe2772 4530 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4531
6dbe2772
KP		 4532 mutex_unlock(&dev->struct_mutex);
4533
29105ccc
CW		 4534 /* Cancel the retire work handler, which should be idle now. */
4535 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4536
673a394b
EA		 4537 return 0;
4538}
4539
e552eb70
JB		 4540/*
4541 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4542 * over cache flushing.
4543 */
8187a2b7 4544static int
e552eb70
JB		 4545i915_gem_init_pipe_control(struct drm_device *dev)
4546{
4547 drm_i915_private_t *dev_priv = dev->dev_private;
4548 struct drm_gem_object *obj;
4549 struct drm_i915_gem_object *obj_priv;
4550 int ret;
4551
34dc4d44 4552 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4553 if (obj == NULL) {
4554 DRM_ERROR("Failed to allocate seqno page\n");
4555 ret = -ENOMEM;
4556 goto err;
4557 }
4558 obj_priv = to_intel_bo(obj);
4559 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4560
4561 ret = i915_gem_object_pin(obj, 4096);
4562 if (ret)
4563 goto err_unref;
4564
4565 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4566 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4567 if (dev_priv->seqno_page == NULL)
4568 goto err_unpin;
4569
4570 dev_priv->seqno_obj = obj;
4571 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4572
4573 return 0;
4574
4575err_unpin:
4576 i915_gem_object_unpin(obj);
4577err_unref:
4578 drm_gem_object_unreference(obj);
4579err:
4580 return ret;
4581}
4582
8187a2b7
ZN		 4583
4584static void
e552eb70
JB		 4585i915_gem_cleanup_pipe_control(struct drm_device *dev)
4586{
4587 drm_i915_private_t *dev_priv = dev->dev_private;
4588 struct drm_gem_object *obj;
4589 struct drm_i915_gem_object *obj_priv;
4590
4591 obj = dev_priv->seqno_obj;
4592 obj_priv = to_intel_bo(obj);
4593 kunmap(obj_priv->pages[0]);
4594 i915_gem_object_unpin(obj);
4595 drm_gem_object_unreference(obj);
4596 dev_priv->seqno_obj = NULL;
4597
4598 dev_priv->seqno_page = NULL;
673a394b
EA		 4599}
4600
8187a2b7
ZN		 4601int
4602i915_gem_init_ringbuffer(struct drm_device *dev)
4603{
4604 drm_i915_private_t *dev_priv = dev->dev_private;
4605 int ret;
68f95ba9 4606
8187a2b7 4607 dev_priv->render_ring = render_ring;
68f95ba9 4608
8187a2b7
ZN		 4609 if (!I915_NEED_GFX_HWS(dev)) {
4610 dev_priv->render_ring.status_page.page_addr
4611 = dev_priv->status_page_dmah->vaddr;
4612 memset(dev_priv->render_ring.status_page.page_addr,
4613 0, PAGE_SIZE);
4614 }
68f95ba9 4615
8187a2b7
ZN		 4616 if (HAS_PIPE_CONTROL(dev)) {
4617 ret = i915_gem_init_pipe_control(dev);
4618 if (ret)
4619 return ret;
4620 }
68f95ba9 4621
8187a2b7 4622 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
68f95ba9
CW		 4623 if (ret)
4624 goto cleanup_pipe_control;
4625
4626 if (HAS_BSD(dev)) {
d1b851fc
ZN		 4627 dev_priv->bsd_ring = bsd_ring;
4628 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
68f95ba9
CW		 4629 if (ret)
4630 goto cleanup_render_ring;
d1b851fc 4631 }
68f95ba9
CW		 4632
4633 return 0;
4634
4635cleanup_render_ring:
4636 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4637cleanup_pipe_control:
4638 if (HAS_PIPE_CONTROL(dev))
4639 i915_gem_cleanup_pipe_control(dev);
8187a2b7
ZN		 4640 return ret;
4641}
4642
4643void
4644i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4645{
4646 drm_i915_private_t *dev_priv = dev->dev_private;
4647
4648 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4649 if (HAS_BSD(dev))
4650 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
8187a2b7
ZN		 4651 if (HAS_PIPE_CONTROL(dev))
4652 i915_gem_cleanup_pipe_control(dev);
4653}
4654
673a394b
EA		 4655int
4656i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4657 struct drm_file *file_priv)
4658{
4659 drm_i915_private_t *dev_priv = dev->dev_private;
4660 int ret;
4661
79e53945
JB		 4662 if (drm_core_check_feature(dev, DRIVER_MODESET))
4663 return 0;
4664
ba1234d1 4665 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4666 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4667 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4668 }
4669
673a394b 4670 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4671 dev_priv->mm.suspended = 0;
4672
4673 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4674 if (ret != 0) {
4675 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4676 return ret;
d816f6ac 4677 }
9bb2d6f9 4678
5e118f41 4679 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 4680 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
d1b851fc 4681 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
5e118f41
CW		 4682 spin_unlock(&dev_priv->mm.active_list_lock);
4683
673a394b
EA		 4684 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4685 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
852835f3 4686 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
d1b851fc 4687 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
673a394b 4688 mutex_unlock(&dev->struct_mutex);
dbb19d30 4689
5f35308b
CW		 4690 ret = drm_irq_install(dev);
4691 if (ret)
4692 goto cleanup_ringbuffer;
dbb19d30 4693
673a394b 4694 return 0;
5f35308b
CW		 4695
4696cleanup_ringbuffer:
4697 mutex_lock(&dev->struct_mutex);
4698 i915_gem_cleanup_ringbuffer(dev);
4699 dev_priv->mm.suspended = 1;
4700 mutex_unlock(&dev->struct_mutex);
4701
4702 return ret;
673a394b
EA		 4703}
4704
4705int
4706i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4707 struct drm_file *file_priv)
4708{
79e53945
JB		 4709 if (drm_core_check_feature(dev, DRIVER_MODESET))
4710 return 0;
4711
dbb19d30 4712 drm_irq_uninstall(dev);
e6890f6f 4713 return i915_gem_idle(dev);
673a394b
EA		 4714}
4715
4716void
4717i915_gem_lastclose(struct drm_device *dev)
4718{
4719 int ret;
673a394b 4720
e806b495
EA		 4721 if (drm_core_check_feature(dev, DRIVER_MODESET))
4722 return;
4723
6dbe2772
KP		 4724 ret = i915_gem_idle(dev);
4725 if (ret)
4726 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4727}
4728
4729void
4730i915_gem_load(struct drm_device *dev)
4731{
b5aa8a0f 4732 int i;
673a394b
EA		 4733 drm_i915_private_t *dev_priv = dev->dev_private;
4734
5e118f41 4735 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b 4736 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4737 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b 4738 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
a09ba7fa 4739 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
852835f3
ZN		 4740 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4741 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
d1b851fc
ZN		 4742 if (HAS_BSD(dev)) {
4743 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4744 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4745 }
007cc8ac
DV		 4746 for (i = 0; i < 16; i++)
4747 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4748 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4749 i915_gem_retire_work_handler);
31169714
CW		 4750 spin_lock(&shrink_list_lock);
4751 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4752 spin_unlock(&shrink_list_lock);
4753
94400120
DA		 4754 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4755 if (IS_GEN3(dev)) {
4756 u32 tmp = I915_READ(MI_ARB_STATE);
4757 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4758 /* arb state is a masked write, so set bit + bit in mask */
4759 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4760 I915_WRITE(MI_ARB_STATE, tmp);
4761 }
4762 }
4763
de151cf6 4764 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4765 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4766 dev_priv->fence_reg_start = 3;
de151cf6 4767
0f973f27 4768 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4769 dev_priv->num_fence_regs = 16;
4770 else
4771 dev_priv->num_fence_regs = 8;
4772
b5aa8a0f
GH		 4773 /* Initialize fence registers to zero */
4774 if (IS_I965G(dev)) {
4775 for (i = 0; i < 16; i++)
4776 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4777 } else {
4778 for (i = 0; i < 8; i++)
4779 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4780 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4781 for (i = 0; i < 8; i++)
4782 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4783 }
673a394b 4784 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4785 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4786}
71acb5eb
DA		 4787
4788/*
4789 * Create a physically contiguous memory object for this object
4790 * e.g. for cursor + overlay regs
4791 */
4792int i915_gem_init_phys_object(struct drm_device *dev,
4793 int id, int size)
4794{
4795 drm_i915_private_t *dev_priv = dev->dev_private;
4796 struct drm_i915_gem_phys_object *phys_obj;
4797 int ret;
4798
4799 if (dev_priv->mm.phys_objs[id - 1] || !size)
4800 return 0;
4801
9a298b2a 4802 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4803 if (!phys_obj)
4804 return -ENOMEM;
4805
4806 phys_obj->id = id;
4807
e6be8d9d 4808 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4809 if (!phys_obj->handle) {
4810 ret = -ENOMEM;
4811 goto kfree_obj;
4812 }
4813#ifdef CONFIG_X86
4814 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4815#endif
4816
4817 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4818
4819 return 0;
4820kfree_obj:
9a298b2a 4821 kfree(phys_obj);
71acb5eb
DA		 4822 return ret;
4823}
4824
4825void i915_gem_free_phys_object(struct drm_device *dev, int id)
4826{
4827 drm_i915_private_t *dev_priv = dev->dev_private;
4828 struct drm_i915_gem_phys_object *phys_obj;
4829
4830 if (!dev_priv->mm.phys_objs[id - 1])
4831 return;
4832
4833 phys_obj = dev_priv->mm.phys_objs[id - 1];
4834 if (phys_obj->cur_obj) {
4835 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4836 }
4837
4838#ifdef CONFIG_X86
4839 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4840#endif
4841 drm_pci_free(dev, phys_obj->handle);
4842 kfree(phys_obj);
4843 dev_priv->mm.phys_objs[id - 1] = NULL;
4844}
4845
4846void i915_gem_free_all_phys_object(struct drm_device *dev)
4847{
4848 int i;
4849
260883c8 4850 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4851 i915_gem_free_phys_object(dev, i);
4852}
4853
4854void i915_gem_detach_phys_object(struct drm_device *dev,
4855 struct drm_gem_object *obj)
4856{
4857 struct drm_i915_gem_object *obj_priv;
4858 int i;
4859 int ret;
4860 int page_count;
4861
23010e43 4862 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4863 if (!obj_priv->phys_obj)
4864 return;
4865
4bdadb97 4866 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4867 if (ret)
4868 goto out;
4869
4870 page_count = obj->size / PAGE_SIZE;
4871
4872 for (i = 0; i < page_count; i++) {
856fa198 4873 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4874 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4875
4876 memcpy(dst, src, PAGE_SIZE);
4877 kunmap_atomic(dst, KM_USER0);
4878 }
856fa198 4879 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4880 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4881
4882 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4883out:
4884 obj_priv->phys_obj->cur_obj = NULL;
4885 obj_priv->phys_obj = NULL;
4886}
4887
4888int
4889i915_gem_attach_phys_object(struct drm_device *dev,
4890 struct drm_gem_object *obj, int id)
4891{
4892 drm_i915_private_t *dev_priv = dev->dev_private;
4893 struct drm_i915_gem_object *obj_priv;
4894 int ret = 0;
4895 int page_count;
4896 int i;
4897
4898 if (id > I915_MAX_PHYS_OBJECT)
4899 return -EINVAL;
4900
23010e43 4901 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4902
4903 if (obj_priv->phys_obj) {
4904 if (obj_priv->phys_obj->id == id)
4905 return 0;
4906 i915_gem_detach_phys_object(dev, obj);
4907 }
4908
4909
4910 /* create a new object */
4911 if (!dev_priv->mm.phys_objs[id - 1]) {
4912 ret = i915_gem_init_phys_object(dev, id,
4913 obj->size);
4914 if (ret) {
aeb565df 4915 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4916 goto out;
4917 }
4918 }
4919
4920 /* bind to the object */
4921 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4922 obj_priv->phys_obj->cur_obj = obj;
4923
4bdadb97 4924 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4925 if (ret) {
4926 DRM_ERROR("failed to get page list\n");
4927 goto out;
4928 }
4929
4930 page_count = obj->size / PAGE_SIZE;
4931
4932 for (i = 0; i < page_count; i++) {
856fa198 4933 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4934 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4935
4936 memcpy(dst, src, PAGE_SIZE);
4937 kunmap_atomic(src, KM_USER0);
4938 }
4939
d78b47b9
CW		 4940 i915_gem_object_put_pages(obj);
4941
71acb5eb
DA		 4942 return 0;
4943out:
4944 return ret;
4945}
4946
4947static int
4948i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4949 struct drm_i915_gem_pwrite *args,
4950 struct drm_file *file_priv)
4951{
23010e43 4952 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4953 void *obj_addr;
4954 int ret;
4955 char __user *user_data;
4956
4957 user_data = (char __user *) (uintptr_t) args->data_ptr;
4958 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4959
44d98a61 4960 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4961 ret = copy_from_user(obj_addr, user_data, args->size);
4962 if (ret)
4963 return -EFAULT;
4964
4965 drm_agp_chipset_flush(dev);
4966 return 0;
4967}
b962442e
EA		 4968
4969void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4970{
4971 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4972
4973 /* Clean up our request list when the client is going away, so that
4974 * later retire_requests won't dereference our soon-to-be-gone
4975 * file_priv.
4976 */
4977 mutex_lock(&dev->struct_mutex);
4978 while (!list_empty(&i915_file_priv->mm.request_list))
4979 list_del_init(i915_file_priv->mm.request_list.next);
4980 mutex_unlock(&dev->struct_mutex);
4981}
31169714 4982
1637ef41
CW		 4983static int
4984i915_gpu_is_active(struct drm_device *dev)
4985{
4986 drm_i915_private_t *dev_priv = dev->dev_private;
4987 int lists_empty;
4988
4989 spin_lock(&dev_priv->mm.active_list_lock);
4990 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
852835f3 4991 list_empty(&dev_priv->render_ring.active_list);
d1b851fc
ZN		 4992 if (HAS_BSD(dev))
4993 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
1637ef41
CW		 4994 spin_unlock(&dev_priv->mm.active_list_lock);
4995
4996 return !lists_empty;
4997}
4998
31169714 4999static int
7f8275d0 5000i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
31169714
CW		 5001{
5002 drm_i915_private_t *dev_priv, *next_dev;
5003 struct drm_i915_gem_object *obj_priv, *next_obj;
5004 int cnt = 0;
5005 int would_deadlock = 1;
5006
5007 /* "fast-path" to count number of available objects */
5008 if (nr_to_scan == 0) {
5009 spin_lock(&shrink_list_lock);
5010 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5011 struct drm_device *dev = dev_priv->dev;
5012
5013 if (mutex_trylock(&dev->struct_mutex)) {
5014 list_for_each_entry(obj_priv,
5015 &dev_priv->mm.inactive_list,
5016 list)
5017 cnt++;
5018 mutex_unlock(&dev->struct_mutex);
5019 }
5020 }
5021 spin_unlock(&shrink_list_lock);
5022
5023 return (cnt / 100) * sysctl_vfs_cache_pressure;
5024 }
5025
5026 spin_lock(&shrink_list_lock);
5027
1637ef41 5028rescan:
31169714
CW		 5029 /* first scan for clean buffers */
5030 list_for_each_entry_safe(dev_priv, next_dev,
5031 &shrink_list, mm.shrink_list) {
5032 struct drm_device *dev = dev_priv->dev;
5033
5034 if (! mutex_trylock(&dev->struct_mutex))
5035 continue;
5036
5037 spin_unlock(&shrink_list_lock);
852835f3 5038 i915_gem_retire_requests(dev, &dev_priv->render_ring);
d1b851fc
ZN		 5039
5040 if (HAS_BSD(dev))
5041 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
31169714
CW		 5042
5043 list_for_each_entry_safe(obj_priv, next_obj,
5044 &dev_priv->mm.inactive_list,
5045 list) {
5046 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 5047 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5048 if (--nr_to_scan <= 0)
5049 break;
5050 }
5051 }
5052
5053 spin_lock(&shrink_list_lock);
5054 mutex_unlock(&dev->struct_mutex);
5055
963b4836
CW		 5056 would_deadlock = 0;
5057
31169714
CW		 5058 if (nr_to_scan <= 0)
5059 break;
5060 }
5061
5062 /* second pass, evict/count anything still on the inactive list */
5063 list_for_each_entry_safe(dev_priv, next_dev,
5064 &shrink_list, mm.shrink_list) {
5065 struct drm_device *dev = dev_priv->dev;
5066
5067 if (! mutex_trylock(&dev->struct_mutex))
5068 continue;
5069
5070 spin_unlock(&shrink_list_lock);
5071
5072 list_for_each_entry_safe(obj_priv, next_obj,
5073 &dev_priv->mm.inactive_list,
5074 list) {
5075 if (nr_to_scan > 0) {
a8089e84 5076 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5077 nr_to_scan--;
5078 } else
5079 cnt++;
5080 }
5081
5082 spin_lock(&shrink_list_lock);
5083 mutex_unlock(&dev->struct_mutex);
5084
5085 would_deadlock = 0;
5086 }
5087
1637ef41
CW		 5088 if (nr_to_scan) {
5089 int active = 0;
5090
5091 /*
5092 * We are desperate for pages, so as a last resort, wait
5093 * for the GPU to finish and discard whatever we can.
5094 * This has a dramatic impact to reduce the number of
5095 * OOM-killer events whilst running the GPU aggressively.
5096 */
5097 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5098 struct drm_device *dev = dev_priv->dev;
5099
5100 if (!mutex_trylock(&dev->struct_mutex))
5101 continue;
5102
5103 spin_unlock(&shrink_list_lock);
5104
5105 if (i915_gpu_is_active(dev)) {
5106 i915_gpu_idle(dev);
5107 active++;
5108 }
5109
5110 spin_lock(&shrink_list_lock);
5111 mutex_unlock(&dev->struct_mutex);
5112 }
5113
5114 if (active)
5115 goto rescan;
5116 }
5117
31169714
CW		 5118 spin_unlock(&shrink_list_lock);
5119
5120 if (would_deadlock)
5121 return -1;
5122 else if (cnt > 0)
5123 return (cnt / 100) * sysctl_vfs_cache_pressure;
5124 else
5125 return 0;
5126}
5127
5128static struct shrinker shrinker = {
5129 .shrink = i915_gem_shrink,
5130 .seeks = DEFAULT_SEEKS,
5131};
5132
5133__init void
5134i915_gem_shrinker_init(void)
5135{
5136 register_shrinker(&shrinker);
5137}
5138
5139__exit void
5140i915_gem_shrinker_exit(void)
5141{
5142 unregister_shrinker(&shrinker);
5143}
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