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drm/i915: framebuffer compression for GM45+
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
585fb111 33#include "i915_reg.h"
79e53945 34#include "intel_bios.h"
0839ccb8 35#include <linux/io-mapping.h>
585fb111 36
1da177e4
LT		 37/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
673a394b 44#define DRIVER_DATE "20080730"
1da177e4 45
317c35d1
JB		 46enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
80824003
JB		 51enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54};
55
52440211
KP		 56#define I915_NUM_PIPE 2
57
1da177e4
LT		 58/* Interface history:
59 *
60 * 1.1: Original.
0d6aa60b
DA		 61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
de227f5f 63 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 64 * 1.5: Add vblank pipe configuration
2228ed67
MD		 65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
1da177e4
LT		 67 */
68#define DRIVER_MAJOR 1
2228ed67 69#define DRIVER_MINOR 6
1da177e4
LT		 70#define DRIVER_PATCHLEVEL 0
71
673a394b
EA		 72#define WATCH_COHERENCY 0
73#define WATCH_BUF 0
74#define WATCH_EXEC 0
75#define WATCH_LRU 0
76#define WATCH_RELOC 0
77#define WATCH_INACTIVE 0
78#define WATCH_PWRITE 0
79
71acb5eb
DA		 80#define I915_GEM_PHYS_CURSOR_0 1
81#define I915_GEM_PHYS_CURSOR_1 2
82#define I915_GEM_PHYS_OVERLAY_REGS 3
83#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90};
91
1da177e4 92typedef struct _drm_i915_ring_buffer {
1da177e4
LT		 93 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
673a394b 99 struct drm_gem_object *ring_obj;
1da177e4
LT		 100} drm_i915_ring_buffer_t;
101
102struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
6c340eac 107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 108};
109
0a3e67a4
JB		 110struct opregion_header;
111struct opregion_acpi;
112struct opregion_swsci;
113struct opregion_asle;
114
8ee1c3db
MG		 115struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121};
122
7c1c2871
DA		 123struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126};
de151cf6
JB		 127#define I915_FENCE_REG_NONE -1
128
129struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131};
7c1c2871 132
9b9d172d 133struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138};
139
63eeaf38
JB		 140struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
153 struct timeval time;
154};
155
e70236a8
JB		 156struct drm_i915_display_funcs {
157 void (*dpms)(struct drm_crtc *crtc, int mode);
158 bool (*fbc_enabled)(struct drm_crtc *crtc);
159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
160 void (*disable_fbc)(struct drm_device *dev);
161 int (*get_display_clock_speed)(struct drm_device *dev);
162 int (*get_fifo_size)(struct drm_device *dev, int plane);
163 void (*update_wm)(struct drm_device *dev, int planea_clock,
164 int planeb_clock, int sr_hdisplay, int pixel_size);
165 /* clock updates for mode set */
166 /* cursor updates */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
171};
172
1da177e4 173typedef struct drm_i915_private {
673a394b
EA		 174 struct drm_device *dev;
175
ac5c4e76
DA		 176 int has_gem;
177
3043c60c 178 void __iomem *regs;
1da177e4 179
ec2a4c3f 180 struct pci_dev *bridge_dev;
1da177e4
LT		 181 drm_i915_ring_buffer_t ring;
182
9c8da5eb 183 drm_dma_handle_t *status_page_dmah;
1da177e4 184 void *hw_status_page;
1da177e4 185 dma_addr_t dma_status_page;
0a3e67a4 186 uint32_t counter;
dc7a9319
WZ		 187 unsigned int status_gfx_addr;
188 drm_local_map_t hws_map;
673a394b 189 struct drm_gem_object *hws_obj;
1da177e4 190
d7658989
JB		 191 struct resource mch_res;
192
a6b54f3f 193 unsigned int cpp;
1da177e4
LT		 194 int back_offset;
195 int front_offset;
196 int current_page;
197 int page_flipping;
1da177e4
LT		 198
199 wait_queue_head_t irq_queue;
200 atomic_t irq_received;
ed4cb414
EA		 201 /** Protects user_irq_refcount and irq_mask_reg */
202 spinlock_t user_irq_lock;
203 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
204 int user_irq_refcount;
205 /** Cached value of IMR to avoid reads in updating the bitfield */
206 u32 irq_mask_reg;
7c463586 207 u32 pipestat[2];
036a4a7d
ZW		 208 /** splitted irq regs for graphics and display engine on IGDNG,
209 irq_mask_reg is still used for display irq. */
210 u32 gt_irq_mask_reg;
211 u32 gt_irq_enable_reg;
212 u32 de_irq_enable_reg;
1da177e4 213
5ca58282
JB		 214 u32 hotplug_supported_mask;
215 struct work_struct hotplug_work;
216
1da177e4
LT		 217 int tex_lru_log_granularity;
218 int allow_batchbuffer;
219 struct mem_block *agp_heap;
0d6aa60b 220 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
702880f2 221 int vblank_pipe;
a6b54f3f 222
f65d9421
BG		 223 /* For hangcheck timer */
224#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
225 struct timer_list hangcheck_timer;
226 int hangcheck_count;
227 uint32_t last_acthd;
228
79e53945
JB		 229 bool cursor_needs_physical;
230
231 struct drm_mm vram;
232
80824003
JB		 233 unsigned long cfb_size;
234 unsigned long cfb_pitch;
235 int cfb_fence;
236 int cfb_plane;
237
79e53945
JB		 238 int irq_enabled;
239
8ee1c3db
MG		 240 struct intel_opregion opregion;
241
79e53945
JB		 242 /* LVDS info */
243 int backlight_duty_cycle; /* restore backlight to this value */
244 bool panel_wants_dither;
245 struct drm_display_mode *panel_fixed_mode;
88631706
ML		 246 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
247 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
79e53945
JB		 248
249 /* Feature bits from the VBIOS */
95281e35
HE		 250 unsigned int int_tv_support:1;
251 unsigned int lvds_dither:1;
252 unsigned int lvds_vbt:1;
253 unsigned int int_crt_support:1;
43565a06 254 unsigned int lvds_use_ssc:1;
32f9d658 255 unsigned int edp_support:1;
43565a06 256 int lvds_ssc_freq;
79e53945 257
c1c7af60
JB		 258 struct notifier_block lid_notifier;
259
db545019 260 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
de151cf6
JB		 261 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
262 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
263 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
264
7662c8bd
SL		 265 unsigned int fsb_freq, mem_freq;
266
63eeaf38
JB		 267 spinlock_t error_lock;
268 struct drm_i915_error_state *first_error;
8a905236 269 struct work_struct error_work;
9c9fe1f8 270 struct workqueue_struct *wq;
63eeaf38 271
e70236a8
JB		 272 /* Display functions */
273 struct drm_i915_display_funcs display;
274
ba8bbcf6 275 /* Register state */
06891e27 276 bool suspended;
ba8bbcf6
JB		 277 u8 saveLBB;
278 u32 saveDSPACNTR;
279 u32 saveDSPBCNTR;
e948e994 280 u32 saveDSPARB;
881ee988 281 u32 saveRENDERSTANDBY;
461cba2d 282 u32 saveHWS;
ba8bbcf6
JB		 283 u32 savePIPEACONF;
284 u32 savePIPEBCONF;
285 u32 savePIPEASRC;
286 u32 savePIPEBSRC;
287 u32 saveFPA0;
288 u32 saveFPA1;
289 u32 saveDPLL_A;
290 u32 saveDPLL_A_MD;
291 u32 saveHTOTAL_A;
292 u32 saveHBLANK_A;
293 u32 saveHSYNC_A;
294 u32 saveVTOTAL_A;
295 u32 saveVBLANK_A;
296 u32 saveVSYNC_A;
297 u32 saveBCLRPAT_A;
0da3ea12 298 u32 savePIPEASTAT;
ba8bbcf6
JB		 299 u32 saveDSPASTRIDE;
300 u32 saveDSPASIZE;
301 u32 saveDSPAPOS;
585fb111 302 u32 saveDSPAADDR;
ba8bbcf6
JB		 303 u32 saveDSPASURF;
304 u32 saveDSPATILEOFF;
305 u32 savePFIT_PGM_RATIOS;
306 u32 saveBLC_PWM_CTL;
307 u32 saveBLC_PWM_CTL2;
308 u32 saveFPB0;
309 u32 saveFPB1;
310 u32 saveDPLL_B;
311 u32 saveDPLL_B_MD;
312 u32 saveHTOTAL_B;
313 u32 saveHBLANK_B;
314 u32 saveHSYNC_B;
315 u32 saveVTOTAL_B;
316 u32 saveVBLANK_B;
317 u32 saveVSYNC_B;
318 u32 saveBCLRPAT_B;
0da3ea12 319 u32 savePIPEBSTAT;
ba8bbcf6
JB		 320 u32 saveDSPBSTRIDE;
321 u32 saveDSPBSIZE;
322 u32 saveDSPBPOS;
585fb111 323 u32 saveDSPBADDR;
ba8bbcf6
JB		 324 u32 saveDSPBSURF;
325 u32 saveDSPBTILEOFF;
585fb111
JB		 326 u32 saveVGA0;
327 u32 saveVGA1;
328 u32 saveVGA_PD;
ba8bbcf6
JB		 329 u32 saveVGACNTRL;
330 u32 saveADPA;
331 u32 saveLVDS;
585fb111
JB		 332 u32 savePP_ON_DELAYS;
333 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 334 u32 saveDVOA;
335 u32 saveDVOB;
336 u32 saveDVOC;
337 u32 savePP_ON;
338 u32 savePP_OFF;
339 u32 savePP_CONTROL;
585fb111 340 u32 savePP_DIVISOR;
ba8bbcf6
JB		 341 u32 savePFIT_CONTROL;
342 u32 save_palette_a[256];
343 u32 save_palette_b[256];
344 u32 saveFBC_CFB_BASE;
345 u32 saveFBC_LL_BASE;
346 u32 saveFBC_CONTROL;
347 u32 saveFBC_CONTROL2;
0da3ea12
JB		 348 u32 saveIER;
349 u32 saveIIR;
350 u32 saveIMR;
1f84e550 351 u32 saveCACHE_MODE_0;
e948e994 352 u32 saveD_STATE;
652c393a 353 u32 saveDSPCLK_GATE_D;
1f84e550 354 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 355 u32 saveSWF0[16];
356 u32 saveSWF1[16];
357 u32 saveSWF2[3];
358 u8 saveMSR;
359 u8 saveSR[8];
123f794f 360 u8 saveGR[25];
ba8bbcf6 361 u8 saveAR_INDEX;
a59e122a 362 u8 saveAR[21];
ba8bbcf6 363 u8 saveDACMASK;
a59e122a 364 u8 saveCR[37];
79f11c19 365 uint64_t saveFENCE[16];
1fd1c624
EA		 366 u32 saveCURACNTR;
367 u32 saveCURAPOS;
368 u32 saveCURABASE;
369 u32 saveCURBCNTR;
370 u32 saveCURBPOS;
371 u32 saveCURBBASE;
372 u32 saveCURSIZE;
a4fc5ed6
KP		 373 u32 saveDP_B;
374 u32 saveDP_C;
375 u32 saveDP_D;
376 u32 savePIPEA_GMCH_DATA_M;
377 u32 savePIPEB_GMCH_DATA_M;
378 u32 savePIPEA_GMCH_DATA_N;
379 u32 savePIPEB_GMCH_DATA_N;
380 u32 savePIPEA_DP_LINK_M;
381 u32 savePIPEB_DP_LINK_M;
382 u32 savePIPEA_DP_LINK_N;
383 u32 savePIPEB_DP_LINK_N;
673a394b
EA		 384
385 struct {
386 struct drm_mm gtt_space;
387
0839ccb8 388 struct io_mapping *gtt_mapping;
ab657db1 389 int gtt_mtrr;
0839ccb8 390
31169714
CW		 391 /**
392 * Membership on list of all loaded devices, used to evict
393 * inactive buffers under memory pressure.
394 *
395 * Modifications should only be done whilst holding the
396 * shrink_list_lock spinlock.
397 */
398 struct list_head shrink_list;
399
673a394b
EA		 400 /**
401 * List of objects currently involved in rendering from the
402 * ringbuffer.
403 *
ce44b0ea
EA		 404 * Includes buffers having the contents of their GPU caches
405 * flushed, not necessarily primitives. last_rendering_seqno
406 * represents when the rendering involved will be completed.
407 *
673a394b
EA		 408 * A reference is held on the buffer while on this list.
409 */
5e118f41 410 spinlock_t active_list_lock;
673a394b
EA		 411 struct list_head active_list;
412
413 /**
414 * List of objects which are not in the ringbuffer but which
415 * still have a write_domain which needs to be flushed before
416 * unbinding.
417 *
ce44b0ea
EA		 418 * last_rendering_seqno is 0 while an object is in this list.
419 *
673a394b
EA		 420 * A reference is held on the buffer while on this list.
421 */
422 struct list_head flushing_list;
423
424 /**
425 * LRU list of objects which are not in the ringbuffer and
426 * are ready to unbind, but are still in the GTT.
427 *
ce44b0ea
EA		 428 * last_rendering_seqno is 0 while an object is in this list.
429 *
673a394b
EA		 430 * A reference is not held on the buffer while on this list,
431 * as merely being GTT-bound shouldn't prevent its being
432 * freed, and we'll pull it off the list in the free path.
433 */
434 struct list_head inactive_list;
435
a09ba7fa
EA		 436 /** LRU list of objects with fence regs on them. */
437 struct list_head fence_list;
438
673a394b
EA		 439 /**
440 * List of breadcrumbs associated with GPU requests currently
441 * outstanding.
442 */
443 struct list_head request_list;
444
445 /**
446 * We leave the user IRQ off as much as possible,
447 * but this means that requests will finish and never
448 * be retired once the system goes idle. Set a timer to
449 * fire periodically while the ring is running. When it
450 * fires, go retire requests.
451 */
452 struct delayed_work retire_work;
453
454 uint32_t next_gem_seqno;
455
456 /**
457 * Waiting sequence number, if any
458 */
459 uint32_t waiting_gem_seqno;
460
461 /**
462 * Last seq seen at irq time
463 */
464 uint32_t irq_gem_seqno;
465
466 /**
467 * Flag if the X Server, and thus DRM, is not currently in
468 * control of the device.
469 *
470 * This is set between LeaveVT and EnterVT. It needs to be
471 * replaced with a semaphore. It also needs to be
472 * transitioned away from for kernel modesetting.
473 */
474 int suspended;
475
476 /**
477 * Flag if the hardware appears to be wedged.
478 *
479 * This is set when attempts to idle the device timeout.
480 * It prevents command submission from occuring and makes
481 * every pending request fail
482 */
ba1234d1 483 atomic_t wedged;
673a394b
EA		 484
485 /** Bit 6 swizzling required for X tiling */
486 uint32_t bit_6_swizzle_x;
487 /** Bit 6 swizzling required for Y tiling */
488 uint32_t bit_6_swizzle_y;
71acb5eb
DA		 489
490 /* storage for physical objects */
491 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
673a394b 492 } mm;
9b9d172d 493 struct sdvo_device_mapping sdvo_mappings[2];
652c393a
JB		 494
495 /* Reclocking support */
496 bool render_reclock_avail;
497 bool lvds_downclock_avail;
498 struct work_struct idle_work;
499 struct timer_list idle_timer;
500 bool busy;
501 u16 orig_clock;
1da177e4
LT		 502} drm_i915_private_t;
503
673a394b
EA		 504/** driver private structure attached to each drm_gem_object */
505struct drm_i915_gem_object {
506 struct drm_gem_object *obj;
507
508 /** Current space allocated to this object in the GTT, if any. */
509 struct drm_mm_node *gtt_space;
510
511 /** This object's place on the active/flushing/inactive lists */
512 struct list_head list;
513
a09ba7fa
EA		 514 /** This object's place on the fenced object LRU */
515 struct list_head fence_list;
516
673a394b
EA		 517 /**
518 * This is set if the object is on the active or flushing lists
519 * (has pending rendering), and is not set if it's on inactive (ready
520 * to be unbound).
521 */
522 int active;
523
524 /**
525 * This is set if the object has been written to since last bound
526 * to the GTT
527 */
528 int dirty;
529
530 /** AGP memory structure for our GTT binding. */
531 DRM_AGP_MEM *agp_mem;
532
856fa198
EA		 533 struct page **pages;
534 int pages_refcount;
673a394b
EA		 535
536 /**
537 * Current offset of the object in GTT space.
538 *
539 * This is the same as gtt_space->start
540 */
541 uint32_t gtt_offset;
e67b8ce1 542
de151cf6
JB		 543 /**
544 * Fake offset for use by mmap(2)
545 */
546 uint64_t mmap_offset;
547
548 /**
549 * Fence register bits (if any) for this object. Will be set
550 * as needed when mapped into the GTT.
551 * Protected by dev->struct_mutex.
552 */
553 int fence_reg;
673a394b 554
673a394b
EA		 555 /** How many users have pinned this object in GTT space */
556 int pin_count;
557
558 /** Breadcrumb of last rendering to the buffer. */
559 uint32_t last_rendering_seqno;
560
561 /** Current tiling mode for the object. */
562 uint32_t tiling_mode;
de151cf6 563 uint32_t stride;
673a394b 564
280b713b
EA		 565 /** Record of address bit 17 of each page at last unbind. */
566 long *bit_17;
567
ba1eb1d8
KP		 568 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
569 uint32_t agp_type;
570
673a394b 571 /**
e47c68e9
EA		 572 * If present, while GEM_DOMAIN_CPU is in the read domain this array
573 * flags which individual pages are valid.
673a394b
EA		 574 */
575 uint8_t *page_cpu_valid;
79e53945
JB		 576
577 /** User space pin count and filp owning the pin */
578 uint32_t user_pin_count;
579 struct drm_file *pin_filp;
71acb5eb
DA		 580
581 /** for phy allocated objects */
582 struct drm_i915_gem_phys_object *phys_obj;
b70d11da
KH		 583
584 /**
585 * Used for checking the object doesn't appear more than once
586 * in an execbuffer object list.
587 */
588 int in_execbuffer;
3ef94daa
CW		 589
590 /**
591 * Advice: are the backing pages purgeable?
592 */
593 int madv;
673a394b
EA		 594};
595
596/**
597 * Request queue structure.
598 *
599 * The request queue allows us to note sequence numbers that have been emitted
600 * and may be associated with active buffers to be retired.
601 *
602 * By keeping this list, we can avoid having to do questionable
603 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
604 * an emission time with seqnos for tracking how far ahead of the GPU we are.
605 */
606struct drm_i915_gem_request {
607 /** GEM sequence number associated with this request. */
608 uint32_t seqno;
609
610 /** Time at which this request was emitted, in jiffies. */
611 unsigned long emitted_jiffies;
612
b962442e 613 /** global list entry for this request */
673a394b 614 struct list_head list;
b962442e
EA		 615
616 /** file_priv list entry for this request */
617 struct list_head client_list;
673a394b
EA		 618};
619
620struct drm_i915_file_private {
621 struct {
b962442e 622 struct list_head request_list;
673a394b
EA		 623 } mm;
624};
625
79e53945
JB		 626enum intel_chip_family {
627 CHIP_I8XX = 0x01,
628 CHIP_I9XX = 0x02,
629 CHIP_I915 = 0x04,
630 CHIP_I965 = 0x08,
631};
632
c153f45f 633extern struct drm_ioctl_desc i915_ioctls[];
b3a83639 634extern int i915_max_ioctl;
79e53945 635extern unsigned int i915_fbpercrtc;
652c393a 636extern unsigned int i915_powersave;
b3a83639 637
1341d655
BG		 638extern void i915_save_display(struct drm_device *dev);
639extern void i915_restore_display(struct drm_device *dev);
7c1c2871
DA		 640extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
641extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
642
1da177e4 643 /* i915_dma.c */
84b1fd10 644extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 645extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 646extern int i915_driver_unload(struct drm_device *);
673a394b 647extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
84b1fd10 648extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac
EA		 649extern void i915_driver_preclose(struct drm_device *dev,
650 struct drm_file *file_priv);
673a394b
EA		 651extern void i915_driver_postclose(struct drm_device *dev,
652 struct drm_file *file_priv);
84b1fd10 653extern int i915_driver_device_is_agp(struct drm_device * dev);
0d6aa60b
DA		 654extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
655 unsigned long arg);
673a394b 656extern int i915_emit_box(struct drm_device *dev,
201361a5 657 struct drm_clip_rect *boxes,
673a394b 658 int i, int DR1, int DR4);
11ed50ec 659extern int i965_reset(struct drm_device *dev, u8 flags);
af6061af 660
1da177e4 661/* i915_irq.c */
f65d9421 662void i915_hangcheck_elapsed(unsigned long data);
c153f45f
EA		 663extern int i915_irq_emit(struct drm_device *dev, void *data,
664 struct drm_file *file_priv);
665extern int i915_irq_wait(struct drm_device *dev, void *data,
666 struct drm_file *file_priv);
673a394b
EA		 667void i915_user_irq_get(struct drm_device *dev);
668void i915_user_irq_put(struct drm_device *dev);
79e53945 669extern void i915_enable_interrupt (struct drm_device *dev);
1da177e4
LT		 670
671extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 672extern void i915_driver_irq_preinstall(struct drm_device * dev);
0a3e67a4 673extern int i915_driver_irq_postinstall(struct drm_device *dev);
84b1fd10 674extern void i915_driver_irq_uninstall(struct drm_device * dev);
c153f45f
EA		 675extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
676 struct drm_file *file_priv);
677extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
0a3e67a4
JB		 679extern int i915_enable_vblank(struct drm_device *dev, int crtc);
680extern void i915_disable_vblank(struct drm_device *dev, int crtc);
681extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
9880b7a5 682extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
c153f45f
EA		 683extern int i915_vblank_swap(struct drm_device *dev, void *data,
684 struct drm_file *file_priv);
8ee1c3db 685extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1da177e4 686
7c463586
KP		 687void
688i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
689
690void
691i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
692
693
1da177e4 694/* i915_mem.c */
c153f45f
EA		 695extern int i915_mem_alloc(struct drm_device *dev, void *data,
696 struct drm_file *file_priv);
697extern int i915_mem_free(struct drm_device *dev, void *data,
698 struct drm_file *file_priv);
699extern int i915_mem_init_heap(struct drm_device *dev, void *data,
700 struct drm_file *file_priv);
701extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
702 struct drm_file *file_priv);
1da177e4 703extern void i915_mem_takedown(struct mem_block **heap);
84b1fd10 704extern void i915_mem_release(struct drm_device * dev,
6c340eac 705 struct drm_file *file_priv, struct mem_block *heap);
673a394b
EA		 706/* i915_gem.c */
707int i915_gem_init_ioctl(struct drm_device *dev, void *data,
708 struct drm_file *file_priv);
709int i915_gem_create_ioctl(struct drm_device *dev, void *data,
710 struct drm_file *file_priv);
711int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
712 struct drm_file *file_priv);
713int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
714 struct drm_file *file_priv);
715int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
716 struct drm_file *file_priv);
de151cf6
JB		 717int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
718 struct drm_file *file_priv);
673a394b
EA		 719int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
720 struct drm_file *file_priv);
721int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
722 struct drm_file *file_priv);
723int i915_gem_execbuffer(struct drm_device *dev, void *data,
724 struct drm_file *file_priv);
725int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
726 struct drm_file *file_priv);
727int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
728 struct drm_file *file_priv);
729int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
730 struct drm_file *file_priv);
731int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
732 struct drm_file *file_priv);
3ef94daa
CW		 733int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
734 struct drm_file *file_priv);
673a394b
EA		 735int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
736 struct drm_file *file_priv);
737int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
738 struct drm_file *file_priv);
739int i915_gem_set_tiling(struct drm_device *dev, void *data,
740 struct drm_file *file_priv);
741int i915_gem_get_tiling(struct drm_device *dev, void *data,
742 struct drm_file *file_priv);
5a125c3c
EA		 743int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *file_priv);
673a394b 745void i915_gem_load(struct drm_device *dev);
673a394b
EA		 746int i915_gem_init_object(struct drm_gem_object *obj);
747void i915_gem_free_object(struct drm_gem_object *obj);
748int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
749void i915_gem_object_unpin(struct drm_gem_object *obj);
0f973f27 750int i915_gem_object_unbind(struct drm_gem_object *obj);
d05ca301 751void i915_gem_release_mmap(struct drm_gem_object *obj);
673a394b
EA		 752void i915_gem_lastclose(struct drm_device *dev);
753uint32_t i915_get_gem_seqno(struct drm_device *dev);
22be1724 754bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
8c4b8c3f 755int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
52dc7d32 756int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
673a394b
EA		 757void i915_gem_retire_requests(struct drm_device *dev);
758void i915_gem_retire_work_handler(struct work_struct *work);
759void i915_gem_clflush_object(struct drm_gem_object *obj);
79e53945
JB		 760int i915_gem_object_set_domain(struct drm_gem_object *obj,
761 uint32_t read_domains,
762 uint32_t write_domain);
763int i915_gem_init_ringbuffer(struct drm_device *dev);
764void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
765int i915_gem_do_init(struct drm_device *dev, unsigned long start,
766 unsigned long end);
5669fcac 767int i915_gem_idle(struct drm_device *dev);
de151cf6 768int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
79e53945
JB		 769int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
770 int write);
71acb5eb
DA		 771int i915_gem_attach_phys_object(struct drm_device *dev,
772 struct drm_gem_object *obj, int id);
773void i915_gem_detach_phys_object(struct drm_device *dev,
774 struct drm_gem_object *obj);
775void i915_gem_free_all_phys_object(struct drm_device *dev);
6911a9b8
BG		 776int i915_gem_object_get_pages(struct drm_gem_object *obj);
777void i915_gem_object_put_pages(struct drm_gem_object *obj);
1fd1c624 778void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
673a394b 779
31169714
CW		 780void i915_gem_shrinker_init(void);
781void i915_gem_shrinker_exit(void);
782
673a394b
EA		 783/* i915_gem_tiling.c */
784void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
280b713b
EA		 785void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
786void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
673a394b
EA		 787
788/* i915_gem_debug.c */
789void i915_gem_dump_object(struct drm_gem_object *obj, int len,
790 const char *where, uint32_t mark);
791#if WATCH_INACTIVE
792void i915_verify_inactive(struct drm_device *dev, char *file, int line);
793#else
794#define i915_verify_inactive(dev, file, line)
795#endif
796void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
797void i915_gem_dump_object(struct drm_gem_object *obj, int len,
798 const char *where, uint32_t mark);
799void i915_dump_lru(struct drm_device *dev, const char *where);
1da177e4 800
2017263e 801/* i915_debugfs.c */
27c202ad
BG		 802int i915_debugfs_init(struct drm_minor *minor);
803void i915_debugfs_cleanup(struct drm_minor *minor);
2017263e 804
317c35d1
JB		 805/* i915_suspend.c */
806extern int i915_save_state(struct drm_device *dev);
807extern int i915_restore_state(struct drm_device *dev);
0a3e67a4
JB		 808
809/* i915_suspend.c */
810extern int i915_save_state(struct drm_device *dev);
811extern int i915_restore_state(struct drm_device *dev);
317c35d1 812
65e082c9 813#ifdef CONFIG_ACPI
8ee1c3db 814/* i915_opregion.c */
74a365b3 815extern int intel_opregion_init(struct drm_device *dev, int resume);
3b1c1c11 816extern void intel_opregion_free(struct drm_device *dev, int suspend);
8ee1c3db
MG		 817extern void opregion_asle_intr(struct drm_device *dev);
818extern void opregion_enable_asle(struct drm_device *dev);
65e082c9 819#else
03ae61dd 820static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
3b1c1c11 821static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
65e082c9
LB		 822static inline void opregion_asle_intr(struct drm_device *dev) { return; }
823static inline void opregion_enable_asle(struct drm_device *dev) { return; }
824#endif
8ee1c3db 825
79e53945
JB		 826/* modesetting */
827extern void intel_modeset_init(struct drm_device *dev);
828extern void intel_modeset_cleanup(struct drm_device *dev);
80824003 829extern void i8xx_disable_fbc(struct drm_device *dev);
74dff282 830extern void g4x_disable_fbc(struct drm_device *dev);
79e53945 831
546b0974
EA		 832/**
833 * Lock test for when it's just for synchronization of ring access.
834 *
835 * In that case, we don't need to do it when GEM is initialized as nobody else
836 * has access to the ring.
837 */
838#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
839 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
840 LOCK_TEST_WITH_RETURN(dev, file_priv); \
841} while (0)
842
3043c60c
EA		 843#define I915_READ(reg) readl(dev_priv->regs + (reg))
844#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
845#define I915_READ16(reg) readw(dev_priv->regs + (reg))
846#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
847#define I915_READ8(reg) readb(dev_priv->regs + (reg))
848#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
de151cf6 849#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
049ef7e4 850#define I915_READ64(reg) readq(dev_priv->regs + (reg))
7d57382e 851#define POSTING_READ(reg) (void)I915_READ(reg)
1da177e4
LT		 852
853#define I915_VERBOSE 0
854
0ef82af7
CW		 855#define RING_LOCALS volatile unsigned int *ring_virt__;
856
857#define BEGIN_LP_RING(n) do { \
858 int bytes__ = 4*(n); \
859 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
860 /* a wrap must occur between instructions so pad beforehand */ \
861 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
862 i915_wrap_ring(dev); \
863 if (unlikely (dev_priv->ring.space < bytes__)) \
864 i915_wait_ring(dev, bytes__, __func__); \
865 ring_virt__ = (unsigned int *) \
866 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
867 dev_priv->ring.tail += bytes__; \
868 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
869 dev_priv->ring.space -= bytes__; \
1da177e4
LT		 870} while (0)
871
0ef82af7 872#define OUT_RING(n) do { \
1da177e4 873 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
0ef82af7 874 *ring_virt__++ = (n); \
1da177e4
LT		 875} while (0)
876
877#define ADVANCE_LP_RING() do { \
0ef82af7
CW		 878 if (I915_VERBOSE) \
879 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
880 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1da177e4
LT		 881} while(0)
882
ba8bbcf6 883/**
585fb111
JB		 884 * Reads a dword out of the status page, which is written to from the command
885 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
886 * MI_STORE_DATA_IMM.
ba8bbcf6 887 *
585fb111 888 * The following dwords have a reserved meaning:
0cdad7e8
KP		 889 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
890 * 0x04: ring 0 head pointer
891 * 0x05: ring 1 head pointer (915-class)
892 * 0x06: ring 2 head pointer (915-class)
893 * 0x10-0x1b: Context status DWords (GM45)
894 * 0x1f: Last written status offset. (GM45)
ba8bbcf6 895 *
0cdad7e8 896 * The area from dword 0x20 to 0x3ff is available for driver usage.
ba8bbcf6 897 */
585fb111 898#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
0baf823a 899#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
0cdad7e8 900#define I915_GEM_HWS_INDEX 0x20
0baf823a 901#define I915_BREADCRUMB_INDEX 0x21
ba8bbcf6 902
0ef82af7 903extern int i915_wrap_ring(struct drm_device * dev);
585fb111 904extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
ba8bbcf6
JB		 905
906#define IS_I830(dev) ((dev)->pci_device == 0x3577)
907#define IS_845G(dev) ((dev)->pci_device == 0x2562)
908#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
909#define IS_I855(dev) ((dev)->pci_device == 0x3582)
910#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
911
4d1f7888 912#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
ba8bbcf6
JB		 913#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
914#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
3bf48468
JB		 915#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
916 (dev)->pci_device == 0x27AE)
ba8bbcf6
JB		 917#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
918 (dev)->pci_device == 0x2982 || \
919 (dev)->pci_device == 0x2992 || \
920 (dev)->pci_device == 0x29A2 || \
921 (dev)->pci_device == 0x2A02 || \
5f5f9d4c 922 (dev)->pci_device == 0x2A12 || \
d3adbc0c
ZW		 923 (dev)->pci_device == 0x2A42 || \
924 (dev)->pci_device == 0x2E02 || \
925 (dev)->pci_device == 0x2E12 || \
72021788 926 (dev)->pci_device == 0x2E22 || \
280da227 927 (dev)->pci_device == 0x2E32 || \
7839c5d5 928 (dev)->pci_device == 0x2E42 || \
280da227
ZW		 929 (dev)->pci_device == 0x0042 || \
930 (dev)->pci_device == 0x0046)
ba8bbcf6 931
c9ed4486
ML		 932#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
933 (dev)->pci_device == 0x2A12)
ba8bbcf6 934
b9bfdfe6 935#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
5f5f9d4c 936
d3adbc0c
ZW		 937#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
938 (dev)->pci_device == 0x2E12 || \
60fd99e3 939 (dev)->pci_device == 0x2E22 || \
72021788 940 (dev)->pci_device == 0x2E32 || \
7839c5d5 941 (dev)->pci_device == 0x2E42 || \
60fd99e3 942 IS_GM45(dev))
d3adbc0c 943
2177832f
SL		 944#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
945#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
946#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
947
ba8bbcf6
JB		 948#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
949 (dev)->pci_device == 0x29B2 || \
2177832f
SL		 950 (dev)->pci_device == 0x29D2 || \
951 (IS_IGD(dev)))
ba8bbcf6 952
280da227
ZW		 953#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
954#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
955#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
956
ba8bbcf6 957#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
280da227
ZW		 958 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
959 IS_IGDNG(dev))
ba8bbcf6
JB		 960
961#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
2177832f 962 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
280da227 963 IS_IGD(dev) || IS_IGDNG_M(dev))
ba8bbcf6 964
280da227
ZW		 965#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
966 IS_IGDNG(dev))
0f973f27
JB		 967/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
968 * rows, which changed the alignment requirements and fence programming.
969 */
970#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
971 IS_I915GM(dev)))
280da227 972#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
a4fc5ed6 973#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
32f9d658 974#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
af729a26 975#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
7662c8bd 976/* dsparb controlled by hw only */
22bd50c5 977#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
b39d50e5 978
652c393a
JB		 979#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
980#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
c1a1cdc1 981#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)))
652c393a 982
ba8bbcf6 983#define PRIMARY_RINGBUFFER_SIZE (128*1024)
0d6aa60b 984
1da177e4 985#endif
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