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drm/i915: implement fastpath for overlay flip waiting
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
585fb111 33#include "i915_reg.h"
79e53945 34#include "intel_bios.h"
0839ccb8 35#include <linux/io-mapping.h>
585fb111 36
1da177e4
LT		 37/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
673a394b 44#define DRIVER_DATE "20080730"
1da177e4 45
317c35d1
JB		 46enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
80824003
JB		 51enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54};
55
52440211
KP		 56#define I915_NUM_PIPE 2
57
1da177e4
LT		 58/* Interface history:
59 *
60 * 1.1: Original.
0d6aa60b
DA		 61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
de227f5f 63 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 64 * 1.5: Add vblank pipe configuration
2228ed67
MD		 65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
1da177e4
LT		 67 */
68#define DRIVER_MAJOR 1
2228ed67 69#define DRIVER_MINOR 6
1da177e4
LT		 70#define DRIVER_PATCHLEVEL 0
71
673a394b
EA		 72#define WATCH_COHERENCY 0
73#define WATCH_BUF 0
74#define WATCH_EXEC 0
75#define WATCH_LRU 0
76#define WATCH_RELOC 0
77#define WATCH_INACTIVE 0
78#define WATCH_PWRITE 0
79
71acb5eb
DA		 80#define I915_GEM_PHYS_CURSOR_0 1
81#define I915_GEM_PHYS_CURSOR_1 2
82#define I915_GEM_PHYS_OVERLAY_REGS 3
83#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90};
91
1da177e4 92typedef struct _drm_i915_ring_buffer {
1da177e4
LT		 93 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
673a394b 99 struct drm_gem_object *ring_obj;
1da177e4
LT		 100} drm_i915_ring_buffer_t;
101
102struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
6c340eac 107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 108};
109
0a3e67a4
JB		 110struct opregion_header;
111struct opregion_acpi;
112struct opregion_swsci;
113struct opregion_asle;
114
8ee1c3db
MG		 115struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121};
122
7c1c2871
DA		 123struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126};
de151cf6
JB		 127#define I915_FENCE_REG_NONE -1
128
129struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131};
7c1c2871 132
9b9d172d 133struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138};
139
63eeaf38
JB		 140struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
153 struct timeval time;
154};
155
e70236a8
JB		 156struct drm_i915_display_funcs {
157 void (*dpms)(struct drm_crtc *crtc, int mode);
158 bool (*fbc_enabled)(struct drm_crtc *crtc);
159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
160 void (*disable_fbc)(struct drm_device *dev);
161 int (*get_display_clock_speed)(struct drm_device *dev);
162 int (*get_fifo_size)(struct drm_device *dev, int plane);
163 void (*update_wm)(struct drm_device *dev, int planea_clock,
164 int planeb_clock, int sr_hdisplay, int pixel_size);
165 /* clock updates for mode set */
166 /* cursor updates */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
171};
172
02e792fb
DV		 173struct intel_overlay;
174
1da177e4 175typedef struct drm_i915_private {
673a394b
EA		 176 struct drm_device *dev;
177
ac5c4e76
DA		 178 int has_gem;
179
3043c60c 180 void __iomem *regs;
1da177e4 181
ec2a4c3f 182 struct pci_dev *bridge_dev;
1da177e4
LT		 183 drm_i915_ring_buffer_t ring;
184
9c8da5eb 185 drm_dma_handle_t *status_page_dmah;
1da177e4 186 void *hw_status_page;
1da177e4 187 dma_addr_t dma_status_page;
0a3e67a4 188 uint32_t counter;
dc7a9319
WZ		 189 unsigned int status_gfx_addr;
190 drm_local_map_t hws_map;
673a394b 191 struct drm_gem_object *hws_obj;
97f5ab66 192 struct drm_gem_object *pwrctx;
1da177e4 193
d7658989
JB		 194 struct resource mch_res;
195
a6b54f3f 196 unsigned int cpp;
1da177e4
LT		 197 int back_offset;
198 int front_offset;
199 int current_page;
200 int page_flipping;
1da177e4
LT		 201
202 wait_queue_head_t irq_queue;
203 atomic_t irq_received;
ed4cb414
EA		 204 /** Protects user_irq_refcount and irq_mask_reg */
205 spinlock_t user_irq_lock;
206 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
207 int user_irq_refcount;
9d34e5db 208 u32 trace_irq_seqno;
ed4cb414
EA		 209 /** Cached value of IMR to avoid reads in updating the bitfield */
210 u32 irq_mask_reg;
7c463586 211 u32 pipestat[2];
036a4a7d
ZW		 212 /** splitted irq regs for graphics and display engine on IGDNG,
213 irq_mask_reg is still used for display irq. */
214 u32 gt_irq_mask_reg;
215 u32 gt_irq_enable_reg;
216 u32 de_irq_enable_reg;
1da177e4 217
5ca58282
JB		 218 u32 hotplug_supported_mask;
219 struct work_struct hotplug_work;
220
1da177e4
LT		 221 int tex_lru_log_granularity;
222 int allow_batchbuffer;
223 struct mem_block *agp_heap;
0d6aa60b 224 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
702880f2 225 int vblank_pipe;
a6b54f3f 226
f65d9421
BG		 227 /* For hangcheck timer */
228#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
229 struct timer_list hangcheck_timer;
230 int hangcheck_count;
231 uint32_t last_acthd;
232
79e53945
JB		 233 bool cursor_needs_physical;
234
235 struct drm_mm vram;
236
80824003
JB		 237 unsigned long cfb_size;
238 unsigned long cfb_pitch;
239 int cfb_fence;
240 int cfb_plane;
241
79e53945
JB		 242 int irq_enabled;
243
8ee1c3db
MG		 244 struct intel_opregion opregion;
245
02e792fb
DV		 246 /* overlay */
247 struct intel_overlay *overlay;
248
79e53945
JB		 249 /* LVDS info */
250 int backlight_duty_cycle; /* restore backlight to this value */
251 bool panel_wants_dither;
252 struct drm_display_mode *panel_fixed_mode;
88631706
ML		 253 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
254 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
79e53945
JB		 255
256 /* Feature bits from the VBIOS */
95281e35
HE		 257 unsigned int int_tv_support:1;
258 unsigned int lvds_dither:1;
259 unsigned int lvds_vbt:1;
260 unsigned int int_crt_support:1;
43565a06 261 unsigned int lvds_use_ssc:1;
32f9d658 262 unsigned int edp_support:1;
43565a06 263 int lvds_ssc_freq;
79e53945 264
c1c7af60
JB		 265 struct notifier_block lid_notifier;
266
db545019 267 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
de151cf6
JB		 268 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
269 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
270 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
271
7662c8bd
SL		 272 unsigned int fsb_freq, mem_freq;
273
63eeaf38
JB		 274 spinlock_t error_lock;
275 struct drm_i915_error_state *first_error;
8a905236 276 struct work_struct error_work;
9c9fe1f8 277 struct workqueue_struct *wq;
63eeaf38 278
e70236a8
JB		 279 /* Display functions */
280 struct drm_i915_display_funcs display;
281
ba8bbcf6 282 /* Register state */
c9354c85 283 bool modeset_on_lid;
ba8bbcf6
JB		 284 u8 saveLBB;
285 u32 saveDSPACNTR;
286 u32 saveDSPBCNTR;
e948e994 287 u32 saveDSPARB;
881ee988 288 u32 saveRENDERSTANDBY;
97f5ab66 289 u32 savePWRCTXA;
461cba2d 290 u32 saveHWS;
ba8bbcf6
JB		 291 u32 savePIPEACONF;
292 u32 savePIPEBCONF;
293 u32 savePIPEASRC;
294 u32 savePIPEBSRC;
295 u32 saveFPA0;
296 u32 saveFPA1;
297 u32 saveDPLL_A;
298 u32 saveDPLL_A_MD;
299 u32 saveHTOTAL_A;
300 u32 saveHBLANK_A;
301 u32 saveHSYNC_A;
302 u32 saveVTOTAL_A;
303 u32 saveVBLANK_A;
304 u32 saveVSYNC_A;
305 u32 saveBCLRPAT_A;
42048781
ZW		 306 u32 saveTRANS_HTOTAL_A;
307 u32 saveTRANS_HBLANK_A;
308 u32 saveTRANS_HSYNC_A;
309 u32 saveTRANS_VTOTAL_A;
310 u32 saveTRANS_VBLANK_A;
311 u32 saveTRANS_VSYNC_A;
0da3ea12 312 u32 savePIPEASTAT;
ba8bbcf6
JB		 313 u32 saveDSPASTRIDE;
314 u32 saveDSPASIZE;
315 u32 saveDSPAPOS;
585fb111 316 u32 saveDSPAADDR;
ba8bbcf6
JB		 317 u32 saveDSPASURF;
318 u32 saveDSPATILEOFF;
319 u32 savePFIT_PGM_RATIOS;
0eb96d6e 320 u32 saveBLC_HIST_CTL;
ba8bbcf6
JB		 321 u32 saveBLC_PWM_CTL;
322 u32 saveBLC_PWM_CTL2;
42048781
ZW		 323 u32 saveBLC_CPU_PWM_CTL;
324 u32 saveBLC_CPU_PWM_CTL2;
ba8bbcf6
JB		 325 u32 saveFPB0;
326 u32 saveFPB1;
327 u32 saveDPLL_B;
328 u32 saveDPLL_B_MD;
329 u32 saveHTOTAL_B;
330 u32 saveHBLANK_B;
331 u32 saveHSYNC_B;
332 u32 saveVTOTAL_B;
333 u32 saveVBLANK_B;
334 u32 saveVSYNC_B;
335 u32 saveBCLRPAT_B;
42048781
ZW		 336 u32 saveTRANS_HTOTAL_B;
337 u32 saveTRANS_HBLANK_B;
338 u32 saveTRANS_HSYNC_B;
339 u32 saveTRANS_VTOTAL_B;
340 u32 saveTRANS_VBLANK_B;
341 u32 saveTRANS_VSYNC_B;
0da3ea12 342 u32 savePIPEBSTAT;
ba8bbcf6
JB		 343 u32 saveDSPBSTRIDE;
344 u32 saveDSPBSIZE;
345 u32 saveDSPBPOS;
585fb111 346 u32 saveDSPBADDR;
ba8bbcf6
JB		 347 u32 saveDSPBSURF;
348 u32 saveDSPBTILEOFF;
585fb111
JB		 349 u32 saveVGA0;
350 u32 saveVGA1;
351 u32 saveVGA_PD;
ba8bbcf6
JB		 352 u32 saveVGACNTRL;
353 u32 saveADPA;
354 u32 saveLVDS;
585fb111
JB		 355 u32 savePP_ON_DELAYS;
356 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 357 u32 saveDVOA;
358 u32 saveDVOB;
359 u32 saveDVOC;
360 u32 savePP_ON;
361 u32 savePP_OFF;
362 u32 savePP_CONTROL;
585fb111 363 u32 savePP_DIVISOR;
ba8bbcf6
JB		 364 u32 savePFIT_CONTROL;
365 u32 save_palette_a[256];
366 u32 save_palette_b[256];
06027f91 367 u32 saveDPFC_CB_BASE;
ba8bbcf6
JB		 368 u32 saveFBC_CFB_BASE;
369 u32 saveFBC_LL_BASE;
370 u32 saveFBC_CONTROL;
371 u32 saveFBC_CONTROL2;
0da3ea12
JB		 372 u32 saveIER;
373 u32 saveIIR;
374 u32 saveIMR;
42048781
ZW		 375 u32 saveDEIER;
376 u32 saveDEIMR;
377 u32 saveGTIER;
378 u32 saveGTIMR;
379 u32 saveFDI_RXA_IMR;
380 u32 saveFDI_RXB_IMR;
1f84e550 381 u32 saveCACHE_MODE_0;
e948e994 382 u32 saveD_STATE;
652c393a 383 u32 saveDSPCLK_GATE_D;
1f84e550 384 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 385 u32 saveSWF0[16];
386 u32 saveSWF1[16];
387 u32 saveSWF2[3];
388 u8 saveMSR;
389 u8 saveSR[8];
123f794f 390 u8 saveGR[25];
ba8bbcf6 391 u8 saveAR_INDEX;
a59e122a 392 u8 saveAR[21];
ba8bbcf6 393 u8 saveDACMASK;
a59e122a 394 u8 saveCR[37];
79f11c19 395 uint64_t saveFENCE[16];
1fd1c624
EA		 396 u32 saveCURACNTR;
397 u32 saveCURAPOS;
398 u32 saveCURABASE;
399 u32 saveCURBCNTR;
400 u32 saveCURBPOS;
401 u32 saveCURBBASE;
402 u32 saveCURSIZE;
a4fc5ed6
KP		 403 u32 saveDP_B;
404 u32 saveDP_C;
405 u32 saveDP_D;
406 u32 savePIPEA_GMCH_DATA_M;
407 u32 savePIPEB_GMCH_DATA_M;
408 u32 savePIPEA_GMCH_DATA_N;
409 u32 savePIPEB_GMCH_DATA_N;
410 u32 savePIPEA_DP_LINK_M;
411 u32 savePIPEB_DP_LINK_M;
412 u32 savePIPEA_DP_LINK_N;
413 u32 savePIPEB_DP_LINK_N;
42048781
ZW		 414 u32 saveFDI_RXA_CTL;
415 u32 saveFDI_TXA_CTL;
416 u32 saveFDI_RXB_CTL;
417 u32 saveFDI_TXB_CTL;
418 u32 savePFA_CTL_1;
419 u32 savePFB_CTL_1;
420 u32 savePFA_WIN_SZ;
421 u32 savePFB_WIN_SZ;
422 u32 savePFA_WIN_POS;
423 u32 savePFB_WIN_POS;
673a394b
EA		 424
425 struct {
426 struct drm_mm gtt_space;
427
0839ccb8 428 struct io_mapping *gtt_mapping;
ab657db1 429 int gtt_mtrr;
0839ccb8 430
31169714
CW		 431 /**
432 * Membership on list of all loaded devices, used to evict
433 * inactive buffers under memory pressure.
434 *
435 * Modifications should only be done whilst holding the
436 * shrink_list_lock spinlock.
437 */
438 struct list_head shrink_list;
439
673a394b
EA		 440 /**
441 * List of objects currently involved in rendering from the
442 * ringbuffer.
443 *
ce44b0ea
EA		 444 * Includes buffers having the contents of their GPU caches
445 * flushed, not necessarily primitives. last_rendering_seqno
446 * represents when the rendering involved will be completed.
447 *
673a394b
EA		 448 * A reference is held on the buffer while on this list.
449 */
5e118f41 450 spinlock_t active_list_lock;
673a394b
EA		 451 struct list_head active_list;
452
453 /**
454 * List of objects which are not in the ringbuffer but which
455 * still have a write_domain which needs to be flushed before
456 * unbinding.
457 *
ce44b0ea
EA		 458 * last_rendering_seqno is 0 while an object is in this list.
459 *
673a394b
EA		 460 * A reference is held on the buffer while on this list.
461 */
462 struct list_head flushing_list;
463
464 /**
465 * LRU list of objects which are not in the ringbuffer and
466 * are ready to unbind, but are still in the GTT.
467 *
ce44b0ea
EA		 468 * last_rendering_seqno is 0 while an object is in this list.
469 *
673a394b
EA		 470 * A reference is not held on the buffer while on this list,
471 * as merely being GTT-bound shouldn't prevent its being
472 * freed, and we'll pull it off the list in the free path.
473 */
474 struct list_head inactive_list;
475
a09ba7fa
EA		 476 /** LRU list of objects with fence regs on them. */
477 struct list_head fence_list;
478
673a394b
EA		 479 /**
480 * List of breadcrumbs associated with GPU requests currently
481 * outstanding.
482 */
483 struct list_head request_list;
484
485 /**
486 * We leave the user IRQ off as much as possible,
487 * but this means that requests will finish and never
488 * be retired once the system goes idle. Set a timer to
489 * fire periodically while the ring is running. When it
490 * fires, go retire requests.
491 */
492 struct delayed_work retire_work;
493
494 uint32_t next_gem_seqno;
495
496 /**
497 * Waiting sequence number, if any
498 */
499 uint32_t waiting_gem_seqno;
500
501 /**
502 * Last seq seen at irq time
503 */
504 uint32_t irq_gem_seqno;
505
506 /**
507 * Flag if the X Server, and thus DRM, is not currently in
508 * control of the device.
509 *
510 * This is set between LeaveVT and EnterVT. It needs to be
511 * replaced with a semaphore. It also needs to be
512 * transitioned away from for kernel modesetting.
513 */
514 int suspended;
515
516 /**
517 * Flag if the hardware appears to be wedged.
518 *
519 * This is set when attempts to idle the device timeout.
520 * It prevents command submission from occuring and makes
521 * every pending request fail
522 */
ba1234d1 523 atomic_t wedged;
673a394b
EA		 524
525 /** Bit 6 swizzling required for X tiling */
526 uint32_t bit_6_swizzle_x;
527 /** Bit 6 swizzling required for Y tiling */
528 uint32_t bit_6_swizzle_y;
71acb5eb
DA		 529
530 /* storage for physical objects */
531 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
673a394b 532 } mm;
9b9d172d 533 struct sdvo_device_mapping sdvo_mappings[2];
a3e17eb8
ZY		 534 /* indicate whether the LVDS_BORDER should be enabled or not */
535 unsigned int lvds_border_bits;
652c393a
JB		 536
537 /* Reclocking support */
538 bool render_reclock_avail;
539 bool lvds_downclock_avail;
540 struct work_struct idle_work;
541 struct timer_list idle_timer;
542 bool busy;
543 u16 orig_clock;
1da177e4
LT		 544} drm_i915_private_t;
545
673a394b
EA		 546/** driver private structure attached to each drm_gem_object */
547struct drm_i915_gem_object {
548 struct drm_gem_object *obj;
549
550 /** Current space allocated to this object in the GTT, if any. */
551 struct drm_mm_node *gtt_space;
552
553 /** This object's place on the active/flushing/inactive lists */
554 struct list_head list;
555
a09ba7fa
EA		 556 /** This object's place on the fenced object LRU */
557 struct list_head fence_list;
558
673a394b
EA		 559 /**
560 * This is set if the object is on the active or flushing lists
561 * (has pending rendering), and is not set if it's on inactive (ready
562 * to be unbound).
563 */
564 int active;
565
566 /**
567 * This is set if the object has been written to since last bound
568 * to the GTT
569 */
570 int dirty;
571
572 /** AGP memory structure for our GTT binding. */
573 DRM_AGP_MEM *agp_mem;
574
856fa198
EA		 575 struct page **pages;
576 int pages_refcount;
673a394b
EA		 577
578 /**
579 * Current offset of the object in GTT space.
580 *
581 * This is the same as gtt_space->start
582 */
583 uint32_t gtt_offset;
e67b8ce1 584
de151cf6
JB		 585 /**
586 * Fake offset for use by mmap(2)
587 */
588 uint64_t mmap_offset;
589
590 /**
591 * Fence register bits (if any) for this object. Will be set
592 * as needed when mapped into the GTT.
593 * Protected by dev->struct_mutex.
594 */
595 int fence_reg;
673a394b 596
673a394b
EA		 597 /** How many users have pinned this object in GTT space */
598 int pin_count;
599
600 /** Breadcrumb of last rendering to the buffer. */
601 uint32_t last_rendering_seqno;
602
603 /** Current tiling mode for the object. */
604 uint32_t tiling_mode;
de151cf6 605 uint32_t stride;
673a394b 606
280b713b
EA		 607 /** Record of address bit 17 of each page at last unbind. */
608 long *bit_17;
609
ba1eb1d8
KP		 610 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
611 uint32_t agp_type;
612
673a394b 613 /**
e47c68e9
EA		 614 * If present, while GEM_DOMAIN_CPU is in the read domain this array
615 * flags which individual pages are valid.
673a394b
EA		 616 */
617 uint8_t *page_cpu_valid;
79e53945
JB		 618
619 /** User space pin count and filp owning the pin */
620 uint32_t user_pin_count;
621 struct drm_file *pin_filp;
71acb5eb
DA		 622
623 /** for phy allocated objects */
624 struct drm_i915_gem_phys_object *phys_obj;
b70d11da
KH		 625
626 /**
627 * Used for checking the object doesn't appear more than once
628 * in an execbuffer object list.
629 */
630 int in_execbuffer;
3ef94daa
CW		 631
632 /**
633 * Advice: are the backing pages purgeable?
634 */
635 int madv;
673a394b
EA		 636};
637
638/**
639 * Request queue structure.
640 *
641 * The request queue allows us to note sequence numbers that have been emitted
642 * and may be associated with active buffers to be retired.
643 *
644 * By keeping this list, we can avoid having to do questionable
645 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
646 * an emission time with seqnos for tracking how far ahead of the GPU we are.
647 */
648struct drm_i915_gem_request {
649 /** GEM sequence number associated with this request. */
650 uint32_t seqno;
651
652 /** Time at which this request was emitted, in jiffies. */
653 unsigned long emitted_jiffies;
654
b962442e 655 /** global list entry for this request */
673a394b 656 struct list_head list;
b962442e
EA		 657
658 /** file_priv list entry for this request */
659 struct list_head client_list;
673a394b
EA		 660};
661
662struct drm_i915_file_private {
663 struct {
b962442e 664 struct list_head request_list;
673a394b
EA		 665 } mm;
666};
667
79e53945
JB		 668enum intel_chip_family {
669 CHIP_I8XX = 0x01,
670 CHIP_I9XX = 0x02,
671 CHIP_I915 = 0x04,
672 CHIP_I965 = 0x08,
673};
674
c153f45f 675extern struct drm_ioctl_desc i915_ioctls[];
b3a83639 676extern int i915_max_ioctl;
79e53945 677extern unsigned int i915_fbpercrtc;
652c393a 678extern unsigned int i915_powersave;
b3a83639 679
1341d655
BG		 680extern void i915_save_display(struct drm_device *dev);
681extern void i915_restore_display(struct drm_device *dev);
7c1c2871
DA		 682extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
683extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
684
1da177e4 685 /* i915_dma.c */
84b1fd10 686extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 687extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 688extern int i915_driver_unload(struct drm_device *);
673a394b 689extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
84b1fd10 690extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac
EA		 691extern void i915_driver_preclose(struct drm_device *dev,
692 struct drm_file *file_priv);
673a394b
EA		 693extern void i915_driver_postclose(struct drm_device *dev,
694 struct drm_file *file_priv);
84b1fd10 695extern int i915_driver_device_is_agp(struct drm_device * dev);
0d6aa60b
DA		 696extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
697 unsigned long arg);
673a394b 698extern int i915_emit_box(struct drm_device *dev,
201361a5 699 struct drm_clip_rect *boxes,
673a394b 700 int i, int DR1, int DR4);
11ed50ec 701extern int i965_reset(struct drm_device *dev, u8 flags);
af6061af 702
1da177e4 703/* i915_irq.c */
f65d9421 704void i915_hangcheck_elapsed(unsigned long data);
c153f45f
EA		 705extern int i915_irq_emit(struct drm_device *dev, void *data,
706 struct drm_file *file_priv);
707extern int i915_irq_wait(struct drm_device *dev, void *data,
708 struct drm_file *file_priv);
673a394b 709void i915_user_irq_get(struct drm_device *dev);
9d34e5db 710void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
673a394b 711void i915_user_irq_put(struct drm_device *dev);
79e53945 712extern void i915_enable_interrupt (struct drm_device *dev);
1da177e4
LT		 713
714extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 715extern void i915_driver_irq_preinstall(struct drm_device * dev);
0a3e67a4 716extern int i915_driver_irq_postinstall(struct drm_device *dev);
84b1fd10 717extern void i915_driver_irq_uninstall(struct drm_device * dev);
c153f45f
EA		 718extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
719 struct drm_file *file_priv);
720extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
721 struct drm_file *file_priv);
0a3e67a4
JB		 722extern int i915_enable_vblank(struct drm_device *dev, int crtc);
723extern void i915_disable_vblank(struct drm_device *dev, int crtc);
724extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
9880b7a5 725extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
c153f45f
EA		 726extern int i915_vblank_swap(struct drm_device *dev, void *data,
727 struct drm_file *file_priv);
8ee1c3db 728extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1da177e4 729
7c463586
KP		 730void
731i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
732
733void
734i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
735
736
1da177e4 737/* i915_mem.c */
c153f45f
EA		 738extern int i915_mem_alloc(struct drm_device *dev, void *data,
739 struct drm_file *file_priv);
740extern int i915_mem_free(struct drm_device *dev, void *data,
741 struct drm_file *file_priv);
742extern int i915_mem_init_heap(struct drm_device *dev, void *data,
743 struct drm_file *file_priv);
744extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
745 struct drm_file *file_priv);
1da177e4 746extern void i915_mem_takedown(struct mem_block **heap);
84b1fd10 747extern void i915_mem_release(struct drm_device * dev,
6c340eac 748 struct drm_file *file_priv, struct mem_block *heap);
673a394b
EA		 749/* i915_gem.c */
750int i915_gem_init_ioctl(struct drm_device *dev, void *data,
751 struct drm_file *file_priv);
752int i915_gem_create_ioctl(struct drm_device *dev, void *data,
753 struct drm_file *file_priv);
754int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
755 struct drm_file *file_priv);
756int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
757 struct drm_file *file_priv);
758int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
759 struct drm_file *file_priv);
de151cf6
JB		 760int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
761 struct drm_file *file_priv);
673a394b
EA		 762int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
763 struct drm_file *file_priv);
764int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
765 struct drm_file *file_priv);
766int i915_gem_execbuffer(struct drm_device *dev, void *data,
767 struct drm_file *file_priv);
768int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
769 struct drm_file *file_priv);
770int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
771 struct drm_file *file_priv);
772int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
773 struct drm_file *file_priv);
774int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
775 struct drm_file *file_priv);
3ef94daa
CW		 776int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
777 struct drm_file *file_priv);
673a394b
EA		 778int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
779 struct drm_file *file_priv);
780int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
781 struct drm_file *file_priv);
782int i915_gem_set_tiling(struct drm_device *dev, void *data,
783 struct drm_file *file_priv);
784int i915_gem_get_tiling(struct drm_device *dev, void *data,
785 struct drm_file *file_priv);
5a125c3c
EA		 786int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
787 struct drm_file *file_priv);
673a394b 788void i915_gem_load(struct drm_device *dev);
673a394b
EA		 789int i915_gem_init_object(struct drm_gem_object *obj);
790void i915_gem_free_object(struct drm_gem_object *obj);
791int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
792void i915_gem_object_unpin(struct drm_gem_object *obj);
0f973f27 793int i915_gem_object_unbind(struct drm_gem_object *obj);
d05ca301 794void i915_gem_release_mmap(struct drm_gem_object *obj);
673a394b
EA		 795void i915_gem_lastclose(struct drm_device *dev);
796uint32_t i915_get_gem_seqno(struct drm_device *dev);
22be1724 797bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
8c4b8c3f 798int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
52dc7d32 799int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
673a394b
EA		 800void i915_gem_retire_requests(struct drm_device *dev);
801void i915_gem_retire_work_handler(struct work_struct *work);
802void i915_gem_clflush_object(struct drm_gem_object *obj);
79e53945
JB		 803int i915_gem_object_set_domain(struct drm_gem_object *obj,
804 uint32_t read_domains,
805 uint32_t write_domain);
806int i915_gem_init_ringbuffer(struct drm_device *dev);
807void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
808int i915_gem_do_init(struct drm_device *dev, unsigned long start,
809 unsigned long end);
5669fcac 810int i915_gem_idle(struct drm_device *dev);
5a5a0c64
DV		 811uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
812 uint32_t flush_domains);
813int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
48764bf4 814int i915_lp_ring_sync(struct drm_device *dev);
de151cf6 815int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
79e53945
JB		 816int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
817 int write);
71acb5eb
DA		 818int i915_gem_attach_phys_object(struct drm_device *dev,
819 struct drm_gem_object *obj, int id);
820void i915_gem_detach_phys_object(struct drm_device *dev,
821 struct drm_gem_object *obj);
822void i915_gem_free_all_phys_object(struct drm_device *dev);
6911a9b8
BG		 823int i915_gem_object_get_pages(struct drm_gem_object *obj);
824void i915_gem_object_put_pages(struct drm_gem_object *obj);
1fd1c624 825void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
673a394b 826
31169714
CW		 827void i915_gem_shrinker_init(void);
828void i915_gem_shrinker_exit(void);
829
673a394b
EA		 830/* i915_gem_tiling.c */
831void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
280b713b
EA		 832void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
833void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
673a394b
EA		 834
835/* i915_gem_debug.c */
836void i915_gem_dump_object(struct drm_gem_object *obj, int len,
837 const char *where, uint32_t mark);
838#if WATCH_INACTIVE
839void i915_verify_inactive(struct drm_device *dev, char *file, int line);
840#else
841#define i915_verify_inactive(dev, file, line)
842#endif
843void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
844void i915_gem_dump_object(struct drm_gem_object *obj, int len,
845 const char *where, uint32_t mark);
846void i915_dump_lru(struct drm_device *dev, const char *where);
1da177e4 847
2017263e 848/* i915_debugfs.c */
27c202ad
BG		 849int i915_debugfs_init(struct drm_minor *minor);
850void i915_debugfs_cleanup(struct drm_minor *minor);
2017263e 851
317c35d1
JB		 852/* i915_suspend.c */
853extern int i915_save_state(struct drm_device *dev);
854extern int i915_restore_state(struct drm_device *dev);
0a3e67a4
JB		 855
856/* i915_suspend.c */
857extern int i915_save_state(struct drm_device *dev);
858extern int i915_restore_state(struct drm_device *dev);
317c35d1 859
65e082c9 860#ifdef CONFIG_ACPI
8ee1c3db 861/* i915_opregion.c */
74a365b3 862extern int intel_opregion_init(struct drm_device *dev, int resume);
3b1c1c11 863extern void intel_opregion_free(struct drm_device *dev, int suspend);
8ee1c3db
MG		 864extern void opregion_asle_intr(struct drm_device *dev);
865extern void opregion_enable_asle(struct drm_device *dev);
65e082c9 866#else
03ae61dd 867static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
3b1c1c11 868static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
65e082c9
LB		 869static inline void opregion_asle_intr(struct drm_device *dev) { return; }
870static inline void opregion_enable_asle(struct drm_device *dev) { return; }
871#endif
8ee1c3db 872
79e53945
JB		 873/* modesetting */
874extern void intel_modeset_init(struct drm_device *dev);
875extern void intel_modeset_cleanup(struct drm_device *dev);
28d52043 876extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
80824003 877extern void i8xx_disable_fbc(struct drm_device *dev);
74dff282 878extern void g4x_disable_fbc(struct drm_device *dev);
79e53945 879
546b0974
EA		 880/**
881 * Lock test for when it's just for synchronization of ring access.
882 *
883 * In that case, we don't need to do it when GEM is initialized as nobody else
884 * has access to the ring.
885 */
886#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
887 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
888 LOCK_TEST_WITH_RETURN(dev, file_priv); \
889} while (0)
890
3043c60c
EA		 891#define I915_READ(reg) readl(dev_priv->regs + (reg))
892#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
893#define I915_READ16(reg) readw(dev_priv->regs + (reg))
894#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
895#define I915_READ8(reg) readb(dev_priv->regs + (reg))
896#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
de151cf6 897#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
049ef7e4 898#define I915_READ64(reg) readq(dev_priv->regs + (reg))
7d57382e 899#define POSTING_READ(reg) (void)I915_READ(reg)
1da177e4
LT		 900
901#define I915_VERBOSE 0
902
0ef82af7
CW		 903#define RING_LOCALS volatile unsigned int *ring_virt__;
904
905#define BEGIN_LP_RING(n) do { \
906 int bytes__ = 4*(n); \
907 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
908 /* a wrap must occur between instructions so pad beforehand */ \
909 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
910 i915_wrap_ring(dev); \
911 if (unlikely (dev_priv->ring.space < bytes__)) \
912 i915_wait_ring(dev, bytes__, __func__); \
913 ring_virt__ = (unsigned int *) \
914 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
915 dev_priv->ring.tail += bytes__; \
916 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
917 dev_priv->ring.space -= bytes__; \
1da177e4
LT		 918} while (0)
919
0ef82af7 920#define OUT_RING(n) do { \
1da177e4 921 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
0ef82af7 922 *ring_virt__++ = (n); \
1da177e4
LT		 923} while (0)
924
925#define ADVANCE_LP_RING() do { \
0ef82af7
CW		 926 if (I915_VERBOSE) \
927 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
928 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1da177e4
LT		 929} while(0)
930
ba8bbcf6 931/**
585fb111
JB		 932 * Reads a dword out of the status page, which is written to from the command
933 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
934 * MI_STORE_DATA_IMM.
ba8bbcf6 935 *
585fb111 936 * The following dwords have a reserved meaning:
0cdad7e8
KP		 937 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
938 * 0x04: ring 0 head pointer
939 * 0x05: ring 1 head pointer (915-class)
940 * 0x06: ring 2 head pointer (915-class)
941 * 0x10-0x1b: Context status DWords (GM45)
942 * 0x1f: Last written status offset. (GM45)
ba8bbcf6 943 *
0cdad7e8 944 * The area from dword 0x20 to 0x3ff is available for driver usage.
ba8bbcf6 945 */
585fb111 946#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
0baf823a 947#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
0cdad7e8 948#define I915_GEM_HWS_INDEX 0x20
0baf823a 949#define I915_BREADCRUMB_INDEX 0x21
ba8bbcf6 950
0ef82af7 951extern int i915_wrap_ring(struct drm_device * dev);
585fb111 952extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
ba8bbcf6
JB		 953
954#define IS_I830(dev) ((dev)->pci_device == 0x3577)
955#define IS_845G(dev) ((dev)->pci_device == 0x2562)
956#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
ba8bbcf6
JB		 957#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
958
4d1f7888 959#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
ba8bbcf6
JB		 960#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
961#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
3bf48468
JB		 962#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
963 (dev)->pci_device == 0x27AE)
ba8bbcf6
JB		 964#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
965 (dev)->pci_device == 0x2982 || \
966 (dev)->pci_device == 0x2992 || \
967 (dev)->pci_device == 0x29A2 || \
968 (dev)->pci_device == 0x2A02 || \
5f5f9d4c 969 (dev)->pci_device == 0x2A12 || \
d3adbc0c
ZW		 970 (dev)->pci_device == 0x2A42 || \
971 (dev)->pci_device == 0x2E02 || \
972 (dev)->pci_device == 0x2E12 || \
72021788 973 (dev)->pci_device == 0x2E22 || \
280da227 974 (dev)->pci_device == 0x2E32 || \
7839c5d5 975 (dev)->pci_device == 0x2E42 || \
280da227
ZW		 976 (dev)->pci_device == 0x0042 || \
977 (dev)->pci_device == 0x0046)
ba8bbcf6 978
c9ed4486
ML		 979#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
980 (dev)->pci_device == 0x2A12)
ba8bbcf6 981
b9bfdfe6 982#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
5f5f9d4c 983
d3adbc0c
ZW		 984#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
985 (dev)->pci_device == 0x2E12 || \
60fd99e3 986 (dev)->pci_device == 0x2E22 || \
72021788 987 (dev)->pci_device == 0x2E32 || \
7839c5d5 988 (dev)->pci_device == 0x2E42 || \
60fd99e3 989 IS_GM45(dev))
d3adbc0c 990
2177832f
SL		 991#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
992#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
993#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
994
ba8bbcf6
JB		 995#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
996 (dev)->pci_device == 0x29B2 || \
2177832f
SL		 997 (dev)->pci_device == 0x29D2 || \
998 (IS_IGD(dev)))
ba8bbcf6 999
280da227
ZW		 1000#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
1001#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
1002#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
1003
ba8bbcf6 1004#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
280da227
ZW		 1005 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
1006 IS_IGDNG(dev))
ba8bbcf6
JB		 1007
1008#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
2177832f 1009 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
280da227 1010 IS_IGD(dev) || IS_IGDNG_M(dev))
ba8bbcf6 1011
280da227
ZW		 1012#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
1013 IS_IGDNG(dev))
0f973f27
JB		 1014/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1015 * rows, which changed the alignment requirements and fence programming.
1016 */
1017#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1018 IS_I915GM(dev)))
280da227 1019#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
a4fc5ed6 1020#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
32f9d658 1021#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
af729a26 1022#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
7662c8bd 1023/* dsparb controlled by hw only */
22bd50c5 1024#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
b39d50e5 1025
652c393a
JB		 1026#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
1027#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
c03342fa
ZW		 1028#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
1029 (IS_I9XX(dev) || IS_GM45(dev)) && \
1030 !IS_IGD(dev) && \
1031 !IS_IGDNG(dev))
97f5ab66 1032#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IGDNG_M(dev))
652c393a 1033
ba8bbcf6 1034#define PRIMARY_RINGBUFFER_SIZE (128*1024)
0d6aa60b 1035
1da177e4 1036#endif
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